JP7289973B2 - voltage regulator - Google Patents

Description

The present invention relates to voltage regulators.

Generally, a voltage regulator receives an input voltage (power supply voltage) VIN and generates a constant output voltage VOUT at an output terminal. At this time, the voltage regulator supplies a current according to the fluctuation of the load, and always keeps the output voltage VOUT constant.
Normally, voltage regulators are equipped with a phase compensation circuit that improves responsiveness by adjusting the frequency of the zero point that is formed, and stabilizes operation without causing malfunctions such as oscillation even with a small output capacitance. there is

If the phase compensation circuit is not formed in accordance with the design, the above-described effect of stable operation cannot be obtained, so it is necessary to test the phase compensation circuit during the manufacturing process.
However, voltage regulators are tested during the manufacturing process to check whether the capacitors in the phase compensation circuit inside the circuit are formed without problems. It is difficult to test by directly observing the presence or absence.

For example, if a test pad terminal is provided for testing each element of the phase compensation circuit, the test pad increases the chip area, and the parasitic capacitance component of the test pad reduces the phase compensation capacitance in the phase compensation circuit. There is a problem that the capacitance value of the (capacitor) changes and the performance of the phase compensation circuit is impaired.
Therefore, there is a test method for indirectly determining whether or not the connection failure of the phase compensation capacitor in the phase compensation circuit and whether or not the capacitance value of the phase compensation capacitor is within the design specification range. In this test method, the connection failure and the capacitance value of the phase compensation capacitor are determined by measuring the discharge time or discharge current of the charge accumulated in the phase compensation capacitor (see, for example, Patent Document 1).

FIG. 5 shows a circuit diagram of the voltage regulator of Patent Document 1. As shown in FIG. The phase compensation circuit 110 includes a phase compensation capacitor 111 and a resistor 112, respectively.
This voltage regulator is also provided with a test circuit 120 for testing the phase compensation capacitor 111 in the phase compensation circuit 110 . The test circuit 120 includes a p-channel MOS transistor 121 and an n-channel MOS transistor 122 and a constant current source 123 .

When testing the phase compensation capacitor 111, as a first step, the p-channel MOS transistor 121 is turned on and the n-channel MOS transistor 122 is kept off so that the phase compensation capacitor 111 is sufficiently charged.
Then, as a second step, the p-channel MOS transistor 121 and the n-channel MOS transistor 122 are turned off, and the consumption current ICS1 of the voltage regulator is measured.

In the third step, the p-channel MOS transistor 121 is kept off, each of the n-channel MOS transistors 122 is turned on, and the charge accumulated in the phase compensation capacitor 111 is discharged through the constant current source 123 .
At this time, the consumption current ICS2 of the voltage regulator is larger than the consumption current ICS1 because the discharge current for discharging the charge of the phase compensation capacitor 111 is added to the consumption current ICS1. Then, after starting the discharge of the phase compensation capacitor 111, the consumption current ICS2 is measured, and the time T until the consumption current ICS2 becomes equal to the consumption current ICS1 is measured to determine whether the connection failure of the phase compensation capacitor 111 is detected. can be determined and the capacitance value can be estimated.

JP 2017-174116 A

However, in the test method according to Patent Document 1, when the capacitance value of the phase compensation capacitor 111 is very small, the charge accumulated in the phase compensation capacitor 111 is small, and the current value of the discharge current that flows when the charge is discharged is also very small. Become.
Also, even if the capacitance value of the phase compensation capacitor 111 is not very small, the discharge current of the phase compensation capacitor 111 is relatively small when the current consumption in other circuits of the voltage regulator is very large.

If the discharge current described above is very small compared to the consumption current ICS1, it will be included in the error range in the measurement of the voltage regulator consumption current.
As a result, the difference between the consumption currents ICS1 and ICS2 cannot be sufficiently detected, that is, the discharge current cannot be detected, and there is a possibility that the above-described time T cannot be measured accurately or not at all.

The present invention has been made in view of such circumstances. An object of the present invention is to provide a voltage regulator capable of estimating a value.

A voltage regulator according to the present invention includes: an output voltage terminal connected to an output transistor for outputting a predetermined output voltage; a voltage adjustment terminal for detecting the output voltage; an error amplifier for controlling the output voltage by comparing each reference voltage and controlling the control terminal of the output transistor; and a phase compensation capacitor for adjusting the phase in the control loop of the output voltage using the error amplifier. and a switch for enabling or disabling the phase compensation capacitor, and a test signal input from the voltage adjustment terminal, and the output when the phase compensation capacitor is enabled or disabled. a test circuit for controlling whether the switch is enabled or disabled in a test mode for testing the phase compensation capacitor by measuring a change in voltage phase.

According to the present invention, poor connection and estimation of the capacitance value can be performed even for a phase compensation capacitor with a capacitance value that is a very small discharge current compared to the steady-state consumption current of the voltage regulator.

1 is a circuit diagram showing a configuration example of a voltage regulator according to an embodiment of the invention; FIG. FIG. 10 is a diagram showing waveforms showing the correspondence between a test pulse and the phase of the change in the output voltage VOUT corresponding to the test pulse when testing the phase compensation capacitor C1; 2 is a circuit diagram showing a modification of phase compensation circuit 13 in voltage regulator 1 of FIG. 1. FIG. FIG. 10 is a circuit diagram showing a modification of the output stage in which one amplifier circuit is added to the preceding stage of the output transistor 14; 1 is a circuit diagram of a voltage regulator disclosed in Patent Document 1; FIG.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration example of a voltage regulator according to one embodiment of the present invention.
In FIG. 1, the voltage regulator 1 includes a reference power supply 11, an error amplifier 12, a phase compensation circuit 13, an output transistor 14, a feedback phase compensation circuit 15, resistors 16 and 17, a variable constant current source 18, a test circuit 19 and a state limiting circuit. 20 each.
The phase compensation circuit 13 also includes a resistor R1, a switch SW1, and a phase compensation capacitor C1. The feedback phase compensation circuit 15 includes a switch SW2 and a phase compensation capacitor C2.

The reference power supply 11 generates a reference voltage Vref and outputs this reference voltage Vref to the inverting input terminal (-) of the error amplifier 12 .
The error amplifier 12 amplifies the difference voltage between the feedback voltage Vfb supplied to the non-inverting input terminal (+) from the connection point P2 and the reference voltage Vref supplied to the inverting input terminal (-), and outputs the voltage from the output terminal. Outputs the amplified voltage Vcmp.

The resistor R1 has one end connected to the output terminal of the error amplifier 12 and the connection point P1, and the other end connected to one end of the switch SW1.
The switch SW1 is a two-terminal switch, the other end of which is connected to one end of the phase compensation capacitor C1.
The phase compensation capacitor C1 is a capacitor for performing phase compensation for delaying the phase of the signal waveform output from the output terminal of the error amplifier 12, and the other end thereof is connected to the output voltage terminal TVOUT.
In this embodiment, the connection point P1, the resistor R1, the switch SW1, and the phase compensation capacitor C1 are connected in this order. good.

The output transistor 14 is a p-channel MOS transistor having a source connected to the wiring of the input voltage (power supply voltage) VIN, a gate connected to the connection point P1, and a drain connected to the output voltage terminal TVOUT.

The switch SW2 is a two-terminal switch, one end of which is connected to the voltage adjustment terminal TVADJ, and the other end of which is connected to one end of the phase compensation capacitor C2.
The phase compensation capacitor C2 is a capacitor for performing phase compensation to advance the phase of the waveform of the feedback voltage Vfb obtained by dividing the adjustment voltage VADJ supplied from the voltage adjustment terminal TVADJ by the resistors 16 and 17, and the other end is a connection point P2. It is connected to the.
In this embodiment, the voltage adjustment terminal TVADJ, the switch SW2, and the phase compensation capacitor C2 are connected in this order, but the order may be changed in any order as long as they are connected in series.

The resistor 16 has one end connected to the voltage adjustment terminal TVADJ and the other end connected to the connection point P2.
The resistor 17 has one end connected to the connection point P2 and the other end connected to the wiring of the input voltage (ground voltage) VSS.
Here, each of the resistors 16 and 17 constitutes a voltage dividing circuit, which divides the adjustment voltage VADJ input from the voltage adjustment terminal TVADJ by a resistance ratio, and the divided voltage is sent from the connection point P2 to the feedback voltage. Output as Vfb.

The variable constant current source 18 is a current source that adjusts the bias current I1 used to drive the error amplifier 12, and is interposed between the negative side power supply terminal of the error amplifier 12 and the wiring of the input voltage VSS.
Alternatively, the variable constant current source 18 may be inserted between the wiring of the input voltage VIN and the positive power supply terminal of the error amplifier 12 .

The test circuit 19 performs on/off control of the switches SW1 and SW2 and control of the bias current I1 of the variable constant current source 18 in a test mode for testing the phase compensation capacitors C1 and C2.
Here, the test circuit 19 is supplied with test signals SG1, SG2 and SG3, for example, as test signals. When the test signal SG1 is at L level, the normal mode is set. On the other hand, when the test signal SG1 is at H level, the test mode is set.

When the test signal SG1 is at L level, the test circuit 19 outputs a control signal SIB (for example, at L level) that instructs the variable constant current source 18 to flow the bias current I1 in the normal mode.
On the other hand, when the test signal SG1 is at H level, the test circuit 19 outputs a control signal SIB (eg, H level) to the variable constant current source 18 to instruct the variable constant current source 18 to flow a bias current I1 of a smaller current amount than in the normal mode. level).
When the test signal SG1 is at L level, the test circuit 19 outputs control signals S1A and S2A (for example, H level) that turn on the switches SW1 and SW2.

Further, each of the test signals SG2 and SG3 is a signal whose input is valid in the test mode in which the test signal SG1 is at H level.
When the test signal SG2 is at L level, the test circuit 19 outputs a control signal S1A (for example, L level) instructing to turn off the switch SW1 to turn off the switch SW1.
On the other hand, when the test signal SG2 is at H level, the control signal S1A (for example, H level) instructing to turn on is output to the switch SW1 to turn on the switch SW1.

Similarly, when the test signal SG3 is at L level, the test circuit 19 outputs a control signal S2A (for example, L level) instructing to turn off the switch SW2 to turn off the switch SW2. and
On the other hand, when the test signal SG3 is at H level, the control signal S2A (for example, H level) instructing to turn on is output to the switch SW2 to turn on the switch SW2.

The normal mode in voltage regulator 1 will be described below.
In the normal mode, the output voltage terminal TVOUT and the voltage adjustment terminal TVADJ are connected, and the switches SW1 and SW2 are on. The voltage regulator 1 operates to output a predetermined output voltage from an output voltage terminal TVOUT. As a result, the output voltage VOUT is divided by the resistance ratio of the resistors R16 and R17 and supplied from the connection point P1 to the positive input terminal (+) of the error amplifier 12 as the feedback voltage Vfb.
The error amplifier 12 compares the feedback voltage Vfb and the reference voltage Vref, and outputs an amplified voltage Vcmp corresponding to the difference between the feedback voltage Vfb and the reference voltage Vref.

In the phase compensation at this time, since the switch SW1 is on, the output voltage VOUT output to the output voltage terminal TVOUT is supplied to the phase compensation capacitor C1.
Then, the waveform of the output voltage VOUT is differentiated by the phase compensation capacitor C1, and a differentiated waveform signal generated by this differentiation is supplied to the connection point P1 via the switch SW1 and the resistor R1.
Since the phase of the differentiated waveform signal is inverted with respect to the voltage waveform of the amplified voltage Vcmp, the voltage change due to the amplified voltage Vcmp at the connection point P1 is hindered, and the amplified voltage Vcmp supplied to the gate of the output transistor 14 is prevented. delay the phase of

In phase compensation, since the switch SW2 is in the ON state, the output voltage VOUT is supplied from the output voltage terminal TVOUT to the voltage adjustment terminal TVADJ.
Then, the waveform of the output voltage VOUT is differentiated by the phase compensation capacitor C2, and a differentiated waveform signal generated by this differentiation is supplied to the connection point P2 via the switch SW2.
At this connection point P2, the resistance ratio of the resistors 16 and 17 produces a feedback voltage Vfb. Since the phase of the differentiated waveform signal is the same as that of the voltage waveform of the feedback voltage Vfb, the voltage change due to the feedback voltage Vfb at the connection point P2 is accelerated. advances the phase of the applied feedback voltage Vfb.

Next, a test mode for phase compensation capacitance in voltage regulator 1 will be described. At this time, the output voltage terminal TVOUT and the voltage adjustment terminal TVADJ are not connected. A test of the phase compensation capacitance is one of quality determination tests performed in the manufacturing process of the voltage regulator 1 .
The phase compensation capacitors C1 and C2 are tested independently because it is necessary to individually determine whether or not each of the phase compensation capacitors C1 and C2 is connected and determine the capacitance value.
For the sake of convenience, the test mode will be described below in the order in which the phase compensation capacitor C1 is tested and then the phase compensation capacitor C2 is tested, but either one may be tested first.

When testing phase compensation capacitor C1, test signal SG1 is fixed at H level and test signal SG3 is fixed at L level. That is, when testing the phase compensation capacitor C1, by setting the test signal SG3 to the L level, the test circuit 19 sets the control signal S2A to the L level to turn off the switch SW2, thereby setting the phase compensation capacitor C2 to the phase compensation state. Disabled in action.

Further, by setting the test signal SG2 to L level, the test circuit 19 sets the control signal S1A to L level to turn off the switch SW1 and disable the phase compensation capacitor C1 in the phase compensation operation.
In this state, a test pulse is supplied to the voltage adjustment terminal TVADJ. This test pulse is a pulse that changes at a voltage level that intersects the reference voltage Vref when the voltage is divided by the resistors 16 and 17 to form the feedback voltage Vfb.
Then, the phase of the test pulse and the phase of the output voltage VOUT that changes corresponding to the test pulse are measured, and the phase difference Pdiff1A between the phase of the test pulse and the output voltage VOUT is obtained.

Next, by setting the test signal SG2 to H level, the test circuit 19 sets the control signal S1A to H level, turns on the switch SW1, and enables the phase compensation capacitor C1 in the phase compensation operation.
In this state, the same test pulse as in the case where the phase compensation capacitor C1 is disabled in the phase compensation operation is supplied to the voltage adjustment terminal TVADJ.
Then, the phase of the test pulse and the phase of the output voltage VOUT that changes corresponding to the test pulse are measured, and the phase difference Pdiff2A between the phase of the test pulse and the output voltage VOUT is obtained.

Depending on the phase difference when the phase compensation capacitor C1 is enabled/disabled for phase compensation, that is, the magnitude of the difference between the phase differences Pdiff2A and Pdiff1A, the presence or absence of connection in the manufacturing process of the phase compensation capacitor C1, or Capacitance values can be estimated.
Also, the variable constant current source 18 reduces the bias current in the test mode compared to the normal mode. As a result, the current output from the error amplifier 12 is reduced, and the slope of the voltage change of the amplified voltage Vcmp becomes gentler than in the normal mode. Compared to the case of the bias current I1 in the normal mode, the magnitude (absolute value) of the difference between the phase differences Pdiff2A and Pdiff1A can be expanded. Estimation can be easily performed with high accuracy.

Next, when testing phase compensation capacitor C2, test signal SG1 is fixed at H level and test signal SG2 is fixed at L level. That is, when testing the phase compensation capacitor C2, by setting the test signal SG2 to the L level, the test circuit 19 sets the control signal S1A to the L level to turn off the switch SW1 and the phase compensation capacitor C1 to the phase compensation capacitor. Disabled in action.

Further, by setting the test signal SG3 to L level, the test circuit 19 sets the control signal S2A to L level to turn off the switch SW2 and disable the phase compensation capacitor C2 in the phase compensation operation.
In this state, a test pulse similar to that for testing the phase compensation capacitor C1 is supplied to the voltage adjustment terminal TVADJ.
Then, the phase of the test pulse and the phase of the output voltage VOUT that changes corresponding to the test pulse are measured, and the phase difference Pdiff1B between the phase of the test pulse and the output voltage VOUT is obtained.

Next, by setting the test signal SG3 to H level, the test circuit 19 sets the control signal S2A to H level, turns on the switch SW2, and enables the phase compensation capacitor C2 in the phase compensation operation.
In this state, a test pulse is supplied to the voltage adjustment terminal TVADJ in the same manner as when the phase compensation capacitor C2 is disabled in the phase compensation operation.
Then, the phase of the test pulse and the phase of the output voltage VOUT that changes corresponding to the test pulse are measured, and the phase difference Pdiff2B between the phase of the test pulse and the output voltage VOUT is obtained.

Depending on the phase difference when the phase compensation capacitor C1 is enabled/disabled for phase compensation, that is, the magnitude of the difference between the phase differences Pdiff2B and Pdiff1B, the presence or absence of connection in the manufacturing process of the phase compensation capacitor C1, or Capacitance values can be estimated.
Also, the variable constant current source 18 reduces the bias current in the test mode compared to the normal mode. As a result, the current output from the error amplifier 12 is reduced, and the slope of the voltage change of the amplified voltage Vcmp becomes gentler than in the normal mode. As a result, the magnitude (absolute value) of the difference between the phase differences Pdiff2B and Pdiff1B can be increased compared to the bias current I1 in the normal mode. Capacitance values can be easily estimated with high accuracy.

Further, in the above-described embodiment, the variable constant current source 18 is provided in order to easily and accurately estimate the presence or absence of connection of the phase compensation capacitors C1 and C2 in the manufacturing process or the capacitance value.
However, when the estimation of the capacitance values of the phase compensation capacitors C1 and C2 does not require accuracy, or when only the presence or absence of connection is tested in the manufacturing process, the operating current of the error amplifier 12 is used instead of the variable constant current source 18. It may be a constant current source that only supplies current.

Further, in the above-described embodiment, the voltage regulator 1 has been described as having the phase compensation capacitors C1 and C2. may be configured.
In this configuration, the test signals in the test circuit 19 are the test signals SG1 and SG2, and the operation of the test signal SG1 is the same as described in the above embodiment.

Here, when only the phase compensation capacitor C1 is provided, the test circuit 19 supplies the control signal S1A at L level to the switch SW1 to turn off the switch SW1 when the test signal SG1 at H level is supplied. and
On the other hand, when the test signal SG2 of H level is supplied, the test circuit 19 supplies the control signal S1A of H level to the switch SW1 to turn on the switch SW1.
The determination of the connection of the phase compensation capacitor C1 and the estimation of the capacitance value based on the difference between the phase differences Pdiff2A and Pdiff1A are the same as those described above.

When only the phase compensation capacitor C2 is provided, the test circuit 19 supplies the test signal SG2 at L level to the switch SW2 to turn off the switch SW2 when the test signal SG1 at H level is supplied. do.
On the other hand, when the test signal SG2 of H level is supplied, the test circuit 19 supplies the control signal S2A of H level to the switch SW2 to turn on the switch SW2.
The determination of the connection of the phase compensation capacitor C2 and the estimation of the capacitance value based on the difference between the phase differences Pdiff2B and Pdiff1B are the same as those described above.

Further, in the above-described embodiment, the state limiting circuit 20 is provided for fixing the operation of the test circuit 19 to the normal mode without shifting to the test mode. The state limiting circuit 20 is provided with a storage element such as a memory inside, for example, the test circuit 19 is fixed to the normal mode at the time of shipment, etc., and what kind of test signals (SG1, SG2 and SG3) are input. Even in such cases, the operation is limited to the normal mode.
However, if the test terminal TTEST does not appear as a terminal of the package at the time of shipment, the state limiting circuit 20 may not be provided.

FIG. 2 is a diagram showing waveforms showing correspondences between test pulses and the phases of changes in the output voltage VOUT corresponding to the test pulses when the phase compensation capacitor C1 is tested.
Here, FIG. 2(a) shows the waveform of the test pulse input to the voltage adjusting terminal TVADJ, where the vertical axis indicates voltage and the horizontal axis indicates time.
FIG. 2(b) shows the changing waveform of the feedback voltage Vfb obtained by dividing the test pulse voltage by the resistors 16 and 17, which is supplied to the positive input terminal (+) of the error amplifier 12. , the vertical axis indicates voltage and the horizontal axis indicates time.
FIG. 2(c) shows the changing waveform of the amplified voltage Vcmp at the connection point P1, where the vertical axis indicates voltage and the horizontal axis indicates time.
FIG. 2(d) shows a changing waveform of the output voltage VOUT output from the output voltage terminal TVOUT, where the vertical axis indicates voltage and the horizontal axis indicates time.

As described above, when testing the phase compensation capacitor C1, a test pulse is supplied to the voltage adjustment terminal TVADJ for each state in which the phase compensation capacitor C1 is enabled and disabled for phase compensation. Then, the phase of the supplied test pulse is compared with the phase of change in the output voltage VOUT corresponding to this test pulse.
In each of FIGS. 2(c) and 2(d), the changing waveform of the amplified voltage Vcmp and the changing waveform of the output voltage VOUT indicated by the solid lines correspond to when the test signal SG1 supplied to the test circuit 19 is L. Level, that is, the case in normal mode (each of phase compensation capacitors C1 and C2 is effective for phase compensation).

Also, in each of FIGS. 2(c) and 2(d), the changing waveform of the amplified voltage Vcmp and the changing waveform of the output voltage VOUT indicated by the dashed line are the test signals supplied to the test circuit 19. SG1 is at H level and test signals SG2 and SG3 are at L level, that is, the switches SW1 and SW2 are in the OFF state in the test mode (the phase compensation capacitors C1 and C2 are invalid for phase compensation). ).

Also, in each of FIGS. 2(c) and 2(d), the change waveform of the amplified voltage Vcmp and the change waveform of the output voltage VOUT indicated by two-dot chain lines are supplied to the test circuit 19. The signal SG1 is at H level, the test signal SG2 is at H level, and the test signal SG3 is at L level. valid for phase compensation, phase compensation capacitor C2 is invalid for phase compensation).

Time t1: As shown in FIG. 2(a), the test pulse supplied from the external device rises to the voltage adjustment terminal TVADJ (transition from L level to H level). Here, the feedback voltage Vfb in FIG. 2(b) changes from a voltage less than the reference voltage Vref to a voltage exceeding the reference voltage Vref. Further, as shown in FIG. 2(c), since the bias current is reduced with respect to the speed of voltage increase of the amplified voltage Vcmp indicated by the solid line in the normal mode, the amplified voltage indicated by the one-dot chain line and the two-dot chain line in the test mode The rate of voltage rise of Vcmp slows down.

Time t2: As shown in FIG. 2(d), the voltage waveform of the solid line output voltage VOUT changes from H level to L level in response to the rise of the test pulse. The phase difference Pdiff1 between the test pulse and the voltage waveform of the output voltage VOUT at this time is time tf1.
Time t3: As shown in FIG. 2(d), the voltage waveform of the output voltage VOUT indicated by the one-dot chain line changes from H level to L level in response to the rise of the test pulse. The phase difference Pdiff1A between the test pulse and the voltage waveform of the output voltage VOUT at this time is time tf2.
Time t4: As shown in FIG. 2(d), the voltage waveform of the output voltage VOUT indicated by the two-dot chain line changes from H level to L level in response to the rise of the test pulse. The phase difference Pdiff2A between the test pulse and the voltage waveform of the output voltage VOUT at this time is time tf3.

Based on the difference between the phase difference Pdiff2A and the phase difference Pdiff1A shown in FIG. 2(d), that is, the magnitude of the difference between the times tf3 and tf2, connection determination and capacitance value estimation of the phase compensation capacitor C1 are performed. Here, the determination of the connection and the estimation of the capacitance value based on the difference between the time tf3 and the time tf2 are carried out by performing an actual test, and statistically calculating the difference between the time tf3 and the time tf2 of the voltage regulator 1 that normally operates in the normal mode. This is done based on the tolerances set by the process.
Further, each of times t5, t6, t7 and t8 is the same as each of times t1, t2, t3 and t4 described above.

FIG. 3 is a circuit diagram showing a modification of phase compensation circuit 13 in voltage regulator 1 of FIG. 3, an amplifier A1 having a predetermined gain is provided in place of the resistor R1 in the phase compensation circuit 13 of FIG. Each of the phase compensation capacitor C1 and the switch SW1 has the same configuration as the phase compensation circuit 13 of FIG.
As long as the amplifier A1 is arranged after the phase compensation capacitor C1 in the signal propagation direction from the output voltage terminal TVOUT to the connection point P1, the switch SW1 may be arranged at any position in the series connection.

In the operation of the phase compensation circuit of FIG. 3, when the switch SW1 is in the ON state (the phase compensation capacitor C1 is effective for phase compensation), the voltage waveform of the output voltage VOUT output by the output transistor 14 is changed via the switch SW1. When supplied to the phase compensation capacitor C1, a differential waveform of the voltage waveform of the output voltage VOUT is supplied to the amplifier A1. Amplifier A1 amplifies the differentiated waveform with a predetermined gain and outputs it to connection point P1. As a result, a differentiated waveform whose phase is opposite to the change in the amplified voltage Vcmp output from the error amplifier 12 is supplied to the connection point P1, and phase compensation is performed to suppress the change in the amplified voltage Vcmp.

FIG. 4 is a circuit diagram showing a modified example of the output stage in which one amplifier circuit is added to the front stage of the output transistor 14. In FIG. In FIG. 4, a transistor 21, which is a p-channel MOS transistor, and a constant current source 22 for passing a bias current I2 are provided as an amplifier circuit.
The transistor 21 has a source connected to the wiring of the input voltage VIN, a gate connected to the connection point P1, and a drain connected to the connection point P3 (the gate of the output transistor 14).
The constant current source 22 has one end connected to the drain of the transistor 21 and the other end connected to the wiring of the power supply VSS.
Each of the transistor 21 and the constant current source 22 constitutes an amplifier circuit that further amplifies the amplified voltage Vcmp output from the error amplifier 12 .

4, the phase of the output voltage VOUT and the voltage waveform of the amplified voltage Vcmp are in phase, so the operation of the error amplifier 12 must correspond to the phase of the output voltage Vout. Therefore, in the error amplifier 12, the reference voltage Vref is supplied to the positive input terminal (+), and the feedback voltage Vfb is supplied to the negative input terminal (-).
Other than this configuration, the operation in the test mode is the same as described in FIG.

As described above, according to the present embodiment, the phase compensation capacitor is enabled and disabled even for a phase compensation capacitor with a capacitance value that causes a very small discharge current compared to the current consumption in the steady state of the voltage regulator. Since the phase compensation capacitance is measured by comparing the phase difference of the output voltage VOUT with respect to the test pulse in each state, there is no need to provide a terminal for directly measuring the phase compensation capacitance, making phase compensation easy and simple. It becomes possible to estimate whether or not there is a connection failure of the capacitance or whether the capacitance value is an abnormal value.

Further, according to the present embodiment, the variable constant current source 18 reduces the bias current of the error amplifier 12 in the test mode compared to the normal mode, thereby reducing the output current of the error amplifier 12. Therefore, the test mode can make the voltage change of the amplified voltage Vcmp at gradual, and the phase difference of the output voltage VOUT with respect to the test pulse can be expanded, and the accuracy of the phase difference comparison can be improved even if the phase compensation capacitor has a very small capacity. It is possible to

In this embodiment, when testing the phase compensation capacitor C1, the test signal SG1 is set at H level and the test signal SG3 is set at L level, and when testing the phase compensation capacitor C2, the test signal SG1 is set at H level and at L level. The setting of the combination of signal levels in which the test signal SG2 is L level has been described. However, it is not limited to the combination of signal levels described above, and any combination of signal levels may be set as long as it is possible to distinguish which of the phase compensation capacitors C1 and C2 is to be tested. For example, when testing the phase compensation capacitor C1, the test signal SG1 is set to H level and the test signal SG3 is set to H level. Test signal SG2 may be set to H level.

Further, in the present embodiment, the test pulse is supplied as the test signal to the voltage adjustment terminal TVADJ when testing the phase compensation capacitors C1 and C2. However, since the propagation delay of the test signal is detected, it can be detected if there is either a rising waveform or a falling waveform of the signal level. A test signal may be supplied as a test signal having a waveform on either side of the curve, and a test may be performed to detect the propagation delay of the test signal.

Although the embodiments of the present invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments, and designs and the like are included within the scope of the gist of the present invention.

DESCRIPTION OF SYMBOLS 1... Voltage regulator 11... Reference power supply 12... Error amplifier 13... Phase compensation circuit 14... Output transistor 15... Feedback phase compensation circuit 16, 17, R1... Resistor 18... Variable constant current source 19... Test circuit 20... State limiting circuit 21 ... Transistor 22 ... Constant current source C1, C2 ... Phase compensation capacitor

Claims (4)

An output voltage terminal connected to an output transistor for outputting a predetermined output voltage, a voltage adjustment terminal for detecting the output voltage, and the output voltage detected at the voltage adjustment terminal and a reference voltage are compared. a voltage regulator comprising: an error amplifier for controlling the output voltage by controlling the control terminal of the output transistor using the error amplifier; and a phase compensation capacitor for adjusting the phase in the control loop of the output voltage using the error amplifier. and
a switch that enables or disables the phase compensation capacitor;
In a test mode for testing the phase compensation capacitor by inputting a test signal from the voltage adjustment terminal and measuring the change in the phase of the output voltage when the phase compensation capacitor is enabled or disabled, the switch a test circuit that either enables or disables the
A voltage regulator comprising: 2. The voltage regulator according to claim 1, further comprising a state limiting circuit that fixes said switch to a state in which said phase compensation capacitor is enabled during a normal mode that is not said test mode. 3. The phase compensation capacitor is provided between the output voltage terminal and the output terminal of the error amplifier, and delays the phase of the output voltage output from the error amplifier. 2. The voltage regulator according to 2. The phase compensation capacitor is provided between the voltage adjustment terminal and an input terminal to which a voltage to be compared with the reference voltage of the error amplifier is input, and advances the phase of the output voltage input to the error amplifier. The voltage regulator according to any one of claims 1 to 3, characterized by:

Images