JP7280011B2 - Manufacturing method for semiconductor device manufacturing member - Google Patents

Description

TECHNICAL FIELD The present invention relates to a method for manufacturing a member for manufacturing a semiconductor device, and more particularly to a method for manufacturing a member for manufacturing a semiconductor device for efficiently manufacturing, at low cost, a semiconductor device for which there is a high demand for miniaturization and high density. .

For the purpose of increasing the density and performance of semiconductor packages, a mounting form in which chips with different performance are mixed in a single package has been proposed. (See, for example, Patent Document 1).

A package-on-package connection, in which different packages are stacked on a package by flip-chip mounting, is widely used in smartphones and tablet terminals (see, for example, Non-Patent Document 1 and Non-Patent Document 2). As a form for mounting at a higher density, package technology using an organic substrate with high-density wiring (organic interposer), fan-out type package technology (FO-WLP) with through mold vias (TMV), silicon or A package technology using a glass interposer, a package technology using a through silicon via (TSV), a package technology using a chip embedded in a substrate for chip-to-chip transmission, and the like have been proposed.

Especially in organic interposers and FO-WLPs, when semiconductor chips are mounted in parallel, a fine wiring layer is required for high-density conduction (see Patent Document 2, for example).

Japanese translation of PCT publication No. 2012-529770 U.S. Patent Application Publication No. 2001/0221071

Application of Through Mold Via (TMV) as PoP Base Package, Electronic Components and Technology Conference (ECTC), 2008 Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology, ECTC, 2012

An organic interposer having a laminate (organic insulating laminate) formed by laminating a plurality of organic insulating layers is sometimes used for a build-up substrate, a wafer level package (WLP), a fan-out type PoP bottom package, and the like. be. For example, when a plurality of fine wirings having line widths and space widths of 5 μm or less are arranged in this organic insulating laminate, the wirings are formed using a trench method. The trench method is a method of forming a metal layer to be wiring in a trench (groove) formed on the surface of an organic insulating layer by plating or the like. Therefore, the shape of the wiring formed on the organic insulating layer follows the shape of the groove.

When fine wiring is formed in an organic insulating laminate by the trench method, a highly conductive metal material such as copper is sometimes used in order to reduce costs and suppress an increase in wiring resistance. When wiring is formed using such a metal material, the metal material may diffuse into the organic insulating laminate. In this case, wirings may be short-circuited through the diffused metal material, and there is a problem in the insulation reliability of the organic interposer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a member for manufacturing a semiconductor device having a fine wiring layer with sufficiently high insulation reliability.

A method of manufacturing a member for manufacturing a semiconductor device according to the present invention comprises the steps of forming an insulating material layer on a support, forming recesses in the surface of the insulating material layer, and modifying the surface of the insulating material layer including the recesses. forming a palladium adsorption layer on the surface including the recesses of the modified insulating material layer; and electroless nickel plating the surface including the recesses of the insulating material layer on which the palladium adsorption layer is formed. forming a nickel layer; forming a copper layer on the nickel layer by electrolytic copper plating; and removing the copper layer, the nickel layer, and the palladium adsorption layer formed in regions other than the recesses on the surface of the insulating material layer. forming a wiring layer including a copper layer formed in the concave portion; and forming a nickel barrier layer on the exposed surface of the wiring layer by electroless nickel plating.

According to the present invention, a method for manufacturing a member for manufacturing a semiconductor device having a fine wiring layer with sufficiently high insulation reliability is provided.

FIG. 1(a) is a cross-sectional view schematically showing a state in which an insulating material layer is formed on a support, and FIG. 1(b) is a cross-sectional view schematically showing a state in which recesses are formed in the insulating material layer. FIG. 1(c) is a cross-sectional view schematically showing a state in which a palladium catalyst adsorption layer is formed on the surface of the insulating material layer by pretreatment, and FIG. 1(d) is an electroless nickel plating on the insulating material. It is a sectional view showing a state typically. FIG. 2(a) is a cross-sectional view schematically showing a state in which electrolytic copper plating is performed using electroless nickel as a seed layer, and FIG. 2(b) is a cross-sectional view schematically showing a state in which a wiring layer is exposed by surface polishing. FIG. 2(c) is a cross-sectional view schematically showing a state in which a nickel barrier layer is formed on the exposed wiring layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and overlapping descriptions are omitted. In addition, unless otherwise specified, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to the illustrated ratios.

Where terms such as “left”, “right”, “front”, “rear”, “upper”, “lower”, “upper”, “lower” are used in the description and claims of this specification, They are meant to be illustrative and do not necessarily mean that they are in this relative position forever. Further, the term "layer" includes not only the shape structure formed over the entire surface but also the shape structure formed partially when viewed as a plan view.

A method of manufacturing a member for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The method of manufacturing a member for manufacturing a semiconductor device according to the present embodiment is particularly suitable for a form that requires miniaturization and a large number of pins, and is particularly suitable for a package form that requires an interposer for mixed mounting of different types of chips. is. More specifically, in the manufacturing method according to the present embodiment, the line width is 20 μm or less (for example, 0.5 to 10 μm for finer lines) and the space width is 20 μm or less (for finer lines, for example 0.5 to 10 μm) in a package form having a trench structure.

The method of manufacturing a member for manufacturing a semiconductor device according to the present embodiment includes a step (I) of forming an insulating material layer 1 on a support S, and a step (II) of forming a concave portion 1a on the surface of the insulating material layer 1. a step (III) of modifying the surface of the insulating material layer 1 including the recesses 1a; a step (IV) of forming a palladium adsorption layer 3 on the modified surface of the insulating material layer 1 including the recesses 1a; Step (V) of forming a nickel layer 5 by electroless nickel plating on the surface of the insulating material layer 1 on which the palladium adsorption layer 3 is formed, including the recesses 1a, and forming a copper layer 7 on the nickel layer 5 by electrolytic copper plating. forming step (VI), and removing the copper layer 7, the nickel layer 5 and the palladium adsorption layer 3 formed in the area (on the upper surface of the insulating material layer 1) other than the recess 1a on the surface of the insulating material layer 1 a step (VII) of forming the wiring layer 8 including the copper layer 7 formed in the recess 1a by the step (VII), and a step of forming the nickel barrier layer 9 on the exposed surface 8a of the wiring layer 8 by electroless nickel plating ( VIII).

According to the manufacturing method described above, diffusion of copper contained in the wiring layer 8 is prevented by the nickel barrier layer 9, so that a semiconductor device manufacturing member having a fine wiring layer with sufficiently high insulation reliability can be manufactured. . Each step will be described below.

<Step (I) of Forming an Insulating Material Layer on a Support>
First, a step (I) of forming an insulating material layer 1 on a support S of a semiconductor device manufacturing member is performed (FIG. 1(a)). The support S is not particularly limited, but may be a silicon plate, a glass plate, a SUS plate, a substrate containing glass cloth, a sealing resin containing a semiconductor element, or the like, and a highly rigid substrate is preferable.

The thickness of the support S is preferably in the range of 0.2 mm to 2.0 mm. If the thickness is less than 0.2 mm, handling becomes difficult, while if the thickness is more than 2.0 mm, the material cost tends to increase. The support S may be wafer-shaped or panel-shaped. Although the size is not particularly limited, a wafer with a diameter of 200 mm, 300 mm or 450 mm, or a rectangular panel with a side of 300 to 700 mm is preferably used.

It is preferable to adopt a photosensitive resin material as the material for forming the insulating material layer 1, because the fine recesses 1a can be easily formed by a photolithography process in step (II) described later. Examples of the photosensitive insulating material include those in the form of a liquid or a film, and the photosensitive insulating material in the form of a film is preferable from the viewpoint of film thickness flatness and cost. In addition, the photosensitive insulating material preferably contains a filler having an average particle size of 500 nm or less (more preferably 50 to 200 nm) in order to form fine wiring. The filler content of the photosensitive insulating material is preferably 0 to 70 parts by mass, more preferably 0 to 50 parts by mass, per 100 parts by mass of the photosensitive insulating material excluding the filler.

When a film-like photosensitive insulating material is used, the lamination process is preferably carried out at a temperature as low as possible, and it is preferable to employ a photosensitive insulating film that can be laminated at 40°C to 120°C. Photosensitive insulating films that can be laminated at temperatures below 40°C tend to be tacky at room temperature (approximately 25°C) and are difficult to handle, while photosensitive insulating films that exceed 120°C tend to warp after lamination. There is

The coefficient of thermal expansion of the insulating material layer 1 after curing is preferably 80×10 ⁻⁶ /K or less from the viewpoint of suppressing warpage, and is 70×10 ⁻⁶ /K or less from the viewpoint of obtaining high reliability. is more preferable. In addition, it is preferably 20×10 ⁻⁶ /K or more in terms of the stress relaxation property of the insulating material and obtaining a high-definition pattern.

The thickness of the insulating material layer 1 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less. When the thickness of the insulating material layer 1 is within the above range, for example, it is easy to form the concave portion 1a having a fine trench structure in the step (II) described later. The thickness of the insulating material layer 1 is preferably 1 μm or more from the viewpoint of insulation reliability.

<Step (II) of Forming Concaves in Insulating Material Layer>
Next, the step (II) of forming recesses 1a on the surface of the insulating material layer 1 is performed (FIG. 1(b)). In this embodiment, the recess 1a refers to a portion recessed in the thickness direction of the insulating material layer 1 with respect to the surface of the insulating material layer 1, and includes inner walls (side surfaces, bottom surface, etc.) of this recessed portion. As shown in FIG. 1(b), the recess 1a is formed to extend to the surface of the support S, namely, the side surface made of the insulating material layer 1 and the bottom surface made of the surface of the support S. It is preferably configured by The recess 1a preferably has a trench structure. In this case, the opening width (line width) is, for example, 0.5 to 20 μm, and may be 0.5 to 5 μm in the case of a finer structure. By setting the opening width of the concave portion 1a within the above range, there is a tendency to easily provide a semiconductor device that achieves high density. That is, it is easy to manufacture a semiconductor device having a fine wiring layer with a good yield and at low cost. The shape of the opening of the concave portion 1a may be, for example, circular or elliptical, and the size of the opening in this case corresponds to the area of a circle with a diameter of 5 to 50 μm (5 to 10 μm in the case of finer diameter). It may be to some extent.

Examples of the method for forming the concave portion 1a include laser ablation, photolithography, and imprinting. It is preferable to form the recesses 1a by processes (exposure and development). As a method for exposing the photosensitive resin material, a normal projection exposure method, a contact exposure method, a direct exposure method, or the like can be used. It is preferable to use After forming the recesses 1a in the insulating material layer 1, the insulating material may be further cured by heating. The heating temperature is 100° C. to 200° C., and the heating time is 30 minutes to 3 hours.

<Step (III) for surface modification>
Next, the step (III) of modifying the surface of the insulating material layer 1 including the recesses 1a is performed (not shown). In the present embodiment, modification means making the surface of the insulating material layer 1 into a state in which the palladium catalyst is more likely to be adsorbed prior to step (IV). Since this treatment is performed before step (IV), this modification treatment may be hereinafter referred to as "pretreatment".

As a reforming method, any of the following wet pretreatment and dry pretreatment can be used. Examples of pretreatment liquids (modifying liquids) used in wet pretreatment include silane cups containing polyethers, glycol ethers, amines, amides, ureides, triazines, melamine, imidazoles, triazoles, benzotriazoles, etc. in their molecules. Examples include those containing at least one selected from the group consisting of ring agents. The type of solvent used in these pretreatment liquids is not particularly limited, and can be selected from commonly used organic solvents and water, and may be used alone or in combination of two or more. Further, a surfactant may be included for the purpose of improving the wettability of the surface of the insulating material layer 1 . In addition, in order to enhance the modification effect, pretreatment may be performed with an aqueous solution containing sodium hypophosphite, potassium hypophosphite, calcium hypophosphite, or the like. Further, as a method of reforming by pretreatment by a wet method other than these, roughening treatment with an acid or an alkali can be mentioned. On the other hand, the pretreatment by the dry method includes surface modification by plasma treatment, corona treatment, ultraviolet treatment, and the like.

Among the above modification methods, it is preferable to modify the surface of the insulating material layer 1 with a pretreatment liquid (modification liquid) containing a silane coupling agent, which is a wet pretreatment, as a pretreatment. . Specific examples of the wet method include a spray method, a dip method, a spin coat method, a printing method, and the like, in which the surface of the insulating material layer 1 is brought into contact with a pretreatment liquid. preferable.

In order to increase the reactivity between the components of the pretreatment liquid and the insulating material layer 1, the surface of the insulating material layer 1 may be activated before the pretreatment for these modifications. Examples of activation methods include ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, and plasma treatment. Ultraviolet irradiation, which does not require vacuum equipment and does not generate waste liquid, is preferred.

A high-pressure mercury lamp, a low-pressure mercury lamp, a vacuum ultraviolet excimer lamp, or the like can be used as a lamp for ultraviolet irradiation used for activation. A low-pressure mercury lamp or an excimer lamp, which has a high activation effect, is preferable.

Activation is preferably performed in the air, more preferably in an oxygen atmosphere.

Activation is preferably carried out at 25°C to 100°C. 40° C. to 100° C. is more preferable, and 60° C. to 100° C. is even more preferable, in order to accelerate the reactivity.

The contact angle between the surface of the insulating material layer 1 and pure water after activation is preferably 40 degrees or less, more preferably 20 degrees or less, and even more preferably 10 degrees or less. Also, the activation process may be repeated multiple times.

Pretreatment is preferably carried out at 25°C to 80°C. 40° C. to 80° C. is more preferable, and 60° C. to 80° C. is even more preferable, in order to accelerate the reactivity. Pretreatment is preferably carried out for 5 to 30 minutes. 10 to 30 minutes is more preferable, and 15 to 30 minutes is even more preferable, in order to accelerate the reactivity. After the contact with the pretreatment liquid used in the pretreatment, it may be washed with water or an organic solvent in order to remove excess pretreatment liquid.

After performing the pretreatment, a heat treatment may be performed in order to increase the bonding strength between the insulating material layer 1 and the silane coupling agent, which is a component of the pretreatment liquid. The heat treatment temperature is preferably 80°C to 200°C. Heating at 120° C. to 200° C. is more preferable, and heating at 120° C. to 180° C. is even more preferable in order to accelerate the reactivity. The heat treatment time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, even more preferably 20 minutes to 60 minutes. Also, pretreatment and heat treatment may be repeated multiple times.

<Step (IV) of forming a palladium adsorption layer>
Next, a step (IV) of forming a palladium adsorption layer 3 on the modified surface of the insulating material layer 1 including the recesses 1a is performed (FIG. 1(c)). In the present embodiment, the palladium adsorption layer 3 means that after palladium is adsorbed on the surface of the insulating material layer 1 including the concave portions 1a, activation is performed so that the palladium acts as a catalyst, and then the subsequent non-reactive process is performed. It serves as a catalyst for the electroless plating reaction in electrolytic nickel plating. A method for forming the palladium adsorption layer 3 will be described below.

First, palladium is deposited on the surface of the first insulating material layer 1 after pretreatment. Palladium may be a commercially available palladium aqueous solution for electroless plating, such as a solution in which palladium-tin colloid is dispersed in water (palladium-tin colloid solution), an aqueous palladium ion solution, a palladium nanoparticle dispersion solution, or the like. The temperature of the aqueous solution used for depositing palladium is 25° C. to 80° C., and the immersion time for deposition is 1 minute to 60 minutes. After depositing palladium, it may be washed with water or an organic solvent to remove excess palladium.

After deposition of palladium, activation is performed to allow the palladium to act as a catalyst. The reagent for activating palladium may be a commercially available activating agent (activation treatment liquid). The temperature of the activating agent for activating palladium is 25° C. to 80° C., and the immersing time for activation is 1 minute to 60 minutes. After activating the palladium, it may be washed with water or an organic solvent to remove excess activator.

<Step (V) of Forming Nickel Layer>
Subsequently, a step (V) of forming a nickel layer 5 by electroless nickel plating on the surface of the insulating material layer 1 including the recesses 1a on which the palladium adsorption layer 3 is formed is performed (FIG. 1(d)). This nickel layer 5 becomes a seed layer (power supply layer for electrolytic copper plating) for electrolytic copper plating to form the copper layer 7 in the subsequent step.

Electroless nickel plating includes electroless pure nickel plating (purity of 99% by mass or more), electroless nickel-phosphorus plating (phosphorus content: 1% to 13% by mass), and electroless nickel-boron plating (boron content : 0.3% by mass to 1% by mass), etc., but from the viewpoint of cost, electroless nickel-phosphorus plating is preferable. The electroless nickel plating solution may be a commercially available plating solution. SB-M", "ICP Nicolon GMSD") can be used. Electroless nickel plating is carried out in an electroless nickel plating solution at 60°C to 90°C.

The thickness of the nickel layer 5 formed by electroless nickel plating is preferably 20 nm to 200 nm, more preferably 40 nm to 200 nm, even more preferably 60 nm to 200 nm.

After electroless nickel plating, it may be washed with water or an organic solvent to remove excess plating solution. After the electroless nickel plating, thermal hardening (annealing: age hardening treatment by heating) may be performed in order to increase the adhesion between the nickel layer 5 and the insulating material layer 1 . The heat curing temperature is preferably 80°C to 200°C. Heating at 120° C. to 200° C. is more preferable, and heating at 120° C. to 180° C. is even more preferable in order to accelerate the reactivity. The heat curing time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, even more preferably 20 minutes to 60 minutes.

<Step (VI) of forming a copper layer>
Next, a step (VI) of forming a copper layer 7 on the nickel layer 5 by electrolytic copper plating is performed (FIG. 2(a)). Specifically, a nickel layer 5 formed by electroless nickel plating is used as a seed layer, and a copper layer 7 is formed on the nickel layer 5 by electrolytic copper plating, and the inner wall is covered with the nickel layer 5. A copper layer 7 is filled in the recess 1a. In addition, in this embodiment, electrolytic copper plating is used as a method of forming the copper layer 7, but, other than this, for example, electroless copper plating can be selected.

The thickness of the copper layer 7 (excluding the region where the recesses 1a are formed) is preferably 1 to 10 μm, more preferably 1 to 5 μm, even more preferably 1 to 3 μm.

As described above, by filling the recess 1a with the copper layer 7, in the next step (VII), the copper layer 7 formed in the region other than the recess 1a on the surface of the insulating material layer 1, nickel The surface of the insulating material layer 1 and the wiring layer 8 (the copper layer 7, the nickel layer 5, and the palladium layer 5) formed in the recess 1a are removed only by removing the layer 5 and the palladium (palladium adsorption layer) remaining thereunder. (composed of the adsorption layer 3) can be flush with each other. In order to fill the recesses 1a with the copper layer 7 by electrolytic copper plating, the deposition amount (plating thickness) of the electrolytic copper plating in the recesses 1a is larger than that on the surface of the insulating material layer 1. It is preferred to use filled plating.

The recess 1a does not necessarily have to be filled with the copper layer 7, and the copper layer 7 may be formed along the inner walls (side and bottom surfaces) of the recess 1a. In this case, in the next step (VII), the copper layer 7, the nickel layer 5, and the palladium (palladium adsorption layer) remaining thereunder formed in regions other than the recesses 1a on the surface of the insulating material layer 1 are removed. After the removal, the surface of the insulating material layer 1 is further scraped to expose the copper layer 7 formed on the bottom surface of the recess 1a, so that the surface of the insulating material layer 1 and the wiring formed in the recess 1a are separated. It can be flush with layer 8 .

<Step (VII) of Forming a Wiring Layer Containing a Copper Layer>
Next, by removing the copper layer 7, the nickel layer 5, and the palladium adsorption layer 3 formed in the area other than the recess 1a on the surface of the insulating material layer 1, the copper layer 7 formed in the recess 1a is included. A step (VII) of forming the wiring layer 8 is performed (FIG. 2(b)). That is, by removing the copper layer 7 and the nickel layer 5 formed on the upper surface of the insulating material layer 1 and the palladium remaining thereunder (the palladium adsorption layer 3), the copper layer 7, the nickel layer 5 and the palladium are removed. A part of the adsorption layer 3 is left in the concave portion 1a. Thereby, a wiring layer 8 composed of the copper layer 7, the nickel layer 5, and the palladium adsorption layer 3 is formed in the recess 1a.

When removing the copper layer 7 and the nickel layer 5 formed on the upper surface of the insulating material layer 1 and the palladium remaining thereunder, the surface of the insulating material layer 1 and the wiring layer 8 in the recess 1a are removed. It is preferable to process so as to become one. In other words, after the step (VII), it is preferable to perform the step (VII) so that the surface of the insulating material layer 1 and the wiring layer 8 in the recess 1a form a flat surface. The removal treatment in step (VII) may target only the copper layer 7 and the nickel layer 5 formed on the upper surface of the insulating material layer 1 and the palladium remaining thereunder. A portion of the top side of layer 1 may also be targeted.

Examples of the removal treatment in step (VII) include back grinding, fly-cutting, chemical mechanical polishing (CMP), and the like. The above may be used in combination. For example, in the fly-cut method, a grinder with a diamond bit may be used. As a specific example, an automatic surface planer compatible with 300 mm wafers (manufactured by DISCO Corporation, trade name "DAS8930") can be used. The removing process by the fly-cutting method can be said to be a flattening process because the entire surface of the copper layer 7 is uniformly polished from the upper surface side, and the polished surface becomes flat.

<Step (VIII) of forming a nickel barrier layer>
Next, a step (VIII) of forming a nickel barrier layer 9 by electroless nickel plating on the exposed surface 8a of the wiring layer 8 formed by the removal treatment in the step (VII) is performed (FIG. 2(c)). . Thus, the wiring board 10 (member for manufacturing a semiconductor device) is manufactured. For example, the exposed surface 8a of the wiring layer 8 is degreased, washed with water, washed with sulfuric acid, palladium catalyzed, and nickel-plated in this order, so that the nickel barrier layer 9 can be formed only on the exposed surface 8a. As a plating solution for electroless nickel plating, a commercially available displacement electroless plating solution can be applied.

By covering the exposed surface 8a of the wiring layer 8 with the nickel barrier layer 9, diffusion of copper contained in the wiring layer 8 can be sufficiently suppressed. Therefore, the wiring substrate 10 is useful for manufacturing a semiconductor device having fine wiring layers with sufficiently high insulation reliability. The thickness of the nickel barrier layer 9 is preferably 50-500 nm, more preferably 100-400 nm, even more preferably 150-300 nm. When the thickness of the nickel barrier layer 9 is 50 nm or more, a sufficient copper diffusion suppressing effect can be easily obtained. Easy to thin.

Although the semiconductor device manufacturing member (wiring board) has been described above, the present invention is not necessarily limited to the above-described embodiments, and may be appropriately modified without departing from the spirit of the present invention.

For example, in the above embodiment, the method of manufacturing the wiring board 10 having a single wiring layer was illustrated, but instead of the wiring board 10, a wiring board having multiple wiring layers was manufactured and used. A semiconductor device may be manufactured. The multi-layered wiring layer is formed by the step (XI) of forming an insulating material layer so as to cover the insulating material layer 1 and the nickel barrier layer 9 after the step (VIII), and the step (II) to the step (VIII). ) can be formed by repeating a series of steps of (1) and (2) one or more times. For forming the insulating material layer in step (XI), the same material as the insulating material layer 1 described above may be used, and a photosensitive insulating material is preferable. The insulating material layer may be formed in the same manner as the insulating material layer 1 . The thickness of the insulating material layer is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less.

S... support 1... insulating material layer 1a... concave portion 3... palladium adsorption layer 5... nickel layer 7... copper layer 8... wiring layer 8a... exposed surface 9... nickel barrier layer 10... wiring Substrates (components for manufacturing semiconductor devices).

Claims (7)

Step (I) of forming an insulating material layer on the support;
a step (II) of forming a recess in the surface of the insulating material layer;
Step (III) of modifying the surface of the insulating material layer including the recesses;
Step (IV) of forming a palladium adsorption layer on the modified surface of the insulating material layer including the recesses;
step (V) of forming a nickel layer by electroless nickel plating on the surface of the insulating material layer on which the palladium adsorption layer is formed, including the recesses;
a step (VI) of forming a copper layer on the nickel layer by electrolytic copper plating or electroless copper plating;
removing the copper layer, the nickel layer, and the palladium adsorption layer formed in the surface of the insulating material layer except for the recess, thereby removing the wiring layer including the copper layer formed in the recess; a forming step (VII);
a step (VIII) of forming a nickel barrier layer on the exposed surface of the wiring layer by displacement electroless nickel plating;
A method for manufacturing a member for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a member for manufacturing a semiconductor device according to claim 1, wherein the surface of said insulating material layer and said wiring layer formed in said recess form a flat surface after said step (VII). The insulating material layer is made of a photosensitive resin material,
3. The method of manufacturing a member for manufacturing a semiconductor device according to claim 1, wherein said concave portion in said step (II) is formed by exposure and development. 4. The method of manufacturing a member for manufacturing a semiconductor device according to claim 1, wherein said recess formed in said step (II) has an opening width of 0.5 to 20 μm. Step (I) of forming an insulating material layer on the support;
a step (II) of forming a recess in the surface of the insulating material layer;
Step (III) of modifying the surface of the insulating material layer including the recesses;
Step (IV) of forming a palladium adsorption layer on the modified surface of the insulating material layer including the recesses;
step (V) of forming a nickel layer by electroless nickel plating on the surface of the insulating material layer on which the palladium adsorption layer is formed, including the recesses;
a step (VI) of forming a copper layer on the nickel layer by electrolytic copper plating or electroless copper plating;
By removing the copper layer, the nickel layer and the palladium adsorption layer formed on the surface of the insulating material layer other than the recess, a wiring layer including the copper layer formed in the recess is removed. a forming step (VII);
a step (VIII) of forming a nickel barrier layer on the exposed surface of the wiring layer by displacement electroless nickel plating;
including
A method of manufacturing a member for manufacturing a semiconductor device, wherein the step (III) includes irradiating the surface of the insulating material layer including the concave portion with ultraviolet rays. 6. The method of manufacturing a member for manufacturing a semiconductor device according to claim 5, wherein said step (III) further comprises modifying said surface with a pretreatment liquid containing a silane coupling agent after irradiation with ultraviolet rays. a step (XI) of forming an insulating material layer so as to cover the insulating material layer and the nickel barrier layer after the step (VIII);
a series of steps from step (II) to step (VIII);
7. The method for manufacturing a member for manufacturing a semiconductor device according to claim 1, wherein a multi-layered wiring layer is formed by repeating the above steps one or more times.

Images