JP7272323B2 - game machine - Google Patents

Description

The present invention relates to gaming machines.

Pachinko machines, slot machines, and the like are known as game machines. For example, a pachinko machine is equipped with a plate storage section for storing game balls given to a player in the front part of the gaming machine, and the game balls stored in the plate storage section are guided to the game ball launching device, It is shot toward the game area according to the player's shooting operation. Then, for example, when a game ball enters a ball entry portion provided in the game area, the game ball is paid out from the payout device to the plate storage portion, for example. Further, in a pachinko machine, there is also known a configuration in which an upper plate storage portion and a lower plate storage portion are provided as the plate storage portions. , and surplus game balls in the upper tray storage section are discharged to the lower tray storage section (see Patent Document 1, for example).

Further, in the slot machine, when the start lever is operated to start a new game while medals are bet, the control means executes the lottery process. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Japanese Unexamined Patent Application Publication No. 2018-20012

Here, in the game machines such as those exemplified above, it is necessary to suitably transmit the information group, and there is still room for improvement in this regard.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of suitably transmitting a group of information.

In order to solve the above problem, the invention according to claim 1 comprises a transmission means for transmitting a predetermined information group,
The predetermined information group includes a plurality of unit information in units of predetermined bytes,
In the unit information of the predetermined byte unit at the beginning of the predetermined information group, information of a bit at a predetermined position is specific bit information,
In the unit information of the predetermined byte unit other than the head in the predetermined information group, the information of the bit at the predetermined position is information other than the specific bit information,
In the predetermined information group, one or more predetermined unit information as unit information of the predetermined byte unit other than the head, and set to the bit at the predetermined position in the predetermined unit information after receiving the predetermined information group. Aggregation unit information in which information is aggregated is set .

ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to perform transmission of an information group suitably.

1 is a perspective view showing a pachinko machine according to a first embodiment; FIG. 1 is an exploded perspective view showing the main components of a pachinko machine; FIG. It is a front view which shows the structure of a game board. (a) to (j) are explanatory diagrams for explaining display contents on the display surface of the pattern display device. 4A and 4B are explanatory diagrams for explaining display contents on the display surface of the pattern display device; FIG. It is an explanatory view for explaining the configuration related to the discharge of the game ball that has flowed down the game area. It is a front view of a main controller. 1 is a block diagram showing an electrical configuration of a pachinko machine; FIG. It is an explanatory view for explaining composition of main side MPU. (a) It is an explanatory diagram for explaining a setting mode of various areas in the main RAM, and (b) an explanatory diagram for explaining a setting mode of data and programs in the main ROM. It is an explanatory view for explaining the contents of various counters used for winning or losing lottery. (a) is an explanatory diagram for explaining how various counters are set in a work area for specific control; (b) is an explanatory diagram for explaining how various maximum value counters are set in a work area for specific control; be. FIG. 4 is an explanatory diagram for explaining various tables stored in a main-side ROM; (a) An explanatory diagram for explaining a first special figure distribution table, and (b) an explanatory diagram for explaining a second special figure distribution table. It is a flowchart which shows the main process in main side CPU. (a) is an explanatory diagram for explaining a storage area where "0" clearing and initial setting are performed in the power-on setting process, and (b) is an explanatory diagram for explaining the data configuration of the power failure area. (a) is an explanatory diagram for explaining the data structure of the machine language of the LDT instruction; (b) is an explanatory diagram for explaining the data structure of the machine language of the LD instruction; FIG. 4 is an explanatory diagram for explaining program contents of a power-on setting process to be executed; (a) is an explanatory diagram for explaining the data structure of a first initialization table; (b) is an explanatory diagram for explaining the data structure of a second initialization table; (a) and (b) are explanatory diagrams for explaining an LDH update command, and (c) is an explanatory diagram for explaining program contents of a data setting execution process. FIG. 10A to FIG. 10G are explanatory diagrams for explaining states of the D register, the E register, the W register, the A register, and the HL register when the data setting execution process is executed in the power-on setting process; (a) is a flowchart showing a clear handling process executed by the main CPU, (b) is an explanatory diagram for explaining a storage area in which data is set in the setting process when clearing, and (c) is a security signal. FIG. 4 is an explanatory diagram for explaining the data structure of an area; (a) An explanatory diagram for explaining a setting table for clearing, and (b) an explanatory diagram for explaining program contents of a setting process for clearing executed by the main CPU. (a) It is an explanatory diagram for explaining a random number maximum value table, and (b) a flowchart showing a random number maximum value setting process executed by the main CPU. (a) is an explanatory diagram for explaining the data structure of the machine language of the first LDY instruction; (b) is an explanatory diagram for explaining the program contents of the maximum value setting start process executed by the main CPU; . It is a flowchart which shows the setting value update process performed by main side CPU. It is a flowchart which shows the timer interrupt processing performed by main side CPU. (a) It is a flowchart which shows the 1st random number update process performed by main side CPU, (b) It is explanatory drawing for demonstrating the program content of the update start setting process performed by main side CPU. It is a flowchart which shows the 2nd random number update process performed by main side CPU. (a) It is a flowchart which shows the fraud detection process performed by main side CPU, (b) It is explanatory drawing for demonstrating the program content of the initialization process for fraud detection performed by main side CPU. It is a flowchart which shows the special figure special electric control processing performed by main side CPU. It is an explanatory view for explaining the data configuration of a special figure special electric address table. (a) ~ (d) is an explanatory diagram for explaining the process of calculating the acquisition start address and acquisition start bit from the acquisition data designation data, (e), (f) from the special special electric address table to the HL register FIG. 10 is an explanatory diagram for explaining how a start address is acquired in . (a) It is an explanatory diagram for explaining the program contents of the special special electric address acquisition process executed by the main side CPU, and (b) to (d) is an explanation for explaining the process of calculating "TBL_TZTD_B". FIG. 12(e) is an explanatory diagram for explaining program contents of an address acquisition execution process executed by the main CPU. It is an explanatory diagram for explaining the correspondence relationship between the value of the special figure special electric counter and the start address acquired by the HL register. It is a flow chart showing a special figure variation start process executed by the main side CPU. (a) is an explanatory diagram for explaining the structure of the validity data area, (b) is an explanatory diagram for explaining the contents of the high probability validity table, and (c) is an explanatory diagram for explaining the data structure of the high probability validity table. It is an explanatory diagram for. (a) is a flowchart showing high-probability judgment processing executed by the main CPU, and (b) is an explanatory diagram for explaining the program content of the success judgment data acquisition processing executed by the main CPU. (c) is an explanatory diagram for explaining how determination value data is set in a WA register; and (d) is an explanatory diagram for explaining how flag data is set in a B register. (a) to (e) high probability table start address, acquisition data designation data in LDB instruction (“LDB WA, (HL+).5”), acquisition start address, acquisition start bit, and acquired data after update FIG. 4 is an explanatory diagram for explaining specified data; (a) to (c) Description for explaining acquisition data designation data, acquisition start address, acquisition start bit, and updated acquisition data designation data in the LDB instruction (“LDB B, (HL+).1”) It is a diagram. The number of executions of the LDB update instruction "LDB WA, (HL+).5" and the LDB update instruction "LDB B, (HL+).1", and the data acquired in the WA register and B register by the LDB update instruction It is an explanatory view for explaining. (a) An explanatory diagram for explaining the configuration of the distribution data area, (b) an explanatory diagram for explaining the data configuration of the first special figure distribution table, and (c) the second special figure. FIG. 4 is an explanatory diagram for explaining the data structure of an allocation table; It is a flowchart which shows the 1st result correspondence process performed by main side CPU. (a) is an explanatory diagram for explaining the contents of a program for distribution data acquisition processing executed by the main CPU, and (b) is an explanation of how the first pre-addition distribution value is set in the W register; (c) is an explanatory diagram for explaining how the first flag data is set in the B register; (a) ~ (e) First special figure distribution table start address, acquisition data designation data in LDB instruction ("LDB W, (HL+).4"), acquisition start address, acquisition start bit, and update FIG. 10 is an explanatory diagram for explaining later acquisition data designation data; (a) to (c) Description for explaining acquisition data designation data, acquisition start address, acquisition start bit, and updated acquisition data designation data in the LDB instruction (“LDB B, (HL+).2”) It is a diagram. The number of executions of the LDB update instruction "LDB W, (HL+).4" and the LDB update instruction "LDB B, (HL+).2", and the data acquired in the W register and B register by these LDB update instructions It is an explanatory view for explaining. It is an explanatory diagram for explaining the correspondence relationship between the variation type number and the result of the determination, the result of the distribution determination, the result of the reach occurrence lottery, and the number of reservations in the first special figure reservation area. It is a flowchart which shows the 2nd result correspondence process performed by main side CPU. FIG. 10 is an explanatory diagram for explaining the data configuration of a fluctuation start table; (a) is an explanatory diagram for explaining how the start address of the fluctuation pattern table is acquired, and (b) is an explanatory diagram for explaining the program content of the fluctuation start address acquisition process executed by the main CPU. be. (a) is an explanatory diagram for explaining the data structure of a variation pattern table corresponding to a variation type number of "0", and (b) stores stop result data and display duration data in a work area for specific control FIG. 2 is an explanatory diagram for explaining the configuration of an area for It is a flowchart which shows the variation information setting process performed by main side CPU. (a) is an explanatory diagram for explaining the data configuration of a pending display data table, (b) is an explanatory diagram for explaining an acquisition mode of pending display data, and (c) is a pending display data table of a comparative example. FIG. 4 is an explanatory diagram for explaining a data structure; It is a flowchart which shows the display control process performed by main side CPU. (a) is an explanatory diagram for explaining the program content of the first special figure pending display data acquisition process executed by the main CPU, (b) pending display data acquisition execution process executed by the main CPU (c) is an explanatory diagram for explaining the program content of the second special figure pending display data acquisition process executed by the main side CPU, (d) main It is an explanatory view for explaining the program contents of the general-purpose map reservation display data acquisition process executed by the side CPU. (a) is a flowchart showing a management process executed by the main CPU, and (b) is an explanatory diagram for explaining a setting mode of various buffers in a work area for non-specific control. It is a flowchart which shows the management execution process performed by main side CPU. FIG. 4 is an explanatory diagram for explaining the configuration of a work area for non-specific control; It is a flowchart which shows the check process performed by main side CPU. It is a flowchart which shows the normal ball entry management process performed by main side CPU. FIG. 4 is an explanatory diagram for explaining electrical configurations of a main control board and an audio emission control board for transmitting commands from the main side CPU to the sound and light side CPU; (a) is an explanatory diagram for explaining the data structure of a header, (b) is an explanatory diagram for explaining the data structure of a footer, and (c) is an explanatory diagram for explaining the data structure of a variation command for communication. (d) is an explanatory diagram for explaining the data configuration of a post-conversion variation command. FIG. 10 is an explanatory diagram for explaining a mode of generating a variation command for communication; FIG. 4 is an explanatory diagram for explaining the data configuration of a normal return command for communication; FIG. 10 is an explanatory diagram for explaining the data structure of a post-conversion normal return command; FIG. 10 is an explanatory diagram for explaining how a normal return command for communication is generated; (a) is an explanatory diagram for explaining a conversion mode of a communication variation command; (b) is an explanatory diagram for explaining a conversion mode of a normal return command for communication; (a) is a flowchart showing variation command transmission processing executed by the main CPU, and (b) is an explanatory diagram for explaining the data configuration of a variation command generation table. FIG. 11 is a flow chart showing variation command setting processing executed by the main CPU; FIG. FIG. 10 is a flowchart showing return command transmission processing executed by the main CPU; FIG. FIG. 4 is an explanatory diagram for explaining the data configuration of a normal return command generation table; FIG. 10 is a flow chart showing normal return command setting processing executed by the main CPU; FIG. FIG. 10 is a flowchart showing command reception handling processing executed by the sound and light side CPU; FIG. 4 is a flowchart showing first command conversion processing executed by a sound and light CPU; FIG. 11 is a flow chart showing a second command conversion process executed by the sound and light side CPU; FIG. It is an explanatory view for explaining the configuration of the main control board in the second embodiment. (a) is an explanatory diagram for explaining the maximum value of the update circuit; (b) is an explanatory diagram for explaining the data structure of a hard random number maximum value table; (a) is a flowchart showing a random number maximum value setting process executed by the main CPU; (b) is an explanatory diagram for explaining the program contents of the update circuit setting process executed by the main CPU; (b) It is an explanatory diagram for explaining the program content of the maximum value setting execution process executed by the main CPU. It is a flowchart which shows the display control process performed by main side CPU in 3rd Embodiment. (a) is an explanatory diagram for explaining the data structure of a pending display data table, (b) is an explanatory diagram for explaining a mode of acquiring pending display data, and (c) is executed by the main CPU. FIG. 10 is a flowchart showing pending display acquisition processing, and is an explanatory diagram for explaining program contents of pending display acquisition execution processing executed by the main CPU (d). (a) is an explanatory diagram for explaining the data structure of a first initialization table in the fourth embodiment; (b) is an explanatory diagram for explaining the data structure of a second initialization table; ) is an explanatory diagram for explaining the data configuration of a random number maximum value table. FIG. 4 is an explanatory diagram for explaining the program contents of the power-on setting process executed by the main CPU, and is an explanatory diagram for explaining the program contents of the data setting execution process executed by the main CPU; It is a flowchart which shows the random number maximum value setting process performed by main side CPU. (a) is an explanatory diagram for explaining the data configuration of a second initialization table in the fifth embodiment, and (b) is a flowchart showing random number maximum value setting processing executed by the main CPU. (a) is an explanatory diagram for explaining the configuration of the main MPU in the sixth embodiment, and (b) to (e) shows the process of calculating an acquisition start address and an acquisition start bit number from acquisition data designation data; It is an explanatory view for explaining. (a) and (b) are explanatory diagrams for explaining how the start address is acquired from the special special electric address table to the HL register, and (c) special special electric address acquisition processing executed by the main CPU. (d) to (f) are explanatory diagrams for explaining the process of calculating "TBL_TZTD2_B". It is an explanatory diagram for explaining the correspondence relationship between the value of the special figure special electric counter and the start address acquired by the HL register. It is a flowchart which shows the address acquisition execution process performed by main side CPU.

<First embodiment>
A first embodiment of a pachinko game machine (hereinafter referred to as a "pachinko machine"), which is a type of game machine, will be described in detail below with reference to the drawings. FIG. 1 is a perspective view of a pachinko machine 10, and FIG. 2 is an exploded perspective view showing the main components of the pachinko machine 10. As shown in FIG. 2, the configuration within the game area of the pachinko machine 10 is omitted for the sake of convenience.

The pachinko machine 10, as shown in FIG. 1, has an outer frame 11 forming an outer shell of the pachinko machine 10 and a game machine main body 12 attached to the outer frame 11 so as to be rotatable forward. . The outer frame 11 is formed by connecting wooden plates on four sides and has a rectangular frame shape. A pachinko machine 10 is installed in a game hall by fixing an outer frame 11 to an island facility. Incidentally, the pachinko machine 10 does not have to have the outer frame 11, and the pachinko machine 10 may have a structure in which the outer frame 11 is attached to the island facilities of the game hall.

As shown in FIG. 2, the game machine body 12 includes an inner frame 13, a front door frame 14 arranged in front of the inner frame 13, and a back pack unit 15 arranged behind the inner frame 13. ing. The inner frame 13 of the game machine main body 12 is rotatably supported with respect to the outer frame 11 . More specifically, the inner frame 13 can be rotated forward with the left side as the rotation base end side and the right side as the rotation tip side in a front view.

A front door frame 14 is rotatably supported by the inner frame 13, and is rotatable forward with the left side as the rotation base end side and the right side as the rotation tip side in a front view. In addition, the back pack unit 15 is rotatably supported by the inner frame 13, and is rotatable rearward with the left side as the rotation base end and the right side as the rotation tip side in a front view.

The gaming machine main body 12 is provided with a locking device at its turning tip, and has a function of locking the gaming machine main body 12 to the outer frame 11 so that it cannot be opened. It has a function of locking the door frame 14 with respect to the inner frame 13 so that it cannot be opened. Each of these locked states is released by unlocking the cylinder lock 17 exposed on the front surface of the pachinko machine 10 using an unlock key.

Next, the configuration of the front side of the gaming machine body 12 will be described.

The inner frame 13 is mainly composed of a resin base 21 that has substantially the same outer shape as the outer frame 11 . A substantially elliptical window hole 23 is formed in the central portion of the resin base 21 . A game board 24 is detachably attached to the resin base 21 . The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window holes 23 of the resin base 21 .

Here, the configuration of the game board 24 will be described with reference to FIG. FIG. 3 is a front view of the game board 24. FIG.

An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA. The guide rail is configured as A game ball shot from a game ball shooting mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 is guided to the upper part of the game area PA by guide rails.

Incidentally, the game ball launching mechanism 27 includes a launch rail 27a extending toward the guide rail, a ball feeder 27b that supplies game balls stored in an upper tray 55a, which will be described later, onto the launch rail 27a, and a and a solenoid 27c, which is an electric actuator that shoots the game ball supplied to the guide rail toward the guide rail. When a shooting operation device (or operation handle) 28 provided on the front door frame 14 is rotated, a solenoid 27c is driven and controlled to shoot a game ball.

The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. Each opening has a general winning port 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special figure unit 37, a general figure unit 38, and a round display section 39. etc. are provided respectively.

Even if a ball enters the through gate 35, no game ball is put out. On the other hand, for the general winning opening 31, the special electric winning device 32, the first operating opening 33 and the second operating opening 34, a predetermined number of game balls are paid out when a ball is entered. Specifically, when a ball enters the first working port 33, three prize balls are paid out, and when a ball enters the second working port 34. , one prize ball is paid out, and if a ball enters the general winning hole 31, ten prize balls are paid out and a ball enters the special electric prize winning device 32. If so, 15 prize balls are paid out.

The number of prize balls is arbitrary. For example, although the number of prize balls is smaller in the second operation port 34 than in the first operation port 33, the specific number of prize balls may be different from the above. Well, the number of prize balls may be the same between the first operation port 33 and the second operation port 34 , and the second operation port 34 may have a larger number of prize balls than the first operation port 33 .

In addition, an out port 24a is provided at the bottom of the game board 24, and game balls that do not enter various winning ports are discharged from the game area PA through the out port 24a. Further, the game board 24 is provided with a large number of nails 24b for appropriately dispersing and adjusting the falling direction of game balls, and various members such as windmills.

Here, the entry ball means that the game ball passes through a predetermined opening. A mode in which the liquid continues to flow down the game area PA without being discharged is also included. However, in the following description, in order to clearly distinguish from the entry of game balls into the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 The entry of a game ball into the game ball is also expressed as winning.

The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24 . Both the first working port 33 and the second working port 34 are open upward. Further, the two operating ports 33 and 34 are vertically aligned with the first operating port 33 facing upward. The second operating port 34 is provided with a universal electrical accessory 34a as a guide piece consisting of a pair of left and right movable pieces. A game ball cannot enter the second operating port 34 when the universal electrical role 34a is closed, and the winning to the second operating port 34 becomes possible when the universal electrical role 34a is in the open state.

A through gate 35 is provided upstream of the second operation port 34 in the direction in which the game ball flows. The through-gate 35 has a through-hole (not shown) penetrating in the vertical direction, and a game ball entering the through-gate 35 flows down the game area PA after winning. As a result, the game ball that has entered the through gate 35 can enter the second operating port 34. - 特許庁

Based on the winning of the through gate 35, the universal electrical accessory 34a of the second operating port 34 is switched from the closed state to the open state. Specifically, the internal lottery is performed with the winning of the through gate 35 as a trigger, and the general figure unit 38 provided in the lower right corner which is the area where the game ball does not pass in the game area PA. Variation display of the pattern is performed in the section 38a. Then, when the result of the internal lottery is the electric power open winning, the stop result corresponding to the result is displayed, and the variable display of the universal diagram display section 38a ends, the state shifts to the electric power open state. In the common electric open state, the common electric accessory 34a is opened in a predetermined manner.

In addition, the normal figure display unit 38a is composed of a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but is not limited to this, and may be a liquid crystal display device or an organic EL display device. , CRT or other type of display such as a dot matrix display. In addition, as the pattern variably displayed in the normal figure display unit 38a, a configuration in which a plurality of types of characters are variably displayed, a configuration in which a plurality of types of symbols are variably displayed, a configuration in which a plurality of types of characters are variably displayed, or A configuration in which a plurality of types of colors are switched and displayed can be considered.

In the normal pattern unit 38, a normal pattern holding display portion 38b is provided at a position adjacent to the normal pattern display portion 38a. The number of winning game balls in the through gate 35 is reserved up to four, and the reserved number is displayed by lighting of the normal figure reservation display section 38b.

A winning lottery is performed with the winning of the first operating port 33 or the second operating port 34 as a trigger. Then, the result of the lottery is clearly shown through the display effect on the special figure unit 37 and the symbol display device 41 of the variable display unit 36. - 特許庁

In detail about the special figure unit 37, the special figure unit 37 is provided with a first special figure display portion 37a and a second special figure display portion 37b. The display area of the first special figure display portion 37a is narrower than the display surface 41a of the symbol display device 41, and similarly, the display area of the second special figure display portion 37b is narrower than the display surface 41a of the symbol display device 41. Furthermore, the area of the display area including the first special figure display portion 37a and the second special figure display portion 37b is also narrower than the display surface 41a.

In the first special figure display portion 37a, a variable display or a predetermined display of the pattern is performed by performing a winning lottery with the winning of the first operation opening 33 as a trigger. Then, a result corresponding to the lottery result is displayed. In addition, in the second special figure display portion 37b, a variable display or a predetermined display of the pattern is performed by performing a winning lottery with the winning of the second operation opening 34 as a trigger. Then, a result corresponding to the lottery result is displayed.

In addition, the first special figure display unit 37a and the second special figure display unit 37b are configured by a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but it is not limited to this Instead, it may be constituted by other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display. In addition, as the pattern displayed in the first special figure display portion 37a and the second special figure display portion 37b, a configuration in which multiple types of characters are displayed, a configuration in which multiple types of symbols are displayed, and multiple types of characters A configuration in which is displayed, a configuration in which a plurality of colors are displayed, or the like is conceivable.

In the special figure unit 37, a first special figure reservation display part 37c and a second special figure reservation display part 37d are provided at positions adjacent to the first special figure display part 37a and the second special figure display part 37b. . The number of game balls winning the first operation port 33 is reserved up to four, and the reserved number is displayed by lighting of the first special figure reservation display section 37c. In addition, the number of game balls winning the second operation opening 34 is reserved up to four, and the reserved number is displayed by lighting of the second special figure reservation display section 37d.

More specifically, the pattern display device 41 is configured as a liquid crystal display device having a liquid crystal display, and display contents are controlled by a display control device, which will be described later. The pattern display device 41 is not limited to a liquid crystal display device, and may be a plasma display device, an organic EL display device, a CRT or other display device having a display surface, or a dot matrix display device. may

In the symbol display device 41, when the variable display or predetermined display of the pattern is performed in the first special symbol display unit 37a based on the winning to the first operation port 33, the variable display or predetermined display of the symbol is performed accordingly. Along with being performed, when the variation display of the pattern or the predetermined display is performed in the second special figure display part 37b based on the winning to the second operation port 34, the variation display of the pattern or the predetermined display is performed accordingly. . In the symbol display device 41, not only the display effects triggered by the winning of the first operation port 33 or the second operation port 34, but also the display effects during the opening/closing execution mode, which will be described later, after winning is won, etc. is done.

The display contents when the symbol display device 41 performs the variable display of the symbols will be described in detail with reference to FIGS. 4 and 5. FIG. 4(a) to (j) are diagrams individually showing the symbols that are variably displayed on the pattern display device 41, and FIGS. It is an explanatory view for explaining.

As shown in FIGS. 4(a) to 4(j), the pattern, which is one type of pattern, consists of 9 types of main patterns to which numbers "1" to "9" are respectively attached, and a shell-shaped picture pattern. It is composed of sub-patterns. More specifically, nine types of character patterns such as an octopus are assigned numbers '1' to '9' to form main patterns.

As shown in FIG. 5A, the display surface 41a of the pattern display device 41 is provided with three pattern rows Z1, Z2, and Z3 of upper, middle, and lower rows as a plurality of display areas. Each of the symbol rows Z1 to Z3 is constructed by arranging main symbols and sub-symbols in a predetermined order. Specifically, in the upper symbol row Z1, 9 types of main symbols "1" to "9" are arranged in descending numerical order, and one sub-symbol is arranged between each main symbol. . In the lower pattern row Z3, 9 kinds of main symbols "1" to "9" are arranged in ascending numerical order, and one sub-symbol is arranged between each main symbol.

That is, the upper symbol row Z1 and the lower symbol row Z3 are composed of 18 symbols. On the other hand, in the middle symbol row Z2, nine types of main symbols "1" to "9" are arranged in ascending order of numbers, and between the main symbol "9" and the main symbol "1" A main symbol of "4" is additionally arranged in the upper part, and one sub-symbol is arranged between each of these main symbols. In other words, only the middle pattern row Z2 is composed of 20 symbols with 10 main symbols arranged. On the display surface 41a, the symbols of each of the symbol rows Z1 to Z3 are variably displayed so as to scroll in a predetermined direction with periodicity.

As shown in FIG. 5(b), the display surface 41a is designed to stop-display three symbols for each row of symbols. It's like In addition, as shown in FIG. 5A, the display surface 41a is provided with five effective lines, that is, a left line L1, a middle line L2, a right line L3, a downward-sloping line L4, and an upward-sloping line L5. .

When the symbols are varied and displayed on the display surface 41a based on the winning of the first operation port 33 or the second operation port 34, the symbols of each of the symbol rows Z1 to Z3 are periodically scrolled in a predetermined direction. The variable display starts like this. Then, the variable display is switched to the standby display in the order of upper pattern row Z1→lower pattern row Z3→middle pattern row Z2, and finally, predetermined symbols are displayed still in each of the pattern rows Z1 to Z3, and the display is finished. . In addition, when the fluctuation display of the pattern ends, if the result of the internal lottery is a 4R high probability big hit result, which will be described later, the same even numbered pattern combination is formed on any of the effective lines, and the 8R high probability big hit result is formed. In some cases, a combination of identical odd-numbered symbols other than the "7" symbol is formed, and in the case of a 16R high-probability jackpot result, a combination of "7" symbols is formed. Further, when the result of the internal lottery is a small winning result, which will be described later, a predetermined symbol combination (for example, "3, 4, 1") is formed on any of the activated lines.

In addition, based on the winning of any of the operation ports 33, 34, the display is started at any of the special figure display units 37a, 37b and the symbol display device 41, and until the predetermined result is displayed and terminated corresponds to one game round. In addition, the pattern display device 41 may arbitrarily display the patterns in any manner without being limited to the above. can be changed as appropriate. Also, the patterns displayed variably on the pattern display device 41 are not limited to the above-described patterns, and for example, only numbers may be variably displayed as the patterns.

When a big win or a small win is won in a winning lottery based on the winning to the first operating port 33, the operation shifts to an opening/closing execution mode in which a prize to the special electric prize winning device 32 is possible. Similarly, when a big win or a small win is won in the winning lottery based on the winning to the second operation port 34, the operation shifts to the opening/closing execution mode in which the prize to the special electric prize winning device 32 is possible.

Returning to the description of FIG. 3, the special electric prize winning device 32 includes a large prize winning opening (not shown) leading to the back side of the game board 24, and an opening/closing door 32a for opening and closing the big winning opening. The opening/closing door 32a is arranged in either a closed state or an open state. Specifically, the opening/closing door 32a is normally in a closed state in which game balls cannot win prizes, and is switched to an open state in which game balls can win prizes in the event that the internal lottery wins the transition to the opening/closing execution mode. It has become. Incidentally, the open/close execution mode is a mode to be shifted to when a winning result is obtained. It should be noted that although it is not impossible to win a prize in the closed state, it may be configured to be in a state in which it is more difficult to win a prize than in the open state.

The round display portion 39 displays the number of round games that occur in the opening/closing execution mode. Here, the opening/closing execution mode includes a round number regulation mode that occurs when a big win is won and an opening/closing number regulation mode that occurs when a small win is won. The round number regulation mode is an opening/closing execution mode executed with a predetermined number of round games as an upper limit. A round game is a game that continues until either a predetermined upper limit duration time elapses or a predetermined upper limit number of game balls wins a special electric prize winning device 32 is satisfied. That is. The number of round games executed in the round number regulation mode differs according to the type of the jackpot result that triggered the shift. In the round display section 39, the number of times of the round game is displayed or a display corresponding thereto is made. The display on the round display section 39 is started when the opening/closing execution mode is started, and is ended when the opening/closing execution mode is terminated and a new game cycle is started. On the other hand, in the opening/closing number regulation mode, no round game is set, the opening/closing number of times of the special electric prize winning device 32 is the upper limit, and a predetermined upper limit number of game balls wins the special electric prize winning device 32. is terminated when one of the conditions is satisfied. In the opening/closing number regulation mode, the round display portion 39 is maintained in a non-display state.

FIG. 6 is an explanatory diagram for explaining a configuration relating to discharge of game balls that have flowed down the game area PA.

As already explained, a game ball entering any one of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34 and the out opening 24a is discharged from the game area PA. In other words, the game ball launched from the game ball launching mechanism 27 and flowed into the game area PA is any of the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34 and the out port 24a It will be discharged from the game area PA by entering the ball into. A game ball entering any one of the general prize winning port 31, the special electric prize winning device 32, the first operating port 33, the second operating port 34 and the out port 24a is led to the back side of the game board 24.例文帳に追加

On the back surface of the game board 24, discharge passage portions 42 to 48 are formed corresponding to the general prize winning port 31, the special electric prize winning device 32, the first operating port 33, the second operating port 34 and the out port 24a, respectively. . The game balls that have flowed into the discharge passages 42 to 48 are led to the lower end of the game board 24 on the back side of the game board 24 by flowing down the discharge passages 42 to 48 into which they have flowed, and are led to the discharged ball recovery section (not shown). is recovered. Then, the game balls collected by the discharge ball collecting section are discharged to the ball circulation device of the island facility where the pachinko machine 10 is installed in the game hall.

Various detection sensors 42a to 48a for detecting game balls are provided in the discharge passages 42 to 48, respectively. These discharge passage portions 42 to 48 and detection sensors 42a to 48a will be described below. Since four general prize winning openings 31 are provided as already explained, there are discharge passage portions 42 to 44 corresponding to each of these four openings. In this case, one detection sensor 42a is provided for each of the first discharge passage portion 42 corresponding to the leftmost general prize winning port 31 and the second discharge passage portion 43 corresponding to the general prize winning port 31 adjacent thereto. 43a is provided. Specifically, the first winning opening detection sensor 42a is provided so that the detection range exists in the middle of the first discharge passage portion 42, and the detection range is in the middle of the second discharge passage portion 43. A second winning hole detection sensor 43a is provided so as to exist. The game ball entering the leftmost general winning hole 31 is detected by the first winning hole detection sensor 42a while passing through the first discharge passage part 42, and enters the general winning hole 31 on the right side. The ball is detected by the second winning opening detection sensor 43a while passing through the second discharge passage portion 43. FIG. In addition, a third discharge passage portion 44 is formed so as to join the two general prize winning openings 31 on the right side at a midway position. The third discharge passage portion 44 has an entrance side area corresponding to each of the two general winning openings 31, and has one exit side area by joining the entrance side areas in the middle. are doing. A third winning opening detection sensor 44a is provided so that a detection range exists in the middle of the exit side area of the third discharge passage portion 44 . A game ball that enters one of the two right-side general winning holes 31 is detected by the third winning hole detection sensor 44a while passing through the third discharge passage portion 44. - 特許庁

A fourth discharge passage portion 45 exists corresponding to the special electric prize winning device 32 . A special electric detection sensor 45a is provided so that a detection range exists in the middle of the fourth discharge passage portion 45, and the game ball entering the special electric prize winning device 32 passes through the fourth discharge passage portion 45. It is detected by the special electric detection sensor 45a. A fifth discharge passage portion 46 exists corresponding to the first operation port 33 . A first operation opening detection sensor 46a is provided so that a detection range exists in the middle of the fifth discharge passage portion 46, and the game ball entering the first operation opening 33 passes through the fifth discharge passage portion 46. It is detected by the first operation port detection sensor 46a while passing through. A sixth discharge passage portion 47 exists corresponding to the second operation port 34 . A second operation opening detection sensor 47a is provided so that a detection range exists in the middle of the sixth discharge passage portion 47, and the game ball entering the second operation opening 34 passes through the sixth discharge passage portion 47. It is detected by the second operation opening detection sensor 47a while it is passing through. A seventh discharge passage portion 48 is present corresponding to the out port 24a. An out-port detection sensor 48a is provided so that a detection range exists in the middle of the seventh discharge passage portion 48, and the game ball entering the out port 24a passes through the seventh discharge passage portion 48. It is detected by the outlet detection sensor 48a.

A game ball that is detected by any one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and the game ball passing through the through gate 35 on the way down the game area PA is detected by the gate detection sensor 49a.

Electromagnetic induction type proximity sensors are used as the various detection sensors 42a to 49a, but any sensor can be used as long as the game balls can be detected individually. Further, the various detection sensors 42a-49a are electrically connected to a main controller 60 which will be described later, and detection results of the various detection sensors 42a-49a are output to the main controller 60. FIG. Specifically, the various detection sensors 42a to 49a output a HI state signal when no game ball is detected, and output a LOW state signal when a game ball is detected. It should be noted that the various detection sensors 42a-49a may be configured to output a LOW state signal when the game ball is not detected, and output a HI state signal when the game ball is detected.

As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front side of the inner frame 13 in which the game board 24 having the above configuration is attached to the resin base 21 . As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 through which substantially the entire game area PA can be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted therein. The window panel 52 is made of glass in a colorless and transparent manner, but is not limited to this, and may be made of a synthetic resin in a colorless and transparent manner. As long as it is visible, it may be colored and transparent.

A display light-emitting portion 53 is provided above the window portion 51 . A pair of left and right speaker units 54 are provided for outputting sound effects and the like according to the game state. An upper bulging portion 55 and a lower bulging portion 56 that bulge forward are vertically arranged below the window portion 51 . An upper plate 55a that opens upward is provided inside the upper bulging portion 55, and a lower plate 56a that likewise opens upward is provided inside the lower bulging portion 56. As shown in FIG. The upper tray 55a has a function of temporarily storing game balls paid out from a payout device, which will be described later, and guiding them toward the game ball launching mechanism 27 while aligning them in a line. In addition, the lower tray 56a has a function of storing surplus game balls in the upper tray 55a.

Next, the configuration of the rear side of the gaming machine main body 12 will be described.

As shown in FIG. 2, a main control device 60 is mounted on the back surface of the inner frame 13 (specifically, the game board 24) for main control of the game. FIG. 7 is a front view of the main controller 60. FIG. As shown in FIG. 7, the main controller 60 has a main control board 61 housed in a board box 60a.

A main side MPU 62 is mounted on the element mounting surface which is one plate surface of the main control board 61 . The board box 60a is formed transparent so that the main side MPU 62 accommodated in the board box 60a can be visually observed from the outside of the board box 60a. Although the substrate box 60a is made transparent and colorless, it may be made transparent and colored so long as the main MPU 62 accommodated in the substrate box 60a can be visually observed from the outside of the substrate box 60a. good. The main control device 60 is mounted on the back surface of the resin base 21 in the board box 60a such that the facing wall portion 60b facing the element mounting surface of the main control board 61 faces the pachinko machine 10 rearward. Therefore, by opening the game machine main body 12 to the front of the pachinko machine 10 with respect to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually see the opposing wall portion 60b of the board box 60a and It is possible to see the main MPU 62 through the opposing wall portion 60b.

The board box 60a is formed by assembling a plurality of case bodies 60c back and forth. A coupling portion 60e is provided for leaving the . A plurality of coupling portions 60e are arranged side by side on one side of the substantially rectangular parallelepiped board box 60a. As a result, in a state in which separation of the case body 60c is prevented by using some of the joint portions 60e, even if the case body 60c is separated by destroying the part of the joint portions 60e, another joint may be performed after that. By bringing the portion 60e into the coupled state, it becomes possible to prevent the separation of the case body 60c again. In addition, since the connecting portion 60e is destroyed and a trace remains when the case body 60c is separated, it is possible to grasp whether or not the case body 60c is illegally separated by visually checking the connecting portion 60e. It becomes possible. In addition, a sealing seal 60f is attached to one side of the board box 60a opposite to the one side on which the coupling portions 60e are arranged so as to straddle the boundary between the case bodies 60c. When the sealing seal 60f is peeled off, the adhesive layer remains on the case body 60c. As a result, when the sealing seal 60f is peeled off when the case body 60c is separated, it is possible to leave a trace.

In the main control device 60 having the above configuration, the main control board 61 is owned by the manager of the game hall in order to generate an opportunity to change the setting state of the pachinko machine 10 within the range of "setting 1" to "setting 6". A setting key insertion unit 68a into which a setting key is inserted and turned ON, an update button 68b operated to sequentially change the setting state of the pachinko machine 10 after the ON operation to the setting key insertion unit 68a, and a main control unit. A reset button 68c operated to clear data in a main side RAM 65, which is provided in the main side MPU 62 of 60 and will be described later, and first to third notification display devices 69a to notify the management results of the game history. 69c and are provided. Incidentally, the setting state of the pachinko machine 10 is not limited to the six stages of "setting 1" to "setting 6", and any number of stages may be used.

These setting key insertion portion 68a, update button 68b, reset button 68c, and first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. FIG. The device mounting surface of the main control board 61 faces the opposite wall portion 60b of the board box 60a as already described, but the setting key insertion portion 68a, the update button 68b and the reset button 68c are covered by the opposite wall portion 60b. not That is, the opposed wall portion 60b has individual openings in areas opposed to the setting key insertion portion 68a, the update button 68b, and the reset button 68c. As a result, the setting key can be inserted into the setting key insertion portion 68a without opening the board box 60a, the update button 68b can be pressed, and the reset button 68c can be pressed. Is possible.

By inserting the setting key into the setting key inserting portion 68a and rotating it in a predetermined direction, the setting key inserting portion 68a is turned on. By starting the supply of operating power to the pachinko machine 10 in that state (that is, by starting the supply of operating power to the main side MPU 62 of the main controller 60), the setting state of the pachinko machine 10 is changed. becomes a modifiable state in which In this state, each time the update button 68b is pressed once, the setting state of the pachinko machine 10 is changed step by step in the range of "setting 1" to "setting 6" in ascending order. When the update button 68b is operated in the state of "setting 6", the state is updated to "setting 1". The setting key insertion portion 68a is turned off by rotating the setting key inserted in the setting key insertion portion 68a from the ON operation position in a direction opposite to the predetermined direction to return to the initial position. Become. When the setting key insertion portion 68a is turned off, the changeable state ends, and the game can be played with the set values at that time. In other words, even if the update button 68b is operated after the changeable state ends, the setting value cannot be changed.

The ON operation for the setting key insertion portion 68a is valid only when the supply of operating power to the pachinko machine 10 is started (that is, when the supply of operating power to the main side MPU 62 of the main controller 60 is started). Therefore, even if the setting key insertion portion 68a is turned ON after the main MPU 62 of the main controller 60 has completed the operation power supply start process, the setting value cannot be changed.

The setting state of the pachinko machine 10 determines the advantage per unit time in the pachinko machine 10, and the larger the value of "setting a" (a is an integer from "1" to "6") (that is, the setting The higher the value, the higher the advantage. Although the details will be described later, there are a low probability mode in which the winning probability is relatively low and a high probability mode in which the winning probability is relatively high as a winning lottery mode that determines the winning probability of the jackpot result, and the set value is It is set so that the higher the value, the higher the winning probability of the jackpot result in the low-probability mode. On the other hand, the winning probability of the jackpot result in the high probability mode is constant regardless of the setting value.

The reset button 68c is operated to clear the data in the main RAM 65 as described above, but in order to clear the data, the operating power is supplied to the pachinko machine 10 while the reset button 68c is pressed. (that is, it is necessary to start supplying operating power to the main MPU 62 of the main controller 60). The ON operation for the reset button 68c is valid only when the supply of operating power to the pachinko machine 10 is started (that is, when the supply of operating power to the main side MPU 62 of the main controller 60 is started). Therefore, even if the reset button 68c is pressed after the main MPU 62 of the main controller 60 completes the operation power supply start process, the data in the main RAM 65 cannot be cleared.

Each of the first to third notification display devices 69a to 69c is a segment display device in which seven LED display segments are arranged. It may be a light emitter, a liquid crystal display device, or an organic EL display. Each of the first to third notification display devices 69a to 69c is installed so that its display surface faces the direction in which the element mounting surface of the main control board 61 faces. covered. In this case, since the substrate box 60a is transparent, the display surfaces of the first to third notification display devices 69a to 69c housed in the substrate box 60a can be viewed from the outside of the substrate box 60a. becomes possible. As already explained, the main controller 60 is mounted on the rear surface of the resin base 21 in the substrate box 60a so that the facing wall portion 60b facing the element mounting surface of the main control substrate 61 faces the rear of the pachinko machine 10. Therefore, when the game machine main body 12 is opened to the front of the pachinko machine 10 with respect to the outer frame 11 and the back surface of the resin base 21 is exposed to the front of the pachinko machine 10, the first to third notifications are made through the opposing wall portion 60b. It is possible to view the display surfaces of the display devices 69a to 69c.

On the display surfaces of the first to third notification display devices 69a to 69c, not only numbers "0" to "9" but also various characters including alphabetic characters are displayed. The management result of the game history is notified using the first to third notification display devices 69a to 69c. In the changeable state in which the setting state of the pachinko machine 10 can be changed, the value corresponding to the current setting value is displayed on the third notification display device 69c. The value corresponding to the set value may be displayed on the first notification display device 69a, or may be displayed on the second notification display device 69b. In addition, the setting value before entering the changeable state is displayed on one of the first to third notification display devices 69a to 69c, and the current setting value is displayed on the first to third notification display devices. It is also possible to adopt a configuration in which the information is displayed on another notification display device out of the display devices 69a to 69c.

As shown in FIG. 2, the back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main controller 60 . The back pack unit 15 includes a back pack 72 made of a transparent synthetic resin, and a payout mechanism 73 and a controller assembly unit 74 are attached to the back pack 72 .

The payout mechanism part 73 includes a tank 75 to which game balls supplied from the island facilities of the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75 . The game balls paid out from the payout device 76 are discharged to the upper tray 55a or the lower tray 56a through a payout passage provided on the downstream side of the payout device 76.例文帳に追加The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power on and off.

The control device assembly unit 74 includes a payout control device 77 having a function of controlling a payout device 76, and a predetermined electric power required by various control devices, etc., is generated and output, and is accompanied by the operation of the shooting operation device 28 by the player. A power supply/shooting control device 78 for controlling the launching of game balls is provided. The payout control device 77 and the power supply/launch control device 78 are arranged one on top of the other in such a manner that the payout control device 77 is behind the pachinko machine 10 .

The back pack 72 is provided with an external terminal plate 79 in addition to the payout mechanism section 73 and the controller assembly unit 74 . The external terminal plate 79 is installed on the back of the pachinko machine 10 at the upper corner portion on the rotation base end side of the back pack unit 15 . The external terminal board 79 is a board for outputting a predetermined signal in order to make the management computer of the game hall recognize the state of the pachinko machine 10, and inputting a predetermined signal from the management computer of the game hall to the pachinko machine 10. is. The management computer receives various information from the main controller 60 and the payout controller 77 through the external terminal board 79 .

<Electrical Configuration of Pachinko Machine 10>
FIG. 8 is a block diagram showing the electrical configuration of the pachinko machine 10. As shown in FIG.

The main control device 60 includes a main control board 61 that controls the main game, and a power outage monitoring board 67 that monitors the power supply. A main side MPU 62 is mounted on the main control board 61 . The main MPU 62 incorporates a main ROM 64 and a main RAM 65 in addition to a main CPU 63 which is an arithmetic processing device including a control section and a calculation section. In addition, the main MPU 62 includes a first transmission circuit 101 for transmitting commands to the sound emission control device 90, a second transmission circuit 102 for transmitting commands to the payout control device 77, and a payout control device 77. A receiving circuit 103 for receiving commands from the control device 77 is incorporated. In addition to the elements described above, the main MPU 62 incorporates an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits as a random number generator, and the like.

The main ROM 64 is a memory such as a NOR flash memory and a NAND flash memory that does not require external power supply (that is, non-volatile storage means), and is used exclusively for reading. The main ROM 64 stores various control programs executed by the main CPU 63 and fixed value data.

The main RAM 65 is a memory (that is, volatile storage means) such as SRAM and DRAM that requires power supply from the outside to retain data, and is used for both reading and writing. The main RAM 65 can be randomly accessed, and has a faster read time than the main ROM 64 when compared with the same data capacity. The main RAM 65 temporarily stores various data for execution of the control program stored in the main ROM 64 .

An input side of the main side MPU 62 is connected with a power failure monitoring board 67 and a payout control device 77 provided in the main control device 60 . A power supply/emission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 67 , and operating power is supplied to the main MPU 62 via the power failure monitoring board 67 . A command transmitted from the payout control device 77 to the main side CPU 63 is received by the receiving circuit 103 .

The input side of the main side MPU 62 is connected to various sensors such as the ball entry detection sensors 42a to 49a. As already described, the respective ball entry detection sensors 42a to 49a include the first winning opening detection sensor 42a, the second winning opening detection sensor 43a, the third winning opening detection sensor 44a, the special electric detection sensor 45a, and the first operation opening detection. A sensor 46a, a second working opening detection sensor 47a, an outlet detection sensor 48a and a gate detection sensor 49a are included. Based on the detection results of these ball-entering detection sensors 42a to 49a, the main CPU 63 determines whether a ball is entering each ball-entering section. Further, in the main CPU 63, various lotteries are executed based on the winning of the first operation port 33, and various lotteries are executed based on the winning of the second operation port 34.

A setting key insertion portion 68a, an update button 68b, and a reset button 68c provided on the main control board 61 are provided on the input side of the main MPU 62 . A sensor (not shown) is provided in the setting key inserting portion 68a, and the sensor detects whether the setting key inserting portion 68a is arranged at the ON operation position or the OFF operation position. Based on the detection result from the sensor, the main CPU 63 identifies whether the setting key insertion portion 68a is located at the position for the ON operation or the position for the OFF operation. The update button 68b is provided with a sensor (not shown), and the sensor detects whether or not the update button 68b is pressed. Then, the main CPU 63 determines whether or not the update button 68b is pressed based on the detection result from the sensor. A sensor (not shown) is provided on the reset button 68c, and the sensor detects whether or not the reset button 68c is pressed. Then, the main CPU 63 determines whether or not the reset button 68c is pressed based on the detection result from the sensor.

A power failure monitoring board 67, a payout control device 77, and an audio emission control device 90 are connected to the output side of the main MPU 62. FIG. A prize ball command is transmitted to the payout control device 77 based on, for example, that a game ball has entered a prize ball corresponding ball entry portion among the ball entry portions where the occurrence of the ball entry corresponds to the payout of the game ball. be. The main CPU 63 sets a command to be transmitted to the payout control device 77 in the second transmission circuit 102 , and the second transmission circuit 102 transmits the set command to the payout control device 77 . Various commands such as a normal return command, a partial clear return command, a variation command, a type command, and an opening command, which will be described later, are transmitted to the sound emission control device 90 . The main CPU 63 sets a command to be transmitted to the sound emission control device 90 in the first transmission circuit 101 , and the first transmission circuit 101 transmits the set command to the sound emission control device 90 .

On the output side of the main MPU 62, there are a drive unit 32b for special electric that opens and closes the open/close door 32a of the special electric prize winning device 32, and a drive unit 34b for general electric that opens and closes the general electric accessory 34a of the second operation opening 34. , a special figure unit 37 and a general figure unit 38 are connected. Incidentally, the special figure unit 37 is provided with a first special figure display portion 37a, a second special figure display portion 37b, a first special figure reservation display portion 37c and a second special figure reservation display portion 37d. are all connected to the output side of the main MPU 62 . Similarly, the normal map unit 38 is provided with a normal map display unit 38 a and a normal map reservation display unit 38 b , but all of these are connected to the output side of the main MPU 62 . Various driver circuits are provided on the main control board 61, and the main side MPU 62 executes drive control of various drive units and various display units through the driver circuits.

In other words, in the opening/closing execution mode, the driving control of the special electric driving unit 32b is executed in the main CPU 63 so that the special electric winning device 32 is opened and closed. Further, when the general electric accessory 34a is won in the open state, the main side CPU 63 executes drive control of the general electric drive unit 34b so that the general electric accessory 34a is opened and closed. In addition, display control of the first special figure display portion 37a or the second special figure display portion 37b is executed in the main side CPU 63 at each game round. In addition, when indicating the lottery result of whether or not to open the general electric accessory 34a, the main side CPU 63 controls the display of the general pattern display unit 38a. Further, when the winning to the first operation port 33 occurs, or when the variable display is started in the first special figure display unit 37a, the display control of the first special figure reservation display unit 37c is executed in the main side CPU 63 Then, when the winning to the second operation port 34 occurs, or when the variable display is started in the second special figure display part 37b, the display control of the second special figure reservation display part 37d is executed in the main side CPU 63 Then, when a winning to the through gate 35 occurs, or when the variable display is started in the normal pattern display unit 38a, the main CPU 63 controls the display of the normal pattern reservation display unit 38b.

The output side of the main MPU 62 is connected to first to third notification display devices 69a to 69c. The game history management results are reported through displays on the first to third reporting display devices 69a to 69c. Further, when changing the setting state of the pachinko machine 10, the current setting value is displayed on the third notification display device 69c. The main side CPU 63 controls the display of these first to third notification display devices 69a to 69c.

The blackout monitoring board 67 relays between the main control board 61 and the power supply/launch control device 78 and monitors the maximum voltage output from the power supply/launch control device 78, which is a stable DC voltage of 24 volts. The payout control device 77 controls the payout of prize balls and rental balls by the payout device 76 based on the prize ball command received from the main controller 60 .

The power/emission control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power supply, the main control board 61, the payout control device 77, etc. are generated with the necessary operating power, and the generated operating power is supplied. Incidentally, the power supply/launch control device 78 is provided with a power supply unit for power failure such as a backup capacitor, and even if the power supply of the pachinko machine 10 is in the OFF state, the power supply unit for power failure is used as the main power supply. Electric power for memory retention is supplied to the main side RAM 65 and the payout control device 77 of the control device 60 . The power/shooting control device 78 is responsible for controlling the shooting of the game ball shooting mechanism 27, and the game ball shooting mechanism 27 is driven when predetermined shooting conditions are met. In addition, as already explained, the payout mechanism unit 73 is provided with a power switch, and when the power switch is turned ON, the supply of operating power to the pachinko machine 10 is started, and the power switch is turned OFF. , the supply of operating power to the pachinko machine 10 is stopped.

Next, the payout control device 77 will be described.

The payout control device 77 includes a payout control board 81 for controlling the payout of game balls. A payout side MPU 82 is mounted on the payout control board 81 . The payout side MPU 82 incorporates a payout side ROM 84 and a payout side RAM 85 in addition to a payout side CPU 83 which is an arithmetic processing device including a control section and a calculation section. Also, the payout side MPU 82 incorporates a payout side transmission circuit 86 for sending commands to the main side CPU 63 and a payout side reception circuit 87 for receiving commands sent from the main side CPU 63 . In addition to the elements described above, the payout side MPU 82 incorporates an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits as a random number generator, and the like.

The payout-side ROM 84 is a memory (that is, a non-volatile storage means) that does not require power supply from the outside to retain memory, such as a NOR flash memory and a NAND flash memory, and is used exclusively for reading. The payout side ROM 84 stores various control programs and fixed value data executed by the payout side CPU 83 .

The payout side RAM 85 is a memory (that is, volatile storage means) such as SRAM and DRAM that requires power supply from the outside for memory retention, and is used for both reading and writing. The payout-side RAM 85 can be randomly accessed, and takes a shorter time to read than the payout-side ROM 84 when compared with the same data capacity. The payout side RAM 85 temporarily stores various data for execution of the control program stored in the payout side ROM 84 .

Next, the sound emission control device 90 will be described.

The sound emission control device 90 drives and controls the display light emitting portion 53 and the speaker portion 54 provided on the front door frame 14 based on various commands received from the main control device 60, and controls the display control device 89. is. The display control device 89 executes display control of the pattern display device 41 based on the command received from the sound emission control device 90 .

The sound emission control device 90 has a sound emission control board 91 that controls the performance. A sound and light side MPU 92 is mounted on the sound emission control board 91 . The sound and light side MPU 92 incorporates a sound and light side ROM 94 and a sound and light side RAM 95 in addition to a sound and light side CPU 93 which is an arithmetic processing device including a control section and a calculation section. Further, the sound and light side MPU 92 incorporates a sound and light side receiving circuit 96 for receiving commands transmitted from the main side CPU 63 . In addition to the elements described above, the sound and light side MPU 92 incorporates an interrupt circuit, a timer circuit, a data input/output circuit, various counter circuits as a random number generator, and the like.

The sound and light side ROM 94 is a memory (that is, a non-volatile storage means) that does not require power supply from the outside to retain data such as a NOR flash memory and a NAND flash memory, and is used exclusively for reading. The sound and light side ROM 94 stores various control programs and fixed value data executed by the sound and light side CPU 93 .

The sound and light side RAM 95 is a memory (that is, volatile storage means) such as SRAM and DRAM that requires power supply from the outside to hold data, and is used for both reading and writing. The RAM 95 on the sound and light side can be randomly accessed, and has a shorter time required for reading than the ROM 94 on the sound and light side when compared with the same data capacity. The sound and light side RAM 95 temporarily stores various data for execution of the control program stored in the sound and light side ROM 94 .

Next, the configuration of the main MPU 62 will be described.

FIG. 9 is an explanatory diagram for explaining the configuration of the main MPU 62. As shown in FIG. As shown in FIG. 9, the main MPU 62 includes W register 104a, A register 104b, B register 105a, C register 105b, D register 106a, E register 106b, H register 107a and L register 107b as general purpose registers. there is These eight general purpose registers are 1-byte registers. These general-purpose registers can also be used as pair registers by combining two corresponding general-purpose registers. Specifically, the W register 104a and A register 104b can be combined to be used as a 2-byte WA register 104, and the B register 105a and C register 105b can be combined to be used as a 2-byte BC register 105. be able to. The D register 106a and E register 106b can be combined to be used as a 2-byte DE register 106, and the H register 107a and L register 107b can be combined to be used as a 2-byte HL register 107. .

The main MPU 62 has an IX register 108 and an IY register 109 as index registers. These two index registers are two byte registers. The main MPU 62 also has a 2-byte TP register 111 . The TP register 111 stores "9000H" as the reference address of the data table which is used as the reference when specifying the address of the data table. Although the details will be described later, the reference address of the data table is the head address of the area in which various data tables are stored in the main ROM 64 . The reference address of the data table stored in the TP register 111 is used to reduce the data capacity of the data for specifying the address of the data table. The details of addressing of the data table using the reference address stored in the TP register 111 will be described later.

The main MPU 62 has a 1-byte flag register, and a zero flag ZF is set to 1 bit in the flag register. The zero flag ZF is a flag to which "1" is set when the operation result is "0". A carry flag, a P/V flag, a sign flag and a half carry flag are also set in the flag register. The information of these flags set in the flag register changes according to the execution results of operation instructions, rotate instructions, input/output instructions, and the like.

<Specific control and non-specific control>
The main CPU 63 performs various controls by distinguishing between specific control and non-specific control. Specifically, control related to game history management is defined as non-specific control, and control other than non-specific control, including control for progressing a game based on game operations by the player, is defined as specific control.

Regarding the specific control in detail, all the control by the main process (FIG. 15) executed when the supply of operating power to the main CPU 63 is started is included in the specific control. In a state in which interrupts by timer interrupt processing are permitted, timer interrupt processing is periodically executed so as to interrupt the main processing (FIG. 15). All the processes other than the management process (step S518) are included in the specific control. Part of management processing is also included in specific control.

FIG. 10(a) is an explanatory diagram for explaining how various areas are set in the main RAM 65. As shown in FIG. As shown in FIG. 10(a), the main RAM 65 is assigned addresses from "0000H" to "04B2H". A 1-byte area (hereinafter also referred to as a 1-byte area) is set for each address in the main RAM 65 . In this specification, "H" attached after a numerical value is a symbol indicating that the numerical value is expressed in hexadecimal.

In correspondence with the fact that the control executed by the main side CPU 63 is distinguished between specific control and non-specific control, the address range of the work area 121 for specific control and the address range for non-specific control in the main side RAM 65 The address range of the work area 122, the address range of the stack area 123 for specific control, and the address range of the stack area 124 for non-specific control are clearly distinguished.

Specifically, an area of consecutive addresses in the address range from "0000H" to "02FFH" is set as the work area 121 for specific control. In addition, "0300H" to "0302H" which are continuous in the address range of "0000H" to "02FFH" are addresses of unused areas, followed by continuous addresses in the address range of "0303H" to "03FFH". A work area 122 for non-specific control is set for each address to be used. In addition, the address range of ``0400H'' to ``0402H'', which is continuous with the address range of ``0303H'' to ``03FFH'', is the address of an unused area. An area of consecutive addresses in the range is set as a stack area 123 for specific control. In addition, the address range of ``0450H'' to ``0452H'', which is continuous with the address range of ``0403H'' to ``044FH'', is the address of an unused area. An area of consecutive addresses in the range is set as a stack area 124 for non-specific control. The relationship between each area and address as described above is set in both the physical address in the main RAM 65 and the logical address on the memory map recognized by the main CPU 63 .

Since the work area 121 for specific control and the work area 122 for non-specific control are separately set as described above, when the main CPU 63 executes the specific control and when the non-specific control is executed, Therefore, different areas of the main RAM 65 are used when executing various calculations. As a result, when one of the specific control and the non-specific control is executed, it is possible to make it difficult to cause an event in which necessary information in the main RAM 65 is erased in the other.

Since the stack area 123 for specific control and the stack area 124 for non-specific control are set separately, the main CPU 63 can determine whether the main CPU 63 executes the specific control or the non-specific control. Different areas of the main RAM 65 are used when saving the information stored in the register of the side CPU 63 and when storing the information of the return address on the program. As a result, when one of the specific control and the non-specific control is executed, when saving the information stored in the register of the main side CPU 63 and when storing the information of the return address on the program, the other can be used. It is possible to make it difficult to cause an event such as the information to be deleted to be erased. Incidentally, when writing information to the stack areas 123 and 124, the main CPU 63 issues a push instruction, and when reading information from the stack areas 123 and 124, the main CPU 63 issues a pop instruction. When reading information from the respective stack areas 123 and 124, the information written later in the order of writing to the stack areas 123 and 124 is read first.

Here, when the main CPU 63 executes a process corresponding to the specific control, the main CPU 63 can write information to the work area 121 for specific control and the stack area 123 for specific control. Information can be read from the work area 121 for specific control and the stack area 123 for specific control. On the other hand, when the main CPU 63 executes processing corresponding to specific control, the main CPU 63 can read information from the work area 122 for non-specific control and the stack area 124 for non-specific control. , the work area 122 for non-specific control and the stack area 124 for non-specific control cannot be written. This makes it possible to prevent the information used in the process corresponding to the non-specific control from being erroneously deleted while the process corresponding to the specific control is being executed.

When the main CPU 63 executes processing corresponding to non-specific control, the main CPU 63 can write information to the work area 122 for non-specific control and the stack area 124 for non-specific control. In addition, information can be read from the work area 122 for non-specific control and the stack area 124 for non-specific control. On the other hand, when the main CPU 63 executes processing corresponding to non-specific control, although the main CPU 63 can read information from the work area 121 for specific control and the stack area 123 for specific control, Information cannot be written to the work area 121 for specific control and the stack area 123 for specific control. This makes it possible to prevent the information used in the process corresponding to the specific control from being erroneously deleted in a situation where the process corresponding to the non-specific control is being executed.

Although backup power is supplied to the main RAM 65 even after the pachinko machine 10 is powered off, the backup power includes the work area 121 for specific control, the work area 122 for non-specific control, and the work area 122 for non-specific control. and the stack area 124 for non-specific control. As a result, the information stored in the work area 121 for specific control, the work area 122 for non-specific control, the stack area 123 for specific control, and the stack area 124 for non-specific control is stored in the pachinko machine 10 when the power is turned off. Even afterward, the memory is retained while the backup power is being supplied.

FIG. 10(b) is an explanatory diagram for explaining how data and programs are set in the main ROM 64. As shown in FIG. As shown in FIG. 10(b), the main ROM 64 is assigned addresses of "9000H" to "9EFFH". A 1-byte area (1-byte area) is set for each address in the main-side ROM 64 .

In correspondence with the fact that the control executed by the main CPU 63 is classified into specific control and non-specific control, the main ROM 64 also contains data for specific control, a program for specific control, and a program for non-specific control. The addresses of the areas where the data and non-specific control programs are stored are clearly distinguished.

Specifically, data for specific control is collectively stored in areas of consecutive addresses in the address range of "9000H" to "94FFH". Further, the address range of "9500H" to "9502H" which is continuous with the address range of "9000H" to "94FFH" is the address of an unused area in which no data is stored, followed by "9503H". A specific control program is collectively stored in an area of each consecutive address in the address range of .about.98FFH. In addition, the address range of "9900H" to "9902H" which is continuous with the address range of "9503H" to "98FFH" is the address of an unused area in which no data is stored, followed by "9903H". Data for non-specific control are collectively stored in areas of consecutive addresses in the address range of .about.9BFFH. Further, the address range of "9C00H" to "9C02H" which is continuous with the address range of "9903H" to "9BFFH" is the address of an unused area in which data is not stored, followed by "9C03". A program for non-specific control is collectively stored in an area of each consecutive address in the address range of .about.9EFFH. The relationship between data, programs, and addresses as described above is set in both physical addresses in the main ROM 64 and logical addresses on the memory map recognized by the main CPU 63 .

As described above, the specific control data and specific control program, and the non-specific control data and non-specific control program, regardless of the execution order of the processes for executing the corresponding controls, Since they are stored in areas with different ranges of addresses, for example, when only specific control data and specific control programs are to be checked, the addresses where these specific control data and specific control programs are stored are stored. It is sufficient to check only the area of the range. For example, when checking only non-specific control data and non-specific control programs, the addresses where these non-specific control data and non-specific control programs are stored are checked. Only the area of coverage needs to be checked. Therefore, it is possible to efficiently perform work when checking data and programs by distinguishing between specific control and non-specific control. Further, along with this, it becomes possible to efficiently perform the work in the case of correcting data and programs by distinguishing between specific control and non-specific control.

No data is stored between the address range of the area in which the data for specific control and the program for specific control are stored and the address range of the area in which the data for non-specific control and the program for non-specific control are stored. By setting the address range of the unused area, it becomes easier to grasp the boundary between the address range for specific control and the address range for non-specific control in the checking work.

In each of the address range for specific control and the address range for non-specific control, data and programs are stored in areas of different ranges of addresses, regardless of the execution order of processes for executing the corresponding control. As a result, it becomes possible to efficiently perform work when checking data and programs separately. In addition, since the address range of an unused area in which no data is stored is set between the address range of the area in which the data is stored and the address range of the area in which the program is stored, the data cannot be stored. It becomes easy to grasp the boundary between the address range and the address range of the program in the checking work.

<Electrical Configuration for Performing Various Lottery Draws by Main Side CPU 63>
Next, an electrical configuration for performing various lotteries by the main CPU 63 will be described with reference to FIG.

The main side CPU 63 uses various counter information during the game to set the winning lottery, the display setting of the first special figure display section 37a, the display setting of the second special figure display section 37b, and the design display setting of the design display device 41. , Display setting of the general pattern display unit 38a, etc. Specifically, as shown in FIG. a jackpot type counter C2, a reach random number counter C3 used for a reach generation lottery when the pattern display device 41 loses and fluctuates, a random number initial value counter C4 used for setting the initial value of the hit random number counter C1, and each special figure. The display units 37a, 37b and the variation type counter C5 for determining the display continuation time in the pattern display device 41 are used. Furthermore, a general electric random number counter C6 used for lottery determination as to whether or not the general electric accessory 34a of the second operating port 34 is to be in the electric open state is used. The counters C1 to C6 are provided in the lottery counter area 112 in the work area 121 for specific control.

Each of the counters C1 to C6 is a loop counter that adds 1 to the previous value each time it is updated and returns to 0 after reaching the maximum value. Each counter is updated at short intervals. Each numerical value information of the hit random number counter C1, the jackpot type counter C2 and the reach random number counter C3 is stored in the special figure reservation area 113 when the winning to the first operation opening 33 or the second operation opening 34 occurs. The special figure reservation area 113 includes a first special figure reservation area 115, a second special figure reservation area 116, and an execution area 117 for special figures.

The first special figure reservation area 115 includes a first area 115a, a second area 115b, a third area 115c and a fourth area 115d. Each numerical value information of the jackpot type counter C2 and the reach random number counter C3 is stored in one of the areas 115a to 115d as the reserved information on the special figure side.

In this case, in the first area 115a to the fourth area 115d, when the winning to the first operation opening 33 occurs a plurality of times in succession, the first area 115a→second area 115b→third area 115c→third area Each numerical value information is stored chronologically in the order of the 4 areas 115d. Since the four areas 115a to 115d are provided in this manner, up to four winning histories of game balls to the first operation opening 33 are reserved and stored.

In addition, the number that can be reserved and stored in the first special figure reservation area 115 is not limited to four and is arbitrary, and may be another plurality such as two, three, or five or more. , may be singular.

The second special figure reservation area 116 comprises a first area 116a, a second area 116b, a third area 116c and a fourth area 116d. Each numerical value information of the jackpot type counter C2 and the reach random number counter C3 is stored in one of the areas 116a to 116d as the reserved information on the special figure side.

In this case, in the first area 116a to the fourth area 116d, when the winning to the second operation opening 34 occurs multiple times in succession, the first area 116a→second area 116b→third area 116c→third area Each numerical value information is stored chronologically in the order of the 4 areas 116d. By providing four areas 116a to 116d in this manner, up to four winning histories of game balls to the second operation opening 34 can be reserved and stored.

In addition, the number that can be reserved and stored in the second special figure reservation area 116 is not limited to four and is arbitrary, and may be another plurality such as two, three, or five or more. , may be singular.

The execution area 117 for the special figure stores reservation information of the target for the determination of whether or not the special figure is determined and the distribution determination when the variable display is started in one of the special figure display units 37a and 37b. area. Specifically, when starting the variable display of the first special figure display unit 37a, the reservation information stored in the first area 115a of the first special figure reservation area 115 moves to the special figure execution area 117 be done. On the other hand, when starting the variable display of the 2nd special figure display part 37b, the reservation information stored in the 1st area 116a of the 2nd special figure reservation area 116 is moved to the execution area 117 for special figures.

The special figure reservation area 113 is provided with a first special figure reservation number counter 118 and a second special figure reservation number counter 119 . The first special figure reservation number counter 118 is a counter that enables the main side CPU 63 to grasp the number of reservation information stored in the first special figure reservation area 115, and the second special figure reservation number counter 119 , It is a counter that allows the main side CPU 63 to grasp the number of reservation information stored in the second special figure reservation area 116 . These special figure reservation number counters 118 and 119 consist of 1 byte, and these special figure reservation number counters 118 and 119 store any numerical information of "0" to "4".

The value of the first special figure reservation number counter 118 is incremented by 1 each time the reservation information is stored in the first special figure reservation area 115, and the reservation information stored in the first special figure reservation area 115 is When it is moved to the execution area 117 for a special figure, 1 is subtracted. The value of the second special figure reservation number counter 119 is incremented by 1 each time the reservation information is stored in the second special figure reservation area 116, and the reservation information stored in the second special figure reservation area 116 is When it is moved to the execution area 117 for a special figure, 1 is subtracted.

Information corresponding to the general/universal random number counter C6 is stored in the general/universal pattern reservation area 114 when winning to the through gate 35 occurs. The general pattern reservation area 114 includes a first area 125a, a second area 125b, a third area 125c and a fourth area 125d. is stored in one of the areas 125a to 125d as reserved information on the general map side.

In this case, in the first area 125a to the fourth area 125d, when winning to the through gate 35 occurs multiple times in succession, the first area 125a→second area 125b→third area 125c→fourth area Numerical information is stored chronologically in the order of 125d. Since the four areas 125a to 125d are provided in this way, up to four winning histories of game balls to the through gate 35 are reserved and stored.

In addition, the number that can be reserved and stored in the normal drawing reservation area 114 is not limited to 4 and is arbitrary, and may be another plurality such as 2, 3 or 5 or more. may be

The normal map reservation area 114 is provided with an execution area 126 for the normal map. The execution area 126 for the normal map is an area in which pending information of the target for the propriety determination for support is stored when the variable display is started in the normal map display section 38a. Specifically, when the variable display of the normal map display unit 38a is started, the reservation information stored in the first area 125a of the normal map reservation area 114 is moved to the execution area 126 for the normal map.

A general pattern reservation number counter 127 is provided in the general pattern reservation area 114 . The general pattern reservation number counter 127 is a counter that enables the main side CPU 63 to grasp the number of reservation information stored in the general pattern reservation area 114 . The general pattern reservation number counter 127 consists of 1 byte, and the general pattern reservation number counter 127 stores any numerical information of "0" to "4". The value of the general pattern reservation number counter 127 is incremented by 1 each time the reservation information is stored in the general pattern reservation area 114, and the reservation information stored in the general pattern reservation area 114 is transferred to the execution area for the general pattern. When moved to 126, 1 is subtracted.

Each of the counters C1 to C6 will be described in detail. FIG. 12(a) is an explanatory diagram for explaining the setting mode of various counters C1 to C6 in the work area 121 for specific control, and FIG. 12(b) is various maximum value counters in the work area 121 for specific control. FIG. 4 is an explanatory diagram for explaining a setting mode of CN1 to CN6;

As shown in FIG. 12(a), in the work area 121 for specific control, a jackpot type counter C2 is provided in a 1-byte area corresponding to the address of "0011H", and 1 corresponding to the address of "0012H". A reach random number counter C3 is provided in the byte area, a fluctuation type counter C5 is provided in the 1-byte area corresponding to the address "0013H", and a general electric random number counter is provided in the 1-byte area corresponding to the address "0014H" A counter C6 is provided. In addition, a random number counter C1 is provided for a 2-byte area (hereinafter also referred to as a 2-byte area) corresponding to addresses "0015H" to "0016H", and corresponds to addresses "0017H" to "0018H". A random number initial value counter C4 is provided in the 2-byte area.

Specifically, a lower area, which is a lower 1-byte area of the random number counter C1, is set in a 1-byte area corresponding to the address "0015H", and a 1-byte area corresponding to the address "0016H" is set. A high-order area, which is an area of the high-order 1 byte of the winning random number counter C1, is set. The lower area (lower 1-byte area) of the random number initial value counter C4 is set in the 1-byte area corresponding to the address "0017H", and the random number is set in the 1-byte area corresponding to the address "0018H". A high-order area (high-order 1-byte area) of the initial value counter C4 is set. In this way, in the work area 121 for specific control, these counters C1 to C6 are provided in a continuous address range of "0011H" to "0018H".

The maximum value of the jackpot type counter C2 is "99", the maximum value of the reach random number counter C3 is "238", the maximum value of the fluctuation type counter C5 is "198", and the maximum value of the general electric random number counter C6. is "250". Also, the maximum values of the winning random number counter C1 and the random number initial value counter C4 are "7999".

As shown in FIG. 12(b), in the work area 121 for specific control, the maximum value ("99") of the jackpot type counter C2 is set in the 1-byte area corresponding to the address of "0019H" jackpot type A reach maximum value counter CN2 is provided, and a reach maximum value counter CN3 in which the maximum value ("238") of the reach random number counter C3 is set is provided in a 1-byte area corresponding to the address 001AH, A 1-byte area corresponding to the 001BH address is provided with a variation type maximum value counter CN5 in which the maximum value ("198") of the variation type counter C5 is set. is provided with a general electric maximum value counter CN6 in which the maximum value ("250") of the general electric random number counter C6 is set. In addition, a 2-byte area corresponding to addresses "001DH" to "001EH" is provided with a winning maximum value counter CN1 in which the maximum value ("7999") of the winning random number counter C1 is set. ” to “0020H” is provided with an initial value maximum value counter CN4 in which the maximum value (“7999”) of the random number initial value counter C4 is set.

Specifically, the lower area (lower 1-byte area) of the hit maximum value counter CN1 is set in the 1-byte area corresponding to the address 001DH, and the 1-byte area corresponding to the address 001EH. A high-order area (high-order 1-byte area) of the maximum value counter CN1 is set. In addition, the lower area (lower 1-byte area) of the initial value maximum value counter CN4 is set in the 1-byte area corresponding to the address 001FH, and the 1-byte area corresponding to the address 0020H is set for the initial value. A high-order area (high-order 1-byte area) of the maximum value counter CN4 is set.

First, the general electric random number counter C6 will be described. The general electric random number counter C6 is configured to be sequentially incremented by 1 within the range of 0 to 250, and return to "0" after reaching the maximum value. The general electric random number counter C6 is periodically updated, and stored in the general pattern reservation area 114 in the work area 121 for specific control at the timing when the game ball wins the through gate 35.例文帳に追加Then, at a predetermined timing, a lottery is performed as to whether or not to control the general electrical accessory 34a to the open state based on the stored value of the general electrical random number counter C6.

In this pachinko machine 10, a plurality of types of support modes are set so that the mode of support by the general electric role item 34a is different from each other. Specifically, in the support mode, when compared with a situation in which game balls are continued to be shot in a similar manner to the game area PA, the general electric role 34a of the second operation port 34 per unit time A high-frequency support mode and a low-frequency support mode are set so that the frequency of the open state is relatively high or low.

In the high-frequency support mode and the low-frequency support mode, the probability of winning the general electricity open state in the general electricity open lottery using the general electricity random number counter C6 is the same (for example, 4/5 for both), but the probability is high. In the frequency support mode, the number of times the general electrical accessory 34a is in the open state when the general electrical open state is won is set more than in the low frequency support mode, and the open time for one time is set longer. there is In this case, in the high frequency support mode, when the general electric open state is won and the open state of the general electric accessory 34a occurs multiple times, the time from the end of one open state to the start of the next open state The closing time is set shorter than one opening time. Furthermore, in the high-frequency support mode, compared to the low-frequency support mode, the minimum secured time (i.e., the The duration of one display on the display section 38a) is set short.

As described above, in the high-frequency support mode, the probability of winning the second operation port 34 is higher than in the low-frequency support mode. In other words, in the low frequency support mode, the probability of winning the first operation opening 33 is higher than in the second operation opening 34, but in the high frequency support mode, the second operation opening is higher than the first operation opening 33. The probability of winning a prize to the mouth 34 is increased.

In addition, the configuration for making the high-frequency support mode more frequent than the low-frequency support mode to become the electric power open state per unit time is not limited to the above, for example, in the electric power open lottery A configuration may be adopted in which the probability of winning the electric power open state is increased. In addition, after one general electric open lottery is performed, the time secured for the next general electric open lottery In a configuration where multiple types of variable display time) are prepared, in the high-frequency support mode, it is easier to select a shorter reserved time than in the low-frequency support mode, or is set so that the average reserved time is shorter. good too. In addition, the number of open times is increased, the open time is lengthened, and the secured time that is secured after one electric power open lottery is held and the next electric power open lottery is held is shortened. The advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one condition or any combination of shortening the average time of winning and increasing the probability of winning.

If the general power open state is won in the general power open lottery using the general power random number counter C6, the general power open state is entered. The general electric open state ends when the general electric accessory 34a is opened and closed a predetermined number of times, or when a predetermined upper limit number of game balls wins the second operation opening 34. do. More specifically, the upper limit number is 10 in both the low-frequency support mode and the high-frequency support mode. On the other hand, the number of times of opening and closing the general electric accessory 34a is one in the low-frequency support mode, whereas in the high-frequency support mode, it is more than the low-frequency support mode. 3 times. In addition, the duration of one opening of the general electric accessory 34a is 1 second in the low frequency support mode, whereas it is 2 seconds in the high frequency support mode.

Next, the winning random number counter C1 will be described. The hit random number counter C1 is configured to be incremented by 1 in order within the range of 0 to 7999, and return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 makes one round, the value of the random number initial value counter C4 at that time is read as the initial value of the winning random number counter C1. The random number initial value counter C4 is a loop counter similar to the winning random number counter C1 (value=0 to 7999).

The hit random number counter C1 is periodically updated by timer interrupt processing (FIG. 26) described later, and is also irregularly updated by main processing (FIG. 15) described later. The value of the hit random number counter C1 is stored in the first special figure reservation area 115 in the work area 121 for specific control at the timing when the game ball wins the first operation opening 33, and the game ball is stored in the second operation opening 34. It is stored in the 2nd special figure reservation area 116 in the work area 121 for specific control at the timing of winning.

The values of random numbers for winning the jackpot are stored in the main ROM 64 as a success/failure table. FIG. 13 is an explanatory diagram for explaining various tables stored in the main ROM 64. As shown in FIG. Low probability mode tables 64a to 64f and a high probability mode high probability table 64g are stored as right/wrong tables.

The low certainty tables 64a to 64f are provided in one-to-one correspondence with the setting states of "setting 1" to "setting 6". That is, the low accuracy table 64a for setting 1 referred to when the setting state of the pachinko machine 10 is "setting 1" and the setting referred to when the setting state of the pachinko machine 10 is "setting 2" A low accuracy table 64b for 2, a low accuracy table 64c for setting 3 that is referred to when the setting state of the pachinko machine 10 is "setting 3", and a setting state of the pachinko machine 10 is "setting 4". A low certainty table 64d for setting 4 referred to when the setting state of the pachinko machine 10 is "setting 5", a low certainty table 64e for setting 5 referred to when the setting state is "setting 5", and the pachinko machine 10 There is a low certainty table 64f for setting 6 that is referred to when the setting state of is "setting 6".

These low certainty tables 64a to 64f are set so that the higher the setting value, the higher the winning probability of the jackpot result. Specifically, 25 values that result in a big win are set in the low certainty table 64a for setting 1. FIG. When the low certainty table 64a for setting 1 is referred to, 1/320 results in a big win. 26 values that result in a big win are set in the low certainty table 64b for the setting 2. When the low certainty table 64b for the setting 2 is referred to, the jackpot result is about 1/308. The low probability table 64c for setting 3 is set with 27 values that result in a big win. When the low certainty table 64c for setting 3 is referred to, a jackpot result is obtained at about 1/296. The low certainty table 64d for setting 4 is set with 28 values that result in a big win. When the low certainty table 64d for setting 4 is referred to, a jackpot result is obtained at about 1/286. The low probability table 64e for setting 5 is set with 29 values that result in a big win. When the low certainty table 64e for the setting 5 is referred to, the jackpot result is about 1/276. In the low certainty table 64f for the setting 6, 30 values that result in a big win are set. When the low certainty table 64f for setting 6 is referred to, a jackpot result is obtained at about 1/267. As a result, when the setting state of the pachinko machine 10 is set to a high set value, it becomes easier for the player to get a big hit result in the low probability mode, which is advantageous for the player.

On the other hand, the high certainty table 64g is provided with only one type so as to be common to any setting state of "setting 1" to "setting 6". The high-probability table 64g is set so that the winning probability of the jackpot results is higher than the low-probability tables 64a-64f in any setting state of "setting 1" to "setting 6". Specifically, 266 values that result in a big hit result are set in the high probability table 64g, and the other values are values that result in a loss result. When the high certainty table 64g is referred to, a jackpot result is obtained at about 1/30. As a result, regardless of the setting state of the pachinko machine 10, the high-probability mode can be made more advantageous than the low-probability mode. In addition, even in the lowest setting state "setting 1", it is possible to increase the probability of a big hit result by entering the high probability mode than in the low probability mode of "setting 6" which is the highest setting state. becomes. In addition, as for the high probability mode, it is possible to prevent the occurrence of advantage or disadvantage depending on the setting state of the pachinko machine 10, and suppress the storage capacity for pre-storing the high probability table 64g in the main side ROM 64. becomes possible.

40 small hit results are set in the low accuracy tables 64a to 64f and the high accuracy table 64g. In the success/failure determination, the result is a small hit with a probability of 1/200. The probability of a small hit result in the success/failure determination is the same in "setting 1" to "setting 6", and is also the same in the low probability mode and the high probability mode.

Next, the jackpot type counter C2 will be described. The jackpot type counter C2 is configured to be incremented by "1" in order within the range of 0 to 99, and return to "0" after reaching the maximum value. The jackpot type counter C2 is periodically updated. The value of the jackpot type counter C2 is stored in the first special figure reservation area 115 at the timing when the game ball has entered the first operation port 33, and the second special at the timing when the game ball has entered the second operation port 34. It is stored in the drawing reservation area 116 . Then, using the value of the stored jackpot type counter C2, distribution determination for sorting the types of jackpot results is performed.

The distribution destination of the type of the jackpot result for the jackpot type counter C2 is stored in the main ROM 64 as a distribution table. As the distribution table, the first special figure distribution table 64h used when determining the distribution of the first special figure side reserved information, and the second special figure used when determining the distribution of the second special figure side reserved information A diagram allocation table 64j is set. FIG. 14(a) is an explanatory diagram for explaining the contents of the first special figure distribution table 64h, and FIG. 14(b) is an explanation for explaining the contents of the second special figure distribution table 64j. It is a diagram. As shown in FIGS. 14(a) and 14(b), the sorting tables 64h and 64j include 4R high-probability jackpot results, 8R high-probability jackpot results, and 16R high-probability jackpot results as types of jackpot results. and are set.

In the 4R high-probability jackpot result, it becomes an opening and closing execution mode in which round games occur four times. Further, after the opening/closing execution mode ends, the high probability mode is set regardless of whether the winning/failure lottery mode before shifting to the opening/closing execution mode is set, and the high-frequency support mode is set regardless of the support mode before shifting to the opening/closing execution mode. Become. These high-probability mode and high-frequency support mode continue until 8 game rounds are completed. After the opening/closing execution mode triggered by the 4R high-probability jackpot result is completed, when 8 game rounds are completed without the opening/closing execution mode newly occurring, the winning/failure lottery mode becomes the low-probability mode, and the support mode. is the low-frequency support mode.

In the 8R high-probability jackpot result, it becomes an opening and closing execution mode in which round games occur eight times. Further, after the opening/closing execution mode ends, the high probability mode is set regardless of whether the winning/failure lottery mode before shifting to the opening/closing execution mode is set, and the high-frequency support mode is set regardless of the support mode before shifting to the opening/closing execution mode. Become. These high-probability mode and high-frequency support mode continue until 8 game rounds are completed. After the opening/closing execution mode triggered by the 8R high-probability jackpot result is completed, when 8 game rounds are completed without the opening/closing execution mode newly occurring, the success/failure lottery mode becomes the low-probability mode, and the support mode. is the low-frequency support mode.

In the 16R high-probability jackpot result, it becomes an opening and closing execution mode in which round games occur 16 times. Further, after the opening/closing execution mode ends, the high probability mode is set regardless of whether the winning/failure lottery mode before shifting to the opening/closing execution mode is set, and the high-frequency support mode is set regardless of the support mode before shifting to the opening/closing execution mode. Become. These high-probability mode and high-frequency support mode continue until 8 game rounds are completed. After the opening/closing execution mode triggered by the 16R high-probability jackpot result is completed, when 8 game rounds are completed without the opening/closing execution mode newly occurring, the win/fail lottery mode becomes the low-probability mode, and the support mode. is the low-frequency support mode.

The types of jackpot results to be distributed in either the first special figure distribution table 64h or the second special figure distribution table 64j are the 4R high probability jackpot result, the 8R high probability jackpot result and the 16R high probability result. It is one of the jackpot results. In this case, in the first special figure distribution table 64h, as shown in FIG. It corresponds to the result, "40 to 79" corresponds to the 8R high probability jackpot result, and "80 to 99" corresponds to the 16R high probability jackpot result. On the other hand, in the second special figure distribution table 64j, as shown in FIG. Correspondingly, "30 to 79" corresponds to the 8R high probability jackpot result, and "80 to 99" corresponds to the 16R high probability jackpot result. Although the probability that the 16R high probability jackpot result is selected is the same between the first special figure distribution table 64h and the second special figure distribution table 64j, in the case of the second special figure distribution table 64j, the The probability that the 4R high probability jackpot result is selected is lower than the distribution table for 1 special figure 64h, and the probability that the 8R high probability jackpot result is selected is set high. Therefore, as the type of jackpot result that can be selected when the jackpot is won, the second special figure side reservation information is the trigger rather than the first special figure side reservation information. It is advantageous for those who

The first special figure distribution table 64h is provided with only one type so that it is common to any setting state of "setting 1" to "setting 6", and the second special figure distribution table 64h Only one type of table 64j is provided so as to be common to any of the setting states of "setting 1" to "setting 6". As a result, it is possible to prevent the setting state of the pachinko machine 10 from causing an advantage or a disadvantage in terms of the mode of distribution determination, and the first special figure distribution table 64h and the second special figure distribution table 64h. 64j can be saved in the main ROM 64 in advance.

It should be noted that it is also possible to adopt a configuration in which the mode of distribution determination differs according to the setting state of the pachinko machine 10 . For example, the higher the setting value, the higher the probability of being distributed to the 16R high probability jackpot result, or the higher the setting value, the higher the probability of being distributed to the 16R high probability jackpot result or the 8R high probability jackpot result. Also, the higher the setting value, the lower the probability of being distributed to the 4R high probability jackpot result. It is good also as a structure which can be distributed. As a result, the higher the set value, the more times the round game occurs, which is advantageous for the player.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is incremented by 1 in order within the range of 0 to 238, and returns to "0" after reaching the maximum value. Here, in the pachinko machine 10, an expected effect is set as a kind of display effect in the pattern display device 41. - 特許庁The expected effect is a gaming machine equipped with a symbol display device 41 capable of performing a variable display of symbols, and the symbol display device 41 in which the final stop result is the award corresponding result in a game round that results in a predetermined big win result. It is a display state for making the player think that it is a variable display state that is likely to result in the grant correspondence result in the stage before the stop result is derived and displayed after the symbol variable display is started in . Concretely, a combination of symbols with the same number on any of the activated lines is stopped and displayed with respect to the award correspondence result.

There are two types of expectation effects: a ready-to-win display and an advance notice display for expecting the occurrence of the ready-to-win display and the occurrence of the grant correspondence result in a stage before the occurrence of the ready-to-win display.

In the ready-to-win display, a combination of ready-to-win symbols is displayed by stopping and displaying the symbols of some of the plurality of symbol rows displayed on the display surface 41a of the symbol display device 41, and the remaining symbols are displayed in that state. It includes a display state in which symbols are variably displayed in the symbol row. In addition, in a state in which the combinations of ready-to-win patterns are displayed as described above, the patterns are displayed in the remaining pattern rows in a variable manner, and a predetermined character or the like is displayed as a moving image on the background screen to produce a ready-to-win effect. , the combination of the ready-to-win pattern is reduced or hidden, and then a predetermined character or the like is displayed as a moving image on substantially the entire display surface 41a to perform the ready-to-win effect.

In the advance notice display, after the start of the variable display of the symbols on the display surface 41a of the symbol display device 41, the symbols are displayed variably in all of the symbol rows Z1 to Z3, or in some of the symbol rows. In a situation where symbols are variably displayed in a plurality of symbol rows, a mode is included in which a character is displayed separately from the symbols on the symbol rows Z1 to Z3. In addition, it also includes a background screen in a predetermined mode different from the previous mode, and a pattern in the pattern rows Z1 to Z3 in a predetermined mode different from the previous mode. Such an advance notice display can occur in any game round when the reach display is performed or when the reach display is not performed, but the rate when the reach display is performed is higher than when the reach display is not performed. It is set to occur with probability.

The ready-to-win display is executed regardless of the value of the ready-to-win random number counter C3 in game rounds in which the same combination of symbols is finally stopped and displayed. On the other hand, in the game round corresponding to the result of the small hit, the game is not executed regardless of the value of the reach random number counter C3. In addition, in the game round corresponding to the result of losing, the value of the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the reach table storage area of the main ROM 64 corresponds to the occurrence of the reach display. Executed when it is determined that

On the other hand, the determination of whether or not to perform the advance notice display is made not by the main CPU 63 but by the sound and light CPU 93 . In this case, in the sound and light side CPU 93, the game round corresponding to either the big win result or the small win result is more likely to cause the notice display than the game round corresponding to the losing result, and the appearance rate is low. Lottery processing for advance notice display is executed so as to satisfy at least one condition that the advance notice display is likely to occur. Incidentally, the result of the lottery is reflected when the symbol display device 41 executes an effect for a game cycle.

Next, the variation type counter C5 will be described. The fluctuation type counter C5 is configured to be incremented by 1 in order within the range of 0 to 198, for example, and return to "0" after reaching the maximum value. The fluctuation type counter C5 is used for determining the display duration in the first special figure display portion 37a or the second special figure display portion 37b and the display duration of the symbol in the symbol display device 41 in the main side CPU63. Specifically, the value of the variation type counter C5 is determined when determining the variation pattern at the start of the variation display in the first special figure display unit 37a or the second special figure display unit 37b and at the start of the variation of the symbol by the symbol display device 41 is obtained.

<Regarding the processing configuration of the main CPU 63>
Next, each process executed by the main CPU 63 to advance the game will be described. The processing of the main CPU 63 can be roughly classified into main processing that is activated upon power-on and timer interrupt processing that is periodically activated (at 4 millisecond cycles in this embodiment).

<Main processing>
First, the main processing will be described with reference to the flowchart of FIG.

In the main process, power-on wait process is first executed (step S101). In the power-on wait process, for example, the process waits without proceeding to the next process until a predetermined wait time (specifically, one second) elapses after the main process is activated. The start of operation and initial setting of the pattern display device 41 are completed during the execution period of the power-on wait process. Thereafter, access to the main RAM 65 is permitted (step S102).

After that, the command "LD IY, 0000H" is executed (step S103). In step S103, the IY register 109 of the main MPU 62 is loaded with the specific control reference address "0000H" by the LD instruction. The reference address for specific control is data for specifying an area corresponding to the addresses "0000H" to "00FFH" in the work area 121 for specific control in a situation where the process for specific control is being executed. used to reduce the data capacity of As shown in FIG. 10A, "0000H" is the leading address in the work area 121 for specific control.

Thus, the IY register 109 stores the specific control reference address (“0000H”) at the start of the main process, which is the process for specific control. As a result, in the first LDY instruction and the second LDY instruction, which will be described later, when any one of "0000H" to "00FFH" is specified, the address specification data is only the lower 1 byte in the 2-byte address information. becomes possible.

After that, the command "LD TP, 9000H" is executed (step S104). In step S104, the LD instruction loads the TP register 111 of the main MPU 62 with "9000H", which is the reference address of the data table (step S104). As already explained with reference to FIG. 10(b), data for specific control is set in the address range of "9000H" to "94FFH" in the main ROM 64, and data for non-specific control is set to "9903H". ” to “9BFFH”. The high-order 4 bits of the address corresponding to the area in which the data table is stored in the main-side ROM 64 are commonly "9H". The TP register 111 stores the reference address (“9000H”) of the data table at the start of the main process. As a result, in the LDT instruction, which will be described later, when any one of "9000H" to "94FFH" and "9903H" to "9BFFH" is specified, only the lower 12 bits of the 2-byte address information It becomes possible to In addition, the reference address of the data table stored in the TP register 111 can be used in the LDB instruction and the LDB update instruction, which will be described later.

Thereafter, it is determined whether or not the setting key insertion portion 68a is turned on (step S105). If the setting key insertion portion 68a has not been turned ON (step S105: NO), it is determined whether or not the reset button 68c has been pressed (step S106). If the reset button 68c is pressed (step S106: YES), a partial clear process is executed (step S107).

In the partial clearing process (step S107), each area of the main RAM 65 is cleared to "0" while maintaining the information of the set value counter provided in the work area 121 for specific control. Initialize the area. The set value counter is a counter that enables the main side CPU 63 to grasp the set value of the pachinko machine 10 . The setting value counter consists of 1 byte, and stores numerical information of "1" to "6" corresponding to "setting 1" to "setting 6". When the supply of the operating power to the pachinko machine 10 is started while pressing the reset button 68c without turning ON the setting key inserting portion 68a, the setting value information (information stored in the setting value counter ), the main-side RAM 65 is cleared while maintaining the state before the supply of operating power to the pachinko machine 10 is stopped, and the memory area for which the clearing process has been performed is initialized. will be As a result, other areas of the main RAM 65 can be initialized without changing the set values.

In the partial clearing process (step S107), first, the information of the set value counter is saved in the W register 104a. After that, a first clearing process is executed to clear "0" the work area 121 for specific control set at the addresses "0000H" to "02FFH" in the main RAM 65, and the specific control work area 121 after clearing "0" is executed. Initial setting is performed for the work area 121 for control. After that, the information saved in the W register 104a is written in the set value counter. After that, the second clearing process is executed to clear "0" the stack area 123 for specific control set at the addresses "0403H" to "044FH" in the main RAM 65, and the specific control after clearing "0" is executed. Initial setting is performed for the stack area 123 for control. After that, a third clearing process is executed to clear "0" the work area 122 for non-specific control set at addresses "0303H" to "03FFH" in the main RAM 65, and after clearing "0" The work area 122 for non-specific control is initialized. After that, a fourth clearing process is executed to clear "0" the stack area 124 for non-specific control set at addresses "0453H" to "04AFH" in the main RAM 65, and after clearing "0", The stack area 124 for non-specific control is initialized. In the first clearing process in the partial clearing process (step S104), the specific control reference address ("0000H") stored in the IY register 109 is used to set the start address of the area to be cleared to "0". ("0000H") is specified. Details of the first clear processing will be described later.

In the partial clearing process (step S107), the registers other than the IY register 109 and the TP register 111 among the various registers of the main MPU 62 are cleared to "0" and then initialized. On the other hand, the state in which the IY register 109 is set to the specific control reference address (“0000H”) and the state in which the TP register 111 is set to the data table reference address (“9000H”) are maintained.

After executing the partial clear processing in step S107, the partial clear flag provided in the work area 121 for specific control is set to "1" (step S108). The partial clear flag is a flag that allows the main CPU 63 to grasp that the partial clear process (step S107) has been executed. By setting the partial clear flag to "1" in step S108, a return command ( return command at the time of partial clearing) can be transmitted to the sound and light side CPU 93 . Also, by setting the partial clear flag to "1", it becomes possible to execute the clear setting process (FIG. 22(b)) described later in the clear support process (step S120) described later.

If the reset button 68c is not pressed (step S106: NO), it is determined whether or not the power failure flag 131a (FIG. 16(b)) is set to "1" (step S109). The power failure flag 131a is provided in the work area 121 for specific control. "1" is set to the flag 131a. Details of the power failure flag 131a will be described later.

If the power failure flag 131a is set to "1" (step S109: YES), it determines whether the checksum calculation result matches the checksum saved at the time of power failure, that is, the validity of the stored data. is determined (step S110).

When the process of step S108 is executed, or when an affirmative determination is made in step S110, it is determined whether or not the setting value of the pachinko machine 10 is normal (step S111). In step S111, the setting value of the pachinko machine 10 is grasped based on the value of the setting value counter provided in the work area 121 for specific control. As already explained, the set value counter stores numerical information of "1" to "6" corresponding to "setting 1" to "setting 6". In step S111, if the value of the set value counter is any one of "1" to "6", it is determined to be normal, and if it is "0" or "7" or more, it is determined to be abnormal.

When a negative determination is made in any of steps S109 to S111, operation prohibition processing is executed. In the operation prohibition process, after executing an error notification process for notifying the hall manager or the like of the occurrence of an error (step S112), an infinite loop occurs. The operation prohibition process is canceled by executing the partial clear process (step S107) or the all clear process (step S114) described later.

When all of steps S109 to S111 are affirmative, return command transmission processing is executed (step S113). In the return command transmission process, when the partial clear flag in the work area 121 for specific control is set to "1", the partial clear return command is transmitted to the sound and light side CPU 93 . The partial clear return command is a command for causing the sound and light side CPU 93 to recognize that the partial clear processing (step S107) has been executed. When the sound/light side CPU 93 receives the partial clear return command, it controls the display of the pattern display device 41 so as to display an indication that the partial clear processing (step S107) has been executed. As a result, it is possible to notify the manager of the game hall that the partial clearing process (step S107) has been executed. In addition, in the return command transmission process in step S113, if the partial clear flag is not set to "1", the normal return command is transmitted to the sound and light side CPU93. The normal return command is a command for making the sound/light side CPU 93 recognize that the partial clear process (step S107) and the all clear process (step S114), which will be described later, were not executed when the power was restored. When the sound/light side CPU 93 receives the normal return command, the pattern is displayed so that a display is made to notify that the partial clear processing (step S107) and the all clear processing (step S114) were not executed when the power was restored. Display control of the device 41 is performed. As a result, it is possible to inform the manager of the game hall that the partial clearing process (step S107) and the all clearing process (step S114) were not executed when the power was restored. Details of the return command transmission process will be described later.

On the other hand, if the setting key inserting portion 68a is ON-operated (step S105: YES), all clear processing is executed (step S114). In the all-clearing process, all areas of the main RAM 65, including the area in which the setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0" and cleared to "0". Initialize the area. That is, when an operation for changing the setting state of the pachinko machine 10 is performed, all areas of the main side RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the clearing is performed. Initialization is performed for the storage area in which the process has been performed. Even if the operation for changing the setting state of the pachinko machine 10 is being performed, if the reset button 68c is not pressed, the main side RAM 65 will not be completely cleared, and the pachinko game will not be executed. The configuration may be such that the all clear processing is executed when an operation for changing the setting state of the machine 10 is performed and the reset button 68c is pressed.

In the all-clearing process (step S114), a first clearing process is executed to clear "0" the specific control work area 121 set at addresses "0000H" to "02FFH" in the main RAM 65. The work area 121 for specific control after clearing "0" is initialized. After that, the second clearing process is executed to clear "0" the stack area 123 for specific control set at the addresses "0403H" to "044FH" in the main RAM 65, and the specific control after clearing "0" is executed. Initial setting is performed for the stack area 123 for control. After that, a third clearing process is executed to clear "0" the work area 122 for non-specific control set at addresses "0303H" to "03FFH" in the main RAM 65, and after clearing "0" The work area 122 for non-specific control is initialized. After that, a fourth clearing process is executed to clear "0" the stack area 124 for non-specific control set at addresses "0453H" to "04AFH" in the main RAM 65, and after clearing "0", The stack area 124 for non-specific control is initialized. In the first clearing process in the all clearing process (step S114), the specific control reference address ("0000H") stored in the IY register 109 is used to set the starting address ("0") of the area to be cleared to "0" ( "0000H"). Details of the first clear processing will be described later.

In the all-clearing process (step S114), as in the already-described partial clearing process (step S107), among the various registers of the main MPU 62, the registers other than the IY register 109 and the TP register 111 are cleared to "0". After that, make the initial settings. On the other hand, the state in which the IY register 109 is set to the specific control reference address (“0000H”) and the state in which the TP register 111 is set to the data table reference address (“9000H”) are maintained.

After executing the all-clear processing in step S114, the all-clear flag provided in the work area 121 for specific control is set to "1" (step S115). The all-clear flag is a flag that enables the main CPU 63 to recognize that the all-clear processing (step S114) has been executed. By setting the all-clear flag to "1" in step S115, it is possible to execute the clear setting process (FIG. 22(b)) described later in the clear handling process (step S120) described later.

After that, a return command for clearing all is transmitted to the sound and light side CPU 93 (step S116). The all-clear recovery command is a command for making the sound and light side CPU 93 recognize that the all-clear processing (step S114) has been executed at the time of power recovery. When receiving the all-clear return command, the sound and light side CPU 93 controls the display of the pattern display device 41 so as to display a notification that the all-clear processing (step S114) has been executed. As a result, it is possible to inform the manager of the gaming hall that the all-clearing process (step S114) has been executed. After that, set value update processing, which will be described later, is executed (step S117).

When the process of step S113 is performed, or when the process of step S117 is performed, a power-on setting process is performed (step S118). In the power-on setting process, initial setting is performed for a predetermined area in the work area 121 for specific control, such as initialization of the power failure flag 131a. Details of the power-on setting process will be described later.

Thereafter, random number maximum value setting processing is executed (step S119). In the random number maximum value setting process, the maximum value counters CN1 to CN6 are set to the maximum values of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the fluctuation type counter C5 and the general electric random number counter C6. set. After that, a clear handling process is executed (step S120). Details of the random number maximum value setting process (step S119) and the clear handling process (step S120) will be described later.

After that, the process proceeds to the remaining processes of steps S121 to S124. The main CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited at the stage when the main processing is started. The state in which the generation of the timer interrupt process is prohibited is released by executing the process of step S121 after the process of step S120 is completed, and the execution of the timer interrupt process is permitted. Although the main CPU 63 is configured to periodically execute timer interrupt processing, there will be a residual time between one timer interrupt processing and the next timer interrupt processing. Although this remaining time varies according to the processing completion time of each timer interrupt process, the remaining process of steps S121 to S124 is repeatedly executed using such irregular time. In this respect, it can be said that the remaining processes of steps S121 to S124 are irregular processes that are executed irregularly.

In the remaining processing, first, an interrupt permission setting is performed to switch from a state in which the occurrence of timer interrupt processing is prohibited to a state in which it is permitted (step S121). Thereafter, an interrupt prohibition setting is performed to prohibit the occurrence of timer interrupt processing (step S122). Thereafter, random number initial value update processing for updating the random number initial value counter C4 is executed (step S123). In the random number initial value update process, 1 is added to the value of the random number initial value counter C4, and when the value after the 1 addition exceeds the maximum value of "7999", the value of the random number initial value counter C4 is set to "0". clear.

Thereafter, a variation counter update process for updating the variation type counter C5 is executed (step S124). In the fluctuation counter update process, 1 is added to the value of the fluctuation type counter C5, and when the value after the addition of 1 exceeds the maximum value of "250", the value of the fluctuation type counter C5 is cleared to "0". . After that, the process returns to step S121, and the remaining processes of steps S121 to S124 are repeated.

Next, the power-on setting process in step S118 of the main process (FIG. 15) will be described.

FIG. 16(a) is an explanatory diagram for explaining a storage area where "0" clearing and initial setting are performed in the power-on setting process. As shown in FIG. 16(a), a blackout area 131 is provided at the address "0001H" in the work area 121 for specific control, and an illegal monitoring timer counter 132 is provided at the addresses "0008H" to "0009H". is provided, an illegal radio wave detection counter 133 is provided at the address "0021H", an illegal magnetic detection counter 134 is provided at the address "0022H", and an abnormal magnetic field detection counter 134 is provided at the address "0023H" A vibration detection counter 135 is provided.

In the power-on setting process, the high-order 1 byte of the address for specifying the storage area where "0" clearing and initialization are performed is commonly "00H". In the power-on setting process, "00H" is set in the D register 106a, and the lower 1 byte of the address is read from the data table and set in the E register 106b, thereby storing the entire address (2 bytes) in the DE register 106. ) is stored. Then, the address information stored in the DE register 106 is used to designate the area to be cleared to "0" and initialized. This makes it possible to reduce the data capacity of the data stored in the main ROM 64 for addressing.

The power outage area 131 is a 1-byte area including a power outage flag 131a. FIG. 16B is an explanatory diagram for explaining the data configuration of the power outage area 131. As shown in FIG. As shown in FIG. 16B, a power failure flag 131a is set to the least significant bit (0th bit) in the power failure area 131, and the first to seventh bits in the power failure area 131 are unused bits. It's becoming

Although not shown, the pachinko machine 10 includes an illegal radio wave detection sensor for detecting illegal radio waves, an illegal magnetism detection sensor for detecting illegal magnetism, and an abnormal vibration for detecting abnormal vibration. A detection sensor is provided. Detection signals from these detection sensors are input to the input side of the main MPU 62 . When the detection signal received from the fraudulent radio wave detection sensor is in the HI state, the main CPU 63 recognizes that fraudulent radio waves are being detected. In some cases, it is grasped that an illegal magnetism is detected, and when the detection signal received from the abnormal vibration detection sensor is in a HI state, it is grasped that an abnormal vibration is detected. . The fraudulent radio wave detection counter 133 allows the main side CPU 63 to grasp whether or not the state in which fraudulent radio waves are detected has been specified five times during one fraud monitoring reference period (specifically, approximately 262 seconds). The fraudulent magnetism detection counter 134 is a counter that enables the main side CPU 63 to grasp whether or not the state in which fraudulent magnetism is detected is specified 10 times during one fraud monitoring reference period. , and the abnormal vibration detection counter 135 is a counter that enables the main CPU 63 to grasp whether or not a state in which abnormal vibration is detected has been specified 15 times during one fraud monitoring reference period. These detection counters 133 to 135 consist of 1 byte. The fraudulent radio wave detection counter 133 is set to "5" ("0101B") as an initial value, the fraudulent magnetism detection counter 134 is set to "10" ("1010B") as an initial value, and the abnormal vibration detection counter 135 is set to is set to "15" ("1111B") as an initial value. One fraud monitoring reference period is about 262 seconds, and when the fraud monitoring reference period ends, the next fraud monitoring reference period starts. That is, the fraud monitoring reference period is repeatedly set with a period of about 262 seconds. In this specification, "B" attached after a numerical value is a symbol indicating that the numerical value is expressed in binary.

The initial value of the fraudulent magnetism detection counter 134 is less than the initial value of the fraudulent radio wave detection counter 133 so as not to be erroneously recognized as fraud when a magnetic material contained in the player's belongings accidentally approaches the game board 24. is also set large. In addition, the initial value of the abnormal vibration detection counter 135 is set to the initial value of the fraudulent radio wave detection counter 133 and fraudulent magnetism detection so as not to be mistakenly recognized as fraudulent when the player accidentally touches the pachinko machine 10 and lightly vibrates. It is set larger than the initial value of the counter 134 . Note that the initial values of these detection counters 133 to 135 are not limited to the above values and are arbitrary.

The main CPU 63 decrements the value of the illegal radio wave detection counter 133 by 1 each time a timer interrupt process (FIG. 26), which will be described later, is executed in a state where illegal radio waves are detected, and illegal magnetism is detected. Each time timer interrupt processing (FIG. 26), which will be described later, is executed in this state, the value of the fraudulent magnetism detection counter 134 is decremented by 1, and timer interrupt processing (FIG. 26), which will be described later, is executed while abnormal vibration is detected. The value of the abnormal vibration detection counter 135 is decremented by 1 each time. Then, when the value of any one of these detection counters 133 to 135 becomes "0", fraud detection handling processing is executed. In the fraud detection handling process, the game stop flag provided in the work area 121 for specific control is set to "1". The game stop flag is a flag that enables the main side CPU 63 to grasp whether or not the progress of the game is stopped. By setting the game stop flag to "1", the progress of the game is stopped. The details of the fraud detection handling process will be described later.

In the fraud detection response process, if the state in which fraudulent radio waves are detected is specified five times during one fraud monitoring reference period, the state in which fraudulent magnetism is detected is regarded as one fraud monitoring. It is executed when it is identified 10 times during the reference period, or when the state in which abnormal vibration is detected is identified 15 times during one fraud monitoring reference period. Therefore, when the detection signal received from the fraudulent radio wave detection sensor, the fraudulent magnetism detection sensor, or the abnormal vibration detection sensor is detected to rise once from the LOW state to the HI state, the fraud detection response processing is immediately executed. , it is possible to reduce the possibility that the fraud detection handling process is erroneously executed due to the influence of noise.

The fraud monitoring timer counter 132 is a 2-byte counter that enables the main CPU 63 to recognize that the fraud monitoring reference period has elapsed without execution of the fraud detection response process. The initial value of the fraud monitoring timer counter 132 is "0". The fraud monitoring timer counter 132 is incremented by 1 each time a timer interrupt process (FIG. 26) described later is executed, and when the maximum value of "65535" is exceeded, it goes back to "0". The main CPU 63 specifies that the fraud monitoring reference period has elapsed each time the value of the fraud monitoring timer counter 132 cycles, and initializes the fraud radio wave detection counter 133, fraud magnetism detection counter 134, and abnormal vibration detection counter 135. set the value. Since the detection counters 133 to 135 are initialized each time the fraud monitoring reference period elapses, the effects of noise generated over a long period (for example, 10 hours) exceeding the fraud monitoring reference period are accumulated. Therefore, it is possible to prevent the values of these detection counters 133 to 135 from becoming "0".

<LDT instruction>
Next, before describing the contents of the program for the power-on setting process (FIG. 17(c)), the LDT instruction included in the program for the power-on setting process will be described. FIG. 17(a) is an explanatory diagram for explaining the data structure of the machine language of the LDT instruction, and FIG. 17(b) is an explanatory diagram for explaining the data structure of the machine language of the LD instruction. (c) is an explanatory diagram for explaining the program contents of the power-on setting process.

As shown in FIG. 17(c), the power-on setting process program includes an LDT command "LDT HL, 400H". The main CPU 63 can execute an LDT instruction in addition to an LD instruction as a transfer instruction for transferring data. As shown in FIG. 9 , the main MPU 62 has an LDT execution circuit 149 . The LDT execution circuit 149 is a dedicated circuit for executing LDT instructions.

The instruction code of the LD instruction has a configuration of "LD transfer destination, transfer source". In the LD instruction, a general-purpose register such as the W register 104a, a pair register such as the WA register 104, or a storage area of the main RAM 65 are set as the "transfer destination", and a general-purpose register such as the W register 104a is set as the "transfer source." A pair register such as the WA register 104, data stored in the storage area of the main RAM 65, or a numerical value is set.

In the LD instruction, 2-byte numerical information set in the "source" is loaded into the "destination". For example, when the instruction "LD HL, 9400H" is executed, "9400H" set as the "source" is loaded into the HL register 107 set as the "destination".

The instruction code of the LDT instruction has a configuration of "LDT transfer destination, transfer source". In the LDT instruction, the HL register 107 is set as the "transfer destination". In the LDT instruction, a 12-bit numerical value (for example, "400H") is set as the "transfer source". Note that the WA register 104, the BC register 105, or the DE register 106 may be set as the "transfer destination" of the LDT instruction.

In the LDT instruction, the 2-byte numerical information obtained by adding the 2-byte numerical information set in the TP register 111 to the 12-bit numerical information set as the “transfer source” is the “transfer destination”. is loaded into the pair register set to As already explained, in the present embodiment, the TP register 111 is set with "9000H", which is the reference address of the data table. By executing "LDT HL, 400H" with "9000H" set in the TP register 111 in advance, the HL register 107 is set to "9400H" is loaded.

First, the data structure of the machine language of the LD instruction will be described while exemplifying "LD HL, 9400H" as a specific instruction code of the LD instruction. “LD HL, 9400H” is an instruction code for loading 2-byte numerical information “9400H” into the HL register 107 . As shown in FIG. 17(b), the machine language of the LD instruction includes instruction data to instruct loading of the data of the "transfer source" into the "transfer destination" and the HL register 107 as the "transfer destination". It includes transfer destination designation data that specifies the transfer destination and transfer source designation data that designates the “transfer source”. In the machine language of the LD instruction, the total data capacity of the instruction data and transfer destination designation data is 2 bytes, and the data capacity of the transfer source designation data is 2 bytes. Thus, the total data capacity of the machine language of the LD instruction is 4 bytes.

Next, the data configuration of the machine language of the LDT instruction will be described while exemplifying "LDT HL, 400H" as a specific instruction code of the LDT instruction. As shown in FIG. 17(a), the machine language of the LDT instruction includes instruction data for instructing loading of the data of the "source" into the "destination", similar to the machine language of the LD instruction described above. , the transfer destination designating data designating the HL register 107 as the "transfer destination" and the transfer source designating data designating the "transfer source". In the machine language of the LDT instruction, the total data capacity of the instruction data and transfer destination designating data is 4 bits, and the data capacity of the transfer source designating data is 12 bits. In the case of "LDT HL, 400H", the 12-bit numerical information "400H" is set as the "transfer source", and the 12-bit numerical information "400H" is used as is in the machine language of the LDT instruction. Included as transfer source designation data. Thus, the total data capacity of the machine language of the LDT instruction is 2 bytes.

Therefore, when "9000H" is stored in the TP register 111 and the address of the data table stored in the main ROM 64 is loaded into the HL register 107, the LDT instruction is used instead of the LD instruction. By doing so, the machine language of the instruction to load the data of the "source" to the "destination" can be reduced by 2 bytes. Thereby, the data capacity of the program in the main ROM 64 can be reduced.

Next, the program contents of the power-on setting process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 17(c). The power-on setting process is executed in step S118 of the main process (FIG. 15). As shown in FIG. 17(c), "1001" to "1005" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LDT HL, 400H" is set at the line number "1001". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "400H" sets 12-bit numerical information "400H" as the transfer source. Content. As already explained, the reference address (“9000H”) of the data table is set in the TP register 111 in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 400H", "9400H" obtained by adding "9000H" set in the TP register 111 to "400H" set as the transfer source is obtained. HL register 107 is loaded. The main-side ROM 64 stores a first initialization table 64k (FIG. 18(a)) as a data table for setting initial values for the unauthorized radio wave detection counter 133, the unauthorized magnetism detection counter 134, and the abnormal vibration detection counter 135. "9400H" is the start address of the first initialization table 64k. Details of the first initialization table 64k will be described later.

In this way, by using the LDT instruction to set the start address of the first initialization table 64k in the HL register 107, the LD instruction is used to set the start address of the first initialization table 64k in the HL register 107. The data volume of the program for executing the power-on setting process can be reduced compared to the configuration that sets the address.

The command "XOR D, D" is set at the line number "1002". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma designates the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As already described with reference to FIG. 16(a), the high-order 1 byte of the addresses of the areas and counters targeted for power-on setting processing is commonly "00H". The instruction of line number "1002" is an instruction for setting the common upper 1 byte ("00H") in the D register 106a.

The command "CALL 4BTS10" is set at the line number "1003". "4BTS10" is data setting execution processing (FIG. 19(c)), which will be described later. The instruction "CALL 4BTS10" is an instruction for calling a subroutine called data setting execution processing. At line number "1003", data setting execution processing is executed with the start address of the first initialization table 64k set in the HL register 107 and "00H" stored in the D register 106a. As already explained, the first initialization table 64 k is a data table for setting initial values to the unauthorized radio wave detection counter 133 , the unauthorized magnetism detection counter 134 and the abnormal vibration detection counter 135 . By executing the data setting execution process at line number "1003", the fraudulent radio wave detection counter 133 is set to "5" as an initial value, and the fraudulent magnetism detection counter 134 is set to "10" as an initial value. The abnormal vibration detection counter 135 is initially set to "15". When the data setting execution processing subroutine called based on the command of line number "1003" is completed, the process proceeds to line number "1004". Although the details will be described later, the start address of the second initialization table 64m (FIG. 18(b)) in the main ROM 64 is stored in the HL register 107 by executing the data setting execution process at the line number "1003". It will be in the set state. The second initialization table 64m is a data table for clearing the power failure area 131 and the fraud monitoring timer counter 132 to "0". Details of the second initialization table 64m will be described later.

The command "CALL 4BTS10" is also set at the line number "1004". At line number "1004", data setting execution processing is executed with the start address of the second initialization table 64m set in the HL register 107 and "00H" stored in the D register 106a. By executing the data setting execution process at the line number "1004", the power failure area 131 and the fraud monitoring timer counter 132 are cleared to "0". When the data setting execution processing subroutine called based on the command of line number "1004" is completed, the process proceeds to line number "1005".

A command "RET" is set at the line number "1005". As already explained, the power-on setting process is a subroutine executed in step S118 of the main process (FIG. 15). Therefore, by executing the command "RET", the process proceeds to step S119 of the main process (FIG. 15).

The process of initializing the unauthorized radio wave detection counter 133, the unauthorized magnetism detection counter 134, and the abnormal vibration detection counter 135 using the first initialization table 64k is performed in addition to the power-on setting process (Fig. 17(c)). This is executed in the fraud detection initialization process (FIG. 29(b)) in step S812 of the fraud detection process (FIG. 29(a)). Since the initialization tables are stored separately in the first initialization table 64k and the second initialization table 64m in the main ROM 64, only the first initialization table 64k is used in processes other than the power-on setting process. It is possible to execute processing for initializing the unauthorized radio wave detection counter 133 , the unauthorized magnetism detection counter 134 , and the abnormal vibration detection counter 135 .

<Data Configuration of Initialization Tables 64k and 64m>
Next, the first initialization table 64k and the second initialization table 64m stored in the main ROM 64 will be described.

FIG. 18(a) is an explanatory diagram for explaining the data configuration of the first initialization table 64k, and FIG. 18(b) is an explanatory diagram for explaining the data configuration of the second initialization table 64m. As already explained, the first initialization table 64k is a data table for setting initial values to the fraudulent radio wave detection counter 133, the fraudulent magnetism detection counter 134, and the abnormal vibration detection counter 135, and the second initialization table 64m. is a data table for clearing the power failure area 131 and the fraud monitoring timer counter 132 to "0".

In the main ROM 64, the first initialization table 64k is stored in the address range from "9400H" to "9405H" as shown in FIG. 18(a), and the second initialization table 64m is stored in the As shown in b), it is stored in the address range "9406H" to "940BH" following the address range of the first initialization table 64k.

As shown in FIGS. 18(a) and 18(b), each of the initialization tables 64k and 64m has a data structure in which the first to third areas are repeated in the order of first area→second area→third area. It's becoming The first to third areas are 1-byte areas. The first area is an area in which "0" clear data or initial setting data is set in the upper 4 bits and the lower 4 bits. For example, as shown in FIG. 18(a), in the first initialization table 64k, the upper 4 bits of the first area corresponding to the address of "9400H" are set to the initial value "5" for the unauthorized radio wave detection counter 133. The initial setting data ("0101B") for setting is set, and the initial setting data for setting the initial value "10" to the counterfeit magnetism detection counter 134 in the lower 4 bits of the first area. (“1010B”) is set. Further, as shown in FIG. 18B, "0" for clearing the power failure area 131 to "0" is stored in the upper 4 bits of the first area corresponding to the address of "9406H" in the second initialization table 64m. Clear data (“0000B”) is set, and “0” clear data (“0000B”) is set in the lower 4 bits of the first area to clear the lower 1 byte of the fraud monitoring timer counter 132 to “0”. ) is set.

The second area is an area in which the lower 1 byte of the address specifying the transfer destination to which "0" clear data or initial setting data set in the upper 4 bits of the immediately preceding first area is transferred is set. . For example, as shown in FIG. 18(a), in the second area corresponding to the address "9401H" in the first initialization table 64k, the lower 1 byte (" 21H”) is set. Further, as shown in FIG. 18(b), in the second area corresponding to the address of "9407H" in the second initialization table 64m, the lower 1 byte ("01H") of the address ("0001H") of the power failure area 131 is stored. ) is set.

The third area is an area in which the lower 1 byte of the address specifying the transfer destination to which the "0" clear data or initial setting data set in the lower 4 bits of the immediately preceding first area is transferred is set. . For example, as shown in FIG. 18(a), in the third area corresponding to the address "9402H" in the first initialization table 64k, the lower 1 byte (" 22H”) is set. Further, as shown in FIG. 18(b), in the third area corresponding to the address of "9408H" in the second initialization table 64m, the lower 1 in the lower area address ("0008H") of the fraud monitoring timer counter 132 is stored. A byte (“08H”) is set.

The final address of each initialization table is the second area or the third area. "00H" is set as end data. Specifically, as shown in FIGS. 18A and 18B, "9405H" which is the last address of the first initialization table 64k and "940BH" which is the last address of the second initialization table 64m is set with "00H", which is end data.

<LD update instruction and LDH update instruction>
Here, prior to detailed description of the data setting execution process (FIG. 19(c)), the LD update command and the LDH update command included in the data setting execution process will be described.

First, the LD update instruction will be explained. The data setting execution process (FIG. 19(c)) includes an LD update command "LD E, (HL+)". As shown in FIG. 9, the main MPU 62 has an LD update execution circuit 151, which is a dedicated circuit for executing LD update instructions, and the main CPU 63 can execute LD update instructions.

The instruction code of the LD update instruction has a configuration of "LD transfer destination, (transfer source +)". In the LD update instruction, a general-purpose register such as the W register 104a or a storage area in the main RAM 65 is set as a "transfer destination". In the LD update instruction, the HL register 107 is set as the "transfer source". The LD update instruction loads one byte of data into the "destination" general-purpose register or storage area. A pair register such as the WA register 104 is set as the "transfer destination" of the LD update instruction. A configuration in which byte data is loaded may also be used. Alternatively, the WA register 104, the BC register 105, or the DE register 106 may be set as the "transfer source" of the LD update instruction.

The LD update instruction is a process of loading the data stored in the area corresponding to the address stored in the "transfer source" register into the "transfer destination", and after executing the process, loading the data into the "transfer source" register. This instruction makes it possible to execute a process of adding "1" to a stored address and updating the address with a single instruction. For example, when "LD E, (HL+)" is executed, the data stored in the area corresponding to the address stored in the HL register 107 set as the "transfer source" is transferred to the "transfer destination " is loaded into the E register 106b, and after the loading, "1" is added to the address stored in the HL register 107 so that the address stored in the HL register 107 is updated.

By adopting a configuration that uses the LD update instruction, compared with a configuration that executes an operation instruction for adding "1" to the address stored in the "transfer source" register in the LD instruction after executing the LD instruction. Therefore, the data capacity of the program for updating the address after loading the data can be reduced.

Next, the LDH update instruction will be explained. The data setting execution process (FIG. 19(c)) includes an LDH update command "LDH WA, (HL+)". As shown in FIG. 9, the main MPU 62 has an LDH update execution circuit 152 which is a dedicated circuit for executing LDH update instructions, and the main CPU 63 can execute LDH update instructions.

The instruction code of the LDH update instruction has a configuration of "LDH transfer destination, (transfer source+)". In the LDH update instruction, the WA register 104 is set as the "transfer destination" and the HL register 107 is set as the "transfer source."

The LDH update instruction is set to the WA register 104 whose ``transfer destination'' is the upper 4-bit data in the 1-byte data stored in the area corresponding to the address stored in the ``transfer source'' HL register 107. One of the general-purpose registers (W register 104a) is loaded into the lower 4 bits, and the upper 4 bits of the general-purpose register are masked with "0". of the WA register 104 set to ", and the processing of loading the lower 4 bits of the other general-purpose register (A register 104b) and masking the upper 4 bits of the general-purpose register with "0", and the execution of these processes This is an instruction that can later execute the processing of adding "1" to the address stored in the HL register 107 of the "transfer source" and updating the address stored in the HL register 107 with one instruction. .

FIGS. 19(a) and 19(b) are explanatory diagrams for explaining the LDH update instruction, taking "LDH WA, (HL+)" as an example. As shown in FIG. 19A, the HL register 107 stores "1001010000000000B" ("9400H"). Further, in the main ROM 64, "0101B" is stored in the upper 4 bits of the area corresponding to the address "9400H", and "1010B" is stored in the lower 4 bits. By executing "LDH WA, (HL+)", as shown in FIG. The upper 4 bits of the data stored in the area corresponding to the address are set to "0101B", and the upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b, which is the other general-purpose register of the WA register 104, is set to "1010B" which is the lower 4 bits of the data stored in the area corresponding to the address "9400H". At the same time, the upper 4 bits of the A register 104b are masked with "0". Then, "1" is added to the address stored in the HL register 107, and the address stored in the HL register 107 is updated to "1001010000000001B" ("9401H").

In this way, by using the LDH update instruction, the upper 4-bit data and the lower 4-bit data in the 1-byte area of the main ROM 64 can be read to different general-purpose registers, and each general-purpose The upper 4 bits can be masked with "0" in the register. Further, by adopting a configuration that uses the LDH update instruction, the upper 4-bit data in the area corresponding to the address stored in the "transfer source" HL register 107 is set to the "transfer destination" WA register 104, one of the general purpose registers (W register 104a) is loaded into the lower 4 bits and the upper 4 bits of the general purpose register are masked with "0"; A process of loading the lower 4 bits of the other general-purpose register (A register 104b) of the WA register 104 set to , and masking the upper 4 bits of the general-purpose register with "0"; It is possible to reduce the data volume of the program for executing the process of adding "1" to the address stored in the "transfer source" HL register 107 and updating the address.

Next, the program contents of the data setting execution process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 19(c). As already explained, the data setting execution process is called by executing "CALL 4BTS10" at line numbers "1003" and "1004" of the power-on setting process (FIG. 17(c)). The data setting execution process is performed when "CALL 4BTS10" is executed at line number "1203" of the setting process when clearing (Fig. It is also called when "CALL 4BTS10" is executed at line number "1503" in (b)). As shown in FIG. 19C, "1101" to "1109" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

First, the case where the data setting execution process is executed at line number "1003" of the power-on setting process (FIG. 17(c)) will be described. 20(a) to 20(g) show the D register 106a, E register 106b, FIG. 4 is an explanatory diagram for explaining states of a W register 104a, an A register 104b, and an HL register 107;

As already explained, in line number "1003", "9400H", which is the start address of the first initialization table 64k, is stored in the HL register 107, and the illegal radio wave detection counter 133, the illegal magnetism detection counter 134, and the abnormal The data setting execution process is executed in a state where the upper 1 byte ("00H") common to the address data of the vibration detection counter 135 is stored in the D register 106a (see FIG. 20(a)).

In the data setting execution process executed at line number "1003", first, the data set in the address range of "9400H" to "9402H" in the first initialization table 64k (FIG. 18(a)) is used. The instructions of line numbers "1102" to "1109" are executed. As already described with reference to FIG. 18(a), the initial value "5" is stored in the first area high-order 4 bits of the first area corresponding to the start address 9400H of the first initialization table 64k. ” is set as the initial setting data for setting “0101B”, and the lower 4 bits of the first area are the initial setting for setting “10” which is the initial value of the fraudulent magnetism detection counter 134 "1010B" is set as data. In the second area corresponding to "9401H" following "9400H", "21H", which is the lower 1 byte of the address of the fraudulent radio wave detection counter 133, is set. In the third area corresponding to "9402H" following "9401H", "22H", which is the lower 1 byte of the address of the fraudulent magnetism detection counter 134, is set.

As shown in FIG. 19(c), "4BTS10" is set to the line number of "1101". This is not an instruction but data referred to when the developer of the pachinko machine 10 checks the program. Therefore, at line number "1101", the process proceeds to line number "1102" without executing any instruction.

The command "LDH WA, (HL+)" is set at the line number "1102". "LDH" is an LDH update command by the LDH update execution circuit 152, and "WA" is the contents specifying the WA register 104 as the transfer destination. "(HL+)" designates the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source, and the value of the HL register 107 is set to 1 after the data is loaded. The content instructs to update the address stored in the HL register 107 by addition. As described above, in the first initialization table 64k, the upper 4 bits of the first area corresponding to "9400H" are set to "0101B" as initialization data, and the lower 4 bits of the first area are set to "1010B" is set as initial setting data. Therefore, by executing "LDH WA, (HL+)" at the line number "1102", as shown in FIG. A bit "0101B" is set, and the upper four bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "1010B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the W register 104a stores the data "00000101B" for the initial setting of the fraudulent radio wave detection counter 133, and the A register 104b stores "00000101B" for the initial setting of the fraudulent magnetism detection counter 134. 00001010B" can be stored. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9401H".

Thus, by using the LDH update instruction, the data set in the upper 4 bits of the first area is set in the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are set to "0". , a process of setting the data set in the lower 4 bits of the first area to the lower 4 bits of the A register 104b and masking the upper 4 bits of the A register 104b with "0"; A process of adding 1 to the value of the register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these three processes.

As shown in FIG. 19(c), the command "LD E, (HL+)" is set at the line number "1103". "LD" is an LD update command by the LD update execution circuit 151, and "E" is the content specifying the E register 106b as the transfer destination. "(HL+)" designates the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source, and the value of the HL register 107 is set to 1 after the data is loaded. The content instructs to update the address stored in the HL register 107 by addition. As described above, the second area corresponding to "9401H" in the first initialization table 64k is set with "21H", which is the lower 1 byte of the address of the fraudulent radio wave detection counter 133. FIG. By executing "LD E, (HL+)" at line number "1103", "21H" is stored in E register 106b as shown in FIG. 20(c). As a result, the DE register 106 can store the address "0021H" of the unauthorized radio wave detection counter 133. FIG. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9402H".

In this way, by using the LD update instruction (“LD E, (HL+)”), the process of loading the data set in the second area of the first initialization table 64k into the E register 106b and the HL A process of adding 1 to the value of the register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

As shown in FIG. 19(c), the command "RET Z" is set at the line number "1104". "RET Z" in the line number "1104" terminates this data setting execution processing (FIG. 19(c)) when data for ending this data setting execution processing (FIG. 19(c)) is set in the E register 106b. This is an instruction to proceed to the next line number when the end data is not set in the E register 106b. As already explained, in this embodiment, "00H" is set as data for ending the data setting execution process. As shown in FIG. 20(c), "21H" is set in the E register 106b and end data is not set, so the process proceeds to line number "1105".

As shown in FIG. 19(c), the command "LD (DE), W" is set at the line number "1105". "LD" is the LD instruction, "(DE)" is the content specifying the area corresponding to the address stored in the DE register 106 as the transfer destination, and "W" specifies the W register 104a as the transfer source. It is the content to be done. As already described, the DE register 106 stores "0021H", which is the address of the unauthorized radio wave detection counter 133, and the W register 104a stores "00000101B", which is data for initial setting. Therefore, by executing "LD (DE), W" at the line number "1105", the data for initial setting is loaded into the illegal radio wave detection counter 133. FIG. As a result, the initial value "5" can be set to the illegal radio wave detection counter 133. FIG.

In this way, by using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the fraudulent radio wave detection counter 133, the first initialization is performed. The address data stored in the table 64k can be only the lower 1 byte of the address data (2 bytes) of the illegal radio wave detection counter 133. FIG. Therefore, the data capacity of the first initialization table 64k can be reduced compared to the configuration in which the entire address data (2 bytes) in the unauthorized radio wave detection counter 133 is stored in the first initialization table 64k.

As shown in FIG. 19(c), the command "LD E, (HL+)" is set to the line number "1106", similarly to the line number "1103". As shown in FIG. 20(c), the HL register 107 stores "9402H". As already described with reference to FIG. 18(a), the third area corresponding to "9402H" is set with "22H", which is the lower 1 byte of the address of the fraudulent magnetism detection counter 134. FIG. "22H" is loaded into the E register 106b by executing "LD E, (HL+)" at line number "1106". As a result, the DE register 106 can store "0022H", which is the address of the unauthorized magnetism detection counter 134. FIG. Also, as shown in FIG. 20(d), the value of the HL register 107 is incremented by 1, and the address stored in the HL register 107 is updated to "9403H".

In this way, by using the LD update instruction (“LD E, (HL+)”), the process of loading the data set in the third area of the first initialization table 64k into the E register 106b and the HL A process of adding 1 to the value of the register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

As shown in FIG. 19(c), the command "RET Z" is set to the line number "1107" in the same way as the line number "1104". "RET Z" at the line number "1107" is, like "RET Z" at the line number "1104", the end data ("00H") of this data setting execution process (Fig. ) is set, the data setting execution process is terminated, and if the end data is not set in the E register 106b, the command proceeds to the next line number. As shown in FIG. 20(d), "22H" is set in the E register 106b and end data is not set, so the process proceeds to line number "1108".

As shown in FIG. 19(c), the command "LD (DE), A" is set at the line number "1108". "LD" is the LD instruction, "(DE)" is the content specifying the area corresponding to the address stored in the DE register 106 as the transfer destination, and "A" specifies the A register 104b as the transfer source. It is the content to do. As already described, the DE register 106 stores "0022H", which is the address of the unauthorized magnetism detection counter 134, and the A register 104b stores "00001010B", which is the initial setting data. Therefore, by executing "LD (DE), A" at the line number "1108", the data for initial setting is loaded into the fraudulent magnetism detection counter 134. FIG. As a result, "10" can be set as the initial value in the fraudulent magnetism detection counter 134 .

In this way, by using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the fraudulent magnetism detection counter 134, the first initialization is performed. The address data stored in the table 64k can be only the lower 1 byte of the address data (2 bytes) of the fraudulent magnetism detection counter 134. FIG. Therefore, the data capacity of the first initialization table 64k can be reduced compared to the configuration in which the entire address data (2 bytes) of the fraudulent magnetism detection counter 134 is stored in the first initialization table 64k.

As shown in FIG. 19(c), the command "JR 4BTS10" is set at the line number "1109". "JR" is a JR instruction as an unconditional jump instruction, and "4BTS10" is a content specifying the start address of data setting execution processing as a jump destination. By executing "JR 4BTS10", the process advances to line number "1101" of this data setting execution process.

After that, using the data set in the address range of "9403H" to "9405H" in the first initialization table 64k (FIG. 18(a)), the instructions of line numbers "1102" to "1109" are executed. be. As shown in FIG. 18A, initial setting data for setting the abnormal vibration detection counter 135 to "15" as an initial value is stored in the upper 4 bits of the first area corresponding to "9403H" following "9402H". is set to "1111B". In addition, "0000B" is set as unused adjustment data in the lower 4 bits of the first area. In the second area corresponding to "9404H" following "9403H", "23H", which is the lower 1 byte of the address of the abnormal vibration detection counter 135, is set. Also, "00H" is set as end data in the third area corresponding to "9405H" following "9404H".

Returning to the description of the data setting execution process (Fig. 19(c)), at line number "1101", the process proceeds to line number "1102" without executing any command. As described above, in the first initialization table 64k, initial setting data ("1111B") is set in the upper 4 bits of the first area corresponding to the address 9403H, and adjustment data is set in the lower 4 bits. (“0000B”) is set. By executing "LDH WA, (HL+)" at line number "1102", as shown in FIG. "1111B" is set, and the upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "00001111B" for initialization can be stored in the W register 104a. "00000000B" for adjustment is stored in the A register 104b. Also, 1 is added to the value of the HL register 107 and the address stored in the HL register 107 is updated to "9404H".

As described above, "23H", which is the lower byte of the address corresponding to the abnormal vibration detection counter 135, is set in the second area corresponding to "9404H" in the first initialization table 64k. By executing "LD E, (HL+)" at line number "1103", "23H" is stored in E register 106b as shown in FIG. 20(f). As a result, the state in which "0023H", which is the address of the abnormal vibration detection counter 135, is stored in the DE register 106 can be established. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9405H".

Although "RET Z" is set in the following line number "1104", "23H" is set in the E register 106b as shown in FIG. is not set. Therefore, it proceeds to line number "1105".

As already described, the DE register 106 stores "0023H", which is the address of the abnormal vibration detection counter 135, and the W register 104a stores "00001111B", which is data for initial setting. Therefore, the initial setting data is loaded into the abnormal vibration detection counter 135 by executing "LD (DE), W" at the line number "1105". As a result, the abnormal vibration detection counter 135 can be set to "15" as an initial value.

In this way, by using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the abnormal vibration detection counter 135, the first initialization is performed. The address data stored in the table 64k can be only the lower 1 byte in the address data (2 bytes) of the abnormal vibration detection counter 135. FIG. Therefore, the data capacity of the first initialization table 64k can be reduced compared to the configuration in which the entire address data (2 bytes) of the abnormal vibration detection counter 135 are stored in the first initialization table 64k.

As described above, "00H", which is end data, is set in the third area corresponding to "9405H". By executing "LD E, (HL+)" at line number "1106", "00H" is loaded into E register 106b as shown in FIG. 20(g). Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9406H". This allows the HL register 107 to store the start address of the second initialization table 64m.

After that, in the state where the end data ("00H") is set in the E register 106b, "RET Z" is executed at the line number "1107", thereby ending this data setting process. As already described, when the data setting execution process ends at line number "1003" of the power-on setting process (FIG. 17(c)), the process proceeds to line number "1004".

Next, the case where the data setting execution process (FIG. 19(c)) is executed at line number "1004" of the power-on setting process (FIG. 17(c)) will be described in detail. In line number "1004", "9406H", which is the start address of the second initialization table 64m, is stored in the HL register 107, and the power failure area 131, the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer counter 132 The data setting execution process is executed in a state in which the upper 1-byte data ("00H") common to the addresses of the upper area of the D register 106a is stored.

In the data setting process executed at line number "1004", the data set in the address range of "9406H" to "9408H" in the second initialization table 64m is first used to set line numbers "1102" to " 1109" is executed. As already described with reference to FIG. 18(b), the high-order 4 bits of the first area corresponding to the start address "9406H" of the second initialization table 64m are set to "0" to clear the power failure area 131. "0000B" is set as the data of the first area, and "0000B" is set as "0" clear data for clearing the lower area of the fraud monitoring timer counter 132 to "0" in the lower 4 bits of the first area. It is In the second area corresponding to "9407H" following "9406H", "01H" which is the lower 1 byte of the address of the power failure area 131 is set. Also, in the third area corresponding to "9408H" following "9407H", "08H", which is the lower 1 byte of the address corresponding to the lower area of the fraud monitoring timer counter 132, is set.

At line number "1101" of the data setting execution process (Fig. 19(c)), as already explained, the process proceeds to line number "1102" without executing any command. As described above, "0" clear data ("0000B") is set in the upper 4 bits and lower 4 bits of the first area corresponding to "9406H" in the second initialization table 64m. Therefore, by executing "LDH WA, (HL+)", "0000B", which is the upper 4 bits of the first area, is set to the lower 4 bits of the W register 104a, and the W register 104a The upper 4 bits are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the W register 104a and the A register 104b can be in a state where data "00000000B" for "0" clearing is stored. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9407H".

As already explained, "00H" is stored in the D register 106a. Further, as described above, "01H", which is the lower byte of the address of the power failure area 131, is set in the second area corresponding to "9407H" in the second initialization table 64m. By executing "LD E, (HL+)" at line number "1103", "01H" is stored in E register 106b. As a result, the DE register 106 can store the address "0001H" of the power failure area 131 . Also, the value of the HL register 107 is incremented by 1, and the address stored in the HL register 107 is updated to "9408H".

"RET Z" is set in the following line number "1104", but "01H" is set in the E register 106b in the immediately preceding line number "1103", and end data ("00H") is not set, go to line number "1105".

As already described, the DE register 106 stores "0001H", which is the address of the power failure area 131, and the W register 104a stores "00000000B", which is data for clearing "0". Therefore, by executing "LD (DE), W" at the line number "1105", the "0" clear data is loaded into the power failure area 131, and the power failure area 131 is cleared to "0". be done. As already explained, the lowest bit of the power failure area 131 is provided with the power failure flag 131a. Therefore, the power failure flag 131a can be cleared to "0" by clearing the power failure area 131 to "0".

In this way, by using the common upper 1 byte ("00H") stored in advance in the D register 106a to specify the address of the power failure area 131, the second initialization table 64m (Fig. 18(b)) can be only the lower 1 byte in the address data (2 bytes) of the power failure area 131. FIG. Therefore, the data capacity of the second initialization table 64m can be reduced compared to the configuration in which the entire address data (2 bytes) of the power failure area 131 are stored in the second initialization table 64m.

As already explained, "00H" is set in the D register 106a. Further, as described above, "08H", which is the lower 1 byte in the address of the lower area of the fraud monitoring timer counter 132, is set in the third area corresponding to "9408H". "08H" is loaded into the E register 106b by executing "LD E, (HL+)" at line number "1106". As a result, the DE register 106 can store "0008H", which is the address of the lower area of the fraud monitoring timer counter 132 . Also, the value of the HL register 107 is incremented by 1, and the address stored in the HL register 107 is updated to "9409H".

"RET Z" is set in the following line number "1107", but "08H" is set in the E register 106b in the immediately preceding line number "1106", and end data ("00H") is not set, go to line number "1108".

As already explained, the DE register 106 stores "0008H" which is the lower area address of the fraud monitoring timer counter 132, and the A register 104b stores "00000000B" which is data for clearing "0". stored. Therefore, by executing "LD (DE), A" at the line number "1108", the data for clearing "0" is loaded into the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer The lower area of counter 132 is cleared to "0".

In this manner, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a, the lower area of the fraud monitoring timer counter 132 is addressed. 2 The address data stored in the initialization table 64m can be only the lower 1 byte of the address data (2 bytes) in the lower area of the fraud monitoring timer counter 132. FIG. Therefore, the data capacity of the second initialization table 64m can be reduced compared to the configuration in which the entire address data (2 bytes) in the lower area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can.

After that, "JR 4BTS10" is executed at line number "1109" to proceed to line number "1101" of this data setting execution process. Then, this time, the data set in the address range of "9409H" to "940BH" of the second initialization table 64m are used to execute the instructions of line numbers "1102" to "1109".

As shown in FIG. 18B, data "0000B" for clearing the upper area of the fraud monitoring timer counter 132 to "0" is stored in the upper 4 bits of the first area corresponding to "9409H" following "9408H". ” is set. In addition, "0000B" is set as unused adjustment data in the lower 4 bits of the first area. In the second area corresponding to "940AH" following "9409H", "09H" which is the lower 1 byte of the address ("0009H") corresponding to the upper area of the fraud monitoring timer counter 132 is set. In the third area corresponding to "940BH" following "940AH", "00H" is set as end data for the data setting execution process.

Returning to the description of the data setting execution process (Fig. 19(c)), at line number "1101", the process proceeds to line number "1102" without executing any command. As described above, in the second initialization table 64m, data for clearing "0" ("0000B") is set in the upper 4 bits of the first area corresponding to the address "9409H", and the lower 4 bits is set with adjustment data (“0000B”). By executing "LDH WA, (HL+)" at line number "1102", "0000B", which is the upper 4 bits of the first area, is set to the lower 4 bits of the W register 104a. The upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, data "00000000B" can be stored in the W register 104a and the A register 104b. Also, the value of the HL register 107 is incremented by 1, and the address stored in the HL register 107 is updated to "940AH".

As already explained, "00H" is set in the D register 106a. Further, as described above, the second area corresponding to 940AH in the second initialization table 64m (FIG. 18(b)) contains "09H" which is the lower 1 byte of the address corresponding to the upper area of the fraud monitoring timer counter 132. ” is set. By executing "LD E, (HL+)" at line number "1103", "09H" is stored in E register 106b. As a result, a state in which "0009H", which is the upper area address of the fraud monitoring timer counter 132, is stored in the DE register 106 can be achieved. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "940BH".

"RET Z" is set in the following line number "1104", but "09H" is set in the E register 106b in the immediately preceding line number "1103", and end data ("00H") is not set, go to line number "1105".

As already explained, the DE register 106 stores "0009H", which is the upper area address of the fraud monitoring timer counter 132, and the W register 104a stores "00000000B", which is data for clearing "0". stored. Therefore, by executing "LD (DE), W" at line number "1105", the data for clearing "0" is loaded into the upper area of the fraud monitoring timer counter 132. FIG. As a result, the upper area of the fraud monitoring timer counter 132 can be cleared to "0".

In this manner, by using the common high-order 1-byte data (“00H”) stored in the D register 106a in advance, the high-order area of the fraud monitoring timer counter 132 is addressed. 2 The address data stored in the initialization table 64m (FIG. 18(b)) can be only the lower 1 byte of the address data (2 bytes) in the upper area of the fraud monitoring timer counter 132. FIG. Therefore, the data capacity of the second initialization table 64m can be reduced compared to the configuration in which the entire address data (2 bytes) in the upper area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can.

As described above, "00H", which is end data, is set in the third area corresponding to "9405H". By executing "LD E, (HL+)" at line number "1106", "00H" is loaded into the E register 106b. Also, the value of the HL register 107 is incremented by 1, and the address stored in the HL register 107 is updated to "940CH".

After that, with the end data ("00H") set in the E register 106b, "RET Z" is executed at line number "1107", thereby ending this data setting execution processing. As already described, when the data setting execution process called at line number "1004" of the power-on setting process (FIG. 17(c)) is completed, the process proceeds to line number "1005".

Next, the clear handling process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 21(a). The clear handling process is executed in step S120 of the main process (FIG. 15). Note that the clear handling process is executed using a program for specific control and data for specific control.

In the clear handling process, first, it is determined whether or not the partial clear flag in the work area 121 for specific control is set to "1" (step S201). As already explained, the partial clear flag is a flag that allows the main CPU 63 to grasp that the partial clear process (step S107) has been executed, and also the partial clear flag in the return command transmission process (step S113) This is a flag that enables a return command to be sent to the sound and light side CPU 93 at the time of clearing. If an affirmative determination is made in step S201, the partial clear flag is cleared to "0" (step S202).

If a negative determination is made in step S201, it is determined whether or not the all clear flag in the work area 121 for specific control is set to "1" (step S203). As already explained, the all-clear flag is a flag that enables the main CPU 63 to recognize that the all-clear processing (step S114) has been executed. If a negative determination is made in step S203, this clear handling process is terminated. On the other hand, when an affirmative determination is made in step S203, the all clear flag is cleared to "0" (step S204).

If the process of step S202 has been performed, or if the process of step S204 has been performed, the setting process for clearing is executed (step S205), and this clearing handling process ends. In the clear setting process in step S205, a process for raising the security signal output to the management computer of the game hall from the LOW state to the HI state is executed. The security signal is a signal that enables the management computer of the game hall to recognize that the pachinko machine 10 has partially cleared (step S107) or completely cleared (step S114). In addition, in the clear time setting process in step S205, along with executing a process for performing a display corresponding to the result out in the first special figure display portion 37a and the second special figure display portion 37b, normal figure display A process for performing initial display in the section 38a is executed. The contents of the program for the clear setting process will be described later.

FIG. 21(b) is an explanatory diagram for explaining a storage area in which data is set in the setting process for clearing (step S205). As shown in FIG. 21(b), in the specific control work area 121, a security signal area 153 is provided in a 1-byte area corresponding to the address "0002H", and the security signal area 153 corresponds to the address "0005H". The first special figure display counter 154 is provided in the 1 byte area, the second special figure display counter 155 is provided in the 1 byte area corresponding to the address of "0006H", and the address of "0007H" A normal map display counter 159 is provided in the corresponding 1-byte area. In this way, the upper 1-byte data in the address data of the area and the counter to be set in the setting process at the time of clearing is commonly "00H".

The security signal area 153 is a 1-byte area containing a security signal flag 153a. FIG. 21(c) is an explanatory diagram for explaining the data structure of the security signal area 153. As shown in FIG. As shown in FIG. 21(c), a security signal flag 153a is set in the least significant bit (0th bit) in the security signal area 153, and the 1st to 7th bits in the security signal area 153 are unused. It's been a bit

The security signal flag 153a is a flag that enables the main side CPU 63 to grasp that the above-described security signal should be raised from the LOW state to the HI state. When the security signal flag 153a is set to "1", the external information setting process (step S517) is executed in the timer interrupt process (FIG. 26) described later, and is output to the management computer of the gaming hall. A security signal launch is performed.

The first special figure display counter 154 is a counter in which display data for displaying various patterns on the first special figure display section 37a is set, and the second special figure display counter 155 is the second special figure display section. 37b is a counter in which display data for displaying various patterns is set. The general-purpose map display counter 159 is a counter in which display data for displaying various patterns on the general-purpose map display unit 38a is set. These display counters 154, 155 and 159 consist of 1 byte, and the display data set in these display counters 154, 155 and 159 are 1 byte data.

Next, the clear setting table 64n stored in the main ROM 64 will be described. In the clearing setting table 64n, data for raising the security signal when the partial clearing process (step S107) or the all clearing process (step S114) is executed, the first special figure display section 37a and the second The data for performing the initial display in the data for performing the display corresponding to the deviation result in the 2 special figure display section 37b and the normal figure display section 38a are set. The clear setting table 64n is used in the clear setting process (step S205).

FIG. 22(a) is an explanatory diagram for explaining the clear setting table 64n. As shown in FIG. 22(a), in the main ROM 64, the setting table 64n for clearing is set in the address range from "9300H" to "9307H". The clear setting table 64n is similar to the first initialization table 64k and the second initialization table 64m already described with reference to FIGS. 18(a) and 18(b). The data structure is such that the first to third areas are repeated in the order of the third area.

FIG. 22(b) is an explanatory diagram for explaining the contents of the program for the setting process at the time of clear executed by the main CPU 63. As shown in FIG. The clear setting process is executed in step S205 of the clear correspondence process (FIG. 21(a)). As shown in FIG. 22B, "1201" to "1204" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LDT HL, 300H" is set at the line number "1201". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "300H" sets 12-bit numerical information "300H" as the transfer source. Content. As already described, the TP register 111 is set with "9000H", which is the reference address of the data table in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 300H", "9300H" obtained by adding "9000H" set in the TP register 111 to "300H" set as the transfer source is obtained. HL register 107 is loaded. As a result, the start address of the clear setting table 64n (FIG. 22(a)) can be set in the HL register 107. FIG.

In this way, by using the LDT instruction to set the start address of the clear setting table 64n in the HL register 107, the LD instruction is used to set the start address of the clear setting table 64n in the HL register 107. It is possible to reduce the data volume of the program for executing the setting process when clearing, compared to the setting configuration.

In line numbers "1202" to "1203", commands similar to line numbers "1002" to "1003" of the power-on setting process (FIG. 17(c)) are set. Specifically, the command "XOR D, D" is set at the line number "1202". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma designates the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". Thereby, it is possible to set the upper 1-byte data ("00H") in the address data of the security signal area 153, the first special figure display counter 154 and the second special figure display counter 155 to the D register 106a.

The command "CALL 4BTS10" is set at the line number "1203". "4BTS10" is the already explained data setting execution process (FIG. 19(c)). The instruction "CALL 4BTS10" is an instruction for calling a subroutine called data setting execution processing. At line number "1203", the data setting execution process is executed with the start address of the clear setting table 64n set in the HL register 107 and "00H" stored in the D register 106a.

A command "RET" is set at the line number "1204". By executing the command "RET", the clear setting process ends. As already explained, the clear setting process is a subroutine executed in step S205 of the clear handling process (FIG. 21(a)), and when the clear setting process ends, the clear handling process also ends. becomes.

Next, the case where the data setting execution process (FIG. 19(c)) is executed at the line number "1203" of the setting process at clearing (FIG. 22(b)) will be described. In the line number "1203", "9300H", which is the start address of the clear setting table 64n, is stored in the HL register 107, the security signal area 153, the first special figure display counter 154 and the second special figure display counter. The data setting execution process is executed while the upper 1-byte data ("00H") in the address data of 155 is stored in the D register 106a.

In the data setting execution process executed at line number "1203", the data set in the address range of "9300H" to "9302H" in the setting table 64n for clearing is first used to perform line numbers "1102" to " 1109" is executed. As shown in FIG. 22(a), the security signal flag 153a in the security signal area 153 is set to "1" in the upper 4 bits of the first area corresponding to the start address 9300H of the setting table 64n for clearing. "0001B" is set as the data, and "0011B" is set as the data for setting the display data of the pattern corresponding to the result of the first special figure display counter 154 in the lower 4 bits of the 1 area. is set. In the second area corresponding to "9301H" following "9300H", "02H" which is the lower 1 byte of the address of the security signal area 153 is set. In addition, "05H" which is the lower 1 byte of the address of the first special figure display counter 154 is set in the third area corresponding to "9302H" following "9301H".

At line number "1101" of the data setting execution process (Fig. 19(c)), as already explained, the process proceeds to line number "1102" without executing any command. As described above, "0001B" is set in the upper 4 bits of the first area corresponding to "9300H" in the clear setting table 64n, and "0011B" is set in the lower 4 bits. By executing "LDH WA, (HL+)" at line number "1102", "0001B", which is the upper 4 bits of the first area, is set to the lower 4 bits of the W register 104a. The upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0011B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, data "00000001B" can be set in the W register 104a, and data "00000011B" can be set in the A register 104b. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9301H".

As already explained, "00H" is stored in the D register 106a. Further, as described above, "02H" which is the lower 1 byte in the address of the security signal area 153 is set in the second area corresponding to "9301H" in the clear setting table 64n. By executing "LD E, (HL+)" at line number "1103", "02H" is stored in E register 106b. As a result, the state where "0002H", which is the address of the security signal area 153, is stored in the DE register 106 can be established. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9302H".

"RET Z" is set in the following line number "1104", but "02H" is set in the E register 106b in the immediately preceding line number "1103", and end data ("00H") is not set, the process proceeds to line number "1105" without terminating this data setting execution process.

As already explained, the DE register 106 stores "0002H", which is the address of the security signal area 153, and the W register 104a stores "00000001B". Therefore, "00000001B" is set in the security signal area 153 by executing "LD (DE), W" at line number "1105". Thereby, "1" can be set to the security signal flag 153a.

In this manner, the security signal area 153 is addressed using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a. Only the lower 1 byte in the address data (2 bytes) of the security signal area 153 can be stored in the address data stored in the . Therefore, the data capacity of the clear setting table 64n can be reduced compared to the configuration in which the entire address data (2 bytes) of the security signal area 153 is stored in the clear setting table 64n.

As already explained, "00H" is stored in the D register 106a. Further, as described above, "05H" which is the lower 1 byte in the address of the first special figure display counter 154 is set in the third area corresponding to "9302H". "05H" is loaded into the E register 106b by executing "LD E, (HL+)" at line number "1106". As a result, the DE register 106 can be in a state where "0005H", which is the address of the first special figure display counter 154, is stored. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9303H".

"RET Z" is set in the following line number "1107", but "05H" is set in the E register 106b in the immediately preceding line number "1106", and end data ("00H") is not set, the process proceeds to line number "1108" without terminating this data setting execution process.

As already explained, the DE register 106 stores "0005H", which is the address of the first special figure display counter 154, and the A register 104b stores "00000011B", which is display data for displaying the result of losing. is stored. Therefore, "00000011B" is loaded into the first special figure display counter 154 by executing "LD (DE), A" at line number "1108". Thereby, it is possible to set the display data of the pattern corresponding to the result of the deviation in the first special figure display counter 154 .

In this way, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a to specify the address of the first special figure display counter 154, when clearing The address data stored in the setting table 64n can be only the lower 1 byte in the address data (2 bytes) of the first special figure display counter 154. Therefore, compared to the configuration of storing the entire address data (2 bytes) of the first special figure display counter 154 in the setting table 64n when clearing, the data capacity of the setting table 64n when clearing can be reduced.

After that, "JR 4BTS10" is executed at line number "1109" to proceed to line number "1101" of this data setting execution process. Then, this time, the data set in the address range of "9303H" to "9305H" of the clear setting table 64n are used to execute the instructions of line numbers "1102" to "1109".

As shown in FIG. 22(a), in the upper 4 bits of the first area corresponding to "9303H" following "9302H", the second special figure display counter 155 is set to the display data of the pattern corresponding to the result. "0011B" is set as the data for In addition, "1010B" is set in the low-order 4 bits of the one area as data for performing initial display in the normal diagram display section 38a. "06H" which is the lower 1 byte of the address of the second special figure display counter 155 is set in the second area corresponding to "9304H" following "9303H". Also, in the third area corresponding to "9305H" following "9304H", "07H" which is the lower 1 byte of the address of the normal map display counter 159 is set.

Returning to the description of the data setting execution process (FIG. 19(c)), at line number "1101", the process proceeds to line number "1102" without executing any command. As described above, "0011B" is set in the upper 4 bits of the first area corresponding to the address of "9303H" in the clear setting table 64n, and "1010B" is set in the lower 4 bits. . By executing "LDH WA, (HL+)" at line number "1102", "0011B", which is the upper 4 bits of the first area, is set to the lower 4 bits of the W register 104a. The upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "1001B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the W register 104a can be set with "00000011B", which is the display data of the pattern corresponding to the result of the deviation, and the A register 104b can be set with "00001010B", which is the display data for the initial display. can be done. Also, "1" is added to the address stored in the HL register 107 to update it to "9304H".

As described above, "16H" which is the lower 1 byte of the address corresponding to the second special figure display counter 155 is set in the second area corresponding to "9304H" in the clear setting table 64n. "06H" is stored in the E register 106b by executing "LD E, (HL+)" at line number "1103". Thereby, it is possible to make the state where "0006H", which is the address of the second special figure display counter 155, is stored in the DE register 106. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9305H".

"RET Z" is set in the following line number "1104", but "06H" is set in the E register 106b in the immediately preceding line number "1103", and end data ("00H") is not set, the process proceeds to line number "1105" without terminating this data setting execution process.

As already explained, the DE register 106 stores "0006H", which is the address of the second special figure display counter 155, and the W register 104a stores "00000011B", which is the display data of the pattern corresponding to the result of the deviation. is stored. Therefore, "00000011B" is loaded into the second special figure display counter 155 by executing "LD (DE), W" at the line number "1105". Thereby, it is possible to set the display data of the pattern corresponding to the result of the deviation to the second special figure display counter 155 .

In this way, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a to specify the address of the second special figure display counter 155, when clearing The address data stored in the setting table 64n can be only the lower 1 byte in the address data (2 bytes) of the second special figure display counter 155. Therefore, compared to the configuration in which the entire address data (2 bytes) of the second special figure display counter 155 is stored in the clear setting table 64n, the data capacity of the clear setting table 64n can be reduced. .

As already explained, "00H" is stored in the D register 106a. In addition, as described above, in the third area corresponding to "9305H", "07H" which is the lower 1 byte in the address of the normal map display counter 159 is set. "07H" is loaded into the E register 106b by executing "LD E, (HL+)" at line number "1106". As a result, the DE register 106 can be set to a state in which "0007H", which is the address of the normal diagram display counter 159, is stored. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9306H".

"RET Z" is set in the following line number "1107", but "07H" is set in the E register 106b in the immediately preceding line number "1106", and end data ("00H") is not set, the process proceeds to line number "1108" without terminating this data setting execution process.

As already explained, the DE register 106 stores "0007H" which is the address of the normal map display counter 159, and the A register 104b stores "00001010B" which is display data for initial display. . Therefore, by executing "LD (DE), A" at line number "1108", "00001010B" is loaded into the normal diagram display counter 159. FIG. As a result, display data for initial display can be set in the normal map display counter 159 .

In this way, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a to specify the address of the general pattern display counter 159, the setting table when clearing The address data stored in 64n can be only the lower 1 byte in the address data (2 bytes) of the normal figure display counter 159. FIG. For this reason, the data capacity of the clear setting table 64n can be reduced compared with the structure which memorize|stores the whole address data (2 bytes) of the normal figure display counter 159 in the clear setting table 64n.

After that, "JR 4BTS10" is executed at line number "1109" to proceed to line number "1101" of this data setting execution process. Then, this time, the data set in the address range of "9306H" to "9307H" of the clear setting table 64n are used to execute the instructions of line numbers "1102" to "1104".

As shown in FIG. 22A, unused adjustment data (“00000000B”) is set in the first area corresponding to “9306H” following “9305H”. In the second area corresponding to "9307H" following "9306H", "00H" is set as end data for the data setting execution process.

Returning to the description of the data setting execution process (Fig. 19(c)), at line number "1101", the process proceeds to line number "1102" without executing any command. As described above, "00000000B" is set in the first area corresponding to the address of "9306H" in the clear setting table 64n. By executing "LDH WA, (HL+)" at line number "1102", "0000B", which is the upper 4 bits of the first area, is set to the lower 4 bits of the W register 104a. The upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". Also, "1" is added to the address stored in the HL register 107 to update it to "9307H".

As described above, the end data ("00H") is set in the second area corresponding to "9307H" in the clear setting table 64n. "00H" is loaded into the E register 106b by executing "LD E, (HL+)" at line number "1103". Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9308H".

After that, in the state where the end data is set in the E register 106b, "RET Z" is executed at the line number "1104", thereby ending this data setting execution processing. As already described, when the data setting execution process ends at line number "1203" of the setting process at clear (FIG. 22(b)), the process proceeds to line number "1204".

Next, before describing the random number maximum value setting process executed in step S119 of the main process (FIG. 15), the random number maximum value table 64p stored in the main ROM 64 will be described. As already explained, in the random number maximum value setting process, the maximum values of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the variation type counter C5 and the general electric random number counter C6 are set. The random number maximum value table 64p is a data table used to set maximum value data in the maximum value counters CN1 to CN6 corresponding to these counters C1 to C6.

FIG. 23(a) is an explanatory diagram for explaining the data configuration of the random number maximum value table 64p. As shown in FIG. 23(a), the random number maximum value table 64p is stored in the main ROM 64 in the address range of "9200H" to "9208H". In the area corresponding to "9200H" in the random number maximum value table 64p, "63H" ("99"), which is the maximum value data of the jackpot type counter C2, is set. As already explained, the maximum value of the jackpot type counter C2 is set to the jackpot type maximum value counter CN2.

"EEH" ("238"), which is the maximum value data of the reach random number counter C3, is set in the area corresponding to "9201H" following "9200H". As already explained, the maximum value of the reach random number counter C3 is set in the reach maximum value counter CN3. "C6H" ("198"), which is the maximum value data of the fluctuation type counter C5, is set in the area corresponding to "9202H" following "9201H". As already explained, the maximum value of the fluctuation type counter C5 is set in the fluctuation type maximum value counter CN5. In the area corresponding to "9203H" following "9202H", "FAH" ("250"), which is the maximum value data of the general electric random number counter C6, is set. As already explained, the maximum value of the general electric random number counter C6 is set in the general electric maximum value counter CN6.

In the area corresponding to "9204H" following "9203H", "3FH", which is the lower 1 byte of "1F3FH" ("7999"), which is the maximum value data of the winning random number counter C1, is set. In the area corresponding to "9205H", "1FH" which is the upper 1 byte of the maximum value data is set. As already explained, the maximum value of the winning random number counter C1 is set to the winning maximum value counter CN1. Specifically, "3FH", which is the lower 1 byte of the maximum value data, is set in the lower area of the winning maximum value counter CN1, and the upper byte of the maximum value data is set in the upper area of the winning maximum value counter CN1. "1FH", which is 1 byte, is set. In the area corresponding to "9206H" following "9205H", "3FH", which is the lower 1 byte of "1F3FH" ("7999"), which is the maximum value data of the random number initial value counter C4, is set. "9207H" is set to "1FH" which is the upper 1 byte of the maximum value data. As already explained, the maximum value of the random number initial value counter C4 is set in the initial value maximum value counter CN4. Specifically, "3FH", which is the lower byte of the maximum value data, is set in the lower area of the initial value maximum value counter CN4, and the maximum value data is set in the upper area of the initial value maximum value counter CN4. "1FH" which is the upper 1 byte of is set. "00H" is set as end data in the area corresponding to "9208H" following "9207H".

In the random number maximum value setting process (step S119), the HL register 107 is set to "9200H", which is the start address of the random number maximum value table 64p. As a result, the maximum value data of the jackpot type counter C2 is selected as the maximum value data to be set. The random number maximum value table 64p adds 1 to the value of the HL register 107 and sequentially updates the address data stored in the HL register 107, thereby increasing the maximum value data of the jackpot type counter C2 → the maximum value of the reach random number counter C3. Value data→maximum value data of fluctuation type counter C5→maximum value data of general electric random number counter C6→lower 1 byte of maximum value data of winning random number counter C1→upper 1 byte of maximum value data of winning random number counter C1→initial random number The data structure is such that the maximum value data to be set can be updated in the order of the lower 1 byte of the maximum value data of the value counter C4→the upper 1 byte of the maximum value data of the random number initial value counter C4.

As already described with reference to FIG. 12B, the maximum value counters CN1 to CN6 are set in the address range of "0019H" to "0020H" in the work area 121 for specific control. In the random number maximum value setting process (step S119), the BC register 105 is set to "0019H", which is the leading address of the address range. As a result, the jackpot type maximum value counter CN2 is selected as the setting target counter. In the work area 121 for specific control, the maximum value counters CN1 to CN6 add 1 to the value of the BC register 105 and update the address data stored in the BC register 105 in order to obtain the maximum value for the jackpot type. Counter CN2→maximum value counter for reach CN3→maximum value counter for fluctuation type CN5→maximum value counter for normal electric current CN6→lower area of maximum value counter for winning CN1→upper area of maximum value counter for winning CN1→maximum for initial value The counters to be set are set in such a manner that the counters to be set can be updated in the order of the lower area of the value counter CN4→the upper area of the initial value maximum value counter CN4.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 23(b). The random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed using a program for specific control and data for specific control.

In the random number maximum value setting process, first, a maximum value setting start process is executed (step S301). In the maximum value setting start process, "9200H", which is the start address of the random number maximum value table 64p, is set in the HL register 107, and "0019H", which is the address of the jackpot type maximum value counter CN2 in the work area 121 for specific control. ” is set in the BC register 105 . In the random number maximum value setting process, an address corresponding to the maximum value data to be set in the maximum random number table 64p is set in the HL register 107, and the maximum value data to be set is set in the BC register 105. An address corresponding to the setting target counter to be set is set. By setting "9200H" in the HL register 107, the maximum value data of the jackpot type counter C2 is selected as the maximum value data to be set. The maximum value data to be set is updated in step S302, which will be described later. In addition, by setting "0019H" in the BC register 105, the jackpot type maximum value counter CN2 is selected as the setting target counter. The setting target counter is updated in the setting target update process (step S305), which will be described later. Details of the maximum value setting start process will be described later.

After executing the maximum value setting start process in step S301, the command "LD A, (HL+)" is executed (step S302). "LD" is an LD update command by the LD update execution circuit 151, "A" is the content specifying the A register 104b as the transfer destination, and "(HL+)" is stored in the HL register 107 as the transfer source. It specifies the maximum value data stored in the area corresponding to the address, and updates the address stored in the HL register 107 by adding 1 to the value of the HL register 107 after loading the maximum value data. It is a content that instructs to do. By executing "LD A, (HL+)", the maximum value data ("63H") corresponding to the address data ("9200H") stored in the HL register 107 is loaded into the A register 104b. Thereby, the maximum value data to be set can be set in the A register 104b. After loading the maximum value data, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9201H". Thereby, the maximum value data to be set can be updated.

In this way, by using the LD update instruction, the processing of loading the maximum value data selected as the setting target in the random number maximum value table 64p into the A register 104b and the processing of loading the HL register 107 after loading the maximum value data. A process of adding 1 to the value and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

The processes of steps S302 to S305 are repeatedly executed until an affirmative determination is made in step S303, which will be described later. Every time the process of step S302 is executed, the maximum value data of the jackpot type counter C2 → the maximum value data of the reach random number counter C3 → the maximum value data of the variation type counter C5 → the maximum value data of the general electric random number counter C6 → the random number Lower 1 byte of maximum value data of counter C1→Higher 1 byte of maximum value data of random number counter C1→Lower 1 byte of maximum value data of random number initial value counter C4→Higher 1 byte of maximum value data of random number initial value counter C4 The maximum value data to be set is updated in byte order. Further, when the process of step S302 is executed with the address stored in the HL register 107 updated to "9208H", end data ("00H") is set in the A register 104b.

After executing the process of step S302, it is determined whether or not the end data ("00H") is set in the A register 104b (step S303), and if the end data is set in the A register 104b If (step S303: YES), the present random number maximum value setting process is terminated.

If a negative determination is made in step S303, maximum value data setting processing is executed (step S304). In the maximum value data setting process, an instruction "LD (BC), A" is executed. "LD" is a load instruction, "(BC)" is the content specifying the counter to be set corresponding to the address stored in the BC register 105 as the transfer destination, and "A" is the A register 104b as the transfer source. is the content that specifies By executing "LD (BC), A", the maximum value data stored in the A register 104b is loaded into the counter selected as the counter to be set among the maximum value counters CN1 to CN6. Thereby, the maximum value data can be set in the setting target counter.

After that, setting target update processing is executed (step S305). In the setting target update process, an instruction "INC BC" is executed. "INC" is an instruction to add "1" to an addition target, and "BC" is a content specifying the value of the BC register 105 as the addition target. By executing “INC BC”, “1” is added to the value of the BC register 105 . As a result, the maximum value counters CN1 to CN6 selected as setting target counters are updated. Every time the setting target update process is executed in step S305, the jackpot type maximum value counter CN2 → reach maximum value counter CN3 → variation type maximum value counter CN5 → normal electric maximum value counter CN6 → hit maximum value The counters to be set are updated in the order of the lower area of the counter CN1→the upper area of the winning maximum value counter CN1→the lower area of the initial value maximum value counter CN4→the upper area of the initial value maximum value counter CN4.

After executing the setting target update process in step S305, the process returns to step S302, and the processes of steps S302 to S305 are repeated until the end data is stored in the A register 104b and an affirmative determination is made in step S303. Execute. Thereby, the maximum value data can be set in the maximum value counters CN1 to CN6.

<First LDY instruction>
Next, before describing the program contents of the maximum value setting start process (Fig. 24(b)), the first LDY instruction included in the program of the maximum value setting start process will be described. FIG. 24(a) is an explanatory diagram for explaining the data structure of the machine language of the first LDY instruction, and FIG. 24(b) is an explanatory diagram for explaining the program contents of the maximum value setting start process.

As shown in FIG. 24(b), the maximum value setting start processing program includes a first LDY command "LDY BC, 19H". The main CPU 63 can execute the first LDY instruction as a transfer instruction for transferring data. As shown in FIG. 9, the main MPU 62 has a first LDY execution circuit 156 . The first LDY execution circuit 156 is a dedicated circuit for executing the first LDY instruction.

The instruction code of the first LDY instruction has a configuration of "LDY transfer destination, transfer source". A pair register is set as a "transfer destination" in the first LDY instruction. The WA register 104, BC register 105, DE register 106 or HL register 107 are set as the "transfer destination" in the first LDY instruction. In the first LDY instruction, a 1-byte numerical value (for example, "19H") is set as the "transfer source".

In the first LDY instruction, the 2-byte numerical information obtained by adding the 2-byte numerical information set in the IY register 109 to the 1-byte numerical information set in the "transfer source" is set as the "transfer destination". ” is loaded into the pair register. As already described, in the present embodiment, the IY register 109 is set with "0000H" as the specific control reference address at the start of the specific control process, and at the start of the non-specific control process, the non-specific control address is set. "0300H" is set as the reference address for use.

By executing "LDY BC, 19H" with "0000H" set in the IY register 109 in advance, "0019H" is set in the BC register 105 in the same way as when "LD BC, 0019H" is executed. ” is loaded. By executing "LDY BC, 19H" with "0300H" set in the IY register 109 in advance, the BC register 105 is set to "0319H" is loaded.

The data configuration of the machine language of the first LDY instruction will be described while exemplifying "LDY BC, 19H" as a specific instruction code of the first LDY instruction. As shown in FIG. 24(a), in the machine language of the first LDY instruction, data of "transfer source" is changed to "transfer destination" in the same way as the machine language of the LD instruction already described with reference to FIG. 17(b). , transfer destination designating data designating the BC register 105 as the “transfer destination”, and transfer source designating data designating the “transfer source”. In the machine language of the first LDY instruction, the total data capacity of the instruction data and transfer destination designation data is 2 bytes, and the data capacity of the transfer source designation data is 1 byte. In the case of "LDY HL, 19H", 1-byte numerical information "19H" is set as the "transfer source", and the 1-byte numerical information "19H" is set in the machine language of the first LDY instruction. It is included as it is as transfer source designation data. Thus, the total data capacity of the machine language of the first LDY instruction is 3 bytes.

On the other hand, as already explained with reference to FIG. 17(b), in the machine language of the LD instruction, the total data capacity of the instruction data and transfer destination designation data is 2 bytes, and the data capacity of the transfer source designation data is 2 bytes. The total data capacity of the machine language of the LD instruction is 4 bytes. Thus, when "0000H" is stored in the IY register 109, when the address of the data table stored in the main ROM 64 is loaded into a pair register such as the BC register 105, instead of the LD instruction, By using the first LDY instruction in , the machine language of the instruction to load the data of the "source" to the "destination" can be reduced by one byte. Thereby, the data capacity of the program in the main ROM 64 can be reduced.

Next, the program content of the maximum value setting start process executed by the main CPU 63 will be described with reference to FIG. 24(b). The maximum value setting start process is executed in step S301 of the random number maximum value setting process (FIG. 23(b)). As shown in FIG. 24B, "1301" to "1303" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LDT HL, 200H" is set at the line number "1301". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "200H" sets 12-bit numerical information "200H" as the transfer source. Content. As already described, the TP register 111 is set with "9000H", which is the reference address of the data table in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 200H", "9200H" obtained by adding "9000H" set in the TP register 111 to "200H" set as the "transfer source" ” is loaded into the HL register 107 . As a result, the start address of the random number maximum value table 64p (FIG. 23(a)) can be set in the HL register 107. FIG.

Thus, by setting the start address of the maximum random number table 64p in the HL register 107 using the LDT instruction, the start address of the maximum random number table 64p can be set in the HL register 107 using the LD instruction. The data volume of the program for executing the maximum value setting start process can be reduced compared to the setting configuration.

The command "LDY BC, 19H" is set at the line number "1302". "LDY" is the first LDY instruction by the first LDY execution circuit 156, "BC" is the content specifying the BC register 105 as the transfer destination, and "19H" is a 1-byte numerical value of "19H" as the "transfer source." This is the content for setting information. As already explained, "0000H" is set in the IY register 109 as the specific control reference address in step S103 of the main process (FIG. 15). Therefore, by executing "LDY BC, 19H", "0019H" obtained by adding "0000H" set in the IY register 109 to "19H" set as the "transfer source" ” is loaded into the BC register 105 . As a result, the address of the jackpot type maximum value counter CN2 in the specific control work area 121 can be set in the BC register 105 .

In this way, the address data (2 bytes) of the jackpot type maximum value counter CN2 is set in the BC register 105 by using the first LDY instruction for specifying the address by setting the address data of 1 byte. , the data capacity of the program for executing the maximum value setting start process is reduced compared to the configuration in which the address data is set in the BC register 105 using the LD instruction for specifying the address by setting the address data of 2 bytes. can be reduced.

The command "RET" is set at the line number "1303". As already explained, the maximum value setting start process is a subroutine executed in step S301 of the random number maximum value setting process (FIG. 23(b)). Therefore, by executing the command "RET", the process proceeds to step S302 of the random number maximum value setting process.

Next, the first clear processing performed in the partial clear processing (step S107) and the all clear processing (step S114) will be described. As already explained, the first clearing process is a process of clearing the work area 121 for specific control set at addresses "0000H" to "02FFH" in the main RAM 65 to "0". As already described, the specific control reference address "0000H" is set in the IY register 109 in step S103 of the main process (FIG. 15). The first clear processing is executed with the specific control reference address set in the IY register 109 . In the first clearing process, the HL register 107 is loaded with "0000H", which is the start address of the work area 121 for specific control, by executing the instruction "LDY HL, 00H". After that, by executing the instruction "LD BC, 0300H", the BC register 105 is loaded with "0300H", which is the end address of the first clear processing. After that, until the end address is stored in the HL register 107, the memory area specified by the address stored in the HL register 107 is cleared to "0" and the address stored in the HL register 107 is cleared. is repeatedly executed. Then, when the end address is stored in the HL register 107, the first clear processing ends.

In the main process (FIG. 15), the partial clear process (step S107) or the full clear process (step S114) is executed while the specific control reference address is set in the IY register 109. In the first clearing process, using the specific control reference address stored in the IY register 109, "0000H", which is the top address of the work area 121 for specific control, can be specified.

When using the LD instruction, the address data of the start address included in the instruction code of the LD instruction must be the entire 2-byte address data ("0000H"). , the address data included in the instruction code of the first LDY instruction can be only the lower 1 byte ("00H") in the 2-byte address data. By setting the start address (“0000H”) of the work area 121 for specific control in the HL register 107 using the first LDY instruction (“LDY HL, 00H”), the LD instruction can be used to Compared to the configuration in which the start address is set in the HL register 107, the data capacity of the program can be reduced.

Next, setting value update processing executed by the main CPU 63 will be described with reference to the flowchart of FIG. The set value update process is executed in step S117 of the main process (FIG. 15). Note that the set value update process is executed using a program for specific control and data for specific control.

In the set value update process, first, a set value updating flag provided in the work area 121 for specific control is set to "1" (step S401). The set value updating flag is a flag that enables the main CPU 63 to recognize that the set value update process is being executed. The set value updating flag is cleared to "0" in step S411, which will be described later. After the process of step S401 is performed, interrupt permission setting is performed to switch from the state in which the occurrence of timer interrupt processing is prohibited to the state in which it is permitted (step S402). Although the details will be described later, the display control of the first to third notification display devices 69a to 69c is executed in the management process in step S518 of the timer interrupt process (FIG. 26). By permitting the generation of the timer interrupt process, the management process (step S518) can be executed. In the management process, on condition that the setting value updating flag is set to "1", the number corresponding to the value of the setting value counter in the specific control work area 121 is displayed on the third notification display device 69c. The display control of the third notification display device 69c is performed so that it is displayed. The set value counter is, as already explained, a counter for the main side CPU 63 to specify which set value the pachinko machine 10 is set to. When the value of the set value counter is updated while the set value updating flag is set to "1", the display of the set value on the third notification display device 69c is also updated. The manager of the game hall can grasp the current setting state of the pachinko machine 10 by confirming the third notification display device 69c when changing the setting value.

After that, the set value counter in the work area 121 for specific control is set to "1" (step S403). As a result, when the setting value update process is executed, the setting value becomes "setting 1" regardless of the setting value up to that point.

Thereafter, on the condition that the setting key insertion portion 68a has not been turned off (step S404: NO), it is determined whether or not the update button 68b has been pressed once (step S405). Specifically, it is determined whether or not the signal from the sensor that detects the pressing operation of the update button 68b has switched from the LOW state to the HI state. If a negative determination is made in step S405, the process returns to step S404 to determine whether or not the setting key insertion portion 68a has been turned off.

If the update button 68b has been pressed once (step S405: YES), 1 is added to the set value counter of the work area 121 for specific control (step S406). If the value of the set value counter after adding 1 exceeds "6" (step S407: YES), the set value counter is set to "1" (step S408). As a result, each time the update button 68b is pressed once, the set value is updated to the value one step higher. going back.

If a negative determination is made in step S407, or if the process of step S408 is executed, the process returns to step S404 to determine whether or not the setting key insertion portion 68a has been turned off. If the OFF operation has not been performed (step S404: NO), the processes after step S405 are executed again. On the other hand, if the OFF operation has been performed (step S404: YES), interrupt prohibition is set to prohibit the occurrence of timer interrupt processing (step S409). This completes the display of the set values on the third notification display device 69c.

Thereafter, a set value update command transmission process is executed (step S410). In the set value update command transmission process, a set value update command is transmitted to the sound and light side CPU 93 . The set value update command is a command for allowing the sound and light side CPU 93 to recognize that the set value update process has ended and to allow the sound and light side CPU 93 to grasp the updated set value of the pachinko machine 10 . The set value update command includes data stored in the set value counter in the work area 121 for specific control. After that, the setting value updating flag in the work area 121 for specific control is cleared to "0" (step S411), and this setting value updating process is terminated.

<Timer interrupt processing>
Next, timer interrupt processing in this embodiment executed by the main CPU 63 will be described with reference to the flowchart of FIG. The timer interrupt process is executed periodically (for example, every 4 milliseconds) while the set value update process (step S117) or the residual process (steps S121 to S124) is being executed in the main process (FIG. 15). . Note that the processing of steps S501 to S517 in the timer interrupt processing is executed using a program for specific control and data for specific control. Further, among the management processing (FIG. 56A) in step S518, processing other than the management execution processing (step S1603), which will be described later, is executed using the specific control program and specific control data. The management execution process (step S1603) is executed using a non-specific control program and non-specific control data.

In the timer interrupt processing, power failure information storage processing is first executed (step S501). In the power failure information storage process, it is monitored whether or not a power failure signal corresponding to the occurrence of a power failure is received from the power failure monitoring board 67, and when the occurrence of a power failure is specified, the power failure process is executed and then an infinite loop is performed. Become. In the power failure processing, the power failure flag 131a in the power failure area 131 already described with reference to FIG. 16B is set to "1", the checksum is calculated, and the calculated checksum is stored.

After that, fraud detection processing is executed to monitor whether or not a predetermined event set as a monitoring target for fraud has occurred (step S502). In the fraud detection process, the occurrence of an event in which an unauthorized radio wave is detected, an event in which an unauthorized magnetism is detected, and an event in which an abnormal vibration is detected is monitored. ), if an event in which unauthorized radio waves are detected is identified 5 times, an event in which unauthorized magnetism is detected is identified 10 times, or an event in which abnormal vibration is detected is identified 15 times. Execute the fraud detection response process. Although the details will be described later, the game stop flag provided in the work area 121 for specific control is set to "1" in the fraud detection handling process. The game stop flag is a flag that enables the main side CPU 63 to grasp whether or not the progress of the game is stopped. By setting the game stop flag to "1", the process of steps S506 to S518 in the timer interrupt process is not executed, that is, the progress of the game is stopped. Details of the fraud detection process will be described later.

In the subsequent step S503, it is determined whether or not the set value updating flag in the work area 121 for specific control is set to "1". As already explained, the set value updating flag is a flag that enables the main CPU 63 to recognize that the set value update process (FIG. 25) is being executed. If the setting value updating flag is set to "1" (step S503: YES), that is, if the setting value updating process (FIG. 25) is being executed, the processes of steps S504 to S517 are executed. Without it, the process proceeds to step S518.

If a negative determination is made in step S503, a first random number update process is executed (step S504). In the first random number update process, a process for updating the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the fluctuation type counter C5 and the general electric random number counter C6 is executed. The first random number update process (step S504) is executed on the condition that the setting value updating flag is not set to "1". Therefore, during the execution of the set value update process (FIG. 25), the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the fluctuation type counter C5 and the general electric random number counter C6 are updated. is not performed. As already explained, in the main process (FIG. 15), the setting value update process (step S117) is executed before the random number maximum value setting process (step S119) is executed. Since generation of the timer interrupt process (FIG. 26) is permitted in step S402 of the set value update process (FIG. 25), the timer interrupt process (FIG. 26) is executed even during execution of the set value update process. By preventing these counters C1-C6 from being updated during execution of the set value update process, these counters C1-C6 can be updated before the random number maximum value setting process (step S119) is executed. is prevented from being started. Details of the first random number update process will be described later.

In the subsequent step S505, it is determined whether or not the progress of the game is stopped by determining whether or not the game stop flag is set to "1". When the game stop flag is set to "1" (step S505: YES), this timer interrupt process is terminated without executing the processes of steps S506 to S518. On the other hand, if a negative determination is made in step S505, the processing after step S506 is executed.

In step S506, port output processing is executed. In the port output process, when the output information has been set in the previous timer interrupt process, a process for outputting corresponding to the output information to the various driving units 32b and 34b is executed. For example, when the information to switch the special electric prize winning device 32 to the open state is set, the output of the drive signal to the drive unit 32b for the special electric is started, and when the information to switch to the closed state is set stops the output of the drive signal. In addition, when information is set to switch the general electric accessory 34a of the second operation port 34 to the open state, the output of the drive signal to the general electric drive unit 34b is started to switch to the closed state. When the information is set, the output of the drive signal is stopped.

After that, read processing is executed (step S507). In the reading process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in future processing.

After that, ball entry detection processing is executed (step S508). In the ball-entering detection process, signals received from the ball-entering detection sensors 42a to 49a are read, and based on the reading results, the out port 24a, the general prize-winning port 31, the special electric prize-winning device 32, and the first operation port 33 , the presence or absence of the ball entering the second operating port 34 and the through gate 35 is specified. In the ball-entering detection process in step S508, when the fall of the detection signal of the first operation opening detection sensor 46a from the HI state to the LOW state is detected, the first operation winning flag in the work area 121 for specific control is set to "1". ” is set. The first operation winning flag is a flag that enables the main CPU 63 to recognize that the game ball has entered the first operation opening 33 . In addition, in the ball-entering detection process in step S508, when the fall of the detection signal of the second operation opening detection sensor 47a from the HI state to the LOW state is detected, the second operation winning flag in the work area 121 for specific control is set. Set to "1". The second operation winning flag is a flag that enables the main CPU 63 to recognize that the game ball has entered the second operation opening 34 . The main side CPU 63, in the reservation information acquisition process in step S901 of the special special electric control process (FIG. 30) described later, based on the states of the first operation winning flag and the second operation winning flag, the first operation port 33 And whether or not the game ball has entered the second operating port 34 is grasped.

After that, timer update processing is executed to collectively update numerical information of a plurality of types of timer counters provided in the work area 121 for specific control (step S509). In this case, the timer counters that are updated by subtracting the stored numerical information are collectively handled. may be configured.

Thereafter, a launch control process for controlling the launch of game balls is executed (step S510). In a situation where the shooting operation to the shooting operation device 28 is continued, one game ball is shot in 0.6 seconds, which is a predetermined shooting cycle. In the following step S511, as an input state monitoring process, based on the information read in the reading process of step S507, disconnection confirmation of each ball detection sensor 42a to 49a, opening confirmation of the game machine main body 12 and the front door frame 14 are performed. I do.

After that, a special figure special electric control process for performing execution control of the game round and execution control of the opening and closing execution mode is executed (step S512). In addition, the detail of special figure special electric control processing is mentioned later. After that, the general map general electric control process is executed (step S513). In the general map general electric control process, when the prize to the through gate 35 is generated, the processing for acquiring the reservation information on the general map side is executed, and when the reservation information on the general map side is stored Then, open determination is performed for the reservation information, and processing for performing the production for the normal map is performed with the open determination as a trigger. Moreover, based on the result of open determination, the process which opens and closes the universal electrical accessory 34a of the 2nd operation|movement opening 34 is performed. In this case, if the support mode is the low-frequency support mode, the corresponding process is executed, and if the support mode is the high-frequency support mode, the corresponding process is executed. Further, when the opening/closing execution mode is selected, the low-frequency support mode is set even if the immediately preceding support mode is the high-frequency support mode.

A work area 121 for specific control is provided with a mode data area including a high frequency support mode flag and an opening/closing execution mode flag. The mode data area consists of 1 byte. The high-frequency support mode flag is a flag that enables the main CPU 63 to grasp whether or not the high-frequency support mode is on. It is a flag that can be grasped by The high frequency support mode flag is set in the 0th bit of the mode data area, and the opening/closing execution mode flag is set in the 1st bit of the mode data area. The high-frequency support mode flag is set to "1" when the opening/closing execution mode ends regardless of the type of the jackpot result that triggered the execution. In the normal/universal power control process (step S513), the main CPU 63 determines whether or not the high-frequency support mode is set based on the state of the high-frequency support mode flag, and based on the state of the opening/closing execution mode flag. Specifies whether or not the open/close execution mode is set.

After executing the general map general electric control process in step S513, the display control process is executed (step S514). In the display control process, based on the processing results of steps S512 and S513 immediately before, the increase or decrease number of the first special figure side reservation information related to the first special figure display unit 37a is reflected in the first special figure reservation display unit 37c. Setting the output information for, setting the output information for reflecting the increase/decrease number of the second special figure side reservation information related to the second special figure display unit 37b in the second special figure reservation display unit 37d, and the normal figure display unit Output information is set for reflecting the increase/decrease number of the normal map side reserved information related to 38a in the normal map reserved display unit 38b. In addition, in the display control process in step S514, based on the processing result of step S512 and step S513 immediately before, the output information for updating the display contents of the first special figure display unit 37a and the second special figure display unit 37b In addition to setting, output information is set for updating the display contents of the normal map display section 38a. Furthermore, in the display control processing in step S514, output information for updating the display content of the round display section 39 is set based on the processing result of the previous step S513. Details of the display control processing will be described later.

After that, the content of the command and signal received from the payout side CPU 83 is confirmed, and payout state reception processing is executed for performing processing corresponding to the confirmation result (step S515). Also, a payout output process for setting the prize ball command as an output target is executed (step S516).

Thereafter, external information setting processing is executed (step S517). In the external information setting process, as already explained, when the security signal flag 153a in the security signal area 153 (FIG. 21(c)) is set to "1", the information is output to the management computer of the gaming hall. A process for raising the security signal from the LOW state to the HI state is executed, and the security signal flag 153a is cleared to "0". By raising the security signal, it is possible for the management computer of the game hall to grasp that the partial clearing process (step S107) or the all clearing process (step S114) has been executed. Also, in the external information setting process in step S517, the start and end of the output of the external signal are controlled according to the processing results of the various processes executed in the current timer interrupt process.

If an affirmative determination is made in step S503, or if the process of step S517 is carried out, a subroutine program corresponding to the management process is executed by a call command (step S518). When executing the management process (step S518), a subroutine program corresponding to the management process set in the specific control program is executed. Information for specifying the return address of the timer interrupt process after execution of the process is written in the stack area 123 for specific control by a push instruction. Then, when the management process is completed, information for specifying the return address is read out by a pop instruction, and the program for the timer interrupt process indicated by the return address is returned to. Details of the management processing will be described later.

As already explained, when the set value updating flag in the work area 121 for specific control is set to "1" (step S503: YES), that is, when the set value update process (FIG. 25) is being executed , the processing of steps S504 to S517 is not executed, but the management processing (step S518) is executed. As a result, during execution of the set value update process (FIG. 25), the third notification is performed so that the number corresponding to the value of the set value counter in the specific control work area 121 is displayed on the third notification display device 69c. Display control of the display device 69c can be performed.

Next, the first random number update process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 27(a). The first random number update process is executed in step S504 of the timer interrupt process (FIG. 26). As already explained, in the first random number update process, the jackpot type counter C2 consisting of 1 byte, the reach random number counter C3, the variation type counter C5 and the general electric random number counter C6 are updated. The first random number update process is executed using a specific control program and specific control data.

In the first random number update process, first, it is determined whether or not the setting value updating flag in the work area 121 for specific control is set to "1" (step S601), and the setting value updating flag is set to "1". If it is set (step S601: YES), the first random number update process is terminated without executing the processes after step S602. Thus, during execution of the set value update process, the jackpot type counter C2, the reach random number counter C3, the variation type counter C5 and the general electric random number counter C6 are not updated.

If a negative determination is made in step S601, update start setting processing is executed (step S602). In the update start setting process, "0011H", which is the address of the jackpot type counter C2, is set in the HL register 107. The address of the counter to be updated is set in the HL register 107 in the first random number update process. By setting the address of the jackpot type counter C2 in the HL register 107, the jackpot type counter C2 is selected as the counter to be updated. Further, in the update start setting process in step S602, the address of the jackpot type maximum value counter CN2 is set in the BC register 105. In the first random number update process, the BC register 105 is set with the address of the counter to which the maximum value of the counter to be updated is set. The main CPU 63 identifies the current counter to be updated based on the address data stored in the HL register 107, and sets the maximum value of the counter to be updated based on the address data stored in the BC register 105. Identifies the counters that are

As already described with reference to FIG. 12(a), in the work area 121 for specific control, the jackpot type counter C2, the reach random number counter C3, the fluctuation type counter C5 and the general electric random number counter C6 are "0011H" to "0014H". ” are provided so that the addresses are consecutively numbered. For this reason, every time the process of adding 1 to the address stored in the HL register 107 and updating it (the process of step S607 described later) is executed, the jackpot type counter C2 → reach random number counter C3 → fluctuation type counter C5 → normal The counters to be updated can be updated in the order of the random number counter C6. Also, as already explained with reference to FIG. The maximum value counter CN6 is provided so that the addresses are serially numbered within the address range of "0019H" to "001CH". For this reason, every time the process of updating the address stored in the BC register 105 by adding 1 (process of step S608 described later) is executed, the maximum value counter for jackpot type CN2 → maximum value counter for reach CN3 → fluctuation The counters for which the maximum values of the counters to be updated are set can be updated in the order of the type maximum value counter CN5→general electric maximum value counter CN6.

FIG. 27B is an explanatory diagram for explaining program contents of the update start setting process (step S602). As shown in FIG. 27B, "1401" to "1403" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LDY HL, 11H" is set at the line number "1401". "LDY" is the first LDY instruction by the first LDY execution circuit 156, "HL" is the content specifying the HL register 107 as the transfer destination, and "11H" is a 1-byte numerical value "11H" as the "transfer source". This is the content for setting information. As already described, "0000H" is set in the IY register 109 as the specific control reference address in step S103 of the main process (FIG. 15). Therefore, by executing "LDY HL, 11H", "0011H" obtained by adding "0000H" set in the IY register 109 to "11H" set as the "transfer source" ” is loaded into the HL register 107 . As a result, the address of the jackpot type counter C2 can be set in the HL register 107. FIG.

In this way, the address data (2 bytes) of the jackpot type counter C2 is loaded into the HL register 107 using the first LDY instruction for specifying the address by setting the address data of 1 byte. Compared to the configuration that loads the address data of the jackpot type counter C2 into the HL register 107 using the LD instruction that sets the address data of and specifies the address, the data capacity of the program for executing the update start setting process can be reduced.

The command "LDY BC, 19H" is set at the line number "1402". "LDY" is the first LDY instruction by the first LDY execution circuit 156, "BC" is the content specifying the BC register 105 as the transfer destination, and "19H" is a 1-byte numerical value "19H" as the "transfer source". This is the content for setting information. By executing "LDY BC, 19H", "0019H" obtained by adding "0000H" set in the IY register 109 to "19H" set as the "transfer source" is BC. Loaded into register 105 . As a result, the address of the jackpot type maximum value counter CN2 can be set in the BC register 105. FIG.

In this way, the address data (2 bytes) of the jackpot type maximum value counter CN2 is loaded into the BC register 105 by using the first LDY instruction for specifying the address by setting the address data of 1 byte. , compared to the configuration in which the address data of the jackpot type maximum value counter CN2 is loaded into the BC register 105 using the LD instruction for specifying the address by setting the address data of 2 bytes, the update start setting process is executed. Therefore, the data volume of the program can be reduced.

A command "RET" is set at the line number "1403". As already described, the update start setting process is a subroutine executed in step S602 of the first random number update process (FIG. 27(a)). Therefore, by executing the command "RET", the process proceeds to step S603 of the first random number update process (FIG. 27(a)).

Returning to the description of the first random number update process (FIG. 27(a)), after the update start setting process is executed in step S602, the first addition process of the counter to be updated is executed (step S603). In the first addition process for the update target counter, 1 is added to the value of the counter selected as the update target counter among the four counters C2, C3, C5, and C6. Specifically, 1 is added to the value of the update target counter specified by the address stored in the HL register 107 in the work area 121 for specific control.

Thereafter, it is determined whether or not the value of the update target counter after being incremented by 1 in step S603 has exceeded the maximum value (step S604). As described above, the main CPU 63 can identify the counter to be updated based on the address stored in the HL register 107, and the maximum value of the counter to be updated based on the address stored in the BC register 105. can be specified. When an affirmative determination is made in step S604, the value of the counter to be updated is cleared to "0" (step S605).

When a negative determination is made in step S604, or when the processing of step S605 is performed, the address data stored in the HL register 107 is the end address of the first random number update processing (specifically, "0014H"). ) (step S606). If a negative determination is made in step S606, the value of the HL register 107 is incremented by 1 to update the update target counter (step S607), and the value of the BC register 105 is incremented by 1 (step S608). As a result, based on the address stored in the BC register 105, counters (four maximum value counters CN2, CN3, CN5, CN6 ) can be identified.

If the process of step S608 has been performed, the process returns to step S603, and the processes of steps S603 to S608 are repeatedly performed until an affirmative determination is made in step S606. Thereby, the jackpot type counter C2, the reach random number counter C3, the variation type counter C5 and the general electric random number counter C6 can be updated. If an affirmative determination is made in step S606, the second random number update process is executed (step S609), and the first random number update process ends. FIG. 28 is a flowchart showing second random number update processing.

In the second random number update process, first, 1 is added to the value of the HL register 107 (step S701). As a result, the HL register 107 stores "0015H", which is the address of the lower area of the hit random number counter C1. After that, 1 is added to the value of the BC register 105 (step S702). As a result, the BC register 105 stores "001DH", which is the address of the lower area of the winning maximum value counter CN1.

After that, the second addition processing of the counter to be updated is executed (step S703). In the second addition process, 1 is added to the value of the counter selected as the counter to be updated from among the winning random number counter C1 and the random number initial value counter C4. These counters C1 and C4 are 2-byte counters. In the second update target counter addition process (step S703), 1 is added to the value of the 2-byte counter specified by the address stored in the HL register 107 in the work area 121 for specific control.

Thereafter, it is determined whether or not the value of the update target counter after being incremented by 1 in step S703 has exceeded the maximum value (step S704). As described above, the main CPU 63 can identify the counter to be updated based on the address stored in the HL register 107, and the maximum value of the counter to be updated based on the address stored in the BC register 105. can be specified. When an affirmative determination is made in step S704, the value of the counter to be updated is cleared to "0" (step S705).

When a negative determination is made in step S704, or when the process of step S705 is performed, the address data stored in the HL register 107 is the end address of the second random number update process (specifically, "0017H"). ) (step S706). If a negative determination is made in step S706, 2 is added to the value of the HL register 107 (step S707). As a result, the counter to be updated can be updated from the hit random number counter C1 to the random number initial value counter C4 assuming that the HL register 107 stores "0017H", which is the address of the lower area of the random number initial value counter C4. . After that, 2 is added to the value of the BC register 105 (step S708). As a result, the BC register 105 can store the address "001FH" in the lower area of the initial value maximum value counter CN4.

If the process of step S708 has been performed, the process returns to step S703 and the processes of steps S703 to S706 are executed. As a result, the value of the random number initial value counter C4 can be updated. After that, an affirmative determination is made in step S706, and the second random number update process ends.

Next, the fraud detection process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 29(a). The fraud detection process is executed in step S502 of the timer interrupt process (FIG. 26). Note that the fraud detection process is executed using a program for specific control and data for specific control.

In the fraud detection process, first, it is determined whether or not fraudulent radio waves are detected (step S801). In step S801, an affirmative determination is made when the detection signal received from the already-described unauthorized radio wave detection sensor (not shown) is in the HI state. If an affirmative determination is made in step S801, the value of the unauthorized radio wave detection counter 133 in the work area 121 for specific control is decremented by 1 (step S802), and the value of the unauthorized radio wave detection counter 133 after the subtraction of 1 is It is determined whether or not it has become "0" (step S803). As already described, the fraudulent radio wave detection counter 133 is set to an initial value of "5" each time the fraudulent monitoring reference period (specifically, about 262 seconds) elapses.

If a negative determination is made in step S801 or if a negative determination is made in step S803, it is determined whether or not illegal magnetism is detected (step S804). In step S804, an affirmative determination is made when the detection signal received from the previously described fraudulent magnetism detection sensor (not shown) is in the HI state. If an affirmative determination is made in step S804, the value of the fraudulent magnetism detection counter 134 in the work area 121 for specific control is decremented by 1 (step S805), and the value of the fraudulent magnetism detection counter 134 after the subtraction of 1 is It is determined whether or not it has become "0" (step S806). As already explained, the fraudulent magnetism detection counter 134 is set to an initial value of "10" each time the fraud monitoring reference period (specifically, approximately 262 seconds) elapses.

If a negative determination is made in step S804 or if a negative determination is made in step S806, it is determined whether or not abnormal vibration is detected (step S807). In step S807, an affirmative determination is made when the detection signal received from the already-described abnormal vibration detection sensor (not shown) is in the HI state. When an affirmative determination is made in step S807, the value of the abnormal vibration detection counter 135 in the work area 121 for specific control is subtracted by 1 (step S808), and the value of the abnormal vibration detection counter 135 after the subtraction of 1 is It is determined whether or not it has become "0" (step S809). As already described, the abnormal vibration detection counter 135 is set to an initial value of "15" each time the fraud monitoring reference period (specifically, approximately 262 seconds) elapses.

If a negative determination is made in step S807, or if a negative determination is made in step S809, update processing of the fraud monitoring timer counter 132 is executed (step S810). In the updating process, numerical information stored in the fraud monitoring timer counter 132 in the specific control work area 121 is read to the IX register 108, and the value of the IX register 108 is incremented by one. When the value after adding 1 exceeds the maximum value "65535", the value of the IX register 108 becomes "0" and the carry flag is set to "1". After that, the numerical information stored in the IX register 108 is loaded into the fraud monitoring timer counter 132 by the LD instruction. As a result, the value of the fraud monitoring timer counter 132 is updated. The state of the carry flag does not change even if the LD instruction is executed. For this reason, when the value of the fraud monitoring timer counter 132 after updating becomes "0", that is, when the value of the fraud monitoring timer counter 132 completes one cycle, the carry flag is set to "1" at the end of the process of step S810. ” is set. The value of the fraud monitoring timer counter 132 makes one cycle in about 262 seconds. When the value of the fraud monitoring timer counter 132 completes one cycle, the main CPU 63 recognizes that it is time to end the current fraud monitoring reference period and start the next fraud monitoring reference period.

Thereafter, in step S810, it is determined whether or not the value of the fraud monitoring timer counter 132 has completed one cycle (step S811). In step S811, it is determined whether or not the carry flag is set to "1", and if the carry flag is set to "1", it is determined that the value of the fraud monitoring timer counter 132 has completed one cycle. If the value of the fraud monitoring timer counter 132 has completed one cycle (step S811: YES), initialization processing for fraud detection is executed (step S812), and this fraud detection processing ends. In the fraud detection initialization process in step S812, the fraud radio wave detection counter 133, fraud magnetism detection counter 134, and abnormal vibration detection counter 135 are set to the initial value "5". In this manner, initial values are set in these detection counters 133 to 135 each time the fraud monitoring reference period elapses.

FIG. 29B is an explanatory diagram for explaining program contents of the fraud detection initialization process (step S812). As shown in FIG. 29B, "1501" to "1504" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LDT HL, 400H" is set at the line number "1501". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "400H" sets 12-bit numerical information "400H" as the transfer source. Content. As already described, the TP register 111 is set with "9000H", which is the reference address of the data table in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 400H", "9400H" obtained by adding "9000H" set in the TP register 111 to "400H" set as the transfer source is obtained. HL register 107 is loaded. As a result, the start address of the first initialization table 64k (FIG. 18(a)) can be set in the HL register 107. FIG.

In this way, by using the LDT instruction for setting 12-bit numerical information and specifying the address, the start address of the first initialization table 64k is loaded into the HL register 107, so that 2-byte numerical information is set and the address is specified, and the start address of the first initialization table 64k is loaded into the HL register 107 by using the data of the program for executing the initialization process for fraud detection. Capacity can be reduced.

In line numbers "1502" to "1503", commands similar to line numbers "1002" to "1003" of the power-on setting process (FIG. 17(c)) are set. Specifically, the command "XOR D, D" is set at the line number "1502". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma designates the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As a result, the upper 1-byte data ("00H") common to the address data of the illegal radio wave detection counter 133, the illegal magnetism detection counter 134, and the abnormal vibration detection counter 135 can be set in the D register 106a.

The command "CALL 4BTS10" is set at the line number "1503". "4BTS10" is the already explained data setting execution process (FIG. 19(c)). The instruction "CALL 4BTS10" is an instruction for calling a subroutine called data setting execution processing. In the line number "1503", the start address of the first initialization table 64k is set in the HL register 107, as in the line number "1003" of the power-on setting process (FIG. 17(c)) already described. The data setting execution process is executed while "00H" is stored in the D register 106a. By executing the data setting execution process at the line number "1504", the initial value "5" is set to the illegal radio wave detection counter 133, the illegal magnetism detection counter 134, and the abnormal vibration detection counter 135 in the work area 121 for specific control. ” is set.

In this way, the illegal radio wave detection counter 133 and the illegal magnetism detection counter 134 are detected by using the data setting execution processing program and the data of the first initialization table 64k, which are also used in the power-on setting processing (FIG. 17(c)). , and the abnormal vibration detection counter 135, compared to a configuration that stores a dedicated program and data for initializing these detection counters 133 to 135 in the fraud detection initialization process. Therefore, the data capacity of programs and data in the main ROM 64 can be reduced.

A command "RET" is set at the line number "1504". The initialization process for fraud detection ends when the command "RET" is executed. As already explained, the fraud detection initialization process is a subroutine executed in step S812 of the fraud detection process (FIG. 29(a)), and when the fraud detection initialization process ends, the fraud detection process will also end.

Returning to the description of the fraud detection process (FIG. 29(a)), if affirmative determination is made in step S803, if affirmative determination is made in step S806, or if affirmative determination is made in step S809, , the fraud detection handling process (steps S813 and S814) is executed. Specifically, first, a fraud notification command is transmitted to the sound and light side CPU 93 (step S813). The illegal notification command is a command for making the sound and light side CPU 93 recognize that an illegal radio wave, illegal magnetism, or abnormal vibration has been detected and an abnormal state has occurred. When the sound and light side CPU 93 receives the fraud notification command, the light emission control of the display light emitting unit 53, the sound output control of the speaker unit 54, and the pattern are performed so that the fraud notification for notifying the abnormal state is performed. Display control of the display device 41 is performed. As a result, it is possible to notify the manager of the game hall that an illegal radio wave, illegal magnetism, or abnormal vibration has been detected and an abnormal state has occurred.

After that, the game stop flag in the work area 121 for specific control is set to "1" (step S814), and this fraud detection process ends. By setting the game stop flag to "1", the processing of steps S506 to S518 in the timer interrupt processing (FIG. 26) is not executed, and the progress of the game is stopped. The state in which the game stop flag is set to "1" is resolved by executing the partial clear process (step S107) or the full clear process (step S114) in the main process (FIG. 15).

<Special special train control processing>
Next, the special figure special electric control processing executed by the main side CPU 63 will be described with reference to the flowchart of FIG. In addition, special figure special electric control processing is performed in step S512 in timer interrupt processing (FIG. 26).

In the special figure special electric control process, when the winning to the first operation opening 33 or the second operation opening 34 has occurred, the processing for acquiring the pending information is executed, and when the pending information is stored A decision is made on the pending information, and the decision is used as a trigger to execute a process for performing an effect for the game cycle. Based on the result of the success/failure determination, a process for shifting to the opening/closing execution mode is executed after the effect for the game round, and a process during the opening/closing execution mode and at the end of the opening/closing execution mode is executed.

In the special figure special electric control process, the acquisition process of the pending information is executed first (step S901). In the pending information acquisition process, the pending information on the special figure side is acquired. Specifically, it is determined whether or not the winning of the game ball to the first operation opening 33 has occurred based on the state of the first operation winning flag in the work area 121 for specific control. When the winning of the game ball to the first operation port 33 has occurred, it is stored in the first special figure reservation area 115 by referring to the first special figure reservation number counter 118 in the special figure reservation area 113. Grasping the number of pending information, when the number of pending information is less than the upper limit (specifically "4"), each value of the hit random number counter C1, jackpot type counter C2 and reach random number counter C3, It is stored in the area of the highest side in which the reservation information is not stored in the first special figure reservation area 115.例文帳に追加Then, the first operation winning flag is cleared to "0". Further, in the acquisition process, it is determined whether or not the winning of the game ball to the second operation opening 34 occurs based on the state of the second operation winning flag in the work area 121 for specific control. When the winning of the game ball to the second operation port 34 has occurred, it is stored in the second special figure reservation area 116 by referring to the second special figure reservation number counter 119 in the special figure reservation area 113. Grasping the number of pending information, when the number of pending information is less than the upper limit (specifically "4"), each value of the hit random number counter C1, jackpot type counter C2 and reach random number counter C3, It is stored in the area of the highest side in which the reservation information is not stored in the second special figure reservation area 116.例文帳に追加Then, the second operation winning flag is cleared to "0".

In the hold information acquisition process in step S901, when the hold information for the first special figure reservation area 115 or the hold information for the second special figure reservation area 116 is acquired, a hold command is transmitted to the sound and light side CPU 93 . The sound and light side CPU 93 transmits a command corresponding to the received pending command to the display control device 89 . In the display control device 89, by receiving the pending command, the display of the number of pending information on the pattern display device 41 is changed corresponding to the increase in the pending number. In this case, since the hold command contains information indicating which hold information has increased among the first special figure hold area 115 and the second special figure hold area 116, in the design display device 41, The display of the pending number corresponding to the increased side is changed.

Further, when the number of pending information is increased as described above, in the display control process in step S514 of the timer interrupt process (FIG. 26), the first special figure pending display section 37c and the second special figure pending display section For the side of 37d corresponding to the increase in the number of reserved items, display control is performed so that the display content is changed to correspond to the increase in the number of reserved items. Details of the display control process (step S514) will be described later.

After executing the pending information acquisition process in step S901, the special figure special electric address acquisition process is executed (step S902). In the special special electric address acquisition process, the information of the special special electric counter provided in the specific control work area 121 is read, and the special special electric address table 64q (FIG. 31) stored in the main ROM 64 is read. . Then, the start address corresponding to the information of the special figure special electric counter is acquired from the special figure special electric address table 64q. In addition, the detail of special figure special electric address acquisition processing is mentioned later.

As already explained, the special figure special electric control process includes a process for controlling the effect for the game cycle and a process for controlling the opening/closing execution mode. In this case, as a process for controlling the effect for the game round, special figure fluctuation start processing (step S904) which is a process for starting the effect for the game round, and for advancing the effect for the game round During special figure fluctuation processing (step S905), which is the processing, and during special figure determination processing (step S906), which is processing for ending the effect for the game round, are set.

Further, as processing for controlling the opening/closing execution mode, special electric start processing (step S907) which is processing for controlling the opening of the opening/closing execution mode, and processing for controlling the open state of the special electric prize winning device 32. A special electric open process (step S908), a special electric closed process (step S909) that is a process for controlling the closed state of the special electric winning device 32, the ending of the opening and closing execution mode, and the end of the opening and closing execution mode A special electric end process (step S910), which is a process for controlling the transition of the game state, is set.

In such a processing configuration, the special special electric counter is a counter for the main side CPU 63 to grasp which of the plurality of types of processing should be executed, and the special special electric address table 64q (Fig. In 31), the start address of the program for executing the plurality of types of processing is set in correspondence with the numerical information of the special special electric counter.

FIG. 31 is an explanatory diagram for explaining the data configuration of the special figure special electric address table 64q. As shown in FIG. 31, the special figure special electric address table 64q is stored in the address range of "9180H" to "918AH" in the main ROM64.

The start address SA0 is the start address of the program for executing the special figure fluctuation start process (step S904), and the start address SA1 is the start address of the program for executing the special figure fluctuation process (step S905). Yes, the start address SA2 is the start address of the program for executing the special figure confirmation process (step S906), and the start address SA3 is the start address of the program for executing the special electric start process (step S907). The start address SA4 is the start address of the program for executing the special electric open process (step S908), and the start address SA5 is the start address of the program for executing the special electric closed process (step S909). Yes, and the start address SA6 is the start address of the program for executing the special electric end processing (step S910).

The address data of these start addresses SA0-SA6 are 2-byte data, and the upper 4 bits of these start addresses SA0-SA6 are all "9H". In the special figure special electric address table 64q, only the lower 12 bits excluding the common upper 4 bits ("9H") from these start addresses SA0 to SA6 are set. Specifically, in the main ROM 64, among the area corresponding to the address "9180H" and the area corresponding to the address "9181H", the lower 4-bit area (hereinafter also referred to as the lower 4-bit area) has a start address. The lower 12 bits (“700H”) of SA0 (“9700H”) are set, and the upper 4-bit area (hereinafter also referred to as the upper 4-bit area) of the area corresponding to the address “9181H”; The lower 12 bits (“712H”) of the start address SA1 (“9712H”) are set in the area corresponding to the address “9182H”. The lower 12 bits (“71FH”) of the start address SA2 (“971FH”) are set in the area corresponding to the address “9183H” and the lower 4-bit area corresponding to the address “9184H”. ” and the area corresponding to the address “9185H” are set with the lower 12 bits (“731H”) of the start address SA3 (“9731H”). The lower 12 bits (“740H”) of the start address SA4 (“9740H”) are set in the area corresponding to the address “9186H” and the lower 4-bit area corresponding to the address “9187H”. ” and the area corresponding to the address “9188H” are set with the lower 12 bits (“74CH”) of the start address SA5 (“974CH”). The lower 12 bits ("753H") of the start address SA6 ("9753H") are set in the area corresponding to the address "9189H" and the lower 4-bit area corresponding to the address "918AH". "0000B" is set as unused adjustment data in the upper 4-bit area corresponding to the address of ".

When the processing corresponding to the numerical information currently stored is completed, the special special electric counter is triggered by the fact that the conditions for updating the numerical information are satisfied, and the special special electric control in the next processing time It is incremented by 1, decremented by 1, or cleared to "0" in correspondence with the processing executed in the processing. Therefore, in the special figure special electric control processing in each processing time, the processing corresponding to the numerical information set in the special figure special electric counter should be executed. In addition, the special figure special electric counter is set to 0 as an initial value.

Returning to the description of the special figure special electric control process (FIG. 30), after executing the process of step S902, in step S903, the process of jumping to the process indicated by the start address acquired in step S902 is executed. Specifically, when the acquired start address is SA0, jump to the special figure fluctuation start process of step S904, and when the acquired start address is SA1, jump to the special figure fluctuation process of step S905. , If the acquired start address is SA2, it jumps to the special figure confirmation process of step S906, and if the acquired start address is SA3, it jumps to the special electric start process of step S907, and the acquired start address is If it is SA4, it jumps to the special electric open process of step S908, and if the acquired start address is SA5, it jumps to the special electric closed process of step S909, and if the acquired start address is SA6. It jumps to the special electric end processing of step S910. If any of the processing of steps S904 to S910 is executed, this special figure special electric control processing is terminated. The contents of the processing of steps S904 to S910 will be described later.

<LDB instruction>
The start addresses SA0 to SA6 corresponding to the value of the special figure special electric counter are acquired by the HL register 107 in the address acquisition execution process (FIG. 33(e)) described later. In the address acquisition execution process, an LDB instruction "LDB HL, (HL).A" is executed to acquire the start addresses SA0-SA6. As shown in FIG. 9, the main MPU 62 has an LDB execution circuit 157, which is a dedicated circuit for executing LDB instructions, and the main CPU 63 can execute LDB instructions.

The instruction code of the LDB instruction has a configuration of "LDB transfer destination, acquisition data designation, acquisition bit number designation". In the LDB instruction, a general-purpose register or a pair register is set as a "transfer destination". The W register 104a is set as the "transfer destination" in the LDB instruction, and the HL register 107 is the pair register set as the "transfer destination" in the LDB instruction. The LDB instruction may be configured such that the A register 104b, the B register 105a, the C register 105b, the D register 106a, the E register 106b, the H register 107a, or the L register 107b is set as the "transfer destination" general-purpose register. Alternatively, the WA register 104, the BC register 105, or the DE register 106 may be set as the "transfer destination" pair register in the LDB instruction.

When the 1-byte W register 104a is set as the "transfer destination", any one of 1 to 8 bits of data is set in the W register 104a of the "transfer destination" by the LDB instruction. When data of any number of bits from 1 to 7 is set in the W register 104a of the "transfer destination", the data is loaded into the lower bits of the W register 104a, and the upper bits of the W register 104a are loaded with the data. side bits are masked with '0'. For example, when 2-bit data is loaded into the "transfer destination" W register 104a, the data is loaded into the 0th to 1st bits existing on the lower side of the W register 104a, and The 2nd to 7th bits that are present are masked with "0".

When the 2-byte HL register 107 is set as the "transfer destination", data of any number of bits from 1 to 16 is loaded into the HL register 107 of the "transfer destination" by the LDB instruction. When data of any number of bits from 1 to 15 is loaded into the HL register 107 as the “destination”, the data is loaded into the lower bits of the HL register 107 and the upper bits of the HL register 107 are loaded with the data. side bits are masked with '0'. For example, when 12-bit data is loaded into the “transfer destination” HL register 107, the data is loaded into the 0th to 11th bits existing on the lower side of the HL register 107, and The existing 12th to 15th bits are masked with "0".

In the LDB command, "(HL)" is set as "acquisition data designation". In the LDB instruction, data to be transferred to the "transfer destination" register based on the 2-byte data stored in the HL register 107 set as "acquisition data designation" (hereinafter referred to as "acquisition data designation data"). acquisition start address and acquisition start bit number are specified.

When the 1-byte W register 104a is set as the "transfer destination", a general-purpose register storing any number from "0" to "7" is set as the "specify number of bits to acquire" in the LDB instruction. be done. In addition, when the 2-byte HL register 107 is set as the "transfer destination", the general-purpose register storing any number from "0" to "15" is used as the "specify number of bits to acquire" in the LDB instruction. is set. The general-purpose register set as "specify the number of bits to be acquired" in the LDB instruction is the A register 104b. Note that the B register 105a, the C register 105b, the D register 106a, the E register 106b, the H register 107a, or the L register 107b may be set as general-purpose registers for "specifying the number of bits to be acquired" in the LDB instruction.

The "number of acquired bits specification" is data for specifying the number of bits of data to be loaded into the "transfer destination" register (hereinafter also referred to as "number of acquired bits specification data"). In the LDB instruction, the LDB execution circuit 157 performs a process of calculating a value obtained by adding "1" to the value of the A register 104b set to "specify the number of bits to be obtained", and the result of the calculation is A corresponding number of bits of data is loaded into the Destination. That is, in the "destination", data of the number of bits corresponding to the value obtained by adding "1" to the "designation of number of bits to be obtained" is loaded. Therefore, a value obtained by subtracting "1" from the number of bits of data to be loaded into the "transfer destination" is set in the "specify number of bits to be obtained". For example, when the A register 104b storing the value "1" is set as the "specify number of bits to be acquired", the "transfer destination" register is obtained by adding "1" to the "1". 2-bit data is loaded. Further, for example, when the A register 104b storing the numerical value "11" is set as the "specify number of bits to be acquired", "1" is added to the "11" in the "transfer destination" register. 12-bit data is loaded.

By executing the LDB instruction, the data of the number of bits corresponding to the "specify number of bits to be acquired" from the acquisition start bit of the area corresponding to the acquisition start address in the main ROM 64 is loaded into the "transfer destination" register. .

32(a) to 32(d) are explanatory diagrams for explaining the process of calculating the acquisition start address and the acquisition start bit number from the acquisition data designation data. Of the 2-byte acquisition data specification data, the upper 13 bits (3rd to 15th bits) are data for specifying the acquisition start address, and the lower 3 bits (0th to 2nd bits) are the acquisition start bits. This is data for specifying The acquisition start address is the reference address ("9000H" in this embodiment) of the data table stored in the TP register 111 for the quotient obtained by dividing the acquisition data designation data by "8" ("1000B"). This is the address calculated as the calculation result of the addition calculation. "8" ("1000B") used for division of the acquired data designation data is a numerical range ( It is a value obtained by adding "1" to "7" which is the maximum value of "0" to "7"), which is the cube of "2". The value obtained by adding "1" to the maximum value of the numerical range represented by the number of bits "n" (n is any integer from 1 to 15) is "2" raised to the nth power. When the 2-byte binary number is divided by the nth power of "2", the information of "0" or "1" set in the n-th to 15th bits in the 2-byte binary number is on the n-bit lower side. is set to the lower (16-n) bits of the quotient data after division, and the upper n bits ((16-n) bit to 15th bit) of the quotient data after division are set to "0". is set. In the LDB instruction in this embodiment, the acquired data designation data, which is a 2-byte binary number, is divided by "8" ("1000B"), which is the cube of "2". When the obtained data designation data is divided by "8", the information of "0" or "1" set in the 3rd to 15th bits of the obtained data designation data is shifted to the lower side by 3 bits. The lower 13 bits (0th to 12th bits) of the quotient data are set, and "0" is set to the upper 3 bits (13th to 15th bits) of the quotient data after the division.

Specifically, as shown in FIG. 32(a), "0C24H" is set as acquisition data designation data. As shown in FIG. 32(b), the acquired data designation data (“0C24H”) is set to “8” which is the value obtained by adding “1” to “7” which is the maximum value of the numerical range represented by 3 bits. When the division is performed, "0000110000100" set in the 3rd to 15th bits of the acquisition data designation data is shifted to the lower 3 bits and is converted to the lower 13 bits (0th to 12th bits) of the quotient data after division. At the same time, the upper 3 bits (13th to 15th bits) of the quotient data after the division are set to "0". As a result, the quotient data after division is "0000000110000100". After that, as a calculation result of adding the reference address (“9000H”) of the data table stored in the TP register 111 to the quotient data after the division, “1001000110000100” is obtained as shown in FIG. An acquisition start address (“9184H”) is calculated. The 12th bit of the quotient data after division (FIG. 32(b)) is "0", and the 12th bit of the reference address "9000H" of the data table is "1". Further, in the operation of adding the reference address of the data table to the quotient data after division, no carry-over to the 12th bit occurs. Therefore, as shown in FIG. 32(c), the data of the 3rd to 14th bits in the acquisition data designation data (FIG. 32(a)) are set in the 0th to 11th bits of the acquisition start address. , "1001B" ("9H"), which is the data of the 12th to 15th bits of the reference address of the data table, is set to the 12th to 15th bits of the acquisition start address.

In this way, the data of the 3rd to 14th bits in the acquisition data designation data are set to the 0th to 11th bits of the acquisition start address, and the TP register 111 is set to the 12th to 15th bits of the acquisition start address. 12th to 15th bit data at the reference address of the data table stored in .

The acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00000111B" ("07H"). The "00000111B" used in the calculation for calculating the acquisition start bit separates only the data of the lower 3 bits (0th to 2nd bits) in the acquired data specifying data from the acquired data specifying data of 2 bytes. This is data for making the lower 3-bit data available independently. In the AND operation of the lower 1 byte of the acquired data designation data and "00000111B", the data of the lower 3 bits (0th to 2nd bits) in the acquired data designation data becomes the lower 3 bits (0th to 2nd bits) of the operation result. 2 bits), and the upper 5 bits (3rd to 7th bits) of the calculation result are set to "0". Specifically, as shown in FIG. 32A, when "0C24H" is set as the acquisition data designation data, the acquisition start bit is "00100100B" (" 24H”) and “00000111B” result in “00000100B” (“4”). As shown in FIG. 32(d), the data of the 0th to 2nd bits in the acquisition data designation data (FIG. 32(a)) are set in the 0th to 2nd bits of the acquisition start bit. "0" is set to the 3rd to 7th bits of the start bit.

Data for designating the use of "00000111B" for the calculation for calculating the acquisition start bit is not set in the instruction code of the LDB instruction. The logical product operation of the lower 1 byte of the acquisition data designation data and "00000111B" is automatically executed by the LDB execution circuit 157 when the LDB command set in the program is executed. For this reason, compared to the configuration in which it is necessary to set data for designating the use of "00000111B" in the operation for calculating the acquisition start bit in the instruction code of the LDB instruction, the instruction code of the LDB instruction is The data capacity can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

When the acquisition start bit is "n" (n is an integer of 0 to 7), the nth bit and after (nth bit) of the 0th to 7th bits of the area corresponding to the acquisition start address in the main ROM 64 to the 7th bit) are transferred to the "transfer destination" register. If the number of "0" or "1" data existing after the acquisition start bit (nth bit to 7th bit) in the area corresponding to the acquisition start address is less than the number of bits acquired this time , the data after the acquisition start bit at the acquisition start address (data from the nth bit to the 7th bit at the acquisition start address) and the data after the 0th bit at the address next to the acquisition start address are the "transfer destination". is loaded into Here, the address next to the acquisition start address is an address obtained by adding "1" to the acquisition start address.

For example, the TP register 111 stores "9000H" as the reference address, the HL register 107 stores "0C24H" ("3108") as acquisition data designation data, and the A register 104b stores acquisition bit number designation data. When "LDB HL, (HL).A" is executed in a state in which "BH" (11) is stored as , the "transfer destination" is the HL register 107 . As already explained, the data for specifying the acquisition start address is set in the high-order 13 bits of the acquisition data specification data, and the data for specifying the acquisition start bit is set in the low-order 3 bits of the acquisition data specification data. is set. The acquisition start address is "9184H" obtained by adding the reference address ("9000H") to "0184H" ("388") obtained by dividing the acquisition data designation data by "8". The acquisition start bit is "00000100B" ("4") by extracting the lower 3 bits of the acquisition data designation data. As already explained, the acquisition start bit is calculated by performing a logical product operation of the lower 1 byte (“00100100B”) of the acquisition data designation data and “00000111H”. The number of acquired bits is "0CH" ("12") obtained by adding "1" to "0BH". Therefore, when "LDB HL, (HL).A" is executed in this state, the acquisition start bit in the area corresponding to the acquisition start address "9184H" (see FIG. 31) in the main ROM 64 4-bit data set after (4th bit) and 8-bit data set after 0th bit in the area corresponding to "9185H", which is the next address of the acquisition start address and are set in the 0th to 11th bits of the HL register 107, which is the transfer destination, and the 12th to 15th bits of the HL register 107 are masked with "0". Specifically, the 4th to 7th bit data of the area corresponding to "9184H" and the 0th to 7th bit data of the area corresponding to "9185H" are stored in the 0th to 11th bits of the HL register 107. set.

FIGS. 32(e) and 32(f) are explanatory diagrams for explaining how the start address SA3 is acquired from the special special electric address table 64q to the HL register 107. FIG. As already explained, in the special special electric address table 64q (FIG. 31), the lower 12 bits of the start address SA3 are set to the 4th to 7th bits of "9184H" and the 0th to 7th bits of "9185H". ing. By executing "LDB HL, (HL).A", the lower 12 bits of the start address SA3 are loaded into the lower 12 bits of the HL register 107, as shown in FIG. 32(e). In the address acquisition execution process (FIG. 33(e)), which will be described later, after executing the LDB instruction, the value of the HL register 107 is added to "9000H", which is the reference address of the data table. As a result, the entire start address SA3 can be obtained in the HL register 107, as shown in FIG. 32(f).

A process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111 by using the LDB instruction; A process of specifying the acquisition start bit corresponding to the lower 3 bits (0th to 2nd bits) of the acquisition designation data, and transferring the data for the number of acquisition bits from the acquisition start bit of the acquisition start address to the "transfer destination". A process of loading data into a register and a process of masking, with "0", bits existing on the upper side of the loaded data in the "destination" register can be executed with one instruction. These processes are executed by the LDB execution circuit 157 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

Next, the program content of the special figure special electric address acquisition process executed in step S902 of the special figure special electric control process (FIG. 30) will be described with reference to the explanatory diagram of FIG. 33(a). As shown in FIG. 33(a), "1601" to "1605" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LD W, (TZTDCNT)" is set at the line number "1601". "LD" is the LD instruction, and "W" is the content specifying the W register 104a as the transfer destination. "TZTDCNT" is the address of the special special electric counter in the work area 121 for specific control, and "(TZTDCNT)" is the content for transferring the data stored in the special special electric counter to the "transfer destination". As already explained, any numerical data of 0 to 6 is stored in the special special electric counter. By executing "LD W, (TZTDCNT)", the data (1 byte) of the special special electric counter is loaded into the "transfer destination" W register 104a.

The command "LD B, 0CH" is set at the line number "1602". "LD" is the LD instruction, "B" is the contents of specifying the B register 105a as the transfer destination, and "0CH" is the contents of specifying numerical data "0CH" ("12") as the "transfer source". is. "0CH" is the number of bits of address data acquired from the special figure special electric address table 64q in the address acquisition execution process (FIG. 33(e)) described later. By executing "LD B, 0CH", the number of bits ("12") of the address data acquired from the special special electric address table 64q is set in the "transfer destination" B register 105a.

A command "LD HL, TBL_TZTD_B" is set at the line number "1603". "LD" is the LD instruction, and "HL" is the content specifying the HL register 107 as the transfer destination. "TBL_TZTD_B" is 2-byte numerical data for making the acquisition start address the start address of the special special electric address table 64q, specifically "0C00H". By executing “LD HL, TBL_TZTD_B”, “0C00H” is loaded into the “transfer destination” HL register 107 .

“TBL_TZTD_B” is calculated by the formula “{(start address of special special electric address table 64q)−9000H}×8”. FIGS. 33(b) to 33(d) are explanatory diagrams for explaining the process of calculating "TBL_TZTD_B". By subtracting "9000H", which is the reference address of the data table, from "9180H" (Fig. 33(b)), which is the start address of the special special electric address table 64q, the data after the subtraction is obtained as shown in Fig. 33(c). The data of the 0th to 11th bits of the start address “9180H” (FIG. 33(b)) are set in the 0th to 11th bits of the . After that, when the data after the subtraction is multiplied by "8" ("1000B"), "TBL_TZTD_B" is calculated as shown in FIG. 33(d). "8" used in the calculation for calculating "TBL_TZTD_B" is a numerical range (" 0” to “7”), which is the maximum value “7” plus “1”, which is the cube of “2”. When a 2-byte binary number is multiplied by "2" to the nth power (n is an integer from 1 to 15), the 0th bit to the (15-n)th bit are set in the 2-byte binary number. The "0" or "1" information in the multiplication data is shifted to the upper n-bit side and set to the upper (16-n) bits in the data after multiplication, and the lower n bits (0th bit) in the data after multiplication are set. to (n-1)th bit) are set to "0".

In the calculation of "TBL_TZTD_B", "8 ” is multiplied. As a result, the data of the 0th to 12th bits in the data after the subtraction are shifted to the high-order side by 3 bits and set to the high-order 13 bits (the 3rd to 15th bits) in the data after the multiplication. "0" is set to the lower 3 bits (0th bit to 2nd bit) in the data of . As shown in FIG. 33(d), the 3rd to 14th bits of "TBL_TZTD_B", which is the data after multiplication by "8" (data after multiplication), contains the start address "9180H" (FIG. 33(b) )) are set to the 0th to 11th bit data.

As already explained, the acquisition start address in the LDB instruction is calculated by dividing the acquisition data designation data by "8" ("1000B") and adding "9000H", which is the reference address of the data table. be. In addition, as already explained, in the process of calculating the acquisition start address in the LDB instruction, the acquisition data designation data is divided by "8", so that the upper 13 bits (3rd to 15th bits) in the acquisition data designation data are The set data is shifted to the lower 3 bits. When the LDB instruction is executed with "TBL_TZTD_B" derived by shifting the data of the 0th to 12th bits in the data after the subtraction (FIG. 33(c)) to the high-order side by 3 bits as acquisition data designation data, the acquisition "TBL_TZTD_B" is divided by "8" in the process of calculating the start address. In the quotient data after the division, the data of the 0th to 12th bits in the data after the subtraction (FIG. 33(c)) shifted to the upper 3-bit side are shifted to the lower 3-bit side. Then, the start address ("9180H") of the special figure special electric address table 64q is calculated as the acquisition start address by adding "9000H", which is the reference address of the data table, to the quotient data after the division.

In this way, "TBL_TZTD_B" calculated by the formula "{(starting address of special special electric address table 64q) - 9000H} x 8" is obtained by obtaining the starting address of special special electric address table 64q in the LDB command. This is acquisition data designation data for . By setting "TBL_TZTD_B" as acquisition data designation data, the start address of the special figure special electric address table 64q can be used as the acquisition start address of the LDB instruction.

In the address acquisition execution process (FIG. 33(e)) called at line number "1604", if the value of the special special electric counter is "0", "0C00H" stored in the HL register 107 is specified as acquisition data. used as data. On the other hand, if the value of the special special electric counter is "1" or more, the numerical information stored in the HL register 107 is changed to numerical information corresponding to the value of the special special electric counter before the LDB instruction is executed. Be changed.

The command "CALLS LDBADGET" is set at the line number "1604". "LDBADGET" is address acquisition execution processing (FIG. 33(e)), which will be described later. The instruction "CALLS LDBADGET" is an instruction for calling a subroutine called address acquisition execution processing. Details will be described later, but by executing the address acquisition execution process at line number "1604", the start address (any of SA0 to SA6) corresponding to the value of the special special electric counter is set in the HL register 107. be. When the subroutine of the address acquisition execution process is completed, the process proceeds to the line number "1605".

A command "RET" is set at the line number "1605". As already explained, the special figure special electric address acquisition processing is a subroutine executed in step S902 of the special figure special electric control processing (FIG. 30). Therefore, when the command "RET" is executed, the process proceeds to step S903 of the special figure special electric control process (FIG. 30).

Next, program contents of the address acquisition execution process executed by the main CPU 63 will be described. The address acquisition execution process is executed at line number "1604" of the special figure special electric address acquisition process (FIG. 33(a)). FIG. 33(e) is an explanatory diagram for explaining the program contents of the address acquisition execution process executed by the main CPU 63. FIG. FIG. 34 is an explanatory diagram for explaining the correspondence between the value of the special special electric counter and the start addresses SA0 to SA6 acquired by the HL register 107. As shown in FIG.

As shown in FIG. 33(e), "1701" to "1709" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 33(e), "LDBADGET" is set to the line number of "1701". This is not an instruction but data referred to when the developer of the pachinko machine 10 checks the program. Therefore, at line number "1701", the process proceeds to line number "1702" without executing any instruction.

The command "LD A, B" is set at the line number "1702". "LD" is the LD instruction, "A" is the content specifying the A register 104b as the transfer destination, and "B" is the content specifying the B register 105a as the transfer source. As already explained, in the special special electric address acquisition process (Fig. 33(a)), "0CH" ("12") specifying the number of bits to be acquired from the special special electric address table 64q (number of acquisition bits) is stored in the B register 105a. ) is set. Therefore, by executing "LD A, B", "0CH" is set in the "transfer destination" A register 104b.

The command "MUL W, A" is set at the line number "1703". "MUL" is an operation instruction called a MUL instruction, "W" is the content specifying the W register 104a, and "A" is the content specifying the A register 104b. By executing "MUL W, A", an operation of multiplying the value of the W register 104a by the value of the A register 104b is performed and the result of the operation is stored in the WA register 104. FIG. As already explained, in the special figure special electric address acquisition process (FIG. 33(a)), the value of the special figure special electric counter (any integer from 0 to 6) is set in the W register 104a. Further, as described above, the A register 104b stores "0CH", which is the number of acquired bits. Therefore, when "MUL W, A" is executed at line number "1703", the WA register 104 stores the operation result of "(value of special special electric counter) x (number of bits acquired)". be. As already explained, in the line number "1603" of the special special electric address acquisition process (Fig. 33(a)), the HL register 107 contains the acquisition data designation data (" 0C00H") is stored. For the data of the calculation result of "(value of special special electric counter) x (number of bits acquired)", the acquired data designation data stored in the HL register 107 is changed to data corresponding to the value of the special special electric counter. used for

The command "ADD HL, WA" is set at the line number "1704". "ADD" is an arithmetic instruction called an ADD instruction, "HL" is the content specifying the HL register 107, and "WA" is the content specifying the WA register 104. By executing “ADD HL, WA”, the sum of the value of the HL register 107 and the value of the WA register 104 is stored in the HL register 107 . As described above, in the line number "1603" of the special special electric address acquisition process (FIG. 33(a)), the HL register 107 stores the acquisition data designation data ("0C00H") corresponding to the value "0" in the special special electric counter. ”) is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(the value of the special special electric counter) x (the number of acquired bits)".

As shown in FIG. 34, when the value of the special special electric counter is "0", the data added to the value of the HL register 107 at line number "1704" is "0000000000000000B". In this case, the acquired data designation data stored in the HL register 107 does not change. When the value of the special special electric counter is "1", the upper 13 bits of the data added to the value of the HL register 107 at line number "1704" are "0000000000001B", and the lower 3 bits of the data are It is "100B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "1" and the acquisition start bit becomes "4". When the value of the special special electric counter is "2", the upper 13 bits of the data added to the value of the HL register 107 at line number "1704" are "0000000000011B", and the lower 3 bits of the data are It is "000B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "3" and the acquisition start bit becomes "0". When the value of the special special electric counter is "3", the upper 13 bits of the data added to the value of the HL register 107 at line number "1704" are "0000000000100B", and the lower 3 bits of the data are It is "100B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "4" and the acquisition start bit becomes "4". When the value of the special special electric counter is "4", the upper 13 bits of the data added to the value of the HL register 107 at line number "1704" are "0000000000110B", and the lower 3 bits of the data are It is "000B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "6" and the acquisition start bit becomes "0". When the value of the special special electric counter is "5", the upper 13 bits of the data added to the value of the HL register 107 at line number "1704" are "0000000000111B", and the lower 3 bits of the data are It is "100B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "7" and the acquisition start bit becomes "4". When the value of the special special electric counter is "6", the upper 13 bits of the data added to the value of the HL register 107 at line number "1704" are "0000000001001B", and the lower 3 bits of the data are It is "000B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "9" and the acquisition start bit number becomes "0".

In this way, the data of the calculation result of "(value of the special special electric counter) x (number of bits acquired)" stored in the WA register 104 is added to the acquisition data designation data stored in the HL register 107. By doing so, the obtained data specifying data corresponding to the value of the special special electric counter can be stored in the HL register 107 .

At the line number "1705", the command "LD A, B" is set, like the line number "1702". As already explained, "0CH" ("12") designating the number of bits to be acquired is set in the B register 105a in the special special electric address acquisition process (FIG. 33(a)). Therefore, by executing "LD A, B", "0CH" is set in the "transfer destination" A register 104b. As already explained, "0CH" stored in the B register 105a is also used for calculation of "(value of special special electric counter) x (number of bits acquired)". In this way, "0CH" stored in the B register 105a in advance is used for the calculation of "(value of the special special electric counter) x (number of bits acquired)" and specifies the number of bits acquired in the LDB instruction. data to be set in the A register 104b.

The command "DEC A" is set at the line number "1706". "DEC" is an operation instruction called a DEC instruction, and "A" is the contents of specifying the A register 104b. By executing "DEC A", the value of the A register 104b is decremented by one. As described above, the A register 104b stores "0CH", which is the number of acquired bits. Therefore, "0BH" is stored in the A register 104b by executing "DEC A" at line number "1706". "0BH" is a value obtained by subtracting "1" from "12", which is the number of bits obtained from the special special electric address table 64q.

As already explained, when the LDB instruction "LDB HL, (HL).A" is executed, the LDB execution circuit 157 performs an operation to add 1 to the value of the A register 104b, and the value after the addition of 1 is is used as data for the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b at the line number "1706", the number of bits of data acquired from the special special electric address table 64q in the LDB instruction can be set to "12". .

The command "LDB HL, (HL).A" is set at the line number "1707". "LDB" is an LDB instruction by the LDB execution circuit 157, "HL" before the comma is the content specifying the HL register 107 as the "transfer destination", and "(HL)" before the period is the HL register 107 "A" designates the 1-byte data stored in the A register 104b as the acquisition bit number designation data. As already explained, the HL register 107 is in a state where the acquired data designation data corresponding to the value of the special special electric counter is stored, and the A register 104b is changed from the number of acquired bits ("0CH") to "1". , and "0BH" is stored. Also, the TP register 111 is in a state where the reference address "9000H" is stored. In this state, by executing the instruction "LDB HL, (HL).A" at the line number "1707", the 0th to 11th bits of the HL register 107, which is the transfer destination, are the special special electric counter The lower 12-bit data in the start addresses SA0-SA6 corresponding to the value of . are loaded, and the 12th-15th bits of the HL register 107 are masked with "0".

Specifically, as shown in FIG. 34, when the value of the special special electric counter is "0", the acquisition start address is "9180H" and the acquisition start bit is "0", and the HL register 107 "700H", which is the lower 12 bits of the start address SA0, is loaded into the 0th to 11th bits. When the value of the special special electric counter is "1", the acquisition start address is "9181H" and the acquisition start bit is "4", and the 0th to 11th bits of the HL register 107 are lower than the start address SA1 It is loaded with '712H' which is 12 bits. When the value of the special special electric counter is "2", the acquisition start address is "9183H" and the acquisition start bit is "0", and the 0th to 11th bits of the HL register 107 are lower than the start address SA2 It is loaded with '71FH' which is 12 bits. When the value of the special special electric counter is "3", the acquisition start address is "9184H" and the acquisition start bit is "4", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA3 It is loaded with '731H' which is 12 bits. When the value of the special special electric counter is "4", the acquisition start address is "9186H" and the acquisition start bit is "0", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA4 It is loaded with '740H' which is 12 bits. When the value of the special special electric counter is "5", the acquisition start address is "9187H" and the acquisition start bit is "4", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA5 "74CH", which is 12 bits, is loaded. When the value of the special special electric counter is "6", the acquisition start address is "9189H" and the acquisition start bit is "0", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA6 It is loaded with '753H' which is 12 bits. Thus, every time the value of the special figure special electric counter increases by 1, the data acquisition start position in the special figure special electric address table 64q shifts by 12 bits.

By using the LDB instruction to load the lower 12 bits of the start address SA0 to SA6 obtained from the special special electric address table 64q into the 0th to 11th bits of the HL register 107, 2 bytes of acquisition data designation A process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the data and the reference address of the data table set in the TP register 111; bit), a process of loading the lower 12 bits of the start address SA0 to SA6 acquired from the special special electric address table 64q into the lower 12 bits of the HL register 107, and the HL register 107 can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

The command "ADD HL, 9000H" is set at the line number "1708". "ADD" is an operation instruction called an ADD instruction, "HL" is the content specifying the HL register 107, and "9000H" is 2-byte numerical data. By executing “ADD HL, 9000H”, “9000H”, which is the reference address of the data table, is added to the value of the HL register 107 . As a result, as shown in FIG. 34, the entire start addresses SA0 to SA6 (2 bytes) corresponding to the values "0" to "6" in the special electric special figure counter can be set. Specifically, when the value of the special special electric counter is "0", "9700H" which is the start address SA0 is set in the HL register 107, and when the value of the special special electric counter is "1", "9712H" which is the start address SA1 is set in the HL register 107, and "971FH" which is the start address SA2 is set in the HL register 107 when the special figure special electric counter value is "2", and the special figure When the value of the special electric counter is "3", "9731H" which is the start address SA3 is set in the HL register 107, and when the value of the special electric counter is "4", the start address is set in the HL register 107. When "9740H" which is SA4 is set and the value of the special special electric counter is "5", "974CH" which is the start address SA5 is set in the HL register 107, and the value of the special special electric counter is "6". ”, the HL register 107 is set to “9753H” which is the start address SA6.

The command "RET" is set at the line number "1709". As already explained, the address acquisition execution process is a subroutine executed at line number "1604" of the special special electric address acquisition process (FIG. 33(a)). Therefore, by executing the command "RET", it proceeds to the line number "1605" of the special special electric address acquisition process.

Thus, by using the LDB instruction, the lower 12 bits of the start address SA0-SA6 can be loaded into the HL register 107 from the special special electric address table 64q. Further, after the execution of the LDB instruction, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SA0 to SA6 to the value of the HL register 107, the entire start addresses SA0 to SA6 are stored in the HL register 107. can be obtained. Therefore, only the lower 12 bits of the start addresses SA0 to SA6 can be set in the special figure special electric address table 64q. As a result, the data capacity of the special special electric address table 64q in the main ROM 64 can be reduced compared to the configuration in which the entire 2-byte start address SA0 to SA6 is set in the special special electric address table 64q.

<Special figure fluctuation start process>
Next, the contents of the processing of steps S904 to S910 of the special figure special electric control processing (FIG. 30) will be described. First, the special figure variation start processing of step S904 will be described with reference to the flowchart of FIG.

In the special figure fluctuation start process, first, it is determined whether or not the reservation information is stored in either the first special figure reservation area 115 or the second special figure reservation area 116 (step S1001). In step S1001, a negative determination is made when the value of the first special figure reservation number counter 118 is "0" and the value of the second special figure reservation number counter 119 is "0". When the negative determination is made in step S1001, this special figure fluctuation start processing is terminated as it is.

If the affirmative determination is made in step S1001, it is determined whether the value of the second special figure reservation number counter 119 is 1 or more (step S1002), and the value of the second special figure reservation number counter 119 When it is not 1 or more (step S1002: NO), the first special figure data setting process is executed (step S1003). On the other hand, when the value of the second special figure reservation number counter 119 is 1 or more (step S1002: YES), the second special figure data setting process is executed (step S1004). Thus, if the number of reservations in the second special figure reservation area 116 is not "0", that is, if the reservation information for variable display is stored for the second special figure display unit 37b, the first special figure Regardless of whether or not the number of reservations in the reservation area 115 is 1 or more, the data stored in the second special figure reservation area 116 is set for variable display. As a result, when the reservation information is stored in both the first special figure reservation area 115 and the second special figure reservation area 116, it is stored in the second special figure reservation area 116 corresponding to the second operation port 34 The holding information that is held is prioritized as a target for starting the game round.

In the data setting process for the first special figure in step S1003, first, the data stored in the first area 115a of the first special figure reservation area 115 is moved to the execution area 117 for the special figure, and the first special figure reservation The value of the number counter 118 is decremented by one. After that, a process of shifting the data stored in the storage area of the first special figure reservation area 115 is executed. This data shift process is a process of sequentially shifting the data stored in the first to fourth areas 115a to 115d to the lower area side. The data in each area is shifted in the order of first area 115a, third area 115c→second area 115b, fourth area 115d→third area 115c. After that, the second special figure flag provided in the work area 121 for specific control is cleared to "0". The second special figure flag is a flag for specifying which of the first special figure display portion 37a or the second special figure display portion 37b is the start of the current variable display. After that, output a shift command that is information for making the sound and light side CPU 93 recognize that the data in the first special figure reservation area 115 has been shifted, and end this first special figure data setting process do. In the sound and light side CPU 93, by transmitting a command corresponding to the received shift command to the display control device 89, the display of the number of reservation information corresponding to the first special figure reservation area 115 in the pattern display device 41 is displayed. change to correspond to the decrease in Further, as described above, when the number of pending information in the first special figure pending area 115 is reduced, the first special figure pending display unit 37c , display control is performed so that the display content is changed to correspond to the decrease in the number of reserved items.

In the second special figure data setting process in step S1004, first, the data stored in the first area 116a of the second special figure reservation area 116 is moved to the execution area 117 for special figure. After that, the process of shifting the data stored in the storage area of the second special figure reservation area 116 is executed. This data shift process is a process for sequentially shifting the data stored in the first to fourth areas 116a to 116d to the lower area side. Data in each area is shifted in the order of first area 116a, third area 116c→second area 116b, fourth area 116d→third area 116c. After that, "1" is set to the second special figure flag in the work area 121 for specific control. After that, it outputs a shift time command, which is information for making the sound and light side CPU 93 recognize that the data of the second special figure reservation area 116 has been shifted, and ends this data setting process. In the sound and light side CPU 93, by transmitting a command corresponding to the received shift command to the display control device 89, the display of the number of reservation information corresponding to the second special figure reservation area 116 in the pattern display device 41 is displayed. change to correspond to the decrease in Also, as described above, when the number of pending information in the second special figure pending area 116 is reduced, in the display control process of step S514 in the timer interrupt process (FIG. 26), the second special figure pending display unit 37d , display control is performed so that the display content is changed to correspond to the decrease in the number of reserved items.

When the process of step S1003 or the process of step S1004 is executed, is the high-probability mode flag provided in the mode data area in the work area 121 for specific control set to "1"? By determining whether or not, it is determined whether or not the mode is the high-probability mode (step S1005). The high-probability mode flag is a flag for the main CPU 63 to specify that the win/fail lottery mode is the high-probability mode. The high-probability mode flag is set to "1" when the opening/closing execution mode ends regardless of the kind of the result of the big win that triggered the execution. The high probability mode flag is set in the second bit in the mode data area. In step S1005, an affirmative determination is made when the high probability mode flag is set to "1".

If the determination in step S1005 is affirmative, high-probability determination processing is executed (step S1006). As already explained with reference to FIG. 13, the main ROM 64 has a highly accurate validity table 64g that is referred to regardless of whether the current setting value of the pachinko machine 10 is "setting 1" to "setting 6". remembered. In the high-probability judging process in step S1006, with reference to the high-probability table 64g, among the information stored in the execution area 117 for the special figure, the information for judging the propriety, that is, the numerical information acquired from the random number counter C1 matches the big hit numerical information or the small hit numerical information set in the high probability table 64g.

The work area 121 for specific control is provided with a pass/fail data area 158 in which data corresponding to the result of the pass/fail determination process is set. FIG. 36(a) is an explanatory diagram for explaining the structure of the success/failure data area 158. FIG. The pass/fail data area 158 is an area consisting of 1 byte. As shown in FIG. 36(a), the 0th bit of the success/failure data area 158 is set with a small hit flag 158b, and the 1st bit is set with a big hit flag 158a. In addition, the 2nd to 7th bits of the pass/fail data area 158 are unused bits. The big hit flag 158a is a flag that enables the main side CPU 63 to grasp that a big hit result has been obtained in the success/failure determination process. This is a flag that can be grasped by the CPU 63 .

In the high-probability success/failure determination process in step S1006, data “00000010B” is set in the success/failure data area 158 when the numerical information obtained from the winning random number counter C1 matches the big winning numerical information. Thereby, "1" can be set to the jackpot flag 158a. Also, when the numerical value information obtained from the winning random number counter C1 matches the small winning numerical value information, data “00000001B” is set in the success/failure data area 158 . Thereby, "1" can be set to the small hit flag 158b.

FIG. 36(b) is an explanatory diagram for explaining the contents of the high-probability table 64g, and FIG. 36(c) is an explanatory diagram for explaining the data structure of the high-probability table 64g. As shown in FIG. 36(c), the high certainty table 64g is stored in the main ROM 64 in the address range of "9220H" to "945BH".

As already explained, the numerical information obtained from the winning random number counter C1 is any integer from 0 to 7,999. As shown in FIG. 36(b), 266 pieces of jackpot numerical information including "30", "60", "90" and "7999" are set in the high probability table 64g, and "75" 40 pieces of small winning numerical information including are set. Also, in the high-probability table 64g, a judgment value HVn (n is an integer of 1 to 572) for judging the validity and flag data FDn (n is an integer of 1 to 572) corresponding to the judgment value are set. It is The determination value HVn is 6-bit numerical data corresponding to any integer of 1-31.

The flag data FDn is 2-bit data set in the lower 2 bits (0th to 1st bits) of the yes/no data area 158 . Like flag data FD2, FD4, FD8 and FD572, the flag data corresponding to the big win result is "10B". When the flag data corresponding to the big win result is set in the lower two bits of the win/fail data area 158, the big win flag 158a is set to "1" and the value of the small win flag 158b becomes "0". Like the flag data FD6, the flag data corresponding to the small winning result is "01B". By setting the flag data corresponding to the result of the small win to the lower two bits of the win/fail data area 158, the small win flag 158b is set to "1" and the value of the big win flag 158a becomes "0". The flag data corresponding to the outlier result, such as the flag data FD1, FD3, FD5, FD7 and FD571, is "00B". The value of the big hit flag 158a and the small hit flag 158b becomes "0" by setting the flag data corresponding to the result of the deviation to the lower 2 bits of the success/failure data area 158. FIG.

Next, the high-probability right/wrong determination process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 37(a). The high probability propriety determination process is executed in step S1006 of the special figure fluctuation start process (FIG. 35). The high-probability right/wrong determination process is executed using a program for specific control and data for specific control.

In the high-probability right/wrong determination process, first, a command "LD HL, 1150H" is executed (step S1101). "LD" is the LD instruction, "HL" is the content specifying the HL register 107 as the transfer destination, and "1100H" is 2-byte numerical information. In the data acquisition process (step S1103) to be described later, one judgment value HVn out of the 572 judgment values HV1 to HV572 set in the high-probability judgment table 64g (FIGS. 36(b) and (c)) (n is any one of 1 to 572) is executed in the WA register 104, the LDB update instruction "LDB WA, (HL+).5" is executed, and the determination value HVn obtained in the WA register 104 is In order to obtain the flag data FDn corresponding to the B register 105a, an LDB update instruction "LDB B, (HL+).1" is executed. In the high-probability right/wrong determination process (FIG. 37(a)), the processes of steps S1103 to S1105 are repeatedly executed until an affirmative determination is made in step S1105. The combination of the determination value HVn and the flag data FDn acquired by the WA register 104 and the B register 105a in the pass/fail determination data acquisition process in step S1103 is the combination of HV1 and FD1→the combination of HV2 and FD2→the combination of HV3 and FD3. → … → the combination of the HV 572 and the FD 572 is updated. The numerical value "1100H" indicates that the judgment value HV1 and the flag data are stored in the WA register 104 and B register 105a when the winning judgment data acquisition process (step S1103) is executed for the first time in the current processing round (game round). It is a numerical value for obtaining a combination of FD1. By executing the instruction "LD HL, 1150H" in step S1101, the HL register 107 is loaded with "1100H". Details of the numerical value "1100H" and the LDB update instruction will be described later.

After "1100H" is loaded into the HL register 107 in step S1101, the information for judging whether or not the information stored in the special figure execution area 117, that is, any of 0 to 7999 obtained from the winning random number counter C1 This numerical value information (2 bytes) is set in the DE register 106 (step S1102).

After that, a data acquisition process for judging whether or not it is correct is executed (step S1103). As described above, by executing the correctness determination data acquisition process, one of the 572 determination values HV1 to HV572 set in the high certainty correctness table 64g (FIGS. 36(b) and (c)) The determination value HVn is set in the WA register 104, and the flag data FDn corresponding to the determination value HVn set in the WA register 104 is set in the B register 105a. The details of the win-or-fail determination data acquisition process will be described later.

After that, the value of the WA register 104 is subtracted from the value of the DE register 106 (step S1104). As already explained, in step S1102, the DE register 106 is set with 2-byte numerical information (one of 0 to 7999) obtained from the winning random number counter C1, and in step S1103, the WA register 104 is set with the determination result. A value HVn is set. Therefore, when the process of step S1104 is executed for the first time in the current process round (game round), the process of subtracting the determination value HV1 from the numerical information acquired from the winning random number counter C1 is executed in the step S1104. . In addition, when the process of step S1104 is executed for the (m+1)th time (m is any integer from 1 to 571) in the current processing round (game round), the numerical value obtained from the winning random number counter C1 in the step S1104 A process of subtracting the determination value HV(m+1) from the numerical information obtained by subtracting the m determination values HV1 to HVm from the information is executed.

After that, it is determined whether or not the value of the DE register 106 is less than "0" (step S1105). If the calculation result in step S1104 is "0" or more, the value of the carry flag is set to "0", and if the calculation result is less than "0", the carry flag is set to "1". be done. In step S1105, an affirmative determination is made when the carry flag is set to "1". If the value of the DE register 106 is not less than "0" (step S1105: NO), the process returns to step S1103. Then, the processing of steps S1103 to S1105 is repeatedly executed until an affirmative determination is made in step S1105. As a result, the judgment value HVn is subtracted in the order of HV1→HV2→HV3→...→HV572 from the numerical value information acquired from the winning random number counter C1 to the DE register 106 in step S1102, and the calculation result is determined to be less than "0". The flag data FDn corresponding to the determination value HVn that is not obtained can be specified as the winning flag data.

If an affirmative determination is made in step S1105, the flag data FDn stored in the B register 105a, that is, the winning flag data FDn is set in the win/fail data area 158 in the work area 121 for specific control. (Step S1106), this high-probability right/wrong determination processing ends. In step S1106, when the flag data FDn corresponding to the big winning result is set in the winning data area 158, the big winning flag 158a is set to "1", and the flag data FDn corresponding to the small winning result is set to the winning data area 158. , "1" is set to the small hit flag 158b. Further, when the flag data FDn corresponding to the result of the deviation is set in the success/failure data area 158, the values of the big hit flag 158a and the small hit flag 158b become "0".

<LDB update instruction>
Next, prior to the explanation of the success judgment data acquisition process (step S1103), the LDB update command included in the success judgment data acquisition process will be explained. As already explained, the pass/fail determination data acquisition process includes LDB update commands of "LDB WA, (HL+).5" and "LDB B, (HL+).1." As shown in FIG. 9, the main MPU 62 has an LDB update execution circuit 161 which is a dedicated circuit for executing LDB update instructions, and the main CPU 63 can execute LDB update instructions.

The instruction code of the LDB update instruction has a configuration of "LDB transfer destination, (acquisition data designation +). acquisition bit number designation". In addition to the processing executed by the LDB instruction, the LDB update instruction adds the number of acquisition bits to the acquisition data designation data stored in the "acquisition data designation" register after the processing is executed and updates it. This is an instruction that enables processing to be executed with a single instruction.

As with the LDB instruction, the LDB update instruction sets a general-purpose register or a pair register as a "transfer destination." The general-purpose register set as the "transfer destination" in the LDB update instruction is the W register 104a or the B register 105a. The WA register 104 is the pair register set as the “transfer destination” in the LDB update instruction. It should be noted that the A register 104b, the C register 105b, the D register 106a, the E register 106b, the H register 107a, or the L register 107b may be set as the "transfer destination" general-purpose register in the LDB update instruction. Alternatively, the BC register 105 or the DE register 106 may be set as the "transfer destination" pair register in the LDB update instruction.

In the LDB update command, "(HL+)" is set as "acquisition data designation". In the LDB update instruction, similarly to the LDB instruction, based on the acquired data designation data stored in the HL register 107 set as "acquired data designation", acquisition of data to be loaded into the "transfer destination" register is started. The address and acquisition start bit number are specified.

If a 1-byte general-purpose register (W register 104a or B register 105a) is set as the "transfer destination", the LDB update command specifies any number from "0" to "7" as the "specify number of bits to acquire". is set. When the 2-byte WA register 104 is set as the "transfer destination", any numerical value from "0" to "15" is set as the "specify number of bits to be acquired" in the LDB update command.

In the LDB update instruction, in the main ROM 64, the data for the number of acquisition bits set after the acquisition start address in the acquisition start address is loaded into the area on the lower side of the WA register 104, which is the "transfer destination". The upper area of the WA register 104 is masked with "0". After that, the acquired data designation data stored in the HL register 107 is updated by adding the number of bits acquired this time to the value of the HL register 107 storing the acquired data designation data.

a process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111 by using the LDB update instruction; , a process of specifying the acquisition start bit corresponding to the 0th to 2nd bits (lower 3 bits) of the acquisition designation data, and the acquisition bit set after the acquisition start bit in the acquisition start address in the main ROM 64 A process of loading several minutes of data into the lower bits of the "transfer destination" register, a process of masking the upper bits of the "transfer destination" register with "0", and the value of the HL register 107 after the data transfer. A process of adding the acquired bit number and updating the acquired data designation data can be executed with one instruction. These processes are executed by the LDB update execution circuit 161 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

Next, the success/failure determination data acquisition process executed in step S1103 of the high-probability success/failure determination process (FIG. 37(a)) will be described.

FIG. 37(b) is an explanatory diagram for explaining the contents of a program for the data acquisition process for judging whether or not a match has been made. FIG. 37(c) is an explanatory diagram for explaining how the determination value HVn is set in the WA register 104, and FIG. 37(d) explains how flag data FDn is set in the B register 105a. It is an explanatory view for doing.

As shown in FIG. 37(b), "1801" to "1803" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 37(b), the command "LDB WA, (HL+).5" is set at the line number "1801". "LDB" is an LDB update command by the LDB update execution circuit 161, "WA" is the content specifying the WA register 104 as the "transfer destination", and "(HL+)" is the 2 data stored in the HL register 107. It specifies byte data as acquisition data designation data and instructs to update the acquisition data designation data stored in the HL register 107 after loading the data. 5” is set.

38(a) to 38(e) are the start address of the high accuracy table 64g, acquisition data designation data in the LDB instruction (“LDB WA, (HL+).5”), acquisition start address, acquisition start bit, and FIG. 11 is an explanatory diagram for explaining acquisition data designation data after update. As already described, numerical information "1100H" is set in the HL register 107 in step S1101 of the high certainty validity determination process (FIG. 37(a)). As shown in FIG. 38B, "1100H" is acquired data designation data when the LDB instruction "LDB WA, (HL+).5" is executed for the first time. As already explained, the start address of the high certainty table 64g is "9220H" (see FIG. 38(a)). "1100H" is numerical value information calculated by the formula "{(start address of high certainty table 64g) - 9000H} x 8". As shown in FIG. 38(b), in the 3rd to 14th bits in the acquisition data designation data (“1100H”), the start address of the high probability table 64g “9220H” (FIG. 38(a)) Data of the 0th to 11th bits are set.

As already explained, the acquisition start address is the reference address "9000H" of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquisition data designation data by "8" ("1000B"). ” is calculated by adding When an LDB update instruction is executed with "1100H" stored in the HL register 107 as acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1100H" by "8". " is calculated by adding "9220H". As shown in FIG. 38(c), the 0th to 11th bit data at the acquisition start address are the 3rd to 14th bit data of the acquisition data designation data (the 0th bit at the start address of the high accuracy table 64g). to 11th bit data), and the 12th to 15th bit data at the acquisition start address are the 12th to 15th bit data at the reference address of the data table. The acquisition start address "9220H" is the start address of the high certainty table 64g.

As already explained, the acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00000111H". When an LDB update instruction is executed with "1100H" stored in the HL register 107 as acquisition data designation data, the acquisition start bit is the lower 1 byte ("00000000B") and "00000111H" of the acquisition data designation data. and "00000000B" ("0"). As shown in FIG. 38(d), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the lower 3 bits (0th to 2nd bits) in the acquisition data designation data (FIG. 38(b)). bit), and the data of the upper 5 bits (3rd to 7th bits) at the acquisition start bit is "0".

In the LDB update instruction "LDB WA, (HL+).5", a numerical value "5" is set as acquisition bit specification data, so the number of acquisition bits is obtained by adding "1" to "5". "6" is obtained. When the LDB update instruction "LDB WA, (HL+).5" is executed with "1100H" stored in the HL register 107, as shown in FIG. , the data (HV1) for the number of acquisition bits (6 bits) set after the acquisition start bit (0th bit) of the area corresponding to the acquisition start address "9220H" is transferred to the WA The 0th to 5th bits (lower 6 bits) of the register 104 are loaded, and the 6th to 15th bits (upper 10 bits) of the WA register 104 are masked with "0". As a result, the determination value HV1 can be set in the WA register 104. FIG.

As described above, the number of bits acquired in the LDB update instruction "LDB WA, (HL+).5" is "6". Therefore, in the LDB update instruction, after 6-bit data is loaded into the 0th to 5th bits of the WA register 104, the value of the HL register 107 ("1100H") is changed to the acquired bit number ("6"). After the addition, the value of the HL register 107 is updated to "1106H" as shown in FIG. 38(e).

"1106H" is numerical information in which the acquisition start address is set to "9220H" and the acquired bit is the sixth bit when the next LDB update instruction is executed using the acquired data designation data as "1106H". . In this way, when the LDB update instruction is executed and the acquisition data designation data stored in the HL register 107 is updated, the number of acquired bits in the LDB update instruction is executed next to the LDB update instruction. The data acquisition start position is shifted in the LDB update instruction.

In this way, by setting the determination value data DV1 acquired from the highly accurate validity table 64g using the LDB update command in the WA register 104 and updating the acquisition data specification data, the acquisition data specification of 2 bytes can be achieved. A process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the data and the reference address of the data table set in the TP register 111; bit), a process of loading the determination value data DV1 acquired from the high probability table 64g into the 0th to 5th bits (lower 6 bits) of the WA register 104, and the A process of masking the 6th to 15th bits (upper 10 bits) of the WA register 104 with "0", a process of adding the number of bits acquired this time to the value of the HL register 107, and updating the acquired data designation data; can be executed with one command. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

The command "LDB B, (HL+).1" is set at the line number "1802". "LDB" is an LDB update command by the LDB update execution circuit 161, "B" is the content specifying the B register 105a as the "transfer destination", and "(HL+)" is the 2 data stored in the HL register 107. Byte data is specified as acquisition data designation data, and the acquisition data designation data stored in the HL register 107 is updated after data transfer. ” is the content to set.

39(a) to 39(c) show the acquisition data designation data, acquisition start address, acquisition start bit, and updated acquisition data designation data in the LDB instruction (“LDB B, (HL+).1”). It is an explanatory view for explaining. As already explained, the acquisition start address is the reference address ("9000H") of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquisition data designation data by "8" ("1000B"). ) is added. When an LDB update instruction is executed with "1106H" stored in the HL register 107 as acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1106H" by "8". " is calculated by adding "9220H". As shown in FIG. 39(a), the 0th to 11th bit data at the acquisition start address are the 3rd to 14th bit data of the acquisition data designation data, and the 12th to 12th bit data at the acquisition start address. The 15th bit data is the 12th to 15th bit data in the reference address of the data table. The acquisition start address "9220H" is the start address of the high certainty table 64g.

As already explained, the acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00000111H". When an LDB update instruction is executed with "1106H" stored in the HL register 107 as acquisition data designation data, the acquisition start bit is the lower 1 byte ("00000110B") and "00000111H" of the acquisition data designation data. and "00000110B" ("6"). As shown in FIG. 39(b), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the data of the lower 3 bits (0th to 2nd bits) in the acquisition data designation data. , the data of the upper 5 bits (3rd to 7th bits) at the acquisition start bit is "0".

In the LDB update instruction "LDB B, (HL+).1", the value "1" is set as the acquisition bit specification data, so the number of acquisition bits is obtained by adding "1" to the "1". "2" is obtained. When the LDB update instruction "LDB B, (HL+).1" is executed with "1106H" stored in the HL register 107, as shown in FIG. , the data (flag data FD1) for the number of acquisition bits (2 bits) set after the acquisition start bit (6th bit) of the area corresponding to the acquisition start address "9220H" is transferred to the transfer destination. The 0th to 1st bits (lower 2 bits) of a certain D register 106a are loaded, and the 2nd to 7th bits (higher 6 bits) of the D register 106a are masked with "0". As a result, the flag data FD1 corresponding to the determination value HV1 stored in the WA register 104 can be set in the D register 106a.

As described above, the number of acquired bits in the LDB update instruction "LDB B, (HL+).1" is "2". Therefore, in the LDB update instruction, after 2-bit data is loaded into the 0th to 1st bits of the B register 105a, the value of the HL register 107 ("1106H") is changed to the acquired bit number ("2"). After the addition, the value of the HL register 107 is updated to "1108H" as shown in FIG. 39(c).

"1108H" is numerical information that sets the acquisition start address to "9221H" and sets the acquired bit to the 0th bit when the next LDB update instruction is executed using the acquired data designation data as "1108H". . In this way, when the LDB update instruction is executed and the acquisition data designation data stored in the HL register 107 is updated, the number of acquired bits in the LDB update instruction is executed next to the LDB update instruction. The data acquisition start position is shifted in the LDB update instruction.

By executing the LDB update instruction "LDB WA, (HL+).5" and the LDB update instruction "LDB B, (HL+).1", the judgment value HV1 and the flag data are stored in the WA register 104 and the D register 106a. FD1 is set. Also, by increasing the value of the HL register 107 by "8" (the sum of "6" and "2"), the LDB update instruction "LDB WA, (HL+).5" and "LDB B, (HL+).5" are executed. The acquisition start address in the LDB update instruction of "1" is incremented by "1".

In this way, by setting the flag data FD1 acquired from the high accuracy table 64g using the LDB update instruction to the B register 105a to update the acquisition data designation data, the 2-byte acquisition data designation data and the acquisition start address corresponding to the data of the 3rd to 15th bits and the reference address of the data table set in the TP register 111; bit), a process of loading the flag data FD1 acquired from the high certainty table 64g into the 0th to 1st bits (lower 2 bits) of the B register 105a, and the B A process of masking the 2nd to 7th bits (upper 6 bits) of the register 105a with "0" and a process of adding the number of bits to be acquired to the value of the HL register 107 to update the acquired data designation data are executed as one instruction. can be run with These processes are executed by the LDB update execution circuit 161 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

A command "RET" is set at the line number "1803". As already described, the win-or-fail judgment data acquisition process is a subroutine executed in step S1103 of the high-probability win-or-fail judgment process (FIG. 37(a)). Therefore, by executing the command "RET", the process advances to step S1104 of the high-probability determination process.

As already described, in the high-probability right/wrong determination process (FIG. 37(a)), the processes of steps S1103 to S1105 are repeatedly executed until an affirmative determination is made in step S1105. FIG. 40 shows the number of executions of the LDB update instruction "LDB WA, (HL+).5" and the LDB update instruction "LDB B, (HL+).1", and the WA register 104 and B register 105a by these LDB update instructions. FIG. 10 is an explanatory diagram for explaining data acquired in . As shown in FIG. 40, in the second row number “1801”, “LDB WA, (HL+).5” is executed using “1108H” as acquisition data designation data, and the determination value HV2 is set in the WA register 104. be. Then, the value of the HL register 107 is updated to "110EH". At the second line number "1802", "LDB B, (HL+).1" is executed with "110EH" as the acquisition data designation data, and the flag data FD2 corresponding to the determination value HV2 is set in the B register 105a. be done. Then, the value of the HL register 107 is updated to "1110H".

In this way, by using the high probability table 64g to repeatedly execute the data acquisition process for judgment, the combination of the judgment value HVn and the flag data FDn set in the high probability table 64g is reduced to 1 Each set can be loaded into the WA register 104 and the B register 105a in sequence.

Returning to the description of the special figure fluctuation start processing (FIG. 35), when the negative determination is made in step S1005, that is, when it is the low probability mode, low certainty determination processing is executed (step S1007). As already described with reference to FIG. 13, the main-side ROM 64 stores low-probability tables 64a-64f for settings 1-6. In the low accuracy determination process in step S1007, with reference to the low accuracy tables 64a to 64f corresponding to the current setting values of the pachinko machine 10, among the information stored in the special figure execution area 117 information, that is, the numerical information obtained from the winning random number counter C1 is determined whether or not it matches the big winning numerical information or the small winning numerical information set in the low accuracy tables 64a to 64f. When the numerical information obtained from the winning random number counter C1 matches the low-probability jackpot numerical information corresponding to the set value, by setting the data "00000010B" in the hit/fail data area 158, the jackpot flag 158a is set. is set to "1". Further, when the numerical value information obtained from the winning random number counter C1 matches the small winning numerical information, by setting the data "00000001B" in the win/fail data area 158, the small winning number in the work area 121 for specific control "1" is set in the hit flag 158b.

When the process of step S1006 is performed, or when the process of step S1007 is performed, it is determined whether or not "1" is set in the big hit flag 158a (step S1008), and "1" is set in the big hit flag 158a. is set (step S1008: YES), the first result handling process is executed (step S1009). In the first result handling process, a process for distributing the jackpot type is executed, and the fluctuation type number corresponding to the jackpot type is set in the fluctuation type number counter provided in the work area 121 for specific control. The variation type number is the result of the success or failure determination from the variation pattern table described later, the result of the distribution determination, the result of the reach generation lottery, and the stop result data and display duration data corresponding to the number of reservations in the special figure reservation areas 115 and 116. This is the data to acquire. The variation type number is any numerical information from 0 to 23. The variation type number counter is a counter that enables the main side CPU 63 to grasp the variation type number. The variation type number counter consists of 1 byte. Details of the first result handling process will be described later.

When a negative determination is made in step S1008, a second result handling process corresponding to the small hit result or the missing result is executed (step S1010). In the second result correspondence process, when "1" is set to the small hit flag 158b, the change type number corresponding to the small hit result is set in the change type number counter. In addition, when "1" is not set to the small hit flag 158b, that is, when the result is a losing result, a reach generation lottery is performed, and the variation type number corresponding to the result of the reach generation lottery is set in the variation type number counter. . Details of the second result handling process will be described later.

Here, the first special figure distribution process and the second special figure distribution process performed in the first result correspondence process (step S1009) will be described.

In the first special figure distribution process and the second special figure distribution process, it is distributed to one of the 4R high probability jackpot result, the 8R high probability jackpot result and the 16R high probability jackpot result. The work area 121 for specific control is provided with a distribution data area 162 in which the result of distribution determination is set. FIG. 41(a) is an explanatory diagram for explaining the configuration of the distribution data area 162. FIG. The distribution data area 162 is an area consisting of 1 byte.

As shown in FIG. 41(a), the 0th bit of the distribution data area 162 is set with the 4R high-precision flag 162a, the 1st bit is set with the 8R high-precision flag 162b, and the second A 16R high accuracy flag 162c is set in the bit. Also, the third to seventh bits of the distribution data area 162 are unused bits. The 4R high probability flag 162a is a flag that enables the main side CPU 63 to grasp that the 4R high probability big hit result has occurred, and the 8R high probability flag 162b is a flag that the main side CPU 63 can recognize that the 8R high probability big hit result has occurred. The 16R high probability flag 162c is a flag that enables the main side CPU 63 to grasp that the 16R high probability big hit result has occurred.

In the first special figure distribution process or the second special figure distribution process, data "00000001B" is set in the distribution data area 162 when the 4R high probability jackpot result is distributed. As a result, "1" is set to the 4R high accuracy flag 162a. Also, in these distribution processes, when the 8R high-probability jackpot results are distributed, the distribution data area 162 is set with data “00000010B”. As a result, "1" is set to the 8R high accuracy flag 162b. Furthermore, in these sorting processes, data "00000100B" is set in the sorting data area 162 when sorted to the 16R high-probability jackpot result. As a result, the 16R high accuracy flag 162c is set to "1".

In the first special figure distribution process, the first special figure distribution table 64h in the main ROM 64 is used. As shown in FIG. 14 (a), in the first special figure distribution table 64h, when the value obtained from the jackpot type counter C2 is any of 0 to 39, it is distributed to the 4R high probability jackpot result, and the jackpot If the value obtained from the type counter C2 is any one of 40 to 79, it is distributed to the 8R high probability jackpot result. In addition, when the value obtained from the jackpot type counter C2 is any one of 80 to 99, it is distributed to the 16R high probability jackpot result.

In the first special figure distribution table 64h, "20" is set as the first pre-addition distribution value FVA1 corresponding to the 4R high probability big hit result, and before the second addition corresponding to the 8R high probability big hit result "20" is set as the distribution value FVA2, and "0" is set as the third pre-addition distribution value FVA3 corresponding to the 16R high-probability big hit result. These pre-addition distribution values FVAn (n is an integer of 1 to 3) are 5-bit data. In the first special figure distribution process, by uniformly adding "20" to these pre-addition distribution values FVAn, the first distribution value "40" and the second distribution value "40" and "20", which is the third distribution value, are calculated. Then, in the order of the first distribution value → second distribution value → third distribution value, these distribution values are subtracted from the value obtained from the jackpot type counter C2, and the subtraction result is less than "0" If so, flag data FDAn corresponding to the distribution value is set in the distribution data area 162 . As a result, the main CPU 63 can grasp the result of the allocation determination.

As shown in FIG. 14(a), in the first special figure distribution table 64h, 3-bit "001B" is set as the first flag data FDA1 corresponding to the 4R high probability jackpot result, and the 8R high 3-bit "010B" is set as the second flag data FDA2 corresponding to the high-probability jackpot result, and 3-bit "100B" is set as the third flag data FDA3 corresponding to the 16R high-probability jackpot result. These flag data FDA1 to FDA3 are set in the lower 3 bits (0th to 2nd bits) of the distribution data area 162, and the upper 5 bits (3rd to 7th bits) of the distribution data area 162 are set to "0 ” is masked.

FIG. 41(b) is an explanatory diagram for explaining the data configuration of the first special figure distribution table 64h. As shown in FIG. 41(b), the first special figure distribution table 64h is stored in the address range of "9250H" to "9252H" in the main ROM64. The first pre-addition distribution value FVA1 corresponding to the 4R high probability jackpot result is set to the 0th to 4th bits of "9250H" which is the start address of the first special figure distribution table 64h, and the 1st The first flag data FDA1 is set in the 5th to 7th bits. The 0th to 4th bits of "9251H" following "9250H" are set to the second pre-addition distribution value FVA2 corresponding to the 8R high probability jackpot result, and the 5th to 7th bits are set to the second Flag data FDA2 is set. The 0th to 4th bits of "9252H" following "9251H" are set to the third pre-addition distribution value FVA3 corresponding to the 16R high probability jackpot result, and the 5th to 7th bits are set to the third Flag data FDA3 is set.

As shown in FIG. 41(b), the flag data FDAn is 3-bit data, and the pre-addition distribution value FVAn is 5-bit data. Since the combination of corresponding flag data FDAn and pre-addition apportionment value FVAn is 1-byte data, three combinations of flag data FDAn and pre-addition apportionment value FVAn are stored in a 3-byte storage area. can be kept The second distribution value "40" ("101000B") is 6-bit numerical information in binary notation. A storage area of 9 bits or more is required to store the combination of the second flag data FDA2 and the second distribution value. Therefore, if the combination of the three flag data FDAn and the distribution value is stored in the first special figure distribution table 64h, the data of the first special figure distribution table 64h in the main ROM 64 Capacity increases. On the other hand, the combination of the flag data FDAn and the pre-addition distribution value FVAn obtained by subtracting 20 from the distribution value is stored in the first special figure distribution table 64h. The data capacity of the first special figure distribution table 64h can be reduced.

In the second special figure distribution process, the second special figure distribution table 64j in the main ROM 64 is used. As shown in FIG. 14(b), in the second special figure distribution table 64j, when the value obtained from the jackpot type counter C2 is any of 0 to 29, it is distributed to the 4R high probability jackpot result, and the jackpot If the value obtained from the type counter C2 is any one of 30 to 79, it is distributed to the 8R high probability jackpot result. In addition, when the value obtained from the jackpot type counter C2 is any one of 80 to 99, it is distributed to the 16R high probability jackpot result.

In the second special figure distribution table 64j, "10" is set as the first pre-addition distribution value FVB1 corresponding to the 4R high probability big hit result, and the second pre-addition corresponding to the 8R high probability big hit result "30" is set as the distribution value FVB2, and "0" is set as the third pre-addition distribution value FVB3 corresponding to the 16R high-probability big hit result. These pre-addition distribution values FVBn (n is an integer of 1 to 3) are 5-bit data. In the second special figure distribution process, by uniformly adding "20" to these pre-addition distribution values FVBn, the first distribution value "30" and the second distribution value "50" and "20", which is the third distribution value, are calculated. Then, in the order of the first distribution value → second distribution value → third distribution value, these distribution values are subtracted from the value obtained from the jackpot type counter C2, and the subtraction result is less than "0" If so, the corresponding flag data FDBn is set in the distribution data area 162 .

As shown in FIG. 14(b), in the second special figure distribution table 64j, 3-bit "001B" is set as the first flag data FDB1 corresponding to the 4R high probability jackpot result, and the 8R high 3-bit "010B" is set as the second flag data FDB2 corresponding to the high-probability jackpot result, and 3-bit "100B" is set as the third flag data FDB3 corresponding to the 16R high-probability jackpot result. These flag data FDB1 to FDB3 are set in the lower 3 bits of the distribution data area 162, and the upper 5 bits of the distribution data area 162 are masked with "0".

FIG. 41(c) is an explanatory diagram for explaining the data configuration of the second special figure distribution table 64j. As shown in FIG. 41(c), the second special figure distribution table 64j is stored in the address range of "9253H" to "9255H" in the main ROM64. The first pre-addition distribution value FVB1 corresponding to the 4R high probability jackpot result is set to the 0th to 4th bits of "9253H" which is the start address of the second special figure distribution table 64j, and the The first flag data FDB1 is set in the 5th to 7th bits. The 0th to 4th bits of "9254H" following "9253H" are set to the second pre-addition distribution value FVB2 corresponding to the 8R high probability jackpot result, and the 5th to 7th bits are set to the second Flag data FDB2 is set. The 0th to 4th bits of "9255H" following "9254H" are set to the third pre-addition distribution value FVB3 corresponding to the 16R high probability jackpot result, and the 5th to 7th bits are set to the third Flag data FDB3 is set.

Next, the first result handling process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The first result correspondence process is executed in step S1009 of the special figure fluctuation start process (FIG. 35). Note that the first result handling process is executed using a program for specific control and data for specific control.

In the first result correspondence process, information for allocation determination among the pending information stored in the execution area 117 for the special figure, that is, numerical information (jackpot type random number) acquired from the jackpot type counter C2 is transferred to the A register 104b set (step S1201). After that, it is determined whether or not "1" is set to the second special figure flag in the work area 121 for specific control (step S1202). As already explained, the second special figure flag is set to "1" when the second special figure data setting process (step S1004) is executed in the special figure fluctuation start process (FIG. 35). When "1" is set to the second special figure flag, it means that the start of the current variation display is the second special figure display portion 37b.

When "1" is not set to the second special figure flag (step S1202: NO), the command "LD HL, 1280H" is executed (step S1203). "LD" is the LD instruction, "HL" is the content specifying the HL register 107 as the transfer destination, and "1280H" is 2-byte numerical information. In the distribution data acquisition process (step S1205) described later, if the second special figure flag is not set to "1", it is set in the first special figure distribution table 64h (FIG. 41(b)). In order to acquire one pre-addition apportionment value FVAn (n is any one of 1 to 3) out of the three pre-addition apportionment values FVA1 to FVA3 in the W register 104a, "LDB W, (HL+).4 " is executed, and "LDB B, (HL+).2" is executed to acquire the flag data FDAn corresponding to the pre-addition apportionment value FVAn acquired in the W register 104a into the B register 105a. is executed. In this first result handling process (FIG. 42), the processes of steps S1205 to S1208 are repeatedly executed until an affirmative determination is made in step S1208. The combination of pre-addition apportionment value FVAn and flag data FDAn acquired by W register 104a and B register 105a in the apportioning data acquisition process in step S1205 is as follows: combination of FVA1 and FDA1→combination of FVA2 and FDA2→FVA3 and It is updated in the order of the combination of FDA3. The numerical value “1280H” is the pre-addition distribution value FVA1 in the W register 104a and the B register 105a when the distribution data acquisition process (step S1205) is executed for the first time in the current processing round (game round). and flag data FDA1. By executing the instruction "LD HL, 1280H" in step S1203, the HL register 107 is loaded with "1280H". As already explained, the start address of the first special figure distribution table 64h is "9250H". "1280H" is data calculated by "{(start address of first special figure distribution table 64h)-9000H}×8". Acquisition data designation data set in the HL register 107 is used when an LDB update instruction is executed in the sorting data acquisition process (step S1205).

On the other hand, when "1" is set to the second special figure flag (step S1202: YES), the command "LD HL, 1298H" is executed (step S1204). "LD" is the LD instruction, "HL" is the content specifying the HL register 107 as the transfer destination, and "1298H" is 2-byte numerical information. In the distribution data acquisition process (step S1205) described later, when the second special figure flag is set to "1", it is set in the second special figure distribution table 64j (FIG. 41(c)). In order to acquire one pre-addition distribution value FVBn (n is any one of 1 to 3) out of the three pre-addition distribution values FVB1 to FVB3 in the W register 104a, "LDB W, (HL+).4 ' is executed, and "LDB B, (HL+).2" is executed to acquire the flag data FDBn corresponding to the pre-addition distribution value FVBn acquired in the W register 104a into the B register 105a. is executed. As described above, in the first result handling process (FIG. 42), the processes of steps S1205 to S1208 are repeatedly executed until an affirmative determination is made in step S1208. The combination of pre-addition distribution value FVBn and flag data FDBn obtained in W register 104a and B register 105a in the distribution data obtaining process in step S1205 is as follows: combination of FVB1 and FDB1→combination of FVB2 and FDB2→FVB3 and It is updated in the order of the combination of FDB3. The numerical value "1298H" is the distribution value FVB1 before addition to the W register 104a and the B register 105a when the distribution data acquisition process (step S1205) is executed for the first time in the current processing round (game round). and flag data FDB1. By executing the instruction "LD HL, 1298H" in step S1204, the HL register 107 is loaded with "1298H". As already explained, the start address of the second special figure distribution table 64j is "9253H". "1298H" is data calculated by "{(start address of second special figure distribution table 64j)-9000H}×8". Acquisition data designation data set in the HL register 107 is used when an LDB update instruction is executed in the sorting data acquisition process (step S1205).

When the process of step S1203 is performed, or when the process of step S1204 is performed, a sorting data acquisition process is executed (step S1205). As described above, in the distribution data acquisition process, if the second special figure flag is not set to "1", the first special figure distribution table 64h (FIG. 41(b)) is set to 3 One of the pre-addition apportionment values FVA1 to FVA3 is set in the W register 104a, and flag data FDAn corresponding to the pre-addition apportionment value FVAn set in the W register 104a is set. is set in the B register 105a. Also, as described above, in the distribution data acquisition process (step S1205), when the second special figure flag is set to "1", the second special figure distribution table 64j (FIG. 41(c)) One pre-addition apportionment value FVBn out of the three pre-addition apportionment values FVB1 to FVB3 set in the W register 104a is set in the W register 104a, and the pre-addition apportionment value FVBn set in the W register 104a is set in the B register 105a. The details of the sorting data acquisition process will be described later.

After that, while the pre-addition apportionment value FVAn or the pre-addition apportionment value FVBn is stored in the W register 104a, "20" is added to the value of the W register 104a (step S1206). As a result, when any of the first pre-addition apportionment values FVA1 and FVB1 is stored in the W register 104a before addition, the value of the W register 104a is updated to the corresponding first apportionment value. Further, when any of the second pre-addition apportionment values FVA2 and FVB2 is stored in the pre-addition W register 104a, the value of the W register 104a is updated to the corresponding second apportionment value, If any of the third pre-addition apportionment values FVA3 and FVB3 is stored in the pre-addition W register 104a, the value of the W register 104a is updated to the corresponding third apportionment value.

After that, the value of the W register 104a is subtracted from the value of the A register 104b (step S1207). As already explained, numerical information (jackpot type random number) obtained from the jackpot type counter C2 is set in the A register 104b in step S1201, and any distribution value is set in the W register 104a in step S1206. It will be in the set state. Therefore, when the process of step S1207 is executed for the first time in the current process round (game round), the process of subtracting the distribution value from the numerical information obtained from the jackpot type counter C2 is executed in the step S1207. . In addition, when the process of step S1207 is executed for the (m+1)th time (m is 1 or 2) in the current processing round (game round), m pieces of numerical information obtained from the jackpot type counter C2 in the step S1207 A process of subtracting the (m+1)-th distribution value from the numerical information after the distribution value has been subtracted is executed.

After that, it is determined whether or not the value of the A register 104b is less than "0" (step S1208). If the calculation result in step S1207 is "0" or more, the value of the carry flag is set to "0", and if the calculation result is less than "0", the carry flag is set to "1". be done. In step S1208, an affirmative determination is made when "1" is set in the carry flag. If the value of the A register 104b is not less than "0" (step S1208: NO), the process returns to step S1205. Then, the processes of steps S1205 to S1208 are repeatedly executed until an affirmative determination is made in step S1208. As a result, the distribution value is subtracted in the order of the first distribution value → the second distribution value → the third distribution value from the numerical information acquired from the jackpot type counter C2 to the A register 104b in step S1201, The flag data FDAn and FDBn corresponding to the distribution values for which the calculation result is less than "0" can be identified as the winning flag data. In step S1208, in the order of 4R high-probability jackpot result → 8R high-probability jackpot result → 16R high-probability jackpot result, each jackpot result is subject to distribution determination, and the jackpot type counter C2 Acquired from the jackpot type counter C2 swing corresponding to A result of the minute determination is specified.

If an affirmative determination is made in step S1208, the flag data FDAn and FDBn stored in the B register 105a are set in the distribution data area 162 in the work area 121 for specific control (step S1209). In step S1209, when the first flag data FDA1 and FDB1 corresponding to the 4R high probability jackpot result are set in the distribution data area 162, the 4R high probability flag 162a is set to "1" and the 8R high probability jackpot result is set. When the second flag data FDA2 and FDB2 corresponding to the result are set in the distribution data area 162, the 8R high accuracy flag 162b is set to "1". Further, when the third flag data FDA3 and FDB3 corresponding to the 16R high probability big hit result are set in the distribution data area 162, the 16R high probability flag 162c is set to "1". As a result, the main CPU 63 can grasp the result of the allocation determination.

Next, the sorting data acquisition process executed in step S1205 of the first result handling process (FIG. 42) will be described. Below, the case where the data acquisition process for distribution is performed is mentioned as an example using the distribution table 64h for 1st special figures, and the case where the data acquisition process for distribution is performed is demonstrated.

FIG. 43(a) is an explanatory diagram for explaining the program content of the distribution data acquisition process. FIG. 43(b) is an explanatory diagram for explaining how the first pre-addition apportionment value FVA1 is set in the W register 104a, and FIG. 43(c) shows the first flag data FDA1 is an explanatory diagram for explaining how is set.

As shown in FIG. 43(a), "1901" to "1903" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 43(a), the command "LDB W, (HL+).4" is set at the line number "1901". "LDB" is an LDB update command by the LDB update execution circuit 161, "W" is the content specifying the W register 104a as the "transfer destination", and "(HL+)" is the 2 data stored in the HL register 107. It specifies byte data as acquisition data designation data and instructs to update the acquisition data designation data stored in the HL register 107 after loading the data. 4” is set.

44(a) to 44(e) are the start address of the first special figure distribution table 64h, acquisition data designation data in the LDB update command ("LDB W, (HL+).4"), acquisition start address, FIG. 10 is an explanatory diagram for explaining an acquisition start bit and acquisition data designation data after update; As already described, numerical information "1280H" is set in the HL register 107 in step S1203 of the first result handling process (FIG. 42). As shown in FIG. 44B, "1280H" is acquired data designation data when the LDB instruction "LDB W, (HL+).4" is executed for the first time. As already explained, the start address of the first special figure distribution table 64h is "9250H" (see FIG. 44(a)). "1280H" is numerical information calculated by the formula "{(start address of first special figure distribution table 64h)-9000H}×8". As shown in FIG. 44(b), the 3rd to 14th bits in the acquired data designation data (“1280H”) contain “9250H” (the start address of the first special figure distribution table 64h) ( The data of the 0th to 11th bits in a)) are set.

As already explained, the acquisition start address is the reference address ("9000H") of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquisition data designation data by "8" ("1000B"). ) is added. When an LDB update instruction is executed with "1280H" stored in the HL register 107 as acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1280H" by "8". " is calculated by adding "9250H". As shown in FIG. 44(c), the 0th to 11th bit data at the acquisition start address is the 3rd to 14th bit data of the acquisition data designation data (the start of the first special figure distribution table 64h 0th to 11th bit data in the address), and the 12th to 15th bit data in the acquisition start address are the 12th to 15th bit data in the reference address of the data table. The acquisition start address "9250H" is the start address of the first special figure distribution table 64h.

As already explained, the acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00000111H". When an LDB update instruction is executed with "1280H" stored in the HL register 107 as acquisition data designation data, the acquisition start bit is the lower 1 byte ("10000000B") and "00000111H" of the acquisition data designation data. and "00000000B" ("0"). As shown in FIG. 44(d), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the data of the lower 3 bits (0th to 2nd bits) in the acquisition data designation data. , the data of the upper 5 bits (3rd to 7th bits) at the acquisition start bit is "0".

In the LDB update instruction "LDB W, (HL+).4", a numerical value "4" is set as acquisition bit specification data, so the number of acquisition bits is obtained by adding "1" to "4". "5" is obtained. When the LDB update instruction "LDB W, (HL+).4" is executed while "1280H" is stored in the HL register 107, as shown in FIG. In the minute table 64h, data for the number of acquisition bits (5 bits) set after the acquisition start bit (0th bit) of the area corresponding to the acquisition start address "9250H" (pre-addition distribution The value FVA1) is loaded into the 0th to 4th bits (lower 5 bits) of the W register 104a, which is the transfer destination, and the 5th to 7th bits (upper 3 bits) of the W register 104a are "0". masked. As a result, the determination value HV1 can be set in the W register 104a.

As described above, the number of acquired bits in the LDB update instruction "LDB W, (HL+).4" is "5". Therefore, in the LDB update instruction, after 5-bit data is loaded into the 0th to 4th bits of the W register 104a, the value of the HL register 107 ("1280H") is changed to the acquired bit number ("5"). After the addition, the value of the HL register 107 is updated to "1285H" as shown in FIG. 44(e).

"1285H" is numerical information in which the acquisition start address is "9250H" and the acquired bit is the fifth bit when the next LDB update instruction is executed with the acquired data specifying data "1285H". . In this way, when the LDB update instruction is executed and the acquisition data designation data stored in the HL register 107 is updated, the number of acquired bits in the LDB update instruction is executed next to the LDB update instruction. The data acquisition start position is shifted in the LDB update instruction.

In this way, by setting the pre-addition distribution value FVA1 obtained from the first special figure distribution table 64h using the LDB update command to the W register 104a and updating the obtained data designation data, 3rd to 15th bit data in the 2-byte acquisition data designation data and the acquisition start address corresponding to the reference address of the data table set in the TP register 111; A process of specifying the acquisition start bit corresponding to the second bit (lower 3 bits), and the pre-addition distribution value FVA1 acquired from the first special figure distribution table 64h is converted to the 0th to 4th bits of the W register 104a. (lower 5 bits), masking the 5th to 7th bits (higher 3 bits) of the W register 104a with "0", and adding the number of bits acquired this time to the value of the HL register 107 and updating the acquisition data designation data can be executed with one command. These processes are executed by the LDB update execution circuit 161 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

The command "LDB B, (HL+).2" is set at the line number "1902". "LDB" is an LDB update command by the LDB update execution circuit 161, "B" is the contents specifying the B register 105a as the "transfer destination", and "(HL+)" is the 2 data stored in the HL register 107. This is the contents of specifying byte data as acquisition data designation data and instructing to update the acquisition data designation data stored in the HL register 107 after data transfer. ” is the content to set.

45(a) to 45(c) show the acquisition data designation data, the acquisition start address, the acquisition start bit, and the updated acquisition data designation data in the LDB instruction (“LDB B, (HL+).2”). It is an explanatory view for explaining. As already explained, the acquisition start address is the reference address ("9000H") of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquisition data designation data by "8" ("1000B"). ) is added. When the LDB update instruction is executed with "1285H" stored in the HL register 107 as the acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1285H" by "8". " is calculated by adding "9250H". As shown in FIG. 45(a), the 0th to 11th bit data at the acquisition start address are the 3rd to 14th bit data of the acquisition data designation data, and the 12th to 12th bit data at the acquisition start address. The 15th bit data is the 12th to 15th bit data in the reference address of the data table. As described above, the acquisition start address "9250H" is the start address of the first special figure distribution table 64h.

As already explained, the acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00000111H". When an LDB update instruction is executed with "1285H" stored in the HL register 107 as acquisition data designation data, the acquisition start bit is the lower 1 byte ("10000101B") and "00000111H" of the acquisition data designation data. and "00000101B" ("5"). As shown in FIG. 45(b), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the data of the lower 3 bits (0th to 2nd bits) in the acquisition data designation data. , the data of the upper 5 bits (3rd to 7th bits) at the acquisition start bit is "0".

In the LDB update instruction "LDB B, (HL+).2", a numerical value "2" is set as the acquisition bit designation data, so the number of acquisition bits is obtained by adding "1" to "2". "3" is obtained. When the LDB update instruction "LDB B, (HL+).2" is executed while "1285H" is stored in the HL register 107, as shown in FIG. In the minute table 64h, data (flag data FDA1) for the number of acquisition bits (3 bits) set after the acquisition start bit (5th bit) of the area corresponding to the acquisition start address "9250H" is loaded into the 0th to 2nd bits (lower 3 bits) of the destination D register 106a, and the 3rd to 7th bits (upper 5 bits) of the D register 106a are masked with "0". . As a result, the flag data FDA1 corresponding to the pre-addition apportionment value FVA1 stored in the WA register 104 can be set in the D register 106a.

As described above, the number of acquired bits in the LDB update instruction "LDB B, (HL+).2" is "3". Therefore, in the LDB update instruction, after 3-bit data is loaded into the 0th to 2nd bits of the B register 105a, the value of the HL register 107 ("1285H") is changed to the number of acquired bits ("3"). After the addition, the value of the HL register 107 is updated to "1288H" as shown in FIG. 45(c).

"1288H" is numerical information that sets the acquisition start address to "9251H" and sets the acquired bit to the 0th bit when the next LDB update instruction is executed using the acquired data designation data as "1288H". . In this way, when the LDB update instruction is executed and the acquisition data designation data stored in the HL register 107 is updated, the number of acquired bits in the LDB update instruction is executed next to the LDB update instruction. The data acquisition start position is shifted in the LDB update instruction.

By executing the LDB update instruction "LDB W, (HL+).4" and the LDB update instruction "LDB B, (HL+).2", the pre-addition distribution value FVA1 is stored in the W register 104a and the D register 106a. and flag data FDA1 are set. Also, by increasing the value of the HL register 107 by "8" (the sum of "5" and "3"), the LDB update instruction "LDB W, (HL+).4" and "LDB B, (HL+).4" are executed. 2”, the acquisition start address in the LDB update instruction is incremented by “1”.

In this way, by setting the flag data FDA1 acquired from the first special figure distribution table 64h using the LDB update command to the B register 105a and updating the acquisition data designation data, 2 bytes A process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the acquisition data designation data and the reference address of the data table set in the TP register 111; The process of specifying the acquisition start bit corresponding to the bit (lower 3 bits), and the flag data FDA1 acquired from the first special figure distribution table 64h are stored in the 0th to 2nd bits (lower 3 bits) of the B register 105a. , masking the 3rd to 7th bits (upper 5 bits) of the B register 105a with "0", and adding the number of bits to be acquired to the value of the HL register 107 to obtain acquisition data designation data. updating can be executed with one command. These processes are executed by the LDB update execution circuit 161 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

The command "RET" is set at the line number "1903". As already described, the sorting data acquisition process is a subroutine executed in step S1205 of the first result handling process (FIG. 42). Therefore, by executing the instruction "RET", the process proceeds to step S1206 of the first result handling process.

As already described, in the first result handling process (FIG. 42), the processes of steps S1205 to S1208 are repeatedly executed until an affirmative determination is made in step S1208. FIG. 46 shows the number of executions of the LDB update instruction "LDB W, (HL+).4" and the LDB update instruction "LDB B, (HL+).2", and the W register 104a and B register 105a by these LDB update instructions. FIG. 10 is an explanatory diagram for explaining data acquired in . As shown in FIG. 46, in the second row number "1901", "LDB W, (HL+).4" is executed with "1288H" as the acquired data designation data, and the pre-addition distribution value FVA2 is stored in the W register 104a. is set. Then, the value of the HL register 107 is updated to "128DH". Also, in the second line number "1902", "LDB B, (HL+).2" is executed with "128DH" as the acquisition data designation data, and the flag data FD2 corresponding to the pre-addition distribution value FVA2 is stored in the B register. 105a. Then, the value of the HL register 107 is updated to "1290H".

In this way, by using the first special figure distribution table 64h to repeatedly execute the distribution data acquisition process, the addition pre-shake set in the first special figure distribution table 64h Combinations of minute value FVAn and flag data FDAn can be sequentially loaded into W register 104a and B register 105a one by one. In addition, by using the second special figure distribution table 64j to repeatedly execute the distribution data acquisition process (FIG. 43(a)), the first special figure distribution table 64h can be used. As in the case of repeatedly executing the distribution data acquisition process (FIG. 43(a)), the combination of the pre-addition distribution value FVBn and the flag data FDBn set in the second special figure distribution table 64j is One set at a time can be loaded into W register 104a and B register 105a in sequence.

Next, before describing the processing of steps S1210 to S1216 of the first result handling processing (FIG. 42), the manner of setting the variation type number will be described. As already explained, the variation type number is the result of the success or failure determination from the variation pattern table described later, the result of the distribution determination, the result of the reach generation lottery and the number of reservations in the special figure reservation area 115, 116 Stop result data and This is data for acquiring display duration data.

FIG. 47 is an explanatory diagram for explaining the correspondence relationship between the variation type number and the result of the determination, the result of the distribution determination, the result of the reach occurrence lottery, and the number of reservations in the first special figure reservation area 115. FIG. First, the case where the variable display is started triggered by the reservation information of the first special figure reservation area 115 will be described. As shown in FIG. 47, "0" is set to the type number counter in the work area 121 for specific control corresponding to the occurrence of the 4R high-probability jackpot result, and the type number corresponding to the occurrence of the 8R high-probability jackpot result "1" is set to the counter, "2" is set to the type number counter corresponding to the occurrence of the 16R high probability big win result, and "3" is set to the type number counter corresponding to the occurrence of the small win result. be. In addition, if the result of deviation occurs in the success or failure determination and the reach production is not won in the reach generation lottery described later, if the number of reservations in the first special figure reservation area 115 is "0", the type number counter is "4" is set, and if the number of holds is "1", "5" is set to the type number counter, and if the number of holds is "2", "6" is set to the type number counter, and the number of holds is If it is "3", "7" is set in the type number counter. Furthermore, when the result of deviation occurs in the success/failure determination and the reach effect is won in the reach generation lottery, if the number of reservations in the first special figure reservation area 115 is "0", "8" is set to the type number counter. If the number of reservations is "1", the type number counter is set to "9", and if the number of reservations is "2", the type number counter is set to "10", and the number of reservations is "3". If so, "11" is set in the type number counter.

Next, the case where the variable display is started triggered by the pending information of the second special figure pending area 116 will be described. As shown in FIG. 47, "12" is set to the type number counter in the work area 121 for specific control corresponding to the occurrence of the 4R high-probability jackpot result, and the type number corresponding to the occurrence of the 8R high-probability jackpot result "13" is set to the counter, "14" is set to the type number counter corresponding to the occurrence of the 16R high probability big win result, and "15" is set to the type number counter corresponding to the occurrence of the small win result. be. In addition, if the result of deviation occurs in the judgment of success or failure and the reach production is not won in the reach generation lottery described later, if the number of reservations in the first special figure reservation area 115 is "0", the type number counter is "16" is set, and if the number of holds is "1", "17" is set to the type number counter, and if the number of holds is "2", "18" is set to the type number counter, and the number of holds is If it is "3", "19" is set in the type number counter. Furthermore, when the result of deviation occurs in the success/failure determination and the reach effect is won in the reach generation lottery, if the number of reservations in the first special figure reservation area 115 is "0", "20" is set to the type number counter. , if the number of reservations is "1", the type number counter is set to "21", if the number of reservations is "2", the type number counter is set to "22", and the number of reservations is "3" If so, "23" is set in the type number counter.

Returning to the description of the first result correspondence processing (FIG. 42), after performing the processing of step S1209, it is determined whether or not "1" is set to the second special figure flag in the work area 121 for specific control Then (step S1210), when "1" is not set to the second special figure flag (step S1210: NO), "0" is set to the variation type number counter (step S1211). In this way, when a big hit result occurs in the success/failure determination executed triggered by the reservation information of the first special figure reservation area 115, first, "0" is set to the variation type number counter.

On the other hand, when "1" is set to the second special figure flag (step S1210: YES), "12" is set to the variation type number counter (step S1212). In this way, when a big hit result occurs in the success/failure determination executed with the holding information of the second special figure holding area 116 as a trigger, "12" is first set to the variation type number counter.

When the process of step S1211 is performed, or when the process of step S1212 is performed, it is determined whether or not "1" is set in the 8R high probability flag 162b (step S1213), and the 8R high probability flag 162b is determined. is set to "1" (step S1213: YES), the value of the variation type number counter is incremented by 1 (step S1214). As a result, when "1" is not set to the second special figure flag, it is possible to set the fluctuation type number counter to "1" corresponding to the 8R high probability jackpot result, and the second When "1" is set to the 2 special figure flag, it is possible to set "13" corresponding to the 8R high probability big hit result to the variation type number counter.

If a negative determination is made in step S1213, it is determined whether or not "1" is set in the 16R high accuracy flag 162c (step S1215), and "1" is set in the 16R high accuracy flag 162c. If so (step S1215: YES), the value of the variation type number counter is incremented by 2 (step S1216), and the first result handling process ends. By adding 2 to the value of the variation type number counter, if "1" is not set to the second special flag, "2" corresponding to the 16R high probability big hit result is set to the variation type number counter. In addition, when the second special flag is set to "1", the fluctuation type number counter is set to "14" corresponding to the 16R high probability jackpot result. be able to.

When neither the 8R high-precision flag 162b nor the 16R high-precision flag 162c is set to "1" (step S1213: NO, step S1215: NO), the first result corresponding processing is terminated. Thereby, when "1" is not set to the second special figure flag, it is possible to maintain the state in which "0" corresponding to the 4R high probability jackpot result is set to the variation type number counter, When "1" is set to the second special figure flag, it is possible to maintain the state in which "12" corresponding to the 4R high probability jackpot result is set to the variation type number counter.

Next, the second result handling process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The second result correspondence process is executed in step S1010 of the special figure fluctuation start process (FIG. 35). The second result handling process is executed using a program for specific control and data for specific control.

In the second result corresponding process, it is first determined whether or not "1" is set to the small hit flag 158b in the success or failure data area 158 (step S1301), and if "1" is set to the small hit flag 158b In (step S1301: YES), it is determined whether or not "1" is set to the second special figure flag in the work area 121 for specific control (step S1302). If a negative determination is made in step S1302, "3" is set in the variation type number counter (step S1303), and the second result handling process ends. In this way, when a small hit result occurs in the success/failure determination executed triggered by the reservation information of the first special figure reservation area 115, "3" is set to the variation type number counter.

If an affirmative determination is made in step S1302, "15" is set in the variation type number counter (step S1304), and the second result handling process is terminated. In this way, when a small hit result occurs in the success/failure determination executed triggered by the reservation information of the second special figure reservation area 116, "15" is set to the variation type number counter.

If a negative determination is made in step S1301, that is, if the result is out in the right or wrong determination, information for reach generation lottery out of the information stored in the execution area 117 for special figures, that is, reach random number counter C3 (Step S1305), and read out the reach occurrence lottery table from the main ROM 64 (Step S1306). A winning value corresponding to the result of winning the ready-to-win performance and a winning value corresponding to the result of not winning to the ready-to-win performance are set in the ready-to-win generation lottery table so that the probability of winning the ready-to-win performance becomes about 1/10. ing.

After that, it is determined whether or not the reach production is won by comparing the numerical information grasped in step S1305 with the reach generation lottery table read out in step S1306 (step S1307), and when the reach production is won (step If S1307: YES), the reach generation flag provided in the work area 121 for specific control is set to "1" (step S1308). The ready-to-win occurrence flag is a flag that enables the main side CPU 63 to grasp that the ready-to-win effect has been won in the ready-to-win occurrence lottery.

If a negative determination is made in step S1307, or if the processing of step S1308 is performed, it is determined whether or not "1" is set to the second special figure flag in the work area 121 for specific control. (Step S1309), when "1" is not set to the second special figure flag (step S1309: NO), it is determined whether or not "1" is set to the reach occurrence flag (step S1310) . If a negative determination is made in step S1310, "4" is set in the variation type number counter (step S1311). In this way, when the result of deviation occurs in the success/failure determination executed with the holding information of the first special figure holding area 115 as a trigger and the reach production lottery is not won, first to the fluctuation type number counter "4" is set.

If an affirmative determination is made in step S1310, "8" is set in the variation type number counter (step S1312). In this way, when the winning result occurs in the success/failure determination executed with the holding information of the first special figure holding area 115 as a trigger and the reach production is won in the reach generation lottery, first, the variation type number counter "8 ” is set.

If the processing of step S1311 is performed, or if the processing of step S1312 is performed, the number of reservations in the first special figure reservation area 115 is added to the value of the variation type number counter (step S1313), this second Terminate the result handling process. By adding the number of reservations in the first special figure reservation area 115 to the value of the variation type number counter, the result is out and the reach occurs in the right or wrong judgment executed with the reservation information of the first special figure reservation area 115 as a trigger When the ready-to-win production is not won in the lottery, if the number of reservations in the first special figure reservation area 115 is "0", the type number counter is set to "4", and the number of reservations is "1". If so, the type number counter is set to "5", and if the pending number is "2", the type number counter is set to "6", and the pending number is "3". If so, the type number counter is set to "7". In addition, when a result is lost in the success or failure judgment and the reach production is won in the reach generation lottery, if the number of reservations in the first special figure reservation area 115 is "0", "8" is set to the type number counter If the number of reservations is "1", the type number counter is set to "9", and if the number of reservations is "2", the type number counter is set to "10". If the pending number is "3", the type number counter is set to "11".

If an affirmative determination is made in step S1309, it is determined whether or not the reach occurrence flag is set to "1" (step S1314). If a negative determination is made in step S1314, "16" is set in the variation type number counter (step S1315). In this way, when the winning result occurs in the winning judgment executed with the holding information of the second special figure holding area 116 as a trigger and the reach production is not won in the reach generation lottery, first to the fluctuation type number counter "16" is set.

If an affirmative determination is made in step S1314, "20" is set in the variation type number counter (step S1316). In this way, when the winning result occurs in the success/failure determination executed with the holding information of the second special figure holding area 116 as a trigger and the reach production is won in the reach generation lottery, first, the variation type number counter "20 ” is set.

If the processing of step S1315 is performed, or if the processing of step S1316 is performed, the number of reservations in the second special figure reservation area 116 is added to the value of the variation type number counter (step S1317), this second Terminate the result handling process. By adding the number of reservations in the second special figure reservation area 116 to the value of the variation type number counter, the deviation result occurs and the reach occurs in the judgment performed with the reservation information of the second special figure reservation area 116 as a trigger When the ready-to-win production is not won in the lottery, if the number of reservations in the second special figure reservation area 116 is "0", the type number counter is set to "16", and the number of reservations is "1". If so, the type number counter is set to "17", and if the pending number is "2", the type number counter is set to "18", and the pending number is "3". If so, the type number counter is set to "19". In addition, when a result is lost in the success/failure determination and the reach effect is won in the reach generation lottery, if the number of reservations in the second special figure reservation area 116 is "0", "20" is set to the type number counter If the pending number is "1", the type number counter is set to "21", and if the pending number is "2", the type number counter is set to "22". If the pending number is "3", the type number counter is set to "23".

Returning to the explanation of the special figure fluctuation start processing (FIG. 35), when the processing of step S1009 is performed, or when the processing of step S1010 is performed, the start address acquisition processing for variation is executed (step S1011). In the variation start address acquisition process, the start address of the variation pattern table corresponding to the variation type number stored in the variation type number counter is acquired from the variation start table 64r stored in the main ROM 64 to the HL register 107. . The main side ROM 64 stores 24 variation pattern tables corresponding to the result of winning/failure determination, the result of distribution determination, the result of reach generation lottery, and the number of reservations in the first special figure reservation area 115. In the fluctuation pattern table, the result of the determination, the result of the distribution determination, the result of the reach generation lottery, and the stop result data and display duration data of the variable display corresponding to the number of reservations in the special figure reservation areas 115 and 116 are set. It is The start address of the variation pattern table consists of 2 bytes, and the upper 4 bits of the start address are all "9H". In the fluctuation start table 64r, the start address of the fluctuation pattern table corresponding to the result of winning or not judgment based on the fluctuation type number, the result of allocation judgment, the result of the reach generation lottery, and the number of reservations in the special figure reservation areas 115 and 116 As data for obtaining , the lower 12 bits of the start address are set.

FIG. 49 is an explanatory diagram for explaining the data configuration of the fluctuation start table 64r, and FIG. 50(a) is an explanatory diagram for explaining how the start address of the fluctuation pattern table is obtained.

As shown in FIG. 49, the fluctuation start table 64r is stored in the main ROM 64 in the address range of "9135H" to "9158H". In the fluctuation start table 64r, the lower 12 bits of the start addresses SB0 to SB23 of the fluctuation pattern table corresponding to the fluctuation type numbers 0 to 23 are set. The variable start table 64r has a data configuration in which the lower 12 bits of two start addresses SBn are set in areas corresponding to three consecutive addresses. For example, the lower 12 bits of the start address SB0 and the lower 12 bits of the start address SB1 are set in a total 3-byte area corresponding to "9135H" to "9137H", and the lower 12 bits of the start address SB2 and the start address The lower 12 bits of SB3 are set in a 3-byte area corresponding to "9138H" to "913AH".

In the variable start table 64r, the lower 12 bits of the 24 start addresses SB0 to SB23 are set in a storage area of 36 bytes in total. On the other hand, if the data structure is such that the whole (2 bytes) of one start address SBn (n is an integer from 0 to 23) is stored in an area corresponding to two consecutive addresses, 24 start addresses are stored. A storage area of 48 bytes is required in the main ROM 64 in order to store the fluctuation start table 64r in which SB0 to SB23 are set. In this way, the data capacity of the fluctuation start table 64r in the main ROM 64 is reduced by setting the data structure in which the lower 12 bits of the two start addresses SBn are set in areas corresponding to three consecutive addresses. be able to.

In the variation start address acquisition process in step S1011 of the special figure variation start process (FIG. 35), as shown in FIG. The lower 12 bits of the start address SBn of the corresponding variation pattern table are obtained. For example, when the variation type number is "0", "5CFH" which is the lower 12 bits of the start address SB0 is acquired, and when the variation type number is "1", the lower 12 bits of the start address SB1 are acquired. Bits "5D9H" are obtained.

Next, the program contents of the variation start address acquisition process executed in step S1011 of the special figure variation start process (FIG. 35) will be described with reference to the explanatory diagram of FIG. 50(b). As shown in FIG. 50(b), "2001" to "2005" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LD W, (HSBCNT)" is set at the line number "2001". "LD" is the LD instruction, and "W" is the content specifying the W register 104a as the transfer destination. "HSBCNT" is the address of the variable type number counter in the work area 121 for specific control, and "(HSBCNT)" is the contents of loading the data stored in the variable type number counter to the "transfer destination". As already explained, the variation type number counter stores any numerical data from 0 to 23. By executing "LD W, (HSBCNT)", the data of the fluctuation type number counter is loaded into the "transfer destination" W register 104a.

The command "LD B, 0CH" is set at the line number "2002". "LD" is the LD instruction, "B" is the content specifying the B register 105a as the transfer destination, and "0CH" is the content specifying numerical data "0CH" ("12") as the "transfer source". is. "0CH" is the number of bits (the number of bits acquired) of the address data acquired from the fluctuation start table 64r (FIG. 49) in the address acquisition execution process (FIG. 33(e)) called at line number "2004" to be described later. be. By executing "LD B, 0CH", the number of bits ("12") of the address data acquired from the change start table 64r is set in the "transfer destination" B register 105a.

The command "LD HL, TBL_HDK_B" is set in the line number "2003". "LD" is the LD instruction, and "HL" is the content specifying the HL register 107 as the transfer destination. "TBL_HDK_B" is 2-byte numerical data for setting the acquisition start address to the start address of the fluctuation start table 64r, specifically "09A8H". By executing “LD HL, TBL_HDK_B”, “09A8H” is loaded into the “transfer destination” HL register 107 .

“TBL_HDK_B” is calculated by the formula “{(start address of fluctuation start table 64r)−9000H}×8”. The 3rd to 14th bits of "TBL_HDK_B" are set with the data of the 0th to 11th bits of the start address "9135H". As already explained, in the LDB instruction, the data of the 3rd to 14th bits in the acquisition data designation data are set to the 0th to 11th bits of the acquisition start address, and are set to the 12th to 15th bits of the acquisition start address. The data of the 12th to 15th bits at the reference address (“9000H”) of the data table are set. By setting "TBL_HDK_B" calculated by the formula "{(start address of the fluctuation start table 64r) - 9000H} x 8" as the acquisition data designation data, the start address of the fluctuation start table 64r is set to the acquisition start address. can be

In the address acquisition execution process (FIG. 33(e)) called at line number "2004", if the value of the fluctuation type number counter is "0", "09A8H" stored in the HL register 107 is specified as acquisition data. used as data. On the other hand, if the value of the variation type number counter is "1" or more, the numerical information stored in the HL register 107 is changed to the numerical information corresponding to the value of the variation type number counter before the LDB instruction is executed. Be changed.

The command "CALLS LDBADGET" is set at the line number "2004". "LDBADGET" is the address acquisition execution process already described with reference to FIG. 33(e). The instruction "CALLS LDBADGET" is an instruction for calling a subroutine called address acquisition execution processing. Although the details will be described later, the start address (one of SB0 to SB23) corresponding to the value of the variation type number counter is set in the HL register 107 by executing the address acquisition execution process at the line number “2004”. be. When the subroutine of the address acquisition execution process is completed, the process proceeds to the line number "2005".

A command "RET" is set at the line number "2005". As already explained, the variation start address acquisition process is a subroutine executed in step S1011 of the special figure variation start process (FIG. 35). Therefore, by executing the command "RET", the process proceeds to step S1012 of the special figure fluctuation start process (FIG. 35).

Next, refer to FIG. 33(e) again for the case where the address acquisition execution process (FIG. 33(e)) is executed at line number "2004" of the variable start address acquisition process (FIG. 50(b)). while explaining.

As already explained, "LDBADGET" is set in line number "1701", but since this is not an instruction, line number "1701" does not execute any instruction and proceeds to line number "1702". .

As already explained, in the change start address acquisition process (FIG. 50(b)), "0CH" ("12") designating the number of bits (acquisition bit number) to be acquired from the change start table 64r is stored in the B register 105a. is set. Therefore, "0CH" is set in the "transfer destination" A register 104b by executing "LD A, B" at the line number "1702".

As already explained, in the variation start address acquisition process (FIG. 50(b)), the W register 104a is set with the value of the variation type number counter (any integer from 0 to 23). Further, as described above, the A register 104b stores "0CH", which is the number of acquired bits. Therefore, when "MUL W, A" is executed at line number "1703", the WA register 104 stores the calculation result of "(variation type number counter value) x 0CH". As already explained, at the line number "2003" of the variation start address acquisition process (Fig. 50(b)), the HL register 107 stores the acquired data designation data (" 09A8H") is stored. For the data of the calculation result of "(value of variation type number counter) x (number of bits to be acquired)", the acquisition data designation data stored in the HL register 107 is changed to data corresponding to the value of the variation type number counter. used for

As described above, in the line number "1603" of the variation start address acquisition process (FIG. 50(b)), the HL register 107 stores acquisition data designation data ("09A8H") corresponding to the value "0" in the variation type number counter. ”) is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(the value of the variation type number counter) x (the number of acquired bits)". By adding the data of the calculation result of “(value of variation type number counter)×(number of bits acquired)” stored in WA register 104 to the acquired data designation data stored in HL register 107, Acquisition data designation data corresponding to the value of the variation type number counter can be stored in the HL register 107 .

As already explained, "0CH" ("12") designating the number of bits to be obtained is set in the B register 105a in the variable start address obtaining process (FIG. 50(b)). Therefore, "0CH" is set in the "transfer destination" A register 104b by executing "LD A, B" at line number "1705". As already explained, "0CH" stored in the B register 105a is also used for calculation of "(value of variation type number counter) x (number of acquired bits)". In this way, "0CH" stored in the B register 105a in advance is used for the calculation of "(value of the variation type number counter) x (number of bits acquired)" and specifies the number of bits acquired in the LDB instruction. is used to set the data for the A register 104b.

As described above, the A register 104b stores "0CH", which is the number of acquired bits. Therefore, "0BH" is stored in the A register 104b by executing "DEC A" at line number "1706". "0BH" is a value obtained by subtracting "1" from "12", which is the number of bits of data acquired from the fluctuation start table 64r.

As already explained, when the LDB instruction "LDB HL, (HL).A" is executed, the LDB execution circuit 157 performs an operation to add 1 to the value of the A register 104b, and the value after the addition of 1 is is used as data for the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b at the line number "1706", the number of bits of data acquired from the special special electric address table 64q in the LDB instruction can be set to "12". .

As already explained, the command "LDB HL, (HL).A" is set at the line number "1707". "LDB" is a transfer instruction called the already explained LDB instruction, "HL" is the content specifying the HL register 107 as the "transfer destination", and "(HL)" is the two bytes stored in the HL register 107. data is designated as acquisition data designation data, and "A" designates 1-byte data stored in the A register 104b as acquisition bit number designation data. As already explained, the HL register 107 is in a state where the acquisition data designation data corresponding to the value of the variation type number counter is stored, and the A register 104b is in a state where the acquisition bit number (“0CH”) is changed to “1”. , and "0BH" is stored. Also, the TP register 111 is in a state where "9000H", which is the reference address of the data table, is stored. In this state, by executing the instruction "LDB HL, (HL).A" at the line number "1707", the 0th to 11th bits of the HL register 107, which is the transfer destination, have a variation type number counter The lower 12-bit data in the start addresses SB0 to SB23 corresponding to the value of . Specifically, as shown in FIG. 50(a), when the value of the variation type number counter is "0", the acquisition start address is "9135H" and the acquisition start bit is "0". The 0-11th bits of the HL register 107 are loaded with "05CFH", which is the lower 12 bits of the start address SB0. When the value of the variation type number counter is "1", the acquisition start address is "9136H" and the acquisition start bit is "4". The lower 12 bits of SB1 are loaded with "05D9H". Furthermore, when the value of the variation type number counter is "2", the acquisition start address becomes "9138H", the acquisition start bit becomes "0", and the 0th to 11th bits of the HL register 107 start. The lower 12 bits of address SB2 are loaded with "05E1H". In this way, every time the value of the fluctuation type counter increases by 1, the position at which data acquisition is started is shifted by 12 bits in the fluctuation start table 64r (FIG. 49).

By using the LDB instruction to load the lower 12 bits of the start address SB0 to SB23 obtained from the fluctuation start table 64r into the 0th to 11th bits of the HL register 107, 2 bytes of obtained data designation data can be obtained. and the acquisition start address corresponding to the data of the 3rd to 15th bits and the reference address of the data table set in the TP register 111; ), a process of loading the lower 12 bits of the start address SBn obtained from the fluctuation start table 64r into the lower 12 bits of the HL register 107, and the upper 4 bits of the HL register 107. A process of masking bits with "0" can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

As already explained, the command "ADD HL, 9000H" is set at the line number "1708". By executing “ADD HL, 9000H”, “9000H”, which is the reference address of the data table, is added to the value of the HL register 107 . By executing "ADD HL, 9000H" at line number "1708", the entire start address (one of the start addresses SB0 to SB23) corresponding to the value of the variation type number counter is set in the HL register 107. can be in a state of Specifically, the entire start address SBn is set in the HL register 107 when the value of the variation type number counter is “n” (n is any integer from 0 to 23).

As already explained, the command "RET" is set at the line number "1709". The address acquisition execution process is a subroutine executed at line number "2004" of the variable start address acquisition process (FIG. 50(b)). Therefore, execution of the command "RET" advances to the line number "2005" of the variable start address acquisition process.

Thus, by using the LDB instruction, the low-order 12 bits of the start addresses SB0 to SB23 can be obtained from the variable start table 64r. Further, after executing the LDB instruction, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SB0 to SB23 to the lower 12 bits, the entire start addresses SB0 to SB23 can be obtained. can. Therefore, the address data to be set in the fluctuation start table 64r can be only the lower 12 bits of the start addresses SB0 to SB23. As a result, the data capacity of the fluctuation start table 64r in the main ROM 64 can be reduced compared to the configuration in which the entire 2-byte start addresses SB0 to SB23 are set in the fluctuation start table 64r.

Returning to the description of the special figure fluctuation start process (FIG. 35), after executing the fluctuation start address acquisition process in step S1011, the fluctuation information setting process is executed (step S1012). In the variation information setting process, the variation pattern table is specified based on the start address SBn (n is any of 0 to 23) acquired in the HL register 107 in step S1011, and the specified variation pattern table is used to Set stop result data and display duration data for the current game round.

Here, the data structure of the fluctuation pattern table will be described by taking the fluctuation pattern table corresponding to the fluctuation type number of "0" as an example. FIG. 51(a) is an explanatory diagram for explaining the data configuration of the variation pattern table 64t corresponding to the variation type number of "0".

As shown in FIG. 51( a ), the variation pattern table 64 t is set to addresses “95CFH” to “95D8H” in the main ROM 64 . In "95CFH", which is the top address of the variation pattern table 64t, stop result data corresponding to the form of the pattern to be stopped and displayed on the first special figure display portion 37a is set. In addition, although not shown, it is stopped and displayed on the first special figure display unit 37a or the second special figure display unit 37b also at the top address of the variation pattern table corresponding to the variation type number of "1" to "23" Stop result data corresponding to the mode of the pattern is set. The stop result data is 1-byte data. The kind of the pattern mode stopped and displayed on the first special figure display portion 37a or the second special figure display portion 37b is set to be different for each kind of the result of the success/failure determination and the result of the distribution determination.

As shown in FIG. 51(a), three display duration data HK1 to HK3 and three judgment values HVB1 to HVB1 to HK3 corresponding to the display duration data HK1 to HK3 are stored at addresses "95D0H" to "95D8H". HVB3 is set. Specifically, the determination value HVB1 corresponding to the display duration data HK1 is set at the address "95D0H", and the display duration data is set at the addresses "95D1H" to "95D2H" following "95D0H". HK1 is set. Further, the determination value HVB2 corresponding to the display duration data HK2 is set at the address "95D3H", and the display duration data HK2 is set at the addresses "95D4H" to "95D5H" following "95D3H". It is Furthermore, the determination value HVB3 corresponding to the display duration data HK3 is set at the address "95D6H", and the display duration data HK3 is set at the addresses "95D7H" to "95D8H" following "95D6H". is set.

The judgment values HVB1 to HVB3 are 1-byte data, and the display duration data HK1 to HK3 are 2-byte data. The judgment values HVB1 to HVB3 are used for a display duration lottery for selecting one display duration data from the three display duration data HK1 to HK3. The display continuation time data HK1 is "1000", and when the display continuation time data HK1 is won, the display continuation time is 4 seconds. The display continuation time data HK2 is "1500", and when the display continuation time data HK2 is won, the display continuation time is 6 seconds. The display continuation time data HK3 is "2000", and when the display continuation time data HK3 is won, the display continuation time is 8 seconds.

In the display duration lottery, 1-byte numerical information (one of "0" to "255") obtained from a random number generator (counter circuit) provided in the main MPU 62 is used. The determination value HVB1 and the determination value HVB2 are "102", and the determination value HVB3 is "51". In the fluctuation pattern table 64t, the probability of winning the display duration data HK1 and the probability of winning the display duration data HK2 are 2/5, and the probability of winning the display duration data HK3 is 1/5.

FIG. 51(b) is an explanatory diagram for explaining the configuration of areas for storing stop result data and display duration data HK1 to HK3 in the work area 121 for specific control. As shown in FIG. 51(b), in the specific control work area 121, the stop result counter 141 is provided at the address "0031H", and the display continuation counter 141 is provided at the addresses "0032H" to "0033H". A time counter 142 is provided. The stop result counter 141 is a counter that enables the main side CPU 63 to grasp the stop result data in the current game round. The stop result counter 141 consists of 1 byte. The display continuation time counter 142 is a counter that enables the main side CPU 63 to grasp the display continuation time in the current game round. The display duration counter 142 consists of 2 bytes.

As already explained, the main ROM 64 stores 23 variation pattern tables corresponding to variation type numbers of "1" to "23" in addition to the variation pattern table 64t corresponding to the variation type number of "0". It is Two to four combinations of display continuation time and determination value are set in the variation pattern table corresponding to variation type numbers "1" to "23". The intervals of the start addresses in the 24 variation pattern tables stored in the main ROM 64 are irregular. Therefore, the start address of the variation pattern table corresponding to the variation type number cannot be calculated based only on the variation type number. In the configuration for acquiring the start address of the variation pattern table corresponding to the variation type number using the variation start table 64r, only the lower 12 bits are set in the variation start table 64r instead of the entire 2-byte start address. As a result, the data capacity of the fluctuation start table 64r is reduced.

Next, the variation information setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. Variation information setting processing is executed in step S1012 of the special figure variation start processing (FIG. 35). The variation information setting process is executed using a program for specific control and data for specific control.

In the variable information setting process, first, a command "LD (0031H), (HL+)" is executed (step S1401). "LD" is an LD update command by the LD update execution circuit 151, "0031H" is the content specifying the stop result counter 141 in the work area 121 for specific control as the transfer destination, and "(HL+)" is the transfer source. to specify the stop result data stored in the area corresponding to the address stored in the HL register 107, and after loading the stop result data, add 1 to the value of the HL register 107 and add 1 to the HL register This is the contents of an instruction to update the address stored in 107 . By executing "LD (0031H), (HL+)", the stop result data ("3") corresponding to the address data ("95CFH") stored in the HL register 107 is loaded into the stop result counter 141. be done. As a result, the main side CPU 63 can grasp the stop result data in the current game round. After loading the stop result data, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "95D0H". As a result, the determination value HVB1 can be grasped based on the address stored in the HL register 107. FIG.

In this way, by using the LD update instruction, the process of loading the stop result data set at the head address of the fluctuation pattern table 64t into the stop result counter 141, and the HL register 107 after loading the stop result data A process of adding 1 to the value and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

A variation pattern table is specified based on the start address SBn acquired in the HL register 107 in the variation start address acquisition process (step S1011 of the special figure variation start process (FIG. 35)), and based on the specified variation pattern table With the configuration for acquiring the stop result data, the stop result data corresponding to the result of the success/failure determination and the result of the distribution determination can be set in the stop result counter 141 .

In addition to the fluctuation pattern table, if a stop result table for acquiring stop result data corresponding to the current pass/fail judgment result and distribution judgment result is stored in the main side ROM 64, the start address of the stop result table In addition, it becomes necessary to specify the area corresponding to the current pass/fail determination result and distribution determination result in the stop result table. On the other hand, a variation pattern table is specified based on the start address SBn acquired in the HL register 107 in the variation start address acquisition process (step S1011, FIG. 50(b)), and the specified variation pattern table is used. The configuration for acquiring the stop result data and the display duration data can simplify the configuration for acquiring the stop result data and the display duration data.

After executing the command "LD (0031H), (HL+)" in step S1401, 1-byte lottery numerical information is acquired from the random number generator (counter circuit) provided in the main MPU 62, The acquired numerical information is stored in the variable random number counter provided in the specific control work area 121 (step S1402). The variable random number counter is a counter in which lottery numerical information used for the lottery of display duration data is set. The variable random number counter is a 1-byte counter provided in the storage area corresponding to the address "0105H". Numerical information from "0" to "255" is stored in the variable random number counter.

As already explained, storage areas such as the jackpot type counter C2 and the jackpot type maximum value counter CN2, which appear frequently in the program in order to execute specific control processing, are stored in the characteristic control work area 121. is set to the address range (“0000H” to “00FFH”) that is the target of the LDY instruction (the first LDY instruction and the second LDY instruction described later), while executing specific control processing like a variable random number counter Therefore, storage areas such as counters that appear less frequently in the program are stored in the address range (“0100H” to “02FFH ”). This reduces the data volume of the program for executing the specific control process.

After obtaining the numerical value information for lottery in the variable random number counter in step S1402, the command "LD D, (HL+)" is executed (step S1403). "LD" is an LD update command by the LD update execution circuit 151, "D" is the content specifying the D register 106a as the transfer destination, and "(HL+)" is stored in the HL register 107 as the transfer source. It specifies the determination value HVB1 stored in the area corresponding to the address, and updates the address stored in the HL register 107 by adding 1 to the value of the HL register 107 after loading the stop result data. It is a content that instructs to do. By executing "LD D, (HL+)", the determination value HVB1 ("102") corresponding to the address data ("95D0H") stored in the HL register 107 is loaded into the D register 106a. After the determination value HVB1 is loaded, the value of the HL register 107 is incremented by "1", and the address stored in the HL register 107 is updated to "95D1H". As a result, the display duration data HK1 (“1000”) corresponding to the determination value HVB1 can be grasped based on the address stored in the HL register 107. FIG.

Thus, by using the LD update instruction, the process of loading the determination value HVB1 set in the fluctuation pattern table 64t to the D register 106a, and the value of the HL register 107 after loading the determination value HVB1 is added by 1 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

After that, subtraction processing is executed to subtract the value of the D register 106a from the value of the variable random number counter in the work area 121 for specific control (step S1404). If the subtraction process is executed while the variable random number counter stores the same value as the value of the D register 106a or a value larger than the value of the D register 106a, the carry flag is set to "0". state. On the other hand, if the subtraction process is executed while the variable random number counter stores a value smaller than the value of the D register 106a, the carry flag is set to "1".

Thereafter, it is determined whether or not the carry flag is set to "1" (step S1405), and if the carry flag is not set to "1" (step S1405: NO), the value of the HL register 107 is 2 is added (step S1406). As a result, the value of the HL register 107 becomes "95D3H", and the determination value HVB2 can be grasped based on the address stored in the HL register 107. FIG. If the process of step S1406 has been performed, the process advances to step S1403, and the processes of steps S1403 to S1406 are repeatedly executed until an affirmative determination is made in step S1405.

If an affirmative determination is made in step S1405, the command "LD (0032H), HL" is executed (step S1407), and this fluctuation information setting process ends. In step S1407, "LD" is the LD command, "(0032H)" is the contents of designating the display duration counter 142 in the work area 121 for specific control as the transfer destination, and "HL" is the HL command as the transfer source. This is the content for designating the register 107 . If the carry flag is set to "1" by the subtraction process of subtracting the judgment value HVB1 stored in the D register 106a from the value of the variable random number counter in the work area 121 for specific control, the display continues in step S1407. Display duration data HK1 is set in the time counter 142 . Further, if the carry flag is set to "1" by the subtraction processing of subtracting the determination value HVB2 stored in the D register 106a from the value of the variable random number counter, the display continuation time counter 142 continues to display in step S1407. When the time data HK2 is set and the carry flag is set to "1" by the subtraction processing of subtracting the judgment value HVB3 stored in the D register 106a from the value of the variable random number counter, it is displayed in step S1407. The display duration data HK3 is set in the duration counter 142 .

A variation pattern table is specified based on the start address SBn acquired in the HL register 107 in the variation start address acquisition process (step S1011 of the special figure variation start process (FIG. 35)), and based on the specified variation pattern table Due to the configuration of performing the display duration lottery, the display duration data corresponding to the result of the winning judgment, the result of the distribution judgment, the result of the reach occurrence lottery, and the number of reservations in the first special figure reservation area 115 Display duration time A counter 142 can be set.

Thus, by executing the variable information setting process (FIG. 52), the stop result data in the current game turn is set in the stop result counter 141, and the display duration counter 142 wins the display duration lottery. Display continuation time data HK1 to HK3 are set.

Returning to the explanation of the special figure fluctuation start process (FIG. 35), after executing the fluctuation information setting process in step S1012, the setting process of the special figure special electric timer counter provided in the work area 121 for specific control is executed (step S1013). The special figure special electric timer counter is a timer counter that is updated by subtracting 1 in the timer update process in step S509 of the timer interrupt process (FIG. 26). As an effect for the game cycle, the fluctuation display of the pattern in the first special figure display portion 37a or the second special figure display portion 37b and the fluctuation display of the pattern in the pattern display device 41 are performed, but each of these fluctuation displays is terminated. In this case, the final stop display is performed for the final stop time in a state in which the stop result of the game round is displayed (in the state where a predetermined combination of symbols is waiting on the activated line in the pattern display device 41). In this case, the display duration acquired in step S1012 is the total time for one game, and in the setting processing of the special special electric timer counter in step S1013, the display duration acquired in step S1012 is the final display duration. Set the time information minus the stop time to the special special electric timer counter.

After that, a variation command transmission process is executed (step S1014). In the transmission process, a variation command is transmitted to the sound and light side CPU 93 . The variation command includes identification data indicating that it is a variation command, and display duration data set in the display duration counter 142 in step S1012. The sound and light side CPU 93 grasps the start timing of the variable display of the pattern in the pattern display device 41 based on the variable command, and also grasps the display continuation time of the variable display of the pattern. Details of the variation command transmission process will be described later.

After that, type command transmission processing is executed (step S1015). In the transmission process, the type command is transmitted to the sound and light side CPU 93 . The type command includes identification data indicating that it is a type command, data corresponding to the result of the success/failure determination process, data corresponding to the result of the distribution determination, data indicating whether or not the mode is the high probability mode, and data indicating whether or not it is in the high-frequency support mode. When the sound and light side CPU 93 receives the variation command and the type command, the light emission control of the display light emitting unit 53 is performed in order to perform the variable display of the pattern corresponding to the result of the success/failure determination process, the result of the allocation determination, and the display duration time. , sound output control of the speaker unit 54 and display control of the pattern display device 41 are performed. Further, when receiving the type command, the sound/light side CPU 93 sets data indicating whether the mode is the high-probability mode and whether or not the mode is the high-frequency support mode.

After that, the variable display of the pattern is started in the display part of the execution target side of the game cycle of this time among the first special figure display part 37a and the second special figure display part 37b (step S1016). After that, 1 is added to the special figure special electric counter (step S1017), and this special figure fluctuation start processing is ended. Since the numerical information of the special figure special electric counter when the special figure fluctuation start processing is executed is "0", the numerical information of the special figure special electric counter becomes "1" when the processing of step S1017 is performed .

<Process during special figure fluctuation>
Next, the processing during special figure fluctuation in step S905 of the special figure special electric control processing (FIG. 30) will be described.

In the special figure fluctuation process, during the duration of the game round, it is determined whether it is the timing before the final stop display, and if it is before the final stop display, the first special figure display unit 37a and the second special A process for regularly changing the display mode of the pattern on the execution target side of the current game round in the figure display section 37b is executed. This regular change continues until the timing for starting the final stop display. Also, this regular change is performed in a fixed manner regardless of whether a winning result is obtained and whether a ready-to-win indication occurs.

In addition, instead of waiting in the special figure fluctuation process until the timing of the final stop display, if it is not the time to display the final stop, after executing the process for changing regularly, this special figure Terminate the process during fluctuation. Therefore, after the effect for the game round is started, the special figure fluctuation process is started each time the special figure special electric control process is started until the timing of the final stop display. Further, when it is time to display the final stop, in order to display the final stop result of the current game round on the pattern display device 41, a final stop command is transmitted to the sound and light side CPU 93, and the first stop display is performed. Of the special figure display portion 37a and the second special figure display portion 37b, the display mode of the pattern on the execution target side of the current game round is set to the display mode corresponding to the lottery result of the current game round. Also, the information of the final stop time (0.5 seconds) of the game round is read from the main side ROM 64 and set to the special special electric train timer counter. Then, by adding 1 to the value of the special figure special electric counter, the value of the counter is updated from the value corresponding to the special figure fluctuation process to the one corresponding to the special figure determination process.

<Processing during special figure confirmation>
Next, the processing during special figure determination in step S906 of the special figure special electric control processing (FIG. 30) will be described.

In the special figure confirmation process, it is determined whether or not the final stop time of this game round has passed, and if the final stop time has passed, the result of the success or failure judgment that triggered this game round is a big hit result or a small hit result. If the win/loss determination result that triggered the current game round is neither the big win result nor the small win result, the high probability mode flag in the data mode area in the work area 121 for specific control is set to "1". Determine whether or not The main CPU 63 determines whether or not the high-probability mode flag is set to "1" in the win-or-fail determination process in the case of starting a game round, and determines whether the high-probability table 64g and the low-probability table 64a are used as win-fail tables. .about.64f to be referenced. As already explained, the high-probability mode flag is set to "1" when the opening/closing execution mode ends regardless of the type of the jackpot result that triggered the execution. When the high-probability mode flag is set to "1", 1 is subtracted from the value of the high-probability continuation counter provided in the work area 121 for specific control. The high-probability continuation counter specifies by the main CPU 63 whether or not the number of game rounds completed (specifically, "8") after the end of the open/close execution mode is the number of times that triggers the end of the high-probability mode. It is a counter for When the value of the high-probability continuation counter after subtracting 1 is "0", the high-probability mode flag is cleared to "0" and the high-frequency support mode flag is cleared to "0".

On the other hand, in the special figure confirmation process (step S906), if it is determined that the result of the success or failure determination that triggered the game round this time is a big hit result or a small hit result, it is stored in advance in the main side ROM 64 Read the information of the opening time (for example, 4 seconds), and set the information of the opening time to the special special electric timer counter. After that, an opening command is transmitted to the sound and light side CPU 93 . The opening command is a command for making the sound/light side CPU 93 recognize that it is time to start the effect for the opening/closing execution mode. The opening command also includes information indicating whether the game result that triggered the opening/closing execution mode is one of various big win results and small win results. Therefore, the sound/light side CPU 93 can execute the effect of the opening/closing execution mode in a manner corresponding to the game result that triggered the opening/closing execution mode. After that, by adding 1 to the value of the special figure special electric counter, the value of the special figure special electric counter, which had been stored as "2", is changed to "3", and this special figure fixing process is ended.

<Special electric start processing>
Next, the special electric start processing in step S907 of the special electric electric control processing (FIG. 30) will be described.

In the special electric start process, it is determined whether or not the opening time in the opening and closing execution mode of this time has passed, and if it is determined that the opening time has passed, the execution trigger of the opening and closing execution mode of this time is one of the jackpot results It is determined whether or not. When it is determined that the current opening/closing execution mode execution opportunity is one of the jackpot results, the round counter provided in the work area 121 for specific control displays the number of round games corresponding to the jackpot result of this time. A value (“4”, “8” or “16”) is set, and “10” is set in the winning counter provided in the work area 121 for specific control. The round counter is a counter for specifying the number of remaining round games in the opening/closing execution mode by the main side CPU 63, and the winning counter is the upper limit number of game balls in one round game or one opening/closing number regulation mode. It is a counter for the main side CPU 63 to specify whether or not a prize has been won. After that, reading processing of the opening duration corresponding to the jackpot result is executed.

On the other hand, if it is determined that the execution trigger of the opening and closing execution mode this time is not any big winning result, that is, if the execution trigger of the opening and closing execution mode this time is a small winning result, it is provided in the work area 121 for specific control. "5" is set to the opened/closed counter provided, and "10" is set to the winning counter provided in the work area 121 for specific control. The opening/closing counter is a counter for the main CPU 63 to specify the number of times the special electric prize winning device 32 is opened/closed in the opening/closing execution mode of the opening/closing number regulation mode. After that, reading processing of the opening duration corresponding to the small hit result is executed. The open duration is pre-stored in the main ROM 64, and is specifically 0.05 seconds, which is shorter than the game ball firing cycle (0.6 seconds).

When it is determined that the execution trigger of the current opening/closing execution mode is one of the jackpot results, and when the above-mentioned open duration reading process is executed, or when the execution trigger of the opening/closing execution mode this time is none of the jackpot results. In the case where it is determined that the information on the open duration is read, the information on the read open duration is set in the special figure special electric timer counter, and the special electric winning device 32 is opened for opening Execute the setting process. After that, output the release command. The opening command is a command for making the sound and light side CPU 93 recognize that it is the timing when the special electric prize winning device 32 is opened. Upon receiving the opening command, the sound and light side CPU 93 executes control for switching the effect in the opening/closing execution mode accordingly. After that, by adding 1 to the special-pattern electric counter, the value of the special-pattern electric counter, which had been stored as "3", is changed to "4", and the special electric start processing is terminated.

<Processing during opening of the special train>
Next, a description will be given of the special electric open processing in step S908 of the special electric electric control processing (FIG. 30).

In the special electric open processing, if the current open/close execution mode is the round number regulation mode, it is determined whether or not the end condition of the round game of 1 is satisfied, and if the end condition is satisfied The special electric prize winning device 32 is closed, and a closing command is transmitted to the sound and light side CPU 93 . The closing command is a command for making the sound and light side CPU 93 recognize that it is time to close the special electric prize winning device 32 . In addition, it is determined whether or not the value of the round counter after subtracting 1 is "0", and if it is not "0", the closing time is set to the special special electric timer counter. The closing time is constant irrespective of the type of game result that triggered the transition to the opening/closing execution mode, and is specifically set to 2 seconds, which is longer than the shooting cycle of the game ball. Also, when the special electric prize winning device 32 is closed, regardless of whether the value of the round counter is "0" or not, 1 is added to the special electric special electric counter. In this case, since the value of the special figure special electric counter when the special electric open processing is executed is "4", it becomes "5" after adding 1.

When the current opening/closing execution mode is the opening/closing number regulation mode, if the opening continuation time of the special electric prize winning device 32 has passed, the special electric prize winning device 32 is put in a closed state, and the closing command is sent to the sound and light side CPU 93. Send to Then, it is determined whether or not the value of the open/close counter after subtracting 1 is "0", and if it is not "0", the closing time is set to the special special electric timer counter. As already described, the closing time is constant regardless of the type of game result that triggered the transition to the opening/closing execution mode. Also, when the open duration time has not elapsed, it is determined whether or not a prize has been awarded to the special electric prize winning device 32, and when a prize has been awarded, the prize counter is decremented by one. Then, when the value of the winning counter after subtracting 1 is "0", the open/close counter is cleared to "0" and the special electric winning device 32 is closed. Also, when the special electric prize winning device 32 is closed, the special electric special electric counter is incremented by 1 regardless of whether or not the value of the open/close counter is "0". In this case, since the value of the special figure special electric counter when the special electric open processing is executed is "4", it becomes "5" after adding 1.

<Treatment during special train closure>
Next, the processing during special electric closing in step S909 of the special electric electric control processing (FIG. 30) will be described.

In the special electric closing process, it is determined whether or not both the round counter and the open/close counter are "0". If either one is not "0", it is determined whether or not the closing time has elapsed. If the closing time has not passed, this special electric closing process is terminated as it is, and if the closing time has passed, the special electric prize winning device 32 is opened, and the opening and closing execution mode of this time is executed. Set the opening duration corresponding to the winning result to the special special electric timer counter. Further, when the special electric prize winning device 32 is set to the open state, an open command is transmitted to the sound and light side CPU 93 . After that, after subtracting 1 from the special figure special electric counter, this special electric closing processing is terminated. In this case, since the value of the special figure special electric counter when the special electric closed processing is executed is "5", it becomes "4" after subtracting 1.

On the other hand, when both the round counter and the open/close counter are "0", an ending command is transmitted to the sound and light side CPU 93. FIG. The ending command is a command for making the sound/light side CPU 93 recognize that it is time to start the ending effect. The ending command also includes information indicating whether the game result that triggered the opening/closing execution mode is one of various big win results and small win results. Therefore, the sound/light side CPU 93 can execute the ending effect in a manner corresponding to the game result that triggered the opening/closing execution mode. Also, the information of the ending time (for example, 6 seconds) stored in advance in the main ROM 64 is read, and the information of the ending time is set to the special special electric train timer counter. Incidentally, the ending time is constant regardless of the type of game result that triggers the transition to the opening/closing execution mode. After that, after adding 1 to the special special electric counter, this special electric closing processing is ended. In this case, since the value of the special figure special electric counter when the special electric closed processing is executed is "5", it becomes "6" after adding 1.

<Special call end processing>
Next, the special electric end processing in step S910 of the special electric electric control processing (FIG. 30) will be described.

In the special call ending process, it is determined whether or not the ending time has passed. When it is determined that the ending time has elapsed, the game state transition processing is executed, the special figure special electric counter is cleared to "0", and the special electric end processing is ended. Here, the game state transition processing will be described.

In the game state transition process, if the result of the success/failure determination that triggered the transition to the opening/closing execution mode that ended this time is a jackpot result, the high probability mode flag of the data area in the work area 121 for specific control and the high frequency support mode "1" is set to the flag, and "8" is set to the high-probability continuation counter in the work area 121 for specific control. As a result, the game state after the opening/closing execution mode is the high-probability mode and becomes the high-frequency support mode, and the game state is continued until eight game rounds are completed.

In the game state transition process, if the winning result that triggered the transition to the opening/closing execution mode that has ended this time is a small winning result, a post-small winning counter provided in the work area 121 for specific control is set to "30". Then, the game state transition processing is terminated. The after-small-hit counter is a counter for the main side CPU 63 to specify whether or not the game times of the post-small-hit reference number of times have already been completed after a small-hit result is obtained. The value of the after-small-hit counter is decremented by 1 each time a game round is finished. Further, when the opening/closing execution mode is shifted, the value of the post-small winning counter is cleared to "0". When the value of the after-small-hit counter is 1 or more, the selection of the display continuation time in the game round is performed in a mode corresponding to the result of the small-hit result.

Next, before describing the display control processing executed in step S514 of the timer interrupt processing (FIG. 26), the pending display data table 64s stored in the main ROM 64 will be described. The pending display data table 64s is a data table for performing display control of the first special figure pending display portion 37c, the second special figure pending display portion 37d and the general figure pending display portion 38b.

FIG. 53(a) is an explanatory diagram for explaining the data configuration of the pending display data table 64s, and FIG. 53(b) is an explanatory diagram for explaining how to acquire pending display data corresponding to the number of pending. , FIG. 53(c) is an explanatory diagram for explaining the data structure of a conventional pending display data table shown for comparison. As shown in FIG. 53(a), the pending display data table 64s is stored in the main ROM 64 in the address range of "9190H" to "9192H". As shown in FIG. 53(b), the pending display data HR0 to HR4 are 1-byte data, and the upper 4 bits of the pending display data HR0 to HR4 are commonly "0000B".

As shown in FIG. 53(a), in the pending display data table 64s, the lower 4 bits of five pending display data HR0 to HR4 corresponding to the pending numbers "0" to "4" are set. Specifically, the lower 4 bits (0th to 3rd bits) of the 1-byte area corresponding to the start address "9190H" of the pending display data table 64s are the lower 4 bits (0th to 3rd bits) of the 0th pending display data HR0. "0000B") are set, and the lower 4 bits ("0001B") of the first reserved display data HR1 are set in the upper 4 bits (4th to 7th bits) of the area. The lower 4 bits ("0011B") of the second pending display data HR2 are set in the lower 4 bits of the 1-byte area corresponding to "9191H" following "9190H", and the upper 4 bits of the area are set to is set with the lower 4 bits (“0111B”) of the third reserved display data HR3. The lower 4 bits ("1111B") of the fourth pending display data HR4 are set in the lower 4 bits of the 1-byte area corresponding to "9192H" following "9191H", and the upper 4 bits of the area are set to is set to "0000B" as unused adjustment data.

Display control processing to be described later (Figure 54) in step S1501 first special figure pending display data acquisition processing, step S1503 second special figure pending display data acquisition processing and step S1505 in normal figure pending display data acquisition processing, the number of pending are loaded into the lower 4 bits (0th to 3rd bits) of the W register 104a, and the lower 4 bits of the pending display data HRn (n is any integer from 0 to 4) corresponding to The upper 4 bits (4th to 7th bits) are masked with "0". As a result, all of the pending display data HR0 to HR4 corresponding to the pending number can be set in the W register 104a.

As shown in FIG. 53(a), the lower 4 bits of the five pending display data HR0 to HR4 in the pending display data table 64s are set in a 3-byte area in the main ROM 64 in total. On the other hand, if all of the 1-byte pending display data HR0-HR4 are stored in the pending display data table 64s, the five pending display data HR0-HR4 are stored as shown in FIG. 53(c). A total of 5 bytes of area is required for setting. In this way, with the data configuration in which only the lower 4 bits of the five pending display data HR0 to HR4 are set in the pending display data table 64s, the pending display data table 64s is stored in the main ROM 64. data capacity has been reduced.

Next, the display control processing executed by the main CPU 63 will be described with reference to the flowchart of FIG. The display control process is executed in step S514 of the timer interrupt process (FIG. 26). The display control process is executed using a program for specific control and data for specific control.

In the display control process, the first special figure pending display data acquisition process is executed (step S1501). In the first special figure reservation display data acquisition process, the number of reservations in the first special figure reservation area 115 is grasped by referring to the first special figure reservation number counter 118 in the work area 121 for specific control. After that, based on the reservation display data table 64s in the main ROM 64, the lower 4 bits of the reservation display data HRn (n is an integer of 0 to 4) corresponding to the grasped number of reservations are transferred to the lower 4 bits of the W register 104a. (0th to 3rd bits) and mask the upper 4 bits (4th to 7th bits) of the W register 104a with "0". Thereby, the whole of the pending display data HRn corresponding to the value of the first special figure pending number counter 118 can be set in the W register 104a. In addition, the detail of the 1st special figure reservation display data acquisition process is mentioned later.

After that, the reservation display data HRn set in the W register 104a in step S1501 is set in the first special figure reservation display area provided in the work area 121 for specific control (step S1502). The first special figure reservation display area is a storage area in which display data for performing display control of the first special figure reservation display section 37c is set. The first special figure reservation display area consists of 1 byte. Reservation display data HRn set in the first special figure reservation display area is the first special figure driver provided in the main control board 61 for performing display control of the first special figure reservation display section 37c in step S1507. output to the circuit.

After that, the second special figure reservation display data acquisition process is executed (step S1503). In the second special figure reservation display data acquisition process, the number of reservations in the second special figure reservation area 116 is grasped by referring to the second special figure reservation number counter 119 in the work area 121 for specific control. After that, based on the pending display data table 64s in the main ROM 64, the lower 4 bits of the pending display data HRn corresponding to the grasped pending number are set to the lower 4 bits (0th to 3rd bits) of the W register 104a. , the upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". Thereby, the whole of the pending display data HRn corresponding to the value of the second special figure pending number counter 119 can be set in the W register 104a. The details of the second special figure pending display data acquisition process will be described later.

After that, the pending display data HRn set in the W register 104a in step S1503 is set in the second special figure pending display area provided in the work area 121 for specific control (step S1504). The second special figure reservation display area is a storage area in which display data for performing display control of the second special figure reservation display section 37d is set. The second special figure reservation display area consists of 1 byte. The suspension display data HRn set in the second special figure suspension display area is the second special figure driver circuit provided in the main control board 61 to control the display of the second special figure suspension display section 37d in step S1507. output to

After that, normal figure reservation display data acquisition processing is executed (step S1505). In the normal pattern reservation display data acquisition process, the normal pattern reservation number counter 127 in the work area 121 for specific control is referred to, and the number of reservations in the normal pattern reservation area 114 is grasped. After that, based on the reservation display data table 64s in the main ROM 64, the lower 4 bits of the reservation display data HRn corresponding to the grasped number of reservations are set to the lower 4 bits (0th to 3rd bits) of the W register 104a. , the upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". Thereby, the whole of the pending display data HRn corresponding to the value of the normal pattern pending number counter 127 can be set in the W register 104a. In addition, the details of the normal map reservation display data acquisition process will be described later.

After that, the suspension display data HRn set in the W register 104a in step S1505 is set in the normal diagram suspension display area provided in the work area 121 for specific control (step S1506). The general pattern reservation display area is a storage area in which display data for performing display control of the general pattern reservation display section 38b is set. The normal map reservation display area consists of 1 byte. The reservation display data HRn set in the normal diagram reservation display area is output to the normal diagram driver circuit provided in the main control board 61 in order to perform display control of the normal diagram reservation display unit 38b in step S1507.

After that, output processing of various display data is executed (step S1507), and the present display control processing ends. In the output processing of various display data in step S1507, the holding display data HRn set in the first special figure holding display area in the work area 121 for specific control is output to the first special figure driver circuit, and the second special The reserved display data HRn stored in the drawing reserved display area is output to the second special drawing driver circuit, and the reserved display data HRn stored in the normal drawing reserved display area is output to the normal drawing driver circuit.

Next, the program content of the 1st special figure display data acquisition process performed in step S1501 of display control processing (FIG. 54) is demonstrated, referring explanatory drawing of Fig.55 (a). As shown in FIG. 55(a), "2101" to "2105" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LD W, (THRYUH1)" is set at the line number "2101". "LD" is the LD instruction, and "W" is the content specifying the W register 104a as the transfer destination. "THRYUH1" is the address of the first special figure pending number counter 118 in the work area 121 for specific control, and "(THRYUH1)" is the data stored in the first special figure pending number counter 118 as the "transfer destination" This is the content to load into the . As already explained, in the first special figure reservation number counter 118, any numerical data of 0 to 4 is stored. By executing "LD W, (THRYUH1)", the data of the first special figure pending number counter 118 is loaded into the "transfer destination" W register 104a.

The command "LD B, 04H" is set at the line number "2102". "LD" is the LD instruction, "B" is the content specifying the B register 105a as the transfer destination, and "04H" is the content specifying numerical data "04H" as the "transfer source". "04H" is the number of bits (acquisition bit number) of the address data acquired from the pending display data table 64s in the pending display data acquisition execution process (FIG. 55(b)) called at line number "2104" to be described later. By executing "LD B, 04H", the number of bits ("4") of the address data acquired from the pending display data table 64s is set in the "transfer destination" B register 105a.

A command "LD HL, TBL_LEDHYU_B" is set at the line number "2103". "LD" is the LD instruction, and "HL" is the content specifying the HL register 107 as the transfer destination. "TBL_LEDHYU_B" is 2-byte numerical data for setting the acquisition start address to the start address ("9190H") of the pending display data table 64s, specifically "0C80H". By executing “LD HL, TBL_LEDHYU_B”, “0C80H” is loaded into the “transfer destination” HL register 107 .

“TBL_LEDHYU_B” is calculated by the formula “{(start address of pending display data table 64s)−9000H}×8”. The data of the 0th to 11th bits of the start address "9190H" are set in the 3rd to 14th bits of "TBL_LEDHYU_B". As already explained, in the LDB instruction, the data of the 3rd to 14th bits in the acquisition data designation data are set to the 0th to 11th bits of the acquisition start address, and are set to the 12th to 15th bits of the acquisition start address. The data of the 12th to 15th bits at the reference address ("9000H") of the data table are set. By setting "TBL_LEDHYU_B" calculated by the formula "{(start address of the pending display data table 64s)-9000H}×8" as the acquisition data designation data, the start address of the pending display data table 64s is obtained as the acquisition start address. can be

In the pending display data acquisition execution process (FIG. 55(b)) called at line number "2104", when the value of the first special figure pending number counter 118 is "0", stored in the HL register 107 " 0C80H" is used as acquisition data designation data. On the other hand, if the value of the first special figure reservation number counter 118 is greater than or equal to "1", the numerical information stored in the HL register 107 is the first special figure reservation number counter 118 before the LDB instruction is executed is changed to numerical information corresponding to the value of

A command "CALLS LDBGET" is set at the line number "2104". "LDBGET" is pending display data acquisition execution processing (FIG. 55(b)), which will be described later. The command "CALLS LDBGET" is a command for calling a subroutine called hold display data acquisition execution processing. Although the details will be described later, by executing the pending display data acquisition execution process at the line number "2104", the pending display data HRn corresponding to the value of the first special figure pending number counter 118 is set in the W register 104a. be. When the subroutine of the pending display data acquisition execution process ends, the process proceeds to the line number "2105".

A command "RET" is set at the line number "2105". As already explained, the first special figure display data acquisition process is a subroutine executed in step S1501 of the display control process (FIG. 54). Therefore, by executing the command "RET", the process proceeds to step S1502 of the display control process (FIG. 54).

Next, the pending display data acquisition execution process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 55(b). FIG. 55(b) is an explanatory diagram for explaining the program contents of the pending display data acquisition execution process. The pending display data acquisition execution process is executed at the line number "2104" of the first special figure pending display data acquisition process (FIG. 55(a)). In addition, the pending display data acquisition execution process includes the line number "2304" of the second special figure pending display data acquisition process (Fig. )) at line number “2404”. First, the case where the pending display data acquisition execution process is executed at the line number "2104" of the first special figure pending display data acquisition process (FIG. 55(a)) will be described.

As shown in FIG. 55(b), "2201" to "2208" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 55(b), "LDBGET" is set to the line number of "2201". This is not an instruction but data referred to when the developer of the pachinko machine 10 checks the program. Therefore, at line number "2201", the process proceeds to line number "2202" without executing any instruction.

The command "LD A, B" is set at the line number "2202". "LD" is the LD instruction, "A" is the content specifying the A register 104b as the transfer destination, and "B" is the content specifying the B register 105a as the transfer source. As already explained, "04H", which is the number of acquisition bits, is set to the B register 105a in the first special figure pending display data acquisition process (FIG. 55(a)). Therefore, by executing "LD A, B", "04H" is set in the "transfer destination" A register 104b.

The command "MUL W, A" is set at the line number "2203". "MUL" is an operation instruction called a MUL instruction, "W" is the content specifying the W register 104a, and "A" is the content specifying the A register 104b. By executing "MUL W, A", an operation of multiplying the value of the W register 104a by the value of the A register 104b is performed and the result of the operation is stored in the WA register 104. FIG. As already explained, in the line number "2103" of the first special figure pending display data acquisition process (FIG. 55(a)), the HL register 107 corresponds to the value "0" in the first special figure pending number counter 118. Acquisition data designation data (“0C80H”) to be acquired is stored. The data of the calculation result of "(the value of the first special figure reservation number counter 118) x (the number of acquired bits)" is the acquisition data designation data stored in the HL register 107 Used to change the data corresponding to the value.

The command "ADD HL, WA" is set at the line number "2204". “ADD” is an arithmetic instruction called an ADD instruction; By executing “ADD HL, WA”, the sum of the value of the HL register 107 and the value of the WA register 104 is stored in the HL register 107 . As described above, in the line number "2103" of the first special figure pending display data acquisition process (FIG. 55(a)), the HL register 107 corresponds to the value "0" in the first special figure pending number counter 118. Obtained data designation data (“0C80H”) is stored. In addition, as described above, the WA register 104 stores the data of the calculation result of "(the value of the first special figure reservation number counter 118) x (the number of acquired bits)". Add the data of the calculation result of "(the value of the first special figure reservation counter 118) x (the number of bits acquired)" stored in the WA register 104 to the acquisition data designation data stored in the HL register 107 By doing so, the acquisition data designation data corresponding to the value of the first special figure pending number counter 118 can be in a state where it is stored in the HL register 107 .

At the line number "2205", the command "LD A, B" is set, like the line number "2202". As already explained, "04H" is set as the number of acquisition bits in the B register 105a in the first special figure pending display data acquisition process (FIG. 55(a)). Therefore, by executing "LD A, B", "04H" is loaded into the "transfer destination" A register 104b. As already explained, "04H" stored in the B register 105a was also used for the calculation of "(the value of the first special figure reservation number counter 118) x (acquisition bit number)". Thus, "04H" stored in the B register 105a in advance is used for the calculation of "(the value of the first special figure reservation number counter 118) x (number of bits acquired)", and the acquired bits in the LDB instruction It is used to set the data for specifying the number in the A register 104b.

The command "DEC A" is set at the line number "2206". "DEC" is a calculation instruction called a DEC instruction, and "A" is the contents of specifying the A register 104b. By executing "DEC A", the value of the A register 104b is decremented by one. As described above, "04H" is stored in the A register 104b. Therefore, "03H" is stored in the A register 104b by executing "DEC A" at line number "2206". "03H" is a value obtained by subtracting "1" from "4", which is the number of bits acquired from the pending display data table 64s.

When the LDB instruction "LDB W, (HL).A" is executed at line number "2207", the LDB execution circuit 157 performs an operation to add 1 to the value of the A register 104b. is used as the acquired bit number data. Therefore, by subtracting 1 from the value of the A register 104b at line number "2206", the number of bits of data acquired from the pending display data table 64s in the LDB instruction can be set to "4".

The command "LDB W, (HL).A" is set at the line number "2207". "LDB" is the LDB instruction by the LDB execution circuit 157, "HL" is the content specifying the HL register 107 as the "transfer destination", and "(HL)" is the 2-byte data stored in the HL register 107. Data is specified as acquisition data specification data, and "A" is content specifying 1-byte data stored in the A register 104b as acquisition bit number specification data. As already explained, the HL register 107 is in a state where the acquired data designation data corresponding to the value of the first special figure pending number counter 118 is stored, and the A register 104b stores the number of acquired bits ("04H") "03H" obtained by subtracting "1" from is stored. Also, the TP register 111 is in a state where "9000H", which is the reference address of the data table, is stored. In this state, by executing the instruction "LDB W, (HL).A" at the line number "2207", the first special figure The lower 4-bit data of the pending display data HRn corresponding to the value of the pending number counter 118 is loaded, and the 4th to 7th bits of the W register 104a are masked with "0".

Specifically, as shown in FIG. 53(b), when the value of the first special figure reservation number counter 118 is "0", the acquisition start address becomes "9190H" and the acquisition start bit is "0 , and the lower 4 bits of the reserved display data HR0 are loaded into the 0th to 3rd bits of the W register 104a. When the value of the first special figure reservation number counter 118 is "1", the acquisition start address becomes "9190H" and the acquisition start bit number becomes "4", and the 0th to 3rd bits of the W register 104a are reserved. The lower 4 bits of display data HR1 are loaded. When the value of the first special figure reservation number counter 118 is "2", the acquisition start address becomes "9191H" and the acquisition start bit becomes "0", and the 0th to 3rd bits of the W register 104a are reserved. The lower 4 bits of display data HR2 are loaded. When the value of the first special figure reservation number counter 118 is "3", the acquisition start address becomes "9191H" and the acquisition start bit number becomes "4", and the 0th to 3rd bits of the W register 104a are reserved. The lower 4 bits of display data HR3 are loaded. When the value of the first special figure reservation number counter 118 is "4", the acquisition start address becomes "9192H" and the acquisition start bit becomes "0", and the 0th to 3rd bits of the W register 104a are reserved. The lower 4 bits of display data HR4 are loaded. Thus, every time the value of the first special figure reservation number counter 118 increases by 1, the acquisition start position of the data in the reservation display data table 64s shifts by 4 bits.

The low 4 bits of the pending display data HRn obtained from the pending display data table 64s using the LDB instruction are loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. 3rd to 15th bit data in the acquisition data designation data and a process of specifying the acquisition start address corresponding to the reference address of the data table set in the TP register 111, and the 0th to 2nd bits of the acquisition designation data (lower 3 bits), a process of loading the lower 4 bits of the pending display data HRn acquired from the pending display data table 64s into the lower 4 bits of the W register 104a, and the W A process of masking the high-order 4 bits of the register 104a with "0" can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

A command "RET" is set at the line number "2208". When the pending display data acquisition execution process is executed at the line number "2104" of the first special figure pending display data acquisition process (FIG. 55(a)), the command "RET" is executed, It will progress to the line number "2105" of the 1st special figure reservation display data acquisition process.

Thus, by using the LDB instruction, the lower 4 bits of the pending display data HRn are acquired from the pending display data table 64s into the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are set to "0". ” to obtain the entire pending display data HRn. Therefore, the reserved display data HRn set in the reserved display data table 64s can be set to only the lower 4 bits of the reserved display data HRn. As a result, the data capacity of the pending display data table 64s in the main ROM 64 can be reduced compared to the configuration in which the entire 1-byte pending display data HRn is set in the pending display data table 64s. In addition, a process of loading the lower 4 bits of the pending display data HRn into the lower 4 bits of the W register 104a and a process of masking the upper 4 bits of the W register 104a with "0" can be executed with one instruction. Therefore, compared to a configuration in which a plurality of instructions are set for executing these processes, the configuration of the program for executing the pending display data acquisition execution process can be simplified, and the program data capacity in the main ROM 64 can be reduced.

Next, it demonstrates, referring the explanatory view of FIG.55(c) about the program content of the 2nd special figure display data acquisition process performed in step S1503 of display control processing (FIG. 54). As shown in FIG. 55(c), "2301" to "2305" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LD W, (THRYUH2)" is set at the line number "2301". "LD" is the LD instruction, and "W" is the content specifying the W register 104a as the transfer destination. "THRYUH2" is the address of the second special figure pending number counter 119 in the work area 121 for specific control, "(THRYUH2)" is the data stored in the second special figure pending number counter 119 as "transfer destination" This is the content to load into the . As already explained, in the second special figure reservation number counter 119, any numerical data of 0 to 4 is stored. By executing "LD W, (THRYUH2)", the data of the second special figure pending number counter 119 is loaded into the "transfer destination" W register 104a.

In the line number "2302", a command "LD B, 04H" is set as in the line number "2102" of the first special figure pending display data acquisition process (FIG. 55(a)). "04H" is the number of bits (acquisition bit number) of the address data acquired from the pending display data table 64s in the pending display data acquisition execution process (FIG. 55(b)) called at line number "2304" to be described later. By executing "LD B, 04H", the number of bits ("4") of the address data acquired from the pending display data table 64s is set in the "transfer destination" B register 105a.

In the line number of "2303", a command "LD HL, TBL_LEDHYU_B" is set in the same manner as the line number "2103" of the first special figure reservation display data acquisition process (FIG. 55(a)). By executing “LD HL, TBL_LEDHYU_B”, “0C80H” is set in the “transfer destination” HL register 107 . "0C80H" is the pending display data HRn corresponding to the value of the second special figure pending number counter 119 from the pending display data table 64s in the pending display data acquisition execution process (FIG. 55(b)) called at the line number "2304" (n is any integer from 0 to 4) is stored in the HL register 107 to obtain the lower 4 bits.

In the line number of "2304", a command "CALLS LDBGET" is set in the same manner as the line number "2104" of the first special figure pending display data acquisition process (FIG. 55(a)). As already explained, the command "CALLS LDBGET" is a command for calling a subroutine called pending display data acquisition execution processing. By executing the pending display data acquisition execution process at the line number "2304", the pending display data HRn corresponding to the value of the second special figure pending number counter 119 is loaded into the W register 104a. In this way, using the subroutine program common to the first special figure pending display data acquisition process (Fig. 55(a)) and the pending display data table 64s, the pending corresponding to the value of the second special figure pending number counter 119 With the configuration for acquiring the display data HRn, the data volume of the program and data for acquiring the reserved display data HRn can be reduced. When the acquisition processing subroutine is completed, the process proceeds to the line number "2305".

A command "RET" is set at the line number "2305". As already explained, the second special figure display data acquisition process is a subroutine executed in step S1503 of the display control process (FIG. 54). Therefore, by executing the command "RET", the process proceeds to step S1504 of the display control process (FIG. 54).

Next, the program contents of the general-purpose map display data acquisition process executed in step S1505 of the display control process (FIG. 54) will be described with reference to the explanatory diagram of FIG. 55(d). As shown in FIG. 55(d), "2401" to "2405" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LD W, (HHRYUH)" is set at the line number "2401". "LD" is the LD instruction, and "W" is the content specifying the W register 104a as the transfer destination. "HHRYUH" is the address of the normal pattern pending number counter 127 in the work area 121 for specific control, and "(HHRYUH)" is the content of loading the data stored in the normal pattern pending number counter 127 to the "transfer destination". is. As already explained, in the general pattern reservation number counter 127, any numerical data of 0 to 4 is stored. By executing "LD W, (THRYUH2)", the data of the normal figure pending number counter 127 is loaded into the "transfer destination" W register 104a.

In the line number of "2402", the line number "2102" of the first special figure pending display data acquisition process (Fig. 55 (a)) and the line of the second special figure pending display data acquisition process (Figure 55 (c)) Similar to the number "2302", the command "LD B, 04H" is set. "04H" is the number of bits (acquisition bit number) of the address data acquired from the pending display data table 64s in the pending display data acquisition execution process (FIG. 55(b)) called at line number "2404" to be described later. By executing "LD B, 04H", the number of bits ("4") of the address data acquired from the pending display data table 64s is set in the "transfer destination" B register 105a.

In the line number of "2403", the line number "2103" of the first special figure pending display data acquisition process (Fig. 55 (a)) and the line of the second special figure pending display data acquisition process (Figure 55 (c)) Similar to the number "2303", the command "LD HL, TBL_LEDHYU_B" is set. By executing “LD HL, TBL_LEDHYU_B”, “0C80H” is loaded into the “transfer destination” HL register 107 . "0C80H" is the pending display data HRn (n is any integer from 0 to 4) is stored in the HL register 107 to obtain the lower 4 bits.

In the line number of "2404", the line number "2104" of the first special figure pending display data acquisition process (Fig. 55 (a)) and the line of the second special figure pending display data acquisition process (Figure 55 (c)) As with the number "2304", the instruction "CALLS LDBGET" is set. As already explained, the command "CALLS LDBGET" is a command for calling a subroutine called pending display data acquisition execution processing. By executing the pending display data acquisition execution process at the line number "2404", the pending display data HRn corresponding to the value of the normal diagram pending number counter 127 is set in the W register 104a. In this way, the first special figure pending display data acquisition process (Fig. 55(a)) and the second special figure pending display data acquisition process (Fig. 55(c)) and the common subroutine program and the pending display data table 64s By using the configuration of acquiring the pending display data HRn corresponding to the value of the normal figure pending number counter 127, it is possible to reduce the data capacity of the program and data for acquiring the pending display data HRn. When the acquisition processing subroutine is completed, the process proceeds to the line number "2405".

A command "RET" is set at the line number "2405". As already explained, the normal map display data acquisition process is a subroutine executed in step S1505 of the display control process (FIG. 54). Therefore, by executing the command "RET", the process proceeds to step S1506 of the display control process (FIG. 54).

<Management processing>
Next, the management processing executed by the main CPU 63 will be described with reference to the flowchart of FIG. 56(a). Management processing is executed in step S518 of timer interrupt processing (FIG. 26). Note that the management process is executed using a program for specific control and data for specific control.

In the management process, first, interrupt prohibition is set to prohibit the occurrence of the timer interrupt process (FIG. 26) (step S1601). As a result, timer interrupt processing (FIG. 26), which is processing corresponding to specific control, is not started by interrupting in the middle of management execution processing (FIG. 57), which is processing corresponding to non-specific control, which will be described later. It becomes possible to do so.

Thereafter, as "PUSH PSW", the information in the flag register of the main CPU 63 is saved in the stack area 123 for specific control by a push instruction (step S1602). As already explained, the flag register includes a zero flag ZF, a carry flag, a P/V flag, a sign flag, a half carry flag, etc., and the information in the flag register changes depending on the execution results of operation instructions, rotate instructions, input/output instructions, and the like. It will be done. By saving the information of the flag register before the program of the subroutine corresponding to the management execution process is started, the information of the flag register in the state before the change after the call of the subroutine or the start of the subroutine can be saved. It becomes possible to save to the stack area 123 for specific control.

After that, the management execution processing is started by reading out the subroutine program corresponding to the management execution processing set in the non-specific control program (step S1603). In this case, information for specifying the return address of the management process after execution of the management execution process is written in the specific control stack area 123 by the push instruction. Then, when the management execution processing is completed, information for specifying the return address is read out by a pop instruction, and the program for management processing indicated by the return address is returned to.

When returning to the management processing program after executing the management execution processing, the information of the flag register saved in the stack area 123 for specific control in step S1602 is transferred to the main CPU 63 as "POP PSW" by the pop instruction. flag register (step S1604). As a result, the information in the flag register of the main CPU 63 is restored to the information at the time when step S1602 was executed. That is, the information in the flag register of the main CPU 63 is restored to the information for executing the specific control.

After that, as "LD IY, 0000H", "0000H" is set as a reference address for specific control to be used when specifying the address of the work area 121 for specific control in the IY register 109 by the LD instruction (step S1605). ). This makes it possible to use the specific control reference address when executing the first LDY instruction in the specific control process.

Thereafter, interrupt permission is set (step S1606) in order to switch from the state in which the occurrence of timer interrupt processing (FIG. 26) is prohibited to the state in which it is permitted, and this management processing ends. By setting interrupt permission, timer interrupt processing can be newly executed.

Next, prior to the description of the management execution process (FIG. 57) executed by the main CPU 63, the manner of setting various buffers 163a to 163e in the work area 122 for non-specific control will be described. FIG. 56(b) is an explanatory diagram for explaining how the various buffers 163a to 163e are set in the work area 122 for non-specific control.

As shown in FIG. 56(b), in the work area 122 for non-specific control, the storage area corresponding to the addresses "0340H" to "0341H" contains the information of the WA register 104 at the start of the processing for non-specific control. A WA buffer 163a is provided for saving the information of the BC register 105 to save the information of the BC register 105 at the start of non-specific control processing in a storage area corresponding to the addresses "0342H" to "0343H". A buffer 163b is provided, and a DE buffer 163c is provided in a storage area corresponding to addresses "0344H" to "0345H" for saving information in the DE register 106 at the start of non-specific control processing. An HL buffer 163d for saving information in the HL register 107 at the start of non-specific control processing is provided in a storage area corresponding to addresses "0346H" to "0347H". An IX buffer 163e for saving information in the IX register 108 at the start of non-specific control processing is provided in the storage area corresponding to the address "0349H". These buffers 163a-163e consist of 2 bytes. When processing for non-specific control is started, the information of the corresponding registers is saved in these buffers. Also, when the processing for non-specific control ends, the information saved in these buffers is returned to the corresponding buffers.

<Second LDY instruction>
Next, before describing the management execution processing (FIG. 57) executed by the main CPU 63, the second LDY instruction included in the management execution processing program will be described.

In the management execution process (FIG. 57) to be described later, the second LDY "LDY WA, (40H)", "LDY BC, (42H)", "LDY DE, (44H)" and "LDY HL, (46H)" contains instructions. As shown in FIG. 9, the main MPU 62 has a second LDY execution circuit 164 . The second LDY execution circuit 164 is a dedicated circuit for executing the second LDY instruction. The main CPU 63 can execute the second LDY instruction as a transfer instruction for transferring data.

The instruction code of the second LDY instruction has a structure of "LDY transfer destination, (transfer source)". In the second LDY instruction, a pair register is set as the "transfer destination". The WA register 104, BC register 105, DE register 106 or HL register 107 are set as the "transfer destination" in the second LDY instruction. In the second LDY instruction, a 1-byte numerical value (for example, "(40H)") is set as "(transfer source)".

In the second LDY instruction, the 2-byte numerical information set in the IY register 109 is added to the 1-byte numerical information set in "(transfer source)" to calculate a 2-byte address. The 2-byte data stored in the area corresponding to the address and the area corresponding to the address obtained by adding 1 to the address in the side RAM 65 are loaded into the pair register set as the "transfer destination". As already described, in the present embodiment, the IY register 109 is set with "0000H" as the specific control reference address at the start of the specific control process, and at the start of the non-specific control process, the non-specific control address is set. "0300H" is set as the reference address for use.

By executing "LDY WA, 40H" with "0300H" set in the IY register 109 in advance, in the same way as when "LD WA, (0340H)" is executed, The area corresponding to “0340H” and “0341H”, that is, the 2-byte data stored in the WA buffer 163 a in the non-specific control work area 122 is loaded into the WA register 104 .

In the machine language of the second LDY instruction (for example, "LDY WA, (40H)"), 1-byte data (40H) is set as data for designating "(transfer source)". On the other hand, 2-byte data (0340H) is set in the machine language of the LD instruction (for example, "LD WA, (0340H)") as data for designating "(transfer source)". The data capacity of the machine language of the second LDY instruction is smaller than the data capacity of the machine language of the LD instruction. Therefore, when "0300H" is stored in the IY register 109, the 2-byte data stored in the non-specific control work area 122 is transferred to the WA register 104, BC register 105, DE register 106 or HL register. 107, the data capacity of the program in the main ROM 64 can be reduced by using the second LDY instruction instead of the LD instruction.

Next, the management execution processing executed by the main CPU 63 will be described with reference to the flowchart of FIG. The management execution process is executed in step S1603 of the management process (FIG. 56(a)). The management execution process is executed by the main CPU 63 using a program for non-specific control and data for non-specific control.

First, as "LD SP, 04AFH", "04AFH", which is the final address of the stack area 124 for non-specific control, is set as a fixed address at the start of non-specific control in the stack pointer provided in the main CPU 63 by the LD instruction. Set (step S1701). A stack pointer is a register in which a write destination of information to each of the stack areas 123 and 124 is set. Address information stored in the stack pointer is updated when information is written to the stack areas 123 and 124 by a push instruction.

Thereafter, as "LD (0340H), WA", the information in the WA register 104 of the main CPU 63 is saved in the WA buffer 163a by the LD instruction (step S1702). Thereafter, as "LD (0342H), BC", the information in the BC register 105 of the main CPU 63 is saved in the BC buffer 163b by the LD instruction (step S1703). Thereafter, as "LD (0344H), DE", the information in the DE register 106 of the main CPU 63 is saved in the DE buffer 163c by the LD instruction (step S1704). Thereafter, as "LD (0346H), HL", the information in the HL register 107 of the main CPU 63 is saved in the HL buffer 163d by the LD instruction (step S1705). Thereafter, as "LD (0348H), IX", the information in the IX register 108 of the main CPU 63 is saved in the IX buffer 163e by the LD instruction (step S1706).

After that, as "LD IY, 0300H", "0300H" is set as a reference address for non-specific control used when specifying the address of the work area 122 for non-specific control in the IY register 109 by the LD instruction ( step S1707). This makes it possible to use the non-specific control reference address when executing the first LDY instruction and the second LDY instruction in the non-specific control process.

As already explained, when the non-specific control process ends, the specific control reference address ("0000H") is set in the IY register 109 in step S1605 of the management process (FIG. 56(a)). . A non-specific control reference address (“0300H”) is set in the IY register 109 at the start of management execution processing (FIG. 57), which is processing for non-specific control, and the IY register 109 is set at the end of the management execution processing (FIG. 57). By returning the information in the register 109 to the specific control reference address (“0000H”), the specific control reference address can be used by the first LDY instruction and the second LDY instruction while the specific control process is being executed. During the execution of management execution processing, which is processing for specific control, a non-specific control reference address can be made available by the first LDY instruction and the second LDY instruction. By switching the data stored in one register, the specific control reference address and the non-specific control reference address can be used. The number of registers reserved for making these reference addresses available can be reduced compared to a configuration that reserves registers in which reference addresses are set.

As already explained, the main CPU 63 has various general purpose registers, auxiliary registers and index registers. In steps S1702 to S1706, each information of the WA register 104, the BC register 105, the DE register 106, the HL register 107 and the IX register 108, which are some of these general-purpose registers, auxiliary registers and index registers, It is saved in the corresponding buffer in the work area 122 for non-specific control.

These WA register 104, BC register 105, DE register 106, HL register 107 and IX register 108 are registers used in check processing (step S1708) which is processing corresponding to non-specific control. By saving the information set in such registers to the non-specific control work area 122 prior to the execution of the check process (step S1708), the information of these registers used for the specific control can be transferred to the non-specific control. can be evacuated before is started. Therefore, even if these registers are overwritten during the non-specific control, the information saved in the work area 122 for non-specific control is returned to these registers when the non-specific control is terminated. can be returned to the state corresponding to the specific control before the non-specific control is executed.

In addition, instead of saving all the information of various general-purpose registers, auxiliary registers, and index registers to the work area 122 for non-specific control, the WA to be used in the check process, which is the process corresponding to the non-specific control By selectively saving the information of the register 104, the BC register 105, the DE register 106, the HL register 107 and the IX register 108 to the work area 122 for non-specific control, the register information in the work area 122 for non-specific control It is possible to suppress the capacity to be secured for evacuating. Therefore, it is possible to save the above register information while securing a large capacity of the non-specific control work area 122 that can be used for the check processing. Of course, among various general-purpose registers, auxiliary registers, and index registers in the main CPU 63, registers other than the WA register 104, BC register 105, DE register 106, HL register 107, IX register 108, and IY register 109 are , the information set before the process corresponding to the non-specific control is started is stored until the process corresponding to the non-specific control is finished and the process corresponding to the specific control is restarted.

In addition, by saving register information in the work area 122 for non-specific control instead of saving it in the stack area 124 for non-specific control, the capacity of the stack area 124 for non-specific control can be reduced accordingly. It becomes possible. Also, when using the stack area 124 for non-specific control, as already explained, information is written in the order in which later information is read out first. Otherwise, all subsequent read order information will be returned to different registers. The probability of occurrence of such an event increases as the amount of information saved in the stack area 124 for non-specific control increases. On the other hand, by saving the register information to the non-specific control work area 122, it is possible to prevent the occurrence of the above event even when there is a large amount of information to be saved. .

Thereafter, check processing is executed (step S1708). When executing the check processing, a subroutine program corresponding to the check processing set in the non-specific control program is executed. Information for specifying the return address of the execution process is written in the non-specific control stack area 124 by the push instruction. Then, when the check process is completed, information for specifying the return address is read by the pop instruction, and the program of the management execution process indicated by the return address is returned to. Details of the check processing will be described later.

After the check processing is executed, Y(r+α) is set in the stack pointer of the main side CPU 63 as a fixed address at the time of returning to the specific control by the load instruction as "LD SP, Y(r+α)" (step S1709). ). The address of Y(r+α) is set as an address between "0403H" and "044FH" in the stack area 123 for specific control.

Immediately before the management execution processing subroutine is executed in step S1603 of the management processing (FIG. 56(a)), the amount of information stored in the stack area 123 for specific control is always constant. The information of the stack pointer (that is, the value of the stack pointer) of the main CPU 63 at the timing is constant. In this case, the information stored in the specific control stack area 123 includes, for example, return address information of the management process (FIG. 56(a)) after the management execution process (FIG. 57) ends, and management Information on the return address of the timer interrupt processing (FIG. 26) after the end of the processing (FIG. 56(a)) can be mentioned. The constant information of the stack pointer is Y(r+α). Therefore, when the check process, which is the process corresponding to the non-specific control, is completed and the process corresponding to the specific control is resumed, Y(r+α), which is the constant information, is set in the stack pointer of the main CPU 63. This makes it possible to restore the information of the stack pointer to the information immediately before the process corresponding to the non-specific control is started. By setting the fixed information in the stack pointer in this way, the information of the stack pointer is restored to the information immediately before the processing corresponding to the non-specific control is started, so that the processing corresponding to the non-specific control It becomes unnecessary to save the information of the stack pointer of the main side CPU 63 corresponding to the specific control to the main side RAM 65 before starting the control. Therefore, it is possible to reduce the processing load and eliminate the need to secure an area for saving in the main RAM 65 .

Thereafter, as "LDY WA, (40H)", the WA register 104 of the main CPU 63 is overwritten with the information saved in the WA buffer 163a of the non-specific control work area 122 by the second LDY instruction (step S1710). "LDY" is the second LDY instruction by the second LDY execution circuit 164, "WA" is the WA register 104, and "(40H)" is the lower area (lower 1 byte area) address ("0340H"). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, by executing "LDY WA, (40H)", the information of the WA buffer 163a specified by the address "0340H" obtained by adding the non-specified control reference address to "40H" is obtained. can be returned to the WA register 104 . When using the LD instruction, the address data of the WA buffer 163a contained in the instruction code of the LD instruction must be the entire 2-byte address data ("0340H"). , the address data included in the instruction code of the second LDY instruction can be only the lower 1 byte ("40H") of the 2-byte address data. By using the second LDY instruction to restore the information saved in the WA buffer 163a to the WA buffer 163a, compared to the construction of restoring the information to the WA buffer 163a using the LD instruction, the program data capacity can be reduced.

Thereafter, as "LDY BC, (42H)", the BC register 105 of the main CPU 63 is overwritten with the information saved in the BC buffer 163b of the non-specific control work area 122 by the second LDY instruction (step S1711). "LDY" is the second LDY instruction by the second LDY execution circuit 164, "BC" is the BC register 105, and "(42H)" is the lower area (lower 1 byte area) address ("0342H"). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, by executing "LDY BC, (42H)", the information of the BC buffer 163b specified by the address "0342H" obtained by adding the non-specified control reference address to "42H" can be returned to the BC register 105. The entire address (2 bytes) must be set by using a second LDY instruction that can address the BC register 105 by setting only the low-order byte in the BC register 105 address. Compared to using the LD instruction, the data capacity of the instruction for overwriting the BC register 105 with the information saved in the BC buffer 163b can be reduced.

After that, as "LDY DE, (44H)", the DE register 106 of the main CPU 63 is overwritten with the information saved in the DE buffer 163c of the non-specific control work area 122 by the second LDY instruction (step S1712). "LDY" is the second LDY instruction by the second LDY execution circuit 164, "DE" is the DE register 106, and "(44H)" is the lower area (lower 1 byte area) address ("0344H"). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, by executing "LDY DE, (44H)", the information of the DE buffer 163c specified by the address "0344H" obtained by adding the non-specified control reference address to "44H" can be returned to the DE register 106. The entire address (2 bytes) must be set by using a second LDY instruction that can address the DE register 106 by setting only the low order byte in the address of the DE register 106. Compared to using the LD instruction, the data capacity of the instruction for overwriting the DE register 106 with the information saved in the DE buffer 163c can be reduced.

Thereafter, as "LDY HL, (46H)", the HL register 107 of the main CPU 63 is overwritten with the information saved in the HL buffer 163d of the non-specific control work area 122 by the second LDY instruction (step S1713). "LDY" is the second LDY instruction by the second LDY execution circuit 164, "HL" is the HL register 107, and "(46H)" is the lower area (lower 1 byte area) address ("0346H"). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, by executing "LDY HL, (46H)", the information of the HL buffer 163d specified by the address "0346H" obtained by adding the non-specified control reference address to "46H" can be returned to the HL register 107. The entire address (2 bytes) must be set by using the second LDY instruction which can address the HL register 107 by setting only the low order byte in the HL register 107 address. Compared to using the LD instruction, the data capacity of the instruction for overwriting the HL register 107 with the information saved in the HL buffer 163d can be reduced.

Thus, each information of the WA register 104, BC register 105, DE register 106 and HL register 107 of the main CPU 63 is restored to the information corresponding to the specific control immediately before the process corresponding to the non-specific control is started. In the processing (steps S1710 to S1713), the configuration using the second LDY instruction reduces the data capacity of the program for executing the processing compared to the configuration using the LD instruction in the processing. can be reduced.

After executing the process of step S1713, the information saved in the IX buffer 163e of the work area 122 for non-specific control by the LD instruction is transferred to the IX register 108 of the main CPU 63 as "LD IX, (0348H)". It overwrites (step S1714) and terminates this management execution process. By executing the processing of steps S1710 to S1714, each information of the WA register 104, BC register 105, DE register 106, HL register 107 and IX register 108 of the main CPU 63 is processed corresponding to non-specific control. It is possible to return to the information corresponding to the specific control immediately before the start.

Here, the information stored in the flag register and various registers of the main CPU 63 when the process corresponding to the non-specific control is executed is not saved in the main RAM 65 when the process corresponding to the specific control is restarted. . This eliminates the need to secure a storage area for saving the above information in the work area 121 for specific control and the stack area 123 for specific control.

Further, information stored in the flag register and various registers of the main CPU 63 when the process corresponding to the non-specific control is executed will be the information that the process corresponding to the non-specific control is executed after returning to the process corresponding to the specific control. This information is not used when restarting. In other words, the information necessary for multiple processing times of the processing corresponding to the non-specific control executed with the processing corresponding to the specific control in between is stored in the work area 122 for non-specific control or the stack area for non-specific control. 124 and not stored in the flag register and various registers of the main CPU 63 . Therefore, even if the information stored in the flag register and various registers of the main side CPU 63 is not saved in the main side RAM 65 when the processing corresponding to the non-specific control is executed, the processing corresponding to the non-specific control is executed. no problem with

Next, the check processing executed by calling the subroutine program in step S1708 will be described. In the check process, a process for collecting game history information, a process for deriving the management result of the game history, and a process for notifying the management result are executed. That is, the processing for collecting game history information, the processing for deriving the management result of the game history, and the processing for notifying the management result are executed as processing corresponding to non-specific control.

Before explaining the check process, the contents of various counters 171a to 171g, 172a to 172g, and 173a to 173g of the non-specific control work area 122 used to manage the game history will be explained. FIG. 58 is an explanatory diagram for explaining the configuration of the work area 122 for non-specific control.

As shown in FIG. 58, in the work area 122 for non-specific control, the first general winning counter 171a for normal use is provided at addresses "0303H" to "0304H", and "0305H" to "0306H". A second general winning counter 171b for normal use is provided at the address of "0307H" to "0308H", and a third general winning counter 171c for normal use is provided at the address "0309H" to " 030AH" is provided with a special electric winning counter 171d for normal use, and the addresses of "030BH" to "030CH" are provided with first operation counters for normal use 171e, and "030DH" to "030EH". ” is provided with a second operation counter 171f for normal use, and addresses “030FH” to “0310H” are provided with an out-counter 171g for normal use.

The address of the lower area (lower 1-byte area) of the target counter is set in the HL register 107 in the normal incoming ball management process (FIG. 60) described later. The work area 122 for non-specific control sets the address of "0303H" corresponding to the lower area of the first general winning counter 171a for normal use in the HL register 107, and then adds 2 to the value of the HL register 107. is repeatedly executed, the normal first general prize winning counter 171a → normal second general prize winning counter 171b → normal third general prize winning counter 171c → normal The target counters can be updated in the order of special electric prize winning counter 171d→normal first operation counter 171e→normal second operation counter 171f→normal out counter 171g.

As shown in FIG. 58, in the work area 122 for non-specific control, the first general winning counter 172a for the opening/closing execution mode is provided at addresses "0311H" to "0312H", and "0313H" to " A second general winning counter 172b for the opening/closing execution mode is provided at the address "0314H", and a third general winning counter 172c for the opening/closing execution mode is provided at the addresses "0315H" to "0316H". , a special electric prize winning counter 172d for the opening/closing execution mode is provided at addresses "0317H" to "0318H", and a first operation counter 172e for the opening/closing execution mode is provided at addresses "0319H" to "031AH". A second operation counter 172f for the opening/closing execution mode is provided at addresses "031BH" to "031CH", and an out counter 172g for the opening/closing execution mode is provided at addresses "031DH" to "031EH". is provided.

The address of the lower area (lower 1-byte area) of the target counter is set in the HL register 107 in the incoming ball management process (step S1805 of the check process (FIG. 59)) during the opening/closing execution mode, which will be described later. The work area 122 for non-specific control sets the address of "0311H" corresponding to the lower area of the first general winning counter 172a for the open/close execution mode in the HL register 107, and then adds 2 to the value of the HL register 107. By repeatedly executing the process, the first general winning counter 172a for the opening/closing execution mode→the second general winning counter 172b for the opening/closing execution mode→the third general winning counter 172b for the opening/closing execution mode in the ball entry management process during the opening/closing execution mode. General winning counter 172c→Special electric winning counter 172d for opening/closing execution mode→First operation counter 172e for opening/closing execution mode→Second operation counter 172f for opening/closing execution mode→Out counter 172g for opening/closing execution mode The data structure is such that the counter can be updated.

As shown in FIG. 58, in the work area 122 for non-specific control, the addresses of "031FH" to "0320H" are provided with the first general winning counters 173a for the high-frequency support mode. A second general winning counter 173b for the high frequency support mode is provided at the address "0322H", and a third general winning counter 173c for the high frequency support mode is provided at the addresses "0323H" to "0324H". A special electric winning counter 173d for the high-frequency support mode is provided at the addresses "0325H" to "0326H", and the first counter for the high-frequency support mode is provided at the addresses "0327H" to "0328H". An operation counter 173e is provided, and a second operation counter 173f for high frequency support mode is provided at addresses "0329H" to "032AH", and a high frequency support mode is provided at addresses "032BH" to "032CH". An out counter 173g for support mode is provided.

The address of the lower area (lower 1-byte area) of the target counter is set in the HL register 107 in the incoming ball management process (step S1806 of the check process (FIG. 59)) during the high-frequency support mode, which will be described later. The work area 122 for non-specific control sets the address of "031FH" corresponding to the lower area of the first general prize winning counter 173a for the high frequency support mode to the HL register 107, and then changes the value of the HL register 107 to 2. By repeatedly executing the adding process, the first general winning counter 173a for the high frequency support mode→the second general winning counter 173b for the high frequency support mode→high frequency support in the ball entry management process during the high frequency support mode. Third general winning counter 173c for mode→Special electric winning counter 173d for high frequency support mode→First operation counter 173e for high frequency support mode→Second operation counter 173f for high frequency support mode→For high frequency support mode The data structure is such that the target counters can be updated in the order of the out counter 173g.

The general winning counters 171a to 171c, 172a to 172c, 173a to 173c are counters for measuring the number of game balls entering the general winning opening 31 from a predetermined measurement start timing. The special electric prize-winning counters 171d, 172d, and 173d are counters for measuring the number of game balls entering the special electric prize-winning device 32 from a predetermined measurement start timing. The first operation counters 171e, 172e, and 173e are counters for measuring the number of game balls entering the first operation opening 33 from a predetermined measurement start trigger. The second operation counters 171f, 172f, and 173f are counters for measuring the number of game balls entering the second operation opening 34 from a predetermined measurement start trigger. The out counters 171g, 172g, and 173g are counters for measuring the number of game balls entered into the out port 24a from a predetermined measurement start timing.

Each of the counters 171a to 171g for normal use is in a state in which the front door frame 14 is in a closed state and is neither in the open/close execution mode nor in the high frequency support mode. It is used to count the number of game balls entered in the . Each of the counters 172a to 172g for the open/close execution mode is a game in which a ball is entered in the target ball entering portion 24a, 31 to 34 in the state where the front door frame 14 is in the closed state and the open/close execution mode. Used to count the number of balls. Each of the counters 173a to 173g for the high-frequency support mode enters the target ball-entering portions 24a, 31 to 34 in the state in which the front door frame 14 is closed and the high-frequency support mode is in effect. It is used to count the number of game balls played.

The reason why the state in which the front door frame 14 is open is not subject to measurement is that when the front door frame 14 is open, the game balls enter the ball entry portions 24a, 31 to 34 by maintenance. This is to exclude the number of balls entered in the case where the number of balls is counted. However, the present invention is not limited to this, and the state in which the front door frame 14 is in the open state may also be measured in the same manner as the state in which the front door frame 14 is in the closed state.

As shown in FIG. 58, a computation result storage area 174 is provided in the non-specific control work area 122 . The calculation result storage area 174 stores the game history management results calculated using the normal counters 171a to 171g, the open/close execution mode counters 172a to 172g, and the high frequency support mode counters 173a to 173g. This is an area for storing information. The information of the management result of the game history stored in the calculation result storage area 174 is stored and held until the newly calculated information of the management result of the game history is overwritten by the newly calculated information.

FIG. 59 is a flow chart showing the check processing executed by calling the subroutine program in step S1708. Note that the processing of steps S1801 to S1808 in the check processing, including subroutine processing, is executed by the main CPU 63 using a program for non-specific control and data for non-specific control. When executing a subroutine process, the return address information after execution of the subroutine process is written in the storage area corresponding to the current stack pointer value of the main CPU 63 in the stack area 124 for non-specific control. At the same time, the value of the stack pointer is updated to the information of the address of the next memory area to be stored. Further, when the processing of the subroutine is completed, the return address information is read from the storage area corresponding to the previous value with respect to the current stack pointer value of the main side CPU 63, and the return address information is corresponded. While returning to the program, the value of the stack pointer is updated to the information of the address of the storage area from which the information of the return address was read.

In the check process, if the front door frame 14 is open (step S1801: YES), the normal ball entry management process (step S1804), the ball entry management process during the opening/closing execution mode (step S1805), and the high frequency Result calculation processing (step S1807) and display processing (step S1808), which will be described later, are executed without executing any of the incoming ball management processing (step S1806) during the support mode. Since the game area PA is formed by the space partitioned in the front and rear by the back surface of the window panel 52 provided on the front door frame 14 and the front surface of the game board 24, when the front door frame 14 is in an open state, Even if the game area PA is opened forward and a game ball is shot toward the game area PA in this situation, the game ball cannot flow down the game area PA normally. In addition, when a game ball enters the ball entry portions 24a, 31 to 34 while the front door frame 14 is in an open state, the game hall administrator may This is the case where the front door frame 14 is in an open state and a game ball enters due to maintenance or the like. Since such a game ball entry is not a game ball entry in a regular game execution situation, there is no need to manage such a game ball entry. Therefore, in the check process, when the front door frame 14 is in the open state as described above, none of the processes in steps S1804 to S1806 are executed.

If the front door frame 14 is closed and neither the opening/closing execution mode nor the high-frequency support mode is set (steps S1801 to S1803: NO), normal ball entry management processing is executed (step S1804). If the front door frame 14 is in the closed state and the opening/closing execution mode is set (step S1801: NO, step S1802: YES), ball entry management processing during the opening/closing execution mode is executed (step S1805). If the front door frame 14 is closed and the high-frequency support mode is set (step S1801: NO, step S1803: YES), ball entry management processing during the high-frequency support mode is executed (step S1806).

FIG. 60 is a flow chart showing normal ball entry management processing in step S1804.

In normal ball entry management processing, first, a command "LDY HL, 03H" is executed (step S1901). "LDY" is the first LDY instruction by the first LDY execution circuit 156, "HL" is the content for setting the HL register 107 as the "transfer destination", and "03H" is the lower order of the first general winning counter 171a for normal use. This is the lower 1 byte of "0303H" which is the address where the area is set. As already explained, the IY register 109 stores "0300H" as a reference address for non-specific control. By executing "LDY HL, 03H", "0303H" obtained by adding the non-specific control reference address stored in the IY register 109 to the "03H" becomes the "transfer destination". HL register 107 is loaded. As a result, the address of the lower area of the first general prize winning counter 171 a for normal use can be set in the HL register 107 . In addition, in the incoming ball management processing during the opening/closing execution mode in step S1805 of the check processing (FIG. 59), by executing "LDY HL, 11H", it corresponds to the lower area of the first general winning counter 172a for the opening/closing execution mode. The address "0311H" is set in the HL register 107, and "LDY HL, 1FH" is executed in the ball entry management process during the high frequency support mode in step S1806, thereby making it the first general prize winning for the high frequency support mode. The HL register 107 is set to "031FH" which is an address corresponding to the lower area of the counter 173a.

As already explained, when using the LD instruction, the address data included in the instruction code of the LD instruction must be the entire 2-byte address data. The address data included in the instruction code of the 1LDY instruction can be only the lower 1 byte in the 2-byte address data. By setting the address corresponding to the lower area of the first general winning counters 171a to 173a in the HL register 107 using the first LDY instruction, the address is set in the HL register 107 using the LD instruction. The data capacity of the program can be reduced compared to the configuration.

As already explained, the address of the lower area of the target counter is set in the HL register 107 in normal incoming ball management processing. In step S1901, by setting the address corresponding to the lower area of the first general winning counter 171a for normal use in the HL register 107, the first general winning counter 171a for normal use is selected as the target counter. be able to. The target counter is updated by adding "2" to the value of the HL register 107 in step S1905, which will be described later.

After executing the process of step S1901, the information of the first winning opening detecting sensor 42a corresponding to the first general winning counter 171a for normal use is set as the information of the target detecting sensor (step S1902). The information of the object detection sensor is updated in step S1907, which will be described later.

Thereafter, it is determined whether or not a fall from the HI state to the LOW state of the detection signal received from the object detection sensor is detected (step S1903), and if the fall is detected (step S1903: YES) , the value of the target counter is incremented by 1 (step S1904). As already explained, the target counter is grasped based on the address data stored in the HL register 107 .

If a negative determination is made in step S1903, or if the process of step S1904 is carried out, the target counter is updated by adding 2 to the value of the HL register 107 (step S1905). In step S1905, the first general winning counter 171a for normal use→the second general winning counter for normal use 171b→the third general winning counter for normal use 171c→the special electric winning counter for normal use 171d→the first operation counter for normal use 171e →The second operation counter 171f for normal use→The out counter 171g for normal use, the target counters are updated in this order. In addition, in the ball entry management process (step S1805) during the opening/closing execution mode, the first general winning counter 172a for the opening/closing execution mode→the second general winning counter 172b for the opening/closing execution mode→the third general winning counter for the opening/closing execution mode Counter 172c→Special electric winning counter 172d for opening/closing execution mode→First operation counter 172e for opening/closing execution mode→Second operation counter 172f for opening/closing execution mode→Out counter 172g for opening/closing execution mode Along with being updated, in the ball entry management process (step S1806) during the high-frequency support mode, the first general winning counter 173a for the high-frequency support mode→the second general winning counter 173b for the high-frequency support mode→high-frequency support Third general winning counter 173c for mode→Special electric winning counter 173d for high frequency support mode→First operation counter 173e for high frequency support mode→Second operation counter 173f for high frequency support mode→For high frequency support mode , the target counters are updated in the order of the out counter 173g.

After that, it is determined whether or not the HL register 107 stores "0311H", which is the end address of normal incoming ball management processing (step S1906). If a negative determination is made in step S1906, the target detection sensor is updated to the detection sensor corresponding to the target counter updated in step S1905. In step S1907, the first winning opening detection sensor 42a→second winning opening detecting sensor 43a→third winning opening detecting sensor 44a→special train detecting sensor 45a→first operating opening detecting sensor 46a→second operating opening detecting sensor 47a→out The object detection sensors are updated in the order of the mouth detection sensor 48a.

Thereafter, the process returns to step S1903, and the processing of steps S1903 to S1907 is executed for the combination of the target counter and target detection sensor updated in steps S1905 and S1907. The processing of steps S1903 to S1907 is repeatedly executed until an affirmative determination is made in step S1906. As a result, the processing of steps S1903 to S1907 can be executed with all of the normal counters 171a to 171g as target counters. If an affirmative determination is made in step S1907, this normal ball entry management process ends.

Thus, in the normal ball entry management process, 1 is added to the values of the normal counters 171a to 171g corresponding to the detection of one game ball by the detection sensors 42a to 48a. This allows the main side CPU 63 to grasp the number of game balls entering the ball entering sections 24a, 31 to 34 in neither the opening/closing execution mode nor the high-frequency support mode. In addition, in the ball entry management process during the opening and closing execution mode, when one game ball is detected by the detection sensors 42a to 49a, the value of each counter 172a to 172g for the opening and closing execution mode is incremented by 1. . Thereby, it is possible for the main side CPU 63 to grasp the number of game balls entering the ball entering portions 24a, 31 to 34 in the open/close execution mode. Furthermore, in the ball entry management process during the high frequency support mode, the value of each of the counters 173a to 173g for the high frequency support mode corresponding to the case where one game ball is detected by the detection sensors 42a to 49a is 1. is added. This allows the main side CPU 63 to grasp the number of game balls entering the ball entering sections 24a, 31 to 34 in the high frequency support mode.

By executing the processing of steps S1804 to S1806 in the check processing (FIG. 59), the number of game balls entered into the general prize winning opening 31 uses the general winning counters 171a to 171c, 172a to 172c, and 173a to 173c. The number of game balls entering the special electric prize winning device 32 is measured using the special electric prize winning counters 171d, 172d, and 173d, and the number of game balls entering the first operating port 33 is counted as the first operation. Counters 171e, 172e, and 173e are used to measure the number of game balls entering the second operation port 34, and the number of game balls entering the second operation port 34 is measured using the second operation counters 171f, 172f, and 173f, and the number of game balls to the out port 24a is counted. are counted using out counters 171g, 172g, and 173g. As a result, the main side CPU 63 can grasp the ball entry history to each of the ball entry portions 24a, 31-34. Further, each of the normal counters 171a to 171g, each of the opening/closing execution mode counters 172a to 172g, and each of the high frequency support mode counters 173a to 173g are separately provided. The status of none of the frequent support modes, the status of the open/close execution mode, and the status of the high frequency support mode are discriminated from each other, and the history of the ball entry into each ball entry section 24a, 31 to 34 is sent to the main side CPU 63. It is possible to grasp

Returning to the description of the check processing (FIG. 59), if affirmative determination is made in step S1801, if the processing of step S1804 is executed, if the processing of step S1805 is executed, or if the processing of step S1806 is executed , the result calculation process is executed (step S1807). In the result calculation process, the values of the normal counters 171a to 171g, the open/close execution mode counters 172a to 172g, and the high frequency support mode counters 173a to 173g are totaled. The number is calculated, and it is determined whether or not the calculated total number is equal to or greater than "6000" which is the calculation reference number. Then, when the total number is equal to or greater than the calculation reference number, various parameters are calculated to make it possible to grasp the game history, and the calculation result is stored in the work area 122 for non-specific control. Store in area 174 . After that, the values of the normal counters 171a to 171g, the open/close execution mode counters 172a to 172g, and the high frequency support mode counters 173a to 173g are cleared to "0".

After performing the result calculation processing in step S1807, display processing is performed (step S1808), and this check processing ends. In the display processing in step S1808, based on the calculation result stored in the calculation result storage area 174, the first to third notification display devices 69a to 69a are displayed so that the display corresponding to the management result of the game history is performed. 69c display control is performed. The manager of the game hall can confirm the management result of the game history by confirming the display of the first to third notification display devices 69a to 69c.

As described above, when the process for non-specific control ends, the reference address for specific control ("0000H") is set in the IY register 109 in step S1605 of the management process (FIG. 56(a)). A non-specific control reference address (“0300H”) is set in the IY register 109 at the start of management execution processing (FIG. 57), which is processing for non-specific control, and the IY register 109 is set at the end of the management execution processing (FIG. 57). By returning the information in the register 109 to the specific control reference address (“0000H”), the specific control reference address can be used by the first LDY instruction and the second LDY instruction while the specific control process is being executed. During the execution of management execution processing, which is processing for specific control, a non-specific control reference address can be made available by the first LDY instruction and the second LDY instruction. By switching the data stored in one register, the specific control reference address and the non-specific control reference address can be used. The number of registers reserved for making these reference addresses available can be reduced compared to a configuration that reserves registers in which reference addresses are set.

In steps S1710 to S1713 of the management execution process (FIG. 57), the information saved in the WA buffer 163a, BC buffer 163b, DE buffer 163c and HL buffer 163d using the second LDY instruction is transferred to the corresponding WA registers 104 and BC. The configuration for returning to the register 105, the DE register 106 and the HL register 107 is compared with the configuration for returning the information saved in these buffers 163a to 163e using the LD instruction to these registers 104 to 107. Therefore, the data capacity of the program for restoring the information can be reduced.

In step S1901 of the normal ball entry management process (Fig. 60), the first LDY instruction ("LDY HL, 03H") is used to change the lower area address ("0303H") of the first general winning counter 171a for normal use. By setting the address in the HL register 107, the data capacity of the program for setting the address in the HL register 107 is reduced compared to the configuration in which the address is set in the HL register 107 using the LD instruction. can do. Also, in the incoming ball management process during the opening/closing execution mode in step S1805 of the check process (FIG. 59), the first LDY command ("LDY HL, 11H") is used to set the first general winning counter 172a for the opening/closing execution mode. Since the address (“0311H”) corresponding to the lower area is set in the HL register 107, compared to the configuration in which the address is set in the HL register 107 using the LD instruction, the address is set in the HL register 107. 107 can be reduced. Furthermore, in the ball entry management process during the high frequency support mode in step S1806 of the check process (FIG. 59), the first general winning for the high frequency support mode is performed using the first LDY command ("LDY HL, 1FH"). Since the address (“031FH”) corresponding to the lower area of the counter 173a is set in the HL register 107, compared to the configuration in which the address is set in the HL register 107 using the LD instruction, the address in the HL register 107, the data capacity of the program can be reduced.

Next, communication between the main side CPU 63 and the sound/light side CPU 93 or the payout side CPU 83 will be described.

As already described with reference to FIG. 8 , the main control board 61 is provided with the first transmission circuit 101 , the second transmission circuit 102 and the reception circuit 103 . The first transmission circuit 101 is a circuit for transmitting various commands from the main side CPU 63 to the sound and light side CPU 93 . The first transmission circuit 101 is provided with a transmission standby buffer 175 (FIG. 61) in which commands to be transmitted are temporarily stored. communication commands). The first transmission circuit 101 communicates with the sound and light receiving circuit 96 provided on the sound emission control board 91 to transmit the command set in the transmission standby buffer 175 to the sound and light receiving circuit 96 . The sound/light receiving circuit 96 is provided with a post-reception standby buffer 178 (FIG. 61) in which received commands are temporarily stored. Then, it can be used by the sound and light side CPU 93 . Details of communication between the main side CPU 63 and the sound and light side CPU 93 will be described later.

The second transmission circuit 102 is a circuit for transmitting various commands from the main side CPU 63 to the payout side CPU 83 . The second transmission circuit 102 is provided with a transmission standby buffer (not shown) in which commands to be transmitted are temporarily stored, and the main CPU 63 sets commands to be transmitted in the transmission standby buffer. The second transmission circuit 102 communicates with the payout side reception circuit 87 provided on the payout control board 81 to transmit the command set in the transmission standby buffer to the payout side reception circuit 87 . The payout-side receiving circuit 87 is provided with a post-receipt standby buffer (not shown) in which received commands are temporarily stored. It can be used by the side CPU 83 .

The receiving circuit 103 is a circuit for receiving various commands transmitted from the payout side CPU 83 . The payout control board 81 is provided with a payout side transmission circuit (not shown) for transmitting various commands from the payout side CPU 83 to the main side CPU 63 . The payout side transmission circuit is provided with a transmission standby buffer (not shown) in which a command to be transmitted is temporarily stored, and the payout side CPU 83 sets the command to be transmitted in the transmission standby buffer. The payout side transmission circuit communicates with the reception circuit 103 provided on the main control board 61 to transmit the command set in the transmission standby buffer to the reception circuit 103 . The receiving circuit 103 is provided with a post-reception standby buffer (not shown) in which received commands are temporarily stored. will be available at

<Data Configuration of Command Transmitted from Main CPU 63>
Next, the data configuration of the command transmitted from the main CPU 63 to the payout CPU 83 or the sound and light CPU 93 will be described by taking the data configuration of the command transmitted from the main CPU 63 to the sound and light CPU 93 as an example. .

FIG. 61 is an explanatory diagram for explaining the electrical configuration of the main control board 61 and the sound emission control board 91 for transmitting commands from the main side CPU 63 to the sound and light side CPU 93 . As already explained, the main control board 61 is provided with the first transmission circuit 101 , and the audio emission control board 91 is provided with the sound/light receiving circuit 96 . As shown in FIG. 61, the first transmission circuit 101 is provided with a transmission standby buffer 175 in which a command (a communication command to be described later) to be transmitted to the sound/light side CPU 93 is set. The transmission standby buffer 175 is a ring buffer consisting of 30 bytes. Among the commands transmitted from the main side CPU 63 to the sound and light side CPU 93, the command with the largest amount of data is the normal return command, and the normal return command set in the transmission standby buffer 175 (normal return command for communication described later) ) is 14 bytes.

When it is time to set a new command while the command being transmitted remains in the transmission standby buffer 175, the new command is placed next to the area in which the command being transmitted is set in the transmission standby buffer 175. It is set in the following areas and enters a transmission standby state. In addition, when it is time to set a new command in a state in which commands being transmitted and commands awaiting transmission exist in the transmission standby buffer 175, the new command is stored in the transmission standby buffer 175 and waiting for transmission. is set in the area after the area in which the command is set, and the transmission standby state is established. The first transmission circuit 101 transmits the commands set in the transmission standby buffer 175 to the sound and light receiving circuit 96 in the order set in the transmission standby buffer 175 . The data capacity of the transmission standby buffer 175 is set larger than the total data capacity of a plurality of commands that can exist in the transmission standby buffer 175 at the same time. Therefore, at the timing when each command is set in the transmission standby buffer 175, an empty area for setting the command is secured.

The first transmission circuit 101 is provided with a transmission buffer 176 in which data to be transmitted to the sound and light side CPU 93 is set. The transmit buffer 176 consists of 1 byte. The commands set in the transmission standby buffer 175 are set in the transmission buffer 176 byte by byte and transmitted to the sound and light side CPU 93 . Specifically, when a command is set in the transmission standby buffer 175, the first transmission circuit 101 first transmits the leading 1-byte data among the multiple-byte data included in the command. It sets it in the buffer 176 and transmits the 1-byte data to the sound and light side CPU 93 . After that, the first transmission circuit 101 sets, in the transmission buffer 176, the 1-byte data next to the leading 1-byte data among the multiple-byte data included in the command, and data to the sound and light side CPU 93. In this manner, the first transmission circuit 101 keeps one byte of the multiple-byte data included in the command to be set in the transmission buffer 176 until the entire transmission of the command stored in the transmission standby buffer 175 is completed. 1-byte data set in the transmission buffer 176 to the sound and light side CPU 93 is repeatedly executed while sequentially updating the data.

As shown in FIG. 61, the sound and light reception circuit 96 includes a reception buffer 177 in which 1-byte data received from the first transmission circuit 101 is stored, and a reception buffer 177 in which commands received from the main CPU 63 are stored. A waiting buffer 178 is provided. The post-reception standby buffer 178 is a 30-byte ring buffer, like the transmission standby buffer 175 in the first transmission circuit 101 described above. The storage capacity of the post-reception standby buffer 178 is set larger than the total amount of data in a plurality of commands that can exist in the post-reception standby buffer 178 at the same time.

The sound and light side RAM 95 is provided with a command storage buffer 179 in which commands received from the main side CPU 63 are stored in a state in which they can be used by the sound and light side CPU 93 . The command storage buffer 179 is a 30-byte ring buffer. The command stored in the standby buffer 178 after reception is transferred to the command storage buffer 179 and stored in the command storage buffer 179 until the CPU 93 on the sound and light side uses it. The storage capacity of the command storage buffer 179 is set larger than the total amount of data in a plurality of commands that can exist in the command storage buffer 179 at the same time.

After receiving the 1-byte data stored in the reception buffer 177, the sound/light receiving circuit 96 sets the data of 1 byte in the standby buffer 178, and clears the reception buffer 177 to "0" to enable reception of the next 1-byte data. state. Then, it outputs a receivable signal to the first transmission circuit 101 . When the first transmission circuit 101 receives the receivable signal and data is set in the transmission buffer 176, the first transmission circuit 101 transmits the 1-byte data set in the transmission buffer 176 to the sound and light side. It transmits to the receiving circuit 96 .

Next, a case where a command having a data amount of 3 bytes or more at the time of transmission is transmitted from the main side CPU 63 to the sound and light side CPU 93 will be described. A command transmitted from the main side CPU 63 to the sound and light side CPU 93 includes a header HD and a footer FT. FIG. 62(a) is an explanatory diagram for explaining the data structure of the header HD, and FIG. 62(b) is an explanatory diagram for explaining the data structure of the footer FT.

As shown in FIG. 62(a), the header HD is 1-byte data consisting of 0th to 7th bits. The 0th to 7th bits of the header HD are set with command identification data that makes it possible to grasp the type of command. The sound/light side CPU 93 grasps the type of the received command based on the command identification data.

The most significant bit (seventh bit) of the command identification data is a header identification bit that enables identification of the header HD. "1" is set in the header identification bit. Among the 1-byte data included in the command, the header HD is the only data in which the most significant bit is set to "1". The sound and light receiving circuit 96 determines whether or not the most significant bit of the 1-byte data stored in the reception buffer 177 is set to "1", and determines that the 1-byte data is the header HD. grasp whether or not When receiving a plurality of commands from the first transmission circuit 101, the sound/light reception circuit 96 can grasp the delimiter position of these commands based on the position of the header HD. Note that the header identification bit may be set to "0" and the most significant bit (seventh bit) of the data other than the header HD may be set to "1". In this configuration, the sound and light receiving circuit 96 determines whether or not the most significant bit of the 1-byte data stored in the reception buffer 177 is set to "0", thereby determining whether the 1-byte data is It can be grasped whether it is a header HD or not.

As shown in FIG. 62(b), the footer FT is 1-byte data consisting of 0th to 7th bits. The footer FT contains footer identification data indicating that it is a footer FT, and an error detection bit that enables the sound and light receiving circuit 96 to confirm that the contents of the command data have not changed under the influence of noise. is set. Data "0101010" is set in the upper 7 bits (1st to 7th bits) of the footer FT as footer identification data. Of the 1-byte data included in the command transmitted from the main side CPU 63 to the sound and light side CPU 93, only the footer FT has "0101010" set in the upper 7 bits. The sound/light receiving circuit 96 determines whether or not the footer identification data is set in the upper 7 bits of the 1-byte data stored in the reception buffer 177, thereby determining whether the 1-byte data is the footer FT. grasp whether or not The sound/light receiving circuit 96 recognizes the start position of the command by recognizing the header HD, and also recognizes the end position of the command by recognizing the footer FT. A series of data starting from the header HD and ending with the footer FT is recognized as one command.

An error detection bit is set in the 0th bit of the footer FT. The error detection bit is set to "0" or "1" so that the total number of "1"s in the "0" and "1" information contained in the command is an even number. When a command is stored in the standby buffer 178 after reception, the sound/light receiving circuit 96 determines whether or not the total number of "1"s contained in the command is an even number. is not an even number, it is determined that a communication error has occurred. As a result, it is possible to prevent the sound and light side CPU 93 from using commands rewritten by noise as they are.

When the 1-byte data received after the footer FT from the first transmission circuit 101 is data other than the header HD, the sound and light receiving circuit 96 receives the footer FT after receiving the header HD. It is recognized that a communication error has occurred even when the next header HD is received without any delay. This prevents the sound and light CPU 93 from using data different from the data contained in the command set in the transmission standby buffer 175 by the main CPU 63 .

When the sound/light receiving circuit 96 identifies the occurrence of a communication error, it outputs a retransmission request signal to the first transmitting circuit 101 . If the first transmission circuit 101 does not receive a retransmission request signal after the command transmission is completed, the first transmission circuit 101 deletes the data of the command that has been transmitted this time from the transmission standby buffer 175 . Then, when the next command is set in the transmission standby buffer 175, transmission of the next command is started. On the other hand, if a retransmission request signal is received after command transmission is completed, the command stored in the transmission standby buffer 175 is transmitted again.

As shown in FIG. 61, the sound/light receiving circuit 96 is provided with a communication error counter 181 that counts the number of consecutive communication errors. The communication error counter 181 stores numerical information of "0" to "3". The sound and light receiving circuit 96 adds 1 to the value of the communication error counter 181 when the resend request signal is output, and when no communication error is confirmed for the command received after the resend request signal is output, communication is performed. Clear the error counter 181 to "0". When the value of the communication error counter 181 reaches "3", the sound and light side CPU 93 controls the light emission of the display light emitting unit 53, the sound output control of the speaker unit 54, and the pattern display device 41 so that the communication error notification is performed. Control the display. Thereby, it is possible to inform the manager of the game hall that the command transmission from the main side CPU 63 to the sound and light side CPU 93 is not performed normally.

Commands stored in the transmission standby buffer 175 and 1-byte data stored in the transmission buffer 176 are partially cleared (step S107) or completely cleared (step S114) in the main process (FIG. 15). cleared if

When one or more pieces of 1-byte data other than the header HD and footer FT are set in the command sent from the main CPU 63 to the sound and light CPU 93, the main CPU 63 sends a command for communication with a data amount of 4 bytes or more. , and sets the command for the communication in the transmission standby buffer 175 . A command for communication is transmitted from the first transmission circuit 101 to the sound and light reception circuit 96 and stored in the standby buffer 178 after reception. When the data amount of the command stored in the post-reception standby buffer 178 is 4 bytes or more, that is, when the command for communication is stored in the post-reception standby buffer 178, the sound and light side CPU 93 performs the communication. command is converted into a converted command and stored in the command storage buffer 179 . Then, an effect is produced based on the post-conversion command stored in the command storage buffer 179 .

In addition to the header HD and footer FT, the variation command transmitted to the sound and light side CPU 93 in the variation command transmission process (FIG. 68) in step S1014 of the special figure variation start process (FIG. 35) The display continuation time data stored in the display continuation time counter 142 (FIG. 51(b)) in the work area 121 is set. As already explained, the display duration data is 2-byte numerical data. If the data stored in the display continuation time counter 142 is set between the header HD and the footer FT to generate a command for variation, the frame (1-byte data), the most significant bit (seventh bit) may be set to "1". In this configuration, if the variation command is set in the transmission standby buffer 175 as it is, the frame other than the header HD (the frame in which the display duration data is set) in the sound and light receiving circuit 96 is the header HD. is erroneously recognized. In this embodiment, the main CPU 63 generates a variation command for communication in which the most significant bit (seventh bit) in frames other than the header HD is changed to "0", and waits for transmission of the variation command for communication. Set in buffer 175 . As a result, the header HD and frames other than the header HD are discriminated by the sound and light receiving circuit 96 assuming that the most significant bit (seventh bit) of the frames other than the header HD is always set to "0". can be made possible. Hereinafter, in this specification, 1-byte data included in a command is also referred to as a "frame".

On the other hand, for example, the all-clear return command sent to the sound and light side CPU 93 in step S116 of the main processing (FIG. 15) is a 2-byte command consisting of only the header HD and the footer FT. As already explained, the most significant bit (seventh bit) of the footer FT is "0". Therefore, a 2-byte command consisting of only the header HD and footer FT determines whether the frame is the header HD by determining whether the most significant bit (seventh bit) of each frame is "0". It is a command that can identify whether or not In the present embodiment, if no data other than the header HD and footer FT are set in the command sent from the main CPU 63 to the sound and light CPU 93, the main CPU 63 directly transmits the 2-byte command consisting of only the header HD and footer FT. It is set in the transmission standby buffer 175 . The command is transmitted from the first transmission circuit 101 to the sound/light reception circuit 96 and stored in the standby buffer 178 after reception. When the data amount of the command stored in the waiting buffer 178 after reception is 2 bytes, the sound and light side CPU 93 stores the command in the command storage buffer 179 as it is.

In the following, the data structure of a command including frames other than the header HD and footer FT will be described by taking the variation command and the normal return command as examples.

First, the data configuration of the variation command will be described. FIG. 62(c) is an explanatory diagram for explaining the data configuration of the communication variation command, and FIG. 62(d) is an explanatory diagram for explaining the data configuration of the post-conversion variation command.

As shown in FIG. 62(c), the variation command for communication includes five frames in the order of header HD→first data frame FR1→second data frame FR2→first most significant frame SF1→footer FT. is set. As already explained, each frame contains 1-byte data. The data stored in the lower area of the display duration counter 142 is set in the first data frame FR1, and the data stored in the upper area of the display duration counter 142 is set in the second data frame FR2. set. However, the data set in the most significant bit (7th bit) of these data frames FR1 and FR2 is changed to "0" in order to distinguish between the header HD and these data frames FR1 and FR2. be.

The number of data frames FRm (m is an integer from 1 to 10) included in a communication command differs depending on the command type. A maximum of 10 data frames FRm are set in the command for communication. The first most significant frame SF1 is a frame that makes it possible to grasp the data of the most significant bit changed to "0" among the data set in the first to seventh data frames FR1 to FR7. The first most significant frame SF1 is set between the last data frame FRm and the footer FT when the number of data frames FRm included in the communication command is seven or less. The (m-1)th bit (m is an integer from 1 to 7) of the first most significant frame SF1 corresponds to the most significant bit of the mth data frame FRm. For example, the 0th bit of the first most significant frame SF1 corresponds to the most significant bit of the first data frame FR1, and the 1st bit of the first most significant frame SF1 corresponds to the most significant bit of the second data frame FR2. Yes. The most significant bit data in the lower area of the display duration counter 142 is set to the 0th bit of the first most significant frame SF1, and the most significant bit data in the upper area of the display duration counter 142 is set to the first most significant bit. It is set to the first bit of frame SF1.

As described above, the number of data frames FRm included in the communication variation command is two, and there is no data frame corresponding to the 2nd to 6th bits in the first most significant frame SF1. As shown in FIG. 62(c), "0" is set in the second to sixth bits of the first most significant frame SF1 in the variation command for communication. In this way, if the number of data frames FRm included in the command for communication is 6 or less, and the bits for which the corresponding data frame FRm does not exist among the 0th to 6th bits in the first most significant frame SF1, "0 ” is set. "0" is always set to the most significant bit (seventh bit) in the first most significant frame SF1. This enables the sound/light receiving circuit 96 to distinguish between the header HD and the first most significant frame SF1.

As shown in FIG. 62(d), a header HD, a first data frame FR1, a second data frame FR2, and a footer FT are set in the post-conversion variation command. The header HD of the post-conversion variation command, the 0th to 6th bits of the first data frame FR1, the 0th to 6th bits of the second data frame FR2, and the footer FT contain the header HD of the variation command for communication, The 0th to 6th bits of the first data frame FR1, the 0th to 6th bits of the second data frame FR2, and the data of the footer FT are set. Further, the most significant bits of the data frames FR1 and FR2 of the post-conversion variation command are set with the data of the corresponding bits in the first most significant frame SF1 of the variation command for communication. Specifically, in the most significant bit of the first data frame FR1 of the post-conversion variation command, the 0th bit data corresponding to the most significant bit in the first most significant frame SF1 of the variation command for communication is is set. Further, the most significant bit of the second data frame FR2 of the post-conversion variation command is set to the first bit data corresponding to the most significant bit in the first most significant frame SF1 of the variation command for communication. there is

In this way, the first most significant frame SF1, which is a collection of the most significant bit information of the first and second data frames FR1 and FR2, is set in the variation command for communication. As a result, while making it possible to distinguish between the header HD and the frame other than the header HD in the communication variation command, the sound and light side CPU 93 receives the most significant bit data in the various counters in which the data is set in the communication variation command. can be comprehended in

As shown in FIG. 61, the work area 121 for specific control is provided with a first save area 182 and a second save area 183 . The first save area 182 is an area in which data of the first most significant frame SF1 is set, and the second save area 183 is an area in which data of a second most significant frame SF2 described later is set. These save areas 182 and 183 consist of 1 byte. When 1 to 7 data frames FRm are included in the communication command transmitted from the main side CPU 63 to the sound and light side CPU 93, the first save area 182 stores the first to mth data frames FR1 to FRm ( (m is an integer from 1 to 7) is set to the most significant bit data. When 8 to 10 data frames FRm are included in the communication command transmitted from the main side CPU 63 to the sound and light side CPU 93, the first save area 182 stores the first to seventh data frames FR1 to FR7. The data of the most significant bit is set, and the data of the most significant bit of the 8th to mth data frames (m is any integer from 8 to 10) is set in the second save area 183 .

FIG. 63 is an explanatory diagram for explaining how a communication variation command is generated. The most significant bit data in the lower area of the display duration counter 142 is set to the 0th bit of the first save area 182, and the most significant bit data in the upper area of the display duration counter 142 is saved in the first save area 182. is set to the first bit of In the first save area 182, "0" is set to the second to sixth bits for which no corresponding counter exists. Furthermore, the most significant bit (seventh bit) of the first save area 182 is always set to "0". As already described, the configuration in which the most significant bit (seventh bit) in the data of the first highest-order frame SF1 stored in the first save area 182 is always set to "0" enables sound and light reception. The header HD and the first most significant frame SF1 can be distinguished in the circuit 96. FIG.

As shown in FIG. 61, the first transmission circuit 101 is provided with a write pointer 186 . The write pointer 186 is a pointer that enables the main CPU 63 to grasp the command write start position in the transmission standby buffer 175 . The main CPU 63 grasps the empty area of the transmission standby buffer 175 based on the value of the write pointer 186 . Then, the data of the header HD, the data stored in the lower area of the display continuation time counter 142, the data stored in the upper area of the display continuation time counter 142, and the data stored in the first save area 182 are stored in the grasped empty area. Set the data and footer FT data. In the transmission standby buffer 175, the most significant bit (seventh bit) in the area where data other than the header HD and footer FT are set is cleared to "0". As a result, the communication variation command is set in the transmission standby buffer 175 .

Next, the data configuration of the normal return command will be described. FIG. 64 is an explanatory diagram for explaining the data configuration of the normal return command for communication, and FIG. 65 is an explanatory diagram for explaining the data configuration of the post-conversion normal return command.

As shown in FIG. 64, the normal return command for communication includes header HD→first data frame FR1 to seventh data frame FR7→first most significant frame SF1→eighth data frame FR8 to tenth data frame FR10→ 14 frames are set in the order of second highest frame SF2→footer FT. As already explained, 1-byte data is set in each frame.

Data stored in the set value counter in the work area 121 for specific control is set in the first data frame FR1 in the normal return command for communication. As a result, the sound and light side CPU 93 can grasp the current setting value of the pachinko machine 10 . In the second data frame FR2, the data stored in the first special figure reservation number counter 118 in the work area 121 for specific control is set, and in the work area 121 for specific control in the third data frame FR3 The data stored in the second special figure reservation number counter 119 is set. Thereby, the number of reservations in the first special figure reservation area 115 and the number of reservations in the second special figure reservation area 116 can be grasped by the sound and light side CPU 93 . Data stored in the mode data area in the work area 121 for specific control is set in the fourth data frame FR4. As already explained, the high frequency support mode flag and the opening/closing execution mode flag are set in the mode data area. By including the data in the mode data area in the normal return command, it is possible for the sound and light side CPU 93 to grasp whether the high frequency support mode and the opening/closing execution mode are selected. Data stored in the round counter in the work area 121 for specific control is set in the fifth data frame FR5. This allows the sound and light side CPU 93 to grasp the number of remaining round games in the open/close execution mode. The data stored in the right/wrong data area 158 in the work area 121 for specific control is set in the sixth data frame FR6. As already explained, the 0th bit of the success/failure data area 158 is set with the small hit flag 158b, and the 1st bit is set with the big hit flag 158a. By including the data of the success/failure data area 158 in the normal return command, it is possible for the sound/light side CPU 93 to grasp the occurrence of the big winning result and the occurrence of the small winning result. The data stored in the distribution data area 162 is set in the seventh data frame FR7. As already explained, the 0th bit of the distribution data area 162 is set to the 4R high accuracy flag 162a, the 1st bit is set to the 8R high accuracy flag 162b, and the 2nd bit is the 16R high accuracy flag. A sure flag 162c is set. By including the data of the distribution data area 162 in the normal return command, it is possible to hear that the 4R high probability jackpot result has occurred, the 8R high probability jackpot result has occurred, and the 12R high probability jackpot result has occurred. The light side CPU 93 can be made graspable. Data stored in the game cycle area is set in the eighth data frame FR8. As already explained, the game round flag is set in the 0th bit of the game round area. Since the data of the game round area is included in the normal return command, it is possible for the sound and light side CPU 93 to grasp whether or not the game round is being executed. As already explained, based on the winning to any of the operation openings 33, 34, the display is started in any of the special figure display units 37a, 37b and the symbol display device 41, and ends after displaying a predetermined result. The time until the game is played corresponds to one game round. The data stored in the lower area of the special special electric timer counter in the work area 121 for specific control is set in the ninth data frame FR9, and the upper order of the special special electric timer counter is set in the tenth data frame FR10. Data stored in the area is set. As a result, when a game round is being executed, the sound and light side CPU 93 can grasp the remaining display continuation time in the game round. However, the data set in the most significant bit (seventh bit) of these data frames FR1 to FR10 is changed to "0" in order to distinguish between the header HD and these data frames FR1 to FR10. be.

If the data stored in the display continuation time counter 142 is set in the ninth to tenth data frames FR9 to FR10 to generate the normal return command, the most significant bit (seventh bit) of these frames FR9 and FR10 ) may be set to “1”. In this configuration, if the normal return command is set in the transmission standby buffer 175 as it is, the frames other than the header HD (the ninth data frame FR9 and the tenth data frame FR10) are transferred to the header HD in the sound and light receiving circuit 96. It is mistakenly recognized that there is. In this embodiment, the main CPU 63 generates a normal return command for communication by changing the most significant bit (seventh bit) of a frame other than the header HD to "0", and waits for transmission of the normal return command for communication. Set in buffer 175 . As a result, the header HD and frames other than the header HD are discriminated by the sound and light receiving circuit 96 assuming that the most significant bit (seventh bit) of the frames other than the header HD is always set to "0". can be made possible.

As already explained, the first highest-order frame SF1 is a frame that allows the user to grasp the data of the highest-order bit changed to "0" among the data set in the first to seventh data frames FR1 to FR7. . The first most significant frame SF1 is set between the seventh data frame FR7 and the eighth data frame FR8 when the number of data frames FRm included in the command is eight or more. The m-th bit (m is an integer from 0 to 6) of the first most significant frame SF1 corresponds to the most significant bit of the (m+1)th data frame FR(m+1). The most significant bit data in the set value counter is set to the 0th bit of the first most significant frame SF1, and the most significant bit data in the first special figure reservation number counter 118 is set to the first bit of the first most significant frame SF1 The most significant bit data in the second special figure reservation number counter 119 is set to the second bit of the first most significant frame SF1, and the most significant bit data in the mode data area is the first most significant frame SF1 Set to 3 bits. The most significant bit data in the round counter is set to the fourth bit of the first most significant frame SF1, the most significant bit data in the success/failure data area 158 is set to the fifth bit of the first most significant frame SF1, The most significant bit data in the distribution data area 162 is set to the sixth bit of the first most significant frame SF1.

The second most significant frame SF2 is a frame that makes it possible to grasp the data of the most significant bit changed to "0" among the data set in the eighth data frame FR8 to the tenth data frame FR10. The second most significant frame SF2 is set between the last data frame (tenth data frame FR10) and the footer FT when the number of data frames FRm included in the command is eight or more. The (m-8)th bit (m is an integer from 8 to 10) of the second most significant frame SF2 corresponds to the most significant bit of the mth data frame FRm. The most significant bit data in the game area is set to the 0th bit of the second most significant frame SF2, and the most significant bit data in the lower area of the special special electric timer counter is set to the first bit of the second most significant frame SF2. The data of the most significant bit in the upper area of the special special electric timer counter is set to the second bit of the second most significant frame SF2.

As shown in FIG. 65, a header HD, a first data frame FR1 to a tenth data frame FR10, and a footer FT are set in the post-conversion normal return command. The header HD of the normal return command after conversion, the 0th to 6th bits of the 1st to 10th data frames FR1 to FR10, and the footer FT contain the header HD of the normal return command for communication and the 1st to 10th data frame FR1. The 0th to 6th bits of FR10 and the data of the footer FT are set. Further, the most significant bits of the first to seventh data frames FR1 to FR7 of the post-conversion normal return command are set with the data of the corresponding bits in the first most significant frame SF1 of the normal return command for communication. Furthermore, the most significant bits of the eighth to tenth data frames FR8 to FR10 of the post-conversion normal return command are set with the data of the corresponding bits in the second most significant frame SF2 of the normal return command for communication. .

The normal return command for communication includes the first most significant frame SF1 that collects the most significant bit information of the first to seventh data frames FR1 to FR7, and the most significant bit information of the eighth to tenth data frames FR8 to FR10. A second most significant frame SF2 is set up which collects information. As a result, while distinguishing between the header HD and the frame other than the header HD in the normal return command for communication, the data of the most significant bit in the various counters in which the data is set in the normal return command for communication is transferred to the sound and light side CPU 93. can be comprehended in

FIG. 66 is an explanatory diagram for explaining how the normal return command for communication is generated. As shown in FIG. 66, the most significant bit data of the set value counter is set to the 0th bit of the first save area 182, and the most significant bit data of the first special figure reservation number counter 118 is the first save area 182 , the most significant bit data of the second special figure reservation number counter 119 is set to the second bit of the first save area 182, the most significant bit data of the mode data area is the first save area It is set to the 3rd bit of 182. The most significant bit data of the round counter is set to the fourth bit of the first save area 182, the most significant bit data of the success/failure data area 158 is set to the fifth bit of the first save area 182, and sorted. The most significant bit data of the data area 162 is set to the 6th bit of the first save area 182 .

The most significant bit data of the game area is set to the 0th bit of the second save area 183, and the most significant bit data of the lower area of the special special electric timer counter is set to the first bit of the second save area 183. , the most significant bit data in the upper area of the special special electric timer counter is set to the second bit of the first save area 182 . In the second save area 183, "0" is set to the 3rd to 6th bits for which the corresponding counter does not exist.

As already explained, the most significant bit (seventh bit) of the first save area 182 is always set to "0". Also, the most significant bit (seventh bit) of the second save area 183 is always set to “0”. The data stored in the first save area 182 is the data of the first most significant frame SF1, and the data stored in the second save area 183 is the data of the second most significant frame SF2. Since the most significant bit (seventh bit) of these most significant frames SF1 and SF2 is always set to "0", the sound and light side receiving circuit 96 receives the header HD and these most significant frames SF1 and SF2. and can be identified.

The main CPU 63 grasps the empty area of the transmission standby buffer 175 based on the value of the write pointer 186 . Then, in the grasped empty area, the data of the header HD, the set value counter, the first special figure reservation number counter 118, the second special figure reservation number counter 119, the mode data area, the round counter, the success or failure data area 158, the distribution data The data stored in the area 162, the game round area, the lower area of the special special electric timer counter, the upper area of the special special electric timer counter, and the data of the footer FT are set. In the transmission standby buffer 175, the most significant bit (seventh bit) in the area where data other than the header HD and footer FT are set is cleared to "0". As a result, the normal return command for communication is set in the transmission standby buffer 175 .

As already explained, the main side CPU 63 also transmits commands for communication to the sound and light side CPU 93 other than the communication variation command and the normal return command for communication. The number of data frames FRm included in the communication command is any one of "1" to "12". When the number of data frames FRm included in the command for communication is a multiple of "7", the number of data frames FRm included in the command for communication is divided by "7". The most significant frame SFp of the quotient is set in the communication command. Further, when the number of data frames FRm included in the command for communication is not a multiple of "7", the number of data frames FRm included in the command for communication is divided by "7". The most significant frame SFp, which is "1" larger than the number of quotients in the case, is set in the command for this communication. As a result, after the communication command is received, the information set in the most significant bit in all the data frames FRm included in the communication command can be set in the most significant frame SFp.

Next, a case where the sound/light receiving circuit 96 receives a command for communication (variation command for communication and normal return command for communication) will be described.

The communication command received by the sound/light receiving circuit 96 from the main CPU 63 is stored in the standby buffer 178 after the reception. As shown in FIG. 61, the sound and light side RAM 95 has a pre-conversion area 184 in which communication commands are stored, and a post-conversion area 184 for converting the communication commands stored in the pre-conversion area 184 into post-conversion commands. An area 185 is provided. The pre-conversion area 184 is a 14-byte storage area, and the post-conversion area 185 is a 12-byte storage area. As already explained, the maximum data capacity of the communication command received by the sound and light receiving circuit 96 from the first transmitting circuit 101 is 14 bytes. Also, the maximum data capacity of the converted command is 12 bytes. The sound and light side CPU 93 sets the communication command stored in the post-reception waiting buffer 178 in the pre-conversion area 184 and converts the communication command into the post-conversion command in the post-conversion area 185 . Then, the converted command is stored in the command storage buffer 179 . As a result, the post-conversion command can be used by the sound and light side CPU 93 .

FIG. 67(a) is an explanatory diagram for explaining the conversion mode of the communication variation command, and FIG. 67(b) is an explanatory diagram for explaining the conversion mode of the normal return command for communication. As shown in FIGS. 67A and 67B, the pre-conversion area 184 includes first to fourteenth areas RA1 to RA14, and the post-conversion area 185 includes first to twelfth areas RB1 to RB12. is provided. These areas RA1 to RA14 and RB1 to RB12 are storage areas of 1 byte.

When the data amount of the command stored in the post-reception standby buffer 178 is 2 bytes, that is, when the command stored in the post-reception standby buffer 178 is composed only of the header HD and the footer FT, the sound and light side CPU 93 If so, the command is stored in the command storage buffer 179 without conversion. On the other hand, when the data amount of the command stored in the post-reception waiting buffer 178 is 3 bytes or more, the sound and light side CPU 93 stores one or more data frames FRm in the command stored in the post-reception waiting buffer 178. is included, the command is converted into a post-conversion command in the post-conversion area 185 .

As shown in FIG. 67(a), in the conversion of the communication variation command, the header HD included in the communication variation command set in the pre-conversion area 184, the first and second data frames FR1, and the . . FR2, first most significant frame SF1 and footer FT, header HD excluding first most significant frame SF1, first and second data frames FR1 and FR2 and footer FT are loaded into area 185 after conversion. The header HD stored in the first area RA1 of the pre-conversion area 184 is loaded into the first area RB1 of the post-conversion area 185, and the header HD stored in the second to third areas RA2 to RA3 of the pre-conversion area 184 is loaded. The first and second data frames FR1 and FR2 are loaded into the second and third areas RB2 and RB3 of the post-conversion area 185, and the footer FT stored in the fifth area RA5 of the pre-conversion area 184 is loaded into the post-conversion area 185. It is loaded into the fourth area RB4.

After that, the "0" or "1" information stored in the s-th bit (s is an integer of 0 to 1) of the first most significant frame SF1 included in the communication variation command is changed to the (s+1)-th bit. ) is set in the most significant bit (7th bit) of the data frame FR(s+1). As a result, the post-conversion variation command is stored in the post-conversion area 185 . The sound and light side CPU 93 stores the post-conversion variation command stored in the post-conversion area 185 in the command storage buffer 179 . As a result, the post-conversion variation command can be used by the sound and light side CPU 93 .

As shown in FIG. 67(b), in the conversion of the normal return command for communication, the header HD included in the normal return command for communication set in the pre-conversion area 184, the first to tenth data frames FR1, and the to FR10, the first highest-level frame SF1, the second highest-level frame SF2, and the header HD excluding the first highest-level frame SF1 and the second highest-level frame SF2 among the footer FT, the first to tenth data frames FR1 to FR10, and The data of the footer FT are loaded into the after conversion area 185 . The header HD stored in the first area RA1 of the pre-conversion area 184 is loaded into the first area RB1 of the post-conversion area 185, and the header HD stored in the second to eighth areas RA2 to RA8 of the pre-conversion area 184 is loaded. The 1st to 7th data frames FR1 to FR7 are loaded into the 2nd to 8th areas RB2 to RB8 of the post-conversion area 185, and the 8th to 8th data frames stored in the 10th to 12th areas RA10 to RA12 of the pre-conversion area 184 are loaded. The tenth data frames FR8 to FR10 are loaded into the ninth to eleventh areas RB9 to RB11 of the post-conversion area 185, and the footer FT stored in the fourteenth area RA14 of the pre-conversion area 184 is loaded into the twelfth area of the post-conversion area 185. It is loaded into area RB12.

After that, the "0" or "1" information stored in the s-th bit (s is an integer from 0 to 6) of the first most significant frame SF1 included in the normal return command for communication is changed to the (s+1)-th bit. ) is set to the most significant bit (seventh bit) of the data frame FR(s+1), and the t-th bit (t is between 0 and 2) of the second most significant frame SF2 included in the normal return command for communication. Integer) is set to the most significant bit (7th bit) of the (t+8)th data frame FR(t+8). As a result, the post-conversion normal return command is stored in the post-conversion area 185 . The sound and light side CPU 93 stores the post-conversion normal return command stored in the post-conversion area 185 in the command storage buffer 179 . As a result, the post-conversion normal return command can be used by the sound and light side CPU 93 .

As shown in FIG. 61, the sound and light side RAM 95 is provided with a first most significant counter 188 and a second most significant counter 189 . The first most significant counter 188 is a counter that enables the sound and light side CPU 93 to grasp the area RAn (n is any integer from 3 to 9) in which the first most significant frame SF1 is stored in the pre-conversion area 184. At the same time, the second most significant counter 189 causes the sound and light side CPU 93 to grasp the area RAm (m is any integer from 11 to 13) in which the second most significant frame SF2 is stored in the pre-conversion area 184. It is a counter that allows The first most significant counter 188 and the second most significant counter 189 consist of one byte. In the pre-conversion area 184, the first most significant frame SF1 is stored in one of the third area RA3 to the ninth area RA9. In the first most significant counter 188, numerical information of any one of "3" to "9" corresponding to the area RAn in which the first most significant frame SF1 is stored in the pre-conversion area 184 is set. In the pre-conversion area 184, the second most significant frame SF2 is stored in one of the 11th area RA11 to the 13th area RA13. In the second most significant counter 189, numerical information of any one of "11" to "13" corresponding to the area RAm in which the second most significant frame SF2 is stored in the pre-conversion area 184 is set. If the communication command stored in the pre-conversion area 184 is 10 bytes or less, that is, if the communication command does not include the second most significant frame SF2, the second most significant frame SF2 contains " 0” is set. The sound and light side CPU 93 can grasp the position of the first most significant frame SF1 in the pre-conversion area 184 based on the value of the first most significant counter 188 . Further, based on the value of the second most significant counter 189, the sound and light side CPU 93 grasps whether or not the communication command stored in the pre-conversion area 184 includes the second most significant frame SF2. In addition, the position of the second most significant frame SF2 in the pre-conversion area 184 can be grasped.

Next, variation command transmission processing executed by the main CPU 63 will be described with reference to the flowchart of FIG. 68(a). Variation command transmission processing is executed in step S1014 of special figure variation start processing (FIG. 35). The variation command transmission process is executed using a specific control program and specific control data.

In the variation command transmission process, first, the first save area 182 in the specific control work area 121 is cleared to "0" (step S2001). Thereafter, in step S2004, which will be described later, the 0th bit is set as a data destination bit (step S2002). In this variation command transmission process (FIG. 68(a)), the information of the destination bit is set in the W register 104a. In step S2002, the W register 104a is cleared to "0".

Thereafter, "9430H", which is the start address of the variation command generation table 64u (FIG. 68(b)) stored in the main ROM 64, is set in the HL register 107 (step S2003). The variation command generation table 64u is a data table that enables the main CPU 63 to grasp the data to be set in the variation command for communication.

FIG. 68(b) is an explanatory diagram for explaining the data structure of the variation command generation table 64u. As shown in FIG. 68(b), the variation command generation table 64u is set to addresses "9430H" to "9435H" in the main ROM 64. As shown in FIG. The address of the lower area of the display continuation time counter 142 in the work area 121 for specific control is set to the addresses of "9430H" and "9431H" which are the start addresses of the variation command generation table 64u, and "9432H" is set. And the address of the upper area of the display duration counter 142 is set to the address of "9433H". Also, "00H" is set as end data at the address "9434H", and command identification data of the variation command is set at the address "9435H". As already explained, "1" is set to the most significant bit (seventh bit) of the command identification data of the variation command.

In the variation command transmission process (FIG. 68(a)), the HL register 107 is set with the address of the source area. The source area is the area from which data is to be moved in step S2004, which will be described later. By setting "9430H" in the HL register 107 in step S2003, the lower area of the display duration counter 142 is set as the movement source area.

After performing the processing of step S2003, the processing of steps S2004 to S2007 is performed in the state where the value of the W register 104a is "0", ie, the 0th bit is set as the destination bit. Specifically, first, the data "0" or "1" stored in the most significant bit (seventh bit) in the lower area of the display duration counter 142, which is the movement source area, is transferred to the first save area 182. The destination bit is loaded (step S2004). As already explained, the 0th bit is set as the destination bit in step S2002. Therefore, in step S2004, the data stored in the most significant bit in the lower area of the display duration counter 142 is loaded into the 0th bit of the first save area 182. FIG.

Thereafter, 2 is added to the value of the HL register 107 to make it "9432H" (step S2005). As already explained, addresses in the upper area of the display duration counter 142 are set in "9432H" and "9433H" of the variation command generation table 64u (FIG. 68(b)). By updating the value of the HL register 107 to “9432H”, the movement source area is updated to the upper area of the display duration counter 142 .

Thereafter, it is determined whether end data (“00H”) is set in the area corresponding to the address stored in the HL register 107 (step S2006). As described above, the value of the HL register 107 is "9432H", and the end data is not set in the area corresponding to "9432H". (step S2007). In step S2007, 1 is added to the value of the W register 104a to make it "1".

Thereafter, while the value of the W register 104a is "1", that is, while the first bit is set as the destination bit, steps S2004 to S2006 are performed. Specifically, first, the data "0" or "1" stored in the most significant bit (seventh bit) in the upper area of the display duration counter 142, which is the movement source area, is transferred to the first save area 182. The destination bit is loaded (step S2004). As already explained, the destination bit is updated to the first bit in step S2007. Therefore, the data stored in the most significant bit in the upper area of the display duration counter 142 is loaded into the first bit of the first save area 182 .

After that, 2 is added to the value of the HL register 107 to set it to "9434H" (step S2005), and it is determined whether end data ("00H") is set in the area corresponding to the address stored in the HL register 107. is determined (step S2006). As already explained, end data is set in "9434H" of the variation command generation table 64u (FIG. 68(b)), so an affirmative determination is made in step S2006, and variation command setting processing is executed. Then (step S2008), the variation command transmission process ends.

Next, the variation command setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The variation command setting process is executed in step S2008 of the variation command transmission process (FIG. 68(a)). Note that the variation command setting process is executed using a program for specific control and data for specific control.

In the variation command setting process, the value of the write pointer 186 corresponding to the transmission standby buffer 175 is stored in the head storage area provided in the work area 121 for specific control (step S2101). The leading storage area is a storage area that allows the main CPU 63 to grasp the leading area of the area in which the current command is set in the transmission standby buffer 175 . The head storage area consists of 2 bytes. By storing the value of the write pointer 186 in step S2101, it becomes possible to grasp the area in which the current command is set in the transmission standby buffer 175 in step S2113, which will be described later. It is possible to grasp the total number of "1"s that are present.

After that, 1 is added to the value of the HL register 107 to update the address stored in the HL register 107 from "9434H" to "9435H" (step S2102). As already explained, the command identification data of the variation command is set in the area corresponding to "9435H" in the variation command generation table 64u (FIG. 68(b)). After that, the command identification data is set in the area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2103). As already explained, the most significant bit (seventh bit) of the command identification data is set to "1" as the header identification bit. As a result, the sound/light receiving circuit 96 can distinguish between the header HD and the frame other than the header HD.

After that, by adding 2 to the value of the write pointer 186, the setting destination area in the transmission standby buffer 175 is updated (step S2104). Thereafter, "9430H", which is the start address of the variation command generation table 64u (FIG. 68(b)), is set in the HL register 107 (step S2105), and the process proceeds to step S2106. As already explained, the addresses of the lower area of the display duration counter 142 are stored in "9430H" and "9431H" of the variation command generation table 64u.

The processing of steps S2106 to S2110 is repeated twice until an affirmative determination is made in step S2110. In the first step S2106, which is executed while the address of the lower area of the display duration counter 142 is stored in the HL register 107, the data stored in the lower area of the display duration counter 142 is sent to the transmission standby buffer. In 175, the setting destination area corresponding to the value of the write pointer 186 is set (step S2106), and the most significant bit (seventh bit) of the setting destination area is cleared to "0" (step S2107).

After that, by adding 2 to the value of the write pointer 186, the setting destination area in the transmission standby buffer 175 is updated (step S2108). After that, 2 is added to the value of the HL register 107 to update the address stored in the HL register 107 to "9432H" (step S2109). As already explained, in the variation command generation table 64u (FIG. 68(b)), the addresses of the upper area of the display continuation time counter 142 are stored in the addresses of "9432H" and "9433H".

Thereafter, it is determined whether end data (“00H”) is set in the area corresponding to the address stored in the HL register 107 in the variation command generation table 64u (step S2110). Since the high-order 1 byte of the display duration data is set in the area and the end data is not set, a negative determination is made in step S2110, and the process proceeds to step S2106.

In the second step S2106, which is executed while the address of the upper area of the display duration counter 142 is stored in the area corresponding to the value of the HL register 107, the address is stored in the upper area of the display duration counter 142. data is set in the setting destination area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2106), and the highest bit (seventh bit) of the setting destination area is cleared to "0" (step S2107). .

After that, by adding 2 to the value of the write pointer 186, the setting destination area in the transmission standby buffer 175 is updated (step S2108). After that, 2 is added to the value of the HL register 107 to update the address stored in the HL register 107 to "9434H" (step S2109). As already explained, the end data ("00H") is stored at the address "9434H" in the variation command generation table 64u (FIG. 68(b)). Thereafter, an affirmative determination is made in step S2110 to determine whether end data is set in the area corresponding to the value of the HL register 107, and the process proceeds to step S2111.

In step S2111, the data stored in the first save area 182 in the specific control work area 121 is set in the setting destination area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2111). Thereafter, the value of the write pointer 186 is incremented by 2 to update the setting destination area (step S2112), and the footer identification data stored in the main ROM 64 is set in the updated setting destination area (step S2113). , to end this variation command setting process. In step S2113, a footer FT is set after the first most significant frame SF1. Also, in step S2113, it is determined whether or not the total number of "1"s among the "0" and "1" data contained in the communication variation command stored in the transmission standby buffer 175 is an even number. If the total number of "1" contained in the communication variation command is not an even number, the error detection bit of the footer FT is set to "1". The main CPU 63 sets a variable command for communication in the transmission standby buffer 175 based on the value of the first write pointer 186 stored in the head storage area in step S2101 and the current value of the write pointer 186. Know where you are. On the other hand, when the total number of "1"s included in the communication variation command is an even number, the error detection bit of the footer FT is kept set to "0". By setting the total number of "1"s included in the variation command for communication to be an even number, it is possible to detect the occurrence of a communication error in the sound/light receiving circuit 96. FIG.

Next, the return command transmission process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The return command transmission process is executed in step S113 of the main process (FIG. 15). The return command transmission process is executed using a program for specific control and data for specific control.

In the return command transmission process, first, the first save area 182 and the second save area 183 in the work area 121 for specific control are cleared to "0" (step S2201). After that, in step S2207 which will be described later, the 0th bit is set as a destination bit to which data is to be moved (step S2202). In this variation command transmission process (FIG. 70), the information of the destination bit is set in the W register 104a. In step S2202, the W register 104a is cleared to "0".

After that, it is determined whether or not the partial clear flag in the work area 121 for specific control is set to "1" (step S2203). As already described, the partial clear flag is set to "1" in step S108 when the partial clear process (step S107) is executed in the main process (FIG. 15). If the partial clear flag is set to "1" (step S2203: YES), the partial clear return command transmission process is executed (step S2204), and the return command transmission process ends. In the partial clear return command transmission process (step S2204), when the partial clear includes the data in the header HD, the data stored in the set value counter in the work area 121 for specific control, and the data in the footer FT, to the sound and light side CPU 93. A header HD, a first data frame FR1, a first most significant frame SF1, and a footer FT are set in the return command at the time of partial clearing for communication. The header HD contains the command identification data of the return command for partial clearing. Data of the 0th to 6th bits of the set value counter in the work area 121 for specific control are set in the first data frame FR1. The 0th bit of the first most significant frame SF1 is set to "0" which is the data of the most significant bit (seventh bit) of the set value counter. By receiving the return command at the time of partial clearing, the sound and light side CPU 93 grasps that the partial clearing process (step S107) has been executed in the main process (FIG. 15), and the current status of the pachinko machine 10 Know your settings.

If a negative determination is made in step S2203, "9450H", which is the start address of the normal return command generation table 64v (FIG. 71) stored in the main ROM 64, is set in the HL register 107 (step S2205). . The normal return command generation table 64v is a data table that enables the main CPU 63 to grasp data to be set in the normal return command for communication.

FIG. 71 is an explanatory diagram for explaining the data configuration of the normal return command generation table 64v. As shown in FIG. 71, the normal return command generation table 64v is set to addresses “9450H” to “9466H” in the main ROM 64 . The addresses of the set value counter in the work area 121 for specific control are set to the addresses of "9450H" and "9451H" which are the start addresses of the normal return command generation table 64v, and the addresses of "9452H" and "9453H" are set. The address of the first special figure reservation number counter 118 in the work area 121 for specific control is set, and the addresses of "9454H" and "9455H" are the second special figure reservation in the work area 121 for specific control The addresses of the number counter 119 are set, the addresses of the mode data area in the work area 121 for specific control are set to the addresses of "9456H" and "9457H", and the addresses of "9458H" and "9459H" are set. is set with the address of the round counter in the work area 121 for specific control, and the addresses of the pass/fail data area 158 in the work area 121 for specific control are set at the addresses of "945AH" and "945BH". , "945CH" and "945DH" are set with the addresses of the distribution data area 162 in the work area 121 for specific control. "0001H" is stored at the address "945EH" as the first end data. Addresses of "945FH" and "9460H" are set to the addresses of the game areas in the work area 121 for specific control, and addresses of "9461H" and "9462H" are set to the addresses of the special game areas in the work area 121 for specific control. The addresses of the lower area of the special electric timer counter are set, and the addresses of the upper area of the special electric timer counter in the work area 121 for specific control are set to the addresses "9463H" and "9464H". "0002H" is stored as the second end data at the address "9465H", and the command identification data of the normal return command is stored at the address "9466H".

In the normal return command transmission process (FIG. 70), the HL register 107 is set with the address of the source area from which data is to be moved in step S2207, which will be described later. By setting "9450H" in the HL register 107 in step S2205, the set value counter is set as the movement source area.

Thereafter, in step S2207, which will be described later, the first save area 182 is set as a destination area to which data is to be moved (step S2206). The address of the destination area is stored in the DE register 106 in this return command transmission process (FIG. 70). In step S2206, the address of the first save area 182 is stored in the DE register 106. FIG.

After that, the address of the first save area 182 is stored in the DE register 106, that is, the first save area 182 is set as the destination area, and the value of the W register 104a is "0". In a certain state, that is, in a state where the 0th bit is set as the destination bit, the processing of steps S2207 to S2211 is performed. Specifically, first, the data stored in the set value counter currently set as the movement source area grasped based on the address stored in the HL register 107 is transferred to the first save area as the movement destination area. The 0th bit, which is the destination bit of 182, is loaded (step S2207).

After that, 2 is added to the value of the HL register 107 to update it to "9452H" (step S2208). As already explained, the address of the first special figure pending number counter 118 is set to "9452H" and "9453H" of the normal return command generation table 64v (Fig. 71). By updating the value of the HL register 107 to "9452H", the first special figure reservation number counter 118 is set as the source area.

After that, it is determined whether or not the second end data (“0002H”) is set in the movement source area grasped based on the address stored in the HL register 107 (step S2209). As described above, the value of the HL register 107 is "9452H", and the second end data is not set in the area corresponding to "9452H".

In step S2210, it is determined whether or not the first end data ("0001H") is set in the source area (step S2211). As described above, the value of the HL register 107 is "9452H", and the first end data is not set in the area corresponding to "9452H".

In step S2211, 1 is added to the value of the W register 104a to update it to "1". As a result, the destination bit is updated to the first bit. After that, the process proceeds to step S2207. The address of the first save area 182 is stored in the DE register 106, that is, the first save area 182 is set as the data destination area, and the value of the W register 104a is "1". , that is, in a state in which the first bit is set as the destination bit, the processing of steps S2207 to S2211 is performed.

As described above, the processing of steps S2207 to S2211 is executed in a state in which the 0th bit of the first save area 182 is set as the data destination and the set value counter is set as the destination area. As a result, the most significant bit (seventh bit) data in the set value counter is loaded into the zeroth bit of the first save area 182 . In addition, the movement destination of the data is updated to the first bit of the first evacuation area 182, and the movement source area is updated to the first special figure reservation number counter 118. The processing of steps S2207 to S2211 is repeated seven times until an affirmative determination is made in step S2210. Every time the process of step S2207 ~ step S2211 is executed, the movement source area is set value counter → 1st special figure reservation number counter 118 → 2nd special figure reservation number counter 119 → mode data area → round counter → success or failure data area 158→distribution data area 162, and the data is moved to the 0th bit→1st bit→2nd bit→3rd bit→4th bit→5th bit→in the first save area 182. It is updated in the order of the 6th bit. As a result, the most significant bit (seventh bit) data in these counters and areas can be set to the corresponding bit in the first save area 182 . Specifically, the most significant bit of the set value counter is set to the 0th bit, the most significant bit of the first special figure reservation number counter 118 is set to the first bit, and the second special figure reservation number counter 119 The most significant bit of the mode data area is set to the third bit, the most significant bit of the round counter is set to the fourth bit, and the most significant bit of the success/failure data area 158 is set to the fifth bit. bit, and the most significant bit of the distribution data area 162 is set to the sixth bit.

When the process of step S2208 is performed with "945CH" stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "945EH". As already explained, the first termination data (“0001H”) is set in the area corresponding to “945EH” in the normal return command generation table 64v (FIG. 71). Therefore, a negative determination is made in step S2209 and an affirmative determination is made in step S2210, and the process proceeds to step S2212.

In step S2212, the destination area is updated to the second save area 183 by setting the address of the second save area 183 in the work area 121 for specific control in the DE register . After that, the value of the W register 104a is cleared to "0" to set the 0th bit as the destination bit (step S2213). As a result, the 0th bit of the second save area 183 is set as the data destination.

After that, 1 is added to the value of the HL register 107 to update it to "945FH" (step S2214). As already explained, the address of the game area is set in the area corresponding to "945FH" in the normal return command generation table 64v (FIG. 71), and the game area is set as the movement source area. Become. After that, in a state where the game play area is set as the movement source area and the 0th bit of the second save area 183 is set as the data movement destination, the process proceeds to step S2207.

The processing of steps S2207 to S2211 is repeated three times until an affirmative determination is made in step S2209. Every time the processing of steps S2207 to S2211 is executed, based on the normal return command generation table 64v (FIG. 71), the movement source area is the game round area → the lower area of the special special electric timer counter → the special special electric timer counter , and the data destination is updated in the order of the 0th bit→the 1st bit→the 2nd bit in the second save area 183 . As a result, the most significant bit (seventh bit) data in these counters and areas can be set to the corresponding bit in the second save area 183 . Specifically, the most significant bit of the game area is set to the 0th bit, the most significant bit of the lower area of the special special electric timer counter is set to the first bit, and the highest area of the special special electric timer counter is set. The upper bit is set to the second bit.

When the process of step S2208 is performed with "9463H" stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "9465H". As already explained, the second termination data (“0002H”) is set in the area corresponding to “9465H” in the normal return command generation table 64v (FIG. 71). Therefore, an affirmative determination is made in step S2209, and the process proceeds to step S2215. In step S2215, normal return command setting processing is executed to set a normal return command for communication in the transmission standby buffer 175, and this return command transmission processing ends.

Next, the normal return command setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The normal return command setting process is executed in step S2215 of the normal return command transmission process (FIG. 70). The normal return command setting process is executed using a program for specific control and data for specific control.

In the normal return command setting process, first, the value of the write pointer 186 corresponding to the transmission standby buffer 175 is stored in the head storage area of the work area 121 for specific control (step S2301). As a result, in step S2317 to be described later, it is possible for the main CPU 63 to grasp the area in which the normal return command for communication is set in the transmission standby buffer 175 .

After that, 1 is added to the value of the HL register 107 (step S2302). As already described, "9465H" is stored in the HL register 107 at step S2208 of the return command transmission process (FIG. 70). In step S2302, the address stored in the HL register 107 is updated to "9466H". As already explained, the command identification data of the normal return command is set in the area corresponding to "9466H" in the normal return command generation table 64v (FIG. 71). After that, the command identification data is set in the setting destination area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2303). As already explained, the most significant bit (seventh bit) of the command identification data is set to "1" as the header identification bit. As a result, the sound/light receiving circuit 96 can distinguish between the header HD and the frame other than the header HD.

After that, by adding 2 to the value of the write pointer 186, the setting destination area in the transmission standby buffer 175 is updated to the next area (step S2304). Thereafter, "9450H", which is the start address of the normal return command generation table 64v (FIG. 71), is set in the HL register 107 (step S2305), and the process proceeds to step S2306. As already described, "9450H" and "9451H" of the normal return command generation table 64v store the addresses of the set value counters in the work area 121 for specific control. By setting "9450H" in the HL register 107, the set value counter is set as the movement source area.

The processing of steps S2306 to S2311 is repeated seven times until an affirmative determination is made in step S2311. In the first step S2306, which is executed while the set value counter is set as the source area, the data stored in the set value counter, which is the source area, is written to the value of the write pointer 186 in the transmission standby buffer 175. The corresponding setting destination area is set (step S2306), and the most significant bit (seventh bit) of the setting destination area is cleared to "0" (step S2307).

After that, by adding 2 to the value of the write pointer 186, the setting destination area in the transmission standby buffer 175 is updated to the next area (step S2308). After that, 2 is added to the value of the HL register 107 to update the address stored in the HL register 107 to "9452H" (step S2309). As already explained, the address of the first special figure pending number counter 118 is stored in the addresses of "9452H" and "9453H" in the normal return command generation table 64v (Fig. 71). As a result, the first special figure reservation number counter 118 is set as the movement source area.

After that, it is determined whether or not the second termination data (specifically, "0002H") is set in the area corresponding to the address stored in the HL register 107 in the normal return command generation table 64v (step S2310). ). As described above, since the second end data is not set to "9452H", a negative determination is made in step S2310, and the process proceeds to step S2311. In step S2311, it is determined whether or not the first termination data (specifically, "0001H") is set in the area corresponding to the address stored in the HL register 107 in the normal return command generation table 64v. As described above, since the first end data is not set to "9452H", a negative determination is made in step S2311, and the process proceeds to step S2306.

The processing of steps S2306 to S2311 is repeated seven times until an affirmative determination is made in step S2311. In the first step S2306, which is executed while the set value counter is set as the source area, the data stored in the set value counter, which is the source area, is written to the value of the write pointer 186 in the transmission standby buffer 175. The corresponding setting destination area is set (step S2306), and the most significant bit (seventh bit) of the setting destination area is cleared to "0" (step S2307).

As described above, by executing the processing of steps S2306 to S2311 with the set value counter set as the movement source area, the data stored in the set value counter is transferred to the setting destination area of the transmission standby buffer 175. , and the most significant bit in the setting destination area is cleared to "0". In addition, the moving source area is updated to the first special figure reservation number counter 118, and the setting destination area in the transmission waiting buffer 175 is updated to the next area. As described above, the processing of steps S2306 to S2311 is repeated seven times until an affirmative determination is made in step S2311. Every time the process of step S2306 ~ step S2311 is executed, based on the normal return command generation table 64v (Fig. 71), the movement source area is set value counter → first special figure reservation number counter 118 → second special figure reservation The data are updated in the order of number counter 119→mode data area→round counter→win/fail data area 158→distribution data area 162, and the setting destination areas in the transmission standby buffer 175 are updated in order. As a result, the data stored in the 0th to 6th bits of these counters and areas can be set in the transmission standby buffer 175 .

When the process of step S2309 is performed with "945CH" stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "945EH". As already explained, the first termination data (“0001H”) is set in the area corresponding to “945EH” in the normal return command generation table 64v (FIG. 71). Therefore, an affirmative determination is made in step S2311, and the process proceeds to step S2312.

In step S2312, the data stored in the first save area 182 in the specific control work area 121 is set in the area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2312). As a result, the first most significant frame SF1 can be set after the seventh data frame FR7.

After that, the value of the write pointer 186 is incremented by 1, and the setting destination area in the transmission standby buffer 175 is updated to the next area (step S2313). After that, 1 is added to the value of the HL register 107 to update it to "945FH" (step S2314). As already explained, in the normal return command generation table 64v (Fig. 71), the address of the game area in the work area 121 for specific control is stored at the address "945FH". By updating the address stored in the HL register 107 to "945FH", the game area is set as the movement source area. Thereafter, the process proceeds to step S2306, and the processes of steps S2306 to S2311 are repeatedly executed until an affirmative determination is made in step S2310. The processing from step S2306 to step S2311 is executed three times.

By executing the processing of steps S2306 to S2311 while the game area is set as the movement source area, the data stored in the game area is set in the setting destination area of the transmission standby buffer 175. At the same time, the most significant bit in the setting destination area is cleared to "0". Also, the source area is updated to the lower area of the special special electric timer counter, and the setting destination area in the transmission standby buffer 175 is updated to the next area. Every time the processing of steps S2306 to S2311 is executed, based on the normal return command generation table 64v (FIG. 71), the movement source area is the game round area → the lower area of the special electric timer counter → the upper area of the special electric timer counter. Areas are updated in order, and setting destination areas in the transmission standby buffer 175 are updated in order. As a result, the data stored in the 0th to 6th bits of these counters and areas can be set in the transmission standby buffer 175 .

When the process of step S2309 is performed with "9463H" stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "9465H". As already explained, the second termination data (“0002H”) is set in the area corresponding to “9465H” in the normal return command generation table 64v (FIG. 71). Therefore, an affirmative determination is made in step S2310, and the process proceeds to step S2315.

In step S2315, the data stored in the second save area 183 in the specific control work area 121 is set in the area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2315). As a result, the second most significant frame SF2 can be set after the tenth data frame FR10.

After that, 1 is added to the value of the write pointer 186, and the setting destination area in the transmission standby buffer 175 is updated to the next area (step S2316). After that, the footer identification data stored in the main-side ROM 64 is set in the setting destination area in the transmission standby buffer 175 (step S2317), and this normal return command setting process is terminated. In step S2317, a footer FT is set after the second top frame SF2. Further, in step S2317, it is determined whether or not the total number of "1"s among the "0" and "1" data contained in the communication normal return command stored in the transmission standby buffer 175 is an even number. If the total number of "1" contained in the normal return command for communication is not an even number, "1" is set in the error detection bit of the footer FT. The main CPU 63 sets the normal return command for communication in the transmission standby buffer 175 based on the value of the first write pointer 186 stored in the head storage area in step S2301 and the current value of the write pointer 186. Know where you are. On the other hand, if the total number of "1"s contained in the normal return command for communication is an even number, the error detection bit of the footer FT remains set to "0". By setting the total number of "1"s included in the normal return command for communication to an even number, it is possible to detect the occurrence of a communication error in the sound/light receiving circuit 96. FIG.

Next, the command reception handling process executed by the sound/light side CPU 93 will be described with reference to the flow chart of FIG. The command reception processing is periodically executed in the sound and light side CPU 93 at a cycle of 4 milliseconds.

In the command reception processing, first, it is determined whether or not the header HD is stored in the post-reception standby buffer 178 of the sound and light receiving circuit 96 (step S2401). In step S2401, it is determined whether or not there is an area in the post-reception waiting buffer 178 in which "1" is set to the most significant bit (seventh bit). Affirmative determination is made when the area where the object exists exists. If a negative determination is made in step S2401, this command reception handling process is terminated.

If an affirmative determination is made in step S2401, it is determined whether or not the footer FT is stored in the post-reception waiting buffer 178 (step S2402). In step S2402, it is determined whether or not an area in which footer identification data is set exists in the waiting buffer 178 after reception. . If a negative determination is made in step S2402, this command reception handling process is terminated. If only the header HD is stored in the post-reception waiting buffer 178 and the footer FT is not stored (step S2401: YES, step S2402: NO), that is, if command reception has not been completed, step S2403 and subsequent steps are performed. is not executed.

If an affirmative determination is made in step S2402, that is, if the command is stored in the standby buffer 178 after reception, there is an empty area in the command storage buffer 179 in the sound and light side RAM 95 that can store the command. It is determined whether or not there is (step S2403). If there is an empty area in the command storage buffer 179 in which the command can be stored (step S2403: YES), it is determined whether or not the data amount of the command stored in the post-reception waiting buffer 178 is 3 bytes or more. (step S2404).

If the data amount of the command stored in the post-reception standby buffer 178 is 3 bytes or more (step S2404: YES), that is, the command stored in the post-reception standby buffer 178 includes one or more data frames FRm. If the command is for communication, the pre-conversion area 184 and the post-conversion area 185 in the sound and light side RAM 95 are cleared to "0" (step S2405), and the first highest counter 188 and the second highest counter 188 in the sound and light side RAM 95 are cleared. The upper counter 189 is cleared to "0" (step S2406). As already explained, the first most significant counter 188 causes the sound and light side CPU 93 to store the area RAn (n is any integer from 3 to 9) in which the first most significant frame SF1 is stored in the pre-conversion area 184. The second most significant counter 189 is a counter that makes it possible to grasp the area RAm (m is any integer from 11 to 13) in which the second most significant frame SF2 is stored in the pre-conversion area 184. This is a counter that can be grasped by the side CPU 93 .

After that, the command for communication stored in the waiting buffer 178 after reception is read to the pre-conversion area 184 (step S2407). In step S2407, if the number of bytes of the communication command stored in the post-reception standby buffer 178 is "n+3" (n is any integer from 1 to 7), the first area RA1 of the pre-conversion area 184 is In the (n+3)th area RA(n+3), frames are set in the order of header HD→first data frame FR1 through nth data frame FRn→first most significant frame SF1→footer FT. In step S2407, if the number of bytes of the communication command stored in post-reception standby buffer 178 is “m+4” (m is any integer from 8 to 10), the first From area RA1 to (m+4)th area RA(m+4), header HD→first to seventh data frames FR1 to FR7→first most significant frame SF1→eighth data frame FR8 to mth data frame FRm→second most significant frame. The frames are set in the order of upper frame SF2→footer FT. After that, first command conversion processing is executed (step S2408). In the first command conversion process, the command for communication stored in the pre-conversion area 184 is converted into the post-conversion command in the post-conversion area 185 . Details of the first command conversion process will be described later.

If a negative determination is made in step S2404, or if the process of step S2408 is executed, the write destination is grasped based on the value of the write pointer 187 of the command storage buffer 179 provided in the sound and light side RAM 95 ( Step S2409), command write processing is executed (step S2410). The write pointer 187 is a pointer that enables the sound and light side CPU 93 to grasp the write destination of the command in the command storage buffer 179 . If no command is stored in post-conversion area 185, that is, if the command stored in post-reception standby buffer 178 is a 2-byte command, then in step S2410, the 2-byte command stored in post-reception standby buffer 178 is replaced. command is stored in the command storage buffer 179 . If a command is stored in post-conversion area 185, that is, if the command stored in post-reception standby buffer 178 is a command for communication, then in step S2410 the conversion stored in post-conversion area 185 is processed. The post-command is stored in the command storage buffer 179 .

After that, the write pointer 187 of the command storage buffer 179 is updated (step S2411). In step S2411, a value corresponding to the number of bytes of the command written in the command storage buffer 179 in step S2410 is added to the value of the write pointer 187. When the maximum value is exceeded, the value obtained by subtracting “1” from the maximum value is subtracted from the value of the write pointer 187 . This enables the sound and light side CPU 93 to grasp the next write destination in the command storage buffer 179 .

After that, the post-reception waiting buffer 178 is cleared (step S2412). In the clear processing, the area in which the command was stored in the standby buffer 178 after reception is cleared to "0". Thereafter, it is determined whether or not the header HD is stored in the post-reception standby buffer 178 after the post-reception standby buffer 178 has been cleared in step S2412 (step S2413), and if the header HD is not stored. If (step S2413: NO), the command reception handling process is terminated.

If an affirmative determination is made in step S2413, it is determined whether or not the footer FT is stored in the post-reception waiting buffer 178 (step S2414), and if the footer FT is not stored (step S2414: NO). , the command reception handling process is terminated as it is. On the other hand, if the header HD and footer FT are stored in the post-reception standby buffer 178 (step S2413: YES, step S2414: YES), that is, if another command is stored in the post-reception standby buffer 178, Returning to step S2403, the processing of steps S2403 to S2414 is executed for the command.

Next, the first command conversion processing executed by the sound/light side CPU 93 will be described with reference to the flowchart of FIG. The first command conversion process is executed in step S2408 of the command reception handling process (FIG. 73).

In the first command conversion process, the area RAn where the footer identification data is stored in the pre-conversion area 184 (n is any integer from 4 to 14) is identified, and the area RAn where the footer FT is stored is identified. is grasped (step S2501). Thereafter, based on the area RAn storing the footer FT ascertained in step S2501, it is determined whether or not the number of bytes of the communication command stored in the pre-conversion area 184 is 11 bytes or more ( step S2502). In step S2502, a negative determination is made if the footer FT is stored in any of the fourth to tenth areas RA4 to RA10, and if the footer FT is stored in any of the eleventh to fourteenth areas RA11 to RA14. Affirmative judgment is made if

If a negative determination is made in step S2502, that is, if only the first most significant frame SF1 is set in the command for communication, area RAn (where n is Any integer from 4 to 10) is set in the first most significant counter 188 in the sound and light side RAM 95 (step S2503). In step S2503, if the footer FT is set to the n-th area RAn, the first most significant counter 188 is set to "n-1". This allows the sound and light side CPU 93 to grasp the position of the first highest frame SF1 in the pre-conversion area 184 . Also, in step S2503, the state in which the value of the second most significant counter 189 is "0" is maintained. As a result, the sound and light CPU 93 can recognize that the communication command stored in the pre-conversion area 184 does not include the second most significant frame SF2.

On the other hand, if an affirmative determination is made in step S2502, that is, if the first most significant frame SF1 and the second most significant frame SF2 are set in the command for communication, the first most significant frame in the sound and light side RAM 95 "9" is set in the counter 188 (step S2504). As a result, the sound and light side CPU 93 can recognize that the first most significant frame SF1 is stored in the ninth area RA9 of the pre-conversion area 184. FIG. After that, the value corresponding to the area RA (m-1) immediately before the area RAm (m is any integer from 11 to 14) where the footer FT is stored in the pre-conversion area 184 is stored in the sound and light side RAM 95. It is set in the second most significant counter 189 (step S2505). In step S2505, if the footer FT is set in the m-th area RAm, the second most significant counter 189 is set to "m-1". This allows the sound and light side CPU 93 to grasp the position of the second highest frame SF2 in the pre-conversion area 184 .

When the processing of step S2503 or the processing of step S2505 is performed, a value corresponding to the number of bytes of the command stored in the pre-conversion area 184 is set to the movement number counter provided in the sound and light side RAM 95. (step S2506). The movement number counter counts the number of times the information stored in the pre-conversion area 184 is loaded into the post-conversion area 185 in order to convert the communication command stored in the pre-conversion area 184 into the post-conversion command. This is a counter that can be grasped by the side CPU 93 . In step S2506, the number of bytes of the communication command stored in pre-conversion area 184 is grasped based on the position of footer FT in pre-conversion area 184 grasped in step S2501. After that, the first area RA1 of the pre-conversion area 184 is set as the information movement source area in step S2509 described later (step S2507), and the first area RB1 of the post-conversion area 185 is set as the information movement destination area in step S2509 described later. is set (step S2508).

After that, the data stored in the source area (first area RA1) is loaded into the destination area (first area RB1) (step S2509). Thereafter, 1 is subtracted from the value of the number-of-moves counter (step S2510), and it is determined whether or not the value after the subtraction of 1 is "0" (step S2511). If a negative determination is made in step S2511, the source area is updated (step S2512). In step S2512, the source areas are updated in the order of the first area RA1→second area RA2→...→eighth area RA8→ninth area RA9 in the pre-conversion area 184. FIG. After that, the destination area is updated (step S2513). In step S2513, the destination areas are updated in the order of the first area RB1→second area RB2→...→eighth area RB8→ninth area RB9 in the area 185 after conversion.

Thereafter, it is determined whether or not the movement source area updated in step S2513 is the first most significant frame SF1 or the second most significant frame SF2 in the pre-conversion area 184 (step S2514). In step S2514, the position of the first most significant frame SF1 in the pre-conversion area 184 is grasped based on the value of the first most significant counter 188 in the sound and light side RAM 95. FIG. Also, based on the value of the second most significant counter 189 in the sound and light side RAM 95, the presence or absence of the second most significant frame SF2 in the pre-conversion area 184 and the position of the second most significant frame SF2 are grasped. Then, if the source area updated in step S2513 is the first most significant frame SF1, or if the source area is the second most significant frame SF2, an affirmative determination is made.

If an affirmative determination is made in step S2514, the source area is updated to the area next to the first most significant frame SF1 or second most significant frame SF2 in the pre-conversion area 184 (step S2515). In step S2515, if the movement source area is the first most significant frame SF1 of the pre-conversion area 184, the movement destination area is updated to the area next to the first most significant frame SF1, and the movement destination area is changed to the pre-conversion area. If it is the second most significant frame SF2 in the area 184, the source area is updated to the area next to the second most significant frame SF2. After that, 1 is subtracted from the value of the number-of-moves counter (step S2516).

If a negative determination is made in step S2514, or if the process of step S2516 is performed, the process returns to step S2509, and the processes of steps S2509 to S2516 are executed until an affirmative determination is made in step S2511. As a result, among the header HD, data frame FRm, top frames SF1 and SF2, and footer FT stored in the pre-conversion area 184, each data other than the top frames SF1 and SF2 is transferred to the corresponding area of the post-conversion area 185. can be loaded.

If an affirmative determination is made in step S2511, second command conversion processing is executed (step S2517), and the first command conversion processing ends. In the second command conversion process in step S2517, the information stored in the most significant frames SF1 and SF2 in the pre-conversion area 184 is loaded into the most significant bit (seventh bit) of the corresponding data frame FRm in the post-conversion area 185. . FIG. 75 is a flowchart showing second command conversion processing.

In the second command conversion process, first, a value corresponding to the number of bytes of the command stored in the pre-conversion area 184 of the sound and light side RAM 95 is set in the movement count counter of the sound and light side RAM 95 (step S2601). In step S2601, the area RAn (n is any integer from 4 to 14) in which the footer FT is stored in the pre-conversion area 184 is determined, and the value corresponding to the area RAn is set in the number-of-moves counter.

After that, "2" is subtracted from the movement number counter (step S2602). As a result, the number of frames included in the communication command stored in the pre-conversion area 184, excluding the header HD and footer FT, is set in the movement count counter.

Thereafter, it is determined whether or not the value of the second most significant counter 189 in the sound and light side RAM 95 is "0" (step S2603). As already explained, when the command for communication stored in the pre-conversion area 184 includes only the first most significant frame SF1, the value of the second most significant counter 189 in the sound and light side RAM 95 is "0". is. On the other hand, when the command for communication includes the first most significant frame SF1 and the second most significant frame SF2, the value of the second most significant counter 189 is any one of "11" to "13". If an affirmative determination is made in step S2603, that is, if only the first most significant frame SF1 is included in the communication command stored in the pre-conversion area 184, the movement count counter in the sound and light side RAM 95 is subtracted by 1 (step S2604). On the other hand, if a negative determination is made in step S2604, that is, if the communication commands stored in the pre-conversion area 184 include the first most significant frame SF1 and the second most significant frame SF2, 2 is subtracted from the value of the movement count counter in the sound and light side RAM 95 (step S2605). By executing the processing in step S2604 or step S2605, the data frame FRm excluding the header HD, footer FT, and top frame SFp (p is 1 or 2) in the communication command stored in the pre-conversion area 184 A value corresponding to the number can be set in the movement number counter.

When the processing of step S2604 or the processing of step S2605 is performed, the first most significant frame SF1 is stored in the pre-conversion area 184 based on the value of the first most significant counter 188 in the sound and light side RAM 95. The area RAn (n is any integer from 4 to 9) is grasped, and the area RAn is set as the source area of the information in step S2609, which will be described later (step S2606). After that, the 0th bit of the first most significant frame SF1 is set as the source bit of information in step S2609, which will be described later (step S2607). After that, the second area RB2 of the post-conversion area 185 is set as the destination area of information in step S2609, which will be described later (step S2608). As already described with reference to FIG. 67, the second area RB2 is an area in which the first data frame FR1 of the post-conversion command is set.

After that, the "0" or "1" information stored in the source bit of the source area is loaded into the most significant bit (seventh bit) of the destination area (step S2609), and the number of moves counter is decremented by 1. (step S2610). Thereafter, it is determined whether or not the value after subtracting 1 is "0" (step S2611), and if the value of the movement number counter is not "0" (step S2611: NO), Update (step S2612). In step S2612, the source bits are updated in the order of 0th bit→1st bit→...→7th bit→8th bit. After that, the destination area is updated (step S2613). In step S 2613 , the destination area is updated to the area next to the current destination area in the post-conversion area 185 .

Thereafter, it is determined whether or not the source bit updated in step S2612 is the eighth bit (step S2614). If the top frame SFp (p is 1 or 2) included in the communication command stored in the pre-conversion area 184 is only the first top frame SF1, an affirmative determination is made in step S2614. After the processing of steps S2609 to S2614 is repeated, an affirmative determination is made in step S2611. On the other hand, if the communication command stored in the pre-conversion area 184 includes the first most significant frame SF1 and the second most significant frame SF2, after the processing of steps S2609 to S2614 is repeated, , the source bit updated in step S2612 becomes the 8th bit, and an affirmative determination is made in step S2614.

If an affirmative determination is made in step S2614, the area RAm (where m is Any integer from 11 to 13) is grasped, and the area RAm is set as the movement source area of the information (step S2615). After that, the process returns to step S2609, and the processes of steps S2609 to S2615 are repeatedly executed until the value of the movement number counter becomes "0". As a result, the information stored in each bit of the most significant frame SFp (p is 1 or 2) in the pre-conversion area 184 is loaded into the most significant bit (seventh bit) in the corresponding area of the post-conversion area 185. , and the post-conversion area 185 can be in a state in which the command before conversion is stored. If the value of the number-of-movements counter becomes "0" (step S2611: YES), the second command conversion process is terminated.

According to this embodiment detailed above, the following excellent effects are obtained.

In the IY register 109, "0000H", which is the reference address for specific control, is stored at the start of the main process (FIG. 15), which is the process for specific control. As a result, in the first LDY instruction by the first LDY execution circuit 156, when any one of "0000H" to "00FFH" is specified, the address specification data is only the lower 1 byte in the 2-byte address information. becomes possible. Therefore, the data capacity of the program can be reduced.

The IY register 109 stores "0300H" as a reference address for non-specific control used when designating the address of the work area 122 for non-specific control in the management execution process (FIG. 57) for non-specific control. is set. This makes it possible to use the non-specific control reference address when executing the first LDY instruction and the second LDY instruction in the non-specific control process.

In the IY register 109, "0000H" is set as the reference address for specific control when the management execution process (FIG. 57), which is the process for non-specific control, is completed. This makes it possible to use the specific control reference address when executing the first LDY instruction and the second LDY instruction in the specific control process.

The total data capacity of the machine language of the first LDY instruction is 3 bytes. On the other hand, the total data capacity of the machine language of the LD instruction is 4 bytes. Therefore, when "0000H" is stored in the IY register 109, when the address of the data table stored in the main ROM 64 is loaded into a pair register such as the BC register 105, instead of the LD instruction, By using the first LDY instruction, the machine language of the instruction to load the data of the "source" to the "destination" can be reduced by one byte. Thereby, the data capacity of the program in the main ROM 64 can be reduced.

Storage areas such as the jackpot type counter C2 and the jackpot type maximum value counter CN2, which appear in the program many times in order to execute specific control processing, are stored in the characteristic control work area 121 with the LDY instruction (first 1LDY instruction and 2LDY instruction) is set in the target address range (“0000H” to “00FFH”), and appears in the program to execute specific control processing like a variable random number counter. A storage area such as a counter with a small number of times is set in an address range (“0100H” to “02FFH”) that is not subject to LDY instructions (first LDY instruction and second LDY instruction) in the work area 121 for characteristic control. This reduces the data volume of the program for executing the specific control process.

By setting the address data (2 bytes) of the jackpot type maximum value counter CN2 in the BC register 105 using the first LDY instruction that sets 1-byte address data and specifies the address, 2-byte address data A program for executing the maximum value setting start process (FIG. 24(b)) compared to the configuration in which the address data is set in the BC register 105 using the LD instruction for setting the address data and specifying the address. data capacity can be reduced.

The address data (2 bytes) of the jackpot type counter C2 is loaded into the HL register 107 using the first LDY instruction that specifies the address by setting the address data of 1 byte. Program for executing the update start setting process (FIG. 27(b)) compared to the configuration in which the address data of the jackpot type counter C2 is loaded into the HL register 107 using the LD instruction for setting and addressing data capacity can be reduced.

The address data (2 bytes) of the jackpot type maximum value counter CN2 is loaded into the BC register 105 using the first LDY instruction that sets 1-byte address data and specifies the address. Compared to the configuration of loading the address data of the jackpot type maximum value counter CN2 into the BC register 105 using the LD instruction that sets the address data and specifies the address, update start setting processing (Fig. 27 (b)) It is possible to reduce the data volume of the program for executing

When using the first LDY instruction, the address data included in the instruction code of the first LDY instruction can be only the lower 1 byte in the 2-byte address data. On the other hand, when using the LD instruction, the address data included in the instruction code of the LD instruction must be the entire 2-byte address data. By setting the address corresponding to the lower area of the first general winning counters 171a to 173a in the HL register 107 using the first LDY instruction, the address is set in the HL register 107 using the LD instruction. The data capacity of the program can be reduced compared to the configuration.

The high-order 4 bits of the address corresponding to the area in which the data table is stored in the main-side ROM 64 are commonly "9H". In the main process (FIG. 15) executed when the supply of operating power to the main CPU 63 is started, the TP register 111 stores "9000H", which is the reference address of the data table. As a result, when the LDT instruction by the LDT execution circuit 149 specifies one of "9000H" to "94FFH" and "9903H" to "9BFFH", the specified address data is transferred to the lower order of the 2-byte address information. Only 12 bits are possible. Therefore, the data capacity of the program can be reduced. Also, in the LDB instruction by the LDB execution circuit 157 and the LDB update instruction in the LDB update execution circuit 161, the reference address of the data table stored in the TP register 111 can be used.

The total data capacity of the machine language of the LDT instruction is 2 bytes. On the other hand, the total data capacity of the machine language of the LD instruction is 4 bytes. Therefore, when "9000H" is stored in the TP register 111, when the address of the data table stored in the main ROM 64 is loaded into the pair register such as the HL register 107, instead of the LD instruction, By using the LDT instruction, the machine language of the instruction to load the data of the "source" to the "destination" can be reduced by 2 bytes. Thereby, the data capacity of the program in the main ROM 64 can be reduced.

By using the LDT instruction to set the start address of the first initialization table 64k in the HL register 107, compared to the configuration in which the LD instruction is used to set the start address in the HL register 107, The data volume of the program for executing the power-on setting process (FIG. 17(c)) can be reduced.

By using the LDT instruction to set the start address of the random number maximum value table 64p in the HL register 107, the maximum The data capacity of the program for executing the value setting start process (Fig. 24(b)) can be reduced.

The configuration loads the start address of the second initialization table 64m into the HL register 107 using the LDT instruction for specifying the address by setting 12-bit numerical information, thereby setting 2-byte numerical information. Compared to the configuration in which the start address is loaded into the HL register 107 using the LD instruction that specifies the address, the data volume of the program for executing the fraud detection initialization process (FIG. 29(b)) is reduced. can do.

In the power-on setting process (FIG. 17(c)), the high-order 1 byte of the address for specifying the storage area where "0" clearing and initialization are performed is commonly "00H". In the power-on setting process, "00H" is set in the D register 106a, and the lower 1 byte of the address is read from the data table and set in the E register 106b, thereby storing the entire address (2 bytes) in the DE register 106. ) is stored. Then, the address information stored in the DE register 106 is used to designate the area to be cleared to "0" and initialized. This makes it possible to reduce the data capacity of the data stored in the main ROM 64 for addressing.

By using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the fraudulent radio wave detection counter 133, the address is stored in the first initialization table 64k. Only the lower 1 byte in the address data (2 bytes) of the unauthorized radio wave detection counter 133 can be used as the address data to be used. Therefore, the data capacity of the first initialization table 64k can be reduced compared to the configuration in which the entire address data (2 bytes) in the unauthorized radio wave detection counter 133 is stored in the first initialization table 64k. In addition, by using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the fraudulent magnetism detection counter 134, the first initialization table 64k The address data to be stored in can be only the lower 1 byte of the address data (2 bytes) of the fraudulent magnetism detection counter 134 . Therefore, the data capacity of the first initialization table 64k can be reduced compared to the configuration in which the entire address data (2 bytes) of the fraudulent magnetism detection counter 134 is stored in the first initialization table 64k. Furthermore, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a to specify the address of the abnormal vibration detection counter 135, the first initialization table The address data stored in 64 k can be only the lower 1 byte in the address data (2 bytes) of the abnormal vibration detection counter 135 . Therefore, the data capacity of the first initialization table 64k can be reduced compared to the configuration in which the entire address data (2 bytes) of the abnormal vibration detection counter 135 are stored in the first initialization table 64k.

Addressing of the power failure area 131 is performed using the common high-order 1 byte ("00H") stored in advance in the D register 106a, so that the address data to be stored in the second initialization table 64m Only the lower 1 byte in the address data (2 bytes) of the power failure area 131 can be used. Therefore, the data capacity of the second initialization table 64m can be reduced compared to a configuration in which the entire address data (2 bytes) of the power failure area 131 are stored in the second initialization table 64m. In addition, by using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the lower area of the fraud monitoring timer counter 132, the second initial Only the lower 1 byte of the address data (2 bytes) in the lower area of the fraud monitoring timer counter 132 can be stored in the conversion table 64m. Therefore, the data capacity of the second initialization table 64m can be reduced compared to the configuration in which the entire address data (2 bytes) in the lower area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can. Furthermore, by using the common high-order 1-byte data ("00H") stored in the D register 106a in advance, the high-order area of the fraud monitoring timer counter 132 is addressed. The address data stored in the initialization table 64m can be only the lower 1 byte of the address data (2 bytes) in the upper area of the fraud monitoring timer counter 132. FIG. Therefore, the data capacity of the second initialization table 64m can be reduced compared to the configuration in which the entire address data (2 bytes) in the upper area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can.

By using the LDT instruction to set the start address of the clear setting table 64n in the HL register 107, compared to the configuration in which the LD instruction is used to set the start address in the HL register 107, the clearing The data capacity of the program for executing the time setting process (Fig. 22(b)) can be reduced.

By using the common high-order 1-byte data (“00H”) stored in advance in the D register 106a to specify the address of the security signal area 153, the address to be stored in the setting table 64n at the time of clearing can be changed. The data can be only the lower 1 byte in the address data (2 bytes) of the security signal area 153 . Therefore, the data capacity of the clear setting table 64n can be reduced compared to the configuration in which the entire address data (2 bytes) of the security signal area 153 is stored in the clear setting table 64n. In addition, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a to specify the address of the first special figure display counter 154, the setting table at the time of clearing The address data stored in 64n can be only the lower 1 byte in the address data (2 bytes) of the first special figure display counter 154. Therefore, compared to the configuration of storing the entire address data (2 bytes) of the first special figure display counter 154 in the setting table 64n when clearing, the data capacity of the setting table 64n when clearing can be reduced. Furthermore, by using the common high-order 1-byte data ("00H") stored in advance in the D register 106a to specify the address of the second special figure display counter 155, setting when clearing The address data stored in the table 64n can be only the lower 1 byte in the address data (2 bytes) of the second special figure display counter 155. Therefore, compared to the configuration in which the entire address data (2 bytes) of the second special figure display counter 155 is stored in the clear setting table 64n, the data capacity of the clear setting table 64n can be reduced. .

A process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111 by using the LDB instruction; A process of specifying the acquisition start bit corresponding to the lower 3 bits of the specified acquisition data, a process of loading the data of the number of acquisition bits from the acquisition start bit of the acquisition start address to the "transfer destination" register, and a "transfer destination" register. and a process of masking with "0" the bits that exist on the upper side of the loaded data in the "previous" register can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

By using the LDB command to load the lower 12 bits of the start address obtained from the special special electric address table 64q into the HL register 107, the 3rd to 15th bits of the 2-byte acquisition data designation data and a process of specifying an acquisition start address corresponding to the reference address of the data table set in the TP register 111, a process of specifying an acquisition start bit corresponding to the lower 3 bits of the acquisition designation data, and a special special dispatch A process of loading the lower 12 bits of the start address obtained from the address table 64q into the lower 12 bits of the HL register 107 and a process of masking the upper 4 bits of the HL register 107 with "0" are executed by one instruction. can be done. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

By using the LDB instruction, the lower 12 bits of the start address SA0-SA6 can be loaded into the HL register 107 from the special special electric address table 64q. Further, after the execution of the LDB instruction, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SA0 to SA6 to the value of the HL register 107, the entire start addresses SA0 to SA6 are stored in the HL register 107. can be obtained. Therefore, only the lower 12 bits of the start addresses SA0 to SA6 can be set in the special figure special electric address table 64q. As a result, the data capacity of the special special electric address table 64q in the main ROM 64 can be reduced compared to the configuration in which the entire 2-byte start address SA0 to SA6 is set in the special special electric address table 64q.

By using the LDB instruction to load the lower 12 bits of the start address obtained from the variable start table 64r into the HL register 107, the 3rd to 15th bits of the 2-byte acquisition data designation data and A process of specifying an acquisition start address corresponding to the reference address of the data table set in the TP register 111, a process of specifying an acquisition start bit corresponding to the lower 3 bits of the acquisition designation data, and a fluctuation start table. 64r to load the lower 12 bits of the start address SBn obtained from 64r into the lower 12 bits of the HL register 107, and to mask the upper 4 bits of the HL register 107 with "0". can be done. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

By loading the lower 4 bits of the pending display data HRn acquired from the pending display data table 64s using the LDB instruction into the lower 4 bits of the W register 104a, the third to A process of specifying the acquisition start address corresponding to the data of the 15th bit and the reference address of the data table set in the TP register 111, and a process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition designation data. a process of loading the lower 4 bits of the pending display data HRn acquired from the pending display data table 64s into the lower 4 bits of the W register 104a; and a process of masking the upper 4 bits of the W register 104a with "0"; can be executed with one command. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB instruction, the processing of loading the lower 4 bits of the reserved display data HRn into the lower 4 bits of the W register 104a and the processing of masking the upper 4 bits of the W register 104a with "0" are integrated. To simplify the configuration of the program for executing the pending display data acquisition execution process, compared to a configuration in which a plurality of instructions are set for executing these processes, since the process can be executed by commands. In addition, the data capacity of the program in the main ROM 64 can be reduced.

In the fluctuation start table 64r, the lower 12 bits of the start addresses SB0 to SB23 of the fluctuation pattern table corresponding to the fluctuation type numbers 0 to 23 are set. The variable start table 64r has a data configuration in which the lower 12 bits of two start addresses SBn are set in areas corresponding to three consecutive addresses. In the variable start table 64r, the lower 12 bits of the 24 start addresses SB0 to SB23 are set in a storage area of 36 bytes in total. On the other hand, if the data structure is such that the whole (2 bytes) of one start address SBn (n is an integer from 0 to 23) is stored in an area corresponding to two consecutive addresses, 24 start addresses are stored. A storage area of 48 bytes is required in the main ROM 64 in order to store the fluctuation start table 64r in which SB0 to SB23 are set. In this way, the data capacity of the fluctuation start table 64r in the main ROM 64 is reduced by setting the data structure in which the lower 12 bits of the two start addresses SBn are set in areas corresponding to three consecutive addresses. be able to.

By using the LDB instruction, the lower 12 bits of the start addresses SB0 to SB23 can be obtained from the variable start table 64r. Further, after executing the LDB instruction, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SB0 to SB23 to the lower 12 bits, the entire start addresses SB0 to SB23 can be obtained. can. Therefore, the address data set in the fluctuation start table 64r can be only the lower 12 bits of the start addresses SB0 to SB23. As a result, the data capacity of the fluctuation start table 64r in the main ROM 64 can be reduced compared to the configuration in which the entire 2-byte start addresses SB0 to SB23 are set in the fluctuation start table 64r.

The lower 4 bits of the five pending display data HR0 to HR4 in the pending display data table 64s are set in a total 3-byte area in the main-side ROM 64. FIG. On the other hand, if all of the 1-byte pending display data HR0 to HR4 are stored in the pending display data table 64s, a total of 5 bytes of area is required to set the five pending display data HR0 to HR4. necessary. In this way, with the data configuration in which only the lower 4 bits of the five pending display data HR0 to HR4 are set in the pending display data table 64s, the pending display data table 64s is stored in the main ROM 64. data capacity has been reduced.

By using the LDB instruction, the lower 4 bits of the pending display data HRn are acquired from the pending display data table 64s into the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are masked with "0". can acquire the entire pending display data HRn. Therefore, the reserved display data HRn set in the reserved display data table 64s can be only the lower 4 bits of the reserved display data HRn. As a result, the data capacity of the pending display data table 64s in the main ROM 64 can be reduced compared to the configuration in which the entire 1-byte pending display data HRn is set in the pending display data table 64s.

By using the LD update instruction, the process of loading data and the process of adding 1 to the value of the HL register 107 after loading the data and updating the address stored in the HL register 107 can be combined into one instruction. can be run with For this reason, compared to a configuration in which an LD instruction for loading data and an instruction for adding 1 to the value of the HL register 107 after loading the data are set, the data is loaded and the address is changed after the data is loaded. The data capacity of the program for updating can be reduced.

By using the LD update instruction, the process of loading the data set in the second area of the first initialization table 64k into the E register 106b, adding 1 to the value of the HL register 107, and adding 1 to the HL register 107 A process of updating the stored address can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

By using the LD update instruction, a process of loading the maximum value data selected as a setting target in the random number maximum value table 64p into the A register 104b, and adding 1 to the value of the HL register 107 after loading the maximum value data. and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data volume of the program for executing the random number maximum value setting process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

By using the LDH update instruction, the upper 4-bit data and the lower 4-bit data in the 1-byte area of the main ROM 64 can be read to different general-purpose registers, and the data is read. The upper 4 bits in each general purpose register can be masked with "0".

By using the LDH update instruction, the upper 4-bit data in the area corresponding to the address stored in the HL register 107 of the "transfer source" is set to the "transfer destination" of the WA register 104. A process of loading the lower 4 bits of one of the general-purpose registers (W register 104a) and masking the upper 4 bits of the general-purpose register with "0", and setting the upper 4-bit data in the area as the "transfer destination" A process of loading the lower 4 bits of the other general-purpose register (A register 104b) out of the WA registers 104 and masking the upper 4 bits of the general-purpose register with "0"; A process of adding "1" to the address stored in the "original" HL register 107 to update the address can be executed with one instruction. Therefore, compared to a configuration in which a plurality of instructions are set in a program for executing these three processes, the configuration of the program can be simplified and the data capacity of the program can be reduced.

By using the LDH update instruction, the data set in the high-order 4 bits of the first area in the first initialization table 64k is set in the low-order 4 bits of the W register 104a, and the high-order 4 bits of the W register 104a are set. A process of masking with "0" and a process of setting the data set in the lower 4 bits of the first area to the lower 4 bits of the A register 104b and masking the upper 4 bits of the A register 104b with "0". and updating the address stored in the HL register 107 by adding 1 to the value of the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these three processes.

a process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111 by using the LDB update instruction; , a process of specifying the acquisition start bit number corresponding to the lower 3 bits of the specified acquisition data, and a process of loading the acquired bit number data from the acquisition start bit number of the acquisition start address into the lower bits of the "transfer destination" register. , the process of masking the upper bits in the "transfer destination" register with "0" and the process of adding the acquired bit number to the acquired data designation data after the data transfer and updating it can be executed with one instruction. . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

By setting the determination value data DV1 acquired from the high probability table 64g using the LDB update command to the WA register 104 and updating the acquisition data designation data, the third A process of specifying an acquisition start address corresponding to the data of the 15th bit and the reference address of the data table set in the TP register 111, and specifying an acquisition start bit corresponding to the lower 3 bits of the acquisition designation data. a process of loading the decision value data DV1 acquired from the high probability table 64g into the lower 6 bits of the WA register 104; a process of masking the upper 10 bits of the WA register 104 with "0"; A process of adding the acquired bit number to the data and updating the data can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

By setting the flag data FD1 acquired from the high accuracy table 64g using the LDB update instruction to the B register 105a to update the acquired data designation data, the third to A process of specifying the acquisition start address corresponding to the data of the 15th bit and the reference address of the data table set in the TP register 111, and a process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition designation data. Then, a process of loading the flag data FD1 acquired from the high certainty table 64g into the lower 2 bits of the B register 105a, a process of masking the upper 6 bits of the B register 105a with "0", and the acquisition data designation data and updating by adding the number of acquired bits can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB update command to load the first pre-addition distribution value FVA1 acquired from the first special figure distribution table 64h into the W register 104a and updating the acquired data designation data, 2 bytes 3rd to 15th bit data in the acquisition data designation data and the acquisition start address corresponding to the reference address of the data table set in the TP register 111, and corresponding to the lower 3 bits of the acquisition designation data A process of specifying the acquisition start bit, a process of loading the first pre-addition distribution value FVA1 acquired from the first special figure distribution table 64h into the lower 5 bits of the W register 104a, and the W register 104a The process of masking the upper 3 bits with "0" and the process of adding the number of acquisition bits to the acquisition data designation data and updating it can be executed with one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

By loading the first flag data FDA1 obtained from the first special figure distribution table 64h using the LDB update command into the B register 105a and updating the obtained data designation data, the obtained data of 2 bytes A process of specifying an acquisition start address corresponding to the data of the 3rd to 15th bits in the specified data and the reference address of the data table set in the TP register 111, and the acquisition start corresponding to the lower 3 bits of the specified acquisition data. A process of specifying the bit number, a process of loading the first flag data FD1 acquired from the first special figure distribution table 64h into the lower 3 bits of the B register 105a, and setting the upper 5 bits of the B register 105a to "0 , and the process of adding the acquired bit number to the acquired data designation data and updating it can be executed with one command. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

Using the program of the data setting execution process (Fig. 19(c)) and the data of the second initialization table 64m, which is also used in the power-on setting process (Fig. 17(c)), the illegal radio wave detection counter 133, the illegal magnetism By configuring to initialize the detection counter 134 and the abnormal vibration detection counter 135, a dedicated program and The data capacity of programs and data in the main ROM 64 can be reduced compared to a configuration in which data is stored.

In the second special figure pending display data acquisition process (Fig. 55(c)), using the subroutine program common to the first special figure pending display data acquisition process (Figure 55(a)) and the pending display data table 64s Acquire the pending display data HRn corresponding to the value of the second special figure pending number counter 119 . Therefore, it is possible to reduce the data capacity of the program and data for acquiring the pending display data HRn.

Normal figure reservation display data acquisition process (Figure 55 (d)), the first special figure reservation display data acquisition process (Figure 55 (a)) and the second special figure reservation display data acquisition process (Figure 55 (c)) Using the common subroutine program and the pending display data table 64s, the pending display data HRn corresponding to the value of the normal diagram pending number counter 127 is acquired. Therefore, it is possible to reduce the data capacity of the program and data for acquiring the pending display data HRn.

In the first special figure distribution process, by uniformly adding "20" to the pre-addition distribution value FVAn set in the first special figure distribution table 64h, the first distribution value A certain "40", a second apportionment value of "40", and a third apportionment value of "20" are calculated. The first to third pre-addition distribution values FVA1 to FVA3 obtained by subtracting "20" from the first to third distribution values are data configurations set in the first special figure distribution table 64h, Compared with the data configuration in which the first to third distribution values are set, the data capacity of the first special figure distribution table 64h in the main ROM 64 can be reduced.

In the second special figure distribution process, by uniformly adding "20" to the pre-addition distribution value FVBn set in the second special figure distribution table 64j, the first distribution value A certain "30", a second apportionment value of "50", and a third apportionment value of "20" are calculated. By the data configuration in which the first to third pre-addition distribution values FVB1 to FVB3 obtained by subtracting "20" from the first to third distribution values are set in the second special figure distribution table 64j, The data capacity of the second special figure distribution table 64j in the main ROM 64 can be reduced compared to the data configuration in which the first to third distribution values are set.

In the LDB instruction and the LDB update instruction, the data obtained by dividing the 16-bit acquired data designation data by "8" ("1000B") is stored in the TP register 111 at the reference address ("9000H ”) is performed to calculate the acquisition start address. "8" used to calculate the acquisition start address is a numerical range ("0" to " 7”), which is the maximum value of “7” plus “1”, which is the cube of “2”. By dividing the acquisition data designation data by the "8" ("1000B"), the "0" or "1" information set in the 3rd to 15th bits of the acquisition data designation data is reduced by 3 bits. can be set to the lower 13 bits (0th to 12th bits) of the quotient data after division by shifting to the side, and the upper 3 bits (13th to 15th bits) of the quotient data after the division can be set to " 0" can be set. As a result, only the data for specifying the acquisition start address is extracted from the 16-bit acquisition data designation data in which the data for specifying the acquisition start address and the data for specifying the acquisition start bit are aggregated and set. It can be taken out and made available.

In the LDB instruction and the LDB update instruction, the lower 3-bit data in the acquired data designation data is extracted by performing a logical product operation between the lower 1 byte of the acquired data designation data and "00000111B". The lower 3-bit data is data for specifying the acquisition start bit. Data for specifying the acquisition start address and data for specifying the acquisition start bit are aggregated and set by performing a logical product operation of the lower 1 byte of the acquisition data designation data and "00000111B". Only the data for specifying the acquisition start bit can be extracted from the 16-bit acquisition data designation data and made available.

The data for specifying the acquisition start address and the data for specifying the acquisition start bit are aggregated and set in acquisition data designation data consisting of 2 bytes. As a result, the data volume of the acquisition data designation data is reduced, and the data volume of the machine language of the LDB instruction and the LDB update instruction is also reduced.

A header identification bit is set in the header HD to enable identification of the header HD. The header identification bit is the most significant bit (seventh bit) of the header HD. "1" is set in the header identification bit. Among the 1-byte data included in the command, the header HD is the only data in which the most significant bit is set to "1". Therefore, the sound and light side receiving circuit 96 determines whether or not the most significant bit of the 1-byte data stored in the reception buffer 177 is set to "1", so that the 1-byte data is transferred to the header. Whether or not it is HD can be grasped. This enables the sound/light receiving circuit 96 to grasp the delimiter position between the commands received from the first transmitting circuit 101 .

A command for communication (variation command for communication and normal return command for communication) includes a header HD and a footer FT. The sound and light side CPU 93 can grasp the start position of the command for communication using the header HD, and can grasp the end position of the command for communication using the footer FT.

When the 1-byte data received next to the footer FT from the first transmitting circuit 101 is data other than the header HD, the sound and light receiving circuit 96 receives the header HD without receiving the footer FT. It is recognized that a communication error has occurred even when the next header HD is received. As a result, data different from the command set in the transmission standby buffer 175 by the main side CPU 63 can be prevented from being used by the sound and light side CPU 93 .

When transmitting a command including one or more data frames FRm (m is an integer of 1 or more), the main CPU 63 generates a post-conversion command in which the most significant bit of each data frame FRm is changed to "0". The most significant frame SFp (p is 1 or 2) that collects the most significant bit information of each data frame FRm is set in the post-conversion command. As a result, the sound and light reception circuit 96 can distinguish between the header HD and data other than the header HD while enabling the information of the most significant bit of each data frame FRm to be grasped.

The sound and light side CPU 93 sets the command for communication (variation command for communication and normal return command for communication) stored in the post-reception waiting buffer 178 to the pre-conversion area 184, and then sets the command for communication. In a post-conversion area 185, the command is converted into a post-conversion command. Then, the converted command is stored in the command storage buffer 179 . As a result, the post-conversion command can be used by the sound and light side CPU 93 .

The sound and light side CPU 93 grasps the number and position of the highest frame SFp (p is 1 or 2) in the communication command based on the number of bytes of the received communication command. Therefore, the process of setting information indicating the position of the highest frame SFp in the communication command can be eliminated. As a result, it is possible to prevent the data volume of the command for communication from increasing, and to reduce the processing load for generating the command for communication. In addition, it is possible to reduce the data capacity of the program for generating communication commands.

The sound and light side CPU 93 identifies the data frame FRm corresponding to the bit based on the position of the bit in the most significant frame SFp. Therefore, it is possible to eliminate the need for setting information indicating the correspondence between each bit of the most significant frame SFp and the data frame FRm in the communication command. As a result, it is possible to prevent the data volume of the communication command from increasing and to reduce the processing load for generating the communication command. In addition, it is possible to reduce the data capacity of the program for generating communication commands.

The number of data frames FRm included in the communication command transmitted from the main side CPU 63 to the sound and light side CPU 93 is any one of "1" to "12". When the number of data frames FRm included in the command for communication is a multiple of "7", the number of data frames FRm included in the command for communication is divided by "7". The most significant frame SFp of the quotient is set in the communication command. Further, when the number of data frames FRm included in the command for communication is not a multiple of "7", the number of data frames FRm included in the command for communication is divided by "7". The most significant frame SFp, which is "1" larger than the number of quotients in the case, is set in the command for this communication. As a result, after the communication command is received, the information set in the most significant bit in all the data frames FRm included in the communication command can be set in the most significant frame SFp.

<Second embodiment>
The present embodiment differs from the first embodiment in that processing for setting the maximum value of numerical information updated in a hard random number circuit provided on the main control board 61 is executed. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 76 is an explanatory diagram for explaining the configuration of the main control board 61 in this embodiment. As shown in FIG. 76, the main control board 61 includes a jackpot type update circuit 191 that updates the numerical information used when judging the jackpot type, and a reach generation lottery when the symbol display device 41 comes off and fluctuates. A reach random number update circuit 192 that updates the numerical information used for , and the numerical information used for the lottery as to whether or not the general electric accessory 34a of the second operation port 34 is in the electric open state is updated. A general electric random number update circuit 193 is provided. These update circuits 191-193 are hard random number circuits.

The lottery counter area 112 (FIG. 11) in the work area 121 for specific control is provided with the winning random number counter C1, the random number initial value counter C4, and the variation type counter C5 already described in the first embodiment. . As in the first embodiment, the numerical value information updated by the winning random number counter C1 is used for the lottery for the occurrence of winning, and the numerical value information updated by the random number initial value counter C4 is used for the winning random number counter C1. Used for initial value setting. Further, the numerical information updated by the variation type counter C5 is used to determine the display duration time in each special figure display section 37a, 37b and the symbol display device 41.

The numerical information updated by the jackpot type update circuit 191, the numerical information updated by the reach random number update circuit 192, and the numerical information updated by the general electric random number update circuit 193 are updated in these update circuits 191 to 193. Each update adds 1 to the previous value, and returns to 0 after reaching the maximum value. Numerical information is updated at short time intervals in each of the update circuits 191-193. Each numerical value information of the jackpot type update circuit 191 and the reach random number update circuit 192 is stored in the special figure reservation area 113 when winning to the first operation port 33 or the second operation port 34 occurs. Further, as in the first embodiment, when the winning to the first operation opening 33 or the second operation opening 34 occurs, the numerical information of the winning random number counter C1 is also stored in the special figure reservation area 113 . Numerical information updated by the general/universal electric random number update circuit 193 is stored in the general/universal diagram reservation area 114 when winning to the through gate 35 occurs.

As shown in FIG. 76, the jackpot type update circuit 191 is provided with a jackpot type maximum value counter 191a in which the maximum value of numerical information updated by the jackpot type update circuit 191 is set, and a reach random number update. The circuit 192 is provided with a reach random number maximum value counter 192a in which the maximum value of the numerical information updated by the reach random number update circuit 192 is set. A general electric random number maximum value counter 193a in which the maximum value of the numerical information updated by the circuit 193 is set is provided.

FIG. 77(a) is an explanatory diagram for explaining the maximum values of the update circuits 191-193. The setting of the maximum value to the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a and the general electric random number maximum value counter 193a is performed when the power is turned on. As shown in FIG. 77(a), "99" is set in the jackpot type maximum value counter 191a, "238" is set in the reach random number maximum value counter 192a, and " 250” is set.

An address of "1111H" is set in the jackpot type maximum value counter 191a, an address of "1112H" is set in the reach random number maximum value counter 192a, and an address of "1113H" is set in the general electric random number maximum value counter 193a. address is set. By specifying these addresses, the main CPU 63 can set the maximum value to the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a, and the general electric random number maximum value counter 193a.

The main-side ROM 64 stores a hardware random number maximum value table 64w used to set the maximum values of the jackpot type update circuit 191, the reach random number update circuit 192, and the general electric random number update circuit 193. FIG. 77(b) is an explanatory diagram for explaining the data structure of the hard random number maximum value table 64w.

As shown in FIG. 77(b), the hard random number maximum value table 64w is set in the address range of "9420H" to "9426H" in the main ROM 64. As shown in FIG. The hard random number maximum value table 64w has a data structure in which the first area and the second area are alternately repeated. The first area is a 1-byte area in which the lower 1 byte or end data is set in the addresses of the update circuits 191 to 193, and the second area is the update circuits 191 to 193 corresponding to the address of the previous first area. This is a 1-byte area in which the maximum value data of is set.

As shown in FIG. 77(a), the upper 1 byte in each address of the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a and the general electric random number maximum value counter 193a is common to "11H". In this embodiment, the main CPU 63 stores "1100H" in the IY register 109 in advance as the upper 1-byte data of these maximum value counters 191a-193a to set the maximum values of the update circuits 191-193. The main CPU 63 reads out the lower 1 byte at the address of each of the maximum value counters 191a to 193a from the main ROM 64, and adds the upper 1 byte data and the lower 1 byte data to read each maximum value counter 191a to 193a. Identify an address.

As shown in FIG. 77(b), in the hard random number maximum value table 64w, the first area corresponding to 9420H is set with "11H" which is the lower 1 byte of the address of the jackpot type maximum value counter 191a. , "63H" ("99"), which is the maximum value data set in the jackpot type maximum value counter 191a, is set in the second area corresponding to "9421H" following "9420H". In the first area corresponding to "9422H" following "9421H", "12H" which is the lower 1 byte of the address of the reach random number maximum counter 192a is set, and "9423H" following "9422H" "EEH" ("238"), which is the maximum value data set in the reach random number maximum value counter 192a, is set in the corresponding second area. In the first area corresponding to "9424H" following "9423H", "13H", which is the lower 1 byte of the address of the general electrical maximum random number counter 193a, is set, and "9425H" following "9424H" is set. In the second area corresponding to , "FAH" ("250"), which is the maximum value data set in the general electric random number maximum value counter 193a, is set. "00H", which is end data, is set in the first area corresponding to "9426H" following "9425H".

The data set in the hard random number maximum value table 64w to specify the addresses of the maximum value counters 191a to 193a is only the lower 1 byte of the addresses. Therefore, in the hard random number maximum value table 64w, the data capacity (1 byte) of the data for specifying the addresses of the maximum value counters 191a to 193a and the data of the maximum value data set in the maximum value counters 191a to 193a The capacity (1 byte) can be the same data capacity. As a result, the data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 78(a). The random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed using a program for specific control and data for specific control.

In the random number maximum value setting process, an update circuit setting process is first executed (step S2701). In the update circuit setting process, "99", which is the maximum value of the jackpot type update circuit 191, is set to the jackpot type maximum value counter 191a, and "238", which is the maximum value of the reach random number update circuit 192, is set to the reach random number maximum value counter 192a. , and "250", which is the maximum value of the general electrical random number update circuit 193, is set in the general electrical random number maximum value counter 193a. Details of the update circuit setting process will be described later.

After executing the update circuit setting process in step S2701, the maximum value setting process of the winning random number counter C1 is executed (step S2702). In the maximum value setting process, "7999", which is the maximum value of the winning random number counter C1, is set in the winning maximum value counter CN1. After that, the maximum value setting processing of the random number initial value counter C4 is executed (step S2703). In the maximum value setting process, "7999", which is the maximum value of the random number initial value counter C4, is set in the initial value maximum value counter CN4. After that, the maximum value setting process of the fluctuation type counter C5 is executed (step S2704), and the random number maximum value setting process is ended. In the maximum value setting process of the fluctuation type counter C5, the maximum value of the fluctuation type counter C5, ie, "250" is set in the fluctuation type maximum value counter CN5.

Next, the contents of the update circuit setting process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 78(b). The update circuit setting process is executed in step S2701 of the random number maximum value setting process (FIG. 78(a)). As shown in FIG. 78(b), "2501" to "2504" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

The command "LDT HL, 420H" is set at the line number "2501". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "420H" sets 12-bit numerical information "420H" as the transfer source. Content. As already described in the first embodiment, "9000H" is set in the TP register 111 as the reference address of the data table in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 420H", "9420H" obtained by adding "9000H" set in the TP register 111 to "420H" set as the "transfer source" ” is set in the HL register 107 . "9420H" is the start address of the hard random number maximum value table 64w (FIG. 77(b)) in the main ROM 64. FIG.

In this way, by using the LDT instruction for setting 12-bit numerical information and specifying the address, the start address of the hard random number maximum value table 64w is loaded into the HL register 107, thereby enabling 2-byte numerical information. The data capacity of the program for executing the random number update circuit setting process is compared with the configuration in which the start address of the hard random number maximum value table 64w is loaded into the HL register 107 using the LD instruction that sets and specifies the address. can be reduced.

The command "LD IY, 1100H" is set at the line number "2502". "LD" is the LD instruction, "IY" is the content specifying the IY register 109 as the transfer destination, and "1100H" is the "transfer source", which is the upper address common to the random number update circuits 191 to 193. This is the content for setting 1-byte data. By executing “LD IY, 1100H”, “1100H” set as the “transfer source” is loaded into the IY register 109 . As a result, the data for the upper 1 byte can be stored in the IY register 109 .

The command "CALLS HRSDSET" is set at the line number "2503". "HRSDSET" is maximum value setting execution processing (FIG. 78(c)), which will be described later. The instruction "CALLS HRSDSET" is an instruction for calling a subroutine called maximum value setting execution processing. Details will be described later, but by executing the maximum value setting execution process at the line number "2503", the maximum value data in the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a and the general electric random number maximum value counter 193a is set. Details of the maximum value setting execution process will be described later.

When the maximum value setting execution processing subroutine is completed, the process proceeds to the line number "2504". A command "RET" is set at the line number "2504". As already explained, the update circuit setting process is a subroutine executed in step S2701 of the random number maximum value setting process (FIG. 78(a)). Therefore, by executing the command "RET", the process proceeds to step S2702 of the random number maximum value setting process (FIG. 78(a)).

FIG. 78(c) is an explanatory diagram for explaining the program contents of the maximum value setting execution process executed by the main CPU 63. FIG. The maximum value setting execution process is executed at line number "2503" of the update circuit setting process (FIG. 78(b)). As shown in FIG. 78(c), a special LD instruction "LD (IY+A), W" is set in line number "2605" of the maximum value setting execution process.

Before describing the maximum value setting execution process (FIG. 78(c)), the special LD instruction included in the maximum value setting execution process will be described. As shown in FIG. 76, the main control board 61 is provided with a special LD execution circuit 194 as a dedicated circuit for executing special LD instructions.

The instruction code of the special LD instruction has a structure of "LD (index register+general-purpose register), transfer source", such as "LD (IY+A), W". In the special LD instruction, the IY register 109 is set as the "index register" and the A register 104b is set as the "general purpose register". Also, in the special LD instruction, the W register 104a storing 1-byte data is set as the "transfer source". Note that the IX register 108 or TP register 111 may be set as the "index register" in the special LD instruction, and the W register 104a, B register 105a, C register 105b, D register 106a, and E register may be set as the "general-purpose registers." 106b, H register 107a or L register 107b may be set. A configuration in which the D register 106a, the E register 106b, the H register 107a, or the L register 107b is set may be used.

In the special LD instruction, "index register + general purpose register" is the sum ( addition operation result), and “(index register+general-purpose register)” means 1-byte data stored in the area corresponding to the address of the sum. By executing the special LD instruction, the 1-byte data stored in the W register 104a set as the "transfer source" is loaded into the area corresponding to the address of the operation result of "index register + general-purpose register". be done.

In this way, by using the special LD instruction, the processing of calculating the sum of the data stored in the IY register 109 and the data stored in the A register 104b to calculate the address of the transfer destination; A process of loading 1-byte data stored in the W register 104a of the transfer source into the transfer destination can be executed by one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

Next, the program contents of the maximum value setting execution process executed by the main CPU 63 will be described with reference to FIG. 78(c). As already explained, the maximum value setting execution process is executed at line number "2503" of the update circuit setting process (FIG. 78(b)). As shown in FIG. 78(c), "2601" to "2606" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 78(c), "HRSDSET" is set to the line number of "2601". This is not an instruction but data referred to when the developer of the pachinko machine 10 checks the program. Therefore, at line number "2601", the process proceeds to line number "2602" without executing any instruction.

The command "LD A, (HL+)" is set at the line number "2602". "LD" is an LD update command by the LD update execution circuit 151, "A" is the content specifying the A register 104b as the transfer destination, and "(HL+)" is stored in the HL register 107 as the transfer source. The content is to specify a storage area corresponding to 2-byte address data and to update the value of the HL register 107 by adding 1 after loading the data. As already explained, the HL register 107 stores "9420H", which is the start address of the maximum hard random number table 64w (FIG. 77(b)), and the maximum hard random number table 64w has a The lower 1 byte ("11H") in the address of the jackpot type maximum value counter 191a is set in the corresponding first area. Therefore, "11H" is loaded into the A register 104b by executing "LD A, (HL+)". Also, "9421H" is stored in the HL register 107. FIG.

The command "RET Z" is set at the line number "2603". "RET Z" terminates the maximum value setting execution processing (FIG. 78(c)) when data for ending the maximum value setting execution processing (FIG. 78(c)) is set in the A register 104b, and This command instructs to proceed to the next line number when the end data is not set. When the end data (“00H”) is set in the A register 104b at line number “2602”, “RET Z” is executed at line number “2603” to execute this maximum value setting execution process. (FIG. 78(c)) ends. On the other hand, if the data set in the A register 104b at line number "2602" is data other than end data, the maximum value is set even if "RET Z" is executed at line number "2603". The execution process (Fig. 78(c)) never ends and proceeds to line number "2604".

The command "LD W, (HL+)" is set at the line number "2604". "LD" is an LD update command by the LD update execution circuit 151, "W" is the content specifying the W register 104a as the transfer destination, and "(HL+)" is stored in the HL register 107 as the transfer source. The content is to specify a storage area corresponding to 2-byte address data and to update the value of the HL register 107 by adding 1 after loading the data. As already explained, "9421H" is stored in the HL register 107, and in the second area corresponding to "9421H" in the hard random number maximum value table 64w (FIG. 77(b)), the jackpot type maximum value "63H" ("99"), which is the maximum value data set in the counter 191a, is set. Therefore, by executing "LD W, (HL+)", "63H" is loaded into the W register 104a and the address data stored in the HL register 107 is updated to "9422H".

A command "LD (IY+A), W" is set at the line number "2605". "LD" is a special LD instruction by the special LD execution circuit 194, and "(IY+A)" is the storage area corresponding to the address data obtained by adding the data of the IY register 109 to the data of the A register 104b as the transfer destination. This is the content to be specified, and "W" is the content that specifies the W register 104a as the transfer source. As already explained, the IY register 109 stores in advance the upper 1-byte data ("1100H") of the update circuits 191 to 193, and the A register 104b stores the address data of the jackpot type maximum value counter 191a. The lower 1 byte (“11H”) is stored. The W register 104a stores the maximum value data ("63H") corresponding to the jackpot type maximum value counter 191a. Therefore, by executing "LD (IY+A), W", the maximum value data "63H" is loaded into the jackpot type maximum value counter 191a.

Thus, by using the special LD instruction, the processing of calculating the transfer destination address by adding the data stored in the A register 104b to the data stored in the IY register 109; A process of loading the maximum value data stored in the register 104a to the transfer destination can be executed by one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

The command "JR HRSDSET" is set at the line number "2606". "JR" is a JR instruction as a jump instruction, and "HRSDSET" is a content specifying the first line number "2601" in the maximum value setting execution processing as a jump destination. By executing "JR HRSDSET", the process advances to line number "2601" of the maximum value setting execution process.

After that, the processing of line numbers “2602” to “2606” is executed while “9422H” is stored in the HL register 107 . As a result, the reach random number maximum value counter 192a is loaded with the maximum value data "EEH" ("238"), and the address data stored in the HL register 107 is updated to "9424H".

After that, the processing of line numbers “2602” to “2606” is executed while “9424H” is stored in the HL register 107 . As a result, the maximum value data "FAH" is loaded into the general electrical random number maximum value counter 193a, and the address data stored in the HL register 107 is updated to "9426H".

After that, the processing of line numbers “2602” to “2606” is executed while “9426H” is stored in the HL register 107 . By executing "LD A, (HL+)" at line number "2602", end data "00H" is loaded into the A register 104b. Thereafter, "RET Z" is executed at line number "2603" in a state in which data for termination is set in the A register 104b, thereby ending this maximum value setting execution processing. As already explained, the maximum value setting execution process is a subroutine executed at line number "2503" of the update circuit setting process (FIG. 78(b)). Therefore, by executing "RET Z", this maximum value setting execution processing is terminated, and the process advances to line number "2504" of the update circuit setting processing (FIG. 78(b)).

In this way, by executing the update circuit setting process (FIG. 78(b)) using the hardware random number maximum value table 64w (FIG. 77(b)), the jackpot type maximum value counter 191a and the reach random number maximum value counter Maximum value data can be set in 192a and general electric random number maximum value counter 193a.

After performing the process of setting the upper 1-byte data (“1100H”) in the IY register 109, a special LD instruction that uses the upper 1-byte data stored in the IY register 109 is executed multiple times (specifically, is executed 3 times). Therefore, the entire address data (2 bytes) of the maximum value counters 191a to 193a are stored in the hard random number maximum value table 64w (FIG. 77(b)) without setting the upper 1-byte data in the IY register 109. The data capacity of the hard random number maximum value table 64w in the main-side ROM 64 can be reduced compared to a configuration in which data is stored.

According to this embodiment detailed above, the following excellent effects are obtained.

By using a special LD instruction, the data stored in the IY register 109 is added to the data stored in the A register 104b to calculate the transfer destination address, and the data is stored in the W register 104a. and a process of loading the stored maximum value data to the transfer destination can be executed by one instruction. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

The upper 1 byte in each address of the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a and the general electric random number maximum value counter 193a is common at "11H". "1100H" is stored in the IY register 109 in advance as data for the upper 1 byte of these maximum value counters 191a to 193a. The main CPU 63 reads out the lower 1 byte at the address of each of the maximum value counters 191a to 193a from the main ROM 64, and adds the upper 1 byte data and the lower 1 byte data stored in the IY register 109. The address of each maximum value counter 191a-193a is specified. This makes it easier to specify the addresses of the maximum value counters 191a to 193a.

After performing the process of setting "1100H" as the upper 1-byte data in the IY register 109, a special LD instruction that uses the upper 1-byte data stored in the IY register 109 is executed multiple times (specifically, 3 times). Therefore, compared to the configuration in which the entire address data (2 bytes) of the maximum value counters 191a to 193a are stored in the hard random number maximum value table 64w without setting the upper 1-byte data in the IY register 109. , the data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced.

The data set in the hard random number maximum value table 64w for specifying the addresses of the maximum value counters 191a to 193a is only the lower 1 byte of the addresses. Therefore, in the hard random number maximum value table 64w, the data capacity (1 byte) of the data for specifying the addresses of the maximum value counters 191a to 193a and the maximum value data set in the maximum value counters 191a to 193a The capacity (1 byte) can be the same data capacity. Thereby, the data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced.

By using the LDT instruction for setting 12-bit numerical information and specifying the address, the start address of the hard random number maximum value table 64w is loaded into the HL register 107, so that 2-byte numerical information is set. To reduce the data capacity of the program for executing the random number update circuit setting process compared to the configuration in which the start address of the hard random number maximum value table 64w is loaded into the HL register 107 using the LD instruction for addressing. can be done.

<Third Embodiment>
This embodiment differs from the first embodiment in the content of display control processing. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 79 is a flow chart showing display control processing executed by the main CPU 63 in this embodiment. As already explained in the first embodiment, the display control process is executed in step S514 of the timer interrupt process (FIG. 26). The display control process is executed using a program for specific control and data for specific control.

In the display control process, first, the D register 106a is cleared to "0" (step S2801). After that, the value of the first special figure reservation number counter 118 in the work area 121 for specific control is set to the E register 106b (step S2802). After that, a hold display acquisition process is executed (step S2803). In the pending display acquisition process, the 4-bit data corresponding to the pending number stored in the E register 106b from the pending display data table 64x (FIG. 80(a)) stored in the main ROM 64 is stored in the W register 104a. The lower 4 bits (0th to 3rd bits) are loaded, and the upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". As a result, the pending display data HRn (n is any integer from 0 to 4) corresponding to the pending number stored in the E register 106b can be set in the W register 104a.

FIG. 80(a) is an explanatory diagram for explaining the data structure of the pending display data table 64x. As shown in FIG. 80(a), the pending display data table 64x is stored in a 1-byte area corresponding to the address "9195H". The lower 4 bits (0th to 3rd bits) of the 1-byte area are set to "1", and the upper 4 bits (4th to 7th bits) are set to "0". .

FIG. 80(b) is an explanatory diagram for explaining the correspondence relationship between the number of reservations and the mode of acquisition of the reservation display data HRn. In the hold display acquisition execution process (FIG. 80(d)) described later, the HL register 107 is set to hold display data corresponding to the hold number (one of "0" to "4") in the W register 104a. In a state where acquisition data designation data corresponding to any of the pending numbers "0" to "4" is stored and "03H" is stored as acquisition bit number designation data in the A register 104b, "LDB W, (HL).A" is executed. In the LDB instruction, 4-bit data from the pending display data table 64x (FIG. 80(a)) is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and the 4th bit of the W register 104a is loaded. The 4th to 7th bits are masked with "0".

As shown in FIG. 80(b), the acquisition data designation data corresponding to the pending number "4" is "0CA8H". Acquisition data designation data corresponding to the number of reservations "3" is "0CA9H", acquisition data designation data corresponding to the number "2" of reservations is "0CAAH", and acquisition data corresponding to the number of reservations "1". The designation data is "0CABH", and the acquisition data designation data corresponding to the pending number "0" is "0CACH". “0CA8H”, which is the acquired data designation data corresponding to the number of reservations “4”, is numerical information calculated by the formula “{(start address of reservation display data table 64x)−9000H}×8”. Acquisition data designation data corresponding to the number of reservations "0" to "4" is numerical information calculated by subtracting the number of reservations from "0CACH", which is the acquisition data designation data corresponding to the number of reservations "0". is.

When the LDB instruction “LDB W, (HL). The start address becomes "9195H" and the acquisition start bit number becomes "4". Then, the 4-bit data ("0000B") set after the 4th bit of the area corresponding to "9195H" is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , the 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". As a result, the pending display data HR0 (“00000000B”) corresponding to the pending number “0” can be set in the W register 104a. When the LDB instruction "LDB W, (HL).A" is executed in a state where the acquisition data designation data ("0CABH") corresponding to the pending number "1" is stored in the HL register 107, the acquisition The start address becomes "9195H" and the acquisition start bit number becomes "3". Then, the 4-bit data ("0001B") set after the 3rd bit of the area corresponding to "9195H" is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , the 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". As a result, the pending display data HR0 (“00000001B”) corresponding to the pending number “1” can be set in the W register 104a. When the LDB instruction “LDB W, (HL). The start address becomes "9195H" and the acquisition start bit number becomes "2". Then, the 4-bit data ("0011B") set after the second bit in the area corresponding to "9195H" is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , the 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". As a result, the pending display data HR0 (“00000011B”) corresponding to the pending number “2” can be set in the W register 104a. When the LDB instruction "LDB W, (HL).A" is executed with the acquisition data designation data ("0CA9H") corresponding to the pending number "3" stored in the HL register 107, the acquisition The start address becomes "9195H" and the acquisition start bit becomes "1". Then, the 4-bit data ("0111B") set after the 1st bit in the area corresponding to "9195H" is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , the 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". As a result, the pending display data HR0 (“00000111B”) corresponding to the pending number “3” can be set in the W register 104a. When the LDB instruction “LDB W, (HL). The start address becomes "9195H" and the acquisition start bit becomes "0". Then, the 4-bit data ("1111B") set after the 0th bit in the area corresponding to "9195H" is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , the 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". As a result, the pending display data HR0 (“00001111B”) corresponding to the pending number “4” can be set in the W register 104a.

Next, the pending display acquisition process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 80(c). The pending display acquisition process is executed in step S2803 of the display control process (FIG. 79). The pending display acquisition process is also executed in steps S2806 and S2809 of the display control process (FIG. 79).

In the hold display acquisition process, first, the HL register 107 is set to "0CACH" (step S2901). After that, the value of the DE register 106 is subtracted from the value of the HL register 107 (step S2902). As already explained, the value of the D register 106a is cleared to "0" at step S2801 of the display control process (FIG. 79), and at step S2802 the E register 106b contains the first special figure pending number counter 118. A value is set. Therefore, by subtracting the value of the DE register 106 from the value of the HL register 107, the value obtained by subtracting the number of reservations in the first special figure reservation area 115 from "0CACH" in the HL register 107, that is, the first special figure reservation Acquisition data designation data corresponding to the value of the number counter 118 is stored. Note that when the pending display acquisition process (FIG. 80(c)) is executed in step S2806 of the display control process (FIG. 79), the process of step S2902 is executed to store the second Acquired data designation data corresponding to the value of the special figure pending number counter 119 is stored, and at step S2809 of the display control process (FIG. 79), the pending display acquisition process (FIG. 80 (c)) is executed. When it is executed, the acquisition data designation data corresponding to the value of the normal figure reservation number counter 127 is stored in the HL register 107 by executing the process of step S2902.

Thereafter, pending display acquisition execution processing is executed (step S2903), and this pending display acquisition processing ends. FIG. 80(d) is an explanatory diagram for explaining the contents of the program of the pending display acquisition execution process. As shown in FIG. 80(d), "2701" to "2703" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

As shown in FIG. 80(d), the command "LD A, 03H" is set at the line number "2702". "LD" is the LD instruction, "A" is the content specifying the A register 104b as the transfer destination, and "03H" is the content specifying 1-byte numerical information "03H" as the transfer source. "03H" is a value obtained by subtracting "1" from the number of bits ("4") acquired from the pending display data table 64x by the LDB command set in line number "2702". By executing "LD A, 03H", "03H" is loaded into the "transfer destination" A register 104b. When an LDB instruction "LDB W, (HL).A" is executed in the pending display acquisition execution process (Fig. 80(d)), which will be described later, the LDB execution circuit 157 performs an operation to add 1 to the value of the A register 104b. The value after the addition of 1 is used as data of the number of acquired bits. Therefore, by storing "03H" in the A register 104b at the line number "2701", the number of bits of data acquired from the pending display data table 64x in the LDB instruction can be set to "4".

The command "LDB W, (HL).A" is set at the line number "2702". "LDB" is the LDB instruction by the LDB execution circuit 157, "W" is the content specifying the W register 104a as the "transfer destination", and "(HL)" is the 2-byte data stored in the HL register 107. Data is specified as acquisition data specification data, and "A" is content specifying 1-byte data stored in the A register 104b as acquisition bit number specification data. As already described, the HL register 107 stores acquisition data designation data corresponding to the pending number, and the A register 104b stores "03H". Also, the TP register 111 stores "9000H" which is the reference address of the data table. As shown in FIG. 80(b), the acquisition start address is "9195H" in which the pending display data table 64x is stored regardless of whether the pending number is "0" to "4". As already explained, by executing "LDB W, (HL).A", the pending display data HRn (n is any integer from 0 to 4) corresponding to the pending number "n" is stored in the W register 104a. can be set to

In this way, the lower 4 bits of the pending display data HRn obtained from the pending display data table 64x using the LDB instruction are loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and the W register 104a is loaded. is masked with "0", the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111 correspond to A process of specifying an acquisition start address, a process of specifying an acquisition start bit corresponding to the 0th to 2nd bits (lower 3 bits) of the acquisition designation data, and the pending display data HRn acquired from the pending display data table 64x. into the 0th to 3rd bits (lower 4 bits) of the W register 104a and the processing of masking the upper 4 bits of the W register 104a with "0" are executed by one instruction. be able to. These processes are executed by the LDB execution circuit 157 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

A command "RET" is set at the line number "2703". As already described, the pending display acquisition execution process is a subroutine executed in step S2903 of the pending display acquisition process (FIG. 80(c)). Therefore, execution of the command "RET" terminates the pending display acquisition execution process and also terminates the pending display acquisition process.

In this way, by using the LDB instruction, it is possible to acquire the lower 4 bits of the pending display data HRn by shifting the acquisition start bit in a manner corresponding to the pending number in the pending display data table 64x. Therefore, the data capacity of the pending display data table 64x can be reduced to 1 byte.

Returning to the description of the display control process (FIG. 79), after the pending display acquisition process is executed in step S2803, the pending display data HRn stored in the W register 104a is transferred to the first display data HRn in the work area 121 for specific control. Set to special figure reservation display area (step S2804). Thereby, it is possible to perform a display corresponding to the number of reservations in the first special figure reservation area 115 in the first special figure reservation display section 37c.

After that, the value of the second special figure reservation number counter 119 in the work area 121 for specific control is set to the E register 106b (step S2805), and the above-described reservation display acquisition processing (FIG. 80 (c)) is executed ( step S2806). Thereby, the pending display data HRn corresponding to the value of the second special figure pending number counter 119 can be acquired in the W register 104a.

After that, the pending display data HRn stored in the W register 104a is set in the second special figure pending display area in the work area 121 for specific control (step S2807). Thereby, it is possible to perform a display corresponding to the number of reservations in the second special figure reservation area 116 in the second special figure reservation display section 37d.

After that, set the value of the normal figure reservation number counter 127 in the work area 121 for specific control to the E register 106b (step S2808), and execute the above-described reservation display acquisition processing (FIG. 80 (c)) (step S2809 ). Thereby, the reservation display data HRn corresponding to the value of the normal diagram reservation number counter 127 can be acquired in the W register 104a.

Thereafter, the suspension display data HRn stored in the W register 104a is set in the normal diagram suspension display area in the work area 121 for specific control (step S2810). Thereby, it becomes possible to perform a display corresponding to the number of reservations in the normal diagram reservation area 125 in the normal diagram reservation display section 38b. After that, various display data output processes are executed (step S2811), and the present display control process ends.

According to this embodiment detailed above, the following excellent effects are obtained.

The lower 4 bits of the pending display data HRn obtained from the pending display data table 64x using the LDB instruction are loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and the 4th to 4th bits of the W register 104a are loaded. By masking the 7th bit (upper 4 bits) with "0", the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference of the data table set in the TP register 111 A process of specifying an acquisition start address corresponding to the address, a process of specifying an acquisition start bit corresponding to the 0th to 2nd bits (lower 3 bits) of the acquisition designation data, and a process of specifying the acquisition start bit corresponding to the acquisition designation data A process of loading the lower 4 bits of the pending display data HRn into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and setting the 4th to 7th bits (upper 4 bits) of the W register 104a to "0". can be executed with one instruction. These processes are executed by the LDB execution circuit 157 . As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

By using the LDB instruction, it is possible to acquire the lower 4 bits of the pending display data HRn by shifting the acquisition start bit in a manner corresponding to the pending number in the pending display data table 64x. Therefore, the data capacity of the pending display data table 64x can be reduced to 1 byte. A configuration in which all five types of pending display data HRn corresponding to five types of pending numbers are set in the pending display data table, and five types of pending display data HRn corresponding to the five types of pending numbers are set in the pending display data table. The data capacity of the pending display data table 64x can be reduced compared to the configuration in which the lower 4 bits of are set.

<Fourth Embodiment>
This embodiment differs from the first embodiment in that the final address of the second initialization table and the starting address of the maximum random number table are common addresses. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 81(a) is an explanatory diagram for explaining the data structure of the first initialization table 64y in this embodiment, and FIG. 81(b) is an explanation for explaining the data structure of the second initialization table 64z. FIG. 81(c) is an explanatory diagram for explaining the data configuration of the random number maximum value table 64α.

In the first initialization table 64y, similar to the first initialization table 64k (FIG. 18(a)) in the first embodiment, the unauthorized radio wave detection counter 133, the unauthorized magnetism detection counter 134, and the abnormal vibration detection counter 135 Along with being a data table for setting initial values, the second initialization table 64z is similar to the second initialization table 64m (FIG. 18(b)) in the first embodiment. It is a data table for clearing the watchdog timer counter 132 to "0". Further, the random number maximum value table 64α, similar to the random number maximum value table 64p (FIG. 23(a)) in the first embodiment, is a winning random number counter C1, a jackpot type counter C2, a reach random number counter C3, a random number initial value It is a data table used to set the maximum value data in the maximum value counters CN1 to CN6 corresponding to the counter C4, fluctuation type counter C5, and general electric random number counter C6.

As shown in FIG. 81(a), the first initialization table 64y contains "9400H" to It is set to the address of "9405H". As shown in FIG. 81(b), the second initialization table 64z contains "9406H" to It is set to the address of "940BH". As shown in FIG. 81(c), the random number maximum value table 64α is set to addresses "940BH" to "9413H" in the main ROM 64. As shown in FIG.

As shown in FIG. 81(b), the final address of the second initialization table 64z is "940BH", and as shown in FIG. 81(c), "940BH" is also the start address of the random number maximum value table 64α. 1-byte data of "63H" is set in the "940BH". "63H" is the maximum value data of the jackpot type maximum value counter CN2 as shown in FIG. ) is the end data.

In this way, in the area corresponding to one address in the main ROM 64, "63H" which is the maximum value data of the jackpot type maximum value counter CN2 and the end data of the data setting execution process (FIG. 82(b)) is stored. is set, separately from the area in which the maximum value data of the jackpot type maximum value counter CN2 is set in the main ROM 64, data setting execution processing (Fig. 82 (b)) For ending The total data capacity of the second initialization table 64z and the random number maximum value table 64α in the main ROM 64 is reduced compared to a configuration in which an area in which data is set is provided.

FIG. 82(a) is an explanatory diagram for explaining the program contents of the power-on setting process executed by the main CPU 63. FIG. As already described in the first embodiment, the power-on setting process is executed in step S118 of the main process (FIG. 15). As shown in FIG. 82(a), "2801" to "2806" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

Line numbers "2801" to "2802" are set with commands similar to line numbers "1001" to "1002" in the power-on setting process (FIG. 82(a)) in the first embodiment. there is Specifically, the command "LDT HL, 400H" is set at the line number "2801". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "400H" sets 12-bit numerical information "400H" as the transfer source. Content. As already explained in the first embodiment, the reference address (“9000H”) of the data table is set in the TP register 111 at step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 400H", "9400H" obtained by adding "9000H" set in the TP register 111 to "400H" set as the transfer source is obtained. HL register 107 is loaded. As a result, the HL register 107 can be set to the start address of the first initialization table 64y (FIG. 81(a)).

An instruction "XOR D, D" is set at the line number "2802". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma designates the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As already described with reference to FIG. 16A in the first embodiment, the high-order 1 byte of the address of the area and counter targeted for power-on setting processing is commonly "00H". The instruction at line number "2802" is an instruction for setting the common upper 1 byte ("00H") in the D register 106a.

The command "CALL 4BTS20" is set at the line number "2803". "4BTS20" is data setting execution processing (FIG. 82(b)), which will be described later. The instruction "CALL 4BTS20" is an instruction for calling a subroutine called data setting execution processing. At line number "2803", data setting execution processing is executed with the start address of the first initialization table 64y set in the HL register 107 and "00H" stored in the D register 106a. As already explained, the first initialization table 64 y is a data table for setting initial values to the unauthorized radio wave detection counter 133 , the unauthorized magnetism detection counter 134 , and the abnormal vibration detection counter 135 . By executing the data setting execution process at line number "2803", the fraudulent radio wave detection counter 133 is set to "5" as an initial value, and the fraudulent magnetism detection counter 134 is set to "10" as an initial value. The abnormal vibration detection counter 135 is initially set to "15". When the data setting execution processing subroutine called based on the command of line number "2803" is completed, the process proceeds to line number "2804". Although the details will be described later, the HL register 107 is set to "9405H" by executing the data setting execution process at the line number "2803".

The command "INC HL" is set at the line number "2804". "INC HL" is an arithmetic instruction to add 1 to the value of the HL register 107. By executing "INC HL" at line number "2804", the value of the HL register 107 is incremented by 1 and updated to "9406H". As a result, the HL register 107 can be set to the start address of the second initialization table 64z (FIG. 81(c)) in the main ROM 64. FIG.

The command "CALL 4BTS20" is set to the line number "2805" in the same way as the line number "2803" described above. At line number "2805", data setting execution processing is executed with the start address of the second initialization table 64z set in the HL register 107 and "00H" stored in the D register 106a. By executing the data setting execution process at the line number "2805", the power failure area 131 and the fraud monitoring timer counter 132 are cleared to "0". When the data setting execution processing subroutine called based on the command of line number "2805" is completed, the process proceeds to line number "2806".

The command "RET" is set at the line number "2806". As already explained, the power-on setting process is a subroutine executed in step S118 of the main process (FIG. 15). Therefore, by executing the command "RET", the process proceeds to step S119 of the main process (FIG. 15).

Next, the program contents of the data setting execution process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 82(b). As already explained, the data setting execution process is called by executing "CALL 4BTS20" at line numbers "2803" and "2805" of the power-on setting process (FIG. 82(a)). As shown in FIG. 82(b), "2901" to "2911" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

First, the case where the data setting execution process is executed at line number "2803" of the power-on setting process (FIG. 82(a)) will be described. As already explained, in line number "2803", the start address "9400H" of the first initialization table 64y (FIG. 81(a)) is stored in the HL register 107, and the illegal radio wave detection counter 133, The data setting execution process is executed in a state where the high-order 1 byte (“00H”) common to the address data of the illegal magnetism detection counter 134 and the abnormal vibration detection counter 135 is stored in the D register 106a.

In the data setting execution process executed at line number "2803", first, the data set in the address range of "9400H" to "9402H" in the first initialization table 64y (Fig. 81(a)) is used. The instructions of line numbers "2902" to "2911" are executed. As shown in FIG. 81(a), the initial value "5" is set to the illegal radio wave detection counter 133 in the upper 4 bits of the first area corresponding to the start address "9400H" of the first initialization table 64y. "0101B" is set as the initial setting data for setting, and the lower 4 bits of the first area are the initial setting data for setting the initial value "10" to the fraudulent magnetism detection counter 134. "1010B" is set. In the second area corresponding to "9401H" following "9400H", "21H", which is the lower 1 byte of the address of the fraudulent radio wave detection counter 133, is set. Also, in the third area corresponding to "9402H" following "9401H", "22H", which is the lower 1 byte of the address of the counterfeit magnetism detection counter 134, is set.

As shown in FIG. 82(b), "4BTS20" is set to the line number of "2901". This is not an instruction but data referred to when the developer of the pachinko machine 10 checks the program. Therefore, at line number "2901", the process proceeds to line number "2902" without executing any instruction.

The command "LDH WA, (HL+)" is set at the line number "2902". "LDH" is an LDH update command by the LDH update execution circuit 152, and "WA" is the contents specifying the WA register 104 as the transfer destination. "(HL+)" designates the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source, and the value of the HL register 107 is set to 1 after the data is loaded. The content instructs to update the address stored in the HL register 107 by addition. As described above, in the first initialization table 64y, the upper 4 bits of the first area corresponding to "9400H" are set to "0101B" as initialization data, and the lower 4 bits of the first area are set to "1010B" is set as initial setting data. Therefore, by executing "LDH WA, (HL+)" at line number "2902", "0101B", which is the upper four bits of the first area, is set to the lower four bits of the W register 104a. At the same time, the upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "1010B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "00000101B" for initial setting can be stored in the W register 104a, and the data "00001010B" for initial setting can be stored in the A register 104b. be able to. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9401H".

The command "LD E, (HL)" is set at the line number "2903". "LD" is the LD instruction, and "E" is the content specifying the E register 106b as the transfer destination. Also, "(HL)" is the content specifying the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source. As described above, the second area corresponding to "9401H" in the first initialization table 64y is set with "21H", which is the lower 1 byte of the address of the fraudulent radio wave detection counter 133. FIG. By executing "LD E, (HL)" at line number "2903", "21H" is stored in E register 106b. As a result, the DE register 106 can store the address "0021H" of the unauthorized radio wave detection counter 133. FIG.

The command "RET Z" is set at the line number "2904". "RET Z" in the line number "2904" terminates this data setting execution processing when end data is set in the E register 106b, and when end data is not set in the E register 106b. is an instruction to advance to the next line number. In this embodiment, "63H" is set as end data. As described above, since "21H" is stored in the E register 106b at the immediately preceding line number "2903", the process advances to line number "2905".

The command "INC HL" is set at the line number "2905". By executing "INC HL" at line number "2905", "1" is added to the value of the HL register 107 and the address stored in the HL register 107 is updated to "9402H". In this embodiment, the main MPU 62 does not have the LD update execution circuit 151 . The address stored in the HL register 107 is updated using an operation instruction "INC".

A command "LD (DE), W" is set at the line number "2906". "LD" is the LD instruction, "(DE)" is the content specifying the area corresponding to the address stored in the DE register 106 as the transfer destination, and "W" specifies the W register 104a as the transfer source. It is the content to be done. As already described, the DE register 106 stores "0021H", which is the address of the illegal radio wave detection counter 133, and the W register 104a stores "00000101B", which is data for initial setting. Therefore, by executing "LD (DE), W" at the line number "2905", the data for initial setting is loaded into the illegal radio wave detection counter 133. FIG. As a result, the initial value "5" can be set to the illegal radio wave detection counter 133. FIG.

At the line number "2907", the command "LD E, (HL)" is set, like the line number "2903". As described above, the HL register 107 stores "9402H". As already explained, in the first initialization table 64y (FIG. 81(a)), the third area corresponding to "9402H" is set to "22H", which is the lower 1 byte of the address of the counterfeit magnetism detection counter 134. ing. "22H" is loaded into the E register 106b by executing "LD E, (HL)" at line number "2907". As a result, the DE register 106 can store "0022H", which is the address of the unauthorized magnetism detection counter 134. FIG.

The command "RET Z" is set to the line number "2908" in the same way as the line number "2904". In "RET Z" in the line number "2908", similarly to "RET Z" in the line number "2904", this data setting execution process is executed when "63H", which is data for ending, is set in the E register 106b. , and proceeds to the next line number if the end data is not set in the E register 106b. As described above, since "22H" is stored in the E register 106b at the previous line number "2907", the process proceeds to line number "2909".

At the line number "2909", the command "INC HL" is set, like the line number "2905". By executing "INC HL" at line number "2909", "1" is added to the value of the HL register 107 and the address stored in the HL register 107 is updated to "9403H".

A command "LD (DE), A" is set at the line number "2910". "LD" is the LD instruction, "(DE)" is the content specifying the area corresponding to the address stored in the DE register 106 as the transfer destination, and "A" specifies the A register 104b as the transfer source. It is the content to be done. As already described, the DE register 106 stores "0022H", which is the address of the unauthorized magnetism detection counter 134, and the A register 104b stores "00001010B", which is the initial setting data. Therefore, by executing "LD (DE), A" at the line number "2910", the data for the initial setting is loaded into the unauthorized magnetism detection counter 134. FIG. As a result, "10" can be set as the initial value in the fraudulent magnetism detection counter 134 .

The command "JR 4BTS20" is set at the line number "2911". "JR" is a JR instruction as an unconditional jump instruction, and "4BTS20" is a content specifying the start address of data setting execution processing as a jump destination. By executing "JR 4BTS20", the process advances to line number "2901" of this data setting execution process.

After that, using the data set in the address range of "9403H" to "9405H" in the first initialization table 64y (FIG. 81(a)), the instructions of line numbers "2902" to "2911" are executed. be. As shown in FIG. 81(a), initial setting data for setting the abnormal vibration detection counter 135 to "5" as an initial value is stored in the upper 4 bits of the first area corresponding to "9403H" following "9402H". is set to "1111B". In addition, "0000B" is set as unused adjustment data in the lower 4 bits of the first area. In the second area corresponding to "9404H" following "9403H", "23H" which is the lower 1 byte of the address of the abnormal vibration detection counter 135 is set. Also, "00H" is set as end data in the third area corresponding to "9405H" following "9404H".

Returning to the description of the data setting execution process (Fig. 82(b)), at line number "2901", the process proceeds to line number "2902" without executing any command. As described above, in the first initialization table 64y, the initial setting data (“1111B”) is set in the upper 4 bits of the first area corresponding to the address “9403H”, and the adjustment data is set in the lower 4 bits. data ("0000B") is set. By executing "LDH WA, (HL)" at the line number "2902", "1111B", which is the upper four bits of the first area, is set to the lower four bits of the W register 104a. The upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "00001111B" for initialization can be stored in the W register 104a. "00000000B" for adjustment is stored in the A register 104b. Also, 1 is added to the value of the HL register 107 and the address stored in the HL register 107 is updated to "9404H".

As described above, "23H", which is the lower byte of the address corresponding to the abnormal vibration detection counter 135, is set in the second area corresponding to "9404H" in the first initialization table 64y. By executing "LD E, (HL)" at line number "2903", "23H" is stored in E register 106b. As a result, the state in which "0023H", which is the address of the abnormal vibration detection counter 135, is stored in the DE register 106 can be established. After that, at the line number "2904", the data stored in the E register 106b is "23H", not the end data ("63H"), so the process proceeds to the line number "2905". At line number "2905", "INC HL" is executed to add 1 to the value of the HL register 107 and update it to "9405H".

As already described, the DE register 106 stores "0023H", which is the address of the abnormal vibration detection counter 135, and the W register 104a stores "00001111B", which is the initial setting data. Therefore, the initial setting data is loaded into the abnormal vibration detection counter 135 by executing "LD (DE), W" at the line number "2906". As a result, the abnormal vibration detection counter 135 can be set to "15" as an initial value.

As described above, "63H", which is end data, is set in the third area corresponding to "9405H". By executing "LD E, (HL)" at line number "2907", "63H" is loaded into the E register 106b. After that, in the state where the end data ("63H") is stored in the E register 106b, "RET Z" is executed at the line number "2908", thereby ending this data setting process. As already described, when the data setting execution process ends at line number "2803" of the power-on setting process (FIG. 82(a)), the process proceeds to line number "2804".

Next, the case where the data setting execution process (FIG. 82(b)) is executed at the line number "2805" of the power-on setting process (FIG. 82(a)) will be described in detail. In line number "2805", "9406H", which is the start address of the second initialization table 64z, is stored in the HL register 107, and the power failure area 131, the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer counter 132 The data setting execution process is executed in a state in which the upper 1-byte data ("00H") common to the addresses in the upper area of the D register 106a is stored.

In the data setting process executed at the line number "2805", first, the data set in the address range of "9406H" to "9408H" in the second initialization table 64z is used to 2911" is executed. As shown in FIG. 81(b), data for clearing the power failure area 131 to "0" is stored in the upper 4 bits of the first area corresponding to the start address "9406H" of the second initialization table 64z. 0000B" is set, and "0000B" is set in the lower 4 bits of the first area as "0" clear data for clearing the lower area of the fraud monitoring timer counter 132 to "0". In the second area corresponding to "9407H" following "9406H", "01H" which is the lower 1 byte of the address of the power failure area 131 is set. Also, in the third area corresponding to "9408H" following "9407H", "08H", which is the lower 1 byte of the address corresponding to the lower area of the fraud monitoring timer counter 132, is set.

At line number "2901" of the data setting execution process (FIG. 82(b)), as already described, the process proceeds to line number "2902" without executing any command. As described above, "0" clear data ("0000B") is set in the upper 4 bits and lower 4 bits of the first area corresponding to "9406H" in the second initialization table 64z. Therefore, by executing "LDH WA, (HL+)" at line number "2902", "0000B", which is the upper four bits of the first area, is set to the lower four bits of the W register 104a. At the same time, the upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, data "00000000B" for "0" clearing can be stored in the W register 104a and the A register 104b. Also, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9407H".

As described above, in the second initialization table 64z, the second area corresponding to "9407H" is set with "01H", which is the lower 1 byte of the address of the power failure area 131. FIG. By executing "LD E, (HL)" at line number "2903", "01H" is stored in E register 106b. As a result, the DE register 106 can store the address "0001H" of the power failure area 131 . "RET Z" is set in the following line number "2904", but the data stored in the E register 106b is "01H", not the end data ("63H"). 2905”. At line number "2905", "INC HL" is executed to add 1 to the value of the HL register 107 and update it to "9408H".

As already described, the DE register 106 stores "0001H", which is the address of the power failure area 131, and the W register 104a stores "00000000B", which is data for clearing "0". Therefore, by executing "LD (DE), W" at the line number "2906", the "0" clear data is loaded into the power failure area 131, and the power failure area 131 is cleared to "0". be done. As already explained, the lowest bit of the power failure area 131 is provided with the power failure flag 131a. Therefore, the power failure flag 131a can be cleared to "0" by clearing the power failure area 131 to "0".

As shown in FIG. 81(b), in the third area corresponding to "9408H" in the second initialization table 64z (FIG. 81(b)), the lower 1 byte of the address in the lower area of the fraud monitoring timer counter 132 is stored. "08H" is set. "08H" is loaded into the E register 106b by executing "LD E, (HL)" at line number "2907". As a result, the DE register 106 can store "0008H", which is the address of the lower area of the fraud monitoring timer counter 132 . Although "RET Z" is set in the following line number "2908", the data stored in the E register 106b is "08H" and not the end data ("63H"). 2909”. At line number "2909", "INC HL" is executed to add 1 to the value of the HL register 107 and update it to "9409H".

As already explained, the DE register 106 stores "0008H" which is the lower area address of the fraud monitoring timer counter 132, and the A register 104b stores "00000000B" which is data for clearing "0". stored. Therefore, by executing "LD (DE), A" at the line number "2910", the data for clearing "0" is loaded into the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer The lower area of counter 132 is cleared to "0".

After that, "JR 4BTS20" is executed at line number "2911" to proceed to line number "2901" of this data setting execution process. Then, this time, the data set in the address range of "9409H" to "940BH" of the second initialization table 64z are used to execute the instructions of line numbers "2902" to "2911".

As shown in FIG. 81(b), data "0000B" for clearing the upper area of the fraud monitoring timer counter 132 to "0" is stored in the upper 4 bits of the first area corresponding to "9409H" following "9408H". ” is set. In addition, "0000B" is set as unused adjustment data in the lower 4 bits of the first area. In the second area corresponding to "940AH" following "9409H", "09H" which is the lower 1 byte of the address ("0009H") corresponding to the upper area of the fraud monitoring timer counter 132 is set. Also, "63H" is set as end data in the third area corresponding to "940BH" following "940AH".

Returning to the description of the data setting execution process (Fig. 82(b)), at line number "2901", the process proceeds to line number "2902" without executing any command. As described above, in the second initialization table 64z, data for clearing "0" ("0000B") is set in the upper 4 bits of the first area corresponding to the address "9409H", and the lower 4 bits is set with adjustment data (“0000B”). By executing "LDH WA, (HL+)" at the line number "2902", "0000B", which is the upper four bits of the first area, is set to the lower four bits of the W register 104a. The upper 4 bits of the W register 104a are masked with "0". The lower 4 bits of the A register 104b are set to "0000B", which are the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, data "00000000B" for "0" clearing can be stored in the W register 104a and the A register 104b. Also, the value of the HL register 107 is incremented by 1, and the address stored in the HL register 107 is updated to "940AH".

As described above, in the second initialization table 64z (FIG. 81(b)), the second area corresponding to 940AH contains "09H", which is the lower 1 byte of the address corresponding to the upper area of the fraud monitoring timer counter 132. is set. By executing "LD E, (HL)" at line number "2903", "09H" is stored in E register 106b. As a result, the state in which "0009H", which is the upper area address of the fraud monitoring timer counter 132, is stored in the DE register 106 can be achieved. "RET Z" is set in the following line number "2904", but the data stored in the E register 106b is "09H", not the end data ("63H"). 2905”.

At line number "2905", "INC HL" is executed to add 1 to the value of the HL register 107 and update it to "940BH". As a result, the HL register 107 stores "940BH", which is the final address of the second initialization table 64z and the start address of the maximum random number table 64α.

As already explained, the DE register 106 stores "0009H", which is the upper area address of the fraud monitoring timer counter 132, and the W register 104a stores "00000000B", which is data for clearing "0". stored. Therefore, by executing "LD (DE), W" at line number "2906", the data for clearing "0" is loaded into the upper area of the fraud monitoring timer counter 132. FIG. As a result, the upper area of the fraud monitoring timer counter 132 can be cleared to "0".

As described above, "63H", which is end data, is set in the third area corresponding to 940BH. "63H" is loaded into the E register 106b by executing "LD E, (HL)" at line number "2907". After that, with the end data ("63H") stored in the E register 106b, "RET Z" is executed at line number "2908", thereby ending this data setting execution process.

As already described, when the data setting execution process called at line number "2805" of the power-on setting process (FIG. 82(a)) is completed, the process proceeds to line number "2806". As already described with reference to FIG. 82(a), the command "RET" is set at the line number "2806", and the power-on setting process ends when the "RET" is executed. do.

In this way, in the state where "940BH", which is the final address of the second initialization table 64z and the start address of the maximum random value table 64α, is stored in the HL register 107, step S118 of the main process (FIG. 15) is executed. , the power-on setting process in step S119 is completed, and the random number maximum value setting process is executed in step S119. Therefore, the process for setting the start address of the maximum random number table 64α in the HL register 107 can be omitted at the start of the maximum random number setting process. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

The random number maximum value setting process (FIG. 83) is executed using the random number maximum value table 64α. As shown in FIG. 81(c), "9200H" in the maximum random number table 64p (FIG. 23(a)) in the first embodiment is stored at addresses "940BH" to "9413H" in the maximum random number table 64α. ” to “9208H” are set. Specifically, "940BH" is set to "63H", which is the maximum value data of the jackpot type counter C2, and "940CH" is set to "EEH", which is the maximum value data of the reach random number counter C3. "940DH" is set to "FAH", which is the maximum value data of the fluctuation type counter C5, and "940EH" is set to "C6H", which is the maximum value data of the general electrical random number counter C6. there is Also, "940FH" to "9410H" are set to "1F3FH" ("7999"), which is the maximum value data of the winning random number counter C1, and "9411H" to "9412H" are set to the random number initial value counter C4. "1F3FH", which is the maximum value data, is set. Furthermore, "00H" is set to "9413H" as data for ending the random number maximum value setting process.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. As already described in the first embodiment, the random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed using a program for specific control and data for specific control.

In the random number maximum value setting process, the instruction "LDY BC, 19H" is first executed (step S3001). "LDY" is the first LDY instruction by the first LDY execution circuit 156, "BC" is the content specifying the BC register 105 as the transfer destination, and "19H" is a 1-byte numerical value "19H" as the "transfer source". This is the content for setting information. As already described in the first embodiment, "0000H" is set in the IY register 109 as the specific control reference address in step S103 of the main process (FIG. 15). Therefore, by executing "LDY BC, 19H", "0019H" obtained by adding "0000H" set in the IY register 109 to "19H" set as the "transfer source" ” is loaded into the BC register 105 . Thereby, the address of the jackpot type maximum value counter CN2 in the work area 121 for specific control can be set in the BC register 105 .

As already described, this random number maximum value setting process (FIG. 83) is executed in a state where the HL register 107 stores "940BH", which is the start address of the random number maximum value table 64α. As a result, the processing for setting the start address in the HL register 107 can be omitted.

After performing the process of step S3001, the command "LD A, (HL)" is executed (step S3002). "LD" is the LD instruction, "A" is the content specifying the A register 104b as the transfer destination, and "(HL)" is stored in the area corresponding to the address stored in the HL register 107 as the transfer source. This is the content that specifies the maximum value data that is set. By executing "LD A, (HL)", the maximum value data ("63H") corresponding to the address data ("940BH") stored in the HL register 107 is loaded into the A register 104b. Thereby, the maximum value data to be set can be set in the A register 104b.

After that, the instruction "INC HL" is executed (step S3003). By executing "INC HL", "1" is added to the value of the HL register 107 and the address stored in the HL register 107 is updated to "940CH". Thereby, the maximum value data to be set can be updated.

The processing of steps S3002 to S3006 is repeatedly executed until an affirmative determination is made in step S3004, which will be described later. Every time the process of step S3003 is executed, the maximum value data of the jackpot type counter C2 → the maximum value data of the reach random number counter C3 → the maximum value data of the fluctuation type counter C5 → the maximum value data of the general electric random number counter C6 → the random number Lower 1 byte of maximum value data of counter C1→Higher 1 byte of maximum value data of random number counter C1→Lower 1 byte of maximum value data of random number initial value counter C4→Higher 1 byte of maximum value data of random number initial value counter C4 The maximum value data to be set is updated in byte order. When the process of step S3002 is executed with the address stored in the HL register 107 updated to "9413H", end data ("00H") is set in the A register 104b.

After performing the process of step S3003, in steps S3004 to S3006, the same processes as steps S303 to S305 of the random number maximum value setting process (FIG. 23(b)) in the first embodiment are executed. Specifically, first, it is determined whether or not "00H", which is end data, is set in the A register 104b (step S3004). If YES), this processing for setting the random number maximum value ends.

On the other hand, if the end data is not set in the A register 104b (step S3004: NO), maximum value data setting processing is executed (step S3005). In the maximum value data setting process, an instruction "LD (BC), A" is executed. "LD" is a load instruction, "(BC)" is the content specifying the counter to be set corresponding to the address stored in the BC register 105 as the transfer destination, and "A" is the A register 104b as the transfer source. is the content that specifies By executing "LD (BC), A", the maximum value data stored in the A register 104b is loaded into the counter selected as the setting object counter among the maximum value counters CN1 to CN6. Thereby, the maximum value data can be set in the setting target counter.

After that, setting target update processing is executed (step S3006). In the setting target update process, an instruction "INC BC" is executed. "INC" is an instruction to add "1" to an addition target, and "BC" is a content specifying the value of the BC register 105 as the addition target. By executing “INC BC”, “1” is added to the value of the BC register 105 . As a result, the maximum value counters CN1 to CN6 selected as setting target counters are updated. Every time the setting target update process is executed in step S3006, the jackpot type maximum value counter CN2 → reach maximum value counter CN3 → variation type maximum value counter CN5 → normal electric maximum value counter CN6 → hit maximum value The counters to be set are updated in the order of the lower area of the counter CN1→the upper area of the winning maximum value counter CN1→the lower area of the initial value maximum value counter CN4→the upper area of the initial value maximum value counter CN4.

After executing the setting target update process in step S3006, the process returns to step S3002, and the processes of steps S3002 to S3006 are repeated until the end data is stored in the A register 104b and an affirmative determination is made in step S3004. Execute. Thereby, the maximum value data can be set in the maximum value counters CN1 to CN6.

According to this embodiment detailed above, the following excellent effects are obtained.

The final address of the second initialization table 64z and the starting address of the random number maximum value table 64α are common addresses. "940BH" is the final address of the second initialization table 64z and the start address of the random number maximum value table 64α. In the area corresponding to the address of "940BH" in the main ROM 64, "63H", which is the maximum value data of the jackpot type maximum value counter CN2, is set. The "63H" is set as end data for the data setting execution process (FIG. 82(b)) executed in the power-on setting process (FIG. 82(a)). With the HL register 107 storing "940BH", which is the final address of the second initialization table 64z and the start address of the maximum random value table 64α, the power-on setting in step S118 of the main process (FIG. 15) is performed. The process ends, and the random number maximum value setting process is executed in step S119. Therefore, the process for setting the start address of the maximum random number table 64α in the HL register 107 can be omitted at the start of the maximum random number setting process. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

In the area corresponding to one address in the main side ROM 64, "63H", which is the maximum value data of the jackpot type maximum value counter CN2 and the end data of the data setting execution process (FIG. 82(b)), is set. Due to the configuration, data for ending the data setting execution process (Fig. 82 (b)) is set separately from the area where the maximum value data of the jackpot type maximum value counter CN2 is set in the main side ROM 64 The total data capacity of the second initialization table 64z and the random number maximum value table 64α in the main ROM 64 is reduced compared to a configuration in which an area is provided.

<Fifth Embodiment>
In this embodiment, the power-on setting process is completed in a state where "19H", which is the lower 1 byte of the address of the jackpot type maximum value counter CN2, is stored in the E register 106b, and the "19H" is used. This embodiment differs from the first embodiment in that a random number maximum value setting process is executed. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

FIG. 84(a) is an explanatory diagram for explaining the data configuration of the second initialization table 64β in this embodiment. The second initialization table 64β (FIG. 84(a)) is similar to the second initialization table 64m (FIG. 18(b)) in the above-described first embodiment, and contains "9406H" to "940BH" in the main ROM 64. is set to the address of

As shown in FIG. 84(a), in the third area corresponding to the address of "940BH", "19H" which is the lower 1 byte in the address of the jackpot type maximum value counter CN2 is set as end data. ing. As already described in the first embodiment, the power-on setting process (FIG. 17(c)) is executed in step S118 of the main process (FIG. 15). In the data setting execution process (FIG. 20(c)) executed at line number "1004" of the power-on setting process, the command "RET Z" is executed at line number "1107". At the line number "1107", when the end data is set in the E register 106b, the data setting execution process ends and the power-on setting process ends. After that, in step S119 of the main process (FIG. 15), a random number maximum value setting process is executed.

In this embodiment, "19H" is set as end data for the data setting execution process (FIG. 20(c)). Therefore, at line number "1107", when "19H" is set as end data in the E register 106b, the data setting execution process ends and the power-on setting process ends. Further, as already described in the first embodiment, "00H" is set in the D register 106a at line number "1002" of the power-on setting process (FIG. 17). Therefore, the random number maximum value setting process (step S119) can be started in a state where "0019H", which is the address of the jackpot type maximum value counter CN2, is stored in the DE register .

In the random number maximum value setting process (FIG. 84(b)) in this embodiment, the jackpot type maximum value counter CN2, which is set to the address of "0019H" in the work area 121 for specific control, to the address of "001AH" The set reach maximum value counter CN3, the fluctuation type maximum value counter CN5 set to the address of "001BH", the normal electric maximum value counter CN6 set to the address of "001CH", "001DH" Set of the winning maximum value counter CN1 set at the address of ~ "001EH" and the initial value maximum value counter CN4 set at the address of "001FH" ~ "0020H" (see Fig. 12 (b)) The address of the maximum value counter selected as the target counter is set in the DE register 106 . As described above, the random number maximum value setting process (FIG. 84(b)) is a state in which "0019H", which is the address of the jackpot type maximum value counter CN2, is stored in the DE register 106, that is, the jackpot type as the setting target counter. It is started with the maximum value counter CN2 set. Therefore, at the start of the random number maximum value setting process, the process of setting "0019H" to the DE register 106 in order to set the jackpot type maximum value counter CN2 as the setting target counter can be omitted. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 84(b). As already described in the first embodiment, the random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed using a program for specific control and data for specific control.

In the random number maximum value setting process, the instruction "LDT HL, 200H" is first executed (step S3101). "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is the content specifying the HL register 107 as the transfer destination, and "200H" sets 12-bit numerical information "200H" as the transfer source. Content. As already described in the first embodiment, the TP register 111 is set with "9000H", which is the reference address of the data table, in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 200H", "9200H" obtained by adding "9000H" set in the TP register 111 to "200H" set as the "transfer source" ” is loaded into the HL register 107 . As a result, the start address of the random number maximum value table 64p (FIG. 23(a)) can be set in the HL register 107. FIG.

Thus, by setting the start address of the maximum random number table 64p in the HL register 107 using the LDT instruction, the start address of the maximum random number table 64p can be set in the HL register 107 using the LD instruction. The data volume of the program for executing the maximum value setting start process can be reduced compared to the setting configuration.

After that, in steps S3102 and S3103, the same processes as steps S302 and S303 of the random number maximum value setting process (FIG. 23(b)) in the first embodiment are executed. Specifically, first, the instruction "LD A, (HL+)" is executed (step S3102). "LD" is an LD update command by the LD update execution circuit 151, "A" is the content specifying the A register 104b as the transfer destination, and "(HL+)" is stored in the HL register 107 as the transfer source. It specifies the maximum value data stored in the area corresponding to the address, and updates the address stored in the HL register 107 by adding 1 to the value of the HL register 107 after loading the maximum value data. It is the content that instructs to do. By executing "LD A, (HL+)", the maximum value data ("63H") corresponding to the address data ("9200H") stored in the HL register 107 is loaded into the A register 104b. Thereby, the maximum value data to be set can be set in the A register 104b. After loading the maximum value data, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9201H". Thereby, the maximum value data to be set can be updated.

In this way, by using the LD update instruction, the processing of loading the maximum value data selected as the setting target in the random number maximum value table 64p into the A register 104b, and the processing of loading the HL register 107 after loading the maximum value data. A process of adding 1 to the value and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data volume of the program for executing the random number maximum value setting process can be reduced compared to a configuration in which a plurality of instructions are set in the program for executing these two processes.

The processing of steps S3102 to S3105 is repeatedly executed until an affirmative determination is made in step S3103, which will be described later. Each time the process of step S3102 is executed, maximum value data of jackpot type counter C2 → maximum value data of reach random number counter C3 → maximum value data of fluctuation type counter C5 → maximum value data of general electric random number counter C6 → hit random number Lower 1 byte of maximum value data of counter C1→Higher 1 byte of maximum value data of random number counter C1→Lower 1 byte of maximum value data of random number initial value counter C4→Higher 1 byte of maximum value data of random number initial value counter C4 The maximum value data to be set is updated in byte order. When the process of step S3102 is executed with the address stored in the HL register 107 updated to "9208H", end data ("00H") is set in the A register 104b.

After executing the processing of step S3102, it is determined whether or not end data ("00H") is set in the A register 104b (step S3103). If (step S3103: YES), this processing for setting the random number maximum value (FIG. 84(b)) ends.

If a negative determination is made in step S3103, the command "LD (DE), A" is executed (step S3104). "LD" is a load instruction, "(DE)" is the content specifying the counter to be set corresponding to the address stored in the DE register 106 as the transfer destination, and "A" is the A register 104b as the transfer source. is the content that specifies By executing "LD (DE), A", the maximum value data stored in the A register 104b is loaded into the maximum value counter selected as the setting target counter among the maximum value counters CN1 to CN6. . Thereby, the maximum value data can be set in the setting target counter.

After that, setting target update processing is executed (step S3105). In the setting target update process, an instruction "INC DE" is executed. "INC" is an instruction to add "1" to an addition target, and "DE" is a content specifying the value of the DE register 106 as the addition target. By executing “INC DE”, “1” is added to the value of the DE register 106 . As a result, the maximum value counters CN1 to CN6 selected as setting target counters are updated. Every time the setting target update process is executed in step S3105, the maximum value counter for jackpot type CN2 → maximum value counter for reach CN3 → maximum value counter for variation type CN5 → maximum value counter for normal electric power CN6 → maximum value for winning The counters to be set are updated in the order of the lower area of the counter CN1→the upper area of the winning maximum value counter CN1→the lower area of the initial value maximum value counter CN4→the upper area of the initial value maximum value counter CN4.

After executing the setting target update process in step S3105, the process returns to step S3102, and the processes of steps S3102 to S3105 are repeated until the end data is stored in the A register 104b and the affirmative determination is made in step S3103. Execute. Thereby, the maximum value data can be set in the maximum value counters CN1 to CN6.

According to this embodiment detailed above, the following excellent effects are obtained.

In the random number maximum value setting process (FIG. 84(b)), the address of the maximum value counter selected as the counter to be set among the six maximum value counters CN1 to CN6 set in the specific control work area 121 is It is set in the DE register 106 . In the second initialization table 64β, "19H", which is the lower 1 byte in the address of the jackpot type maximum value counter CN2, is set as end data for the data setting execution process (FIG. 20(c)). The power-on setting process is performed in a state where "0019H", which is the address of the jackpot type maximum value counter CN2, is stored in the DE register 106, that is, in a state where the jackpot type maximum value counter CN2 is set as the setting target counter. Upon completion, the random number maximum value setting process is started. Therefore, at the start of the random number maximum value setting process, the process of setting "0019H" to the DE register 106 in order to set the jackpot type maximum value counter CN2 as the setting target counter can be omitted. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

<Sixth embodiment>
This embodiment differs from the first embodiment in that the main MPU 62 executes a special LDB instruction. The configuration different from that of the first embodiment will be described below. Note that the description of the same configuration as that of the first embodiment is basically omitted.

In this embodiment, in order to acquire the start addresses SA0 to SA6 corresponding to the value of the special special electric counter in the work area 121 for specific control to the HL register 107, step S3208 of the address acquisition execution process (FIG. 88) described later is performed. , a special LDB instruction "LDB HL, (HL).A" is executed. FIG. 85(a) is an explanatory diagram for explaining the configuration of the main MPU 62 in this embodiment. As shown in FIG. 85(a), the main MPU 62 has a special LDB execution circuit 201 which is a dedicated circuit for executing special LDB instructions, and the main CPU 63 can execute the special LDB instructions.

The special LDB instruction uses the upper 12 bits (4th to 15th bits) of the 2-byte acquisition data designation data to calculate the acquisition start address, and the lower 4 bits of the acquisition data designation data. The acquisition start bit is calculated using the data of (0th to 3rd bits).

Like the instruction code of the LDB instruction in the first embodiment, the instruction code of the special LDB instruction has a configuration of "LDB transfer destination, acquisition data designation, acquisition bit number designation". A pair register is set as a "transfer destination" in the special LDB instruction. The pair register set as the “transfer destination” in the special LDB instruction is the HL register 107 . Note that the WA register 104, the BC register 105, or the DE register 106 may be set as the "transfer destination" pair register in the LDB instruction.

In the special LDB instruction, data of any number of bits from 1 to 16 is loaded into the "transfer destination" HL register 107 . When data of any number of bits from 1 to 15 is loaded into the HL register 107 as the “destination”, the data is loaded into the lower bits of the HL register 107 and the upper bits of the HL register 107 are loaded with the data. side bits are masked with '0'. For example, when 12-bit data is loaded into the “transfer destination” HL register 107, the data is loaded into the 0th to 11th bits existing on the lower side of the HL register 107, and The existing 12th to 15th bits are masked with "0".

In the special LDB instruction, "(HL)" is set as "acquisition data designation". In the special LDB instruction, based on the 2-byte data stored in the HL register 107 set as "acquisition data designation" (hereinafter referred to as "acquisition data designation data"), it is transferred to the "transfer destination" register. A data acquisition start address and acquisition start bit number are specified.

In the special LDB instruction, a general-purpose register storing any number from "0" to "15" is set as "specify number of bits to be acquired". The general-purpose register set as "specify the number of bits to be acquired" in the special LDB instruction is the A register 104b. Note that the B register 105a, the C register 105b, the D register 106a, or the E register 106b may be set as general-purpose registers for "specifying the number of bits to be acquired" in the special LDB instruction.

The "number of acquired bits designation" is data (number of acquired bits designation data) for designating the number of bits of data to be loaded into the HL register 107 of the "transfer destination". In the special LDB instruction, the special LDB execution circuit 201 performs an operation to add "1" to the value of the A register 104b set to "specify the number of bits to be obtained", and the number of bits corresponding to the operation result is obtained. The data is loaded into the "destination". That is, in the "destination", data of the number of bits corresponding to the value obtained by adding "1" to the "designation of number of bits to be obtained" is loaded. Therefore, a value obtained by subtracting "1" from the number of bits of data to be loaded into the "transfer destination" is set in the "specify number of bits to be obtained". Specifically, when the A register 104b storing the numerical value "11" is set as the "specify number of bits to be acquired", "1" is added to the "11" in the "transfer destination" register. 12-bit data is loaded.

By executing the special LDB instruction, the data of the number of bits corresponding to the "specify number of bits to be acquired" from the acquisition start bit of the area corresponding to the acquisition start address in the main ROM 64 is loaded into the "transfer destination" register. be.

85(b) to 85(e) are explanatory diagrams for explaining the process of calculating the acquisition start address and the acquisition start bit number from the acquisition data designation data. As described above, the upper 12 bits (4th to 15th bits) of the 2-byte acquisition data specification data are data for specifying the acquisition start address, and the lower 4 bits (0th to 3rd bits) are This is data for specifying the acquisition start bit. The acquisition start address is the reference address (9000H) of the data table stored in the TP register 111 for the data (quotient data after division) obtained by dividing the acquisition data designation data by "16" (10000H). This is the address obtained by adding. As already explained in the first embodiment, "9000H" is set in the TP register 111 as the reference address of the data table. "16" (10000H) used for division of acquired data designation data is a numerical range ("0 ” to “15”), which is the value obtained by adding “1” to the maximum value “15”, which is the fourth power of “2”. As already explained in the first embodiment, when a 2-byte binary number is divided by the n-th power of "2" (n is any integer from 1 to 15), the n-th bit in the 2-byte binary number is ∼ The information of "0" or "1" set in the 15th bit is shifted to the lower n bits and set to the lower (16-n) bits in the quotient data after the division, and "0" is set in the upper n bits ((16-n) bit to 15th bit) of the quotient data. In the LDB instruction in this embodiment, the acquisition data designation data, which is a 2-byte binary number, is divided by "16" (10000H), which is "2" to the fourth power. When the obtained data designation data is divided by "16", the "0" or "1" information set in the 4th to 15th bits of the obtained data designation data is shifted to the lower 4 bits and becomes The lower 12 bits (0th to 11th bits) of the quotient data are set, and "0" is set to the upper 4 bits (12th to 15th bits) of the quotient data after the division.

Specifically, as shown in FIG. 85(b), a case where "180CH" is set as acquisition data designation data will be described. As shown in FIG. 85(c), "16" (10000H ), the "000110000000" set in the 4th to 15th bits of the acquired data specifying data is shifted to the lower side by 4 bits, and the quotient data after division is The lower 12 bits (0th to 11th bits) are set, and "0" is set to the higher 4 bits (12th to 15th bits) in the quotient data after the division. As a result, the quotient data after the division is "0000000110000000" as shown in FIG. 85(c). After that, by adding the reference address (“9000H”) of the data table stored in the TP register 111 to the quotient data after the division, the acquisition start address (“9180H”) is obtained as shown in FIG. ”) is calculated. The data of the 4th to 15th bits in the acquisition data designation data (FIG. 85(b)) are set to the 0th to 11th bits of the acquisition start address, and the 12th to 15th bits of the acquisition start address are set to is set to "1001B" ("9H") which is data of the 12th to 15th bits in the reference address of the data table.

In this way, in the special LDB instruction, the data of the 4th to 15th bits in the acquisition data designation data are set to the 0th to 11th bits of the acquisition start address, and the 12th to 15th bits of the acquisition start address are set to The data of the 12th to 15th bits at the reference address of the data table stored in the TP register 111 are set.

The acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00001111B" ("0FH"). "00001111B" used for calculation for calculating the acquisition start bit is obtained by separating only the lower 4 bits (0th to 3rd bits) of the acquired data specifying data from the acquired data specifying data of 2 bytes. It is data to make it available. In the AND operation of the lower 1 byte of the acquired data designation data and "00001111B", the data of the lower 4 bits (0th to 3rd bits) in the acquired data designation data becomes the lower 4 bits (0th to 3rd bits) of the operation result. 3 bits), and the high-order 4 bits (4th to 7th bits) of the calculation result are set to "0". Specifically, as shown in FIG. 85(b), when "180CH" is set as the acquisition data designation data, the lower 1 byte of the acquisition data designation data is "00001100B" ("0CH"). In this case, the acquisition start bit calculated by the AND operation of the lower 1 byte of the acquisition data designation data and "00001111B" is "00001100B" ("12") as shown in FIG. 85(e). . The 0th to 3rd bits of the acquisition start bit are set to the data of the 0th to 3rd bits in the acquisition data designation data (FIG. 85(b)), and the 4th to 7th bits of the acquisition start bit are set. is set to "0".

The instruction code of the special LDB instruction does not include data for designating the use of "00001111B" in the calculation for calculating the acquisition start bit. A logical AND operation of the lower 1 byte of the acquisition data designation data and "00001111B" is automatically executed by the special LDB execution circuit 201 when the special LDB instruction set in the program is executed. For this reason, compared to the configuration in which it is necessary to set data for designating the use of "00001111B" in the operation for calculating the acquisition start bit in the instruction code of the special LDB instruction, the instruction of the special LDB instruction The data capacity of the code can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

The acquisition start bit in the special LDB instruction is any integer from "0" to "15". First, the case where the acquisition start bit is any integer from "0" to "7" will be described. When the acquisition start bit is "n" (n is an integer of 0 to 7), the nth bit and after (nth bit) of the 0th to 7th bits of the area corresponding to the acquisition start address in the main ROM to the 7th bit) are transferred to the HL register 107 of the "transfer destination". If the number of "0" or "1" data existing after the acquisition start bit (nth bit to 7th bit) in the area corresponding to the acquisition start address is less than the number of bits acquired this time , the data after the acquisition start bit at the acquisition start address (data from the nth bit to the 7th bit at the acquisition start address) and the data after the 0th bit at the address next to the acquisition start address are the "transfer destination". is loaded into Here, the address next to the acquisition start address is an address obtained by adding "1" to the acquisition start address.

For example, the TP register 111 stores "9000H" as the reference address, the HL register 107 stores "1800H" ("6144") as acquisition data designation data, and the A register 104b stores acquisition bit number designation data. When a special LDB instruction of "LDB HL, (HL).A" is executed in a state in which "BH" (11) is stored as , the "transfer destination" becomes the HL register 107. FIG. As already explained, the data for specifying the acquisition start address is set in the high-order 12 bits of the acquisition data specification data, and the data for specifying the acquisition start bit is set in the low-order 4 bits of the acquisition data specification data. is set. The acquisition start address is "9180H" obtained by adding the reference address ("9000H") to "0180H" ("384") obtained by dividing the acquisition data designation data by "16". The acquisition start bit becomes "00000000B" ("0") by extracting the lower 4 bits of the acquisition data designation data. As already explained, the acquisition start bit is calculated by performing a logical product operation of the lower 1 byte (“00000000B”) of the acquisition data designation data and “00001111H”. The number of acquired bits is "0CH" ("12") obtained by adding "1" to "0BH". For this reason, when a special LDB instruction "LDB HL, (HL).A" is executed in this state, in the area corresponding to the acquisition start address "9180H" (see FIG. 31) in the main ROM 64, 8-bit data set after the acquisition start bit (0th bit), and set after the 0th bit in the area corresponding to "9181H", which is the address next to the acquisition start address 4-bit data is set in the 0th to 11th bits of the HL register 107, which is the transfer destination, and the 12th to 15th bits of the HL register 107 are masked with "0". Specifically, the 0th to 7th bit data of the area corresponding to "9180H" and the 0th to 3rd bit data of the area corresponding to "9181H" are stored in the 0th to 11th bits of the HL register 107. set.

Next, a case where the acquisition start bit is any integer from "8" to "15" will be described. When the acquisition start bit is "m" (m is an integer of 8 to 15), the (m-8)th bit of the 0th to 7th bits of the area corresponding to the address next to the acquisition start address in the main ROM 64 ) and subsequent bits ((m−8)th bit to 7th bit) are transferred to the HL register 107 of the “transfer destination” for the number of acquired bits. As described above, the address next to the acquisition start address is an address obtained by adding "1" to the acquisition start address. The number of "0" or "1" data present in the (m-8)th and subsequent bits ((m-8)th to 7th bits) in the area corresponding to the address next to the acquisition start address is less than the number of bits acquired this time, the data after the (m-8)th bit at the address next to the acquisition start address (the (m-8)th bit at the address next to the acquisition start address to the 7-bit data) and the data after the 0th bit at the address next to the acquisition start address are loaded into the "transfer destination". Here, the next address after the acquisition start address is an address obtained by adding "2" to the acquisition start address.

For example, the TP register 111 stores "9000H" as the reference address, the HL register 107 stores "180CH" ("6156") as acquisition data designation data, and the A register 104b stores acquisition bit number designation data. When a special LDB instruction of "LDB HL, (HL).A" is executed in a state in which "BH" (11) is stored as , the "transfer destination" becomes the HL register 107. FIG. As already explained, the data for specifying the acquisition start address is set in the high-order 12 bits of the acquisition data specification data, and the data for specifying the acquisition start bit is set in the low-order 4 bits of the acquisition data specification data. is set. The acquisition start address is "9180H" obtained by adding the reference address ("9000H") to "0180H" ("384") obtained by dividing the acquisition data designation data by "16". The acquisition start bit becomes "00001100B" ("12") by extracting the lower 4 bits of the acquisition data designation data. As already explained, the acquisition start bit is calculated by performing a logical product operation of the lower 1 byte (“00001100B”) of the acquisition data designation data and “00001111H”. The number of acquired bits is "0CH" ("12") obtained by adding "1" to "0BH". The acquisition start bit is "12" and exceeds "7". Therefore, when the special LDB instruction "LDB HL, (HL).A" is executed in this state, the address "9181H" ( 31), and 4-bit data set after the (12-8)th bit (4th bit) in the area corresponding to the area corresponding to "9182H", which is the next address after the acquisition start address. and the 8-bit data set after the 0th bit in the area corresponding to . The fifteenth bit is masked with "0". Specifically, the 4th to 7th bit data of the area corresponding to "9181H" and the 0th to 7th bit data of the area corresponding to "9182H" are stored in the 0th to 11th bits of the HL register 107. set.

FIGS. 86(a) and 86(b) are explanatory diagrams for explaining how the start address SA1 is acquired from the special special electric address table 64q to the HL register 107. FIG. As already explained in the first embodiment, in the special special electric address table 64q (FIG. 31), the 4th to 7th bits of "9181H" and the 0th to 7th bits of "9182H" have the start address SA1 is set. By executing "LDB HL, (HL).A", the lower 12 bits of the start address SA1 are loaded into the lower 12 bits of the HL register 107 as shown in FIG. 86(a). In the address acquisition execution process (FIG. 88) described later, after executing the LDB instruction, the value of the HL register 107 is added to the reference address of the data table, ie, "9000H". As a result, the entire start address SA1 can be obtained in the HL register 107, as shown in FIG. 86(b).

By using a special LDB instruction, a process of specifying the acquisition start address corresponding to the 4th to 15th bits of the 2-byte acquisition data designation data, and the lower 4 bits (0th to 3rd bits) of the acquisition designation data. ), the process of loading the data for the number of bits to be acquired from the acquisition start bit of the acquisition start address into the "transfer destination" register, and the "transfer destination" register. and a process of masking with "0" the bits present on the upper side of the loaded data can be executed with one instruction. These processes are executed by the special LDB execution circuit 201. FIG. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

Next, the program contents of the special special electric address acquisition process executed by the main side CPU 63 will be described with reference to the explanatory diagram of FIG. 86(c). As already described in the first embodiment, the special figure special electric address acquisition process is executed in step S902 of the special figure special electric control process (FIG. 30). As shown in FIG. 86(c), "3001" to "3005" are set as line numbers in this program. Program instructions are executed in ascending order of line number, except when a call or jump instruction is executed.

In the line numbers "3001" to "3002", commands similar to "1601" to "1602" in the special special electric address acquisition process (FIG. 33(a)) in the first embodiment are set. . Specifically, the command "LD W, (TZTDCNT)" is set at the line number "3001". "LD" is the LD instruction, and "W" is the content specifying the W register 104a as the transfer destination. As already described in the first embodiment, "TZTDCNT" is the address of the special special electric counter in the work area 121 for specific control, and "(TZTDCNT)" is the data stored in the special special electric counter. This is the content to be transferred to the "transfer destination". As in the first embodiment, any numerical data of 0 to 6 is stored in the special special electric counter. By executing "LD W, (TZTDCNT)", the data (1 byte) of the special special electric counter is loaded into the "transfer destination" W register 104a.

The command "LD B, 0CH" is set at the line number "3002". "LD" is the LD instruction, "B" is the content specifying the B register 105a as the transfer destination, and "0CH" is the content specifying numerical data "0CH" ("12") as the "transfer source". is. "0CH" is the number of bits of address data acquired from the special figure special electric address table 64q in the address acquisition execution process (FIG. 88) described later. By executing "LD B, 0CH", the number of bits ("12") of the address data acquired from the special special electric address table 64q is set in the "transfer destination" B register 105a.

A command "LD HL, TBL_TZTD2_B" is set in the line number "3003". "LD" is the LD instruction, and "HL" is the content specifying the HL register 107 as the transfer destination. "TBL_TZTD2_B" is 2-byte numerical data for making the acquisition start address the start address of the special special electric address table 64q, specifically "1800H". By executing “LD HL, TBL_TZTD2_B”, “1800H” is loaded into the “transfer destination” HL register 107 .

“TBL_TZTD2_B” is calculated by the formula “{(start address of special special electric address table 64q)−9000H}×16”. FIGS. 86(d) to 86(f) are explanatory diagrams for explaining the process of calculating "TBL_TZTD2_B". By subtracting "9000H", which is the reference address of the data table, from "9180H" (Fig. 86(d)), which is the start address of the special special electric address table 64q, the data after the subtraction is obtained as shown in Fig. 86(e). The data of the 0th to 11th bits of the start address “9180H” (FIG. 86(d)) are set to the 0th to 11th bits of . Then, by multiplying the subtracted data by "16" (10000H), "TBL_TZTD2_B" is calculated as shown in FIG. 86(f). "16" used for the multiplication for calculating "TBL_TZTD2_B" is a numerical range (" 0” to “15”) is the value obtained by adding “1” to “15” which is the maximum value. As already explained in the first embodiment, when a 2-byte binary number is multiplied by "2" to the nth power (n is any integer from 1 to 15), the 0th bit in the 2-byte binary number is ~ "0" or "1" information set in the (15-n)th bit is shifted to the upper n-bit side and set in the upper (16-n) bit in the data after multiplication, and "0" is set in the lower n bits (0th bit to (n-1)th bit) in the data after multiplication.

In the calculation of "TBL_TZTD2_B", the value obtained by subtracting "9000H", which is the reference address of the data table, from the start address of the special special electric address table 64q (data after subtraction) is "16" which is the fourth power of "2". ” is multiplied. As a result, the data of the 0th to 12th bits in the data after subtraction (FIG. 86(e)) is shifted to the upper 4 bits, and the data after multiplication (FIG. 86(f)) in the upper 12 bits (4th to the 15th bit), and "0" is set to the lower 4 bits (the 0th bit to the 3rd bit) in the data after the multiplication. As shown in FIG. 86(f), the 4th to 15th bits in "TBL_TZTD2_B", which is the data after multiplication by "16" (data after multiplication), contains the start address "9180H" ((d) in FIG. 86). )) are set to the 0th to 11th bit data. As already explained, the acquisition start address in the special LDB instruction is calculated by dividing the acquisition data designation data by 16 (10000H) and adding the reference address of the data table, 9000H. . In addition, as already explained, in the process of calculating the acquisition start address in the special LDB instruction, the acquisition data designation data is divided by "16", so that the upper 12 bits (4th to 15th bits) in the acquisition data designation data The data set in is shifted to the lower 4 bits. When a special LDB instruction is executed with "TBL_TZTD2_B" derived by shifting the 0th to 12th bits of the data after subtraction (FIG. 86(e)) to the upper 4-bit side as acquisition data designation data, "TBL_TZTD2_B" is divided by "16" in the process of calculating the acquisition start address. In the quotient data after division, the data of the 0th to 12th bits in the data after subtraction, which has been shifted to the upper 4-bit side, is shifted to the lower 4-bit side. Then, the start address of the special figure special electric address table 64q is calculated as the acquisition start address by the calculation of adding "9000H" which is the reference address of the data table to the quotient data after the division.

In this way, "TBL_TZTD2_B" calculated by the formula "{(starting address of special special electric address table 64q) - 9000H} x 16" starts acquiring the starting address of special special electric address table 64q with a special LDB command. Acquisition data designation data for use as an address. By setting "TBL_TZTD2_B" as the acquisition data designation data, the start address of the special special electric address table 64q can be used as the acquisition start address of the special LDB instruction.

In the address acquisition execution process (FIG. 88) to be described later, when the value of the special special electric counter is "0", "1800H" stored in the HL register 107 is used as acquisition data designation data. On the other hand, when the value of the special special electric counter is "1" or more, the numerical information stored in the HL register 107 is the numerical information corresponding to the value of the special special electric counter before the special LDB instruction is executed. is changed to

The command "CALLS LDBADGET20" is set to the line number "3004" in the special figure special electric address acquisition process (FIG. 86(c)). "LDBADGET20" is address acquisition execution processing (FIG. 88), which will be described later. The instruction "CALLS LDBADGET20" is an instruction for calling a subroutine called address acquisition execution processing. Details will be described later, but by executing the address acquisition execution process at line number "3004", the start address (one of SA0 to SA6) corresponding to the value of the special special electric counter is set in the HL register 107. be. When the subroutine of the address acquisition execution process is completed, the process proceeds to the line number "3005".

A command "RET" is set at the line number "3005". As already described in the first embodiment, the special figure special electric address acquisition process is a subroutine executed in step S902 of the special figure special electric control process (FIG. 30). Therefore, when the command "RET" is executed, the process proceeds to step S903 of the special figure special electric control process (FIG. 30).

Next, prior to the description of the address acquisition execution process (FIG. 88), a manner of acquiring the lower 12-bit data in the start addresses SA0 to SA6 corresponding to the value of the special special electric counter from the special special electric address table 64q will be described. . FIG. 87 is an explanatory diagram for explaining the correspondence relationship between the value of the special special electric counter and the start addresses SA0 to SA6 acquired by the HL register 107. FIG.

As already described with reference to FIG. 31 in the first embodiment, the special special electric address table 64q is stored in the address range of "9180H" to "918AH" in the main ROM 64. In the address table 64q, the lower 12-bit data of the start addresses SA0 to SA6 corresponding to the value of the special special electric counter are set.

As already explained, "1800H" is stored in the HL register 107 at line number "3003" of the special figure special electric address acquisition process (FIG. 86(c)). As shown in FIG. 87, when the value of the special special electric counter is "0", the special LDB command is executed with the "1800H" as the acquired data designating data. In the special special electric address table 64q, the lower 12-bit data of the start address SA0 corresponding to the value of "0" of the special special electric counter are the 0th to 7th bits of "9180H" and the 0th to 7th bits of "9181H". It is set in the 3rd bit. The lower 12-bit data of the start address SA0 is set at a position that can be obtained by setting the 0th bit of the area corresponding to "9180H" as the acquisition start position and setting the number of acquisition bits to "12". . The low-order 12-bit data of the start address SA0 is obtained when the acquisition start address is Acquired by setting the acquisition start bit to "0" together with "9180H".

In the special figure special electric address table 64q, the lower 12-bit data of the start addresses SA1 to SA6 corresponding to the special figure special electric counter values "1" to "6" have the special figure special electric counter value "0". Based on the acquisition start position (the 0th bit of the area corresponding to "9180H") in the case, the acquisition start position is shifted backward by "(number of bits acquired) x (value of special special electric counter)" bits. It is set to a position that can be obtained by In this embodiment, the “rear side” as the direction in which the acquisition start position is shifted is the direction in which the acquisition start bit increases (direction from the 0th bit to the 7th bit) and the direction in which the acquisition start address increases. (direction from "9180H" to "918AH").

As shown in FIG. 31, the lower 12-bit data of the start address SA1 corresponding to the value of "1" of the special special electric counter are the 4th to 7th bits of "9181H" and the 0th to 7th bits of "9182H". It is set to 7 bits. The lower 12-bit data of the start address SA1 is based on the acquisition start position when the value of the special special electric counter is "0", and the acquisition start position is "number of acquired bits x 1" bits (12 bits). It is set at a position that can be obtained by shifting it backward. The lower 12-bit data of the start address SA1 is obtained by setting the acquisition start position to the fourth bit of the area corresponding to the address ("9181H") next to "9180H" and setting the acquisition bit number to "12". It is set in a retrievable position. As shown in FIG. 87, the lower 12-bit data of the start address SA1 is a special LDB instruction (“LDB HL, (HL). ), the acquisition start address becomes "9180H" and the acquisition start bit number becomes "12".

As shown in FIG. 31, the lower 12-bit data of the start address SA2 corresponding to the value "2" of the special special electric counter are the 0th to 7th bits of "9183H" and the 0th to 7th bits of "9184H". It is set to 3 bits. The lower 12-bit data of the start address SA2 is based on the acquisition start position when the value of the special special electric counter is "0", and the acquisition start position is "number of acquired bits x 2" bits (24 bits). It is set at a position that can be obtained by shifting it backward. The lower 12-bit data of the start address SA2 is obtained by setting the 0th bit of the area corresponding to the address next to "9182H" ("9183H") as the acquisition start position and setting the acquisition bit number to "12". It is set in a retrievable position. As shown in FIG. 87, the lower 12-bit data of the start address SA2 is a special LDB instruction (“LDB HL, (HL). ), the acquisition start address becomes "9182H" and the acquisition start bit number becomes "8".

As shown in FIG. 31, the lower 12-bit data of the start address SA3 corresponding to the value of "3" of the special special electric counter are the 4th to 7th bits of "9184H" and the 0th to 7th bits of "9185H". It is set to 7 bits. The lower 12-bit data of the start address SA3 is based on the acquisition start position when the value of the special special electric counter is "0", and the acquisition start position is "number of acquired bits x 3" bits (36 bits). It is set at a position that can be obtained by shifting it backward. The lower 12-bit data of the start address SA3 is set at a position that can be obtained by setting the fourth bit of the area corresponding to "9184H" as the acquisition start position and setting the number of acquisition bits to "12". . As shown in FIG. 87, the lower 12-bit data of the start address SA3 is a special LDB instruction (“LDB HL, (HL). ), the acquisition start address becomes "9184H" and the acquisition start bit becomes "4".

As shown in FIG. 31, the lower 12-bit data of the start address SA4 corresponding to the value of "4" of the special special electric counter are the 0th to 7th bits of "9186H" and the 0th to 7th bits of "9187H". It is set to 4 bits. The lower 12-bit data of the start address SA4 is based on the acquisition start position when the value of the special special electric counter is "0", and the acquisition start position is "number of acquired bits x 4" bits (48 bits). It is set at a position that can be obtained by shifting it backward. The lower 12-bit data of the start address SA4 is set at a position that can be obtained by setting the 0th bit of the area corresponding to "9186H" as the acquisition start position and setting the number of acquisition bits to "12". . As shown in FIG. 87, the lower 12-bit data of the start address SA4 is a special LDB instruction (“LDB HL, (HL). ), the acquisition start address becomes "9186H" and the acquisition start bit becomes "0".

As shown in FIG. 31, the lower 12-bit data of the start address SA5 corresponding to the value of "5" of the special special electric counter are the 4th to 7th bits of "9187H" and the 0th to 7th bits of "9188H". It is set to 7 bits. The lower 12-bit data of the start address SA5 is based on the acquisition start position when the value of the special special electric counter is "0", and the acquisition start position is "number of acquired bits x 5" bits (60 bits). It is set at a position that can be obtained by shifting it backward. The lower 12-bit data of the start address SA5 is obtained by setting the acquisition start position to the fourth bit of the area corresponding to the address ("9187H") next to "9186H" and the acquisition bit number to "12". It is set in a retrievable position. As shown in FIG. 87, the lower 12-bit data of the start address SA5 is a special LDB instruction (“LDB HL, (HL). ), the acquisition start address becomes "9186H" and the acquisition start bit number becomes "12".

As shown in FIG. 31, the lower 12-bit data of the start address SA6 corresponding to the value of "6" of the special special electric counter are the 0th to 7th bits of "9189H" and the 0th to 7th bits of "918AH". It is set to 4 bits. The lower 12-bit data of the start address SA6 is based on the acquisition start position when the value of the special special electric counter is "0", and the acquisition start position is "number of acquired bits x 6" bits (72 bits). It is set at a position that can be obtained by shifting it backward. The lower 12-bit data of the start address SA6 is obtained by setting the acquisition start position to the 0th bit of the area corresponding to the address ("9189H") next to "9188H" and the acquisition bit number to "12". It is set in a retrievable position. As shown in FIG. 87, the lower 12-bit data of the start address SA6 is a special LDB instruction (“LDB HL, (HL). ), the acquisition start address becomes "9188H" and the acquisition start bit number becomes "8".

Next, the address acquisition execution processing executed by the main CPU 63 will be described with reference to the flowchart of FIG. The address acquisition execution process is executed at the line number "3004" of the special figure special electric address acquisition process (FIG. 86(c)). The address acquisition execution process is executed using a program for specific control and data for specific control.

As already explained, in the line number "3003" of the special special electric address acquisition process (Fig. 86(c)), the HL register 107 contains the acquired data designation data (" 1800H") is stored. The processing of steps S3201 to S3205 is executed to change the acquisition data designation data stored in the HL register 107 to data corresponding to the value of the special special electric counter.

In steps S3201 to S3203 in the address acquisition execution process, the same instructions as line numbers "1702" to "1704" in the address acquisition execution process (FIG. 33(e)) in the first embodiment are executed. Specifically, first, the command "LD A, B" is executed (step S3201). "LD" is the LD instruction, "A" is the content specifying the A register 104b as the transfer destination, and "B" is the content specifying the B register 105a as the transfer source. As already explained, in the special special electric address acquisition process (Fig. 86(c)), "0CH" ("12") specifying the number of bits to be acquired from the special special electric address table 64q (number of acquisition bits) is stored in the B register 105a. ) is set. Therefore, by executing "LD A, B", "0CH" is set in the "transfer destination" A register 104b.

After that, the instruction "MUL W, A" is executed (step S3202). "MUL" is an operation instruction called a MUL instruction, "W" is the content specifying the W register 104a, and "A" is the content specifying the A register 104b. By executing "MUL W, A", an operation of multiplying the value of the W register 104a by the value of the A register 104b is performed and the result of the operation is stored in the WA register 104. FIG. As already explained, in the special figure special electric address acquisition process (FIG. 86(c)), the value of the special figure special electric counter (any integer from 0 to 6) is set in the W register 104a. Further, as described above, the A register 104b stores "0CH", which is the number of acquired bits. Therefore, when "MUL W, A" is executed in step S3202, the WA register 104 stores the calculation result of "(value of special special electric counter) x (number of bits acquired)".

After that, the instruction "ADD HL, WA" is executed (step S3203). “ADD” is an arithmetic instruction called an ADD instruction; By executing “ADD HL, WA”, the sum of the value of the HL register 107 and the value of the WA register 104 is stored in the HL register 107 . As described above, in the line number "3003" of the special special electric address acquisition process (Fig. 86(c)), the HL register 107 stores the acquired data designation data ("1800H") corresponding to the value "0" in the special special electric counter. ”) is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(the value of the special special electric counter) x (the number of acquired bits)". By executing the command "ADD HL, WA" in step S3203, "(special figure Tokuden counter value) x (acquired bit number)” is added. As a result, the lower 4 bits of the acquisition data designation data are updated in a manner corresponding to the value of the special special electric counter. As already explained, in the special LDB instruction, the lower 4 bits of the acquisition data designation data are used to specify the acquisition start bit.

By executing the instruction "ADD HL, WA" in step S3203, the calculation result of "(the number of bits acquired) x (the value of the special special electric counter)" stored in the WA register 104 is changed to "16". The acquisition data designation data stored in the HL register 107 is updated in such a manner that the acquisition start address is increased by the quotient obtained by dividing by . As already explained in the first embodiment, 8-bit data is set for one address in the special figure special electric address table 64q. On the other hand, in the special LDB instruction in this embodiment, the acquisition start bit is specified within a numerical range of "0" to "15". Therefore, in the special LDB instruction, it is necessary to increase the acquisition start address by "2" every time the acquisition start bit increases by "16". In order to update the upper 12-bit data of the acquisition data designation data stored in the HL register 107 in a manner corresponding to the value of the special special electric counter, "(number of acquired bits) x (value of the special special electric counter )” by dividing the result by “16”. However, simply executing the instruction in step S3203 increases the acquisition start address by the quotient obtained by dividing the operation result by "16". Therefore, by executing the processing of steps S3204 and S3205, the acquisition start address is further increased by the quotient obtained by dividing the calculation result by "16".

Specifically, first, the logical product of the value of the WA register 104 and "11111111111110000B" is calculated, and the result of the calculation is stored in the WA register 104, so that of the 2-byte data stored in the WA register 104, The lower 4-bit data is changed to "0000B" (step S3204). As already explained, the WA register 104 stores the calculation result of "(the number of bits acquired) x (the value of the special special electric counter)". In step S3204, by changing the lower 4 bits of the operation result stored in the WA register 104 to "0000B", the value obtained by dividing the operation result by "16" and multiplying it by "16" becomes WA. The state is assumed to be stored in the register 104 .

Thereafter, as in step S3203, the instruction "ADD HL, WA" is executed (step S3205). As a result, it is stored in the HL register 107 in such a manner that the acquisition start address is increased by the quotient obtained by dividing the calculation result of "(number of bits acquired) x (value of special special electric counter)" by "16". Acquisition data specification data is updated.

By executing the processing of steps S3201 to S3205 in this way, the data acquisition start position (corresponding to The 0th bit of the area to be acquired) is stored in the HL register 107 in such a manner that the acquisition start position is shifted backward by "(number of acquisition bits) x (value of special special electric counter)" bits. Data specification data can be updated. As already explained, in the special special electric address table 64q, the start addresses SA1 to SA6 corresponding to the special special electric counter values "1" to "6" are Based on the data acquisition start position (the 0th bit of the area corresponding to "9180H"), the acquisition start position is "(number of bits acquired) x (value of special special electric counter)" bits later It is set at a position that can be obtained by shifting.

In steps S3206 to S3209, the same instructions as the line numbers "1705" to "1708" in the address acquisition execution process (FIG. 33(e)) in the first embodiment are executed. Specifically, first, as in step S3201, the command "LD A, B" is executed (step S3206). As already explained, "0CH" ("12") designating the number of bits to be acquired is set in the B register 105a in the special special electric address acquisition process (FIG. 86(c)). Therefore, by executing "LD A, B", "0CH" is set in the "transfer destination" A register 104b. As already explained, "0CH" stored in the B register 105a is also used for calculation of "(value of special special electric counter) x (number of bits acquired)". In this way, "0CH" stored in the B register 105a in advance is used for the calculation of "(value of the special special electric counter) x (number of bits acquired)" and specifies the number of bits acquired in the LDB instruction. data to be set in the A register 104b.

After that, the command "DEC A" is executed (step S3207). "DEC" is an operation instruction called a DEC instruction, and "A" is the contents of specifying the A register 104b. By executing "DEC A", the value of the A register 104b is decremented by one. As described above, the A register 104b stores "0CH", which is the number of acquired bits. Therefore, "0BH" is stored in the A register 104b by executing "DEC A" in step S3207. "0BH" is a value obtained by subtracting "1" from "12", which is the number of bits obtained from the special special electric address table 64q.

As already explained, when the LDB instruction "LDB HL, (HL).A" is executed, the LDB execution circuit 157 performs an operation to add 1 to the value of the A register 104b, and the value after the addition of 1 is is used as data for the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b in step S3207, the number of bits of data acquired from the special special electric address table 64q in the LDB command can be set to "12".

After that, the instruction "LDB HL, (HL).A" is executed (step S3208). "LDB" is a special LDB instruction by the special LDB execution circuit 201, "HL" before the comma is the content specifying the HL register 107 as the "transfer destination", and "(HL)" before the period is the HL command. The 2-byte data stored in the register 107 is specified as the acquired data specifying data, and "A" is the content specifying the 1-byte data stored in the A register 104b as the acquired bit number specifying data. . As already explained, the HL register 107 is in a state where the acquired data designation data corresponding to the value of the special special electric counter is stored, and the A register 104b is changed from the number of acquired bits ("0CH") to "1". , and "0BH" is stored. Also, the TP register 111 is in a state where the reference address "9000H" is stored. In this state, by executing the instruction "LDB HL, (HL).A" in step S3208, the 0th to 11th bits of the HL register 107, which is the transfer destination, are set to the value of the special special electric counter. The lower 12-bit data at the corresponding start addresses SA0-SA6 are loaded, and the 12th-15th bits of the HL register 107 are masked with "0".

Specifically, as shown in FIG. 87, when the value of the special special electric counter is "0", the acquisition start address is "9180H" and the acquisition start bit is "0", and the HL register 107 "700H", which is the lower 12 bits of the start address SA0, is loaded into the 0th to 11th bits. When the value of the special special electric counter is "1", the acquisition start address is "9180H" and the acquisition start bit is "12", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA1 It is loaded with '712H' which is 12 bits. When the value of the special special electric counter is "2", the acquisition start address is "9182H" and the acquisition start bit is "8", and the 0th to 11th bits of the HL register 107 are lower than the start address SA2 It is loaded with '71FH' which is 12 bits. When the value of the special special electric counter is "3", the acquisition start address is "9184H" and the acquisition start bit is "4", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA3 It is loaded with '731H' which is 12 bits. When the value of the special special electric counter is "4", the acquisition start address is "9186H" and the acquisition start bit is "0", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA4 It is loaded with '740H' which is 12 bits. When the value of the special special electric counter is "5", the acquisition start address is "9186H" and the acquisition start bit is "12", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA5 "74CH", which is 12 bits, is loaded. When the value of the special special electric counter is "6", the acquisition start address is "9188H" and the acquisition start bit is "8", and the 0th to 11th bits of the HL register 107 are the lower order of the start address SA6 It is loaded with '753H' which is 12 bits. In this way, every time the value of the special special electric counter increases by 1, the data acquisition start position in the special special electric address table 64q is shifted backward by 12 bits.

By using a special LDB instruction to load the lower 12 bits of the start address SA0 to SA6 obtained from the special special electric address table 64q into the 0th to 11th bits of the HL register 107, 2 bytes of obtained data A process of specifying an acquisition start address corresponding to the 4th to 15th bits of the specified data, a process of specifying an acquisition start bit corresponding to the lower 4 bits (0th to 3rd bits) of the acquisition specified data; A process of loading the lower 12 bits of the start address SA0 to SA6 obtained from the special special electric address table 64q into the lower 12 bits of the HL register 107, and a process of masking the upper 4 bits of the HL register 107 with "0". It can be executed with one command. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set for executing these processes. can.

After that, the command "ADD HL, 9000H" is executed (step S3209), and this address acquisition execution processing ends. "ADD" is an operation instruction called an ADD instruction, "HL" is the content specifying the HL register 107, and "9000H" is 2-byte numerical data. By executing “ADD HL, 9000H”, “9000H”, which is the reference address of the data table, is added to the value of the HL register 107 . As a result, as shown in FIG. 87, the entire start addresses SA0 to SA6 (2 bytes) corresponding to the values "0" to "6" in the special electric special figure counter can be set. Specifically, when the value of the special special electric counter is "0", "9700H" which is the start address SA0 is set in the HL register 107, and when the value of the special special electric counter is "1", "9712H" which is the start address SA1 is set in the HL register 107, and "971FH" which is the start address SA2 is set in the HL register 107 when the special figure special electric counter value is "2", and the special figure When the value of the special electric counter is "3", "9731H" which is the start address SA3 is set in the HL register 107, and when the value of the special electric counter is "4", the start address is set in the HL register 107. When "9740H" which is SA4 is set and the value of the special special electric counter is "5", "974CH" which is the start address SA5 is set in the HL register 107, and the value of the special special electric counter is "6". ”, the HL register 107 is set to “9753H” which is the start address SA6.

As already explained, the address acquisition execution process (Fig. 88) is a subroutine executed at line number "3004" of the special special electric address acquisition process (Fig. 86(c)). Therefore, when the address acquisition execution process is completed, the process proceeds to the line number "1605" of the special figure special electric address acquisition process.

Thus, by using the special LDB instruction, the lower 12 bits of the start address SA0-SA6 can be loaded into the HL register 107 from the special special electric address table 64q. Further, after the execution of the special LDB instruction, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SA0 to SA6 to the value of the HL register 107, can be obtained in its entirety. Therefore, only the lower 12 bits of the start addresses SA0 to SA6 can be set in the special figure special electric address table 64q. As a result, the data capacity of the special special electric address table 64q in the main ROM 64 can be reduced compared to the configuration in which the entire 2-byte start address SA0 to SA6 is set in the special special electric address table 64q.

According to this embodiment detailed above, the following excellent effects are obtained.

In the special LDB instruction, the data acquisition start address in the main ROM 64 is specified based on the data of the upper 12 bits (4th to 15th bits) in the 2-byte acquisition data designation data, and the lower order in the acquisition data designation data is specified. Based on the data of 4 bits (0th to 3rd bits), the data acquisition start bit in the main ROM 64 is specified. For this reason, compared to a configuration in which 2-byte data for specifying the acquisition start address and 1-byte data for specifying the acquisition start bit are set in the acquisition data specification data, the data for the acquisition data specification data The capacity can be reduced by 1 byte.

In the special LDB execution circuit 201, in order to specify the acquisition start bit, a logical AND operation of the lower 1 byte of the acquisition data designation data and "00001111B" is performed. The instruction code of the special LDB instruction does not include data for designating the use of "00001111B" in the calculation for calculating the acquisition start bit. A logical AND operation of the lower 1 byte of the acquisition data designation data and "00001111B" is automatically executed by the special LDB execution circuit 201 when the special LDB instruction set in the program is executed. For this reason, compared to the configuration in which it is necessary to set data for designating the use of "00001111B" in the operation for calculating the acquisition start bit in the instruction code of the special LDB instruction, the instruction of the special LDB instruction The data capacity of the code can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

In the special LDB execution circuit 201, an operation of dividing the acquisition data designation data by "16" is performed in order to specify the acquisition start address. "16" used in the calculation for specifying the acquisition start address is a numerical range represented by 4 bits (" 0” to “15”) is the value obtained by adding “1” to “15” which is the maximum value. Thus, in a configuration in which the data for specifying the acquisition start address and the data for specifying the acquisition start bit are set in the 2-byte acquisition data specifying data, it is possible to specify the acquisition start bit. Data for specifying the acquisition start address can be set independently of the data of .

In the special LDB execution circuit 201, an operation is performed to divide the acquisition data designation data by "16" in order to specify the acquisition start address. The instruction code of the special LDB instruction does not include data for designating the use of "16" in the calculation for calculating the acquisition start address. The operation of dividing the acquisition data designation data by "16" is automatically executed by the special LDB execution circuit 201 when the special LDB instruction set in the program is executed. For this reason, compared to the configuration in which it is necessary to set data for designating the use of "16" in the calculation for calculating the acquisition start address in the instruction code of the special LDB instruction, the instruction code of the special LDB instruction is In addition, the data capacity of the program in the main ROM 64 can be reduced.

By using a special LDB instruction to load the lower 12 bits of the start address SA0 to SA6 obtained from the special special electric address table 64q into the 0th to 11th bits of the HL register 107, 2 bytes of obtained data A process of specifying an acquisition start address corresponding to the 4th to 15th bits of the specified data, a process of specifying an acquisition start bit corresponding to the lower 4 bits (0th to 3rd bits) of the acquisition specified data; A process of loading the lower 12 bits of the start address SA0 to SA6 obtained from the special special electric address table 64q into the lower 12 bits of the HL register 107, and a process of masking the upper 4 bits of the HL register 107 with "0". It can be executed with one command. As a result, the program configuration can be simplified and the data capacity of the program in the main ROM 64 can be reduced compared to a configuration in which a plurality of instructions are set to execute these processes. can.

<Other embodiments>
It should be noted that the present invention is not limited to the description of the above-described embodiment, and various modifications and improvements are possible without departing from the spirit of the present invention. For example, it may be changed as follows. Incidentally, the configurations of the following different forms may be applied individually or in combination with the configuration of the above-described embodiment.

(1) In each of the above-described embodiments, instead of the configuration in which when the LDB instruction is executed by the LDB execution circuit 157, the data of the number of bits obtained by adding "1" to the value of the number-of-acquisition-bits designation data is acquired. , the data of the number of bits corresponding to the value of the number-of-bits-to-be-acquired designation data may be acquired. As already explained in the first embodiment, the instruction code of the LDB instruction has a configuration of "LDB transfer destination, acquisition data designation, acquisition bit number designation". In this configuration, the number of bits of data to be acquired from the data table stored in the main-side ROM 64 can be set in the "specify number of bits to acquire" in the instruction code of the LDB instruction. Further, in each of the above-described embodiments, when the special LDB instruction is executed by the special LDB execution circuit 201, instead of the configuration in which the data of the number of bits obtained by adding "1" to the value of the number-of-acquisition-bits designation data is acquired. Then, the data of the number of bits corresponding to the value of the number-of-acquisition-bits specification data may be acquired. As already explained in the sixth embodiment, the instruction code of the special LDB instruction has a configuration of "LDB transfer destination, acquisition data designation, acquisition bit number designation". In this configuration, the number of bits of data to be acquired from the data table stored in the main-side ROM 64 can be set in the "specify number of bits to be acquired" in the instruction code of the special LDB instruction.

(2) In each of the above embodiments, when the LDB update instruction is executed by the LDB update execution circuit 161, the data of the number of bits obtained by adding "1" to the value of the number-of-acquisition-bits specification data is acquired. Alternatively, a configuration may be adopted in which data of the number of bits corresponding to the value of the number-of-acquisition-bits specification data is acquired. As already explained in the first embodiment, the instruction code for updating the LDB instruction has a configuration of "LDB transfer destination, (acquisition data specification +).acquisition bit number specification". In this configuration, the number of bits of data to be acquired from the data table stored in the main-side ROM 64 can be set in the "specify number of bits to be acquired" in the instruction code of the LDB update instruction.

(3) The main MPU 62 may be provided with an LDH execution circuit, which is a dedicated circuit for executing LDH instructions. The main CPU 63 can execute LDH instructions. The instruction code of the LDH instruction has a structure of "LDH transfer destination, transfer source". In the LDH instruction, the WA register 104 is set as the "transfer destination" and the HL register 107 is set as the "transfer source." The LDH instruction transfers the upper 4-bit data in the 1-byte data stored in the area corresponding to the address stored in the HL register 107, which is the “transfer source”, to the WA register 104, which is set as the “transfer destination”. A process of loading the lower 4 bits of one general-purpose register (W register 104a) and masking the upper 4 bits of the general-purpose register with "0", and transferring the lower 4-bit data of the 1-byte data to the "transfer destination" A process of loading the lower 4 bits of the other general-purpose register (A register 104b) of the WA register 104 set to 0 and masking the upper 4 bits of the general-purpose register with "0" It is an instruction to By using the LDH instruction, compared to a configuration in which a plurality of instructions are set to execute these two processes, the program configuration can be simplified, and the data capacity of the program can be reduced. can be reduced. The BC register 105, the DE register 106 or the HL register 107 may be set as the "transfer destination" in the LDH instruction, and the WA register 104, the BC register 105 or the DE register 106 may be set as the "transfer source" in the LDH instruction. It may be configured to be set.

(4) In each of the above-described embodiments, when the state in which the specific control process is being executed changes to the situation in which the non-specific control process is being executed, and when the non-specific control process is being executed A configuration may be adopted in which the reference address of the data table stored in the TP register 111 is changed when the state shifts to the state in which the specific control process is being executed. Specifically, in the main ROM 64, the data for specific control is set in the address range of "9000H" to "94FFH", and the data for non-specific control is set in the address range of "8903H" to "8BFFH". is set. The main CPU 63 outputs specific control data when the supply of operating power is started and when the state in which the non-specific control processing is being executed changes to the state in which the specific control processing is being executed. "9000H" is set in the TP register 111 as the reference address of the table. The "9000H" is the high-order 4 bits ("9H") common to the address range that is referenced in the situation where the specific control process is being executed, out of the address range in which the data table is stored in the main ROM 64. It is information that enables identification. By executing the LDT instruction in the process for specific control, "9000H" stored in the TP register 111 is diverted while the addressing data set in the program is the lower 12 bits of the 2-byte address. can specify the entire 2-byte address. The main CPU 63 sets "8000H" as the reference address of the non-specific control data table when shifting from the specific control process to the non-specific control process. set. The "8000H" is the high-order 4 bits ("8H") that are common to the address range referred to in the situation where non-specific control processing is being executed, out of the address range in which the data table is stored in the main ROM 64. It is information that enables the identification of By executing the LDT instruction in the non-specific control process, "8000H" stored in the TP register 111 is diverted while the addressing data set in the program is the lower 12 bits of the 2-byte address. Thus, the entire 2-byte address can be specified. In this way, the high-order 4 bits common to the address corresponding to the storage area to be referenced in the situation where non-specific control processing is being executed in the address range in which the data table is stored in the main ROM 64 are Even in a configuration that differs from the high-order 4 bits common to the address corresponding to the storage area to be referenced in the situation in which the specific control process is being executed, it is unspecified from the situation in which the specific control process is being executed. It is stored in the TP register 111 when shifting to a state in which control processing is being executed, or when shifting from a state in which non-specific control processing is being executed to a state in which specific control processing is being executed. The LDT instruction can be made available in each situation by changing the base address of the data table that is stored.

(5) In the sixth embodiment, the number of bits of data set to specify the acquisition start bit in the acquisition data designation data of the special LDB instruction may be "5" or more. Specifically, the acquisition data designation data is 2-byte data as in the sixth embodiment. If the number of bits of the data set to specify the acquisition start bit in the acquisition data designation data is "n" (n is any integer from 5 to 15), the upper order (16-15) in the acquisition data designation data The n) bit is used for an operation to specify the acquisition start address, and the lower n bits in the acquisition data designation data are used for an operation to specify the acquisition start bit. The acquisition start address is obtained by adding the reference address ("9000H") of the data table stored in advance in the TP register 111 to the value obtained by dividing the acquired data designation data by "2 nth power". Calculated. The data "2 to the nth power" used in the calculation to specify the acquisition start address is represented by n bits, which is the number of data bits set to specify the acquisition start bit in the acquisition data designation data. It is a value obtained by adding "1" to "(nth power of 2)-1" which is the maximum value in the numerical range ("0" to "(nth power of 2)-1"). When the acquired data specifying data is divided by the "nth power of 2", the "0" or "1" information set in the n-th to 15th bits of the acquired data specifying data is shifted to the lower n bits. is set to the lower (16-n) bits (0th to (15-n)th bits) in the quotient data after division, and the upper n bits ((16-n)th to 15th bit) is set to "0". The acquisition start bit is data of the lower n bits of acquisition data designation data. The acquisition start bit is any integer from "0" to "(nth power of 2)-1".

For example, if the number of bits of data set to specify the acquisition start bit in the acquisition data designation data is "5", the upper 11 bits in the acquisition data designation data are used for the calculation to specify the acquisition start address. At the same time, the lower 5 bits in the acquisition data designation data are used for the calculation for specifying the acquisition start bit. The acquisition start address is calculated by adding the reference address ("9000H") of the data table stored in advance in the TP register 111 to the value obtained by dividing the acquisition data designation data by "32". . The data "32" used for the calculation to specify the acquisition start address is a numerical range represented by 5 bits, which is the number of bits of data set to specify the acquisition start bit in the acquisition data designation data ( "0" to "31"), which is the maximum value of "31" plus "1", which is the fifth power of "2". When the obtained data designation data is divided by the "32" (100000H), the "0" or "1" information set in the 5th to 15th bits of the obtained data designation data is shifted to the lower side by 5 bits. is set to the lower 11 bits (0th to 10th bits) of the quotient data after division, and "0" is set to the upper 5 bits (11th to 15th bits) of the quotient data after the division. . In this configuration, the minimum value of the acquisition start address that can be set is "1001000000000000" (9000H), and the maximum value of the acquisition start address that can be set is "1001011111111111" (97FFH). The acquisition start bit is lower 5-bit data of acquisition data designation data. The acquisition start bit is calculated by ANDing the lower 1 byte of the acquisition data designation data and "00011111B" ("1FH"). The "00011111B" used in the calculation for calculating the acquisition start bit extracts only the data of the lower 5 bits (0th to 4th bits) in the acquired data specifying data from the 16-bit acquired data specifying data. This data is for The acquisition start bit is any integer from "0" to "31".

(6) In the sixth embodiment, the data structure of the main ROM 64 may be a structure in which a 2-byte storage area is set for one address. By adding predetermined numerical information to the acquisition data designation data of the special LDB instruction, the acquisition start address is changed by the quotient of the operation result of dividing the predetermined numerical information by "16" (2 to the 4th power). In addition to updating, the acquisition start bit can be updated by the remainder of the calculation result.

(7) In each of the above embodiments, two different registers (W register 104a and W register 104a and The combination of the number of bits of data read out to the A register 104b) is not limited to the combination of the upper 4 bits and the lower 4 bits. Combinations of bit numbers of data read out to two different registers out of 1-byte data when an LDH update instruction is executed are a combination of upper 1 bit and lower 7 bits, a combination of upper 2 bits and lower 6 bits, A combination of the upper 3 bits and the lower 5 bits, a combination of the upper 5 bits and the lower 3 bits, a combination of the upper 6 bits and the lower 2 bits, or a combination of the upper 7 bits and the lower 1 bit may be used.

(8) In the LDH update instruction, the area in which the upper 4-bit data and the lower 4-bit data in the 1-byte area of the data table are set is the lower 4 bits of the W register 104a and the lower 4 bits of the A register 104b. not limited. For example, in the LDH update instruction, the upper 4-bit data in the 1-byte area is set in the first to fourth bits of the W register 104a, and the lower 4-bit data in the 1-byte area is set in the A register 104b. It may be configured to be set to the 1st to 4th bits. In this configuration, "0" is set to the 0th bit and the 5th to 7th bits to which no data is set in the W register 104a, and "0" is set to the 0th bit and the 5th bit to which no data is set in the A register 104b. ~ 7th bit is set to "0". When setting multiple types of 1-byte data in which the 0th bit and the 5th to 7th bits are "0" in common in the data table, only the 1st to 4th bits of each 1-byte data can be aggregated and set, the data capacity of the data table can be reduced.

(9) In the LDB instruction and the LDB update instruction, the area in which the data obtained from the data table is set is not limited to the lower side area in the "transfer destination" register. For example, in the LDB instruction and the LDB update instruction, 3-bit data obtained from the data table may be set to the first to third bits in the "destination" B register 105a. When the 3-bit data is set in the B register 105a, "0" is set in the 0th bit and the 4th to 7th bits where no data is set in the B register 105a. When setting multiple types of 1-byte data in which the 0th bit and the 4th to 7th bits are "0" in common in the data table, only the 1st to 3rd bits of each 1-byte data can be aggregated and set, the data capacity of the data table can be reduced.

(10) The specific control reference address and the non-specific control reference address preset in the IY register 109 are not limited to the configuration used to specify the upper 4 bits of the address, and these references A configuration may be used in which the address is used to designate part or all of the address. Specifically, in the main RAM 65, the work area for specific control is set in the address range of "1050H" to "134DH", and the work area for non-specific control is set to the address range of "1350H" to "14FFH". set in the range. In the IY register 109, "1050H" is set as the specific control reference address at the start of the specific control process, and "1350H" is set as the non-specific control reference address at the start of the non-specific control process. be done. By executing the first LDY instruction "LDY BC, 19H" in the state where "1050H" is set in the IY register 109, "1069H" calculated by adding "19H" to "1050H" is changed to BC. It can be stored in register 105 . By executing the first LDY instruction "LDY HL, 03H" with "1350H" set in the IY register 109, "1353H" is calculated by adding "03H" to "1350H". can be stored in the HL register 107.

(11) Addition of the specific control reference address (“0000H”) or non-specific control reference address (“0300H”) set in the IY register 109 and 1-byte numerical information (for example, “19H”). The processing and the setting processing for setting the result of the arithmetic processing in a pair register such as the BC register 105 may be performed by a subroutine on the program. This eliminates the need to provide a dedicated circuit for executing these two processes, and enables addressing by diverting the specific control reference address or non-specific control reference address stored in the IY register 109 in advance. can be In addition, by configuring the subroutine for executing these two processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these two processes can be reduced. can be reduced.

(12) Arithmetic processing for adding the reference address (“9000H”) of the data table set in the TP register 111 and 12-bit numerical information (for example, “400H”), and the result of the arithmetic processing (“9400H” ) in a pair register such as the HL register 107 may be performed by a subroutine on the program. This makes it unnecessary to provide a dedicated circuit for executing these two processes, and enables addressing using the reference address of the data table stored in the TP register 111 in advance. In addition, by configuring the subroutine for executing these two processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these two processes can be reduced. can be reduced.

(13) A process of specifying an acquisition start address corresponding to the 3rd to 15th bits of the acquisition data designation data, a process of specifying an acquisition start bit corresponding to the lower 3 bits of the acquisition designation data, and an acquisition start address The process of loading the data for the number of bits to be acquired from the acquisition start bit into the "destination" register, and setting the bits in the "destination" register that are higher than the loaded data to "0". The masking process may be performed by a subroutine on the program. This eliminates the need to provide a dedicated circuit for executing these four processes, while specifying the information set in the data table in units of bits to maintain the order of the bit array, and the "transfer destination". (for example, the HL register 107), and the bits present in the register above the loaded data can be masked with "0". In addition, by configuring the subroutines for executing these four processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these four processes can be reduced. can be reduced.

(14) The sum of the data stored in the IY register 109 (specifically, "1100H") and the data stored in the A register 104b (eg, "11H") is calculated to obtain the transfer destination address ("11H"). . This makes it unnecessary to provide a dedicated circuit for executing these two processes, while enabling addressing using the information stored in the IY register 109 in advance. In addition, by configuring the subroutine for executing these two processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these two processes can be reduced. can be reduced.

(15) A process of loading the data (for example, the judgment value HVB1) set in the data table (for example, the fluctuation pattern table 64t) into a register such as the D register 106a, and adding 1 to the value of the HL register 107 after loading the data. and updating the address stored in the HL register 107 may be performed by a subroutine on the program. This makes it unnecessary to provide a dedicated circuit for executing these two processes. In addition, the data capacity of the program can be reduced compared to a configuration in which each program is set to update the address stored in the HL register 107 after execution of the subroutine.

(16) a process of specifying an acquisition start address corresponding to the 3rd to 15th bits of the acquisition data designation data; a process of specifying an acquisition start bit corresponding to the 0th to 2nd bits of the acquisition designation data; A process of loading the data for the number of acquisition bits set after the acquisition start bit in the acquisition start address in the main ROM 64 into the lower bits of the "transfer destination" register, and loading the upper bits of the "transfer destination" register. The processing of masking with "0" and the processing of adding the current acquired bit number to the value of the HL register 107 after the data transfer to update the acquired data designation data may be performed by a subroutine on the program. This eliminates the need to provide a dedicated circuit for executing these five processes, while specifying the information set in the data table in units of bits and maintaining the order of the bit array, while maintaining the order of the "transfer destination". (for example, the HL register 107), and the bits present in the register above the loaded data can be masked with "0". Also, after the data is loaded, the acquired data designation data can be updated by adding the currently acquired bit number to the value of the HL register 107 . The data capacity of the program set in the main ROM 64 for executing these five processes is reduced by configuring the subroutines for executing these five processes to be commonly used in a plurality of processes. be able to.

(17) A process of specifying an acquisition start address corresponding to the 4th to 15th bits of the acquisition data designation data, a process of specifying an acquisition start bit corresponding to the 0th to 3rd bits of the acquisition designation data, A process of loading the data for the number of acquisition bits set after the acquisition start bit in the acquisition start address in the main ROM 64 into the lower bits of the "transfer destination" register, and loading the upper bits of the "transfer destination" register. The process of masking with "0" may be performed by a subroutine on the program. This eliminates the need to provide a dedicated circuit for executing these four processes, while specifying the information set in the data table in units of bits to maintain the order of the bit array, and the "transfer destination". (for example, the HL register 107), and the bits present in the register above the loaded data can be masked with "0". By configuring the subroutines for executing these four processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these four processes is reduced. be able to.

(18) A process of setting the data set in the high-order 4 bits of the 1-byte area in the data table to the low-order 4 bits of the W register 104a and masking the high-order 4 bits of the W register 104a with "0"; A process of setting the data set in the lower 4 bits of the 1-byte area to the lower 4 bits of the A register 104b and masking the upper 4 bits of the A register 104b with "0", and the value of the HL register 107 , and updating the address stored in the HL register 107 by 1 may be performed by a subroutine on the program. As a result, the upper 4-bit data and the lower 4-bit data set in the 1-byte area can be read out to different general-purpose registers without providing a dedicated circuit for executing these three processes. can be made available and the address stored in the HL register 107 can be updated by incrementing the value of the HL register 107 by one. In addition, by configuring the subroutines for executing these three processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these three processes can be reduced. can be reduced.

(19) In each of the above embodiments, the most significant frame SFp (p is 1 or 2) in the communication command (communication variation command and communication normal return command) is the header HD and the first data frame FR1. It is good also as a structure set between. In the variation command for communication including two data frames FR1 and FR2, frames are set in the order of header HD→first most significant frame SF1→first data frame FR1→second data frame FR2→footer FT. Further, in the normal return command for communication including ten data frames FR1 to FR10, header HD→first most significant frame SF1→second most significant frame SF2→first data frame FR1 to tenth data frame FR10→footer Frames are set in order of FT. When the data size of the command for communication stored in the pre-conversion area 184 is 3 to 9 bytes, the sound and light side CPU 93 stores the first most significant frame SF1 in the second area RA2 in the pre-conversion area 184. can be found to be set. Further, when the data size of the command for communication stored in the pre-conversion area 184 is 10 to 12 bytes, the sound and light side CPU 93 stores the first most significant data in the second area RA2 in the pre-conversion area 184. It can be seen that the frame SF1 is set and the second most significant frame SF2 is set in the third area RA3 in the pre-conversion area 184. FIG.

(20) In each of the above embodiments, the configuration in which the highest frame SFp (p is 1 or 2) in the commands for communication (variation command for communication and normal return command for communication) is set immediately before the footer FT. may be In the variation command for communication including two data frames FR1 and FR2, frames are set in the order of header HD→first data frame FR1→second data frame FR2→first most significant frame SF1→footer FT. Further, in the normal return command for communication including ten data frames FR1 to FR10, header HD→first data frame FR1 to tenth data frame FR10→first most significant frame SF1→second most significant frame SF2→footer Frames are set in order of FT. When the data size of the command for communication stored in the pre-conversion area 184 is 3 to 9 bytes, the sound and light side CPU 93 stores one of the areas in which the footer FT is stored in the pre-conversion area 184. It can be seen that the first most significant frame SF1 is set in the previous area. Further, when the data volume of the command for communication stored in the pre-conversion area 184 is 10 to 12 bytes, the sound and light side CPU 93 stores the area in which the footer FT is stored in the pre-conversion area 184. To understand that the first most significant frame SF1 is set in the area two before and the second most significant frame SF2 is set in the area one before the area in which the footer FT is stored. can be done.

(21) In each of the above embodiments, the bit used to distinguish between the header HD and data other than the header HD is not limited to the most significant bit (seventh bit) in each frame. For example, the least significant bit (0th bit) in each frame may be used to distinguish between the header HD and data other than the header HD. In commands for communication (variation command for communication and normal return command for communication), information "1" is set in the least significant bit of the header HD, while information other than the header HD is set to "1" in the least significant bit. is set to "0" information. The sound/light receiving circuit 96 can recognize whether or not the frame is the header HD based on the state of the least significant bit in each frame. In this configuration, the command for communication is set to the least significant frame that collects the information of "0" or "1" in the least significant bit of each data frame FRm. The n-th bit (n is an integer from 1 to 7) of the first least significant frame corresponds to the n-th data frame FRn. Also, the p-th bit (p is an integer from 1 to 3) of the second least significant frame corresponds to the (p+7)-th data frame FR(p+7). The sound and light side CPU 93 sets the information of each bit of the least significant frame included in the command for communication to the least significant bit of the data frame FRm corresponding to the bit in the post-conversion command. As a result, during communication, the header HD and frames other than the header HD are used as communication commands that can be distinguished from each other. can be converted into a post-conversion command in which "1" can be set to

(22) In each of the above embodiments, instead of saving the data to be set in the top frames SF1 and SF2 to the save areas 182 and 183, save them to registers (for example, the D register 106a and the E register 106b). It is good also as a structure which puts. Specifically, when setting a communication variation command including two data frames FR1 and FR2 in the transmission standby buffer 175, the most significant bit (7th bit) is saved in the D register 106a. Also, when setting a normal return command for communication including 10 data frames FR1 to FR10 in the transmission standby buffer 175, the most significant bit ( 7th bit) data is saved in the D register 106a, and the most significant bit (7th bit) data in the data set in the 8th to 10th data frames FR8 to FR10 is saved in the E register 106b. Keep In this way, by adopting a configuration in which the data of the most significant bit is saved in the register, a dedicated area for saving the data of the most significant bit can be made unnecessary in the work area 121 for specific control.

(23) A configuration may be adopted in which three or more highest-level frames are set in the communication command transmitted from the main side CPU 63 to the sound and light side CPU 93 . For example, when 15 data frames FR1 to FR16 are set in a communication command, information of the most significant bits in the first to seventh data frames FR1 to FR7 is aggregated in the communication command. the first most significant frame SF1, the second most significant frame SF2 in which the most significant bit information in the eighth to fourteenth data frames FR8 to FR14 is aggregated, and the most significant in the fifteenth to sixteenth data frames FR15 to FR16 A third most significant frame SF3 in which bit information is aggregated is set. As already described in the first embodiment, when the number of data frames FRm included in the communication command is a multiple of "7", the data frames included in the communication command The most significant frame SFp of the number of quotients obtained by dividing the number of FRm by "7" is set in the command for this communication. Further, when the number of data frames FRm included in the command for communication is not a multiple of "7", the number of data frames FRm included in the command for communication is divided by "7". The most significant frame SFp, which is "1" larger than the number of quotients in the case, is set in the command for this communication. As a result, after the communication command is received, the information set in the most significant bit in all the data frames FRm included in the communication command can be set in the most significant frame SFp.

(24) In each of the above embodiments, the sound and light side RAM 95 may be configured to have a dedicated area for storing the commands received from the main side CPU 63 in one-to-one correspondence. Specifically, the sound and light side RAM 95 is provided with a variation command storage area for storing the post-conversion variation command and a normal return command storage area for storing the post-conversion normal return command. The variation command storage area is an area consisting of 4 bytes, and the normal return command storage area is an area consisting of 12 bytes. When the sound/light side CPU 93 receives a communication variation command from the main side CPU 63, the communication variation command is converted into a post-conversion variation command and stored in the variation command storage area. As a result, until the post-conversion variation command is used in the sound and light side CPU 93, the command is stored in the variation command storage area while preventing the command from being overwritten by another command. can be done. When the sound/light side CPU 93 receives a normal return command for communication from the main side CPU 63, the normal return command for communication is converted into a post-conversion normal return command and stored in the normal return command storage area. As a result, the command is stored in the normal return command storage area while preventing the command from being overwritten by another command until the normal return command after conversion is used in the CPU 93 on the sound and light side. can be done.

(25) In each of the above embodiments, instead of the configuration in which only one type of high accuracy table 64g common to "setting 1" to "setting 6" is stored in the main ROM 64, the main ROM 64 stores "setting 1” to “setting 6” may be stored in a high-probability table in one-to-one correspondence. These high-probability tables are set so that the higher the setting value, the higher the winning probability of the jackpot result. Specifically, 250 values that result in a big win are set in the high-probability table for setting 1 . When the high certainty table for setting 1 is referred to, 1/32 results in a big win. 260 values that result in a big win are set in the high certainty table for setting 2. When the high certainty table for setting 2 is referred to, the jackpot result is about 1/30.8. 270 values that result in a big win are set in the high certainty table for setting 3. When the high certainty table for setting 3 is referred to, a jackpot result is obtained at about 1/29.6. 280 values that result in a big win are set in the high certainty table for setting 4. When the high certainty table for setting 4 is referred to, about 1/28.6 results in a big win. The high certainty table for setting 5 has 290 values that result in a big win. When the high certainty table for setting 5 is referred to, the jackpot result is about 1/27.6. The high certainty table for setting 6 has 300 values that result in a big win. When the high certainty table for setting 6 is referred to, a jackpot result is obtained at approximately 1/26.7. When the setting state of the pachinko machine 10 is set to a high setting value, it becomes easier to generate a big hit result in the high probability mode, and it is advantageous for the player. As a result, it is possible to improve the amusement of the game.

(26) In each of the above embodiments, depending on the operation mode of the setting key insertion unit 68a and the reset button 68c at the start of supply of operating power to the pachinko machine 10, the case where the setting value update process is executed and the setting confirmation There may be a case where the process is executed and a case where the RAM clear process is executed. Specifically, when the supply of the operating power to the pachinko machine 10 is started while the setting key insertion portion 68a is being turned ON and the reset button 68c is being turned ON. , a setting value update process is executed to enable the setting value of the pachinko machine 10 to be updated, and a RAM clearing process is executed to clear the information stored in the main side RAM 65 after the setting value update process is completed. . Further, when the supply of operating power to the pachinko machine 10 is started while the setting key inserting portion 68a is being turned on and the reset button 68c is not being turned on, the pachinko A setting confirmation process is executed to enable confirmation of the current setting values in the machine 10 . Furthermore, when the supply of operating power to the pachinko machine 10 is started in a state in which the ON operation of the setting key insertion portion 68a is not performed and the ON operation of the reset button 68c is performed, The RAM clear processing described above is executed. In this manner, depending on the operating mode of the setting key inserting portion 68a and the reset button 68c at the start of supply of operating power to the pachinko machine 10, the setting value updating process and the setting confirmation process are executed. Management of the pachinko machine 10 by the manager of the game hall can be facilitated by setting up a case and a case in which the RAM clearing process is executed.

(27) Display control based on a command sent from the main controller 60 instead of the configuration in which the display controller 89 is controlled by the sound emission control device 90 based on a command sent from the main controller 60 The device 89 may be configured to control the sound emission control device 90 . Further, instead of the configuration in which the sound emission control device 90 and the display control device 89 are provided separately, a configuration in which both control devices are provided as one control device may be used, and the function of one of the two control devices may be changed. may be integrated into the main controller 60 , or both functions of both controllers may be integrated into the main controller 60 . Also, the content of the command sent from the main control device 60 to the sound emission control device 90 and the content of the command sent from the sound emission control device 90 to the display control device 89 are also arbitrary.

(28) Other types of pachinko machines different from the above embodiments, such as a pachinko machine in which an electric accessory is released a predetermined number of times when a game ball enters a specific area of a special device, or a game ball in a specific area of a special device The present invention can also be applied to a pachinko machine in which a right is generated and a jackpot is obtained when a coin is entered, a pachinko machine equipped with other accessories, an arrangement ball machine, a mahball, or the like.

In addition, a game machine that is not a bullet type, for example, is equipped with a plurality of reels on which a plurality of types of patterns are attached in the circumferential direction. After the reels stop due to the elapse of a predetermined time, if a specific pattern or a combination of specific patterns is established on the effective line that can be visually recognized from the display window, the player is given a privilege such as the payout of medals. The present invention can also be applied to a slot machine that

In addition, the gaming machine main body which is openably and closably supported by the outer frame is provided with a storage portion and a take-in device, and the start lever is operated after a predetermined number of game balls stored in the storage portion are taken in by the take-in device. The present invention can also be applied to a gaming machine that combines a pachinko machine and a slot machine, in which the reels start rotating.

<Invention groups extracted from the above embodiments>
Hereinafter, the features of the group of inventions extracted from each of the above-described embodiments will be described, showing effects and the like as necessary. In the following description, for ease of understanding, configurations corresponding to the above-described embodiments are appropriately shown in parentheses or the like, but are not limited to the specific configurations shown in parentheses or the like.

<Characteristic group A>
Feature A1. Specifying means (by the first LDY execution circuit 156) for specifying a predetermined address of the storage area to be used (the address specifying the transfer source in the first LDY instruction, the second LDY instruction, the LDT instruction, the LDB instruction, the LDB update instruction, and the special LDB instruction) Function of executing the first LDY instruction, function of executing the LDT instruction by the LDT execution circuit 149, function of executing the LDB instruction by the LDB execution circuit 157, function of executing the LDB update instruction by the LDB update execution circuit 161, second LDY execution circuit 164, the function of executing the special LD instruction in the special LD execution circuit 194, the function of executing the special LDB instruction in the special LDB execution circuit 201);
Predetermined process executing means (executing the first LDY instruction by the first LDY executing circuit 156) for executing the predetermined process (processing for transferring the information of the transfer source) using the storage area corresponding to the predetermined address specified by the specifying means function to execute the LDT instruction by the LDT execution circuit 149; function to execute the LDB instruction by the LDB execution circuit 157; function to execute the LDB update instruction by the LDB update execution circuit 161; , the function of executing the special LD instruction in the special LD execution circuit 194, the function of executing the special LDB instruction in the special LDB execution circuit 201);
In a game machine equipped with
It is possible to store first predetermined address information (reference address for specific control, reference address for non-specific control, reference address of data table) which is information of a part of the plurality of bits included in the predetermined address. Predetermined storage means (IY register 109, TP register 111) are provided,
The identifying means may provide second predetermined address information (address information in the first LDY instruction, the second LDY instruction and the special LD instruction), which is information of bits different from the part of the bits included in the predetermined address. (lower 1 byte, LDT instruction, LDB instruction, LDB update instruction and special LDB instruction, lower 12 bits of address information) are specified from the program, and the specified second predetermined address information and the second address information stored in the predetermined storage means are specified. 1. A gaming machine, wherein the predetermined address is specified from predetermined address information.

According to feature A1, since the predetermined address is specified from the second predetermined address information specified from the program and the first predetermined address information stored in the predetermined storage means, the entire predetermined address is set in the program. As a result, the data volume of information set in the program to specify the predetermined address can be reduced.

Feature A2. The game machine according to feature A1, wherein the predetermined storage means is a predetermined register (IY register 109, TP register 111) provided in the control means.

According to feature A2, the control means can easily access the predetermined register storing the first predetermined address information used to specify the predetermined address. It is possible to eliminate the need to provide a dedicated storage area for storing the first predetermined address information other than the predetermined register provided in the control means.

Feature A3. The predetermined address range specified by the specifying means is a first address range (“0000H” to “ 00FFH”) to a second address range (“0303H” to “03FFH”) in which the first predetermined address information, which is the information of the part of bits, is common to the address information (“0300H”) different from the first address range (“0303H” to “03FFH”). ”), changing means for changing the information in the predetermined storage means from the first predetermined address information to the different address information (“0300H”) (the function of executing the processing of step S1707 in the main CPU 63 ), the gaming machine according to feature A1 or A2.

According to feature A3, in a situation where the identifying means identifies the predetermined address within the first address range, the first predetermined address information stored in the predetermined storage means can be used, and the identifying means can use the second address range. Different address information stored in the predetermined storage means can be used in situations where a predetermined address is specified in the memory.

Feature A4. a first specific process executing means (a function of executing a specific control process in the main CPU 63) for executing a first specific process (a process for specific control);
Second specific process execution means (function for executing non-specific control process in main CPU 63) for executing second specific process (process for non-specific control);
with
The predetermined process executing means uses the storage area corresponding to the predetermined address specified by the specifying means from the first address range in a situation where the first specifying process is being executed. In a situation where the process is executed and the second identification process is being executed, the predetermined process is performed by using the storage area corresponding to the predetermined address identified by the identification means from the second address range. run,
The changing means changes the information in the predetermined storage means from the first predetermined address information to the different address information when the second identifying process is started while the first identifying process is being executed. The gaming machine according to feature A3, characterized by:

According to feature A4, in a situation where the first specifying process is being executed, the first predetermined address information stored in the predetermined storage means can be used to specify the specific address, and the second specifying process is executed. In such situations, different address information stored in the predetermined storage means can be used to identify the particular address.

Feature A5. The predetermined process executing means uses the first predetermined address information stored in the predetermined storage means to determine the address included in the first address range in a situation where the first specific process is being executed. Addresses in a third address range (“0100H” to “02FFH”) that do not overlap with the first address range and the second address range without specifying a predetermined address and using information stored in the predetermined storage means The gaming machine according to feature A4, characterized in that it specifies .

According to feature A5, it is possible to specify the predetermined addresses in the first address range and the addresses in the third address range in a situation where the first specifying process is being executed. For this reason, compared to a configuration in which only predetermined addresses in the first address range are specified in a situation in which the first specifying process is executed, the range of addresses that can be specified in the situation in which the first specifying process is being executed is increased. can be widely secured. When the predetermined address in the first address range is identified in the situation where the first identification process is executed, the first predetermined address information stored in the predetermined storage means is used, while the third address range information is used. When the address is specified, the information stored in the predetermined storage means is not used. Therefore, it is possible to fix the state in which the first predetermined address information is set in the predetermined storage means while the first specifying process is being executed. As a result, in this situation, it is possible to eliminate the need for the process of changing the information set in the predetermined storage means and the process of returning the information in the predetermined storage means to the information before the change. Therefore, the data capacity of the program for executing the first specific process can be reduced.

Feature A6. The number of times the second predetermined address information for specifying the predetermined address in the first address range appears in the program for executing the first specifying process specifies the address in the third address range in the program. The gaming machine according to feature A5, wherein the number of appearances of the information for playing is greater than the number of appearances.

According to feature A6, it is possible to reduce the data volume of the program for executing the first specific process.

Feature A7. Characteristics A1 to A6 characterized by comprising information setting means (a function of executing the processing of step S103 in the main CPU 63) for setting the first predetermined address information in the predetermined storage means when supply of operating power is started. The gaming machine according to any one of 1.

According to feature A7, by setting the first predetermined address information in the predetermined storage means when supply of operating power is started, the first address information stored in the predetermined storage means for specifying the specific address immediately after the supply of operating power is started. Predetermined address information may be available.

Feature A8. Equipped with information storage means (main ROM 64) in which an address is set for each storage area,
The specifying means specifies, as the specified address, the address of the storage area of the information storage means from the second specified address information specified from the program and the first specified address information stored in the specified storage means. The gaming machine according to any one of the characterizing features A1 to A7.

According to feature A8, the first predetermined address information stored in the predetermined storage means can be used when specifying the address of the storage area in the information storage means. For this reason, compared to the configuration in which the entire information of the address is set in the program in order to specify the address of the storage area in the information storage means, the program is set in the program to specify the address of the storage area in the information storage means. It is possible to reduce the data capacity of the information to be stored.

Feature A9. information storage means (main-side ROM 64) in which an address is set for each storage area;
Using the first information group (the first initialization table 64y and the second initialization table 64z in the fourth embodiment) stored in the information storage means, the first processing (power-on setting processing) (function for executing the processing of line numbers “2801” to “2806” in the main side CPU 63);
The second processing (random number maximum value setting processing in the fourth embodiment) is executed using the second information group (random number maximum value table 64α in the fourth embodiment) stored in the information storage means. 2 processing execution means (function for executing the processing of steps S3001 to S3006 in the main CPU 63);
with
The specifying means specifies the second predetermined address information from the program at the start of the first processing, and the specified second predetermined address information and the first predetermined address information stored in the predetermined storage means Means for specifying, as a predetermined address, the first address in the specific address range (the address range of "9400H" to "940BH") in which the first information group is set in the information storage means (the main address in the fourth embodiment). function to execute the processing of line number "2801" of the side CPU 63),
Characteristic features A1 through A1, characterized in that the last address in the specific address range is the same common address ("940BH") as the first address in the address range in which the second information group is set in the information storage means The gaming machine according to any one of A8.

According to feature A9, compared to the configuration in which the last address in the address range in which the first information group is set and the first address in the address range in which the second information group is set are different addresses, information The total data capacity of the first information group and the second information group in the storage means can be reduced. In order to specify the first address in the specified address range from the second specified address information specified from the program and the first specified address information stored in the specified storage means, the entire address is compared with the configuration set in the program. Therefore, it is possible to reduce the data volume of information set in the program to specify the first address in the specific address range.

Feature A10. Predetermined common information ("63H") is set in a storage area corresponding to the common address in the information storage means,
The first process executing means uses the predetermined common information to end the first process,
The gaming machine according to feature A9, wherein the second process executing means sets the predetermined common information in an information setting area when starting the second process.

According to feature A10, the first process is terminated using the predetermined common information set in the information setting area in the second process. For this reason, compared to the configuration in which information for ending the first process is set in the information storage means separately from the predetermined common information set in the information setting area, the first information group in the information storage means and the The total data capacity of the second information group can be reduced.

Feature A11. The first processing execution means is
Predetermined common setting means (command of line number "2903" in main CPU 63) for setting predetermined common information ("63H") set in the storage area corresponding to the common address in predetermined common storage means (E register 106b) function) and
a predetermined termination means (a function of executing the command of line number "2904" in the main CPU 63) for terminating the first process based on the fact that the predetermined common information is set in the predetermined common storage means;
and
The feature A10 according to feature A10, wherein the second process execution means executes the second process using the predetermined common information set in the predetermined common storage means at the end of the first process. game machine.

According to feature A11, it is possible to omit the process of setting the predetermined common information in the predetermined common storage means at the start of the second process. Thereby, the data capacity of the program for executing the second process can be reduced.

For the configuration of features A1 to A11, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the invention according to the characteristic group A, the following problems can be solved.

Pachinko machines, slot machines, and the like are known as game machines. For example, a pachinko machine is equipped with a plate storage section for storing game balls given to a player in the front part of the gaming machine, and the game balls stored in the plate storage section are guided to the game ball launching device, It is shot toward the game area according to the player's shooting operation. Then, for example, when a game ball enters a ball entry portion provided in the game area, the game ball is paid out from the payout device to the plate storage portion, for example. Further, in a pachinko machine, there is also known a configuration in which an upper plate storage portion and a lower plate storage portion are provided as the plate storage portions. , and surplus game balls in the upper plate storage portion are discharged to the lower plate storage portion.

Further, in the slot machine, when the start lever is operated to start a new game while medals are bet, the control means executes the lottery process. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in gaming machines such as those exemplified above, it is necessary to execute various processes appropriately, and there is still room for improvement in this respect.

<Characteristic group B>
Feature B1. Address information (lower 12 bits of start addresses SA0 to SA6, lower 12 bits of start addresses SB0 to SB23 in the first embodiment, lower 1 byte of addresses of maximum value counters 191a to 193a in the second embodiment) A specific address to be referenced using the set specific address information group (special special electric address table 64q, fluctuation start table 64r in the first embodiment, hard random number maximum value table 64w in the second embodiment) (the function of executing the command of line number "1708" in the main side CPU 63, the function of executing the command of line number "2605" in the main side CPU 63) for specifying the
Specific processing using the storage area corresponding to the specific address specified by the address specifying means (the processing of steps S903 to S910 of the main CPU 63 in the first embodiment, the main CPU 63 in the second embodiment (Maximum value setting execution processing in the main CPU 63 in the first embodiment) (the function of executing the processing of steps S903 to S910 of the main CPU 63 in the first embodiment, the maximum value setting in the main CPU 63 in the second embodiment function to execute execution processing) and
In a game machine equipped with
The specific address specified by the address specifying means using the specific address information group is information of a predetermined range of bits among a plurality of bits included in the specific address (data table reference address, maximum value counter 191a to 193a address common upper 1 byte) is common,
The game machine comprises specific storage means (IY register 109, TP register 111) capable of storing information of bits in the predetermined range,
The address information included in the specific address information group includes information other than the bits in the predetermined range among the plurality of bits included in the specific address (lower 12 bits of start addresses SA0 to SA6, start addresses SB0 to SB23 and the lower 1 byte of the addresses of the maximum value counters 191a to 193a) are set.

According to feature B1, the specific address can be specified using the address information set in the specific address information group. Since the address information set in the specific address information group is information other than the bits in the predetermined range among the plurality of bits included in the specific address, the address set in the specific address information group to specify the specific address The data capacity of the information can be reduced, and the data capacity of the specific address information group can be reduced.

Feature B2. The game machine according to feature B1, wherein the specific storage means is a predetermined register (IY register 109, TP register 111) provided in the control means.

According to feature B2, the control means can easily access a predetermined register storing information of a predetermined range of bits used for specifying a specific address. It is possible to eliminate the need to provide a dedicated storage area for storing information of a predetermined range of bits other than a predetermined register provided in the control means.

Feature B3. The specific address information group includes address information of a plurality of setting target areas (lower 1-byte data of the addresses of the maximum value counters 191a to 193a set in the hard random number maximum value table 64w in the second embodiment) and , numerical value information (maximum value data corresponding to the maximum value counters 191a to 193a of the hard random number maximum value table 64w in the second embodiment) set in the plurality of setting target areas, and
The address identifying means identifies an address of the setting target area to be referenced by using the specific address information group,
The specifying process executing means executes, as the specifying process, a process of setting the numerical information in the setting target area corresponding to the address specified by the address specifying means,
Information of the bits in the predetermined range among the plurality of bits included in the address of the setting target area is common,
information other than the predetermined range of bits among the plurality of bits included in the address of the setting target area is set in the specific address information group;
The gaming machine according to feature B1 or B2, wherein the address information of the setting target area set in the specific address information group has the same data capacity as the numerical information.

According to feature B3, the address information of the setting target area set in the specific address information group is set to information other than the bits in the predetermined range, so that the address information of the setting target area set in the specific address information group and the address information of the setting target area set in the specific address information group. The same data capacity can be used as the data capacity of the numerical information. Therefore, the data capacity of the specific address information group can be reduced compared to a configuration in which adjustment data that is not used in the specific address information group is set.

Feature B4. Characteristic features B1 to B3 characterized by comprising a setting means (a function of executing the processing of step S103 in the main CPU 63) for setting the information of the bits of the predetermined range in the specific storage means when the supply of operating power is started. The gaming machine according to any one of 1.

According to the feature B4, by setting the information of the bits in the predetermined range in the specific storage means when the supply of the operating power is started, the predetermined data stored in the specific storage means for specifying the specific address immediately after the supply of the operating power is started. A range of bits of information may be available.

Feature B5. The information of the predetermined range of bits stored in the specific storage means can be referred to by using another address information group (variation start table 64r in the first embodiment) in which a plurality of address information are set. The gaming machine according to any one of features B1 to B4, which is also used when specifying other addresses (start addresses SB0 to SB23).

According to feature B5, the information of the predetermined range of bits stored in the specific storage means is used when identifying a specific address, and is also used when identifying other addresses. Therefore, it is possible to eliminate the need for processing to change the information stored in the specific storage means.

Feature B6. The game according to any one of features B1 to B5, wherein the information other than the bits in the predetermined range is information arranged in the lower side than the information in the bits in the predetermined range in the specific address. machine.

According to characteristic B6, the information set in the program to specify the specific address can be only information other than the bits in the predetermined range on the lower side than the bits in the predetermined range in the specific address.

For the configuration of features B1 to B6, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the invention according to the characteristic group B, the following problems can be solved.

Pachinko machines, slot machines, and the like are known as game machines. For example, a pachinko machine is equipped with a plate storage section for storing game balls given to a player in the front part of the gaming machine, and the game balls stored in the plate storage section are guided to the game ball launching device, It is shot toward the game area according to the player's shooting operation. Then, for example, when a game ball enters a ball entry portion provided in the game area, the game ball is paid out from the payout device to the plate storage portion, for example. Further, in a pachinko machine, there is also known a configuration in which an upper plate storage portion and a lower plate storage portion are provided as the plate storage portions. , and surplus game balls in the upper plate storage portion are discharged to the lower plate storage portion.

Further, in the slot machine, when the start lever is operated to start a new game while medals are bet, the control means executes the lottery process. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in the gaming machines such as those exemplified above, it is necessary to make the data structure of the information group suitable, and there is still room for improvement in this respect.

<Characteristic group C>
Feature C1. Using the storage area corresponding to the specified address (LD update command, LDH update command, and transfer source address in LDB update command), predetermined corresponding processing (process for transferring information by LD update command, transfer of information by LDH update command) processing to transfer information by the LDB update command) (function of executing the LD update command by the LD update execution circuit 151, function of executing the LDH update command by the LDH update execution circuit 152, LDB a function of executing an LDB update command by the update execution circuit 161);
Address update means for updating the specified address when the predetermined corresponding process is executed (function of executing LD update instruction by LD update execution circuit 151, function of executing LDH update instruction by LDH update execution circuit 152, LDB update a function of executing an LDB update instruction by the execution circuit 161);
with
The instructions for executing the predetermined correspondence process and for updating the specified address after the execution of the predetermined correspondence process are integrated into a predetermined instruction (LD update instruction, LDH update instruction, LDB update instruction). game machine.

According to feature C1, by updating the specified address when the predetermined correspondence process is executed, the storage area corresponding to the specified address can be updated. The predetermined correspondence process and the process of updating the designated address after execution of the predetermined correspondence process can be executed with one instruction. Therefore, compared to a configuration in which a plurality of instructions are set in the program for executing these two processes, the configuration of the program for executing these two processes can be simplified, and the program data capacity can be reduced.

Feature C2. The predetermined correspondence process is a process of reading information stored in the storage area corresponding to the specified address to a read destination area (transfer destination in the instruction code of the LD update instruction, the LDH update instruction, and the LDB update instruction). The gaming machine according to feature C1, characterized by:

According to feature C2, the process of reading information stored in the storage area corresponding to the specified address to the read destination area and the process of updating the specified address after the process is executed can be executed with one instruction.

Feature C3. The predetermined command includes information designating the designated address and information designating the read destination area, and does not contain information designating the update amount of the designated address by the address updating means. The gaming machine according to feature C2, characterized by:

According to feature C3, the predetermined instruction does not include information specifying the amount of update of the designated address. The data capacity of instructions can be reduced.

Feature C4. The gaming machine according to any one of features C1 to C3, wherein an update amount of the designated address updated by the address updating means when the predetermined instruction is executed is fixed.

According to feature C4, by executing the predetermined instruction, the designated address can be updated in a fixed manner after the predetermined corresponding process is executed.

Feature C5. The gaming machine according to feature C4, wherein the update amount of the designated address updated by the address updating means when the predetermined command is executed is "1".

According to feature C5, by executing a predetermined instruction, the specified address can be updated by "1" after execution of the predetermined corresponding process.

Feature C6. After the initial designated address is set, the predetermined command execution means for repeatedly executing the predetermined command until the end is determined (the function of executing the processing of steps S301 to S305 of the main CPU 63 in the first embodiment , a function of executing the processing of line numbers "1101" to "1109" of the main side CPU 63).

According to feature C6, while updating the designated address, the predetermined correspondence processing is executed using the storage area corresponding to the designated address, and the processing of updating the designated address after the execution of the predetermined correspondence processing is repeatedly executed. can be done.

For the configuration of features C1 to C6, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Characteristic group D>
Feature D1. In a gaming machine in which an address is set for each storage area in units of a predetermined number of bytes (units of 1 byte) among storage areas provided in information storage means (main-side ROM 64),
Designated address information (in the LDH update instruction, the transfer source address information stored in the HL register 107; in the LDB instruction, the LDB update instruction, and the special LDB instruction, the acquired Area specifying means for specifying the storage area of the predetermined byte unit corresponding to the start address) (function of executing LDH update instruction in LDH update execution circuit 152, function of LDB execution circuit 157 executing LDB instruction, LDB update execution circuit 161 to execute an LDB update instruction, a function to execute a special LDB instruction by a special LDB execution circuit 201);
Bit specifying means for specifying a part of the bits of the storage area specified by the area specifying means as the target of use (function for executing LDH update instruction in LDH update execution circuit 152, LDB instruction by LDB execution circuit 157) a function to execute an LDB update command by the LDB update execution circuit 161, a function to execute a special LDB command by the special LDB execution circuit 201);
A game machine characterized by comprising:

According to feature D1, it is possible to specify some bits of the storage area in units of a predetermined number of bytes to be used. Since information can be aggregated in the information storage means in units smaller than a predetermined number of bytes, the data volume of information stored in the information storage means can be reduced.

Feature D2. Means (LDH update execution circuit 152 in function of executing an LDH update command).

According to feature D2, in the configuration having the configuration of feature D1 and in which some bits of the predetermined byte unit storage area specified by the area specifying means are specified as being used, another part of the storage area bits are also specified for use. Since some bits and some other bits stored in one predetermined byte unit storage area can be specified as being used, two pieces of information (some bits and some other bits ) can be aggregated and set in one predetermined byte unit storage area. As a result, the data capacity of information set in the information storage means can be reduced.

Feature D3. The number of bits (4 bits) of the part of the bits specified as the target of use and the number of bits (4 bits) of the other part of the storage area specified by the area specifying means is the same. The gaming machine according to feature D2.

According to the feature D3, since it is possible to specify a part of bits having the same number of bits and a part of other bits to be used in one predetermined byte unit storage area, 2 bits having the same number of bits One piece of information (a part of bits and a part of other bits) can be aggregated and set in one predetermined byte unit storage area.

Feature D4. A first readout means (LDH update execution circuit) that reads the part of the bits specified as the target of use in the storage area of the predetermined byte unit specified by the area specifying means into the first readout target area (W register 104a) 152), and
A second readout means (LDH update) that reads the other part of the bits specified as use targets in the storage area of the predetermined byte unit specified by the area specifying means to the second readout target area (A register 104b) a function of executing an LDH update instruction in the execution circuit 152);
The gaming machine according to feature D2 or D3, characterized by comprising:

According to feature D4, part of the bits specified to be used in the predetermined byte unit storage area specified by the area specifying means are read into the first read target area, thereby separating them from the other part of the bits. can be used. In addition, by reading out the other part of the bits specified to be used in the storage area into the second readout area, it is possible to use them separately from the part of the bits.

Feature D5. The information of the bits for which information reading has not been performed in the first read target area and the second read target area is predetermined binary information (information of "0") which is one of binary information. The gaming machine according to the characterizing feature D4.

According to feature D5, the first read target area is set with a part of the bits specified as the use target in the predetermined byte unit storage area specified by the area specifying means, and the specified binary information. can be In addition, it is possible to set the second read target area to a state in which the other part of the bits specified as the use target in the storage area of the predetermined byte unit and the predetermined binary information are set.

Feature D6. specifying the storage area of the predetermined byte unit corresponding to the specified address information, specifying the part of the bits in the storage area specified by the area specifying means as a target for use, and specifying the part of the bits reading into the first read target area, specifying the other part of the bits in the storage area specified by the area specifying means as a use target, and the second reading of the other part of the bits The gaming machine according to feature D4 or D5, wherein the command to read to the target area is concentrated in a specific command (LDH update command).

According to characteristic D6, the process of specifying a storage area in units of a predetermined number of bytes corresponding to the specified address information, the process of specifying a part of the bits of the storage area specified by the area specifying means as a target for use, the part of the A process of reading bits into a first read target area, a process of specifying other part of the bits in the storage area specified by the area specifying means as a use target, and a second read target area of the other part of the bits can be executed with one instruction. Therefore, compared to a configuration in which a plurality of instructions for executing these processes are set in the program, the configuration of the program for executing these processes can be simplified, and the data of the program can be simplified. Capacity can be reduced.

Feature D7. The specific command includes information specifying the specified address information (for example, information of "(HL+)" in the LDH update command "LDH WA, (HL+)"), information specifying the first read target area ( "WA" information in the LDH update command "LDH WA, (HL+)") and information specifying the second read target area ("WA" information in the LDH update command "LDH WA, (HL+)" ) is set, and the number of bits of the part of the bits and the part of the other bits (the number of bits of information read out to the W register 104a and the number of bits of information read out to the A register 104b). The gaming machine according to feature D6, wherein is not set.

According to feature D7, a specific command can be executed by specifying the specified address information, the first read target area, and the second read target area. The data capacity of a specific instruction can be reduced compared to a configuration in which information designating bit allocation of some bits and some other bits is set in the specific instruction.

Feature D8. the part of the bits specified to be used in the storage area specified by the area specifying means are bits whose arrangement order is continuous in the storage area;
Characteristic features D2 through D2, characterized in that the other part of the bits specified to be used in the storage area specified by the area specifying means are bits arranged consecutively in the storage area. The gaming machine according to any one of D7.

According to feature D8, it is possible to specify some bits and some other bits to be used while maintaining the arrangement order from the predetermined byte unit storage area provided in the information storage means.

Feature D9. According to any one of features D1 to D8, the part of the bits specified as the target of use by the bit specifying means is part of the bits in one of the predetermined byte-unit storage areas. game machine.

According to the feature D9, it is possible to specify a part of bits of a storage area of one predetermined byte unit as a use target.

Feature D10. Reference bit information (LDB instruction, LDB update instruction and special bits to be used based on the acquisition start bit in the LDB instruction) and the reference number information (data specifying the number of bits to be acquired in the LDB instruction, the LDB update instruction, and the special LDB instruction) that enables the number of bits to be used as the reference for use. It is characterized by having specifying means (a function of executing an LDB instruction in the LDB execution circuit 157, a function of executing an LDB update instruction in the LDB update execution circuit 161, and a function of executing a special LDB instruction in the special LDB execution circuit 201). The gaming machine according to feature D1.

According to feature D10, in a configuration in which an address is set for each storage area in units of a predetermined number of bytes among storage areas provided in the information storage means, among a plurality of bits in the storage area specified by the area specifying means, A bit group including some bits can be specified as a utilization target. In addition, information can be aggregated in bit units in the information storage means. As a result, the data capacity of information stored in the information storage means can be reduced.

Feature D11. The reference bit information is information (acquisition start bit) specifying a start bit of the bit group specified as a target of use by the bit specifying means in the storage area specified by the area specifying means. The gaming machine according to feature D10.

According to feature D11, the start bit of the bit group specified as the target of use in the storage area specified by the area specifying means can be specified by the reference bit information.

Feature D12. The gaming machine according to feature D10 or D11, wherein the bit group is bits arranged consecutively in the information storage means.

According to the feature D12, it is possible to specify bits arranged consecutively in the information storage means as a bit group to be used.

Feature D13. The bit group specified as a use target by the bit specifying means is read in the predetermined byte unit read target area (transfer destination W register 104a or HL register 107 in the LDB instruction, transfer destination WA register 104 or W register in the LDB update instruction). 104a or B register 105a, the HL register 107 of the transfer destination in the special LDB instruction) read information reading means (function of executing the LDB instruction by the LDB execution circuit 157, function of executing the LDB update instruction by the LDB update execution circuit 161, special function of executing a special LDB instruction by the LDB execution circuit 201),
Any one of the features D10 to D12, wherein the information of the bits whose information has not been read in the read target area is the same information ("0" information) that is one of the binary information. 1. The game machine according to 1.

According to feature D13, the bit group specified as the target of use by the bit specifying means in the information storage means can be read into the read target area and used. The bit group can be used in such a manner that each bit in an area from which the bit group is not read in the read target area is the same information, which is one of binary information.

Feature D14. Characteristic feature D13, characterized in that the number of bits of the bit group read by the information reading means into the read target area is larger than the number of bits of information set in the storage area in units of one of the predetermined bytes. game machine.

According to the feature D14, information with a data volume exceeding a predetermined number of bytes can be read from the information storage means to the read target area. In addition, information with a data volume exceeding a predetermined number of bytes can be aggregated in the information storage means.

Feature D15. specifying the storage area of the predetermined byte unit corresponding to the specified address information, and specifying a bit group including a part of the plurality of bits in the storage area specified by the area specifying means as the reference bit information and specifying as a use target based on the reference number information; reading the bit group specified as a use target by the bit specifying means into the read target area; and bits whose information has not been read in the read target area. is the same information that is one of the binary information is aggregated as a specific instruction (LDB instruction, LDB update instruction, special LDB instruction) The gaming machine according to feature D13 or D14.

According to feature D15, a process of specifying a storage area in units of predetermined bytes corresponding to specified address information, and a bit group including a part of a plurality of bits in the storage area specified by the area specifying means is used as the reference bit information. and a process of specifying as a use target based on the reference number information, a process of reading the bit group specified as a use target by the bit specifying means to the read target area, and the information of the bit whose information was not read in the read target area is set to 2 One instruction can execute a process of making one of the value information pieces the same information. Therefore, compared to a configuration in which a plurality of instructions for executing these processes are set in the program, the configuration of the program for executing these processes can be simplified, and the data of the program can be simplified. Capacity can be reduced.

Feature D16. The specific command includes information specifying predetermined information (obtained data specifying data) used for calculating the specified address information and the reference bit information (that the acquired data specifying data is stored in the HL register 107). ) is set, and the specified address information and the reference bit information are not set.

According to the characteristic D16, the specific instruction is set with predetermined information used for calculating the specified address information and the reference bit information, and the specified address information and the reference bit information are not set. Compared to a configuration in which the specified address information and the reference bit information are set in the instruction, the data capacity of the information set in the specific instruction can be reduced.

Feature D17. The gaming machine according to feature D16, wherein the reference number information is set in the specific command.

According to the feature D17, by setting the reference number information in the specific command, it is possible to specify the number of bits to be used as the reference.

Feature D18. The gaming machine according to feature D16 or D17, wherein information specifying a method of calculating the specified address information and the reference bit information using the predetermined information is not set in the specific command.

According to feature D18, the data volume of the information set in the specific instruction is reduced compared to the configuration in which the specific instruction is set with information designating the method of calculating the designated address information and the reference bit information. can be done.

Feature D19. First predetermined information of the first predetermined number of bits ("13" in the first embodiment, "12" in the sixth embodiment) data of the upper 13 bits (in the sixth embodiment, data of the upper 12 bits of the acquisition data designation data in the special LDB instruction) and a second predetermined number of bits arranged on the lower side than the first predetermined information (the first ("3" in the embodiment, "4" in the sixth embodiment) of the second predetermined information (lower 3-bit data of the acquired data designation data in the LDB instruction and the LDB update instruction in the first embodiment, the sixth In the embodiment, means for reading predetermined information (acquisition data designation data) having the lower 4-bit data of the acquisition data designation data in the special LDB command (the function of executing the LDB command by the LDB execution circuit 157, the LDB update execution circuit 161 function to execute the LDB update instruction by the special LDB execution circuit 201),
The area specifying means is
By executing a predetermined arithmetic processing on the predetermined information, the quotient obtained by dividing by a binary value larger by "1" than the maximum value of the binary numerical value information that can be set by the second predetermined number of bits is Derivation means for deriving corresponding information (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161, and a function of executing a special LDB command by the special LDB execution circuit 201); ,
Address generating means for generating the specified address information using the information derived by the deriving means (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161, a special a function of executing a special LDB instruction by the LDB execution circuit 201;
The gaming machine according to any one of features D10 to D18, characterized by comprising:

According to the feature D19, by performing a predetermined arithmetic processing on the predetermined information, it is divided by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set with the second predetermined number of bits. Information corresponding to the quotient of cases can be derived. Then, the specified address information can be generated using the information derived by the deriving means.

Feature D20. the first predetermined information and the second predetermined information are continuous in a bit arrangement order,
the least significant bit of the second predetermined information is the least significant bit of the predetermined information;
The information derived by the deriving means is information arranged such that the least significant bit in the bit array of the first predetermined information is the least significant bit of the derived information. The gaming machine described in D19.

According to feature D20, by executing a predetermined arithmetic process on predetermined information, a predetermined The first predetermined information in the information can be shifted to the lower side by the second predetermined number of bits.

Feature D21. Information derived by the deriving means (quotient data obtained by dividing the acquired data designation data by "8" for the LDB command and the LDB update command, quotient data obtained by dividing the obtained data designation data by "16" for the special LDB command) data), each bit existing on the upper side of the bit array of the first predetermined information is the same information ("0" information) that is one of the binary information, or The gaming machine described in D20.

According to the feature D21, by executing the predetermined arithmetic processing on the predetermined information, each bit existing on the upper side of the bit array of the first predetermined information has the same information as one of the binary information. The set information can be generated and the information can be used.

Feature D22. The bit identifying means includes information extracting means for extracting the second predetermined information from the predetermined information and generating the reference bit information (a function of executing an LDB command by the LDB execution circuit 157, an LDB update by the LDB update execution circuit 161, A game machine according to any one of features D19 to D21, characterized by having a command execution function and a function of executing a special LDB command by a special LDB execution circuit 201).

According to feature D22, in a configuration in which the first predetermined information and the second predetermined information are integrated into the predetermined information, the second predetermined information can be extracted from the predetermined information to generate the reference bit number information.

Feature D23. The information extracting means extracts information including the second predetermined information (lower 1 byte of acquisition data designation data) and mask data (data "00000111B" for LDB command and LDB update command, data "00001111B" for special LDB command). ) to extract the second predetermined information from the predetermined information.

According to feature D23, by using mask data, the first predetermined information included in the predetermined information can be masked, and the second predetermined information included in the predetermined information can be extracted.

Feature D24. The gaming machine according to any one of features D19 to D23, wherein the predetermined information is information in units of the predetermined bytes.

According to feature D24, the first predetermined information and the second predetermined information can be aggregated into predetermined information in units of predetermined bytes. Therefore, compared to a configuration in which information enabling the use of the second predetermined information exists separately from the information enabling the use of the first predetermined information, it is possible to reduce the total data capacity of these pieces of information. can.

For the configuration of features D1 to D24, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Characteristic group E>
Features E1. In a gaming machine in which an address is set for each storage area in units of a predetermined number of bytes (units of 1 byte) among storage areas provided in information storage means (main-side ROM 64),
Area identification for identifying the storage area in the predetermined byte unit corresponding to the specified address information (the acquisition start address calculated from the acquired data specifying data stored in the HL register 107 in the LDB instruction, LDB update instruction, and special LDB instruction) means (the function of executing the LDB instruction by the LDB execution circuit 157, the function of executing the LDB update instruction by the LDB update execution circuit 161, the function of executing the special LDB instruction by the special LDB execution circuit 201);
Reference bit information (acquisition start bit number) and use target for specifying a bit group including a part of the bits in the storage area specified by the area specifying means as a use target reference bit Bit identification means (function to execute LDB instruction by LDB execution circuit 157, LDB by LDB update execution circuit 161, LDB instruction by LDB execution circuit 157, LDB update execution circuit 161) a function of executing an update instruction, a function of executing a special LDB instruction by the special LDB execution circuit 201);
A game machine characterized by comprising:

According to the feature E1, it is possible to specify a bit group including a part of the plurality of bits in the predetermined byte unit storage area specified by the area specifying means as a utilization target. Since the information of the bit group can be collectively set in the information storage means, the data capacity of the information stored in the information storage means can be reduced.

Feature E2. The reference bit information is information (acquisition start bit) specifying a start bit of the bit group specified as a target of use by the bit specifying means in the storage area specified by the area specifying means. The gaming machine according to feature E1.

According to feature E2, it is possible to specify the start bit of the bit group specified as the target of use in the storage area specified by the area specifying means using the reference bit information.

Feature E3. The gaming machine according to feature E1 or E2, wherein the bit group is bits arranged consecutively in the information storage means.

According to the feature E3, it is possible to specify bits that are consecutively arranged in the information storage unit as the bit group to be used.

Feature E4. The bit group specified as a use target by the bit specifying means is read in the predetermined byte unit read target area (transfer destination W register 104a or HL register 107 in the LDB instruction, transfer destination WA register 104 or W register in the LDB update instruction). 104a or B register 105a, the HL register 107 of the transfer destination in the special LDB instruction) read information reading means (function of executing the LDB instruction by the LDB execution circuit 157, function of executing the LDB update instruction by the LDB update execution circuit 161, special function of executing a special LDB instruction by the LDB execution circuit 201),
Any one of features E1 to E3, characterized in that the information of the bits whose information has not been read in the read target area is the same information (“0” information) that is one of binary information. 1. The game machine according to 1.

According to feature E4, the bit group specified as the target of use by the bit specifying means in the information storage means can be read into the read target area and used. The bit group can be used in such a manner that each bit in an area from which the bit group is not read in the read target area is the same information, which is one of binary information.

Feature E5. Characteristic feature E4, characterized in that the number of bits of the bit group read by the information reading means into the read target area is larger than the number of bits of information set in the storage area of one of the predetermined byte units. game machine.

According to feature E5, information with a data capacity exceeding a predetermined number of bytes can be read from the information storage means to the read target area. In addition, information with a data volume exceeding a predetermined number of bytes can be aggregated in the information storage means.

Feature E6. specifying the storage area of the predetermined byte unit corresponding to the specified address information, and specifying a bit group including a part of the plurality of bits in the storage area specified by the area specifying means as the reference bit information and specifying as a use target based on the reference number information; reading the bit group specified as a use target by the bit specifying means into the read target area; and bits whose information has not been read in the read target area. is the same information that is one of the binary information is aggregated as a specific instruction (LDB instruction, LDB update instruction, special LDB instruction) The gaming machine according to feature E4 or E5.

According to characteristic E6, a process of specifying a storage area of a predetermined byte unit corresponding to specified address information, and a bit group including a part of a plurality of bits in the storage area specified by the area specifying means is used as the reference bit information. and a process of specifying as a use target based on the reference number information, a process of reading the bit group specified as a use target by the bit specifying means to the read target area, and the information of the bit whose information was not read in the read target area is set to 2 One instruction can execute a process of making one of the value information pieces the same information. Therefore, compared to a configuration in which a plurality of instructions for executing these processes are set in the program, the configuration of the program for executing these processes can be simplified, and the data of the program can be simplified. Capacity can be reduced.

Feature E7. The specific command includes information specifying predetermined information (obtained data specifying data) used for calculating the specified address information and the reference bit information (that the acquired data specifying data is stored in the HL register 107). ) is set, and the specified address information and the reference bit information are not set.

According to the feature E7, the specific instruction is set with predetermined information used for calculating the specified address information and the reference bit information, and the specified address information and the reference bit information are not set. Compared to a configuration in which the specified address information and the reference bit information are set in the instruction, the data capacity of the information set in the specific instruction can be reduced.

Feature E8. The gaming machine according to feature E7, wherein the reference number information is set in the specific command.

According to the feature E8, by setting the reference number information in the specific command, it is possible to specify the number of bits to be used as the reference.

Feature E9. The gaming machine according to feature E7 or E8, wherein information specifying a method of calculating the specified address information and the reference bit information using the predetermined information is not set in the specific command.

According to feature E9, the data volume of information set in the specific instruction is reduced compared to a configuration in which information designating a method of calculating the designated address information and the reference bit information is set in the specific instruction. can be done.

Feature E10. First predetermined information of the first predetermined number of bits ("13" in the first embodiment, "12" in the sixth embodiment) data of the upper 13 bits (in the sixth embodiment, data of the upper 12 bits of the acquisition data designation data in the special LDB instruction) and a second predetermined number of bits arranged on the lower side than the first predetermined information (the first ("3" in the embodiment, "4" in the sixth embodiment) of the second predetermined information (lower 3-bit data of the acquired data designation data in the LDB instruction and the LDB update instruction in the first embodiment, the sixth In the embodiment, means for reading predetermined information (acquisition data designation data) having the lower 4-bit data of the acquisition data designation data in the special LDB command (the function of executing the LDB command by the LDB execution circuit 157, the LDB update execution circuit 161 function to execute the LDB update instruction by the special LDB execution circuit 201),
The area specifying means is
By executing a predetermined arithmetic processing on the predetermined information, the quotient obtained by dividing by a binary value larger by "1" than the maximum value of the binary numerical value information that can be set by the second predetermined number of bits is Derivation means for deriving corresponding information (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161, and a function of executing a special LDB command by the special LDB execution circuit 201); ,
Address generating means for generating the specified address information using the information derived by the deriving means (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161, a special a function of executing a special LDB instruction by the LDB execution circuit 201;
The gaming machine according to any one of features E1 to E9, characterized by comprising:

According to the characteristic E10, by performing a predetermined arithmetic processing on the predetermined information, the binary value is divided by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set with the second predetermined number of bits. Information corresponding to the quotient of cases can be derived. Then, the specified address information can be generated using the information derived by the deriving means.

Feature E11. the first predetermined information and the second predetermined information are continuous in a bit arrangement order,
the least significant bit of the second predetermined information is the least significant bit of the predetermined information;
The information derived by the deriving means is information arranged such that the least significant bit in the bit array of the first predetermined information is the least significant bit of the derived information. The gaming machine described in E10.

According to feature E11, by executing a predetermined operation on predetermined information, a predetermined The first predetermined information in the information can be shifted to the lower side by the second predetermined number of bits.

Feature E12. Each bit of the information derived by the deriving means, which exists on the upper side of the bit array of the first predetermined information, is the same information ("0" information) which is one of the binary information. A gaming machine according to characterizing feature E10 or E11.

According to feature E12, by executing the predetermined arithmetic processing on the predetermined information, each bit existing on the upper side of the bit array of the first predetermined information has the same information as one of binary information. The set information can be generated and the information can be used.

Feature E13. The bit identifying means includes information extracting means for extracting the second predetermined information from the predetermined information and generating the reference bit information (a function of executing an LDB command by the LDB execution circuit 157, an LDB update by the LDB update execution circuit 161, A game machine according to any one of features E10 to E12, characterized in that it has a command execution function and a function of executing a special LDB command by a special LDB execution circuit 201).

According to the feature E13, in a configuration in which the first predetermined information and the second predetermined information are aggregated into the predetermined information, the second predetermined information can be extracted from the predetermined information to generate the reference bit number information.

Feature E14. The information extracting means extracts information including the second predetermined information (lower 1 byte of acquisition data designation data) and mask data (data "00000111B" for LDB command and LDB update command, data "00001111B" for special LDB command). ) to extract the second predetermined information from the predetermined information.

According to feature E14, by using mask data, the first predetermined information included in the predetermined information can be masked, and the second predetermined information included in the predetermined information can be extracted.

Feature E15. The gaming machine according to any one of characteristics E10 to E14, wherein the predetermined information is information in units of the predetermined bytes.

According to feature E15, the first predetermined information and the second predetermined information can be aggregated into predetermined information in units of predetermined bytes. Therefore, compared to a configuration in which information enabling the use of the second predetermined information exists separately from the information enabling the use of the first predetermined information, it is possible to reduce the total data capacity of these pieces of information. can.

For the configuration of features E1 to E15, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Feature group F>
Feature F1. In a gaming machine in which an address is set for each storage area in units of a predetermined number of bytes (units of 1 byte) among storage areas provided in information storage means (main-side ROM 64),
Area identification for identifying a storage area in units of predetermined bytes corresponding to designated address information (acquisition start address calculated from acquisition data designation data stored in HL register 107 in LDB instruction, LDB update instruction and special LDB instruction) means (the function of executing the LDB instruction by the LDB execution circuit 157, the function of executing the LDB update instruction by the LDB update execution circuit 161, the function of executing the special LDB instruction by the special LDB execution circuit 201);
The information stored in some bits of the storage area specified by the area specifying means is transferred to the predetermined byte unit read target area (transfer destination W register 104a or HL register 107 in LDB instruction, LDB update instruction WA register 104, W register 104a or B register 105a of the transfer destination in , and HL register 107) of the transfer destination in the special LDB instruction, and the information of the bit whose information was not read in the read target area is binary information Information reading means (a function of executing an LDB instruction by the LDB execution circuit 157, a function of executing an LDB update instruction by the LDB update execution circuit 161, which is one of the predetermined binary information ("0" information)) a function of executing a special LDB instruction by the special LDB execution circuit 201);
A game machine characterized by comprising:

According to the feature F1, information stored in some bits of the predetermined byte unit storage area can be read to the read target area and used. A state in which the information stored in the part of the bits is read into the read target area, and the information of the bits not read out in the read target area is predetermined binary information. , the information of the read target area can be used. Since the information stored in some bits of the predetermined byte unit storage area can be read out and used in the read target area, the information can be collectively set in the information storage means. As a result, the data capacity of information stored in the information storage means can be reduced.

Feature F2. specifying the storage area of the predetermined byte unit corresponding to the specified address information, and reading information stored in a part of bits of the storage area specified by the area specifying means into the read target area; Instructions for making the information of bits whose information has not been read in the read target area become the predetermined binary information are aggregated into predetermined transfer instructions (LDB instruction, LDB update instruction, special LDB instruction). The gaming machine according to feature F1, characterized in that

According to feature F2, a process of specifying a storage area in units of predetermined bytes corresponding to specified address information, and reading information stored in some bits of the storage area specified by the area specifying means into a read target area. A single instruction can execute a process of making the information of bits whose information has not been read in the read target area become predetermined binary information. Therefore, compared to a configuration in which a plurality of instructions are set for executing these processes, the configuration of the program can be simplified and the data capacity of the program can be reduced.

Feature F3. The information reading means reads information stored in some bits of the storage area specified by the area specifying means as a lower side area (lower side area of WA register 104) including the least significant bit in the read target area. bit, lower bit of W register 104a, lower bit of B register 105a, lower bit of HL register 107), and the upper area (WA Characteristic feature F1 or F2, characterized in that the predetermined binary information is set in each bit of the high-order bit of the register 104, the high-order bit of the W register 104a, the high-order bit of the B register 105a, and the high-order bit of the HL register 107). game machine.

According to feature F3, information stored in some bits in the storage area specified by the area specifying means can be set in the lower side area of the read target area. Predetermined binary information is set in each bit of the upper region in the read target area. Therefore, only the information stored in some bits of the storage area specified by the area specifying means and the predetermined binary information are set in the read target area while eliminating the need for the process of clearing the read target area in advance. It can be in a state where

Feature F4. Features F1 to F3, wherein the information read by the information reading means to the read target area is information of a part of bits whose arrangement order is continuous in the storage area specified by the area specifying means. The gaming machine according to any one of 1.

According to feature F4, information stored in some bits of the storage area specified by the area specifying means is read out to the read target area in a manner in which the arrangement order of the some bits is maintained, and used. can do.

Feature F5. The gaming machine according to any one of features F1 to F4, wherein the number of bits of the information read to the read target area by the information reading means is larger than the predetermined number of bytes.

According to feature F5, in the information storage means, information having a larger number of bits than the number of bits of information set in one predetermined byte storage area corresponding to one address can be read to the read target area.

Feature F6. The read target area includes predetermined registers provided in the control means (W register 104a or HL register 107 as the transfer destination in the LDB instruction, WA register 104, W register 104a or B register 105a as the transfer destination in the LDB update instruction, special The game machine according to any one of features F1 to F5, which is the HL register 107) of the transfer destination in the LDB instruction.

According to feature F6, the control means can easily access a predetermined register from which information stored in some bits of the storage area specified by the area specifying means is read.

Feature F7. The information reading means includes bit number specifying means for specifying the number of bits of information to be read from the storage area specified by the area specifying means to the read target area. The gaming machine according to any one of features F1 to F6, characterized in that it has a function of executing an LDB update instruction in the execution circuit 161 and a function of executing a special LDB instruction in the special LDB execution circuit 201.

According to the feature F7, information can be read from the information storage means to the read target area by designating the number of bits. For this reason, information can be collectively set in the information storage means in units of bits. As a result, the data capacity of information stored in the information storage means can be reduced.

For the configuration of features F1 to F7, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

<Characteristic group G>
Feature G1. First predetermined information of the first predetermined number of bits ("13" in the first embodiment, "12" in the sixth embodiment) data of the upper 13 bits (in the sixth embodiment, data of the upper 12 bits of the acquisition data designation data in the special LDB instruction) and a second predetermined number of bits arranged on the lower side than the first predetermined information (the first ("3" in the embodiment, "4" in the sixth embodiment) of the second predetermined information (lower 3-bit data of the acquired data designation data in the LDB instruction and the LDB update instruction in the first embodiment, the sixth In the embodiment, means for reading predetermined information (acquisition data designation data) having the lower 4-bit data of the acquisition data designation data in the special LDB command (the function of executing the LDB command by the LDB execution circuit 157, the LDB update execution circuit 161 function to execute the LDB update instruction by the special LDB execution circuit 201);
By executing a predetermined arithmetic processing on the read-out predetermined information, the value obtained by dividing by a binary value larger by "1" than the maximum value of the binary numerical information that can be set by the second predetermined number of bits is obtained. Derivation means for deriving information corresponding to the quotient (a function of executing an LDB instruction by the LDB execution circuit 157, a function of executing an LDB update instruction by the LDB update execution circuit 161, a function of executing a special LDB instruction by the special LDB execution circuit 201, )and,
A game machine characterized by comprising:

According to the feature G1, by performing a predetermined arithmetic processing on the predetermined information, it is divided by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set with the second predetermined number of bits. Information corresponding to the quotient of cases can be derived.

Feature G2. the first predetermined information and the second predetermined information are continuous in a bit arrangement order,
the least significant bit of the second predetermined information is the least significant bit of the predetermined information;
The information derived by the deriving means is information arranged such that the least significant bit in the bit array of the first predetermined information is the least significant bit of the derived information. The gaming machine described in G1.

According to feature G2, by executing a predetermined arithmetic process on predetermined information, a predetermined The first predetermined information in the information can be shifted to the lower side by the second predetermined number of bits.

Feature G3. Each bit of the information derived by the deriving means, which exists on the upper side of the bit array of the first predetermined information, is the same information ("0" information) which is one of the binary information. The gaming machine according to the characterizing feature G1 or G2.

According to feature G3, by executing the predetermined arithmetic processing on the predetermined information, each bit existing on the upper side of the bit array of the first predetermined information has the same information as one of binary information. The set information can be generated and the information can be used.

Feature G4. Information extraction means for extracting the second predetermined information from the predetermined information (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161, a special LDB by the special LDB execution circuit 201 A gaming machine according to any one of features G1 to G3, characterized in that it has a function of executing commands.

According to feature G4, in a configuration in which the first predetermined information and the second predetermined information are integrated into the predetermined information, the second predetermined information can be extracted from the predetermined information and the second predetermined information can be used alone. can.

Feature G5. The information extracting means extracts information including the second predetermined information (lower 1 byte of acquisition data designation data) and mask data (data "00000111B" for LDB command and LDB update command, data "00001111B" for special LDB command). ) to extract the second predetermined information from the predetermined information.

According to feature G5, by using mask data, the first predetermined information included in the predetermined information can be masked, and the second predetermined information included in the predetermined information can be extracted.

Feature G6. By executing the predetermined arithmetic processing on the predetermined information, the quotient when divided by a binary value larger by "1" than the maximum value of the binary numerical information that can be set by the second predetermined number of bits and extracting the second predetermined information from the predetermined information are integrated into predetermined instructions (LDB instruction, LDB update instruction, special LDB instruction) The gaming machine according to feature G4 or G5.

According to the characteristic G6, by executing a predetermined arithmetic processing on the predetermined information, it is divided by a binary value larger by "1" than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. The process of deriving the information corresponding to the quotient of cases and the process of extracting the second predetermined information from the predetermined information can be executed with one instruction. Therefore, compared to a configuration in which a plurality of instructions are set in the program for executing these two processes, the configuration of the program for executing these two processes can be simplified, and the program data capacity can be reduced.

Feature G7. The game machine according to any one of features G1 to G6, wherein the predetermined information is information in units of predetermined bytes.

According to feature G7, the first predetermined information and the second predetermined information can be aggregated into predetermined information in units of predetermined bytes. Therefore, compared to a configuration in which information enabling the use of the second predetermined information exists separately from the information enabling the use of the first predetermined information, it is possible to reduce the total data capacity of these pieces of information. can.

Feature G8. The game machine according to any one of features G1 to G7, wherein the predetermined information has a data capacity of 2 bytes.

According to feature G8, the data volume of the predetermined information in which the first predetermined information and the second predetermined information are aggregated can be suppressed to 2 bytes.

Feature G9. information storage means (main-side ROM 64) in which an address is set for each storage area of a predetermined byte unit (1 byte unit);
Area specifying means (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161) for specifying the storage area of the predetermined byte unit using the information derived by the derivation means a function of executing a special LDB instruction by the special LDB execution circuit 201);
A bit specifying means for specifying a bit group including a part of the bits in the storage area specified by the area specifying means as a use target (a function of executing an LDB instruction by the LDB execution circuit 157, LDB update execution a function of executing an LDB update instruction by the circuit 161, a function of executing a special LDB instruction by the special LDB execution circuit 201;
The gaming machine according to any one of features G1 to G8, characterized by comprising:

According to feature G9, it is possible to specify a storage area in units of predetermined bytes by using information derived by the deriving means using predetermined information. A bit group including a part of the plurality of bits in the storage area specified by the area specifying means can be specified as a utilization target. Since the information can be aggregated in the information storage means in units of bits, the data capacity of the information stored in the information storage means can be reduced.

Feature G10. Information extraction means for extracting the second predetermined information from the predetermined information (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161, a special LDB by the special LDB execution circuit 201 function to execute instructions),
The bit identifying means uses the second predetermined information extracted by the information extracting means to identify a bit group including a part of the plurality of bits in the storage area identified by the area identifying means. The gaming machine according to feature G9, which is specified as an object to be used.

According to feature G10, in a configuration having the configuration of feature G9 and capable of specifying a storage area in units of predetermined bytes using predetermined information, using second predetermined information extracted from the predetermined information , a bit group including a part of the plurality of bits in the storage area specified by the area specifying means can be specified as an object to be used. Information for specifying a storage area in units of predetermined bytes and information for specifying a bit group to be used can be aggregated into predetermined information. As a result, it is possible to reduce the total data capacity of the information for specifying the storage area in units of predetermined bytes and the information for specifying the bit group to be used.

For the configuration of features G1 to G10, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the inventions according to the feature group C, the feature group D, the feature group E, the feature group F, and the feature group G, the following problems can be solved.

Pachinko machines, slot machines, and the like are known as gaming machines. For example, a pachinko machine is equipped with a plate storage section for storing game balls given to a player in the front part of the gaming machine, and the game balls stored in the plate storage section are guided to the game ball launching device, It is shot toward the game area according to the player's shooting operation. Then, for example, when a game ball enters a ball entry portion provided in the game area, the game ball is paid out from the payout device to the plate storage portion, for example. Further, in a pachinko machine, there is also known a configuration in which an upper plate storage portion and a lower plate storage portion are provided as the plate storage portions. , and surplus game balls in the upper plate storage portion are discharged to the lower plate storage portion.

Further, in the slot machine, when the start lever is operated to start a new game while medals are bet, the control means executes the lottery process. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to the winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in gaming machines such as those exemplified above, it is necessary to execute various processes appropriately, and there is still room for improvement in this respect.

<Characteristic group H>
Feature H1. Transmission means for transmitting a predetermined information group (command for communication) (function to execute processing of steps S2001 to S2008 in main CPU 63, function to execute processing of steps S2101 to S2113 in main CPU 63, main CPU 63 , a function of executing the processing of steps S2201 to S2215 in the main CPU 63, and a function of executing the processing of steps S2301 to S2317 in the main CPU 63),
The predetermined information group includes a plurality of unit information (header HD, data frames FR1 to FR10, top frames SF1 and SF2, footer FT) in predetermined byte units (1 byte units),
In the predetermined byte unit information at the beginning of the predetermined information group, information at a predetermined position bit (most significant bit) is specific bit information ("1" information),
A gaming machine, wherein the unit information of the predetermined byte unit other than the head in the predetermined information group is information of the bit at the predetermined position (information of "0") other than the specific bit information.

According to the feature H1, based on the state of a bit at a predetermined position in each predetermined byte unit information of the predetermined information group, identification is made between the first predetermined byte unit information and the predetermined byte unit information other than the first byte unit information. can be made possible. By making it possible to grasp the unit information in units of predetermined bytes at the beginning, when a plurality of predetermined information groups are received, it is possible to grasp the separation position between the predetermined information groups.

Feature H2. The gaming machine according to feature H1, wherein the bit at the predetermined position is 1 bit.

According to feature H2, the number of bits set in the unit information of each predetermined byte unit is minimized in order to distinguish between the unit information of predetermined byte units at the beginning and the unit information of predetermined byte units other than the beginning. can be set to "1". As a result, in each predetermined byte unit information, the number of bits in which information other than the information for making it possible to distinguish between the first predetermined byte unit information and the predetermined byte unit information other than the first byte unit information is set is increased. can be secured.

Feature H3. The gaming machine according to feature H1 or H2, wherein the bit at the predetermined position is the most significant bit (seventh bit) in the unit information of the predetermined byte unit.

According to feature H3, based on the state of the most significant bit in the unit information of each predetermined byte unit, it is possible to identify the unit information of predetermined byte units at the beginning and the unit information of predetermined byte units other than the beginning. can.

Feature H4. The predetermined information group includes one or more predetermined unit information (data frames FR1 to FR10) as unit information of the predetermined byte unit other than the head, and the predetermined unit information in the predetermined unit information after receiving the predetermined information group. The gaming machine according to any one of features H1 to H3, characterized in that aggregation unit information (top frames SF1, SF2) in which information set in position bits is aggregated is set.

According to feature H4, in a configuration in which a bit at a predetermined position in unit information in units of predetermined bytes other than the head in a predetermined information group is information other than specific bit information, based on aggregation unit information set in the predetermined information group After receiving the predetermined information group, the information set in the bit at the predetermined position in the predetermined unit information can be grasped. In addition, the number of transmission/reception of the information group can be reduced compared to the configuration in which the information of the bit at the predetermined position in the predetermined unit information is transmitted as another information group.

Feature H5. The gaming machine according to feature H4, wherein the bit information at the predetermined position in the aggregation unit information is information other than the specific bit information.

According to the feature H5, it is possible to distinguish between the head unit information in units of predetermined bytes and the aggregation unit information based on the information of the bit at the predetermined position in the unit information in units of predetermined bytes.

Feature H6. The gaming machine according to feature H5, wherein the aggregation unit information is not set with identification information indicating that it is the aggregation unit information.

According to feature H6, compared to a configuration in which identification information indicating aggregation unit information is set in aggregation unit information, after receiving a predetermined information group in aggregation unit information, a bit at a predetermined position in the predetermined unit information It is possible to prevent a decrease in the number of bits for which information to be set can be set.

Feature H7. The unit information is information in 1-byte units,
The gaming machine according to any one of features H4 to H6, wherein one piece of aggregation unit information is set for seven pieces of predetermined unit information set in the predetermined information group.

According to the feature H7, by setting the information of the bit at the predetermined position in the seven pieces of predetermined unit information as the aggregation unit information, it is possible to grasp the information of the bit at the predetermined position in the seven pieces of predetermined unit information. can. By using one bit in the aggregation unit information in which the information of the bit at the predetermined position in the predetermined unit information is not set, it is possible to distinguish between the leading 1-byte unit information and the aggregation unit information.

Feature H8. When the number of the predetermined unit information included in the predetermined information group is a multiple of "7", the number of the predetermined unit information included in the predetermined information group is divided by "7" When the aggregation unit information of the number of quotients is set in the predetermined information group, and the number of the predetermined unit information contained in the predetermined information group is not a multiple of "7", the predetermined information group characterized in that a number of the aggregation unit information that is "1" larger than the number of quotients obtained by dividing the number of the contained predetermined unit information by "7" is set in the predetermined information group The game machine according to any one of H4 to H7.

According to feature H8, for all the predetermined unit information contained in the predetermined information group, after receiving the predetermined information group, the information set in the bit at the predetermined position in the predetermined unit information is set in the aggregation unit information. can be done.

Feature H9. In the predetermined information group, the aggregation unit information obtained by aggregating the information set in the bits at the predetermined positions in the consecutive six or less pieces of the predetermined unit information including the last predetermined unit information is the last predetermined unit. The gaming machine according to any one of features H4 to H8, wherein the unit information is set as the unit information in units of the predetermined byte after one piece of information.

According to the feature H9, based on the aggregation unit information set one after the last predetermined unit information, set to the bit at the predetermined position in the consecutive 6 or less predetermined unit information including the last predetermined unit information. It is possible to comprehend the information to be provided. By setting the aggregation unit information one after the last predetermined unit information, it is possible to easily grasp the position of the aggregation unit information.

Feature H10. In the predetermined information group, the aggregation in which the bits at the predetermined positions in the seven consecutive predetermined unit information are aggregated in the predetermined byte unit information after one of the seven consecutive predetermined unit information The gaming machine according to any one of features H4 to H9, wherein unit information is set.

According to feature H10, it is possible to grasp the information set to the bit at the predetermined position in the seven consecutive pieces of predetermined unit information set before the aggregation unit information based on the aggregation unit information. . Even when seven or more pieces of predetermined unit information are set in the predetermined information group, information set in bits at predetermined positions in all the predetermined unit information included in the predetermined information group is set as aggregation unit information. can be grasped by

Feature H11. Tail information (footer FT) is set at the end of the predetermined information group,
The gaming machine according to any one of features H4 to H10, wherein the aggregation unit information is set as unit information in units of predetermined bytes immediately preceding the tail information.

According to the feature H11, it is possible to easily grasp the position of aggregation unit information set immediately before the tail information with reference to the tail information. Also, it is possible to make it easier to grasp the tail end of the predetermined information group based on the tail end information.

Feature H12. a predetermined information storage means (display duration counter 142) in which predetermined information (display duration data) is set;
Predetermined processing execution means (processing of step S904 to step S906 in main side CPU 63) for executing a predetermined process (processing for grasping display duration in game round) using the predetermined information set in the predetermined information storage means function) and
and
When setting the predetermined information stored in the predetermined information storage unit as the predetermined unit information in the predetermined information group, the transmission unit stores a bit at the predetermined position in the predetermined unit information as the aggregation unit. Features H4 to H11 characterized in that a bit corresponding to the predetermined unit information is set in the information, and the information of the bit at the predetermined position is the information of the binary information which is not the specific bit information. The gaming machine according to any one of 1.

According to feature H12, the information of the bit at the predetermined position in the predetermined unit information included in the predetermined information group is binary information while preventing the predetermined information stored in the predetermined information storage means from being changed. Among them, the information on the side other than the specific bit information can be used. Therefore, the predetermined information stored in the predetermined information storage means can be used even after the predetermined information group is transmitted.

Feature H13. The predetermined information group includes one or more predetermined unit information (data frames FR1 to FR10) as unit information of the predetermined byte unit other than the head, and the predetermined unit information in the predetermined unit information after receiving the predetermined information group. Aggregation unit information (top frames SF1, SF2) in which information set in position bits is aggregated is set,
Predetermined conversion means (acoustic and optical side CPU 93) for converting the received predetermined information group into a predetermined post-conversion information group (post-conversion command) in which the specific bit information can also be set in the bit at the predetermined position in the predetermined unit information and a function of executing the second command conversion process in the sound and light side CPU 93).

According to feature H13, having the configuration of feature H1, based on the state of a bit at a predetermined position in each predetermined byte unit of unit information in the predetermined information group, unit information in predetermined byte units at the head and predetermined byte units other than the head are obtained. While being identifiable from the unit information, the predetermined information group can be converted into a predetermined post-conversion information group in which specific bit information can be set to bits at predetermined positions in the predetermined unit information.

Feature H14. Aggregation unit information (most significant frames SF1, SF2) obtained by aggregating information to be set in bits at predetermined positions in the predetermined unit information after receiving the predetermined information group is set in the predetermined information group,
The predetermined conversion means converts the predetermined information group into the The gaming machine according to feature H13, wherein the information is converted into an information group after predetermined conversion.

According to feature H14, the received predetermined information group is converted into a predetermined post-conversion information group in which the information set in the bit of the aggregation unit information is set in the bit at the predetermined position in the predetermined unit information corresponding to the bit. be able to.

Feature H15. The predetermined conversion means converts the predetermined unit information corresponding to the bit of the aggregation unit information included in the predetermined information group based on the position of the bit in the aggregation unit information and the data capacity of the predetermined information group. The game machine according to feature H13 or H14, characterized by grasping.

According to feature H15, the predetermined unit information corresponding to the bit is grasped based on the position of the bit in the aggregation unit information included in the predetermined information group and the data capacity of the predetermined information group. It is possible to reduce the data volume of the predetermined information group by eliminating the need to set dedicated information in the predetermined information group for making it possible to grasp the predetermined unit information corresponding to the bit.

For the configuration of features H1 to H15, features A1 to A11, features B1 to B6, features C1 to C6, features D1 to D24, features E1 to E15, features F1 to F7, features G1 to G10, features H1 to Any one or a plurality of configurations of H15 may be applied. As a result, it is possible to obtain a synergistic effect due to the combined configuration.

According to the invention according to the characteristic group H, the following problems can be solved.

Pachinko machines, slot machines, and the like are known as gaming machines. For example, a pachinko machine is equipped with a plate storage section for storing game balls given to a player in the front part of the gaming machine, and the game balls stored in the plate storage section are guided to the game ball launching device, It is shot toward the game area according to the player's shooting operation. Then, for example, when a game ball enters a ball entry portion provided in the game area, the game ball is paid out from the payout device to the plate storage portion, for example. Further, in a pachinko machine, there is also known a configuration in which an upper plate storage portion and a lower plate storage portion are provided as the plate storage portions. , and surplus game balls in the upper plate storage portion are discharged to the lower plate storage portion.

Further, in the slot machine, when the start lever is operated to start a new game while medals are bet, the control means executes the lottery process. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means Rotation of the reel is stopped by execution of rotation stop control. Then, when the stop result after the rotation of the reels is stopped corresponds to a winning combination in the lottery process, a privilege corresponding to the winning combination is given to the player.

Here, in the game machines such as those exemplified above, it is necessary to suitably transmit the information group, and there is still room for improvement in this respect.

The basic configuration of a gaming machine to which each of the above features can be applied or to which each feature is applied is shown below.

Pachinko machine: an operation means operated by a player, a game ball shooting means for shooting game balls based on the operation of the operation means, a ball passage for guiding the shot game balls to a predetermined game area, and a game This game machine is provided with game parts arranged in an area, and gives a privilege to a player when a game ball passes through a predetermined passing part of the game parts.

A game machine such as a slot machine: equipped with a pattern display device for variably displaying a plurality of patterns, the variable display of the plurality of patterns is started by the operation of the start operation means, and the operation of the stop operation means is caused by the operation of the stop operation means. The game machine stops the variable display of the plurality of pictures after a predetermined period of time has passed, and gives a privilege to the player according to the pictures after the stop.

10... Pachinko machine 63... Main side CPU 64... Main side ROM 64q... Special special electric address table 64r... Fluctuation start table 64w... Hard random number maximum value table 64y... First initialization table 64z... Second initialization table 64α... random number maximum value table 93... sound and light side CPU 104... W register 104a... W register 104b... A register 105a... B register 106b... E register 107... HL register, 109... IY register, 111... TP register, 142... Display continuation counter, 149... LDT execution circuit, 151... LD update execution circuit, 152... LDH update execution circuit, 156... First LDY execution circuit, 157... LDB execution circuit, 161 ... LDB update execution circuit 164 ... second LDY execution circuit 191a ... jackpot type maximum value counter 192a ... reach random number maximum value counter 193a ... general electric random number maximum value counter 201 ... special LDB execution circuit FR1 to FR10 ... data Frame FT... Footer HD... Header SA0 to SA6... Start address SB0 to SB23... Start address SF1... First most significant frame SF2... Second most significant frame.

Claims (1)

A transmitting means for transmitting a predetermined information group,
The predetermined information group includes a plurality of unit information in units of predetermined bytes,
In the unit information of the predetermined byte unit at the beginning of the predetermined information group, information of a bit at a predetermined position is specific bit information,
In the unit information of the predetermined byte unit other than the head in the predetermined information group, the information of the bit at the predetermined position is information other than the specific bit information,
In the predetermined information group, one or more predetermined unit information as unit information of the predetermined byte unit other than the head, and set to the bit at the predetermined position in the predetermined unit information after receiving the predetermined information group. A gaming machine characterized in that aggregation unit information in which information is aggregated is set .

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