JP2021192655A - Game machine - Google Patents

Abstract

To provide a game machine capable of making a data configuration of an information group suitable.SOLUTION: A main-side CPU identifies start addresses SA0 to SA6 to be referenced by utilizing a special pattern special electric address table 64q in which plural data of lower 12 bits of the start addresses SA0 to SA6 are set, and executes specific processing by utilizing the identified start addresses SA0 to SA6. In the start addresses SA0 to SA6 identified by utilizing the special pattern special electric address table 64q, information of upper four bits from among 16 bits included in the start address is common. A Pachinko machine has a TP register capable of storing information of the upper four bits. In the special pattern special electric address table 64q, data other than the upper four bits from among 16 bits included in the start addresses SA0 to SA6 are set.SELECTED DRAWING: Figure 31

Description

The present invention relates to a gaming machine.

Pachinko machines and slot machines are known as game machines. For example, the pachinko machine is provided with a dish storage section for storing the game balls given to the player on the front portion of the game machine, and the game balls stored in the dish storage section are guided to the game ball launcher. It is fired toward the game area according to the player's firing operation. Then, for example, when the game ball enters the ball entry section provided in the game area, the game ball is dispensed from the payout device to the dish storage section, for example. Further, in a pachinko machine, a configuration in which an upper plate storage unit and a lower plate storage unit are provided as a plate storage unit is also known. In this case, the game ball stored in the upper plate storage unit is a game ball launching device. The game ball that has become surplus in the upper dish storage section is discharged to the lower dish storage section (see, for example, Patent Document 1).

Further, in the slot machine, when the start lever is operated and a new game is started in the situation where the medal is bet, the lottery process is executed by the control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means operates. The rotation of the reel is stopped by executing the rotation stop control. Then, when the stop result after the reel rotation is stopped corresponds to the winning combination in the lottery process, the privilege corresponding to the winning combination is given to the player.

Japanese Unexamined Patent Publication No. 2018-20012

Here, in a gaming machine such as the above example, it is necessary to make the data structure of the information group suitable, and there is still room for improvement in this respect.

The present invention has been made in view of the above-exemplified circumstances and the like, and an object of the present invention is to provide a gaming machine capable of making the data structure of an information group suitable.

In order to solve the above problem, the invention according to claim 1 comprises an address specifying means for specifying a specific address to be referred to by using a specific address information group in which a plurality of address information is set.
A specific process execution means that executes a specific process using the storage area corresponding to the specific address specified by the address specific means, and a specific process execution means.
In a gaming machine equipped with
The specific address specified by the address specifying means by using the specific address information group has common information of a predetermined range of bits among a plurality of bits included in the specific address.
The gaming machine is provided with specific storage means capable of storing information in the predetermined range of bits.
The address information included in the specific address information group is characterized in that information other than the bits in the predetermined range among the plurality of bits included in the specific address is set.

According to the present invention, it is possible to make the data structure of the information group suitable.

It is a perspective view which shows the pachinko machine in 1st Embodiment. It is a perspective view which shows the main structure of a pachinko machine by disassembling. It is a front view which shows the structure of a game board. (A)-(j) It is explanatory drawing for demonstrating the display content on the display surface of a symbol display device. (A), (b) It is explanatory drawing for demonstrating the display content on the display surface of a symbol display apparatus. It is explanatory drawing for demonstrating the composition concerning the discharge of the game ball which flowed down the game area. It is a front view of the main control device. It is a block diagram which shows the electric structure of a pachinko machine. It is explanatory drawing for demonstrating the structure of the main MPU. (A) It is explanatory drawing for demonstrating setting mode of various areas in main side RAM, and (b) it is explanatory drawing for demonstrating setting mode of data and program in main side ROM. It is explanatory drawing for demonstrating the contents of various counters used for a winning or failing lottery. (A) An explanatory diagram for explaining a setting mode of various counters in a work area for specific control, and (b) an explanatory diagram for explaining a setting mode of various maximum value counters in a work area for specific control. be. It is explanatory drawing for demonstrating various tables stored in the main ROM. (A) It is explanatory drawing for explaining the 1st special drawing distribution table, and (b) is explanatory drawing for explaining 2nd special drawing distribution table. It is a flowchart which shows the main processing in the main CPU. (A) It is explanatory drawing for demonstrating the storage area where "0" clear and initial setting are performed in the power-on setting process, and (b) it is explanatory drawing for demonstrating the data structure of the power failure area. (A) An explanatory diagram for explaining the machine language data structure of the LDT instruction, (b) an explanatory diagram for explaining the machine language data structure of the LD instruction, and (c) the main CPU. It is explanatory drawing for demonstrating the program contents of the power-on setting process to be executed. (A) It is explanatory drawing for demonstrating the data structure of the 1st initialization table, and (b) it is explanatory drawing for demonstrating the data structure of the 2nd initialization table. (A), (b) is an explanatory diagram for explaining the LDH update instruction, and (c) is an explanatory diagram for explaining the program content of the data setting execution process. (A)-(g) It is explanatory drawing for demonstrating the state of the D register, the E register, the W register, the A register and the HL register when the data setting execution process is executed in the power-on setting process. (A) It is a flowchart which shows the clear correspondence processing executed by the main CPU, (b) is an explanatory diagram for explaining the storage area where data setting is performed in the clear time setting processing, and (c) is a security signal. It is explanatory drawing for demonstrating the data structure of an area. (A) It is explanatory drawing for demonstrating the clear time setting table, and (b) is an explanatory diagram for demonstrating the program content of the clear time setting process executed by the main CPU. (A) It is explanatory drawing for demonstrating the random number maximum value table, and (b) is the flowchart which shows the random number maximum value setting process executed by the main CPU. (A) It is explanatory drawing for demonstrating the data structure of the machine language of the 1st LDY instruction, and (b) it is explanatory drawing for demonstrating the program content of the maximum value setting start processing executed by the main CPU. .. It is a flowchart which shows the setting value update process executed by the main CPU. It is a flowchart which shows the timer interrupt processing executed by the main CPU. (A) It is a flowchart which shows the 1st random number update process executed by the main CPU, and (b) is explanatory drawing for explaining the program content of the update start setting process executed by the main CPU. It is a flowchart which shows the 2nd random number update process executed by the main CPU. It is a flowchart which shows (a) the fraud detection process executed by the main CPU, and (b) is explanatory drawing for explaining the program content of the fraud detection initialization process executed by the main CPU. It is a flowchart which shows the special figure special electric control process which is executed by the main CPU. It is explanatory drawing for demonstrating the data structure of the special figure special electric address table. (A) to (d) are explanatory diagrams for explaining the process of calculating the acquisition start address and the acquisition start bit from the acquisition data designation data, and (e), (f) the HL register from the special figure special electric address table. It is explanatory drawing for demonstrating how the start address is acquired in. (A) An explanatory diagram for explaining the program contents of the special figure special electric address acquisition process executed by the main CPU, and explanations for explaining the process of calculating (b) to (d) "TBL_TZTD_B". It is a figure, and is explanatory drawing for demonstrating (e) the program content of the address acquisition execution process executed by the main CPU. It is explanatory drawing for demonstrating the correspondence relationship between the value of the special figure special electric counter, and the start address acquired in the HL register. It is a flowchart which shows the special figure variation start processing executed by the main CPU. (A) It is an explanatory diagram for explaining the structure of a hit / fail data area, (b) it is an explanatory diagram for explaining the contents of a high probability hit / miss table, and (c) it explains the data structure of a high probability hit / miss table. It is explanatory drawing for. (A) It is a flowchart which shows the high-probability hit / fail determination process executed by the main CPU, and (b) is the explanatory diagram for explaining the program content of the hit / fail determination data acquisition process which is executed by a main CPU. There is (c) an explanatory diagram for explaining how the determination value data is set in the WA register, and (d) an explanatory diagram for explaining how the flag data is set in the B register. (A) to (e) Start address of high accuracy / rejection table, acquisition data designation data in LDB instruction (“LDB WA, (HL +). 5”), acquisition start address, acquisition start bit, and acquisition data after update. It is explanatory drawing for demonstrating designated data. (A)-(c) Explanation for explaining the acquisition data designation data, the acquisition start address, the acquisition start bit, and the updated acquisition data designation data in the LDB instruction ("LDB B, (HL +). 1"). It is a figure. The number of executions of the LDB update instruction "LDB WA, (HL +) .5" and the LDB update instruction "LDB B, (HL +) .1", and the data acquired in the WA register and the B register by the LDB update instruction. It is explanatory drawing for demonstrating. (A) It is an explanatory diagram for explaining the structure of a distribution data area, (b) it is an explanatory diagram for explaining the data structure of the 1st special figure distribution table, and (c) the 2nd special figure. It is explanatory drawing for demonstrating the data structure of the distribution table. It is a flowchart which shows the 1st result correspondence processing executed by the main CPU. (A) It is explanatory drawing for demonstrating the program content of the distribution data acquisition process executed by the main CPU, and (b) the state that the 1st addition pre-distribution value is set in the W register is explained. It is explanatory drawing for demonstrating (c) how the 1st flag data is set in the B register. (A)-(e) Start address of distribution table for first special figure, acquisition data designation data in LDB instruction ("LDB W, (HL +) .4"), acquisition start address, acquisition start bit, and update. It is explanatory drawing for demonstrating later acquisition data designation data. (A)-(c) Explanation for explaining the acquisition data designation data, the acquisition start address, the acquisition start bit, and the updated acquisition data designation data in the LDB instruction ("LDB B, (HL +) .2"). It is a figure. The number of executions of the LDB update instruction "LDB W, (HL +) .4" and the LDB update instruction "LDB B, (HL +) .2", and the data acquired in the W register and the B register by these LDB update instructions. It is explanatory drawing for demonstrating. It is explanatory drawing for demonstrating the correspondence relationship with the variation type number, the result of a hit / fail determination, the result of a distribution determination, the result of a reach generation lottery, and the number of reservations in the first special figure reservation area. It is a flowchart which shows the 2nd result correspondence processing executed by the main CPU. It is explanatory drawing for demonstrating the data structure of the fluctuation start table. (A) It is an explanatory diagram for explaining the acquisition mode of the start address of the variation pattern table, and (b) it is the explanatory diagram for explaining the program content of the variation start address acquisition process executed by the main CPU. be. (A) It is explanatory drawing for demonstrating the data structure of the variation pattern table corresponding to the variation type number of "0", and (b) it stores the stop result data and display duration data in the work area for specific control. It is explanatory drawing for demonstrating the structure of the area for this. It is a flowchart which shows the fluctuation information setting process executed by the main CPU. It is explanatory drawing for demonstrating (a) the data structure of the hold display data table, (b) is an explanatory diagram for explaining the acquisition mode of hold display data, and (c) is the hold display data table of the comparative example. It is explanatory drawing for demonstrating a data structure. It is a flowchart which shows the display control process which is executed by the main CPU. (A) It is explanatory drawing for demonstrating the program content of 1st special figure hold display data acquisition process executed by a main CPU, and (b) hold display data acquisition execution process executed by a main CPU. It is an explanatory diagram for explaining the program content of (c), (c) is an explanatory diagram for explaining the program content of the 2nd special figure hold display data acquisition process executed by the main CPU, and (d) the main. It is explanatory drawing for demonstrating the program content of the general drawing hold display data acquisition process executed by the side CPU. (A) It is a flowchart which shows the management process executed by the main CPU, and (b) is explanatory drawing for explaining the setting mode of various buffers in the work area for non-specific control. It is a flowchart which shows the management execution process which is executed by the main CPU. It is explanatory drawing for demonstrating the structure of the work area for non-specific control. It is a flowchart which shows the check process executed by the main CPU. It is a flowchart which shows the normal ball entry management process which is executed by the main CPU. It is explanatory drawing for demonstrating the electric structure of the main control board and the voice light emission control board for transmitting a command from a main side CPU to a sound light side CPU. (A) An explanatory diagram for explaining the data structure of the header, (b) an explanatory diagram for explaining the data structure of the footer, and (c) for explaining the data structure of the variable command for communication. It is an explanatory diagram for explaining (d) the data structure of the command for variation after conversion. It is explanatory drawing for demonstrating the generation mode of the variation command for communication. It is explanatory drawing for demonstrating the data structure of the normal return command for communication. It is explanatory drawing for demonstrating the data structure of the normal return command after conversion. It is explanatory drawing for demonstrating the generation mode of the normal return command for communication. (A) It is explanatory drawing for demonstrating the conversion mode of the variable command for communication, and (b) it is explanatory drawing for demonstrating the conversion mode of the normal return command for communication. It is a flowchart which shows (a) the variable command transmission processing executed by the main CPU, and (b) is explanatory drawing for explaining the data structure of the variable command generation table. It is a flowchart which shows the command setting process for variation which is executed by the main CPU. It is a flowchart which shows the return command transmission processing executed by the main CPU. It is explanatory drawing for demonstrating the data structure of the normal return command generation table. It is a flowchart which shows the normal return command setting process executed by the main CPU. It is a flowchart which shows the command reception correspondence processing which is executed in the sound light side CPU. It is a flowchart which shows the 1st command conversion process executed by the sound light side CPU. It is a flowchart which shows the 2nd command conversion process executed by the sound light side CPU. It is explanatory drawing for demonstrating the structure of the main control board in 2nd Embodiment. (A) It is explanatory drawing for demonstrating the maximum value of an update circuit, and (b) is an explanatory diagram for demonstrating the data structure of a hard random number maximum value table. (A) is a flowchart showing the random number maximum value setting process executed by the main CPU, and (b) is an explanatory diagram for explaining the program contents of the update circuit setting process executed by the main CPU. (B) It is explanatory drawing for demonstrating the program content of the maximum value setting execution process executed by the main CPU. It is a flowchart which shows the display control process which is executed by the main CPU in 3rd Embodiment. (A) An explanatory diagram for explaining the data configuration of the hold display data table, (b) an explanatory diagram for explaining an acquisition mode of the hold display data, and (c) being executed by the main CPU. It is a flowchart which shows the process for holding display acquisition, and is explanatory drawing for explaining the program content of (d) hold display acquisition execution processing executed by the main CPU. (A) An explanatory diagram for explaining the data structure of the first initialization table in the fourth embodiment, (b) an explanatory diagram for explaining the data structure of the second initialization table, and (c). ) It is explanatory drawing for demonstrating the data structure of the random number maximum value table. It is explanatory drawing for demonstrating the program content of the power-on setting process executed by the main CPU, and is the explanatory diagram for explaining the program content of the data setting execution process executed by the main CPU. It is a flowchart which shows the random number maximum value setting process executed by the main CPU. (A) is an explanatory diagram for explaining the data structure of the second initialization table in the fifth embodiment, and (b) is a flowchart showing a random number maximum value setting process executed by the main CPU. (A) It is explanatory drawing for demonstrating the structure of the main MPU in 6th Embodiment, and (b)-(e) the process of calculating the acquisition start address and the acquisition start bit from the acquisition data designation data. It is explanatory drawing for demonstrating. (A), (b) is an explanatory diagram for explaining how the start address is acquired from the special figure special electric address table to the HL register, and (c) the special figure special electric address acquisition process executed by the main CPU. It is an explanatory diagram of the program contents of (d) to (f), and is an explanatory diagram for explaining the process of calculating "TBL_TZTD2_B". It is explanatory drawing for demonstrating the correspondence relationship between the value of the special figure special electric counter, and the start address acquired in the HL register. It is a flowchart which shows the address acquisition execution process which is executed by the main CPU.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as “pachinko machine”), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is a perspective view showing the main configurations of the pachinko machine 10 in an exploded manner. Note that, in FIG. 2, for convenience, the configuration in the gaming area of the pachinko machine 10 is omitted.

As shown in FIG. 1, the pachinko machine 10 has an outer frame 11 forming an outer shell of the pachinko machine 10 and a gaming machine main body 12 rotatably attached to the outer frame 11 in the forward direction. .. The outer frame 11 is formed by connecting wooden plates on all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by attaching and fixing the outer frame 11 to the island equipment. The outer frame 11 is not an indispensable configuration for the pachinko machine 10, and the outer frame 11 may be provided in the island equipment of the game hall.

As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 arranged in front of the inner frame 13, and a back pack unit 15 arranged behind the inner frame 13. ing. The inner frame 13 of the gaming machine main body 12 is rotatably supported with respect to the outer frame 11. Specifically, the inner frame 13 can rotate forward with the left side as the rotation base end side and the right side as the rotation tip side in front view.

The front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side as the rotation base end side and the right side as the rotation tip side in front view. Further, the back pack unit 15 is rotatably supported on the inner frame 13, and can be rotated backward with the left side as the rotation base end side and the right side as the rotation tip side in front view.

The gaming machine main body 12 is provided with a locking device at the rotating tip portion thereof, and has a function of locking the gaming machine main body 12 to the outer frame 11 so as not to be openable. It has a function of locking the door frame 14 to the inner frame 13 so that it cannot be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 exposed on the front surface of the pachinko machine 10.

Next, the configuration of the front side of the gaming machine main body 12 will be described.

The inner frame 13 is mainly composed of a resin base 21 having an outer shape substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

Here, the configuration of the game board 24 will be described with reference to FIG. FIG. 3 is a front view of the game board 24.

An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA, and the guiding means is provided by the inner rail portion 25 and the outer rail portion 26. As a guide rail is configured. The game ball launched from the game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 is guided to the upper part of the game area PA by the guide rail.

By the way, the game ball launch mechanism 27 has a launch rail 27a extending toward the guide rail, a ball feeding device 27b for supplying the game ball stored in the precision plate 55a described later on the launch rail 27a, and the launch rail 27a. It is equipped with a solenoid 27c, which is an electric actuator that launches the game ball supplied to the guide rail toward the guide rail. The solenoid 27c is driven and controlled by the rotation operation of the launch operation device (or operation handle) 28 provided on the front door frame 14, and the game ball is launched.

The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. Each opening has a general winning opening 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special figure unit 37, a normal drawing unit 38, and a round display unit 39. Etc. are provided respectively.

Even if a ball enters the through gate 35, the game ball is not paid out. On the other hand, with respect to the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, when a ball is entered, a predetermined number of game balls are paid out. Specifically, when the number of prize balls is entered into the first operating port 33, three prize balls are paid out and the balls are entered into the second operating port 34. 1 prize ball is paid out, and when a ball is entered into the general winning opening 31, 10 prize balls are paid out and the special electric winning device 32 is entered. If so, 15 prize balls will be paid out.

The number of prize balls is arbitrary. For example, the number of prize balls in the second operating port 34 is smaller than that in the first operating port 33, but the specific number of prize balls is different from the above. Often, the number of prize balls may be the same in the first operating port 33 and the second operating port 34, and the number of prize balls in the second operating port 34 may be larger than that in the first operating port 33.

In addition, an out opening 24a is provided at the lowermost portion of the game board 24, and a game ball that has not entered various winning openings or the like is discharged from the game area PA through the out opening 24a. Further, a large number of nails 24b are planted on the game board 24 in order to appropriately disperse and adjust the falling direction of the game ball, and various members such as a windmill are arranged.

Here, the entry ball means that the game ball passes through a predetermined opening, and not only is the ball discharged from the game area PA after passing through the opening, but also from the game area PA after passing through the opening. A mode in which the flow of the game area PA is continued without being discharged is also included. However, in the following description, in order to clearly distinguish the ball from entering the game ball into the out opening 24a, the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 The entry of a game ball into a game is also referred to as a prize.

The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first actuating port 33 and the second actuating port 34 are open upward. Further, both the operating ports 33 and 34 are arranged in the vertical direction so that the first operating port 33 faces upward. The second actuating port 34 is provided with a universal electric accessory 34a as a guide piece made of a pair of left and right movable pieces. In the closed state of the general electric accessory 34a, the game ball cannot win the prize in the second operating port 34, and when the general electric accessory 34a is in the open state, the prize can be won in the second operating port 34.

A through gate 35 is provided on the upstream side of the second operating port 34 in the flow direction of the game ball. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball winning the through gate 35 flows down the game area PA after winning. As a result, the game ball that has won the through gate 35 can win the second operating port 34.

Based on the winning of the through gate 35, the universal electric accessory 34a of the second operating port 34 is switched from the closed state to the open state. Specifically, an internal lottery is performed triggered by winning a prize in the through gate 35, and a normal drawing unit 38 is displayed in the lower right corner of the game area PA where the game ball does not pass. The variable display of the pattern is performed in the part 38a. Then, when the result of the internal lottery is the winning of the electric service opening, the stop result corresponding to the result is displayed, and the variable display of the general map display unit 38a is completed, the state shifts to the general electric opening state. In the open state of the normal electric power, the public electric accessory 34a is in the open state in a predetermined manner.

The cathode ray display unit 38a is composed of a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but the present invention is not limited to this, and the liquid crystal display device and the organic EL display device are not limited thereto. , CRT or other types of display devices such as dot matrix displays. Further, as the pattern to be variablely displayed on the general map display unit 38a, a configuration in which a plurality of types of characters are variablely displayed, a configuration in which a plurality of types of symbols are variablely displayed, a configuration in which a plurality of types of characters are variablely displayed, or a configuration in which a plurality of types of characters are variablely displayed. A configuration in which multiple types of colors are switched and displayed can be considered.

In the normal drawing unit 38, a normal drawing holding display unit 38b is provided at a position adjacent to the normal drawing display unit 38a. The number of game balls that have won a prize in the through gate 35 is reserved up to a maximum of four, and the reserved number is displayed by lighting the normal figure reservation display unit 38b.

A winning lottery is performed with a prize in the first operating port 33 or the second operating port 34 as a trigger. Then, the lottery result is clearly shown through the display effect in the symbol display device 41 of the special figure unit 37 and the variable display unit 36.

More specifically, the special figure unit 37 is provided with a first special figure display unit 37a and a second special figure display unit 37b. The display area of the first special symbol display unit 37a is narrower than the display surface 41a of the symbol display device 41, and similarly, the display area of the second special symbol display unit 37b is narrower than the display surface 41a of the symbol display device 41. Further, the area of the display area including the first special figure display unit 37a and the second special figure display unit 37b is also smaller than the display surface 41a.

In the first special figure display unit 37a, a winning lottery is performed with a winning prize in the first operating port 33 as a trigger, so that a variable display or a predetermined display of the pattern is performed. Then, the result corresponding to the lottery result is displayed. Further, in the second special figure display unit 37b, a winning lottery is performed by using a winning prize in the second operating port 34 as a trigger, so that a variable display or a predetermined display of the pattern is performed. Then, the result corresponding to the lottery result is displayed.

The first special figure display unit 37a and the second special figure display unit 37b are configured by a segment display unit in which a plurality of segment light emitting units are arranged in a predetermined manner, but the present invention is not limited thereto. Instead, it may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device. The patterns displayed on the first special figure display unit 37a and the second special figure display unit 37b include a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, and a plurality of types of characters. Is displayed, or a configuration in which a plurality of types of colors are displayed is conceivable.

In the special figure unit 37, a first special figure holding display unit 37c and a second special drawing holding display unit 37d are provided at positions adjacent to the first special figure display unit 37a and the second special figure display unit 37b. .. The number of game balls that have won a prize in the first operating port 33 is reserved up to four, and the reserved number is displayed by lighting the first special figure reservation display unit 37c. Further, the number of game balls winning in the second operating port 34 is reserved up to four, and the reserved number is displayed by lighting the second special figure reservation display unit 37d.

Regarding the symbol display device 41 In detail, the symbol display device 41 is configured as a liquid crystal display device provided with a liquid crystal display, and the display content is controlled by a display control device described later. The symbol display device 41 is not limited to the liquid crystal display device, and may be another display device having a display surface such as a plasma display device, an organic EL display device, or a CRT, and is a dot matrix display device. You may.

In the symbol display device 41, when a variable display or a predetermined display of a pattern is performed on the first special symbol display unit 37a based on a prize in the first operating port 33, the variable display or the predetermined display of the symbol is displayed accordingly. At the same time, when the second special figure display unit 37b performs the variable display or the predetermined display of the pattern based on the winning of the second operating port 34, the variable display or the predetermined display of the symbol is performed accordingly. .. In the symbol display device 41, not only the display effect triggered by winning a prize in the first actuating port 33 or the second actuating port 34, but also the display effect in the opening / closing execution mode described later, which shifts after winning a prize, etc. Is done.

The display contents when the symbol display device 41 performs variable display of the symbol will be described in detail with reference to FIGS. 4 and 5. 4 (a) to 4 (j) are diagrams showing individual symbols that are variablely displayed on the symbol display device 41, and FIGS. 5 (a) and 5 (b) are display contents on the display surface 41a of the symbol display device 41. It is explanatory drawing for demonstrating.

As shown in FIGS. 4 (a) to 4 (j), a pattern which is a kind of pattern consists of nine main patterns with numbers "1" to "9" and a shell-shaped pattern. It is composed of sub-designs. More specifically, nine types of character symbols such as an octopus are assigned numbers "1" to "9" to form a main symbol.

As shown in FIG. 5A, on the display surface 41a of the symbol display device 41, three symbol rows Z1, Z2, and Z3 of an upper row, a middle row, and a lower row are set as a plurality of display areas. Each symbol row Z1 to Z3 is configured by arranging a main symbol and a sub symbol in a predetermined order. In detail, in the upper symbol row Z1, nine types of main symbols "1" to "9" are arranged in descending order of numbers, and one sub symbol is arranged between each main symbol. .. In the lower symbol row Z3, nine types of main symbols "1" to "9" are arranged in ascending order of numbers, and one sub symbol is arranged between each main symbol.

That is, the upper symbol row Z1 and the lower symbol row Z3 are composed of 18 symbols. On the other hand, in the middle symbol string Z2, nine types of main symbols "1" to "9" are arranged in ascending order of numbers, and then between the main symbol of "9" and the main symbol of "1". The main symbol of "4" is additionally arranged in the above, and one sub symbol is arranged between each of these main symbols. That is, only in the middle symbol row Z2, 10 main symbols are arranged and composed of 20 symbols. Then, on the display surface 41a, the symbols of each of the symbol rows Z1 to Z3 are variably displayed so as to scroll in a predetermined direction with periodicity.

As shown in FIG. 5B, on the display surface 41a, three symbols are stopped and displayed for each symbol row, and as a result, a total of nine symbols of 3 × 3 are stopped and displayed. It has become like. Further, as shown in FIG. 5A, five effective lines, that is, a left line L1, a middle line L2, a right line L3, a right-down line L4, and a right-up line L5 are set on the display surface 41a. ..

When the symbol is variablely displayed on the display surface 41a based on the winning of the first actuating port 33 or the second actuating port 34, the symbols of the symbol rows Z1 to Z3 scroll in a predetermined direction with periodicity. The variable display is started. Then, the variable display is switched to the standby display in the order of the upper symbol row Z1 → the lower symbol row Z3 → the middle symbol row Z2, and finally the predetermined symbols are statically displayed in the respective symbol rows Z1 to Z3. .. Further, when the variation display of the symbols ends, if the result of the internal lottery is the 4R high-accuracy jackpot result described later, the same even-numbered symbol combination is formed on any of the effective lines, and the 8R high-accuracy jackpot result is obtained. In some cases, the same odd-numbered symbol combinations other than the "7" symbol are formed, and in the case of a 16R high-accuracy jackpot result, a "7" symbol combination is formed. Further, when the result of the internal lottery is a small hit result described later, a predetermined combination of symbols (for example, "3.4.1") is formed on any of the effective lines.

It should be noted that, based on the winning of any of the operating ports 33 and 34, the display is started on any of the special figure display units 37a and 37b and the symbol display device 41, and until the predetermined result is displayed and ended. Is equivalent to one game. Further, the mode of variable display of symbols in the symbol display device 41 is not limited to the above, and is arbitrary, such as the number of symbol rows, the direction of variable display of symbols in the symbol row, the number of symbols in each symbol row, and the like. Can be changed as appropriate. Further, the pattern to be variablely displayed by the symbol display device 41 is not limited to the above-mentioned symbol, and may be configured such that only numbers are variablely displayed as the symbol, for example.

If a big hit or a small win is won in the winning lottery based on the winning in the first operating port 33, the mode shifts to the opening / closing execution mode in which the special electric winning device 32 can be won. Similarly, even if a big hit or a small win is won in the winning lottery based on the winning in the second operating port 34, the mode shifts to the opening / closing execution mode in which the special electric winning device 32 can be won.

Returning to the description of FIG. 3, the special electric winning device 32 is provided with a large winning opening (not shown) leading to the back side of the game board 24, and is provided with an opening / closing door 32a for opening and closing the large winning opening. The opening / closing door 32a is arranged in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state in which the game ball cannot win a prize, and is switched to an open state in which the game ball can win a prize when the transition to the open / close execution mode is won in the internal lottery. It has become. By the way, the open / close execution mode is a mode in which the transition is made when a hit result is obtained. It should be noted that although it is not impossible to win a prize in the closed state, it may be configured in a state in which it is more difficult for the prize to occur than in the open state.

The round display unit 39 displays the number of round games that occur in the open / close execution mode. Here, the opening / closing execution mode includes a round number specifying mode that occurs when a big hit is won and an opening / closing number specifying mode that occurs when a small hit is won. The round number regulation mode is an open / close execution mode executed up to a predetermined number of round games. A round game is a game that continues until either the predetermined upper limit duration elapses or the predetermined upper limit number of game balls wins the special electric winning device 32. That is. The number of round games executed in the round number specified mode differs depending on the type of jackpot result that triggered the transition. The round display unit 39 displays the number of round games or displays corresponding to the number of round games. Further, the display on the round display unit 39 is started when the open / close execution mode is started, and is ended when the open / close execution mode is ended and a new game round is started. On the other hand, in the open / close number regulation mode, the round game is not set, the number of times of opening / closing of the special electric winning device 32 is the upper limit, and the predetermined upper limit number of game balls wins the special electric winning device 32. It is terminated based on the condition of either one of the above. In the open / close number regulation mode, the round display unit 39 is maintained in the non-display state.

FIG. 6 is an explanatory diagram for explaining a configuration relating to discharge of a game ball flowing down the game area PA.

As described above, the game ball that has entered any of the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the out port 24a is discharged from the gaming area PA. In other words, the game ball launched from the game ball launching mechanism 27 and flowing into the game area PA is any one of the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the out port 24a. By entering the ball, it will be discharged from the game area PA. The game ball that has entered any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the out opening 24a is guided to the back side of the game board 24.

On the back surface of the game board 24, discharge passage portions 42 to 48 are formed corresponding to each of the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the out port 24a. .. The game balls that have flowed into the discharge passages 42 to 48 are guided to the lower end of the game board 24 on the back side of the game board 24 by flowing down the flowed discharge passages 42 to 48, and become a discharge ball recovery part (not shown). Will be collected. Then, the game balls collected by the discharge ball collection unit are discharged to the ball circulation device of the island facility in which the pachinko machine 10 is installed in the game hall.

Various detection sensors 42a to 48a for detecting the game ball are provided in the discharge passage portions 42 to 48. The discharge passage portions 42 to 48 and the detection sensors 42a to 48a will be described below. Since four general winning openings 31 are provided as described above, discharge passage portions 42 to 44 exist corresponding to each of the four general winning openings 31. In this case, one detection sensor 42a, one for each of the first discharge passage portion 42 corresponding to the leftmost general winning opening 31 and the second discharge passage portion 43 corresponding to the general winning opening 31 on the right side thereof. 43a is provided. Specifically, the first winning opening detection sensor 42a is provided so that the detection range exists in the middle position of the first discharge passage portion 42, and the detection range is provided in the middle position of the second discharge passage portion 43. The second winning opening detection sensor 43a is provided so as to exist. The game ball that has entered the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage portion 42, and the game that has entered the general winning opening 31 to the right of the first winning opening detection sensor 42a. The ball is detected by the second winning opening detection sensor 43a on the way through the second discharge passage portion 43. Further, a third discharge passage portion 44 formed so as to join the two general winning openings 31 on the right side at an intermediate position is provided. The third discharge passage portion 44 has an inlet side region corresponding to each of the two general winning openings 31, and has one outlet side region when the inlet side regions merge in the middle. is doing. The third winning opening detection sensor 44a is provided so that the detection range exists in the middle position of the exit side region in the third discharge passage portion 44. The game ball that has entered one of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage portion 44.

The fourth discharge passage portion 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists in the middle of the fourth discharge passage portion 45, and the game ball that has entered the special electric winning device 32 is on the way through the fourth discharge passage portion 45. It is detected by the special electric detection sensor 45a. A fifth discharge passage portion 46 exists corresponding to the first actuating port 33. The first actuating port detection sensor 46a is provided so that the detection range exists in the middle of the fifth discharge passage portion 46, and the game ball that has entered the first actuating port 33 passes through the fifth discharge passage portion 46. It is detected by the first actuating port detection sensor 46a on the way through. A sixth discharge passage portion 47 exists corresponding to the second actuating port 34. The second operating port detection sensor 47a is provided so that the detection range exists in the middle of the sixth discharging passage portion 47, and the game ball that has entered the second operating port 34 uses the sixth discharging passage portion 47. It is detected by the second actuating port detection sensor 47a on the way through. The seventh discharge passage portion 48 exists corresponding to the out port 24a. The out port detection sensor 48a is provided so that the detection range exists in the middle position of the seventh discharge passage portion 48, and the game ball that has entered the out port 24a is on the way through the seventh discharge passage portion 48. It is detected by the out port detection sensor 48a.

The game ball that is the target of detection by any one of the various detection sensors 42a to 48a is not the target of detection by the other detection sensors 42a to 48a. Further, the gate detection sensor 49a is also provided for the through gate 35, and the game ball passing through the through gate 35 while flowing down the game area PA is detected by the gate detection sensor 49a.

As the various detection sensors 42a to 49a, electromagnetic induction type proximity sensors are used, but any sensor can be used as long as the game balls can be individually detected. Further, the various detection sensors 42a to 49a are electrically connected to the main control device 60 described later, and the detection results of the various detection sensors 42a to 49a are output to the main control device 60. Specifically, the various detection sensors 42a to 49a output the HI state signal when the game ball is not detected, and output the LOW state signal when the game ball is detected. The various detection sensors 42a to 49a may be configured to output a LOW state signal when the game ball is not detected, and output a HI state signal when the game ball is detected.

As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front surface side of the inner frame 13 in which the game board 24 having the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 so that almost the entire area of the game area PA can be visually recognized from the front. The window portion 51 has a substantially elliptical shape, and the window panel 52 is fitted therein. The window panel 52 is colorless and transparently formed by glass, but is not limited to this, and may be colorless and transparent by synthetic resin, and the gaming area PA is formed from the front of the pachinko machine 10 through the window panel 52. It may be colored and transparent as long as it is visible.

A display light emitting unit 53 is provided above the window unit 51. Further, a pair of left and right speaker units 54 for outputting sound effects and the like according to the game state are provided. Further, below the window portion 51, an upper bulging portion 55 bulging toward the front side and a lower bulging portion 56 are vertically arranged side by side. An upper plate 55a opened upward is provided inside the upper bulging portion 55, and a lower plate 56a also opened upward is provided inside the lower bulging portion 56. The upper plate 55a has a function of temporarily storing the game balls paid out from the payout device described later and guiding them to the game ball launching mechanism 27 side while arranging them in a row. Further, the lower plate 56a has a function of storing excess game balls in the upper plate 55a.

Next, the configuration of the back side of the gaming machine main body 12 will be described.

As shown in FIG. 2, a main control device 60 that controls the main control of the game is mounted on the back surface of the inner frame 13 (specifically, the game board 24). FIG. 7 is a front view of the main control device 60. As shown in FIG. 7, in the main control device 60, the main control board 61 is housed in the board box 60a.

The main MPU 62 is mounted on the element mounting surface, which is one plate surface of the main control board 61. The substrate box 60a is transparently formed so that the main MPU 62 housed in the substrate box 60a can be visually recognized from the outside of the substrate box 60a. Although the substrate box 60a is formed to be colorless and transparent, it may be formed to be colored and transparent if the main MPU 62 housed in the substrate box 60a can be visually recognized from the outside of the substrate box 60a. good. The main control device 60 is mounted on the back surface of the resin base 21 so that the facing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10 in the board box 60a. Therefore, by opening the gaming machine main body 12 to the front of the pachinko machine 10 with respect to the outer frame 11 to expose the back surface of the resin base 21, it becomes possible to visually check the facing wall portion 60b of the substrate box 60a. The main MPU 62 can be visually observed through the facing wall portion 60b.

The substrate box 60a is formed by combining a plurality of case bodies 60c back and forth, and the plurality of case bodies 60c prevent the case bodies 60c from being separated and trace the case bodies 60c when they are separated. A joint portion 60e is provided for leaving the surface. A plurality of connecting portions 60e are arranged side by side on one side of the substrate box 60a having a substantially rectangular parallelepiped shape. As a result, even if the part of the connecting portion 60e is destroyed and the case body 60c is separated in a state where the separation of the case body 60c is prevented by using a part of the connecting portion 60e, another coupling is subsequently performed. By putting the portion 60e in the coupled state, it is possible to prevent the case body 60c from being separated again. Further, when the case body 60c is separated, the joint portion 60e is destroyed and its trace remains, so that it is possible to grasp whether or not the case body 60c is illegally separated by visually checking the joint portion 60e. It will be possible. Further, in the substrate box 60a, a sealing seal 60f is attached so as to straddle the boundary between the case bodies 60c on the side opposite to the side on which the connecting portions 60e are arranged side by side. When the seal seal 60f is peeled off, an adhesive layer remains on the case body 60c. As a result, when the sealing seal 60f is peeled off when the case body 60c is separated, it is possible to leave a trace thereof.

In the main control device 60 having the above configuration, the main control board 61 is owned by the manager of the game hall in order to give an opportunity to change the setting state of the pachinko machine 10 in the range of "setting 1" to "setting 6". The setting key insertion unit 68a in which the setting key is inserted and turned on, the update button 68b operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion unit 68a is turned on, and the main control device. The reset button 68c operated to clear the data of the main RAM 65 provided on the main MPU 62 of the 60, and the first to third notification display devices 69a to notify the management result of the game history. 69c and are provided. The setting state of the pachinko machine 10 is not limited to the six stages of "setting 1" to "setting 6", and is arbitrary as long as it is a plurality of stages.

The setting key insertion unit 68a, the update button 68b, the reset button 68c, and the first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. Further, the element mounting surface of the main control board 61 faces the facing wall portion 60b of the board box 60a as described above, but the setting key insertion portion 68a, the update button 68b, and the reset button 68c are covered by the facing wall portion 60b. Not broken. That is, the facing wall portion 60b has a region facing each of the setting key insertion portion 68a, the update button 68b, and the reset button 68c as individual openings. As a result, the setting key can be inserted into the setting key insertion unit 68a without the need to open the board box 60a, the update button 68b can be pressed, and the reset button 68c can be pressed. It is possible.

By inserting the setting key into the setting key insertion unit 68a and rotating the setting key in a predetermined direction, the setting key insertion unit 68a is turned on. By starting the supply of the operating power to the pachinko machine 10 in that state (that is, by starting the supply of the operating power to the main MPU 62 of the main control device 60), the setting state of the pachinko machine 10 is changed. Will be in a changeable state. Then, each time the update button 68b is pressed once in this state, the setting state of the pachinko machine 10 is changed step by step in ascending order in the range of "setting 1" to "setting 6". If the update button 68b is operated in the state of "setting 6", it is updated to "setting 1". Further, the setting key insertion unit 68a is turned off by rotating the setting key inserted in the setting key insertion unit 68a in the direction opposite to the predetermined direction from the ON operation position to return to the initial position. Become. When the setting key insertion unit 68a is turned off, the changeable state ends, and the game can be played in the state of the set value at that time. That is, the set value cannot be changed even if the update button 68b is operated after the changeable state ends.

The ON operation for the setting key insertion unit 68a is valid only when the supply of the operating power to the pachinko machine 10 starts (that is, when the supply of the operating power to the main MPU 62 of the main control device 60 starts). Therefore, even if the ON operation for the setting key insertion unit 68a is performed after the processing at the start of supply of the operating power is completed in the main MPU 62 of the main control device 60, the set value cannot be changed.

The setting state of the pachinko machine 10 determines the advantage per unit time in the pachinko machine 10, and the larger the a of "setting a" (a is an integer of "1" to "6"), the larger the value (that is, the setting). (The higher the value), the higher the advantage. Although the details will be described later, there are a low probability mode in which the winning probability is relatively low and a high probability mode in which the winning probability is relatively high as a winning / losing lottery mode for determining the winning probability of the jackpot result. The higher the probability, the higher the winning probability of the jackpot result in the low probability mode. On the other hand, the winning probability of the jackpot result in the high probability mode is constant regardless of the set value.

The reset button 68c is operated to clear the data of the main RAM 65 as described above, but in order to generate the clearing of the data, the operating power is supplied to the pachinko machine 10 while the reset button 68c is pressed. (That is, it is necessary to start supplying the operating power to the main MPU 62 of the main controller 60). The ON operation for the reset button 68c is valid only when the supply of the operating power to the pachinko machine 10 starts (that is, when the supply of the operating power to the main MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of supply of the operating power is completed in the main MPU 62 of the main control device 60, the data in the main RAM 65 cannot be cleared.

The first to third notification display devices 69a to 69c are all segment display devices in which seven display segments by LEDs are arranged, but the present invention is not limited to this, and a single multicolor light emitting type is used. It may be a light emitter, a liquid crystal display device, or an organic EL display. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and the facing wall portion 60b of the board box 60a causes the display devices to face each other. It is covered. In this case, since the substrate box 60a is transparently formed, the display surfaces of the first to third notification display devices 69a to 69c housed in the substrate box 60a are visually observed from the outside of the substrate box 60a. It becomes possible. Further, as described above, the main control device 60 is mounted on the back surface of the resin base 21 in the board box 60a so that the facing wall portion 60b facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened to the front of the pachinko machine 10 with respect to the outer frame 11 and the back surface of the resin base 21 is exposed to the front of the pachinko machine 10, the first to third notifications are sent through the facing wall portion 60b. It is possible to visually check the display surface of the display devices 69a to 69c.

On the display surface of the first to third notification display devices 69a to 69c, not only the numbers "0" to "9" but also various characters including alphabetic characters are displayed. The management result of the game history is notified by using the first to third notification display devices 69a to 69c. In the changeable state in which the setting state of the pachinko machine 10 can be changed, the value corresponding to the current setting value is displayed on the third notification display device 69c. The value corresponding to the set value may be displayed on the first notification display device 69a, or may be displayed on the second notification display device 69b. Further, the set value before the changeable state is displayed on the notification display device of one of the first to third notification display devices 69a to 69c, and the current set value is the first to third notification. The display device may be configured to be displayed on the other notification display device among the display devices 69a to 69c.

As shown in FIG. 2, the back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a transparent synthetic resin, and a payout mechanism unit 73 and a control device collective unit 74 are attached to the back pack 72.

The payout mechanism unit 73 includes a tank 75 in which game balls supplied from the island equipment of the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game ball paid out from the payout device 76 is discharged to the upper plate 55a or the lower plate 56a through the payout passage provided on the downstream side of the payout device 76. The payout mechanism unit 73 is provided with, for example, a back pack board having a power switch for turning on and off the power supply while supplying a main power supply of AC 24 volts.

The control device collective unit 74 generates and outputs predetermined electric power required by the payout control device 77 having a function of controlling the payout device 76 and various control devices, and is accompanied by the operation of the launch operation device 28 by the player. It is equipped with a power supply / launch control device 78 for controlling the launch of a game ball. The payout control device 77 and the power supply / launch control device 78 are arranged so as to be stacked in the front-rear direction so that the payout control device 77 is behind the pachinko machine 10.

The back pack 72 is provided with an external terminal plate 79 in addition to the payout mechanism unit 73 and the control device collective unit 74. The external terminal plate 79 is installed at the upper corner portion on the back surface of the pachinko machine 10 on the rotation base end side of the back pack unit 15. The external terminal board 79 outputs a predetermined signal in order to make the management computer of the game hall recognize the state of the pachinko machine 10, and is a substrate for inputting a predetermined signal from the management computer of the game hall to the pachinko machine 10. Is. The management computer receives various information from the main control device 60 and the payout control device 77 through the external terminal plate 79.

<Electrical configuration of pachinko machine 10>
FIG. 8 is a block diagram showing an electrical configuration of the pachinko machine 10.

The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 67 that monitors the power supply. A main MPU 62 is mounted on the main control board 61. The main MPU 62 contains a main ROM 64 and a main RAM 65 in addition to the main CPU 63, which is an arithmetic processing unit including a control unit and an arithmetic unit. Further, the main MPU 62 has a first transmission circuit 101 for transmitting a command to the voice emission control device 90, which will be described later, a second transmission circuit 102 for transmitting a command to the payout control device 77, and a payout. A receiving circuit 103 for receiving a command from the control device 77 is built in. In addition to the above elements, the main MPU 62 has a built-in interrupt circuit, timer circuit, data input / output circuit, various counter circuits as a random number generator, and the like.

The main ROM 64 is a memory (that is, a non-volatile storage means) that does not require external power supply for storage retention such as a NOR type flash memory and a NAND type flash memory, and is used only for reading. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

The main RAM 65 is a memory (that is, a volatile storage means) that requires external power supply for storage retention such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 can be randomly accessed, and the time required for reading is faster than that of the main ROM 64 when compared with the same data capacity. The main RAM 65 temporarily stores various data and the like for the execution of the control program stored in the main ROM 64.

A power failure monitoring board 67 and a payout control device 77 provided in the main control device 60 are connected to the input side of the main MPU 62. A power supply / emission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 67, and operating power is supplied to the main MPU 62 via the power failure monitoring board 67. The command transmitted from the payout control device 77 to the main CPU 63 is received by the receiving circuit 103.

Various sensors such as ball entry detection sensors 42a to 49a are connected to the input side of the main MPU 62. As described above, the ball entry detection sensors 42a to 49a include the first winning opening detection sensor 42a, the second winning opening detection sensor 43a, the third winning opening detection sensor 44a, the special electric detection sensor 45a, and the first operating port detection. A sensor 46a, a second operating port detection sensor 47a, an out port detection sensor 48a, and a gate detection sensor 49a are included. Based on the detection results of the ball entry detection sensors 42a to 49a, the main CPU 63 determines the entry into each entry portion. Further, in the main CPU 63, various lottery is executed based on the winning of the first operating port 33, and various lottery is executed based on the winning of the second operating port 34.

On the input side of the main MPU 62, a setting key insertion portion 68a, an update button 68b, and a reset button 68c provided on the main control board 61 are provided. The setting key insertion unit 68a is provided with a sensor (not shown), and the sensor detects whether the setting key insertion unit 68a is located at the ON operation position or the OFF operation position. Then, the main CPU 63 specifies whether the setting key insertion unit 68a is located at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), and the sensor detects whether or not the update button 68b is pressed. Then, the main CPU 63 specifies whether or not the update button 68b is pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), and the sensor detects whether or not the reset button 68c is pressed. Then, the main CPU 63 specifies whether or not the reset button 68c is pressed based on the detection result from the sensor.

A power failure monitoring board 67, a payout control device 77, and a voice emission control device 90 are connected to the output side of the main MPU 62. For example, a prize ball command is transmitted to the payout control device 77 based on the fact that the game ball has entered the prize ball corresponding entry unit corresponding to the payout of the game ball in the above-mentioned entry unit. To. The main CPU 63 sets a command to be transmitted to the payout control device 77 in the second transmission circuit 102, and the second transmission circuit 102 transmits the set command to the payout control device 77. Various commands such as a normal return command, a return command at the time of partial clearing, a variable command, a type command, and an opening command, which will be described later, are transmitted to the voice emission control device 90. The main CPU 63 sets a command to be transmitted to the voice emission control device 90 in the first transmission circuit 101, and the first transmission circuit 101 transmits the set command to the voice emission control device 90.

On the output side of the main MPU 62, there is a drive unit 32b for special electric power that opens and closes the opening / closing door 32a of the special electric winning device 32, and a drive unit 34b for general electric power that opens and closes the general electric accessory 34a of the second operating port 34. , The special figure unit 37 and the normal figure unit 38 are connected. Incidentally, the special figure unit 37 is provided with a first special figure display unit 37a, a second special figure display unit 37b, a first special figure hold display unit 37c, and a second special figure hold display unit 37d. Are all connected to the output side of the main MPU 62. Similarly, the normal map unit 38 is provided with a normal map display unit 38a and a normal map hold display unit 38b, all of which are connected to the output side of the main MPU 62. Various driver circuits are provided on the main control board 61, and the main MPU 62 executes drive control of various drive units and various display units through the driver circuits.

That is, in the open / close execution mode, the drive control of the special electric drive unit 32b is executed in the main CPU 63 so that the special electric winning device 32 is opened / closed. Further, when the open state of the utility accessory 34a is won, the drive control of the drive unit 34b for the utility is executed in the main CPU 63 so that the utility accessory 34a is opened and closed. Further, at each game round, the display control of the first special figure display unit 37a or the second special figure display unit 37b is executed in the main CPU 63. Further, when the lottery result of whether or not to open the general electric accessory 34a is clearly shown, the display control of the general drawing display unit 38a is executed in the main CPU 63. Further, when a prize is won in the first operating port 33, or when the variable display is started in the first special figure display unit 37a, the display control of the first special figure hold display unit 37c is executed in the main CPU 63. Then, when a prize is won in the second operating port 34, or when the variable display is started in the second special figure display unit 37b, the display control of the second special figure hold display unit 37d is executed in the main CPU 63. Then, when a prize is won in the through gate 35, or when the variable display is started in the normal figure display unit 38a, the display control of the normal figure hold display unit 38b is executed in the main CPU 63.

The first to third notification display devices 69a to 69c are connected to the output side of the main MPU 62. The management result of the game history is notified through the display on the first to third notification display devices 69a to 69c. Further, when the setting state of the pachinko machine 10 is changed, the current setting value is displayed on the third notification display device 69c. The display control of the first to third notification display devices 69a to 69c is performed by the main CPU 63.

The power failure monitoring board 67 relays between the main control board 61 and the power supply / emission control device 78, and monitors the DC stable 24 volt voltage, which is the maximum voltage output from the power supply / emission control device 78. The payout control device 77 controls the payout of prize balls and rental balls by the payout device 76 based on the prize ball command received from the main control device 60.

The power supply / launch control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power source, the operating power required for each of the main control board 61, the payout control device 77, and the like is generated, and the generated operating power is supplied. By the way, the power supply / emission control device 78 is provided with a power supply unit for power failure such as a backup capacitor, and even when the power of the pachinko machine 10 is in the OFF state, the power supply unit for power failure is mainly used. Power for storage retention is supplied to the main RAM 65 of the control device 60 and the payout control device 77. Further, the power supply / launch control device 78 is responsible for launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are met. Further, the payout mechanism unit 73 is provided with a power switch as described above, and when the power switch is turned on, the supply of operating power to the pachinko machine 10 is started and the power switch is turned off. The supply of operating power to the pachinko machine 10 is stopped.

Next, the payout control device 77 will be described.

The payout control device 77 includes a payout control board 81 that controls the payout of the game ball. A payout side MPU 82 is mounted on the payout control board 81. The payout side MPU 82 contains a payout side ROM 84 and a payout side RAM 85 in addition to the payout side CPU 83, which is an arithmetic processing unit including a control unit and an arithmetic unit. Further, the payout side MPU 82 has a built-in payout side transmission circuit 86 for transmitting a command to the main side CPU 63 and a payout side reception circuit 87 for receiving a command transmitted from the main side CPU 63. In addition to the above elements, the payout side MPU 82 has a built-in interrupt circuit, timer circuit, data input / output circuit, various counter circuits as a random number generator, and the like.

The payout side ROM 84 is a memory (that is, a non-volatile storage means) that does not require external power supply for storage retention such as a NOR type flash memory and a NAND type flash memory, and is used only for reading. The payout side ROM 84 stores various control programs and fixed value data executed by the payout side CPU 83.

The payout side RAM 85 is a memory (that is, a volatile storage means) that requires external power supply for storage retention such as SRAM and DRAM, and is used for both reading and writing. The payout side RAM 85 can be randomly accessed, and the time required for reading is faster than that of the payout side ROM 84 when compared with the same data capacity. The payout side RAM 85 temporarily stores various data and the like for the execution of the control program stored in the payout side ROM 84.

Next, the voice emission control device 90 will be described.

The voice emission control device 90 drives and controls the display light emission unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 89. Is. The display control device 89 executes the display control of the symbol display device 41 based on the command received from the voice emission control device 90.

The voice emission control device 90 includes a voice emission control board 91 that controls the effect. The sound light side MPU 92 is mounted on the sound emission control board 91. The sound light side MPU 92 includes a sound light side ROM 94 and a sound light side RAM 95 in addition to the sound light side CPU 93 which is an arithmetic processing device including a control unit and a calculation unit. Further, the sound / light side MPU 92 has a built-in sound / light side receiving circuit 96 for receiving a command transmitted from the main side CPU 63. In addition to the above elements, the sound / light side MPU 92 has a built-in interrupt circuit, timer circuit, data input / output circuit, various counter circuits as a random number generator, and the like.

The sound-light side ROM 94 is a memory (that is, a non-volatile storage means) that does not require external power supply for storage retention such as a NOR type flash memory and a NAND type flash memory, and is used only for reading. The sound light side ROM 94 stores various control programs and fixed value data executed by the sound light side CPU 93.

The sound-light side RAM 95 is a memory (that is, a volatile storage means) that requires external power supply for storage retention such as SRAM and DRAM, and is used for both reading and writing. The sound light side RAM 95 can be randomly accessed, and the time required for reading is faster than that of the sound light side ROM 94 when compared with the same data capacity. The sound light side RAM 95 temporarily stores various data and the like for the execution of the control program stored in the sound light side ROM 94.

Next, the configuration of the main MPU 62 will be described.

FIG. 9 is an explanatory diagram for explaining the configuration of the main MPU 62. As shown in FIG. 9, the main MPU 62 includes W register 104a, A register 104b, B register 105a, C register 105b, D register 106a, E register 106b, H register 107a, and L register 107b as general-purpose registers. There is. These eight general-purpose registers are 1-byte registers. These general-purpose registers can also be used as pair registers by combining two corresponding general-purpose registers. Specifically, the W register 104a and the A register 104b can be combined and used as a 2-byte WA register 104, and the B register 105a and the C register 105b can be combined and used as a 2-byte BC register 105. be able to. Further, the D register 106a and the E register 106b can be combined and used as a 2-byte DE register 106, and the H register 107a and the L register 107b can be combined and used as a 2-byte HL register 107. ..

The main MPU 62 includes an IX register 108 and an IY register 109 as index registers. These two index registers are 2-byte registers. Further, the main MPU 62 includes a 2-byte TP register 111. In the TP register 111, "9000H" is stored as a reference address of the data table which is a reference when the address of the data table is specified. Although the details will be described later, the reference address of the data table is the start address of the area in which various data tables are stored in the main ROM 64. The reference address of the data table stored in the TP register 111 is used to reduce the data capacity of the data for designating the address of the data table. The details of the address specification of the data table performed by using the reference address stored in the TP register 111 will be described later.

The main MPU 62 includes a flag register consisting of 1 byte, and a zero flag ZF is set for one bit in the flag register. The zero flag ZF is a flag in which "1" is set when the calculation result is "0". Further, a carry flag, a P / V flag, a sine flag, a half carry flag, and the like are also set in the flag register. The information of these flags set in the flag register changes depending on the execution result of the operation instruction, the rotate instruction, the input / output instruction, and the like.

<Specific control and non-specific control>
The main CPU 63 executes various controls separately for specific control and non-specific control. Specifically, the control related to the management of the game history is defined as non-specific control, and the control other than the non-specific control is defined as the specific control including the control for advancing the game based on the game operation by the player.

Regarding the specific control, in detail, all the controls by the main process (FIG. 15) executed when the supply of the operating power to the main CPU 63 is started are included in the specific control. When the interrupt by the timer interrupt process is permitted, the timer interrupt process is periodically executed by interrupting the main process (FIG. 15). Among the various processes of the timer interrupt process, the timer interrupt process will be described later. All the processes other than the management process (step S518) to be performed are included in the specific control. In addition, some of the management processes are included in the specific control.

FIG. 10A is an explanatory diagram for explaining the setting mode of various areas in the main RAM 65. As shown in FIG. 10A, addresses "0000H" to "04B2H" are assigned to the main RAM 65. In the main RAM 65, a 1-byte area (hereinafter, also referred to as a 1-byte area) is set for each address. In the present specification, "H" added after the numerical value is a symbol indicating that the numerical value is expressed in hexadecimal.

Corresponding to the fact that the control executed by the main CPU 63 is distinguished between the specific control and the non-specific control, the address range of the work area 121 for the specific control and the non-specific control are also used in the main RAM 65. The address range of the work area 122, the address range of the stack area 123 for specific control, and the address range of the stack area 124 for non-specific control are clearly distinguished.

Specifically, an area of consecutive addresses in the address range of "0000H" to "02FFH" is set as a work area 121 for specific control. Further, "0300H" to "0302H" consecutive in the address range of "0000H" to "02FFH" are addresses of unused areas, and subsequently, continuous in the address range of "0303H" to "03FFH". The area of each address to be used is set as the work area 122 for non-specific control. Further, the address range of "0400H" to "0402H" continuous with the address range of "0303H" to "03FFH" is an address of an unused area, followed by the addresses of "0403H" to "044FH". Areas of consecutive addresses in the range are set as stack areas 123 for specific control. Further, the address range of "0450H" to "0452H" continuous with the address range of "0403H" to "044FH" is an address of an unused area, followed by the addresses of "0453H" to "04AFH". Areas of consecutive addresses in the range are set as stack areas 124 for non-specific control. The relationship between each area and the address as described above is set in both the physical address in the main RAM 65 and the logical address on the memory map recognized by the main CPU 63.

When the work area 121 for specific control and the work area 122 for non-specific control are set separately as described above, the case where the specific control is executed and the case where the non-specific control is executed in the main CPU 63 are executed. Therefore, different areas of the main RAM 65 are used when executing various operations and the like. As a result, when one of the specific control and the non-specific control is executed, it is possible to make it difficult for an event such as the information of the main RAM 65 necessary for the other to be erased to occur.

Since the stack area 123 for specific control and the stack area 124 for non-specific control are set separately, the main CPU 63 may execute specific control or non-specific control. Different areas of the main RAM 65 are used when saving the information stored in the register of the side CPU 63 and when storing the information of the return address on the program. As a result, it is used in the situation where one of the specific control and the non-specific control is being executed, when the information stored in the register of the main CPU 63 is saved and when the information of the return address in the program is stored in the other. It is possible to make it difficult for an event such as the information to be erased to occur. Incidentally, when writing information to each stack area 123, 124, a push instruction is issued by the main CPU 63, and when reading information from each stack area 123, 124, a pop instruction is issued by the main CPU 63. Further, when reading the information from the stack areas 123 and 124, the writing order to the stack areas 123 and 124 is the target to be read first from the later information.

Here, when the main CPU 63 executes the process corresponding to the specific control, the main CPU 63 can write information to the work area 121 for the specific control and the stack area 123 for the specific control. Information can be read from the work area 121 for specific control and the stack area 123 for specific control. On the other hand, when the main CPU 63 executes a process corresponding to the specific control, the main CPU 63 can read information from the work area 122 for the non-specific control and the stack area 124 for the non-specific control. Information cannot be written to the work area 122 for non-specific control and the stack area 124 for non-specific control. This makes it possible to prevent accidentally erasing the information used in the process corresponding to the non-specific control in the situation where the process corresponding to the specific control is being executed.

Further, when the main CPU 63 executes the process corresponding to the non-specific control, the main CPU 63 can write information to the work area 122 for the non-specific control and the stack area 124 for the non-specific control. At the same time, it is possible to read information from the work area 122 for non-specific control and the stack area 124 for non-specific control. On the other hand, when the main CPU 63 executes a process corresponding to the non-specific control, the main CPU 63 can read information from the work area 121 for the specific control and the stack area 123 for the specific control. Information cannot be written to the work area 121 for specific control and the stack area 123 for specific control. This makes it possible to prevent accidentally erasing the information used in the process corresponding to the specific control in the situation where the process corresponding to the non-specific control is being executed.

The backup power is supplied to the main RAM 65 even after the power of the pachinko machine 10 is cut off, and the backup power is the work area 121 for specific control, the work area 122 for non-specific control, and the specific control. It is supplied to all of the stack area 123 for non-specific control and the stack area 124 for non-specific control. As a result, the information stored in the work area 121 for specific control, the work area 122 for non-specific control, the stack area 123 for specific control, and the stack area 124 for non-specific control is used to shut off the power of the pachinko machine 10. Even after that, the memory is retained while the backup power is supplied.

FIG. 10B is an explanatory diagram for explaining the setting mode of the data and the program in the main ROM 64. As shown in FIG. 10B, addresses "9000H" to "9EFFH" are assigned to the main ROM 64. In the main ROM 64, a 1-byte area (1-byte area) is set for each address.

Corresponding to the fact that the control executed by the main CPU 63 is distinguished between the specific control and the non-specific control, the data for the specific control, the program for the specific control, and the non-specific control are also used in the main ROM 64. The address of the area where the data and the program for non-specific control are stored is clearly distinguished.

Specifically, the data for specific control is aggregated and stored in the area of each consecutive address in the address range of "9000H" to "94FFH". Further, the address range of "9500H" to "9502H" continuous with the address range of "9000H" to "94FFH" is an address of an unused area in which data is not stored, followed by "9503H". ~ The program for specific control is collectively stored in the area of each consecutive address in the address range of "98FFH". Further, the address range of "9900H" to "9902H" continuous with the address range of "9503H" to "98FFH" is an address of an unused area in which data is not stored, followed by "9903H". Data for non-specific control is aggregated and stored in a continuous area of each address in the address range of "9BFFF". Further, the address range of "9C00H" to "9C02H" continuous with the address range of "9903H" to "9BFFF" is the address of an unused area in which data is not stored, followed by "9C03". ~ The program for non-specific control is collectively stored in the area of each consecutive address in the address range of "9EFFH". The relationship between the data and the program and the address as described above is set in both the physical address in the main ROM 64 and the logical address on the memory map recognized by the main CPU 63.

As described above, the data for specific control and the program for specific control and the data for non-specific control and the program for non-specific control are irrespective of the execution order of the processes for executing the corresponding control. By being stored in an area of addresses in a different range, for example, when checking only the data for specific control and the program for specific control, the address where the data for specific control and the program for specific control are stored. It is only necessary to check the area of the range. For example, when checking only the data for non-specific control and the program for non-specific control, the address where the data for non-specific control and the program for non-specific control are stored. You only need to check the area of the range. Therefore, it is possible to efficiently perform the work when checking the data and the program separately for the specific control and the non-specific control. In addition, it becomes possible to efficiently perform the work when the data and the program are distinguished and modified by the specific control and the non-specific control accordingly.

No data is stored between the address range of the area where the data for specific control and the program for specific control are stored and the address range of the area where the data for non-specific control and the program for non-specific control are stored. Since the address range of the unused area that has not been set is set, it becomes easy to grasp the boundary between the address range for specific control and the address range for non-specific control during the check work.

In each of the address range for specific control and the address range for non-specific control, the data and the program are stored in the area of the address in a different range regardless of the execution order of the processes for executing the corresponding control. By doing so, it is possible to efficiently perform the work when checking the data separately from the program. In addition, the address range of the unused area where no data is stored is set between the address range of the area where the data is stored and the address range of the area where the program is stored. It becomes easier to grasp the boundary between the address range and the address range of the program when checking.

<Electrical configuration for performing various lottery on the main CPU 63>
Next, an electrical configuration for performing various lottery on the main CPU 63 will be described with reference to FIG. 11.

The main CPU 63 uses various counter information during the game to draw a winning lottery, set the display of the first special figure display unit 37a, set the display of the second special figure display unit 37b, and set the symbol display of the symbol display device 41. , The display of the normal figure display unit 38a is set, and specifically, as shown in FIG. 11, the hit random number counter C1 used for the lottery for the occurrence of hits and the big hit type are used for determining. The jackpot type counter C2, the reach random number counter C3 used for the reach generation lottery when the symbol display device 41 deviates and fluctuates, the random number initial value counter C4 used for setting the initial value of the hit random number counter C1, and each special figure. The variable type counter C5 for determining the display duration in the display units 37a and 37b and the symbol display device 41 is used. Further, the normal electric random number counter C6 used for the lottery as to whether or not the general electric accessory 34a of the second operating port 34 is set to the electric service open state is used. The counters C1 to C6 are provided in the lottery counter area 112 in the work area 121 for specific control.

Each of the counters C1 to C6 is a loop counter in which 1 is added to the previous value each time the counter is updated, and the counter returns to 0 after reaching the maximum value. Each counter is updated at short intervals. The numerical information of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in the special figure holding area 113 when a prize is generated in the first operating port 33 or the second operating port 34. The special figure holding area 113 includes a first special drawing holding area 115, a second special drawing holding area 116, and an execution area 117 for special drawing.

The first special figure holding area 115 includes a first area 115a, a second area 115b, a third area 115c, and a fourth area 115d, and the winning random number counter C1 is provided according to the winning history of the first operating port 33. The numerical information of the jackpot type counter C2 and the reach random number counter C3 is stored in any of the areas 115a to 115d as the reserved information on the special figure side.

In this case, in the first area 115a to the fourth area 115d, when the winning of the first operating port 33 occurs a plurality of times in succession, the first area 115a → the second area 115b → the third area 115c → the first. Each numerical information is stored in chronological order in the order of the four areas 115d. By providing the four areas 115a to 115d in this way, up to four winning histories of the game ball to the first operating port 33 can be reserved and stored.

The number of items that can be stored in the first special figure holding area 115 is not limited to four, and may be arbitrary, and may be another plurality such as two, three, or five or more. , May be singular.

The second special figure holding area 116 includes the first area 116a, the second area 116b, the third area 116c, and the fourth area 116d, and the winning random number counter C1 is provided according to the winning history to the second operating port 34. The numerical information of the jackpot type counter C2 and the reach random number counter C3 is stored in any of the areas 116a to 116d as the reserved information on the special figure side.

In this case, in the first area 116a to the fourth area 116d, when the winning of the second operating port 34 occurs a plurality of times in succession, the first area 116a → the second area 116b → the third area 116c → the first Each numerical information is stored in time series in the order of 4 areas 116d. By providing the four areas 116a to 116d in this way, up to four winning histories of the game ball to the second operating port 34 can be reserved and stored.

The number of items that can be stored in the second special figure holding area 116 is not limited to four, and may be arbitrary, and may be another plurality such as two, three, or five or more. , May be singular.

In the execution area 117 for the special figure, when the variable display is started on any of the special figure display units 37a and 37b, the hold information for the target for performing the hit / fail judgment and the distribution judgment for the special figure is stored. It is an area. Specifically, when the variable display of the first special figure display unit 37a is started, the hold information stored in the first area 115a of the first special figure hold area 115 moves to the execution area 117 for the special figure. Will be done. On the other hand, when the variable display of the second special figure display unit 37b is started, the hold information stored in the first area 116a of the second special figure hold area 116 is moved to the execution area 117 for the special figure.

The special figure holding area 113 is provided with a first special drawing holding number counter 118 and a second special drawing holding number counter 119. The first special figure hold number counter 118 is a counter that allows the main CPU 63 to grasp the number of hold information stored in the first special figure hold area 115, and the second special figure hold number counter 119 is , A counter that allows the main CPU 63 to grasp the number of hold information stored in the second special figure hold area 116. These special figure hold number counters 118 and 119 are composed of 1 byte, and the numerical information of any one of "0" to "4" is stored in these special figure hold number counters 118 and 119.

The value of the first special figure hold number counter 118 is incremented by 1 each time the hold information is stored in the first special figure hold area 115, and the hold information stored in the first special figure hold area 115 is added. When it is moved to the execution area 117 for the special figure, it is subtracted by 1. The value of the second special figure hold number counter 119 is incremented by 1 each time the hold information is stored in the second special figure hold area 116, and the hold information stored in the second special figure hold area 116 is added. When it is moved to the execution area 117 for the special figure, it is subtracted by 1.

The information corresponding to the normal electric random number counter C6 is stored in the normal figure holding area 114 when a prize is won in the through gate 35. The normal figure holding area 114 includes a first area 125a, a second area 125b, a third area 125c, and a fourth area 125d, and numerical information of the normal number counter C6 according to the winning history to the through gate 35. Is stored in any of the areas 125a to 125d as the reserved information on the normal drawing side.

In this case, in the first area 125a to the fourth area 125d, when the through gate 35 is awarded a plurality of times in succession, the first area 125a → the second area 125b → the third area 125c → the fourth area. Numerical information is stored in chronological order in the order of 125d. By providing the four areas 125a to 125d in this way, up to four winning histories of the game ball to the through gate 35 can be reserved and stored.

It should be noted that the number that can be reserved and stored in the normal drawing holding area 114 is not limited to four, and may be any other, such as two, three, or five or more, and may be a single number. May be.

An execution area 126 for a normal map is provided in the normal map hold area 114. The execution area 126 for the normal map is an area in which the hold information to be determined for support is stored when the variable display is started by the normal map display unit 38a. Specifically, when the variable display of the normal map display unit 38a is started, the hold information stored in the first area 125a of the normal map hold area 114 is moved to the execution area 126 for the normal map.

The normal figure holding area 114 is provided with a normal figure holding number counter 127. The normal figure hold number counter 127 is a counter that allows the main CPU 63 to grasp the number of hold information stored in the normal figure hold area 114. The normal figure hold number counter 127 is composed of 1 byte, and the normal figure hold number counter 127 stores numerical information of any one of "0" to "4". The value of the normal figure hold number counter 127 is incremented by 1 each time the hold information is stored in the normal figure hold area 114, and the hold information stored in the normal figure hold area 114 is the execution area for the normal figure. When moved to 126, it is subtracted by 1.

Each of the above counters C1 to C6 will be described in detail. FIG. 12A is an explanatory diagram for explaining the setting modes of the various counters C1 to C6 in the work area 121 for specific control, and FIG. 12B is an explanatory diagram showing various maximum value counters in the work area 121 for specific control. It is explanatory drawing for demonstrating the setting mode of CN1 to CN6.

As shown in FIG. 12 (a), in the work area 121 for specific control, the jackpot type counter C2 is provided in the 1-byte area corresponding to the address of "0011H", and 1 corresponding to the address of "0012H". The reach random number counter C3 is provided in the byte area, the variation type counter C5 is provided in the 1-byte area corresponding to the address of "0013H", and the normal electric random number is provided in the 1-byte area corresponding to the address of "0014H". A counter C6 is provided. Further, a random number counter C1 is provided in a 2-byte area (hereinafter, also referred to as a 2-byte area) corresponding to the addresses of "0015H" to "0016H", and also corresponds to the addresses of "0017H" to "0018H". A random number initial value counter C4 is provided in the 2-byte area.

Specifically, a lower area which is a lower 1-byte area of the random number counter C1 is set in the 1-byte area corresponding to the address of "0015H", and the 1-byte area corresponding to the address of "0016H" is the corresponding area. An upper area, which is an area of the upper 1 byte of the winning random number counter C1, is set. Further, a lower area (lower 1-byte area) of the random number initial value counter C4 is set in the 1-byte area corresponding to the address of "0017H", and the random number is set in the 1-byte area corresponding to the address of "0018H". The upper area (upper 1-byte area) of the initial value counter C4 is set. As described above, in the work area 121 for specific control, these counters C1 to C6 are provided in a continuous address range of "0011H" to "0018H".

The maximum value of the jackpot type counter C2 is "99", the maximum value of the reach random number counter C3 is "238", the maximum value of the variable type counter C5 is "198", and the maximum value of the general electric random number counter C6. Is "250". Further, the maximum value of the hit random number counter C1 and the random number initial value counter C4 is "7999".

As shown in FIG. 12B, in the work area 121 for specific control, the jackpot type in which the maximum value (“99”) of the jackpot type counter C2 is set in the 1-byte area corresponding to the address of “0019H”. The maximum value counter CN2 for reach is provided, and the maximum value counter CN3 for reach in which the maximum value (“238”) of the reach random number counter C3 is set is provided in the 1-byte area corresponding to the address of 001AH. A variable type maximum value counter CN5 in which the maximum value (“198”) of the variable type counter C5 is set is provided in the 1-byte area corresponding to the address of 001BH, and the 1-byte area corresponding to the address of 001CH is provided. Is provided with a general electric maximum value counter CN6 in which the maximum value (“250”) of the general electric random number counter C6 is set. Further, in the 2-byte area corresponding to the addresses of "001DH" to "001EH", a hit maximum value counter CN1 in which the maximum value of the hit random number counter C1 ("7999") is set is provided, and "001FH" is provided. In the 2-byte area corresponding to the addresses of "0020H", the maximum value counter CN4 for the initial value in which the maximum value (" 7999") of the random number initial value counter C4 is set is provided.

Specifically, the lower area (lower 1-byte area) of the maximum value counter CN1 for hitting is set in the 1-byte area corresponding to the address of 001DH, and the hit area corresponds to the 1-byte area corresponding to the address of 001EH. The upper area (upper 1 byte area) of the maximum value counter CN1 is set. Further, a lower area (lower 1-byte area) of the maximum value counter CN4 for the initial value is set in the 1-byte area corresponding to the address of 001FH, and the 1-byte area corresponding to the address of 0020H is used for the initial value. The upper area (upper 1 byte area) of the maximum value counter CN4 is set.

First, the Fuden random number counter C6 will be described. The normal electric random number counter C6 is configured to add 1 in order within the range of 0 to 250 and return to "0" after reaching the maximum value. The normal electric random number counter C6 is periodically updated, and is stored in the normal figure holding area 114 in the work area 121 for specific control at the timing when the game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed as to whether or not to control the general electric accessory 34a to the open state by the value of the stored general electric random number counter C6.

In the pachinko machine 10, a plurality of types of support modes are set so that the modes of support by the general electric accessory 34a are different from each other. Specifically, in the support mode, when the game ball is continuously launched to the game area PA in the same manner, the general electric accessory 34a of the second operating port 34 is per unit time. A high-frequency support mode and a low-frequency support mode are set so that the frequency of opening is relatively high or low.

In the high frequency support mode and the low frequency support mode, the probability of winning the normal power open state in the normal power open lottery using the normal power random number counter C6 is the same (for example, both are 4/5), but it is high. In the frequency support mode, the number of times the normal power accessory 34a is opened when the normal power open state is won is set more than in the low frequency support mode, and one open time is set longer. There is. In this case, in the high-frequency support mode, when the open state of the general electric power is won and the open state of the public electric accessory 34a occurs multiple times, from the end of one open state to the start of the next open state. The closing time is set shorter than the one-time opening time. Furthermore, in the high-frequency support mode, the minimum secured time for the next public-electric open lottery to be held after one public-electric open lottery is performed (that is, the general-purpose map), compared to the low-frequency support mode. The duration of one display on the display unit 38a) is set short.

As described above, in the high frequency support mode, the probability of winning the second operating port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, the probability of winning the first operating port 33 is higher than that of the second operating port 34, but in the high frequency support mode, the second operation is higher than that of the first operating port 33. The probability that a prize will be awarded to the mouth 34 increases.

In addition, the configuration for increasing the frequency of the high-frequency support mode to be in the open state per unit time is higher than that of the low-frequency support mode, and the configuration is not limited to the above. It may be configured to increase the probability of winning the public electric open state. In addition, the secured time secured for the next Fuden opening lottery after one Fuden opening lottery is performed (for example, is executed by the Fuzu display unit 38a based on the winning of the through gate 35). In a configuration in which multiple types of variable display times are prepared, the high-frequency support mode is set so that a shorter reservation time is easier to select or the average reservation time is shorter than the low-frequency support mode. May be good. Furthermore, the number of times of opening is increased, the opening time is lengthened, and the securing time secured for the next public power opening lottery after one public power opening lottery is held is shortened. By applying any one of the conditions or any combination of the conditions of shortening the average time and increasing the winning probability, the advantage of the high frequency support mode over the low frequency support mode may be enhanced.

When the normal electric open state is won in the general electric open lottery using the normal electric random number counter C6, the general electric open state is set. The open state of the general electric power is terminated when the public electric accessory 34a is opened and closed a predetermined number of times, or when a predetermined maximum number of game balls win a prize in the second operating port 34. do. Specifically, regarding these contents, the upper limit number is 10 in common in any of the low frequency support mode and the high frequency support mode. On the other hand, the number of times of opening and closing of the general electric accessory 34a is once in the low-frequency support mode, whereas in the high-frequency support mode, it is more than one in the low-frequency support mode, which is specific. It is 3 times. Further, the opening duration of the general electric accessory 34a once is 1 second in the low frequency support mode, whereas it is 2 seconds in the high frequency support mode.

Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by 1 in order within the range of 0 to 7999, and return to "0" after reaching the maximum value. In particular, when the hit random number counter C1 makes one round, the value of the random number initial value counter C4 at that time is read as the initial value of the hit random number counter C1. The random number initial value counter C4 is a loop counter similar to the hit random number counter C1 (value = 0 to 7999).

The hit random number counter C1 is periodically updated by the timer interrupt process (FIG. 26) described later, and is also updated irregularly by the main process (FIG. 15) described later. The value of the winning random number counter C1 is stored in the first special figure holding area 115 in the work area 121 for specific control at the timing when the game ball wins the first operating port 33, and the game ball is stored in the second operating port 34. It is stored in the second special figure holding area 116 in the work area 121 for specific control at the timing of winning a prize.

The value of the random number that wins the jackpot is stored in the main ROM 64 as a winning / failing table. FIG. 13 is an explanatory diagram for explaining various tables stored in the main ROM 64. As the hit / fail table, the low probability / hit / fail tables 64a to 64f for the low probability mode and the high probability / hit / fail table 64g for the high probability mode are stored.

The low accuracy / rejection tables 64a to 64f are provided so as to correspond one-to-one with the setting states of "setting 1" to "setting 6". That is, the low accuracy table 64a for setting 1 referred to when the setting state of the pachinko machine 10 is "setting 1" and the setting referred to when the setting state of the pachinko machine 10 is "setting 2". The low accuracy table 64b for setting 2, the low accuracy table 64c for setting 3 referred to when the setting state of the pachinko machine 10 is "setting 3", and the setting state of the pachinko machine 10 is "setting 4". The low accuracy table 64d for setting 4 referred to in the case of, the low accuracy table 64e for setting 5 referred to when the setting state of the pachinko machine 10 is "setting 5", and the pachinko machine 10 There is a low probability table 64f for setting 6 which is referred to when the setting state of is "setting 6".

These low probability / failure tables 64a to 64f are set so that the higher the set value, the higher the winning probability of the jackpot result. Specifically, 25 values that result in big hits are set in the low accuracy table 64a for setting 1. When the low accuracy table 64a for setting 1 is referred to, a big hit result is obtained at 1/320. In the low accuracy table 64b for setting 2, 26 values that result in big hits are set. When the low accuracy table 64b for setting 2 is referred to, a big hit result is obtained at about 1/308. In the low accuracy table 64c for setting 3, 27 values that result in big hits are set. When the low accuracy table 64c for setting 3 is referred to, a big hit result is obtained at about 1/296. In the low accuracy table 64d for setting 4, 28 values that result in big hits are set. When the low accuracy table 64d for setting 4 is referred to, a big hit result is obtained at about 1/286. In the low accuracy table 64e for setting 5, 29 values that result in big hits are set. When the low accuracy table 64e for setting 5 is referred to, a big hit result is obtained at about 1/276. In the low accuracy table 64f for setting 6, 30 values that result in big hits are set. When the low accuracy table 64f for setting 6 is referred to, a big hit result is obtained at about 1/267. As a result, when the setting state of the pachinko machine 10 is a high setting value, a big hit result is likely to occur in the low probability mode, which is advantageous for the player.

On the other hand, only one type of the high-accuracy accuracy table 64g is provided so as to be common to any of the setting states of "setting 1" to "setting 6". The high probability hit / fail table 64g is set so that the winning probability of the jackpot result is higher than that of the low probability hit / fail tables 64a to 64f in any of the setting states of "setting 1" to "setting 6". Specifically, 266 values that result in big hits are set in the high probability accuracy table 64g, and other values are values that result in deviation. When the high accuracy table 64g is referred to, a big hit result is obtained at about 1/30. This makes it possible to make the high-probability mode more advantageous than the low-probability mode regardless of the setting state of the pachinko machine 10. In addition, even in the lowest setting state "setting 1", it is possible to increase the probability of a big hit result by setting the high probability mode as compared with the low probability mode of the highest setting state "setting 6". Will be. Further, in the high probability mode, it is possible to prevent the advantages or disadvantages due to the setting state of the pachinko machine 10 from occurring, and the storage capacity for storing the high probability accuracy table 64 g in advance in the main ROM 64 is suppressed. It becomes possible.

In the low probability accuracy table 64a to 64f and the high probability accuracy table 64g, 40 values that result in small hits are set. In the hit / fail judgment, there is a 1/200 probability that a small hit result will be obtained. The probability of a small hit result in the hit / fail determination is the same in "setting 1" to "setting 6", and is the same in the low probability mode and the high probability mode.

Next, the jackpot type counter C2 will be described. The jackpot type counter C2 is configured to add "1" in order within the range of 0 to 99 and return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically. The value of the jackpot type counter C2 is stored in the first special figure holding area 115 at the timing when the game ball wins the first operating port 33, and the second special is stored at the timing when the game ball wins the second operating opening 34. It is stored in the figure holding area 116. Then, the distribution determination for distributing the types of the jackpot results is performed using the value of the stored jackpot type counter C2.

The distribution destination of the type of the jackpot result with respect to the jackpot type counter C2 is stored in the main ROM 64 as a distribution table. As the distribution table, the first special figure distribution table 64h used for the distribution determination of the first special figure side reserved information and the second special figure used for the distribution determination of the second special figure side reserved information. The figure distribution table 64j and the like are set. FIG. 14A is an explanatory diagram for explaining the contents of the first special figure distribution table 64h, and FIG. 14B is an explanation for explaining the contents of the second special figure distribution table 64j. It is a figure. As shown in FIGS. 14A and 14B, the distribution tables 64h and 64j show the 4R high-accuracy jackpot results, the 8R high-accuracy jackpot results, and the 16R high-accuracy jackpot results as the types of jackpot results. And are set.

In the 4R high-accuracy jackpot result, the open / close execution mode is set in which the round game occurs four times. In addition, after the end of the open / close execution mode, the high-probability mode is set regardless of the winning / failing lottery mode before the open / close execution mode transition, and the high-frequency support mode is set regardless of the support mode before the open / close execution mode transition. Become. These high-probability modes and high-frequency support modes continue until eight game rounds are exhausted. If eight game rounds are completed without a new opening / closing execution mode after the opening / closing execution mode triggered by the 4R high-accuracy jackpot result is completed, the winning / failing lottery mode becomes the low-probability mode and the support mode. Is in the low frequency support mode.

In the 8R high-accuracy jackpot result, the open / close execution mode is set in which the round game occurs eight times. In addition, after the end of the open / close execution mode, the high-probability mode is set regardless of the winning / failing lottery mode before the open / close execution mode transition, and the high-frequency support mode is set regardless of the support mode before the open / close execution mode transition. Become. These high-probability modes and high-frequency support modes continue until eight game rounds are exhausted. If eight game rounds are completed without a new open / close execution mode after the open / close execution mode triggered by the 8R high-accuracy jackpot result is completed, the win / fail lottery mode becomes the low-probability mode and the support mode. Is in the low frequency support mode.

In the 16R high-accuracy jackpot result, the open / close execution mode is set in which the round game occurs 16 times. In addition, after the end of the open / close execution mode, the high-probability mode is set regardless of the winning / failing lottery mode before the open / close execution mode transition, and the high-frequency support mode is set regardless of the support mode before the open / close execution mode transition. Become. These high-probability modes and high-frequency support modes continue until eight game rounds are exhausted. If eight game rounds are completed without a new opening / closing execution mode after the opening / closing execution mode triggered by the 16R high-accuracy jackpot result is completed, the winning / failing lottery mode becomes the low-probability mode and the support mode. Is in the low frequency support mode.

Regardless of whether the first special figure distribution table 64h or the second special figure distribution table 64j, the types of jackpot results to be sorted are 4R high accuracy jackpot result, 8R high accuracy jackpot result and 16R high accuracy. It is one of the jackpot results. In this case, in the first special figure distribution table 64h, as shown in FIG. 14A, among the values of the jackpot type counter C2 of "0 to 99", "0 to 39" is a 4R high accuracy jackpot. Corresponding to the result, "40-79" corresponds to the 8R high-accuracy jackpot result, and "80-99" corresponds to the 16R high-accuracy jackpot result. On the other hand, in the second special figure distribution table 64j, as shown in FIG. 14 (b), among the values of the jackpot type counter C2 of "0 to 99", "0 to 29" is the 4R high accuracy jackpot result. Corresponding, "30-79" corresponds to the 8R high-accuracy jackpot result, and "80-99" corresponds to the 16R high-accuracy jackpot result. Although the probability that the 16R high-accuracy jackpot result is selected is the same in the first special figure distribution table 64h and the second special figure distribution table 64j, in the case of the second special figure distribution table 64j, the first The probability that the 4R high-accuracy jackpot result is selected is lower than that of the 1 special figure distribution table 64h, and the probability that the 8R high-accuracy jackpot result is selected is set higher. Therefore, as the type of jackpot result that can be selected when the jackpot is won, the game is triggered by the second special figure side hold information rather than by the first special figure side hold information. It is advantageous for the person.

Only one type of the first special drawing distribution table 64h is provided so as to be common to any of the setting states of "setting 1" to "setting 6", and the second special drawing distribution table 64h is provided. Only one type of table 64j is provided so as to be common to any of the setting states of "setting 1" to "setting 6". As a result, it is possible to prevent the advantages or disadvantages of the pachinko machine 10 depending on the setting state of the pachinko machine 10 in the aspect of the distribution determination, and the distribution table for the first special figure 64h and the distribution table for the second special figure. It is possible to suppress the storage capacity for storing 64j in advance in the main ROM 64.

In addition, the mode of the distribution determination may be different depending on the setting state of the pachinko machine 10. For example, the higher the set value, the higher the probability of being distributed to the 16R high-accuracy jackpot result, or the higher the setting value, the higher the probability of being distributed to the 16R high-accuracy jackpot result or the 8R high-accuracy jackpot result. In addition, the higher the set value, the lower the probability of being distributed to the 4R high-accuracy jackpot result. The higher the setting value, the lower the probability of being distributed to the 4R high-accuracy jackpot result. It may be a configuration that can be sorted. As a result, the higher the set value, the greater the number of round games that occur, which is advantageous for the player.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to add 1 in order within the range of 0 to 238 and return to "0" after reaching the maximum value. Here, in the pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 41. The expected effect is a symbol display device 41 that is provided with a symbol display device 41 capable of displaying variable symbols, and in a gaming machine in which a final stop result is given as a result of a game that results in a predetermined jackpot. In the stage before the stop result is derived and displayed after the variable display of the symbol in the above is started, it means a display state for making the player think that the variable display state is likely to be the grant correspondence result. Specifically, regarding the grant correspondence result, the combination of symbols with the same number on any of the effective lines is stopped and displayed.

Two types of expected effects are set: a reach display and a notice display for expecting the occurrence of the reach display and the occurrence of the grant response result in the stage before the reach display occurs.

In the reach display, the combination of reach symbols is displayed by stopping and displaying a part of the symbol rows among the plurality of symbol rows displayed on the display surface 41a of the symbol display device 41, and the remaining symbols are displayed in that state. A display state in which a variable display of a symbol is performed in a symbol column is included. In addition, in the state where the combination of reach symbols is displayed as described above, the variation display of the symbols is performed in the remaining symbol rows, and the reach effect is performed by displaying a predetermined character or the like as a moving image on the background screen. , A combination of reach symbols is reduced or hidden, and a predetermined character or the like is displayed as a moving image on substantially the entire display surface 41a to perform a reach effect.

In the notice display, after the variable display of the symbol is started on the display surface 41a of the symbol display device 41, the symbol is variablely displayed in all the symbol rows Z1 to Z3, or in a part of the symbol rows. Therefore, in a situation where the symbols are displayed in a variable manner in a plurality of symbol rows, a mode in which the character is displayed separately from the symbols on the symbol rows Z1 to Z3 is included. Further, the background screen has a predetermined mode different from the previous mode, and the symbols on the symbol rows Z1 to Z3 have a predetermined mode different from the previous mode. Such a notice display may occur in any of the game times when the reach display is performed and when the reach display is not performed, but the case where the reach display is performed is higher than the case where the reach display is not performed. It is set to occur with a probability.

The reach display is executed regardless of the value of the reach random number counter C3 in the game times when the combination of the same symbols is finally stopped and displayed. On the other hand, in the game times corresponding to the small hit result, it is not executed regardless of the value of the reach random number counter C3. Further, in the game times corresponding to the deviation result, the value of the reach random number counter C3 acquired at a predetermined timing by referring to the reach table stored in the reach table storage area of the main ROM 64 corresponds to the occurrence of the reach display. It is executed when it is determined that it is.

On the other hand, the determination as to whether or not to display the advance notice is performed not by the main CPU 63 but by the sound and light side CPU 93. In this case, in the sound / light side CPU 93, the game times corresponding to either the big hit result or the small hit result are more likely to generate the notice display and the appearance rate is lower than the game times corresponding to the missed result. The lottery process for displaying the notice is executed so as to satisfy at least one of the conditions that the notice display is likely to occur. Incidentally, this lottery result is reflected when the effect for the game round is executed on the symbol display device 41.

Next, the variation type counter C5 will be described. The variation type counter C5 is configured to be incremented by 1 in order within the range of 0 to 198, and returns to "0" after reaching the maximum value. The variation type counter C5 is used in the main CPU 63 to determine the display duration in the first special symbol display unit 37a or the second special symbol display unit 37b and the symbol display duration in the symbol display device 41. Specifically, the value of the fluctuation type counter C5 is used when the fluctuation pattern is determined at the start of the fluctuation display on the first special symbol display unit 37a or the second special symbol display unit 37b and at the start of the fluctuation of the symbol by the symbol display device 41. To be acquired.

<About the processing configuration of the main CPU 63>
Next, each process executed for advancing the game on the main CPU 63 will be described. The processing of the main CPU 63 is roughly divided into a main processing that is started when the power is turned on and a timer interrupt processing that is started periodically (in this embodiment, at a cycle of 4 milliseconds).

<Main processing>
First, the main process will be described with reference to the flowchart of FIG.

In the main process, first, the power-on weight process is executed (step S101). In the power-on weight process, for example, the process waits without proceeding to the next process until a predetermined time for weight (specifically, 1 second) elapses after the main process is started. During the execution period of the power-on weight process, the operation start and initial setting of the symbol display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

After that, the instruction "LD IY, 0000H" is executed (step S103). In step S103, the specific control reference address "0000H" is loaded into the IY register 109 of the main MPU 62 by the LD instruction. The specific control reference address is data for designating an area corresponding to an address of "0000H" to "00FFH" in the work area 121 for specific control in a situation where the processing for specific control is being executed. It is used to reduce the data capacity of. As shown in FIG. 10A, "0000H" is a start address in the work area 121 for specific control.

In this way, the specific control reference address (“0000H”) is stored in the IY register 109 at the start of the main process, which is the process for specific control. As a result, when any of "0000H" to "00FFH" is specified in the first LDY instruction and the second LDY instruction described later, the data of the address specification is limited to the lower 1 byte in the 2-byte address information. Is possible.

After that, the instruction "LD TP, 9000H" is executed (step S104). In step S104, the data table reference address "9000H" is loaded into the TP register 111 of the main MPU 62 by the LD instruction (step S104). As already described with reference to FIG. 10B, the data for specific control is set in the address range of "9000H" to "94FFH" in the main ROM 64, and the data for non-specific control is "9903H". It is set in the address range of "9BFFF". The upper 4 bits of the address corresponding to the area where the data table is stored in the main ROM 64 are common to "9H". The reference address (“9000H”) of the data table is stored in the TP register 111 at the start of the main process. As a result, when any of "9000H" to "94FFH" and "9903H" to "9BFFH" is specified in the LDT instruction described later, the data of the address specification is only the lower 12 bits of the 2-byte address information. It becomes possible to. Further, the reference address of the data table stored in the TP register 111 can be used in the LDB instruction and the LDB update instruction described later.

After that, it is determined whether or not the setting key insertion unit 68a is turned on (step S105). When the setting key insertion unit 68a is not turned on (step S105: NO), it is determined whether or not the reset button 68c is pressed (step S106). When the reset button 68c is pressed (step S106: YES), a partial clearing process is executed (step S107).

In the partial clearing process (step S107), each area of the main RAM 65 is cleared to "0" and "0" is cleared while maintaining the information of the set value counter provided in the work area 121 for specific control. Make initial settings for the area. The set value counter is a counter that allows the main CPU 63 to grasp the set value of the pachinko machine 10. The set value counter consists of 1 byte, and the set value counter stores numerical information of "1" to "6" corresponding to "setting 1" to "setting 6". Information on the set value (information stored in the set value counter) when the supply of operating power to the pachinko machine 10 is started while pressing the reset button 68c without turning on the setting key insertion unit 68a. For), the clear processing of the main RAM 65 is executed while maintaining the state before the supply of the operating power to the pachinko machine 10 is stopped, and the initial setting is performed for the storage area where the clear processing is executed. Will be. This makes it possible to initialize other areas of the main RAM 65 without requiring a change in the set value.

In the partial clearing process (step S107), first, the information of the set value counter is saved in the W register 104a. After that, the first clear process for clearing the work area 121 for specific control set to the addresses of "0000H" to "02FFH" in the main RAM 65 by "0" is executed, and the identification after clearing the "0" is executed. Initial settings are made for the control work area 121. After that, the information saved in the W register 104a is written to the set value counter. After that, the second clear process for clearing the stack area 123 for specific control set to the addresses of "0403H" to "044FH" in the main RAM 65 is executed, and the identification after clearing the "0" is executed. Initialize the control stack area 123. After that, a third clear process for clearing the work area 122 for non-specific control set to the addresses of "0303H" to "03FFH" in the main RAM 65 by "0" is executed, and after the "0" is cleared, the third clear process is executed. Initialize the work area 122 for non-specific control. After that, the fourth clear process of clearing the stack area 124 for non-specific control set to the addresses of "0453H" to "04AFH" in the main RAM 65 by "0" is executed, and after the "0" is cleared. Initialize the stack area 124 for non-specific control. In the first clear process in the partial clear process (step S104), the start address of the area to be cleared to "0" is used by using the specific control reference address ("0000H") stored in the IY register 109. ("0000H") is specified. The details of the first clearing process will be described later.

In the partial clearing process (step S107), among the various registers of the main MPU 62, the registers other than the IY register 109 and the TP register 111 are initially set after clearing "0". On the other hand, the state in which the specific control reference address (“0000H”) is set in the IY register 109 and the state in which the data table reference address (“9000H”) is set in the TP register 111 are maintained.

After the partial clearing process is executed in step S107, "1" is set in the partial clearing flag provided in the work area 121 for specific control (step S108). The partial clear flag is a flag that enables the main CPU 63 to grasp that the partial clear process (step S107) has been executed. By setting the partial clear flag to "1" in step S108, the return command corresponding to the execution of the partial clear process (step S107) in the return command transmission process (step S113) described later (step S113). It is possible to send a return command when partially cleared) to the sound and light side CPU 93. Further, by setting "1" to the partial clear flag, it becomes possible to execute the clear time setting process (FIG. 22 (b)) described later in the clear correspondence process (step S120) described later.

When the reset button 68c is not pressed (step S106: NO), it is determined whether or not "1" is set in the power failure flag 131a (FIG. 16B) (step S109). The power failure flag 131a is provided in the work area 121 for specific control, and when the supply of operating power to the main CPU 63 is stopped and the predetermined power failure processing is normally executed, the power failure occurs. “1” is set in the flag 131a. The details of the power failure flag 131a will be described later.

When "1" is set in the power failure flag 131a (step S109: YES), whether or not the checksum calculation result matches the checksum saved when the power is cut off, that is, the validity of the stored data. Is determined (step S110).

When the process of step S108 is executed or when an affirmative determination is made in step S110, it is determined whether or not the set value of the pachinko machine 10 is normal (step S111). In step S111, the set value of the pachinko machine 10 is grasped based on the value of the set value counter provided in the work area 121 for specific control. As described above, the set value counter stores the numerical information of "1" to "6" corresponding to "setting 1" to "setting 6". In step S111, when the value of the set value counter is any one of "1" to "6", it is determined to be normal, and when it is "0" or "7" or more, it is determined to be abnormal.

If a negative determination is made in any of steps S109 to S111, the operation prohibition process is executed. In the operation prohibition process, an infinite loop occurs after the error notification process for notifying the hall manager or the like of the occurrence of an error is executed (step S112). The operation prohibition process is canceled by executing a partial clear process (step S107) or a full clear process (step S114) described later.

If an affirmative determination is made in all of steps S109 to S111, the return command transmission process is executed (step S113). In the return command transmission process, when "1" is set in the partial clear flag in the work area 121 for specific control, the return command at the time of partial clear is transmitted to the sound light side CPU 93. The return command at the time of partial clearing is a command for causing the sound and light side CPU 93 to recognize that the partial clearing process (step S107) has been executed. When the sound / light side CPU 93 receives the return command at the time of partial clearing, the sound / light side CPU 93 controls the display of the symbol display device 41 so that a display notifying that the partial clearing process (step S107) has been executed is performed. As a result, it is possible to notify the manager of the game hall that the partial clearing process (step S107) has been executed. Further, in the return command transmission process in step S113, if "1" is not set in the partial clear flag, the normal return command is transmitted to the sound / light side CPU 93. The normal return command is a command for causing the sound and light side CPU 93 to recognize that the partial clear process (step S107) and the all clear process (step S114) described later have not been executed when the power is restored. When the sound light side CPU 93 receives the normal return command, the symbol display is performed so as to notify that the partial clear process (step S107) and the full clear process (step S114) have not been executed when the power is restored. The display of the device 41 is controlled. As a result, it is possible to notify the manager of the game hall that the partial clearing process (step S107) and the complete clearing process (step S114) have not been executed when the power is restored. The details of the return command transmission process will be described later.

On the other hand, when the setting key insertion unit 68a is turned on (step S105: YES), all clear processing is executed (step S114). In the all clear process, all areas of the main RAM 65 are cleared by "0" and "0" is cleared, including the area in which the information of the set value indicating the setting state of the pachinko machine 10 is set in the main RAM 65. Make initial settings for the area. That is, when the operation for changing the setting state of the pachinko machine 10 is performed, all the areas of the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the clearing is performed. Initial settings are made for the storage area where the processing was executed. Even if the operation for changing the setting state of the pachinko machine 10 is performed, if the reset button 68c is not pressed, the pachinko machine is not completely cleared and the pachinko machine is not cleared. The configuration may be such that all clear processing is executed when the operation for changing the setting state of the machine 10 is performed and the reset button 68c is pressed.

In the all clearing process (step S114), first, the first clearing process of clearing the work area 121 for specific control set to the addresses of "0000H" to "02FFH" in the main RAM 65 by "0" is executed, and at the same time, the first clearing process is executed. Initial settings are made for the work area 121 for specific control after the "0" is cleared. After that, the second clear process for clearing the stack area 123 for specific control set to the addresses of "0403H" to "044FH" in the main RAM 65 is executed, and the identification after clearing the "0" is executed. Initialize the control stack area 123. After that, the third clear process for clearing the work area 122 for non-specific control set to the addresses of "0303H" to "03FFH" in the main RAM 65 by "0" is executed, and after the "0" is cleared, the third clear process is executed. Initialize the work area 122 for non-specific control. After that, the fourth clear process of clearing the stack area 124 for non-specific control set to the addresses of "0453H" to "04AFH" in the main RAM 65 by "0" is executed, and after the "0" is cleared. Initialize the stack area 124 for non-specific control. In the first clear process in the all clear process (step S114), the start address ("0" clear target area start address ("0") is used by using the specific control reference address ("0000H") stored in the IY register 109. "0000H") is specified. The details of the first clearing process will be described later.

In the all clear process (step S114), "0" is cleared for the registers other than the IY register 109 and the TP register 111 among the various registers of the main MPU 62, as in the partial clear process (step S107) already described. After that, make the initial settings. On the other hand, the state in which the specific control reference address (“0000H”) is set in the IY register 109 and the state in which the data table reference address (“9000H”) is set in the TP register 111 are maintained.

After executing the all clear process in step S114, "1" is set in the all clear flag provided in the work area 121 for specific control (step S115). The all clear flag is a flag that enables the main CPU 63 to grasp that the all clear process (step S114) has been executed. By setting "1" to the all clear flag in step S115, it becomes possible to execute the clear time setting process (FIG. 22 (b)) described later in the clear correspondence process (step S120) described later.

After that, a return command at the time of clearing all is transmitted to the sound light side CPU 93 (step S116). The return command at the time of clearing all is a command for causing the sound light side CPU 93 to recognize that the clear processing (step S114) has been executed at the time of power recovery. When the sound and light side CPU 93 receives the return command at the time of clearing all, the sound and light side CPU 93 controls the display of the symbol display device 41 so that the display notifying that the all clear process (step S114) has been executed is performed. As a result, it is possible to notify the manager of the game hall that the all clearing process (step S114) has been executed. After that, the setting value update process described later is executed (step S117).

When the process of step S113 is performed or the process of step S117 is performed, the power-on setting process is executed (step S118). In the power-on setting process, initial settings are made for a predetermined area in the work area 121 for specific control such as initialization of the power failure flag 131a. The details of the power-on setting process will be described later.

After that, the random number maximum value setting process is executed (step S119). In the random number maximum value setting process, the maximum value of the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the variable type counter C5, and the general electric random number counter C6 are set to the maximum value counters CN1 to CN6. Set. After that, the clear correspondence process is executed (step S120). The details of the random number maximum value setting process (step S119) and the clear correspondence process (step S120) will be described later.

After that, the process proceeds to the residual processing of steps S121 to S124. The main CPU 63 is configured to periodically execute the timer interrupt process, but the occurrence of the timer interrupt process is prohibited at the stage when the main process is started. The state in which the occurrence of the timer interrupt process is prohibited is released by executing the process of step S121 after the process of step S120 is completed, and the execution of the timer interrupt process is permitted. The main CPU 63 is configured to periodically execute timer interrupt processing, but a residual time is generated between one timer interrupt processing and the next timer interrupt processing. This residual time varies depending on the processing completion time of each timer interrupt process, and the residual process of steps S121 to S124 is repeatedly executed by utilizing the irregular time. In this respect, it can be said that the residual processing in steps S121 to S124 is an irregular processing that is executed irregularly.

In the residual processing, first, the interrupt enable setting for switching from the state in which the occurrence of the timer interrupt processing is prohibited to the state in which the timer interrupt processing is permitted is set (step S121). After that, in order to prohibit the occurrence of timer interrupt processing, interrupt prohibition is set (step S122). After that, the random number initial value update process for updating the random number initial value counter C4 is executed (step S123). In the random number initial value update process, the value of the random number initial value counter C4 is added by 1, and when the value after the 1 addition exceeds the maximum value "7999", the value of the random number initial value counter C4 is set to "0". clear.

After that, the variable counter update process for updating the variable type counter C5 is executed (step S124). In the variable counter update process, the value of the variable type counter C5 is added by 1, and when the value after the 1 addition exceeds the maximum value of "250", the value of the variable type counter C5 is cleared by "0". .. After that, the process returns to step S121, and the residual processing of steps S121 to S124 is repeated.

Next, the power-on setting process in step S118 of the main process (FIG. 15) will be described.

FIG. 16A is an explanatory diagram for explaining a storage area in which “0” is cleared and initial setting is performed in the power-on setting process. As shown in FIG. 16A, a power failure area 131 is provided at the address of "0001H" in the work area 121 for specific control, and the fraud monitoring timer counter 132 is provided at the addresses of "0008H" to "0009H". Is provided, the fraudulent radio wave detection counter 133 is provided at the address of "0021H", the fraudulent magnetic detection counter 134 is provided at the address of "0022H", and the address of "0023H" is abnormal. A vibration detection counter 135 is provided.

The upper 1 byte of the address for specifying the storage area where "0" is cleared and the initial setting is performed in the power-on setting process is common to "00H". In the power-on setting process, the "00H" is set in the D register 106a, and the lower 1 byte of the address is read from the data table and set in the E register 106b, so that the entire address (2 bytes) is set in the DE register 106. ) Is stored. Then, the area for clearing "0" and initializing is specified by using the address information stored in the DE register 106. This makes it possible to reduce the data capacity of the data stored in the main ROM 64 for address designation.

The power failure area 131 is a 1-byte area including the power failure flag 131a. FIG. 16B is an explanatory diagram for explaining the data structure of the power failure area 131. As shown in FIG. 16B, the power failure flag 131a is set in the least significant bit (0th bit) in the power failure area 131, and the 1st to 7th bits in the power failure area 131 are unused bits. It has become.

Although not shown, the pachinko machine 10 includes an illegal radio wave detection sensor for detecting an illegal radio wave, an illegal magnetic detection sensor for detecting an illegal magnetism, and an abnormal vibration for detecting an abnormal vibration. A detection sensor is provided. The detection signals of these detection sensors are input to the input side of the main MPU 62. The main CPU 63 grasps that an illegal radio wave is detected when the detection signal received from the illegal radio wave detection sensor is in the HI state, and the detection signal received from the illegal magnetic detection sensor is in the HI state. Understand that an abnormal magnetism is detected in a certain case, and that an abnormal vibration is detected when the detection signal received from the abnormal vibration detection sensor is in the HI state. .. The fraudulent radio wave detection counter 133 can grasp whether or not the state in which a fraudulent radio wave is detected is specified five times during one fraud monitoring reference period (specifically, about 262 seconds) by the main CPU 63. The fraudulent magnetism detection counter 134 is a counter that allows the main CPU 63 to grasp whether or not the state in which fraudulent magnetism is detected is specified 10 times during one fraud monitoring reference period. The abnormal vibration detection counter 135 is a counter that allows the main CPU 63 to grasp whether or not the state in which abnormal vibration is detected is specified 15 times during one fraud monitoring reference period. These detection counters 133 to 135 consist of 1 byte. The fraudulent radio wave detection counter 133 is set to "5" ("0101B") as an initial value, the fraudulent magnetic detection counter 134 is set to "10" ("1010B") as an initial value, and the abnormal vibration detection counter 135 is set to "10" ("1010B"). Is set to "15" ("1111B") as an initial value. One fraud monitoring standard period is about 262 seconds, and when the fraud monitoring standard period ends, the next fraud monitoring standard period starts. That is, the fraud monitoring reference period is repeatedly set in a cycle of about 262 seconds. In addition, "B" added after a numerical value in this specification is a symbol indicating that the numerical value is expressed in binary.

The initial value of the fraudulent magnetic detection counter 134 is from the initial value of the fraudulent radio wave detection counter 133 so that if the magnetic material contained in the player's belongings accidentally approaches the game board 24, it is not mistakenly recognized as fraudulent. Is also set large. Further, the initial value of the abnormal vibration detection counter 135 is the initial value of the fraudulent radio wave detection counter 133 and the fraudulent magnetic detection so that the player does not mistakenly recognize the fraud when the player accidentally touches the pachinko machine 10 and vibrates lightly. It is set larger than the initial value of the counter 134. The initial values of these detection counters 133 to 135 are not limited to the above values and are arbitrary.

The main CPU 63 subtracts 1 from the value of the illegal radio wave detection counter 133 each time the timer interrupt process (FIG. 26) described later is executed while the illegal radio wave is detected, and the illegal magnetic field is detected. Each time the timer interrupt process (FIG. 26) described later is executed in the state, the value of the illegal magnetic detection counter 134 is subtracted by 1, and the timer interrupt process (FIG. 26) described later is executed in the state where abnormal vibration is detected. The value of the abnormal vibration detection counter 135 is subtracted by 1 each time. Then, when any value of these detection counters 133 to 135 becomes "0", the fraud detection response process is executed. In the fraud detection response process, "1" is set in the game stop flag provided in the work area 121 for specific control. The game stop flag is a flag that enables the main CPU 63 to grasp whether or not the progress of the game is stopped. When the game stop flag is set to "1", the progress of the game is stopped. The details of the fraud detection response process will be described later.

In the fraud detection response process, when the state in which fraudulent radio waves are detected is identified five times during one fraud monitoring standard period, the state in which fraudulent magnetism is detected is one fraud monitoring. It is executed when it is specified 10 times during the reference period, or when the state in which abnormal vibration is detected is specified 15 times during one fraud monitoring reference period. Therefore, when the rise of the detection signal received from the fraudulent radio wave detection sensor, the fraudulent magnetic detection sensor, or the abnormal vibration detection sensor from the LOW state to the HI state is detected once, the fraud detection response process is immediately executed. In comparison with the above, it is possible to reduce the possibility that the fraud detection response process is erroneously executed due to the influence of noise.

The fraud monitoring timer counter 132 is a 2-byte counter that allows the main CPU 63 to grasp that the fraud monitoring reference period has elapsed without executing the fraud detection response process. The initial value of the fraud monitoring timer counter 132 is "0". The fraud monitoring timer counter 132 is incremented by 1 each time the timer interrupt process (FIG. 26) described later is executed, and when it exceeds the maximum value of "65535", it makes one round and becomes "0". The main CPU 63 specifies that the fraud monitoring reference period has elapsed each time the value of the fraud monitoring timer counter 132 makes one round, and initially sets the fraud radio wave detection counter 133, the fraud magnetic detection counter 134, and the abnormal vibration detection counter 135. Set the value. By configuring the detection counters 133 to 135 to be initialized each time the fraud monitoring reference period elapses, the influence of noise generated over a long period (for example, 10 hours) exceeding the fraud monitoring reference period accumulates. Therefore, it is possible to prevent the values of these detection counters 133 to 135 from becoming "0".

<LDT command>
Next, prior to the explanation of the program contents of the power-on setting process (FIG. 17 (c)), the LDT instruction included in the program of the power-on setting process will be described. FIG. 17A is an explanatory diagram for explaining the data structure of the machine language of the LDT instruction, and FIG. 17B is an explanatory diagram for explaining the data structure of the machine language of the LD instruction. (C) is an explanatory diagram for explaining the program contents of the power-on setting process.

As shown in FIG. 17C, the power-on setting processing program includes an LDT instruction "LDT HL, 400H". The main CPU 63 can execute an LDT instruction in addition to the LD instruction as a transfer instruction for transferring data. As shown in FIG. 9, the main MPU 62 includes an LDT execution circuit 149. The LDT execution circuit 149 is a dedicated circuit for executing an LDT instruction.

The instruction code of the LD instruction has a configuration of "LD transfer destination, transfer source". In the LD instruction, a general-purpose register such as the W register 104a is set as the "transfer destination", a pair register such as the WA register 104 or a storage area of the main RAM 65 is set, and a general-purpose register such as the W register 104a is set as the "transfer source". A pair register such as the WA register 104, data stored in the storage area of the main RAM 65, or a numerical value is set.

In the LD instruction, the 2-byte numerical information set in the "transfer source" is loaded in the "transfer destination". For example, when the instruction "LD HL, 9400H" is executed, "9400H" set in the "transfer source" is loaded into the HL register 107 set in the "transfer destination".

The instruction code of the LDT instruction has a configuration of "LDT transfer destination, transfer source". In the LDT instruction, the HL register 107 is set as the "forwarding destination". In the LDT instruction, a 12-bit numerical value (for example, "400H") is set as the "transfer source". The WA register 104, the BC register 105, or the DE register 106 may be set as the "forwarding destination" of the LDT instruction.

In the LDT instruction, the 2-byte numerical information obtained by adding the 2-byte numerical information set in the TP register 111 to the 12-bit numerical information set in the "transfer source" is the "transfer destination". Loaded into the pair register set to. As described above, in the present embodiment, the TP register 111 is set to "9000H", which is the reference address of the data table. By executing "LDT HL, 400H" in a state where "9000H" is set in the TP register 111 in advance, the HL register 107 is executed in the same manner as when the above-mentioned "LD HL, 9400H" is executed. "9400H" is loaded.

First, the data structure of the machine language of the LD instruction will be described while exemplifying "LD HL, 9400H" as a specific instruction code of the LD instruction. "LD HL, 9400H" is an instruction code for loading the 2-byte numerical information "9400H" into the HL register 107. As shown in FIG. 17B, in the machine language of the LD instruction, instruction data instructing to load the data of the "transfer source" to the "transfer destination" and the HL register 107 as the "transfer destination" are specified. The data for specifying the transfer destination and the data for specifying the transfer source for specifying the "transfer source" are included. In the machine language of the LD instruction, the total data capacity of the instruction data and the transfer destination designated data is 2 bytes, and the data capacity of the transfer source designated data is 2 bytes. As described above, the machine language data capacity of the LD instruction is 4 bytes in total.

Next, the data structure of the machine language of the LDT instruction will be described while exemplifying "LDT HL, 400H" as a specific instruction code of the LDT instruction. As shown in FIG. 17A, the machine language of the LDT instruction includes instruction data instructing to load the data of the “transfer source” to the “transfer destination”, similarly to the machine language of the LD instruction described above. , The transfer destination designation data that designates the HL register 107 as the "transfer destination" and the transfer source designation data that designates the "transfer source" are included. In the machine language of the LDT instruction, the total data capacity of the instruction data and the transfer destination designated data is 4 bits, and the data capacity of the transfer source designated data is 12 bits. In the case of "LDT HL, 400H", 12-bit numerical information "400H" is set as the "transfer source", and the 12-bit numerical information "400H" is used as it is in the machine language of the LDT instruction. It is included as transfer source specified data. As described above, the total data capacity of the machine language of the LDT instruction is 2 bytes.

Therefore, when "9000H" is stored in the TP register 111 and the address of the data table stored in the main ROM 64 is loaded into the HL register 107, the LDT instruction is used instead of the LD instruction. By doing so, the machine language of the instruction for loading the data of the "transfer source" to the "transfer destination" can be reduced by 2 bytes. As a result, the data capacity of the program in the main ROM 64 can be reduced.

Next, the program contents of the power-on setting process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 17 (c). The power-on setting process is executed in step S118 of the main process (FIG. 15). As shown in FIG. 17 (c), "1001" to "1005" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LDT HL, 400H" is set in the line number of "1001". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "400H" sets 12-bit numerical information of "400H" as a transfer source. The content. As described above, the reference address (“9000H”) of the data table is set in the TP register 111 in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 400H", "9400H" obtained by adding "9000H" set in the TP register 111 to "400H" set as the transfer source is obtained. It is loaded into the HL register 107. The main ROM 64 stores the first initialization table 64k (FIG. 18A) as a data table for setting initial values in the fraudulent radio wave detection counter 133, the fraudulent magnetic detection counter 134, and the abnormal vibration detection counter 135. "9400H" is the start address of the first initialization table 64k. The details of the first initialization table 64k will be described later.

In this way, by using the LDT instruction to set the start address of the first initialization table 64k in the HL register 107, the LD instruction is used to start the first initialization table 64k in the HL register 107. Compared with the configuration in which the address is set, the data capacity of the program for executing the power-on setting process can be reduced.

The command "XOR D, D" is set in the line number of "1002". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma specifies the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. Will be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As already described with reference to FIG. 16A, the upper 1 byte in the address of the area and the counter to be the target of the power-on setting process is common to "00H". The instruction of the line number "1002" is an instruction for setting the common upper 1 byte ("00H") in the D register 106a.

An instruction "CALL 4BTS10" is set in the line number of "1003". “4BTS10” is a data setting execution process (FIG. 19 (c)) described later. The instruction "CALL 4BTS10" is an instruction for calling a subroutine called data setting execution processing. At the line number "1003", the data setting execution process is executed in a state where the start address of the first initialization table 64k is set in the HL register 107 and "00H" is stored in the D register 106a. As described above, the first initialization table 64k is a data table for setting initial values in the fraudulent radio wave detection counter 133, the fraudulent magnetism detection counter 134, and the abnormal vibration detection counter 135. By executing the data setting execution process at the line number "1003", "5" is set as the initial value in the fraudulent radio wave detection counter 133, and "10" is set as the initial value in the fraudulent magnetic detection counter 134. Then, "15" is initially set in the abnormal vibration detection counter 135. When the subroutine of the data setting execution process called based on the instruction of the line number "1003" is completed, the process proceeds to the line number of "1004". Although the details will be described later, when the data setting execution process is executed at the line number “1003”, the start address of the second initialization table 64m (FIG. 18 (b)) in the main ROM 64 is set in the HL register 107. It will be in the set state. The second initialization table 64m is a data table for clearing the power failure area 131 and the fraud monitoring timer counter 132 by "0". The details of the second initialization table 64m will be described later.

The command "CALL 4BTS10" is also set in the line number of "1004". In the line number "1004", the data setting execution process is executed in a state where the start address of the second initialization table 64m is set in the HL register 107 and "00H" is stored in the D register 106a. By executing the data setting execution process at the line number “1004”, the power failure area 131 and the fraud monitoring timer counter 132 are cleared to “0”. When the subroutine of the data setting execution process called based on the instruction of the line number "1004" is completed, the process proceeds to the line number of "1005".

An instruction "RET" is set in the line number of "1005". As described above, the power-on setting process is a subroutine executed in step S118 of the main process (FIG. 15). Therefore, when the instruction "RET" is executed, the process proceeds to step S119 of the main process (FIG. 15).

The process of initializing the fraudulent radio wave detection counter 133, the fraudulent magnetic detection counter 134, and the abnormal vibration detection counter 135 using the first initialization table 64k is described later in addition to the power-on setting process (FIG. 17 (c)). The fraud detection process (FIG. 29 (a)) is executed in the fraud detection initialization process (FIG. 29 (b)) in step S812. Since the initialization table is stored separately in the main ROM 64 as the first initialization table 64k and the second initialization table 64m, only the first initialization table 64k is used in the processing other than the power-on setting processing. It is possible to execute the process of initializing the fraudulent radio wave detection counter 133, the fraudulent magnetic detection counter 134, and the abnormal vibration detection counter 135.

<Data structure of initialization table 64k, 64m>
Next, the first initialization table 64k and the second initialization table 64m stored in the main ROM 64 will be described.

FIG. 18A is an explanatory diagram for explaining the data structure of the first initialization table 64k, and FIG. 18B is an explanatory diagram for explaining the data structure of the second initialization table 64m. As described above, the first initialization table 64k is a data table for setting initial values in the fraudulent radio wave detection counter 133, the fraudulent magnetic detection counter 134, and the abnormal vibration detection counter 135, and the second initialization table 64m. Is a data table for clearing the power failure area 131 and the fraud monitoring timer counter 132 by "0".

In the main ROM 64, the first initialization table 64k is stored in the address range of “9400H” to “9405H” as shown in FIG. 18A, and the second initialization table 64m is shown in FIG. As shown in b), it is stored in the address range of "9406H" to "940BH" following the address range of the first initialization table 64k.

As shown in FIGS. 18A and 18B, the initialization tables 64k and 64m have a data structure in which the first to third areas are repeated in the order of the first area → the second area → the third area. It has become. The first to third areas are 1-byte areas. The first area is an area in which data for clearing "0" or data for initial setting is set in the upper 4 bits and the lower 4 bits. For example, as shown in FIG. 18A, the initial value “5” is set in the fraudulent radio wave detection counter 133 for the upper 4 bits of the first area corresponding to the address of “9400H” in the first initialization table 64k. Initial setting data ("0101B") for setting is set, and initial setting data for setting "10", which is an initial value, in the fraudulent magnetism detection counter 134 in the lower 4 bits of the first area. ("1010B") is set. Further, as shown in FIG. 18B, the upper 4 bits of the first area corresponding to the address of "9406H" in the second initialization table 64m are "0" for clearing the power failure area 131 by "0". Clear data ("0000B") is set, and "0" clear data ("0000B") for clearing the lower 1 byte of the fraud monitoring timer counter 132 by "0" is set in the lower 4 bits of the first area. ) Is set.

The second area is an area in which the lower 1 byte of the address that specifies the transfer destination to which the "0" clear data or the initial setting data set in the upper 4 bits of the immediately preceding 1st area is set is set. .. For example, as shown in FIG. 18A, the second area corresponding to the address of “9401H” in the first initialization table 64k is the lower 1 byte (“0021H”) of the address (“0021H”) of the fraudulent radio wave detection counter 133. 21H ") is set. Further, as shown in FIG. 18B, the lower 1 byte (“01H”) in the address (“0001H”) of the power failure area 131 is in the second area corresponding to the address of “9407H” in the second initialization table 64m. ) Is set.

The third area is an area in which the lower 1 byte of the address that specifies the transfer destination to which the "0" clear data or the initial setting data set in the lower 4 bits of the immediately preceding 1st area is set is set. .. For example, as shown in FIG. 18A, the third area corresponding to the address of “9402H” in the first initialization table 64k is the lower 1 byte (“0022H”) of the address (“0022H”) of the fraudulent magnetic detection counter 134. 22H ") is set. Further, as shown in FIG. 18B, the third area corresponding to the address of "9408H" in the second initialization table 64m is the lower 1 in the lower area address ("0008H") of the fraud monitoring timer counter 132. A byte (“08H”) is set.

The final address of each initialization table is the second area or the third area, and the second area or the third area corresponding to the final address is the data setting execution process (FIG. 19 (c)) described later. "00H" is set as the end data. Specifically, as shown in FIGS. 18A and 18B, "9405H" which is the final address of the first initialization table 64k and "940BH" which is the final address of the second initialization table 64m. Is set to "00H", which is the end data.

<LD update order and LDH update order>
Here, the LD update command and the LDH update command included in the data setting execution process will be described prior to the detailed description of the data setting execution process (FIG. 19 (c)).

First, the LD update instruction will be described. The data setting execution process (FIG. 19 (c)) includes an LD update instruction "LDE, (HL +)". As shown in FIG. 9, the main MPU 62 includes an LD update execution circuit 151 which is a dedicated circuit for executing an LD update instruction, and the main CPU 63 can execute the LD update instruction.

The instruction code of the LD update instruction has a configuration of "LD transfer destination, (transfer source +)". In the LD update instruction, a general-purpose register such as the W register 104a or a storage area in the main RAM 65 is set as the “transfer destination”. In the LD update instruction, the HL register 107 is set as the "transfer source". In the LD update instruction, 1 byte of data is loaded into the general-purpose register or storage area of the "transfer destination". A pair register such as WA register 104 is set as the "transfer destination" of the LD update instruction, and when the data capacity of the "transfer destination" is 2 bytes in the LD update instruction, the "transfer destination" is set to 2. It may be configured to load byte data. Further, the WA register 104, the BC register 105, or the DE register 106 may be set as the "transfer source" of the LD update instruction.

The LD update instruction is a process of loading the data stored in the area corresponding to the address stored in the register of the "transfer source" to the "transfer destination", and the process of loading the data into the register of the "transfer source" after the execution of the process. It is an instruction that can execute the process of adding "1" to the stored address and updating the address with one instruction. For example, when "LDE, (HL +)" is executed, the data stored in the area corresponding to the address stored in the HL register 107 set as the "transfer source" is the "transfer destination". Is loaded into the E register 106b, and after the loading, "1" is added to the address stored in the HL register 107 to update the address stored in the HL register 107.

By using the LD update instruction, it is compared with the configuration in which the operation instruction for adding "1" to the address stored in the register of the "transfer source" in the LD instruction is executed after the LD instruction is executed. Therefore, the data capacity of the program for updating the address after loading the data can be reduced.

Next, the LDH update instruction will be described. The data setting execution process (FIG. 19 (c)) includes an LDH update instruction "LDH WA, (HL +)". As shown in FIG. 9, the main MPU 62 includes an LDH update execution circuit 152 which is a dedicated circuit for executing the LDH update instruction, and the main CPU 63 can execute the LDH update instruction.

The instruction code of the LDH update instruction has a configuration of "LDH transfer destination, (transfer source +)". In the LDH update instruction, the WA register 104 is set as the "transfer destination" and the HL register 107 is set as the "transfer source".

The LDH update instruction is a WA register 104 in which the upper 4 bits of the 1-byte data stored in the area corresponding to the address stored in the HL register 107 of the "transfer source" is set as the "transfer destination". A process of loading into the lower 4 bits of one of the general-purpose registers (W register 104a) and masking the upper 4 bits of the general-purpose register with "0", and a process of masking the lower 4 bits of the 1-byte data to "transfer destination". , And the lower 4 bits of the other general-purpose register (A register 104b) among the WA registers 104 set in the above, and the upper 4 bits of the general-purpose register are masked with "0", and the execution of these processes It is an instruction that can execute the process of adding "1" to the address stored in the HL register 107 of the "transfer source" and updating the address stored in the HL register 107 with one instruction. ..

19 (a) and 19 (b) are explanatory views for explaining an LDH update instruction by taking "LDH WA, (HL +)" as an example. As shown in FIG. 19A, "100101000000000000B" ("9400H") is stored in the HL register 107. Further, in the main ROM 64, "0101B" is stored in the upper 4 bits of the area corresponding to the address of "9400H", and "1010B" is stored in the lower 4 bits. When "LDH WA, (HL +)" is executed, as shown in FIG. 19B, the lower 4 bits of the W register 104a, which is one of the general-purpose registers of the WA registers 104, are set to "9400H". "0101B", which is the upper 4 bits of the data stored in the area corresponding to the address, is set, and the upper 4 bits of the W register 104a are masked by "0". Further, in the lower 4 bits of the A register 104b, which is the other general-purpose register of the WA register 104, "1010B", which is the lower 4 bits of the data stored in the area corresponding to the address of "9400H", is set. At the same time, the upper 4 bits of the A register 104b are masked with "0". Then, "1" is added to the address stored in the HL register 107, and the address stored in the HL register 107 is updated to "1001010000000001B" ("9401H").

In this way, by using the LDH update instruction, the upper 4-bit data and the lower 4-bit data in the 1-byte area of the main ROM 64 can be read out to different general-purpose registers, and each general-purpose register can be read. The upper 4 bits in the register can be masked with "0". Further, by using the LDH update instruction, the WA register in which the data of the upper 4 bits in the area corresponding to the address stored in the HL register 107 of the "transfer source" is set as the "transfer destination". The process of loading into the lower 4 bits of one of the 104 general-purpose registers (W register 104a) and masking the upper 4 bits of the general-purpose register with "0" and the data of the upper 4 bits in the area "transfer destination". Of the WA registers 104 set in, the process of loading into the lower 4 bits of the other general-purpose register (A register 104b) and masking the upper 4 bits of the general-purpose register with "0", and after executing these processes It is possible to reduce the data capacity of the program for executing the process of adding "1" to the address stored in the HL register 107 of the "transfer source" to update the address.

Next, the program contents of the data setting execution process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 19 (c). As described above, the data setting execution process is called by executing "CALL 4BTS10" at the line number "1003" and the line number "1004" of the power-on setting process (FIG. 17 (c)). Further, the data setting execution process is performed when the "CALL 4BTS10" is executed at the line number "1203" of the clearing setting process (FIG. 22B) described later, and the initialization process for fraud detection described later (FIG. 29). It is also called when "CALL 4BTS10" is executed at the line number "1503" in (b)). As shown in FIG. 19 (c), "1101" to "1109" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

First, a case where the data setting execution process is executed at the line number “1003” of the power-on setting process (FIG. 17 (c)) will be described. 20 (a) to 20 (g) show the D register 106a and the E register 106b when the data setting execution process is executed at the line number "1003" of the power-on setting process (FIG. 17 (c)). It is explanatory drawing for demonstrating the state of W register 104a, A register 104b, and HL register 107.

As described above, in the row number "1003", the start address "9400H" of the first initialization table 64k is stored in the HL register 107, and the fraudulent radio wave detection counter 133, the fraudulent magnetic detection counter 134, and the abnormality are stored. The data setting execution process is executed in a state where the upper 1 byte (“00H”) common to the address data of the vibration detection counter 135 is stored in the D register 106a (see FIG. 20A).

In the data setting execution process executed by the line number "1003", first, the data set in the address range of "9400H" to "9402H" in the first initialization table 64k (FIG. 18A) is used. The instructions of the line numbers "1102" to "1109" are executed. As already described with reference to FIG. 18A, the upper 4 bits of the first area corresponding to 9400H, which is the start address of the first initialization table 64k, have the initial value "5" in the fraudulent radio wave detection counter 133. "0101B" is set as the initial setting data for setting "", and the initial setting for setting the initial value "10" in the fraudulent magnetic detection counter 134 in the lower 4 bits of the first area. "1010B" is set as the data. In the second area corresponding to "9401H" following "9400H", "21H", which is the lower 1 byte of the address of the fraudulent radio wave detection counter 133, is set. Further, in the third area corresponding to "9402H" following "9401H", "22H", which is the lower 1 byte of the address of the fraudulent magnetism detection counter 134, is set.

As shown in FIG. 19 (c), "4BTS10" is set for the line number of "1101". This is not an instruction but data that is referred to when the developer of the pachinko machine 10 confirms the program. Therefore, the line number "1101" advances to the line number "1102" without executing any instruction.

The command "LDH WA, (HL +)" is set in the line number of "1102". “LDH” is an LDH update instruction by the LDH update execution circuit 152, and “WA” is a content that specifies the WA register 104 as the transfer destination. Further, "(HL +)" is a content that specifies the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source, and the value of the HL register 107 is set to 1 after the data is loaded. It is a content instructing to add and update the address stored in the HL register 107. As described above, in the first initialization table 64k, "0101B" is set as the initial setting data in the upper 4 bits of the first area corresponding to "9400H", and the lower 4 bits of the first area are set. "1010B" is set as the initial setting data. Therefore, by executing "LDH WA, (HL +)" at the line number "1102", as shown in FIG. 20B, the lower 4 bits of the W register 104a are the upper 4 bits of the first area. The bit "0101B" is set, and the upper 4 bits of the W register 104a are masked with "0". Further, "1010B", which is the lower 4 bits of the first area, is set in the lower 4 bits of the A register 104b, and the upper 4 bits of the A register 104b are masked by "0". As a result, the data "00000011B" for the initial setting of the fraudulent radio wave detection counter 133 can be stored in the W register 104a, and the "10001011B" for the initial setting of the fraudulent magnetic detection counter 134 can be stored in the A register 104b. It is possible to set the state in which the data "000001010B" is stored. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9401H".

In this way, by using the LDH update instruction, the data set in the upper 4 bits of the first area is set in the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are set to "0". The process of masking with "0", the process of setting the data set in the lower 4 bits of the first area to the lower 4 bits of the A register 104b, and the process of masking the upper 4 bits of the A register 104b with "0", and HL. The process of adding 1 to the value of the register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these three processes.

As shown in FIG. 19 (c), the command "LDE, (HL +)" is set in the line number of "1103". “LD” is an LD update instruction by the LD update execution circuit 151, and “E” is a content that specifies the E register 106b as the transfer destination. Further, "(HL +)" is a content that specifies the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source, and the value of the HL register 107 is set to 1 after the data is loaded. It is a content instructing to add and update the address stored in the HL register 107. As described above, in the second area corresponding to "9401H" in the first initialization table 64k, "21H", which is the lower 1 byte in the address of the fraudulent radio wave detection counter 133, is set. By executing "LDE, (HL +)" at the line number "1103", "21H" is stored in the E register 106b as shown in FIG. 20 (c). As a result, the address "0021H" of the fraudulent radio wave detection counter 133 can be stored in the DE register 106. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9402H".

In this way, by using the LD update instruction (“LD E, (HL +)”), the process of loading the data set in the second area of the first initialization table 64k into the E register 106b and the HL. The process of adding 1 to the value of the register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

As shown in FIG. 19 (c), the instruction "RET Z" is set in the line number of "1104". "RET Z" in the line number "1104" ends the data setting execution process when the end data of the data setting execution process (FIG. 19 (c)) is set in the E register 106b, and also ends the data setting execution process. If the end data is not set in the E register 106b, this is an instruction instructing to proceed to the next line number. As described above, in the present embodiment, "00H" is set as the end data of the data setting execution process. As shown in FIG. 20 (c), since "21H" is set in the E register 106b and the end data is not set, the process proceeds to the line number "1105".

As shown in FIG. 19 (c), the instruction "LD (DE), W" is set in the line number of "1105". "LD" is an LD instruction, "(DE)" is a content that specifies an area corresponding to an address stored in the DE register 106 as a transfer destination, and "W" specifies a W register 104a as a transfer source. It is the content to be done. As described above, the DE register 106 stores the address “0021H” of the fraudulent radio wave detection counter 133, and the W register 104a stores the data “000000101B” for initial setting. Therefore, by executing "LD (DE), W" at the line number "1105", the data for the initial setting is loaded into the fraudulent radio wave detection counter 133. As a result, the initial value "5" can be set in the fraudulent radio wave detection counter 133.

In this way, the first initialization is performed by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance to specify the address of the fraudulent radio wave detection counter 133. The address data stored in the table 64k can be only the lower 1 byte in the address data (2 bytes) of the fraudulent radio wave detection counter 133. Therefore, the data capacity of the first initialization table 64k can be reduced as compared with the configuration in which the entire address data (2 bytes) in the fraudulent radio wave detection counter 133 is stored in the first initialization table 64k.

As shown in FIG. 19 (c), the line number of "1106" is set with the instruction "LDE, (HL +)" as in the line number of "1103". As shown in FIG. 20 (c), "9402H" is stored in the HL register 107. As already described with reference to FIG. 18A, the lower 1 byte “22H” in the address of the fraudulent magnetic detection counter 134 is set in the third area corresponding to “9402H”. By executing "LDE, (HL +)" at the line number "1106", "22H" is loaded into the E register 106b. As a result, the DE register 106 can be in a state in which "0022H", which is the address of the fraudulent magnetism detection counter 134, is stored. Further, as shown in FIG. 20 (d), the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated to "9403H".

In this way, by using the LD update instruction (“LD E, (HL +)”), the process of loading the data set in the third area of the first initialization table 64k into the E register 106b and the HL. The process of adding 1 to the value of the register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

As shown in FIG. 19 (c), the line number of "1107" is set with the instruction "RET Z" as in the line number of "1104". The "RET Z" in the line number "1107" is the end data ("00H") of the data setting execution process (FIG. 19 (c)) in the E register 106b, similarly to the "RET Z" in the line number "1104". ) Is set, this data setting execution process is terminated, and if the termination data is not set in the E register 106b, it is an instruction to proceed to the next line number. As shown in FIG. 20D, since "22H" is set in the E register 106b and the end data is not set, the process proceeds to the line number "1108".

As shown in FIG. 19 (c), the instruction "LD (DE), A" is set in the line number of "1108". "LD" is an LD instruction, "(DE)" is a content that specifies an area corresponding to an address stored in the DE register 106 as a transfer destination, and "A" specifies an A register 104b as a transfer source. It is the content to be done. As described above, the DE register 106 stores the address “0022H” of the illicit magnetic detection counter 134, and the A register 104b stores the data “000001010B” for initial setting. Therefore, when "LD (DE), A" is executed at the line number "1108", the data for the initial setting is loaded into the fraudulent magnetism detection counter 134. As a result, "10" can be set as the initial value in the fraudulent magnetism detection counter 134.

In this way, the first initialization is performed by configuring the configuration in which the address of the fraudulent magnetism detection counter 134 is specified by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in the table 64k can be only the lower 1 byte in the address data (2 bytes) of the fraudulent magnetism detection counter 134. Therefore, the data capacity of the first initialization table 64k can be reduced as compared with the configuration in which the entire address data (2 bytes) of the fraudulent magnetism detection counter 134 is stored in the first initialization table 64k.

As shown in FIG. 19 (c), the instruction "JR 4BTS10" is set in the line number of "1109". "JR" is a JR instruction as an unconditional jump instruction, and "4BTS10" is a content for designating a start address of data setting execution processing as a jump destination. When "JR 4BTS10" is executed, the process proceeds to the line number "1101" of this data setting execution process.

After that, the instructions of line numbers "1102" to "1109" are executed using the data set in the address range of "9403H" to "9405H" in the first initialization table 64k (FIG. 18A). To. As shown in FIG. 18A, initial setting data for setting “15” as an initial value in the abnormal vibration detection counter 135 in the upper 4 bits of the first area corresponding to “9403H” following “9402H”. "1111B" is set as. Further, "0000B" is set as adjustment data that is not used in the lower 4 bits of the first area. In the second area corresponding to "9404H" following "9403H", "23H", which is the lower 1 byte of the address of the abnormal vibration detection counter 135, is set. Further, "00H" is set as end data in the third area corresponding to "9405H" following "9404H".

Returning to the description of the data setting execution process (FIG. 19 (c)), the line number “1101” proceeds to the line number “1102” without executing any instruction. As described above, in the first initialization table 64k, the initial setting data (“1111B”) is set in the upper 4 bits of the first area corresponding to the address of 9403H, and the adjustment data is set in the lower 4 bits. ("0000B") is set. By executing "LDH WA, (HL +)" at the line number "1102", as shown in FIG. 20 (e), the lower 4 bits of the W register 104a are the upper 4 bits of the first area. “1111B” is set, and the upper 4 bits of the W register 104a are masked with “0”. Further, the lower 4 bits of the A register 104b are set to "0000B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "00001111B" for initial setting can be stored in the W register 104a. The A register 104b is in a state in which "0000000000B" for adjustment is stored. Further, 1 is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9404H".

As described above, in the second area corresponding to "9404H" in the first initialization table 64k, "23H", which is the lower 1 byte of the address corresponding to the abnormal vibration detection counter 135, is set. By executing "LDE, (HL +)" at the line number "1103", "23H" is stored in the E register 106b as shown in FIG. 20 (f). As a result, the address "0023H" of the abnormal vibration detection counter 135 can be stored in the DE register 106. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9405H".

Although "RET Z" is set in the following line number "1104", "23H" is set in the E register 106b as shown in FIG. 20 (f), and the end data ("00H"). Is not set. Therefore, the process proceeds to line number "1105".

As described above, the DE register 106 stores the address “0023H” of the abnormal vibration detection counter 135, and the W register 104a stores the data “000011111B” for initial setting. Therefore, when "LD (DE), W" is executed at the line number "1105", the data for the initial setting is loaded into the abnormal vibration detection counter 135. As a result, "15" can be set as the initial value in the abnormal vibration detection counter 135.

In this way, the first initialization is performed by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance to specify the address of the abnormal vibration detection counter 135. The address data stored in the table 64k can be only the lower 1 byte in the address data (2 bytes) of the abnormal vibration detection counter 135. Therefore, the data capacity of the first initialization table 64k can be reduced as compared with the configuration in which the entire address data (2 bytes) of the abnormal vibration detection counter 135 is stored in the first initialization table 64k.

As described above, the end data "00H" is set in the third area corresponding to "9405H". By executing "LDE, (HL +)" at the line number "1106", "00H" is loaded into the E register 106b as shown in FIG. 20 (g). Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9406H". As a result, the start address of the second initialization table 64m can be stored in the HL register 107.

After that, in a state where the end data (“00H”) is set in the E register 106b, “RET Z” is executed at the line number “1107”, so that the data setting process ends. As described above, when the data setting execution process is completed at the line number “1003” of the power-on setting process (FIG. 17 (c)), the process proceeds to the line number “1004”.

Next, a case where the data setting execution process (FIG. 19 (c)) is executed at the line number “1004” of the power-on setting process (FIG. 17 (c)) will be described in detail. In the line number "1004", "9406H" which is the start address of the second initialization table 64m is stored in the HL register 107, and the power failure area 131, the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer counter 132. The data setting execution process is executed in a state where the upper 1-byte data (“00H”) common to the addresses in the upper area of is stored in the D register 106a.

In the data setting process executed by the line number "1004", first, the data set in the address range of "9406H" to "9408H" in the second initialization table 64m is used to use the line numbers "1102" to "1102". The command of "1109" is executed. As already described with reference to FIG. 18B, in order to clear the power failure area 131 to "0" in the upper 4 bits of the first area corresponding to the start address "9406H" of the second initialization table 64m. "0000B" is set as the data of, and "0000B" is set as the "0" clear data for clearing the lower area of the fraud monitoring timer counter 132 to "0" in the lower 4 bits of the first area. Has been done. In the second area corresponding to "9407H" following "9406H", "01H", which is the lower 1 byte of the address of the power failure area 131, is set. Further, in the third area corresponding to "9408H" following "9407H", "08H", which is the lower 1 byte of the address corresponding to the lower area of the fraud monitoring timer counter 132, is set.

In the line number "1101" of the data setting execution process (FIG. 19 (c)), as described above, the process proceeds to the line number "1102" without executing any instruction. As described above, in the second initialization table 64m, "0" clear data ("0000B") is set in the upper 4 bits and the lower 4 bits of the first area corresponding to "9406H". Therefore, by executing "LDH WA, (HL +)", "0000B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the W register 104a is set. The upper 4 bits are masked with "0". Further, the lower 4 bits of the A register 104b are set to "0000B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "0000000000B" for clearing "0" can be stored in the W register 104a and the A register 104b. Further, the value of the HL register 107 is added by "1", and the address stored in the HL register 107 is updated to "9407H".

As described above, "00H" is stored in the D register 106a. Further, as described above, in the second area corresponding to "9407H" in the second initialization table 64m, "01H", which is the lower 1 byte in the address of the power failure area 131, is set. By executing "LDE, (HL +)" at the line number "1103", "01H" is stored in the E register 106b. As a result, the address "0001H" of the power failure area 131 can be stored in the DE register 106. Further, the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated to "9408H".

"RET Z" is set in the following line number "1104", but "01H" is set in the E register 106b in the immediately preceding line number "1103", and the end data ("00H"). Is not set, so the process proceeds to line number "1105".

As described above, the DE register 106 stores the address “0001H” of the power failure area 131, and the W register 104a stores the data “0000000000B” for clearing “0”. Therefore, when "LD (DE), W" is executed at the line number "1105", the data for clearing the "0" is loaded in the power failure area 131, and the power failure area 131 clears "0". Will be done. As described above, the power failure flag 131a is provided in the least significant bit of the power failure area 131. Therefore, the power failure flag 131a can be cleared by "0" by clearing the power failure area 131 by "0".

In this way, the second initialization table 64m (Fig.) Is configured to specify the address of the power failure area 131 by using the common upper 1 byte (“00H”) stored in the D register 106a in advance. The address data stored in 18 (b)) can be only the lower 1 byte in the address data (2 bytes) of the power failure area 131. Therefore, the data capacity of the second initialization table 64m can be reduced as compared with the configuration in which the entire address data (2 bytes) of the power failure area 131 is stored in the second initialization table 64m.

As described above, "00H" is set in the D register 106a. Further, as described above, in the third area corresponding to "9408H", "08H", which is the lower 1 byte in the address of the lower area of the fraud monitoring timer counter 132, is set. By executing "LDE, (HL +)" at the line number "1106", "08H" is loaded into the E register 106b. As a result, the DE register 106 can be in a state in which "0008H", which is the address of the lower area of the fraud monitoring timer counter 132, is stored. Further, the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated to "9409H".

"RET Z" is set in the following line number "1107", but "08H" is set in the E register 106b in the immediately preceding line number "1106", and the end data ("00H"). Is not set, so the process proceeds to line number "1108".

As described above, the DE register 106 stores "0008H", which is the address of the lower area of the fraud monitoring timer counter 132, and the A register 104b contains "0000000000B", which is the data for clearing "0". It is stored. Therefore, when "LD (DE), A" is executed at the line number "1108", the data for clearing "0" is loaded in the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer The lower area of the counter 132 is cleared to "0".

In this way, the address of the lower area of the fraud monitoring timer counter 132 is specified by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. 2. The address data stored in the initialization table 64m can be only the lower 1 byte in the address data (2 bytes) in the lower area of the fraud monitoring timer counter 132. Therefore, the data capacity of the second initialization table 64m can be reduced as compared with the configuration in which the entire address data (2 bytes) in the lower area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can.

After that, by executing "JR 4BTS10" at the line number "1109", the process proceeds to the line number "1101" of the data setting execution process. Then, this time, the instructions of the line numbers "1102" to "1109" are executed using the data set in the address range of "9409H" to "940BH" of the second initialization table 64m.

As shown in FIG. 18B, "0000B" is used as data for clearing the upper area of the fraud monitoring timer counter 132 to "0" in the upper 4 bits of the first area corresponding to "9409H" following "9408H". Is set. Further, "0000B" is set as adjustment data that is not used in the lower 4 bits of the first area. In the second area corresponding to "940AH" following "9409H", "09H", which is the lower 1 byte of the address ("0009H") corresponding to the upper area of the fraud monitoring timer counter 132, is set. Further, "00H" is set as the end data of the data setting execution process in the third area corresponding to "940BH" following "940AH".

Returning to the description of the data setting execution process (FIG. 19 (c)), the line number “1101” proceeds to the line number “1102” without executing any instruction. As described above, in the second initialization table 64m, data for clearing "0" ("0000B") is set in the upper 4 bits of the first area corresponding to the address of "9409H", and the lower 4 bits are set. The adjustment data (“0000B”) is set in. By executing "LDH WA, (HL +)" at the line number "1102", "0000B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the said The upper 4 bits of the W register 104a are masked with "0". Further, the lower 4 bits of the A register 104b are set to "0000B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "0000000000B" can be stored in the W register 104a and the A register 104b. Further, the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated to "940AH".

As described above, "00H" is set in the D register 106a. Further, as described above, in the second initialization table 64m (FIG. 18B), the second area corresponding to 940AH is the lower 1 byte of the address corresponding to the upper area of the fraud monitoring timer counter 132, "09H". Is set. By executing "LDE, (HL +)" at the line number "1103", "09H" is stored in the E register 106b. As a result, the address "0009H" in the upper area of the fraud monitoring timer counter 132 can be stored in the DE register 106. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "940BH".

"RET Z" is set in the following line number "1104", but "09H" is set in the E register 106b in the immediately preceding line number "1103", and the end data ("00H"). Is not set, so the process proceeds to line number "1105".

As described above, the DE register 106 stores "0009H" which is the address of the upper area of the fraud monitoring timer counter 132, and the W register 104a contains "0000000000B" which is the data for clearing "0". It is stored. Therefore, by executing "LD (DE), W" at the line number "1105", the data for clearing "0" is loaded in the upper area of the fraud monitoring timer counter 132. As a result, the upper area of the fraud monitoring timer counter 132 can be cleared to "0".

In this way, the address of the upper area of the fraud monitoring timer counter 132 is specified by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. 2. The address data stored in the initialization table 64 m (FIG. 18 (b)) can be only the lower 1 byte in the address data (2 bytes) in the upper area of the fraud monitoring timer counter 132. Therefore, the data capacity of the second initialization table 64m can be reduced as compared with the configuration in which the entire address data (2 bytes) in the upper area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can.

As described above, the end data "00H" is set in the third area corresponding to "9405H". By executing "LDE, (HL +)" at the line number "1106", "00H" is loaded into the E register 106b. Further, the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated to "940CH".

After that, in the state where the end data (“00H”) is set in the E register 106b, “RET Z” is executed at the line number “1107”, so that the data setting execution process ends. As described above, when the data setting execution process called by the line number “1004” of the power-on setting process (FIG. 17 (c)) is completed, the process proceeds to the line number “1005”.

Next, the clear correspondence process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 21 (a). The clear correspondence process is executed in step S120 of the main process (FIG. 15). The clear correspondence process is executed by using the program for specific control and the data for specific control.

In the clear correspondence process, first, it is determined whether or not "1" is set in the partial clear flag in the work area 121 for specific control (step S201). As described above, the partial clear flag is a flag that enables the main CPU 63 to grasp that the partial clear process (step S107) has been executed, and is a part of the return command transmission process (step S113). This is a flag that enables the return command at the time of clearing to be transmitted to the sound and light side CPU 93. If an affirmative determination is made in step S201, the partial clear flag is cleared to "0" (step S202).

When a negative determination is made in step S201, it is determined whether or not "1" is set in the all clear flag in the work area 121 for specific control (step S203). As described above, the all clear flag is a flag that enables the main CPU 63 to grasp that the all clear process (step S114) has been executed. If a negative determination is made in step S203, the clearing corresponding process is terminated as it is. On the other hand, when an affirmative determination is made in step S203, all clear flags are cleared to "0" (step S204).

When the process of step S202 is performed or the process of step S204 is performed, the clearing setting process is executed (step S205), and the clearing corresponding process is terminated. In the clearing setting process in step S205, a process for raising the security signal output to the management computer of the game hall from the LOW state to the HI state is executed. The security signal is a signal that enables the management computer of the game hall to grasp that the partial clearing process (step S107) or the complete clearing process (step S114) has been executed in the pachinko machine 10. Further, in the clearing setting process in step S205, a process for making the display corresponding to the disengagement result is performed in the first special figure display unit 37a and the second special figure display unit 37b, and the normal map display is performed. A process for causing the initial display to be performed in the unit 38a is executed. The program contents of the clear setting process will be described later.

FIG. 21B is an explanatory diagram for explaining a storage area in which data is set in the clearing setting process (step S205). As shown in FIG. 21B, in the work area 121 for specific control, the security signal area 153 is provided in the 1-byte area corresponding to the address of "0002H", and corresponds to the address of "0005H". The first special figure display counter 154 is provided in the 1-byte area, and the second special figure display counter 155 is provided in the 1-byte area corresponding to the address of "0006H". A normal map display counter 159 is provided in the corresponding 1-byte area. As described above, the data of the upper 1 byte in the address data of the area and the counter to be set in the clear setting process is common to "00H".

The security signal area 153 is a 1-byte area including the security signal flag 153a. FIG. 21C is an explanatory diagram for explaining the data structure of the security signal area 153. As shown in FIG. 21 (c), the least significant bit (0th bit) in the security signal area 153 is set with the security signal flag 153a, and the 1st to 7th bits in the security signal area 153 are unused. It is a bit of.

The security signal flag 153a is a flag that enables the main CPU 63 to grasp that the above-mentioned security signal should be raised from the LOW state to the HI state. When "1" is set in the security signal flag 153a, the external information setting process (step S517) is executed in the timer interrupt process (FIG. 26) described later, so that the information is output to the management computer of the game hall. The security signal is activated.

The first special figure display counter 154 is a counter in which display data for displaying various patterns is set on the first special figure display unit 37a, and the second special figure display counter 155 is a second special figure display unit. It is a counter in which display data for displaying various patterns is set in 37b. Further, the normal map display counter 159 is a counter in which display data for displaying various patterns is set on the normal map display unit 38a. These display counters 154, 155, 159 are composed of 1 byte, and the display data set in these display counters 154, 155, 159 is 1 byte data.

Next, the clear setting table 64n stored in the main ROM 64 will be described. In the clear setting table 64n, data for raising a security signal when a partial clear process (step S107) or a complete clear process (step S114) is executed, the first special figure display unit 37a, and the first 2 The special figure display unit 37b is set with data for displaying the result corresponding to the deviation result, and the general figure display unit 38a is set with data for performing the initial display. The clear setting table 64n is used in the clear setting process (step S205).

FIG. 22A is an explanatory diagram for explaining the clearing setting table 64n. As shown in FIG. 22A, in the main ROM 64, the clear setting table 64n is set in the address range of "9300H" to "9307H". The clear setting table 64n has the same as the first initialization table 64k and the second initialization table 64m already described with reference to FIGS. 18 (a) and 18 (b), and the first area → the second area →. It is a data structure in which the first to third areas are repeated in the order of the third area.

FIG. 22B is an explanatory diagram for explaining the program contents of the clearing setting process executed by the main CPU 63. The clear setting process is executed in step S205 of the clear correspondence process (FIG. 21 (a)). As shown in FIG. 22 (b), "1201" to "1204" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LDT HL, 300H" is set in the line number of "1201". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "300H" sets 12-bit numerical information of "300H" as a transfer source. The content. As described above, the TP register 111 is set to "9000H", which is the reference address of the data table, in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 300H", "9300H" obtained by adding "9000H" set in the TP register 111 to "300H" set as the transfer source is obtained. It is loaded into the HL register 107. As a result, the start address of the clear setting table 64n (FIG. 22A) can be set in the HL register 107.

In this way, by using the LDT instruction to set the start address of the clear setting table 64n in the HL register 107, the start address of the clear setting table 64n is set in the HL register 107 by using the LD instruction. Compared with the configuration to be set, the data capacity of the program for executing the clear setting process can be reduced.

The line numbers "1202" to "1203" are set with the same instructions as the line numbers "1002" to "1003" in the power-on setting process (FIG. 17 (c)) described above. Specifically, the instruction "XOR D, D" is set in the line number of "1202". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma specifies the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. Will be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As a result, the upper 1-byte data (“00H”) in the address data of the security signal area 153, the first special figure display counter 154, and the second special figure display counter 155 can be set in the D register 106a.

An instruction "CALL 4BTS10" is set in the line number of "1203". “4BTS10” is the data setting execution process (FIG. 19 (c)) already described. The instruction "CALL 4BTS10" is an instruction for calling a subroutine called data setting execution processing. In the line number "1203", the data setting execution process is executed in a state where the start address of the clear setting table 64n is set in the HL register 107 and "00H" is stored in the D register 106a.

An instruction "RET" is set in the line number of "1204". When the command "RET" is executed, the clearing setting process ends. As described above, the clear setting process is a subroutine executed in step S205 of the clear support process (FIG. 21 (a)), and when the clear setting process is completed, the clear support process is also terminated. Will be.

Next, a case where the data setting execution process (FIG. 19 (c)) is executed at the line number “1203” of the clear time setting process (FIG. 22 (b)) will be described. In the line number "1203", "9300H" which is the start address of the clear setting table 64n is stored in the HL register 107, and the security signal area 153, the first special figure display counter 154, and the second special figure display counter are stored. The data setting execution process is executed in a state where the upper 1-byte data (“00H”) in the address data of 155 is stored in the D register 106a.

In the data setting execution process executed by the line number "1203", first, the data set in the address range of "9300H" to "9302H" in the clear setting table 64n is used to use the line numbers "1102" to "". The command of "1109" is executed. As shown in FIG. 22A, in order to set "1" to the security signal flag 153a in the security signal area 153 in the upper 4 bits of the first area corresponding to 9300H which is the start address of the clear setting table 64n. "0001B" is set as the data of the above, and "0011B" is set as the data for setting the display data of the pattern corresponding to the deviation result in the first special figure display counter 154 in the lower 4 bits of the 1 area. It is set. In the second area corresponding to "9301H" following "9300H", "02H", which is the lower 1 byte of the address of the security signal area 153, is set. Further, in the third area corresponding to "9302H" following "9301H", "05H", which is the lower 1 byte of the address of the first special figure display counter 154, is set.

In the line number "1101" of the data setting execution process (FIG. 19 (c)), as described above, the process proceeds to the line number "1102" without executing any instruction. As described above, in the clear setting table 64n, "0001B" is set in the upper 4 bits of the first area corresponding to "9300H", and "0011B" is set in the lower 4 bits. By executing "LDH WA, (HL +)" at the line number "1102", "0001B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the said The upper 4 bits of the W register 104a are masked with "0". Further, the lower 4 bits of the A register 104b are set to "0011B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "00000001B" can be set in the W register 104a, and the data "00000011B" can be set in the A register 104b. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9301H".

As described above, "00H" is stored in the D register 106a. Further, as described above, in the second area corresponding to "9301H" in the clear setting table 64n, "02H", which is the lower 1 byte in the address of the security signal area 153, is set. By executing "LDE, (HL +)" at the line number "1103", "02H" is stored in the E register 106b. As a result, the address "0002H" of the security signal area 153 can be stored in the DE register 106. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9302H".

"RET Z" is set in the following line number "1104", but "02H" is set in the E register 106b in the immediately preceding line number "1103", and the end data ("00H"). Is not set, so the process does not end the data setting execution process, and the process proceeds to the line number "1105".

As described above, the DE register 106 stores "0002H" which is the address of the security signal area 153, and the W register 104a stores "00000001B". Therefore, by executing "LD (DE), W" at the line number "1105", "00000001B" is set in the security signal area 153. As a result, the security signal flag 153a can be set to "1".

In this way, the clear setting table 64n is configured to specify the address of the security signal area 153 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in the security signal area 153 can be limited to the lower 1 byte in the address data (2 bytes) of the security signal area 153. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the security signal area 153 is stored in the clear setting table 64n.

As described above, "00H" is stored in the D register 106a. Further, as described above, in the third area corresponding to "9302H", "05H", which is the lower 1 byte in the address of the first special figure display counter 154, is set. By executing "LDE, (HL +)" at the line number "1106", "05H" is loaded into the E register 106b. As a result, the DE register 106 can be in a state in which "0005H", which is the address of the first special figure display counter 154, is stored. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9303H".

"RET Z" is set in the following line number "1107", but "05H" is set in the E register 106b in the immediately preceding line number "1106", and the end data ("00H"). Is not set, so the process does not end the data setting execution process, and the process proceeds to the line number "1108".

As described above, the DE register 106 stores the address "0005H" of the first special figure display counter 154, and the A register 104b stores the display data "00000011B" for displaying the deviation result. Is stored. Therefore, by executing "LD (DE), A" at the line number "1108", "00000011B" is loaded in the first special figure display counter 154. As a result, it is possible to set the display data of the pattern corresponding to the deviation result in the first special figure display counter 154.

In this way, by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance to specify the address of the first special figure display counter 154, at the time of clearing. The address data stored in the setting table 64n can be only the lower 1 byte in the address data (2 bytes) of the first special figure display counter 154. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the first special figure display counter 154 is stored in the clear setting table 64n.

After that, by executing "JR 4BTS10" at the line number "1109", the process proceeds to the line number "1101" of the data setting execution process. Then, this time, the instructions of the line numbers "1102" to "1109" are executed using the data set in the address range of "9303H" to "9305H" in the clearing setting table 64n.

As shown in FIG. 22A, the second special figure display counter 155 is set to display data of a pattern corresponding to the result of deviation in the upper 4 bits of the first area corresponding to "9303H" following "9302H". "0011B" is set as the data for this purpose. Further, "1010B" is set as data for initial display on the normal map display unit 38a in the lower 4 bits of the 1 area. In the second area corresponding to "9304H" following "9303H", "06H", which is the lower 1 byte of the address of the second special figure display counter 155, is set. Further, in the third area corresponding to "9305H" following "9304H", "07H", which is the lower 1 byte of the address of the normal map display counter 159, is set.

Returning to the description of the data setting execution process (FIG. 19 (c)), the line number “1101” proceeds to the line number “1102” without executing any instruction. As described above, in the clear setting table 64n, "0011B" is set in the upper 4 bits of the first area corresponding to the address of "9303H", and "1010B" is set in the lower 4 bits. .. By executing "LDH WA, (HL +)" at the line number "1102", "0011B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the said The upper 4 bits of the W register 104a are masked with "0". Further, "1001B", which is the lower 4 bits of the first area, is set in the lower 4 bits of the A register 104b, and the upper 4 bits of the A register 104b are masked by "0". As a result, "00000011B", which is the display data of the pattern corresponding to the deviation result, can be set in the W register 104a, and "000001010B", which is the display data for initial display, is set in the A register 104b. Can be done. Further, "1" is added to the address stored in the HL register 107, and the address is updated to "9304H".

As described above, in the second area corresponding to "9304H" in the clear setting table 64n, "16H", which is the lower 1 byte of the address corresponding to the second special figure display counter 155, is set. By executing "LDE, (HL +)" at the line number "1103", "06H" is stored in the E register 106b. As a result, the address "0006H" of the second special figure display counter 155 can be stored in the DE register 106. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9305H".

"RET Z" is set in the following line number "1104", but "06H" is set in the E register 106b in the immediately preceding line number "1103", and the end data ("00H"). Is not set, so the process does not end the data setting execution process, and the process proceeds to the line number "1105".

As described above, the DE register 106 stores the address "0006H" of the second special figure display counter 155, and the W register 104a stores the display data of the pattern corresponding to the disengagement result "00000011B". Is stored. Therefore, by executing "LD (DE), W" at the line number "1105", "00000011B" is loaded in the second special figure display counter 155. As a result, the display data of the pattern corresponding to the deviation result can be set in the second special figure display counter 155.

In this way, by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance to specify the address of the second special figure display counter 155, at the time of clearing. The address data stored in the setting table 64n can be only the lower 1 byte in the address data (2 bytes) of the second special figure display counter 155. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the second special figure display counter 155 is stored in the clear setting table 64n. ..

As described above, "00H" is stored in the D register 106a. Further, as described above, in the third area corresponding to "9305H", "07H", which is the lower 1 byte in the address of the normal figure display counter 159, is set. By executing "LDE, (HL +)" at the line number "1106", "07H" is loaded into the E register 106b. As a result, the DE register 106 can be in a state in which "0007H", which is the address of the normal map display counter 159, is stored. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9306H".

"RET Z" is set in the following line number "1107", but "07H" is set in the E register 106b in the immediately preceding line number "1106", and the end data ("00H"). Is not set, so the process does not end the data setting execution process, and the process proceeds to the line number "1108".

As described above, the DE register 106 stores the address "0007H" of the normal figure display counter 159, and the A register 104b stores the display data "000001010B" for initial display. .. Therefore, by executing "LD (DE), A" at the line number "1108", "000001010B" is loaded in the normal map display counter 159. As a result, display data for initial display can be set in the normal map display counter 159.

In this way, the clear setting table is configured to specify the address of the normal map display counter 159 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in 64n can be only the lower 1 byte in the address data (2 bytes) of the normal figure display counter 159. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the normal figure display counter 159 is stored in the clear setting table 64n.

After that, by executing "JR 4BTS10" at the line number "1109", the process proceeds to the line number "1101" of the data setting execution process. Then, this time, the instructions of the line numbers "1102" to "1104" are executed using the data set in the address range of "9306H" to "9307H" in the clearing setting table 64n.

As shown in FIG. 22A, adjustment data (“0000000000B”) that is not used is set in the first area corresponding to “9306H” following “9305H”. "00H" is set as the end data of the data setting execution process in the second area corresponding to "9307H" following "9306H".

Returning to the description of the data setting execution process (FIG. 19 (c)), the line number “1101” proceeds to the line number “1102” without executing any instruction. As described above, "0000000000B" is set in the first area corresponding to the address of "9306H" in the clear setting table 64n. By executing "LDH WA, (HL +)" at the line number "1102", "0000B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the said The upper 4 bits of the W register 104a are masked with "0". Further, the lower 4 bits of the A register 104b are set to "0000B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". Further, "1" is added to the address stored in the HL register 107, and the address is updated to "9307H".

As described above, the end data ("00H") is set in the second area corresponding to "9307H" in the clearing setting table 64n. By executing "LDE, (HL +)" at the line number "1103", "00H" is loaded into the E register 106b. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9308H".

After that, in the state where the end data is set in the E register 106b, "RET Z" is executed at the line number "1104", so that the data setting execution process ends. As described above, when the data setting execution process is completed at the line number “1203” of the clear setting process (FIG. 22 (b)), the process proceeds to the line number “1204”.

Next, prior to the description of the random number maximum value setting process executed in step S119 of the main process (FIG. 15), the random number maximum value table 64p stored in the main ROM 64 will be described. As described above, in the random number maximum value setting process, the maximum values of the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the variable type counter C5, and the general electric random number counter C6 are set. The random number maximum value table 64p is a data table used for setting maximum value data in the maximum value counters CN1 to CN6 corresponding to these counters C1 to C6.

FIG. 23A is an explanatory diagram for explaining the data structure of the random number maximum value table 64p. As shown in FIG. 23A, the random number maximum value table 64p is stored in the address range of "9200H" to "9208H" in the main ROM 64. In the area corresponding to "9200H" in the random number maximum value table 64p, "63H" ("99"), which is the maximum value data of the jackpot type counter C2, is set. As described above, the maximum value of the jackpot type counter C2 is set in the jackpot type maximum value counter CN2.

In the area corresponding to "9201H" following "9200H", "EEH" ("238"), which is the maximum value data of the reach random number counter C3, is set. As described above, the maximum value of the reach random number counter C3 is set in the reach maximum value counter CN3. In the area corresponding to "9202H" following "9201H", "C6H" ("198"), which is the maximum value data of the variation type counter C5, is set. As described above, the maximum value of the variation type counter C5 is set in the variation type maximum value counter CN5. In the area corresponding to "9203H" following "9202H", "FAH" ("250"), which is the maximum value data of the general electric random number counter C6, is set. As described above, the maximum value of the general electric random number counter C6 is set in the general electric maximum value counter CN6.

In the area corresponding to "9204H" following "9203H", "3FH" which is the lower 1 byte of "1F3FH" ("7999") which is the maximum value data of the hit random number counter C1 is set, and "3FH" is set. In the area corresponding to "9205H", "1FH", which is the upper 1 byte of the maximum value data, is set. As described above, the maximum value of the winning random number counter C1 is set in the winning maximum value counter CN1. Specifically, "3FH", which is the lower 1 byte of the maximum value data, is set in the lower area of the hit maximum value counter CN1, and the upper area of the maximum value data is in the upper area of the hit maximum value counter CN1. One byte, "1FH", is set. In the area corresponding to "9206H" following "9205H", "3FH" which is the lower 1 byte of "1F3FH" ("7999") which is the maximum value data of the random number initial value counter C4 is set, and is also set. In "9207H", "1FH", which is the upper 1 byte of the maximum value data, is set. As described above, the maximum value of the random number initial value counter C4 is set in the initial value maximum value counter CN4. Specifically, "3FH", which is the lower 1 byte of the maximum value data, is set in the lower area of the maximum value counter CN4 for the initial value, and the maximum value data is set in the upper area of the maximum value counter CN4 for the initial value. "1FH", which is the upper 1 byte of, is set. In the area corresponding to "9208H" following "9207H", "00H" is set as end data.

In the random number maximum value setting process (step S119), "9200H", which is the start address of the random number maximum value table 64p, is set in the HL register 107. As a result, the maximum value data of the jackpot type counter C2 is selected as the maximum value data to be set. In the random number maximum value table 64p, the value of the HL register 107 is added by 1 and the address data stored in the HL register 107 is updated in order, so that the maximum value data of the jackpot type counter C2 → the maximum of the reach random number counter C3. Value data → Maximum value data of fluctuation type counter C5 → Maximum value data of Fuden random number counter C6 → Lower 1 byte of maximum value data of hit random number counter C1 → Upper 1 byte of maximum value data of hit random number counter C1 → Initial random number The data configuration is such that the maximum value data to be set can be updated in the order of the lower 1 byte of the maximum value data of the value counter C4 → the upper 1 byte of the maximum value data of the random number initial value counter C4.

As already described with reference to FIG. 12B, the maximum value counters CN1 to CN6 are set in the address range of "0019H" to "0020H" in the work area 121 for specific control. In the random number maximum value setting process (step S119), "0019H", which is the start address of the address range, is set in the BC register 105. As a result, the jackpot type maximum value counter CN2 is selected as the setting target counter. In the work area 121 for specific control, the maximum value counters CN1 to CN6 add 1 to the value of the BC register 105 and update the address data stored in the BC register 105 in order, so that the maximum value for the jackpot type is used. Counter CN2 → Maximum value counter for reach CN3 → Maximum value counter for variation type CN5 → Maximum value counter for general electric power CN6 → Maximum value counter for hits CN1 lower area → Maximum value counter for hits CN1 upper area → Maximum for initial value The setting target counter is set in an order in which the lower area of the value counter CN4 → the upper area of the maximum value counter CN4 for the initial value can be updated.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 23 (b). The random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed by using the program for specific control and the data for specific control.

In the random number maximum value setting process, first, the maximum value setting start process is executed (step S301). In the maximum value setting start processing, "9200H" which is the start address of the random number maximum value table 64p is set in the HL register 107, and "0019H" which is the address of the maximum value counter CN2 for the jackpot type in the work area 121 for specific control. Is set in the BC register 105. In the random number maximum value setting process, the address corresponding to the maximum value data to be set in the random number maximum value table 64p is set in the HL register 107, and the maximum value data to be set is set in the BC register 105. The address corresponding to the set target counter is set. By setting "9200H" in the HL register 107, the maximum value data of the jackpot type counter C2 is selected as the maximum value data to be set. The update of the maximum value data to be set is executed in step S302 described later. Further, by setting "0019H" in the BC register 105, the jackpot type maximum value counter CN2 is selected as the setting target counter. The update of the setting target counter is executed in the setting target update process (step S305) described later. The details of the maximum value setting start processing will be described later.

After executing the maximum value setting start process in step S301, the instruction "LDA, (HL +)" is executed (step S302). "LD" is an LD update instruction by the LD update execution circuit 151, "A" is a content for designating the A register 104b as a transfer destination, and "(HL +)" is stored in the HL register 107 as a transfer source. The content specifies the maximum value data stored in the area corresponding to the address, and after loading the maximum value data, the value of the HL register 107 is added by 1 to update the address stored in the HL register 107. It is the content to instruct to do. By executing "LD A, (HL +)", the maximum value data ("63H") corresponding to the address data ("9200H") stored in the HL register 107 is loaded into the A register 104b. As a result, the maximum value data to be set can be set in the A register 104b. Further, after loading the maximum value data, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9201H". As a result, the maximum value data to be set can be updated.

In this way, by using the LD update instruction, the process of loading the maximum value data selected as the setting target in the random number maximum value table 64p into the A register 104b, and the process of loading the maximum value data into the HL register 107. The process of adding 1 to the value and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

The processes of steps S302 to S305 are repeatedly executed until an affirmative determination is made in step S303, which will be described later. Every time the process of step S302 is executed, the maximum value data of the jackpot type counter C2 → the maximum value data of the reach random number counter C3 → the maximum value data of the variation type counter C5 → the maximum value data of the general electric random number counter C6 → the winning random number. Lower 1 byte of the maximum value data of the counter C1 → Higher 1 byte of the maximum value data of the winning random number counter C1 → Lower 1 byte of the maximum value data of the random number initial value counter C4 → Upper 1 of the maximum value data of the random number initial value counter C4 The maximum value data to be set is updated in the order of bytes. Further, when the process of step S302 is executed with the address stored in the HL register 107 updated to "9208H", the end data ("00H") is set in the A register 104b.

After executing the process of step S302, it is determined whether or not the end data (“00H”) is set in the A register 104b (step S303), and the end data is set in the A register 104b. In (step S303: YES), the random number maximum value setting process is terminated.

If a negative determination is made in step S303, the maximum value data setting process is executed (step S304). In the maximum value data setting process, the instruction "LD (BC), A" is executed. "LD" is a load instruction, "(BC)" is a content that specifies a setting target counter corresponding to an address stored in the BC register 105 as a transfer destination, and "A" is an A register 104b as a transfer source. Is the content to specify. By executing "LD (BC), A", the maximum value data stored in the A register 104b is loaded into the counter selected as the setting target counter among the maximum value counters CN1 to CN6. As a result, the maximum value data can be set in the setting target counter.

After that, the setting target update process is executed (step S305). In the setting target update process, the instruction "INC BC" is executed. "INC" is an instruction to add "1" to the addition target, and "BC" is a content to specify the value of the BC register 105 as the addition target. When "INC BC" is executed, "1" is added to the value of the BC register 105. As a result, the maximum value counters CN1 to CN6 selected as the setting target counters are updated. Every time the setting target update process is executed in step S305, the maximum value counter for jackpot type CN2 → maximum value counter for reach CN3 → maximum value counter for variable type CN5 → maximum value counter for general electric power CN6 → maximum value for hit The setting target counter is updated in the order of the lower area of the counter CN1 → the upper area of the hit maximum value counter CN1 → the lower area of the initial value maximum value counter CN4 → the upper area of the initial value maximum value counter CN4.

After executing the setting target update process in step S305, the process returns to step S302, and the processes of steps S302 to S305 are repeated until the end data is stored in the A register 104b and an affirmative determination is made in step S303. Run. Thereby, the maximum value data can be set in the maximum value counters CN1 to CN6.

<1st LDY command>
Next, the first LDY instruction included in the program of the maximum value setting start processing will be described prior to the explanation of the program contents of the maximum value setting start processing (FIG. 24B). FIG. 24A is an explanatory diagram for explaining the data structure of the machine language of the first LDY instruction, and FIG. 24B is an explanatory diagram for explaining the program contents of the maximum value setting start process.

As shown in FIG. 24 (b), the program of the maximum value setting start processing includes the first LDY instruction "LDY BC, 19H". The main CPU 63 can execute the first LDY instruction as a transfer instruction for transferring data. As shown in FIG. 9, the main MPU 62 includes a first LDY execution circuit 156. The first LDY execution circuit 156 is a dedicated circuit for executing the first LDY instruction.

The instruction code of the first LDY instruction has a configuration of "LDY transfer destination, transfer source". In the first LDY instruction, a pair register is set as a "transfer destination". The pair register set as the "forwarding destination" in the first LDY instruction is the WA register 104, the BC register 105, the DE register 106, or the HL register 107. In the first LDY instruction, a 1-byte numerical value (for example, "19H") is set as the "transfer source".

In the first LDY instruction, the 2-byte numerical information obtained by adding the 2-byte numerical information set in the IY register 109 to the 1-byte numerical information set in the "transfer source" is the "transfer destination". Is loaded into the pair register set in. As described above, in the present embodiment, the IY register 109 is set to "0000H" as the specific control reference address at the start of the specific control process, and the non-specific control is set at the start of the non-specific control process. "0300H" is set as the reference address.

By executing "LDY BC, 19H" in a state where "0000H" is set in the IY register 109 in advance, "0019H" is set in the BC register 105 in the same manner as when "LD BC, 0019H" is executed. Is loaded. Further, by executing "LDY BC, 19H" in a state where "0300H" is set in the IY register 109 in advance, the BC register 105 is executed in the same manner as when "LD BC, 0319H" is executed. "0319H" is loaded.

The machine language data structure of the first LDY instruction will be described while exemplifying "LDY BC, 19H" as a specific instruction code of the first LDY instruction. As shown in FIG. 24 (a), the machine language of the first LDY instruction is the same as the machine language of the LD instruction already described with reference to FIG. 17 (b), and the data of the "transfer source" is "transfer destination". The data instructing the user to load the data, the data for specifying the transfer destination in which the BC register 105 is specified as the "transfer destination", and the data for specifying the transfer source in which the "transfer source" is specified are included. In the machine language of the first LDY instruction, the total data capacity of the instruction data and the transfer destination designated data is 2 bytes, and the data capacity of the transfer source designated data is 1 byte. In the case of "LDY HL, 19H", "19H" which is 1-byte numerical information is set as the "transfer source", and "19H" which is the 1-byte numerical information is set in the machine language of the first LDY instruction. It is included as it is as transfer source specified data. As described above, the data capacity of the machine language of the first LDY instruction is 3 bytes in total.

On the other hand, as already described with reference to FIG. 17B, in the machine language of the LD instruction, the total data capacity of the instruction data and the transfer destination designated data is 2 bytes, and the data capacity of the transfer source designated data is. It is 2 bytes. The machine language data capacity of the LD instruction is 4 bytes in total. In this way, when "0000H" is stored in the IY register 109 and the address of the data table stored in the main ROM 64 is loaded into a pair register such as the BC register 105, the LD instruction is used instead. By using the first LDY instruction, the machine language of the instruction for loading the data of the "transfer source" to the "transfer destination" can be reduced by one byte. As a result, the data capacity of the program in the main ROM 64 can be reduced.

Next, the program contents of the maximum value setting start process executed by the main CPU 63 will be described with reference to FIG. 24 (b). The maximum value setting start process is executed in step S301 of the random number maximum value setting process (FIG. 23 (b)). As shown in FIG. 24 (b), "1301" to "1303" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LDT HL, 200H" is set in the line number of "1301". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "200H" sets 12-bit numerical information of "200H" as a transfer source. The content. As described above, the TP register 111 is set to "9000H", which is the reference address of the data table, in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 200H", "9000H" obtained by adding "9000H" set in the TP register 111 to "200H" set as the "transfer source" is added to "9200H". Is loaded into the HL register 107. As a result, the start address of the random number maximum value table 64p (FIG. 23 (a)) can be set in the HL register 107.

In this way, by using the LDT instruction to set the start address of the random number maximum value table 64p in the HL register 107, the LD instruction is used to set the start address of the random number maximum value table 64p in the HL register 107. Compared with the configuration to be set, the data capacity of the program for executing the maximum value setting start process can be reduced.

The command "LDY BC, 19H" is set in the line number of "1302". "LDY" is the first LDY instruction by the first LDY execution circuit 156, "BC" is the content that specifies the BC register 105 as the transfer destination, and "19H" is a 1-byte numerical value of "19H" as the "transfer source". It is the content to set the information. As described above, the IY register 109 is set to "0000H" as the reference address for specific control in step S103 of the main process (FIG. 15). Therefore, by executing "LDY BC, 19H", "0019H" obtained by adding "0000H" set in the IY register 109 to "19H" set as the "transfer source" is added. Is loaded into the BC register 105. As a result, the address of the jackpot type maximum value counter CN2 in the work area 121 for specific control can be set in the BC register 105.

In this way, the address data (2 bytes) of the jackpot type maximum value counter CN2 is set in the BC register 105 by using the first LDY instruction that sets 1 byte of address data and specifies the address. Data capacity of the program for executing the maximum value setting start processing in comparison with the configuration in which the address data is set in the BC register 105 by using the LD instruction that sets the address data of 2 bytes and specifies the address. Can be reduced.

An instruction "RET" is set in the line number of "1303". As described above, the maximum value setting start process is a subroutine executed in step S301 of the random number maximum value setting process (FIG. 23 (b)). Therefore, when the instruction "RET" is executed, the process proceeds to step S302 of the random number maximum value setting process.

Next, the first clearing process performed in the partial clearing process (step S107) and the full clearing process (step S114) will be described. As described above, the first clearing process is a process of clearing the work area 121 for specific control set to the addresses of "0000H" to "02FFH" in the main RAM 65 by "0". As described above, in step S103 of the main process (FIG. 15), the specific control reference address “0000H” is set in the IY register 109. The first clearing process is executed in a state where the specific control reference address is set in the IY register 109. In the first clear process, first, the instruction "LDY HL, 00H" is executed to load "0000H", which is the start address of the work area 121 for specific control, into the HL register 107. After that, by executing the instruction "LD BC, 0300H", the BC register 105 is loaded with "0300H" which is the end address of the first clear processing. After that, the process of clearing the storage area specified by the address stored in the HL register 107 to "0" and the address stored in the HL register 107 until the end address is stored in the HL register 107. Is repeatedly executed by adding 1. Then, when the end address is stored in the HL register 107, the first clear process is terminated.

In the main process (FIG. 15), a partial clear process (step S107) or a complete clear process (step S114) is executed while the specific control reference address is set in the IY register 109. In the first clear process, "0000H", which is the start address of the work area 121 for specific control, can be specified by using the reference address for specific control stored in the IY register 109.

When using the LD instruction, the address data of the start address included in the instruction code of the LD instruction must be the entire 2-byte address data (“0000H”), while when using the first LDY instruction. Can use only the lower 1 byte (“00H”) of the 2-byte address data as the address data included in the instruction code of the first LDY instruction. By using the first LDY instruction (“LDY HL, 00H”) to set the start address (“0000H”) of the work area 121 for specific control in the HL register 107, the LD instruction is used. The data capacity of the program can be reduced as compared with the configuration in which the start address is set in the HL register 107.

Next, the set value update process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The set value update process is executed in step S117 of the main process (FIG. 15). The set value update process is executed by using the program for specific control and the data for specific control.

In the set value update process, first, "1" is set in the set value updating flag provided in the work area 121 for specific control (step S401). The set value updating flag is a flag that enables the main CPU 63 to grasp that the setting value updating process is being executed. The setting value updating flag is cleared to "0" in step S411 described later. After the processing in step S401 is performed, the interrupt enable setting for switching from the state in which the occurrence of the timer interrupt processing is prohibited to the state in which the timer interrupt processing is permitted is set (step S402). Although the details will be described later, the display control of the first to third notification display devices 69a to 69c is executed by the management process in step S518 of the timer interrupt process (FIG. 26). By permitting the generation of the timer interrupt process, it is possible to set the state in which the management process (step S518) is being executed. In the management process, a number corresponding to the value of the set value counter in the work area 121 for specific control is displayed on the third notification display device 69c on condition that "1" is set in the set value updating flag. The display control of the third notification display device 69c is performed so as to be displayed. As described above, the set value counter is a counter for the main CPU 63 to specify which set value the set state of the pachinko machine 10 is. When the value of the set value counter is updated while the setting value updating flag is set to "1", the display of the set value on the third notification display device 69c is also updated. The manager of the game hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c when changing the set value.

After that, "1" is set in the set value counter in the work area 121 for specific control (step S403). As a result, when the setting value update process is executed, the setting value becomes "setting 1" regardless of the setting values up to that point.

After that, on condition that the setting key insertion unit 68a has not been turned off (step S404: NO), it is determined whether or not the update button 68b has been pressed once (step S405). Specifically, it is determined whether or not the signal from the sensor that detects the pressing operation of the update button 68b has switched from the LOW state to the HI state. If a negative determination is made in step S405, the process returns to the process of step S404, and it is determined whether or not the setting key insertion unit 68a is turned off.

When the update button 68b is pressed once (step S405: YES), the value of the set value counter of the work area 121 for specific control is incremented by 1 (step S406). If the value of the set value counter after 1 addition exceeds "6" (step S407: YES), "1" is set in the set value counter (step S408). As a result, each time the update button 68b is pressed once, it is updated to the setting value one step higher, and when the update button 68b is pressed once in the situation of "setting 6", it is set to "setting 1". Will be back.

If a negative determination is made in step S407, or if the process of step S408 is executed, the process returns to step S404, and it is determined whether or not the setting key insertion unit 68a is turned off. If the OFF operation has not been performed (step S404: NO), the processes after step S405 are executed again. On the other hand, when the OFF operation is performed (step S404: YES), an interrupt prohibition setting for prohibiting the occurrence of timer interrupt processing is set (step S409). As a result, the display of the set value on the third notification display device 69c is completed.

After that, the setting value update command transmission process is executed (step S410). In the setting value update command transmission process, the setting value update command is transmitted to the sound light side CPU 93. The set value update command is a command for causing the sound and light side CPU 93 to recognize that the set value update process has been completed, and for the sound and light side CPU 93 to be able to grasp the set value after the update of the pachinko machine 10. The set value update command includes data stored in the set value counter in the work area 121 for specific control. After that, the setting value updating flag in the work area 121 for specific control is cleared to "0" (step S411), and the setting value updating process is terminated.

<Timer interrupt processing>
Next, the timer interrupt processing in the present embodiment executed by the main CPU 63 will be described with reference to the flowchart of FIG. The timer interrupt process is executed periodically (for example, in a cycle of 4 milliseconds) in a situation where the set value update process (step S117) or the residual process (steps S121 to S124) is executed in the main process (FIG. 15). .. The processing of steps S501 to S517 in the timer interrupt processing is executed by using the program for specific control and the data for specific control. Further, among the management processes (FIG. 56 (a)) in step S518, the processes other than the management execution process (step S1603) described later are executed by using the specific control program and the specific control data. The management execution process (step S1603) is executed by using the program for non-specific control and the data for non-specific control.

In the timer interrupt process, first, the power failure information storage process is executed (step S501). In the power failure information storage process, it is monitored whether or not a power failure signal corresponding to the occurrence of a power failure is received from the power failure monitoring board 67, and if the occurrence of a power failure is identified, an infinite loop occurs after the power failure process is executed. Become. In the power failure processing, "1" is set in the power failure flag 131a in the power failure area 131 already described with reference to FIG. 16B, a checksum is calculated, and the calculated checksum is saved.

After that, a fraud detection process for monitoring whether or not a predetermined event set as a monitoring target for fraud has occurred is executed (step S502). In the fraud detection process, the occurrence of an event in which an illegal radio wave is detected, an event in which an illegal magnetism is detected, and an event in which an abnormal vibration is detected is monitored, and the fraud monitoring reference period (specifically, about 262 seconds) is monitored. ), The event in which an illegal radio wave is detected 5 times, the event in which an illegal magnetism is detected 10 times, or the event in which an abnormal vibration is detected 15 times is specified. If this happens, the fraud detection response process is executed. Although the details will be described later, in the fraud detection response process, "1" is set in the game stop flag provided in the work area 121 for specific control. The game stop flag is a flag that enables the main CPU 63 to grasp whether or not the progress of the game is stopped. When the game stop flag is set to "1", the processing of steps S506 to S518 in the timer interrupt processing is not executed, that is, the progress of the game is stopped. The details of the fraud detection process will be described later.

In the following step S503, it is determined whether or not "1" is set in the set value updating flag in the work area 121 for specific control. As described above, the set value updating flag is a flag that enables the main CPU 63 to grasp that the setting value updating process (FIG. 25) is being executed. When "1" is set in the set value updating flag (step S503: YES), that is, when the setting value updating process (FIG. 25) is being executed, the processes of steps S504 to S517 are executed. Without going through, the process proceeds to step S518.

If a negative determination is made in step S503, the first random number update process is executed (step S504). In the first random number update process, a process for updating the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the variable type counter C5, and the general electric random number counter C6 is executed. The first random number update process (step S504) is executed on condition that "1" is not set in the set value updating flag. Therefore, during the execution of the set value update process (FIG. 25), the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, the random number initial value counter C4, the variable type counter C5, and the general electric random number counter C6 are updated. Is not done. As described above, in the main process (FIG. 15), the set value update process (step S117) is executed before the random number maximum value setting process (step S119) is executed. Since the timer interrupt process (FIG. 26) is permitted to occur in step S402 of the set value update process (FIG. 25), the timer interrupt process (FIG. 26) is also executed during the execution of the set value update process. By preventing the counters C1 to C6 from being updated during the execution of the set value update process, the counters C1 to C6 are updated before the random number maximum value setting process (step S119) is executed. Is prevented from being started. The details of the first random number update process will be described later.

In the following step S505, it is determined whether or not the progress of the game is stopped by determining whether or not "1" is set in the game stop flag. When "1" is set in the game stop flag (step S505: YES), the timer interrupt process is terminated without executing the processes of steps S506 to S518. On the other hand, if a negative determination is made in step S505, the processes after step S506 are executed.

In step S506, the port output process is executed. In the port output process, when the output information is set in the previous timer interrupt process, the process for outputting the output corresponding to the output information to the various drive units 32b and 34b is executed. For example, when the information to switch the special electric winning device 32 to the open state is set, the output of the drive signal to the drive unit 32b for the special electric is started, and when the information to switch to the closed state is set. Stops the output of the drive signal. Further, when the information for switching the utility accessory 34a of the second operating port 34 to the open state is set, the output of the drive signal to the drive unit 34b for the utility should be started and the state should be switched to the closed state. If the information is set, the output of the drive signal is stopped.

After that, the reading process is executed (step S507). In the reading process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in future processing.

After that, the ball entry detection process is executed (step S508). In the ball entry detection process, the signals received from the ball entry detection sensors 42a to 49a are read, and based on the read result, the out port 24a, the general winning opening 31, the special electric winning device 32, and the first operating port 33 are read. , The presence or absence of a ball entering the second operating port 34 and the through gate 35 is specified. In the ball entry detection process in step S508, when the fall of the detection signal of the first operation port detection sensor 46a from the HI state to the LOW state is detected, the first operation winning flag in the work area 121 for specific control is set to "1". "Is set. The first operation winning flag is a flag that enables the main CPU 63 to grasp that a game ball has won a prize in the first operating port 33. Further, in the ball entry detection process in step S508, when the fall of the detection signal of the second operation port detection sensor 47a from the HI state to the LOW state is detected, the second operation winning flag in the work area 121 for specific control is set. Set "1". The second operation winning flag is a flag that enables the main CPU 63 to grasp that a game ball has won a prize in the second operating port 34. The main CPU 63 has a first operation port 33 based on the states of the first operation winning flag and the second operation winning flag in the hold information acquisition process in step S901 of the special figure special electric control process (FIG. 30) described later. And whether or not the game ball has won a prize in the second operating port 34 is grasped.

After that, a timer update process for collectively updating the numerical information of a plurality of types of timer counters provided in the work area 121 for specific control is executed (step S509). In this case, the timer counters to which the stored numerical information is subtracted and updated are collectively handled, but both the subtraction type timer counter update and the addition type timer counter update are collectively performed. It may be configured.

After that, a launch control process for controlling the launch of the game ball is executed (step S510). In a situation where the firing operation to the firing operation device 28 is continued, one game ball is launched every 0.6 seconds, which is a predetermined firing cycle. In the following step S511, as the input state monitoring process, the disconnection confirmation of the ball entry detection sensors 42a to 49a and the opening confirmation of the gaming machine main body 12 and the front door frame 14 are confirmed based on the information read in the reading process of step S507. I do.

After that, the special figure special electric control process for performing the execution control of the game times and the execution control of the open / close execution mode is executed (step S512). The details of the special figure special electric control process will be described later. After that, the Fuzu Fuden control process is executed (step S513). In the Fuzu Fuden control process, when a prize has been won in the through gate 35, a process for acquiring the hold information on the Fuzu side is executed, and the hold information on the Fuzu side is stored. In addition, a release determination is made for the reserved information, and further, a process for performing an effect for a normal drawing is executed with the opening determination as an opportunity. Further, based on the result of the opening determination, a process of opening and closing the general electric accessory 34a of the second operating port 34 is executed. In this case, if the support mode is the low frequency support mode, the corresponding process is executed, and if the support mode is the high frequency support mode, the corresponding process is executed. Further, in the case of the open / close execution mode, even if the support mode immediately before that is the high frequency support mode, the low frequency support mode is set.

The work area 121 for specific control is provided with a mode data area including a high frequency support mode flag and an open / close execution mode flag. The mode data area consists of 1 byte. The high-frequency support mode flag is a flag that enables the main CPU 63 to grasp whether or not it is in the high-frequency support mode, and the open / close execution mode flag tells the main CPU 63 whether or not it is in the open / close execution mode. It is a flag that can be grasped. The high frequency support mode flag is set in the 0th bit of the mode data area, and the open / close execution mode flag is set in the 1st bit of the mode data area. The high frequency support mode flag is set to "1" when the open / close execution mode ends regardless of the type of jackpot result that triggered the execution. In the normal power control process (step S513), the main CPU 63 specifies whether or not the high frequency support mode is set based on the state of the high frequency support mode flag, and is based on the state of the open / close execution mode flag. Specify whether or not it is in the open / close execution mode.

After executing the Fuzu-fuden control process in step S513, the display control process is executed (step S514). In the display control process, the increase / decrease number of the first special figure side hold information related to the first special figure display unit 37a is reflected in the first special figure hold display unit 37c based on the processing results of the immediately preceding steps S512 and S513. Output information setting for, output information setting for reflecting the increase / decrease number of the 2nd special figure side hold information related to the 2nd special figure display unit 37b to the 2nd special figure hold display unit 37d, and the normal figure display unit. The output information is set so that the increase / decrease number of the reserved information on the normal map side related to 38a is reflected in the reserved display unit 38b of the normal map. Further, in the display control process in step S514, the output information for updating the display contents of the first special figure display unit 37a and the second special figure display unit 37b based on the processing results of the immediately preceding steps S512 and S513. In addition to making settings, output information for updating the display contents of the normal map display unit 38a is set. Furthermore, in the display control process in step S514, output information for updating the display content of the round display unit 39 is set based on the process result of the immediately preceding step S513. The details of the display control process will be described later.

After that, the contents of the command and the signal received from the payout side CPU 83 are confirmed, and the payout state reception process for performing the process corresponding to the check result is executed (step S515). In addition, a payout output process for setting the prize ball command as an output target is executed (step S516).

After that, the external information setting process is executed (step S517). In the external information setting process, as described above, when "1" is set in the security signal flag 153a in the security signal area 153 (FIG. 21 (c)), it is output to the management computer of the game hall. The process of raising the security signal from the LOW state to the HI state is executed, and the security signal flag 153a is cleared to "0". By raising the security signal, it is possible for the management computer of the game hall to know that the partial clearing process (step S107) or the complete clearing process (step S114) has been executed. Further, in the external information setting process in step S517, the start and end of the output of the external signal are controlled according to the processing results of the various processes executed in the timer interrupt process this time.

When an affirmative determination is made in step S503, or when the process of step S517 is performed, the program of the subroutine corresponding to the management process is executed by the call instruction (step S518). When the management process (step S518) is executed, the program of the subroutine corresponding to the management process set in the program for specific control is executed, but when the program of the subroutine is executed, the program for management is executed. Information for specifying the return address of the timer interrupt processing after the processing is executed is written in the stack area 123 for specific control by a push instruction. Then, when the management process is completed, the information for specifying the return address is read by the pop instruction, and the program returns to the timer interrupt process program indicated by the return address. The details of the management process will be described later.

As described above, when "1" is set in the setting value updating flag in the work area 121 for specific control (step S503: YES), that is, when the setting value updating process (FIG. 25) is being executed. The process of steps S504 to S517 is not executed, while the management process (step S518) is executed. As a result, during the execution of the set value update process (FIG. 25), the third notification is displayed so that the number corresponding to the value of the set value counter in the work area 121 for specific control is displayed on the third notification display device 69c. The display of the display device 69c can be controlled.

Next, the first random number update process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 27 (a). The first random number update process is executed in step S504 of the timer interrupt process (FIG. 26). As described above, in the first random number update process, the jackpot type counter C2, the reach random number counter C3, the variable type counter C5, and the general electric random number counter C6, which are composed of 1 byte, are updated. The first random number update process is executed by using the program for specific control and the data for specific control.

In the first random number update process, it is first determined whether or not "1" is set in the set value updating flag in the work area 121 for specific control (step S601), and "1" is set in the set value updating flag. If it is set (step S601: YES), the first random number update process is terminated without executing the processes after step S602. As described above, during the execution of the set value update process, the jackpot type counter C2, the reach random number counter C3, the variable type counter C5, and the general electric random number counter C6 are not updated.

If a negative determination is made in step S601, the update start setting process is executed (step S602). In the update start setting process, "0011H", which is the address of the jackpot type counter C2, is set in the HL register 107. In the first random number update process, the address of the update target counter is set in the HL register 107. By setting the address of the jackpot type counter C2 in the HL register 107, the jackpot type counter C2 is selected as the update target counter. Further, in the update start setting process in step S602, the address of the maximum value counter CN2 for the jackpot type is set in the BC register 105. In the first random number update process, the address of the counter in which the maximum value of the update target counter is set is set in the BC register 105. The main CPU 63 specifies the current update target counter based on the address data stored in the HL register 107, and sets the maximum value of the update target counter based on the address data stored in the BC register 105. Identify the counter that is being used.

As already described with reference to FIG. 12 (a), in the work area 121 for specific control, the jackpot type counter C2, the reach random number counter C3, the variable type counter C5, and the general electric random number counter C6 are "0011H" to "0014H". The addresses are provided so as to be serial numbers in the address range of "". Therefore, every time the process of adding 1 to the address stored in the HL register 107 and updating it (the process of step S607 described later) is executed, the jackpot type counter C2 → reach random number counter C3 → variable type counter C5 → general The update target counter can be updated in the order of the electric random number counter C6. Further, as already described with reference to FIG. 12 (b), in the work area 121 for specific control, the maximum value counter CN2 for the jackpot type, the maximum value counter CN3 for the reach, the maximum value counter CN5 for the variable type, and the general electric power are used. The maximum value counter CN6 is provided so that the addresses are serial numbers in the address range of "0019H" to "001CH". Therefore, every time the process of adding 1 to the address stored in the BC register 105 and updating it (the process of step S608 described later) is executed, the maximum value counter CN2 for the jackpot type → the maximum value counter CN3 for reach → fluctuation. The counter in which the maximum value of the update target counter is set can be updated in the order of the maximum value counter CN5 for type → the maximum value counter CN6 for general electric power.

FIG. 27B is an explanatory diagram for explaining the program contents of the update start setting process (step S602). As shown in FIG. 27 (b), "1401" to "1403" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LDY HL, 11H" is set in the line number of "1401". "LDY" is the first LDY instruction by the first LDY execution circuit 156, "HL" is the content that specifies the HL register 107 as the transfer destination, and "11H" is a 1-byte numerical value of "11H" as the "transfer source". It is the content to set the information. As described above, the IY register 109 is set to "0000H" as the reference address for specific control in step S103 of the main process (FIG. 15). Therefore, by executing "LDY HL, 11H", "0011H" obtained by adding "0000H" set in the IY register 109 to "11H" set as the "transfer source" is added. Is loaded into the HL register 107. As a result, the address of the jackpot type counter C2 can be set in the HL register 107.

In this way, the address data (2 bytes) of the jackpot type counter C2 is loaded into the HL register 107 by using the first LDY instruction that sets 1 byte of address data and specifies the address, so that 2 bytes are used. Data capacity of the program for executing the update start setting process compared to the configuration in which the address data of the jackpot type counter C2 is loaded into the HL register 107 using the LD instruction that sets the address data of Can be reduced.

The command "LDY BC, 19H" is set in the line number of "1402". "LDY" is the first LDY instruction by the first LDY execution circuit 156, "BC" is the content that specifies the BC register 105 as the transfer destination, and "19H" is a 1-byte numerical value of "19H" as the "transfer source". It is the content to set the information. By executing "LDY BC, 19H", "0019H" obtained by adding "0000H" set in the IY register 109 to "19H" set as the "transfer source" is BC. It is loaded into register 105. As a result, the address of the maximum value counter CN2 for the jackpot type can be set in the BC register 105.

In this way, the address data (2 bytes) of the jackpot type maximum value counter CN2 is loaded into the BC register 105 by using the first LDY instruction that sets 1 byte of address data and specifies the address. The update start setting process is executed in comparison with the configuration in which the address data of the maximum value counter CN2 for the jackpot type is loaded into the BC register 105 by using the LD instruction that sets the address data of 2 bytes and specifies the address. The data capacity of the program for this can be reduced.

An instruction "RET" is set in the line number of "1403". As described above, the update start setting process is a subroutine executed in step S602 of the first random number update process (FIG. 27 (a)). Therefore, when the instruction "RET" is executed, the process proceeds to step S603 of the first random number update process (FIG. 27 (a)).

Returning to the description of the first random number update process (FIG. 27 (a)), after executing the update start setting process in step S602, the first addition process of the update target counter is executed (step S603). In the first addition process of the update target counter, the value of the counter selected as the update target counter among the four counters C2, C3, C5, and C6 is added by 1. Specifically, the value of the update target counter specified by the address stored in the HL register 107 in the work area 121 for specific control is added by 1.

After that, it is determined whether or not the value of the update target counter after 1 addition in step S603 exceeds the maximum value (step S604). As described above, the main CPU 63 can specify the update target counter based on the address stored in the HL register 107, and the maximum value of the update target counter is based on the address stored in the BC register 105. Can be identified. If an affirmative determination is made in step S604, the value of the update target counter is cleared to "0" (step S605).

When a negative determination is made in step S604, or when the process of step S605 is performed, the address data stored in the HL register 107 is the end address of the first random number update process (specifically, "0014H"". ) (Step S606). When a negative determination is made in step S606, the update target counter is updated by adding 1 to the value of the HL register 107 (step S607), and the value of the BC register 105 is added by 1 (step S608). As a result, a counter (four maximum value counters CN2, CN3, CN5, CN6) in which the maximum value of the update target counter after being updated in step S607 is set based on the address stored in the BC register 105. Any of) can be identified.

When the process of step S608 is performed, the process returns to step S603, and the processes of steps S603 to S608 are repeatedly executed until an affirmative determination is made in step S606. As a result, the jackpot type counter C2, the reach random number counter C3, the variable type counter C5, and the general electric random number counter C6 can be updated. If an affirmative determination is made in step S606, the second random number update process is executed (step S609), and the first random number update process is terminated. FIG. 28 is a flowchart showing the second random number update process.

In the second random number update process, first, the value of the HL register 107 is added by 1 (step S701). As a result, the HL register 107 is in a state in which "0015H", which is the address of the lower area of the hit random number counter C1, is stored. After that, the value of the BC register 105 is added by 1 (step S702). As a result, the BC register 105 is in a state in which "001DH", which is the address of the lower area of the hit maximum value counter CN1, is stored.

After that, the second addition process of the update target counter is executed (step S703). In the second addition process, the value of the counter selected as the update target counter among the hit random number counter C1 and the random number initial value counter C4 is added by 1. These counters C1 and C4 are counters consisting of 2 bytes. In the second addition process (step S703) of the update target counter, the value of the 2-byte counter specified by the address stored in the HL register 107 in the work area 121 for specific control is added by 1.

After that, it is determined whether or not the value of the update target counter after 1 addition in step S703 exceeds the maximum value (step S704). As described above, the main CPU 63 can specify the update target counter based on the address stored in the HL register 107, and the maximum value of the update target counter is based on the address stored in the BC register 105. Can be identified. If an affirmative determination is made in step S704, the value of the update target counter is cleared to "0" (step S705).

When a negative determination is made in step S704 or when the process of step S705 is performed, the address data stored in the HL register 107 is the end address of the second random number update process (specifically, "0017H"). ) (Step S706). If a negative determination is made in step S706, the value of the HL register 107 is added by 2 (step S707). As a result, the update target counter can be updated from the random number counter C1 to the random number initial value counter C4 in a state where the address "0017H" of the lower area of the random number initial value counter C4 is stored in the HL register 107. .. After that, the value of the BC register 105 is added by 2 (step S708). As a result, the BC register 105 can be in a state in which "001FH", which is the address of the lower area of the maximum value counter CN4 for the initial value, is stored.

When the process of step S708 is performed, the process returns to step S703 and the processes of steps S703 to S706 are executed. As a result, the value of the random number initial value counter C4 can be updated. After that, an affirmative determination is made in step S706, and the second random number update process is terminated.

Next, the fraud detection process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 29 (a). The fraud detection process is executed in step S502 of the timer interrupt process (FIG. 26). The fraud detection process is executed by using the program for specific control and the data for specific control.

In the fraud detection process, it is first determined whether or not a fraudulent radio wave is detected (step S801). In step S801, an affirmative determination is made when the detection signal received from the fraudulent radio wave detection sensor (not shown) described above is in the HI state. When an affirmative determination is made in step S801, the value of the fraudulent radio wave detection counter 133 in the work area 121 for specific control is decremented by 1 (step S802), and the value of the fraudulent radio wave detection counter 133 after the deduction is 1. It is determined whether or not the result is "0" (step S803). As described above, the fraudulent radio wave detection counter 133 is set to the initial value "5" every time the fraud monitoring reference period (specifically, about 262 seconds) elapses.

When a negative determination is made in step S801 or a negative determination is made in step S803, it is determined whether or not an illegal magnetism is detected (step S804). In step S804, an affirmative determination is made when the detection signal received from the fraudulent magnetic detection sensor (not shown) described above is in the HI state. When an affirmative determination is made in step S804, the value of the fraudulent magnetism detection counter 134 in the work area 121 for specific control is decremented by 1 (step S805), and the value of the fraudulent magnetism detection counter 134 after the deduction is 1. It is determined whether or not the result is "0" (step S806). As described above, the fraudulent magnetic detection counter 134 is set with an initial value of "10" every time the fraud monitoring reference period (specifically, about 262 seconds) elapses.

When a negative determination is made in step S804, or when a negative determination is made in step S806, it is determined whether or not abnormal vibration is detected (step S807). In step S807, an affirmative determination is made when the detection signal received from the abnormal vibration detection sensor (not shown) described above is in the HI state. When an affirmative determination is made in step S807, the value of the abnormal vibration detection counter 135 in the work area 121 for specific control is subtracted by 1 (step S808), and the value of the abnormal vibration detection counter 135 after the subtraction of 1 is set. It is determined whether or not the result is "0" (step S809). As described above, the abnormal vibration detection counter 135 is set to the initial value "15" every time the fraud monitoring reference period (specifically, about 262 seconds) elapses.

If a negative determination is made in step S807, or if a negative determination is made in step S809, the fraud monitoring timer counter 132 is updated (step S810). In the update process, the numerical information stored in the fraud monitoring timer counter 132 in the work area 121 for specific control is read into the IX register 108, and the value of the IX register 108 is added by 1. When the value after the addition of 1 exceeds the maximum value of "65535", the value of the IX register 108 becomes "0" and the carry flag is set to "1". After that, the numerical information stored in the IX register 108 is loaded into the fraud monitoring timer counter 132 by the LD instruction. As a result, the value of the fraud monitoring timer counter 132 is updated. The state of the carry flag does not change even if the LD instruction is executed. Therefore, when the value of the fraud monitoring timer counter 132 after the update becomes "0", that is, when the value of the fraud monitoring timer counter 132 makes one round, the carry flag is set to "1" at the end of the process of step S810. Is set. The value of the fraud monitoring timer counter 132 makes one round in about 262 seconds. The main CPU 63 grasps that it is the timing when the current fraud monitoring reference period ends and the next fraud monitoring reference period starts based on the value of the fraud monitoring timer counter 132 making one round.

After that, in step S810, it is determined whether or not the value of the fraud monitoring timer counter 132 has made one round (step S811). In step S811, it is determined whether or not the carry flag is set to "1", and when the carry flag is set to "1", it is determined that the value of the fraud monitoring timer counter 132 has made one round. When the value of the fraud monitoring timer counter 132 goes around once (step S811: YES), the fraud detection initialization process is executed (step S812), and the fraud detection process ends. In the fraud detection initialization process in step S812, the initial value “5” is set in the fraud radio wave detection counter 133, the fraud magnetic detection counter 134, and the abnormal vibration detection counter 135. In this way, initial values are set in these detection counters 133 to 135 each time the fraud monitoring reference period elapses.

FIG. 29B is an explanatory diagram for explaining the program contents of the initialization process for fraud detection (step S812). As shown in FIG. 29 (b), "1501" to "1504" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LDT HL, 400H" is set in the line number of "1501". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "400H" sets 12-bit numerical information of "400H" as a transfer source. The content. As described above, the TP register 111 is set to "9000H", which is the reference address of the data table, in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 400H", "9400H" obtained by adding "9000H" set in the TP register 111 to "400H" set as the transfer source is obtained. It is loaded into the HL register 107. As a result, the start address of the first initialization table 64k (FIG. 18A) can be set in the HL register 107.

In this way, the start address of the first initialization table 64k is loaded into the HL register 107 by using the LDT instruction that sets the 12-bit numerical information and specifies the address, so that the 2-byte numerical information is used. Data of the program for executing the initialization process for fraud detection in comparison with the configuration in which the start address of the first initialization table 64k is loaded in the HL register 107 using the LD instruction that sets and specifies the address. The capacity can be reduced.

The line numbers "1502" to "1503" are set with the same instructions as the line numbers "1002" to "1003" in the power-on setting process (FIG. 17 (c)). Specifically, the instruction "XOR D, D" is set in the line number of "1502". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma specifies the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. Will be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As a result, the upper 1-byte data (“00H”) common to the address data of the fraudulent radio wave detection counter 133, the fraudulent magnetism detection counter 134, and the abnormal vibration detection counter 135 can be set in the D register 106a.

An instruction "CALL 4BTS10" is set in the line number of "1503". “4BTS10” is the data setting execution process (FIG. 19 (c)) already described. The instruction "CALL 4BTS10" is an instruction for calling a subroutine called data setting execution processing. In the line number "1503", the start address of the first initialization table 64k is set in the HL register 107 and the start address of the first initialization table 64k is set in the HL register 107 as in the line number "1003" of the power-on setting process (FIG. 17 (c)) already described. The data setting execution process is executed with "00H" stored in the D register 106a. By executing the data setting execution process at the line number "1504", the illegal radio wave detection counter 133, the illegal magnetic detection counter 134, and the abnormal vibration detection counter 135 in the work area 121 for specific control have initial values of "5". Is set.

In this way, the fraudulent radio wave detection counter 133 and the fraudulent magnetic detection counter 134 are used by using the data setting execution processing program also used in the power-on setting process (FIG. 17 (c)) and the data in the first initialization table 64k. And by the configuration that initializes the abnormal vibration detection counter 135, it is compared with the configuration that stores the dedicated program and data for initializing these detection counters 133 to 135 in the initialization process for fraud detection. Therefore, the data capacity of the program and data in the main ROM 64 can be reduced.

An instruction "RET" is set in the line number of "1504". When the instruction "RET" is executed, the initialization process for fraud detection is completed. As described above, the fraud detection initialization process is a subroutine executed in step S812 of the fraud detection process (FIG. 29 (a)), and when the fraud detection initialization process is completed, the fraud detection process is completed. Will also end.

Returning to the description of the fraud detection process (FIG. 29 (a)), when the affirmative judgment is made in step S803, when the affirmative judgment is made in step S806, or when the affirmative judgment is made in step S809, the affirmative judgment is made. , The fraud detection response process (process of steps S813 to S814) is executed. Specifically, first, the fraudulent notification command is transmitted to the sound / light side CPU 93 (step S813). The fraudulent notification command is a command for causing the sound and light side CPU 93 to recognize that an abnormal state has been detected by detecting an illegal radio wave, an illegal magnetism, or an abnormal vibration. When the sound and light side CPU 93 receives the fraudulent notification command, the light emission control of the display light emitting unit 53, the sound output control of the speaker unit 54, and the design are performed so that the fraudulent notification for notifying the abnormal state is performed. The display control of the display device 41 is performed. As a result, it is possible to notify the manager of the game hall that an abnormal radio wave, an illegal magnetism, or an abnormal vibration has been detected and an abnormal state has occurred.

After that, "1" is set in the game stop flag in the work area 121 for specific control (step S814), and the fraud detection process is terminated. When the game stop flag is set to "1", the processing of steps S506 to S518 in the timer interrupt processing (FIG. 26) is not executed, and the progress of the game is stopped. The state in which "1" is set in the game stop flag is resolved by executing a partial clear process (step S107) or a complete clear process (step S114) in the main process (FIG. 15).

<Special figure special electric control processing>
Next, the special figure special electric control process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The special figure special electric control process is executed in step S512 in the timer interrupt process (FIG. 26).

In the special figure special electric control process, the process for acquiring the hold information when the first operating port 33 or the second operating port 34 has won a prize is executed, and when the hold information is stored. A pass / fail judgment is made for the reserved information, and a process for performing a game rounding effect is executed with the hit / fail judgment as an opportunity. Based on the result of the hit / fail determination, the process of shifting to the open / close execution mode after the effect for the game round is executed, and the process of the open / close execution mode and the end of the open / close execution mode is executed.

In the special figure special electric control process, first, the hold information acquisition process is executed (step S901). In the hold information acquisition process, the hold information on the special figure side is acquired. Specifically, it is determined whether or not a game ball has been awarded to the first actuating opening 33 based on the state of the first actuating winning flag in the work area 121 for specific control. When a game ball has been won in the first operating port 33, it is stored in the first special figure holding area 115 with reference to the first special figure holding number counter 118 in the special figure holding area 113. When the number of pending information is grasped and the number of pending information is less than the upper limit value (specifically, "4"), each value of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is set. It is stored in the uppermost area of the first special figure holding area 115 where the holding information is not stored. Then, the first operation winning flag is cleared to "0". Further, in the acquisition process, it is determined whether or not the game ball has been awarded to the second actuated opening 34 based on the state of the second actuated winning flag in the work area 121 for specific control. When a game ball has been won in the second operating port 34, it is stored in the second special figure holding area 116 with reference to the second special figure holding number counter 119 in the special figure holding area 113. When the number of pending information is grasped and the number of pending information is less than the upper limit value (specifically, "4"), each value of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is set. It is stored in the uppermost area in the second special figure holding area 116 where the holding information is not stored. Then, the second operation winning flag is cleared to "0".

In the process of acquiring the hold information in step S901, when the hold information for the first special figure hold area 115 or the hold information for the second special figure hold area 116 is acquired, the hold command is transmitted to the sound / light side CPU 93. .. The sound light side CPU 93 transmits a command corresponding to the received hold command to the display control device 89. By receiving the hold command, the display control device 89 changes the display of the number of hold information in the symbol display device 41 in accordance with the increase in the number of hold information. In this case, since the hold command includes information indicating which of the hold information of the first special figure hold area 115 and the second special figure hold area 116 has increased, the symbol display device 41 may use the symbol display device 41. The display of the number of pending items corresponding to the increased side is changed.

Further, when the number of reserved information increases as described above, the first special figure reserved display unit 37c and the second special figure reserved display unit are displayed in the display control process in step S514 of the timer interrupt process (FIG. 26). The display control is performed so that the display content of the 37d corresponding to the increase in the number of holds is changed to the display content corresponding to the increase in the number of holds. The details of the display control process (step S514) will be described later.

After executing the hold information acquisition process in step S901, the special figure special electric address acquisition process is executed (step S902). In the special figure special electric address acquisition process, the information of the special figure special electric counter provided in the work area 121 for specific control is read, and the special figure special electric address table 64q (FIG. 31) stored in the main ROM 64 is read. .. Then, the start address corresponding to the information of the special figure special electric counter is acquired from the special figure special electric address table 64q. The details of the special figure special electric address acquisition process will be described later.

As described above, the special figure special electric control process includes a process for controlling the effect for the game round and a process for controlling the open / close execution mode. In this case, as the process for controlling the effect for the game round, the special figure variation start process (step S904), which is the process for starting the effect for the game round, and the effect for the game round are to proceed. The special figure changing process (step S905), which is the process of the above, and the special figure finalizing process (step S906), which is the process for ending the effect for the game round, are set.

Further, as the process for controlling the open / close execution mode, the special electric start process (step S907), which is the process for controlling the opening of the open / close execution mode, and the process for controlling the open state of the special electric winning device 32. The special electric power opening process (step S908), the special electric power closing process (step S909) which is a process for controlling the closed state of the special electric power winning device 32, and the ending of the open / close execution mode and the end of the open / close execution mode. The special electric termination process (step S910), which is a process for controlling the transition of the gaming state of the above, is set.

In such a processing configuration, the special figure special electric counter is a counter for the main CPU 63 to grasp which of the above-mentioned plurality of types of processing should be executed, and the special figure special electric address table 64q (FIG. In 31), the start address of the program for executing the above-mentioned plurality of types of processing is set in correspondence with the numerical information of the special figure special electric counter.

FIG. 31 is an explanatory diagram for explaining the data structure of the special figure special electric address table 64q. As shown in FIG. 31, the special figure special electric address table 64q is stored in the address range of “9180H” to “918AH” in the main ROM 64.

The start address SA0 is the start address of the program for executing the special figure change start process (step S904), and the start address SA1 is the start address of the program for executing the special figure change process (step S905). Yes, the start address SA2 is the start address of the program for executing the special figure determination process (step S906), and the start address SA3 is the start address of the program for executing the special electric start process (step S907). Yes, the start address SA4 is the start address of the program for executing the special electric power opening process (step S908), and the start address SA5 is the start address of the program for executing the special electric power closing process (step S909). Yes, the start address SA6 is the start address of the program for executing the special electric end processing (step S910).

The address data of these start addresses SA0 to SA6 are 2-byte data, and the upper 4 bits of these start addresses SA0 to SA6 are all "9H". In the special figure special electric address table 64q, only the lower 12 bits excluding the common upper 4 bits (“9H”) from these start addresses SA0 to SA6 are set. Specifically, in the main ROM 64, the lower 4 bit area (hereinafter, also referred to as the lower 4 bit area) of the area corresponding to the address of "9180H" and the area corresponding to the address of "9181H" is the start address. The lower 12 bits ("700H") of SA0 ("9700H") are set, and the upper 4 bit area (hereinafter, also referred to as the upper 4 bit area) and the upper 4 bit area (hereinafter, also referred to as the upper 4 bit area) among the areas corresponding to the address of "9181H". The lower 12 bits (“712H”) of the start address SA1 (“9712H”) are set in the area corresponding to the address of “9182H”. The lower 12 bits ("71FH") of the start address SA2 ("971FH") are set in the area corresponding to the address "9183H" and the lower 4 bit area corresponding to the address "9184H", and "9184H". The lower 12 bits (“731H”) of the start address SA3 (“9731H”) are set in the upper 4 bit area corresponding to the address of “” and the area corresponding to the address of “9185H”. The lower 12 bits ("740H") of the start address SA4 ("9740H") are set in the area corresponding to the address "9186H" and the lower 4 bit area corresponding to the address "9187H", and "9187H". The lower 12 bits (“74CH”) of the start address SA5 (“974CH”) are set in the upper 4 bit area corresponding to the address of “” and the area corresponding to the address of “9188H”. The lower 12 bits ("753H") of the start address SA6 ("9753H") are set in the area corresponding to the address "9189H" and the lower 4 bit area corresponding to the address "918AH", and "918AH". "0000B" is set as adjustment data that is not used in the upper 4-bit area corresponding to the address of "".

The special figure special electric counter controls the special figure special electric power in the next processing time when the condition for updating the numerical information is satisfied when the processing corresponding to the numerical information currently stored is completed. 1 addition, 1 subtraction or "0" is cleared corresponding to the process executed in the process. Therefore, in the special figure special electric control processing in each processing time, it is sufficient to execute the processing according to the numerical information set in the special figure special electric counter. The special figure special electric counter is set to 0 as an initial value.

Returning to the description of the special figure special electric control process (FIG. 30), after executing the process of step S902, the process of jumping to the process indicated by the start address acquired in step S902 is executed in step S903. Specifically, when the acquired start address is SA0, it jumps to the special figure change start process of step S904, and when the acquired start address is SA1, it jumps to the special figure change process in step S905. If the acquired start address is SA2, the process jumps to the special figure determination process in step S906, and if the acquired start address is SA3, the process jumps to the special electric start process in step S907, and the acquired start address is If it is SA4, it jumps to the processing during opening of the special electric power in step S908, if the acquired start address is SA5, it jumps to the processing during closing of the special electric power of step S909, and if the acquired start address is SA6. Jump to the special electric end processing of step S910. When any of the processes of steps S904 to S910 is executed, the special figure special electric control process is terminated. The contents of the processes of steps S904 to S910 will be described later.

<LDB command>
The start addresses SA0 to SA6 corresponding to the value of the special figure special electric counter are acquired in the HL register 107 in the address acquisition execution process (FIG. 33 (e)) described later. In the address acquisition execution process, the LDB instruction "LDB HL, (HL) .A" is executed in order to acquire the start addresses SA0 to SA6. As shown in FIG. 9, the main MPU 62 includes an LDB execution circuit 157 that is a dedicated circuit for executing the LDB instruction, and the main CPU 63 can execute the LDB instruction.

The instruction code of the LDB instruction has a configuration of "LDB transfer destination, acquisition data specification. Acquisition bit number specification". In the LDB instruction, a general-purpose register or a pair register is set as a "transfer destination". The general-purpose register set as the "transfer destination" in the LDB instruction is the W register 104a, and the pair register set as the "transfer destination" in the LDB instruction is the HL register 107. In the LDB instruction, the A register 104b, the B register 105a, the C register 105b, the D register 106a, the E register 106b, the H register 107a, or the L register 107b may be set as the "transfer destination" general-purpose register. Further, the WA register 104, the BC register 105, or the DE register 106 may be set as the pair register of the "transfer destination" in the LDB instruction.

When the 1-byte W register 104a is set as the "transfer destination", data having any number of bits 1 to 8 is set in the W register 104a of the "transfer destination" by the LDB instruction. When data having any number of bits 1 to 7 is set in the W register 104a of the "transfer destination", the data is loaded in the lower bit in the W register 104a and the upper bit in the W register 104a. The bit on the side is masked with "0". For example, when 2-bit data is loaded into the W register 104a of the "transfer destination", the data is loaded into the 0th to 1st bits existing on the lower side of the W register 104a, and the data is loaded on the upper side. The existing 2nd to 7th bits are masked with "0".

When the 2-byte HL register 107 is set as the "transfer destination", the LDB instruction loads the HL register 107 of the "transfer destination" with data having any number of bits 1 to 16. When data having any number of bits 1 to 15 is loaded into the "transfer destination" HL register 107, the data is loaded into the lower bit in the HL register 107 and the upper bit in the HL register 107. The bit on the side is masked with "0". For example, when 12-bit data is loaded into the "transfer destination" HL register 107, the data is loaded into the 0th to 11th bits existing on the lower side of the HL register 107, and the data is loaded on the upper side. The existing 12th to 15th bits are masked with "0".

In the LDB instruction, "(HL)" is set as "acquisition data designation". In the LDB instruction, the data to be transferred to the "transfer destination" register based on the 2-byte data (hereinafter referred to as "acquisition data designation data") stored in the HL register 107 set as "acquisition data designation". The acquisition start address and the acquisition start bit of the are specified.

When the 1-byte W register 104a is set as the "transfer destination", the general-purpose register in which any of the numerical values "0" to "7" is stored is set as the "acquisition bit number specification" in the LDB instruction. Will be done. Further, when the 2-byte HL register 107 is set as the "transfer destination", the general-purpose register in which any numerical value of "0" to "15" is stored as the "acquisition bit number specification" in the LDB instruction. Is set. The general-purpose register set as "designation of the number of acquired bits" in the LDB instruction is the A register 104b. In the LDB instruction, the B register 105a, the C register 105b, the D register 106a, the E register 106b, the H register 107a, or the L register 107b may be set as the general-purpose register for "specifying the number of acquired bits".

The "acquisition bit number designation" is data for designating the number of bits of data to be loaded in the "transfer destination" register (hereinafter, also referred to as acquisition bit number designation data). In the LDB instruction, a process of adding "1" to the value of the A register 104b set in the "specified number of acquisition bits" in the LDB execution circuit 157 to calculate the value obtained is performed, and the calculation result is calculated. The data with the corresponding number of bits is loaded into the "transfer destination". That is, the data of the number of bits corresponding to the value obtained by adding "1" to the "designation of the number of acquired bits" is loaded in the "transfer destination". Therefore, a value obtained by subtracting "1" from the number of bits of data to be loaded in the "transfer destination" is set in the "specified number of acquired bits". For example, when the A register 104b in which the numerical value "1" is stored is set as "Specify the number of acquired bits", "1" is added to the "1" in the "transfer destination" register. 2 bits of data to be loaded. Further, for example, when the A register 104b in which the numerical value "11" is stored is set as the "designation of the number of acquired bits", "1" is added to the "11" in the "transfer destination" register. The obtained 12-bit data is loaded.

When the LDB instruction is executed, the data of the number of bits corresponding to the "specified number of acquisition bits" is loaded into the register of the "transfer destination" from the acquisition start bit of the area corresponding to the acquisition start address in the main ROM 64. ..

32 (a) to 32 (d) are explanatory diagrams for explaining the process of calculating the acquisition start address and the acquisition start bit from the acquisition data designated data. Of the 2-byte acquisition data designation data, the upper 13 bits (3rd to 15th bits) are data for designating the acquisition start address, and the lower 3 bits (0th to 2nd bits) are the acquisition start bits. It is the data to specify. The acquisition start address is the reference address (“9000H” in this embodiment) of the data table stored in the TP register 111 for the quotient when the acquired data specified data is divided by “8” (“1000B”). It is an address calculated as the calculation result of the calculation to be added. "8" ("1000B") used for division of acquired data specified data is a numerical range ("3") represented by the number of bits ("3") of the data for specifying the acquisition start bit among the acquired data specified data. It is a value obtained by adding "1" to "7", which is the maximum value of "0" to "7"), and is the cube of "2". The value obtained by adding "1" to the maximum value in the numerical range represented by the number of bits "n" (n is an integer of 1 to 15) is the nth power of "2". When a 2-byte binary number is divided by the nth power of the "2", the information of "0" or "1" set in the nth to 15th bits of the 2-byte binary number is on the lower side of the n bits. Is set to the lower (16-n) bits in the quotient data after division, and "0" is set in the upper n bits ((16-n) bits to 15th bits) in the quotient data after division. Is set. In the LDB instruction in the present embodiment, the acquired data designation data, which is a 2-byte binary number, is divided by "8" ("1000B"), which is the cube of "2". When the acquired data specified data is divided by "8", the information of "0" or "1" set in the 3rd to 15th bits of the acquired data specified data is shifted to the lower side by 3 bits and after the division. The lower 13 bits (0th to 12th bits) in the quotient data are set, and "0" is set in the upper 3 bits (13th to 15th bits) in the quotient data after the division.

Specifically, as shown in FIG. 32 (a), "0C24H" is set as the acquired data designation data. As shown in FIG. 32 (b), the acquired data designation data (“0C24H”) is obtained by “8” which is the value obtained by adding “1” to “7” which is the maximum value of the numerical range represented by 3 bits. When divided, "0000110000100" set in the 3rd to 15th bits of the acquired data designation data is shifted to the lower side by 3 bits and becomes the lower 13 bits (0th to 12th bits) in the quotient data after division. At the same time, "0" is set in the upper 3 bits (13th to 15th bits) in the quotient data after the division. As a result, the quotient data after division becomes "0000000110000100". After that, as the calculation result of the operation of adding the reference address (“9000H”) of the data table stored in the TP register 111 to the quotient data after the division, “1001000110000100” as shown in FIG. 32 (c). The acquisition start address (“9184H”) is calculated. The twelfth bit in the divided quotient data (FIG. 32 (b)) is "0", and the twelfth bit of "9000H", which is the reference address of the data table, is "1". Further, in the operation of adding the reference address of the data table to the quotient data after division, the carry to the twelfth bit does not occur. Therefore, as shown in FIG. 32 (c), the data of the 3rd to 14th bits in the acquisition data designation data (FIG. 32 (a)) is set in the 0th to 11th bits at the acquisition start address. , "1001B" ("9H"), which is the data of the 12th to 15th bits in the reference address of the data table, is set in the 12th to 15th bits of the acquisition start address.

In this way, the data of the 3rd to 14th bits in the acquisition data designation data is set in the 0th to 11th bits of the acquisition start address, and the TP register 111 is set in the 12th to 15th bits of the acquisition start address. The data of the twelfth to fifteenth bits in the reference address of the data table stored in is set.

The acquisition start bit is calculated by the operation of the logical product of the lower 1 byte of the acquired data designated data and "00000011B" ("07H"). The "000000111B" used in the calculation for calculating the acquisition start bit separates only the lower 3 bits (0th to 2nd bits) of the acquired data specified data from the 2-byte acquisition data specified data. The data is for making the lower 3 bits of the data available independently. In the calculation of the logical product of the lower 1 byte of the acquired data specified data and "000000111B", the data of the lower 3 bits (0th to 2nd bits) in the acquired data specified data is the lower 3 bits (0th to 3rd bits) of the operation result. 2 bits), and "0" is set in the upper 5 bits (3rd to 7th bits) of the calculation result. Specifically, as shown in FIG. 32 (a), when "0C24H" is set as the acquisition data designation data, the acquisition start bit is "001100100B" ("001100B"), which is the lower 1 byte of the acquisition data designation data. By the operation of the logical product of "24H") and "000000111B", it becomes "00000100B" ("4"). As shown in FIG. 32 (d), the data of the 0th to 2nd bits in the acquisition data designation data (FIG. 32 (a)) is set in the 0th to 2nd bits of the acquisition start bit, and the acquisition is performed. "0" is set in the 3rd to 7th bits of the start bit.

No data is set in the instruction code of the LDB instruction to specify that "000000111B" is used in the operation for calculating the acquisition start bit. The operation of the logical product of the lower 1 byte of the acquired data designated data and "000000111B" is automatically executed by the LDB execution circuit 157 when the LDB instruction set in the program is executed. Therefore, the instruction code of the LDB instruction is compared with the configuration in which it is necessary to set data for designating that "000000111B" is used in the operation for calculating the acquisition start bit in the instruction code of the LDB instruction. The data capacity can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

When the acquisition start bit is "n" (n is an integer of 0 to 7), the nth and subsequent bits (nth bit) of the 0th to 7th bits of the area corresponding to the acquisition start address in the main ROM 64 The data of "0" or "1" corresponding to the number of acquired bits set in (7th bit) is transferred to the register of the "transfer destination". When the number of "0" or "1" data existing after the acquisition start bit (nth bit to 7th bit) in the area corresponding to the acquisition start address is less than the number of acquisition bits this time. , The data after the acquisition start bit at the acquisition start address (data in the nth to 7th bits at the acquisition start address) and the data after the 0th bit at the address next to the acquisition start address are "transfer destinations". Loaded into. Here, the address next to the acquisition start address is an address obtained by adding "1" to the acquisition start address.

For example, "9000H" is stored in the TP register 111 as a reference address, "0C24H" ("3108") is stored in the HL register 107 as acquisition data designation data, and the acquisition bit number designation data is stored in the A register 104b. When "LDB HL, (HL) .A" is executed in the state where "BH" (11) is stored, the "transfer destination" becomes the HL register 107. As already explained, the data for specifying the acquisition start address is set in the upper 13 bits of the acquisition data specification data, and the data for specifying the acquisition start bit is in the lower 3 bits of the acquisition data specification data. It is set. The acquisition start address is "9184H" obtained by adding the reference address ("9000H") to "0184H" ("388") obtained by dividing the acquisition data designated data by "8". As the acquisition start bit, the lower 3 bits of the acquisition data designated data are extracted and become "00000100B" ("4"). As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte (“001001100B”) of the acquired data designated data and “000000111H”. The number of acquired bits is "0CH" ("12") obtained by adding "1" to "0BH". Therefore, when "LDB HL, (HL) .A" is executed in this state, the acquisition start bit th in the area corresponding to the acquisition start address "9184H" (see FIG. 31) in the main ROM 64. 4-bit data set after (4th bit) and 8-bit data set after the 0th bit in the area corresponding to "9185H" which is the address next to the acquisition start address. Is set in the 0th to 11th bits of the HL register 107, which is the transfer destination, and the 12th to 15th bits of the HL register 107 are masked with "0". Specifically, the data of the 4th to 7th bits of the area corresponding to "9184H" and the data of the 0th to 7th bits of the area corresponding to "9185H" are set to the 0th to 11th bits of the HL register 107. Set.

32 (e) and 32 (f) are explanatory views for explaining how the start address SA3 is acquired from the special figure special electric address table 64q to the HL register 107. As described above, in the special figure special electric address table 64q (FIG. 31), the lower 12 bits of the start address SA3 are set in the 4th to 7th bits of "9184H" and the 0th to 7th bits of "9185H". ing. By executing "LDB HL, (HL) .A", as shown in FIG. 32 (e), the lower 12 bits of the start address SA3 are loaded into the lower 12 bits of the HL register 107. In the address acquisition execution process (FIG. 33 (e)) described later, after executing the LDB instruction, "9000H", which is the reference address of the data table, is added to the value of the HL register 107. As a result, as shown in FIG. 32 (f), the entire start address SA3 can be acquired in the HL register 107.

By using the LDB instruction, the process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111, and The process of specifying the acquisition start bit corresponding to the lower 3 bits (0th to 2nd bits) of the acquisition designation data, and the data for the number of acquisition bits from the acquisition start bit of the acquisition start address of the "transfer destination". It is possible to execute a process of loading into a register and a process of masking a bit higher than the loaded data in the "transfer destination" register with "0" with one instruction. These processes are executed by the LDB execution circuit 157. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

Next, the program contents of the special figure special electric address acquisition process executed in step S902 of the special figure special electric control process (FIG. 30) will be described with reference to the explanatory diagram of FIG. 33 (a). As shown in FIG. 33 (a), "1601" to "1605" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LD W, (TZTDCNT)" is set in the line number of "1601". “LD” is an LD instruction, and “W” is a content that specifies the W register 104a as a transfer destination. "TZTDCNT" is the address of the special figure special electric counter in the work area 121 for specific control, and "(TZTDNT)" is the content to transfer the data stored in the special figure special electric counter to the "transfer destination". As described above, the special figure special electric counter stores numerical data of any of 0 to 6. By executing "LD W, (TZTDCNT)", the data (1 byte) of the special figure special electric counter is loaded into the W register 104a of the "transfer destination".

The instruction "LD B, 0CH" is set in the line number of "1602". "LD" is an LD instruction, "B" is a content that specifies the B register 105a as a transfer destination, and "0CH" is a content that specifies numerical data of "0CH" ("12") as a "transfer source". Is. “0CH” is the number of bits of the address data acquired from the special figure special electric address table 64q in the address acquisition execution process (FIG. 33 (e)) described later. By executing "LD B, 0CH", the number of bits ("12") of the address data acquired from the special figure special electric address table 64q is set in the B register 105a of the "transfer destination".

The command "LD HL, TBL_TZTD_B" is set in the line number of "1603". “LD” is an LD instruction, and “HL” is a content that specifies the HL register 107 as a transfer destination. "TBL_TZTD_B" is 2-byte numerical data for using the acquisition start address as the start address of the special figure special electric address table 64q, and is specifically "0C00H". By executing "LD HL, TBL_TZTD_B", "0C00H" is loaded into the HL register 107 of the "transfer destination".

"TBL_TZTD_B" is calculated by the formula "{(start address of special figure special electric address table 64q) -9000H} x 8". 33 (b) to 33 (d) are explanatory views for explaining the process of calculating "TBL_TZTD_B". When "9000H", which is the reference address of the data table, is subtracted from "9180H" (FIG. 33 (b)), which is the start address of the special figure special electric address table 64q, the subtracted data is shown in FIG. 33 (c). The data of the 0th to 11th bits at the start address "9180H" (FIG. 33 (b)) is set in the 0th to 11th bits in the above. After that, when the operation of multiplying the subtracted data by "8" ("1000B") is performed, "TBL_TZTD_B" is calculated as shown in FIG. 33 (d). "8" used in the operation for calculating "TBL_TZTD_B" is a numerical range ("3") represented by the number of bits ("3") of the data for designating the acquisition start bit among the acquisition data designation data. It is a value obtained by adding "1" to "7", which is the maximum value of "0" to "7"), and is the cube of "2". When a 2-byte binary number is multiplied by the nth power of "2" (n is an integer of 1 to 15), the 2-byte binary number is set to the 0th to (15-n) bits. The information of "0" or "1" is shifted to the upper n-bit side and set to the upper (16-n) bit in the multiplied data, and the lower n bits (0th bit) in the multiplied data. "0" is set in the (n-1) th bit).

In the calculation of "TBL_TZTD_B", the value obtained by subtracting "9000H", which is the reference address of the data table, from the start address of the special figure special electric address table 64q (data after subtraction) is the cube of "2", "8". Is multiplied. As a result, the data of the 0th to 12th bits in the data after subtraction is shifted to the upper side of 3 bits and set to the upper 13 bits (3rd to 15th bits) in the data after multiplication, and after the multiplication. "0" is set in the lower 3 bits (0th bit to 2nd bit) in the data of. As shown in FIG. 33 (d), the start address “9180H” (FIG. 33 (b) is used for the third to 14th bits in the “TBL_TZTD_B” which is the data after multiplication by “8” (data after multiplication). )), The data of the 0th to 11th bits is set.

As described above, the acquisition start address in the LDB instruction is calculated by adding "9000H", which is the reference address of the data table, to the value obtained by dividing the acquired data specified data by "8" ("1000B"). To. Further, as already explained, the acquisition data designation data is divided by "8" in the process of calculating the acquisition start address in the LDB instruction, so that the upper 13 bits (third to fifteenth bits) of the acquisition data designation data are obtained. The set data shifts to the lower side by 3 bits. Acquired when the LDB instruction is executed with "TBL_TZTD_B" derived by shifting the data of the 0th to 12th bits in the subtracted data (FIG. 33 (c)) to the upper side by 3 bits as the acquired data designation data. In the process of calculating the start address, "TBL_TZTD_B" is divided by "8". In the quotient data after division, the data of the 0th to 12th bits in the subtracted data (FIG. 33 (c)) that has been shifted to the upper side of 3 bits is shifted to the lower side of 3 bits. Then, the start address (“9180H”) of the special figure special electric address table 64q is calculated as the acquisition start address by the calculation of adding “9000H” which is the reference address of the data table to the quotient data after the division.

In this way, "TBL_TZTD_B" calculated by the formula "{(start address of special figure special electric address table 64q) -9000H} x 8" acquires the start address of special figure special electric address table 64q in the LDB instruction. It is the acquisition data designation data for. By setting "TBL_TZTD_B" as the acquisition data designation data, the start address of the special figure special electric address table 64q can be set as the acquisition start address of the LDB instruction.

In the address acquisition execution process (FIG. 33 (e)) called by the line number "1604", when the value of the special figure special electric counter is "0", "0C00H" stored in the HL register 107 specifies the acquisition data. Used as data. On the other hand, when the value of the special figure special electric counter is "1" or more, the numerical information stored in the HL register 107 becomes the numerical information corresponding to the value of the special figure special electric counter before the LDB instruction is executed. Be changed.

An instruction "CALLS LDBADGET" is set in the line number of "1604". “LDBADGET” is an address acquisition execution process (FIG. 33 (e)) described later. The instruction "CALLS LDBADGET" is an instruction for calling a subroutine called an address acquisition execution process. Although the details will be described later, the start address (any of SA0 to SA6) corresponding to the value of the special figure special electric counter is set in the HL register 107 by executing the address acquisition execution process at the line number "1604". To. When the subroutine of the address acquisition execution process is completed, the process proceeds to the line number of "1605".

An instruction "RET" is set in the line number of "1605". As described above, the special figure special electric address acquisition process is a subroutine executed in step S902 of the special figure special electric control process (FIG. 30). Therefore, by executing the command "RET", the process proceeds to step S903 of the special figure special electric control process (FIG. 30).

Next, the program contents of the address acquisition execution process executed by the main CPU 63 will be described. The address acquisition execution process is executed at the line number "1604" of the special figure special electric address acquisition process (FIG. 33 (a)). FIG. 33 (e) is an explanatory diagram for explaining the program contents of the address acquisition execution process executed by the main CPU 63. Further, FIG. 34 is an explanatory diagram for explaining the correspondence between the value of the special figure special electric counter and the start addresses SA0 to SA6 acquired in the HL register 107.

As shown in FIG. 33 (e), "1701" to "1709" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

As shown in FIG. 33 (e), "LDBADGET" is set in the line number of "1701". This is not an instruction but data that is referred to when the developer of the pachinko machine 10 confirms the program. Therefore, at the line number "1701", the process proceeds to the line number "1702" without executing any instruction.

The command "LD A, B" is set in the line number of "1702". “LD” is an LD instruction, “A” is a content that specifies A register 104b as a transfer destination, and “B” is a content that specifies B register 105a as a transfer source. As described above, in the special figure special electric address acquisition process (FIG. 33 (a)), "0CH" ("12") for designating the number of bits (the number of acquired bits) to be acquired from the special figure special electric address table 64q in the B register 105a. ) Is set. Therefore, by executing "LD A, B", "0CH" is set in the A register 104b of the "transfer destination".

The command "MUL W, A" is set in the line number of "1703". "MUL" is an operation instruction called a MUL instruction, "W" is a content for designating the W register 104a, and "A" is a content for designating the A register 104b. By executing "MUL W, A", an operation of multiplying the value of the W register 104a and the value of the A register 104b is performed, and the result of the operation is stored in the WA register 104. As described above, in the special figure special electric address acquisition process (FIG. 33 (a)), the value of the special figure special electric counter (an integer of 0 to 6) is set in the W register 104a. Further, as described above, "0CH", which is the number of acquired bits, is stored in the A register 104b. Therefore, when "MUL W, A" is executed at the line number "1703", the calculation result of "(value of special figure special electric counter) × (number of acquired bits)" is stored in the WA register 104. To. As described above, in the line number “1603” of the special figure special electric address acquisition process (FIG. 33 (a)), the acquisition data designation data (“0” corresponding to the value of “0” in the special figure special electric counter is stored in the HL register 107. 0C00H ") is stored. For the data of the calculation result of "(value of special figure special electric counter) x (number of acquired bits)", the acquired data designation data stored in the HL register 107 is changed to the data corresponding to the value of the special figure special electric counter. Used for.

The command "ADD HL, WA" is set in the line number of "1704". "ADD" is an operation instruction called an ADD instruction, "HL" is a content for designating an HL register 107, and "WA" is a content for designating a WA register 104. By executing "ADD HL, WA", the sum of the value of the HL register 107 and the value of the WA register 104 is stored in the HL register 107. As described above, in the line number "1603" of the special figure special electric address acquisition process (FIG. 33 (a)), the acquisition data designation data ("0C00H" corresponding to the value of "0" in the special figure special electric counter is stored in the HL register 107. ") Is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(value of special figure special electric counter) x (number of acquired bits)".

As shown in FIG. 34, when the value of the special figure special electric counter is “0”, the data added to the value of the HL register 107 at the line number “1704” is “0000000000000000B”. In this case, the acquired data designation data stored in the HL register 107 does not change. When the value of the special figure special electric counter is "1", the upper 13 bits of the data added to the value of the HL register 107 at the line number "1704" are "0000000000001B", and the lower 3 bits of the data are. It is "100B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "1" and the acquisition start bit becomes "4". When the value of the special figure special electric counter is "2", the upper 13 bits of the data to be added to the value of the HL register 107 at the line number "1704" are "00000000000011B", and the lower 3 bits of the data are. It is "000B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "3" and the acquisition start bit becomes "0". When the value of the special figure special electric counter is "3", the upper 13 bits of the data added to the value of the HL register 107 at the line number "1704" are "0000000000100B", and the lower 3 bits of the data are. It is "100B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "4" and the acquisition start bit becomes "4". When the value of the special figure special electric counter is "4", the upper 13 bits of the data to be added to the value of the HL register 107 at the line number "1704" are "000000000000110B", and the lower 3 bits of the data are. It is "000B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "6" and the acquisition start bit becomes "0". When the value of the special figure special electric counter is "5", the upper 13 bits of the data to be added to the value of the HL register 107 at the line number "1704" are "000000000000111B", and the lower 3 bits of the data are. It is "100B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "7" and the acquisition start bit becomes "4". When the value of the special figure special electric counter is "6", the upper 13 bits of the data to be added to the value of the HL register 107 at the line number "1704" are "000000000000001B", and the lower 3 bits of the data are. It is "000B". In this case, the acquisition data designation data stored in the HL register 107 changes so that the acquisition start address increases by "9" and the acquisition start bit becomes "0".

In this way, the data of the calculation result of "(value of special figure special electric counter) x (number of acquired bits)" stored in the WA register 104 is added to the acquired data designation data stored in the HL register 107. By doing so, it is possible to set the state in which the acquired data designation data corresponding to the value of the special figure special electric counter is stored in the HL register 107.

As with the line number "1702", the command "LD A, B" is set in the line number of "1705". As described above, in the special figure special electric address acquisition process (FIG. 33 (a)), “0CH” (“12”) for designating the number of acquisition bits is set in the B register 105a. Therefore, by executing "LD A, B", "0CH" is set in the A register 104b of the "transfer destination". As described above, "0CH" stored in the B register 105a was also used for the calculation of "(value of special figure special electric counter) × (number of acquired bits)". In this way, "0CH" stored in the B register 105a in advance is used for the calculation of "(value of the special electric power counter) × (number of acquired bits)" and also specifies the number of acquired bits in the LDB instruction. Is used to set the data for the A register 104b.

An instruction "DEC A" is set in the line number of "1706". "DEC" is an operation instruction called a DEC instruction, and "A" is a content that specifies A register 104b. When "DEC A" is executed, the value of the A register 104b is decremented by 1. As described above, "0CH", which is the number of acquired bits, is stored in the A register 104b. Therefore, when "DEC A" is executed at the line number "1706", "0BH" is stored in the A register 104b. "0BH" is a value obtained by subtracting "1" from "12" which is the number of bits acquired from the special figure special electric address table 64q.

As described above, when the LDB instruction "LDB HL, (HL) .A" is executed, the LDB execution circuit 157 performs an operation of adding 1 to the value of the A register 104b, and the value after the 1 addition. Is used as data for the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b at the line number "1706", the number of bits of the data acquired from the special figure special electric address table 64q in the LDB instruction can be set to "12". ..

The command "LDB HL, (HL) .A" is set in the line number of "1707". "LDB" is an LDB instruction by the LDB execution circuit 157, "HL" before the comma is the content that specifies the HL register 107 as the "transfer destination", and "(HL)" before the period is the HL register 107. The content is that the 2-byte data stored in the data is designated as the acquisition data designation data, and the “A” is the content that the 1-byte data stored in the A register 104b is the acquisition bit number designation data. As described above, the HL register 107 is in a state where the acquired data designation data corresponding to the value of the special electric power counter is stored, and the A register 104b is "1" from the number of acquired bits ("0CH"). Is stored in "0BH" obtained by subtracting. Further, the TP register 111 is in a state where the reference address "9000H" is stored. In this state, when the instruction "LDB HL, (HL) .A" is executed at the line number "1707", the special electric power counter is set to the 0th to 11th bits of the HL register 107 which is the transfer destination. The lower 12 bits of data at the start addresses SA0 to SA6 corresponding to the value of are loaded, and the 12th to 15th bits of the HL register 107 are masked with "0".

Specifically, as shown in FIG. 34, when the value of the special figure special electric counter is "0", the acquisition start address becomes "9180H" and the acquisition start bit becomes "0", and the HL register 107 The lower 12 bits of the start address SA0, "700H", are loaded into the 0th to 11th bits. When the value of the special figure special electric counter is "1", the acquisition start address becomes "9181H" and the acquisition start bit becomes "4", and the lower bits of the start address SA1 are assigned to the 0th to 11th bits of the HL register 107. The 12-bit "712H" is loaded. When the value of the special figure special electric counter is "2", the acquisition start address becomes "9183H" and the acquisition start bit becomes "0", and the 0th to 11th bits of the HL register 107 are lower than the start address SA2. The 12-bit "71FH" is loaded. When the value of the special figure special electric counter is "3", the acquisition start address becomes "9184H" and the acquisition start bit becomes "4", and the lower bits of the start address SA3 are in the 0th to 11th bits of the HL register 107. The 12-bit "731H" is loaded. When the value of the special figure special electric counter is "4", the acquisition start address becomes "9186H" and the acquisition start bit becomes "0", and the 0th to 11th bits of the HL register 107 are lower than the start address SA4. The 12-bit "740H" is loaded. When the value of the special figure special electric counter is "5", the acquisition start address becomes "9187H" and the acquisition start bit becomes "4", and the lower bits of the start address SA5 are in the 0th to 11th bits of the HL register 107. The 12-bit "74CH" is loaded. When the value of the special figure special electric counter is "6", the acquisition start address becomes "9189H" and the acquisition start bit becomes "0", and the 0th to 11th bits of the HL register 107 are lower than the start address SA6. The 12-bit "753H" is loaded. In this way, every time the value of the special figure special electric counter increases by 1, the data acquisition start position in the special figure special electric address table 64q shifts by 12 bits.

By using the LDB instruction to load the lower 12 bits of the start addresses SA0 to SA6 acquired from the special electric address table 64q into the 0th to 11th bits of the HL register 107, 2-byte acquisition data can be specified. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the data and the reference address of the data table set in the TP register 111, and the lower 3 bits (the 0th to 2nd bits) of the acquisition designation data. The process of specifying the acquisition start bit corresponding to (bit), the process of loading the lower 12 bits of the start addresses SA0 to SA6 acquired from the special figure special electric address table 64q into the lower 12 bits of the HL register 107, and the process of loading the lower 12 bits of the HL register 107. The process of masking the upper 4 bits of is "0" can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The command "ADD HL, 9000H" is set in the line number of "1708". "ADD" is an operation instruction called an ADD instruction, "HL" is a content for designating an HL register 107, and "9000H" is 2-byte numerical data. By executing "ADD HL, 9000H", "9000H", which is a reference address of the data table, is added to the value of the HL register 107. As a result, as shown in FIG. 34, the entire start address SA0 to SA6 (2 bytes) corresponding to the values of "0" to "6" in the special electric special figure counter can be set. Specifically, when the value of the special figure special electric counter is "0", the start address SA0 "9700H" is set in the HL register 107, and when the value of the special figure special electric counter is "1". Is set to the start address SA1 "9712H" in the HL register 107, and when the value of the special figure special electric counter is "2", the start address SA2 "971FH" is set in the HL register 107. When the value of the special electric counter is "3", the start address SA3 "9731H" is set in the HL register 107, and when the value of the special electric special electric counter is "4", the start address is set in the HL register 107. When "9740H" which is SA4 is set and the value of the special figure special electric counter is "5", "974CH" which is the start address SA5 is set in the HL register 107 and the value of the special figure special electric counter is "6". , The start address SA6 is set to "9753H" in the HL register 107.

An instruction "RET" is set in the line number of "1709". As described above, the address acquisition execution process is a subroutine executed by the line number "1604" of the special figure special electric address acquisition process (FIG. 33 (a)). Therefore, by executing the command "RET", the process proceeds to the line number "1605" of the special figure special electric address acquisition process.

In this way, by using the LDB instruction, the lower 12 bits of the start addresses SA0 to SA6 can be loaded into the HL register 107 from the special figure special electric address table 64q. Further, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SA0 to SA6 to the value of the HL register 107 after the execution of the LDB instruction, the entire start address SA0 to SA6 is added to the HL register 107. Can be obtained. Therefore, the address data set in the special figure special electric address table 64q can be limited to the lower 12 bits of the start addresses SA0 to SA6. As a result, the data capacity of the special figure special electric address table 64q in the main ROM 64 can be reduced as compared with the configuration in which the entire 2-byte start addresses SA0 to SA6 are set in the special figure special electric address table 64q.

<Special figure change start processing>
Next, the contents of the processes of steps S904 to S910 of the special figure special electric control process (FIG. 30) will be described. First, the special figure fluctuation start process in step S904 will be described with reference to the flowchart of FIG. 35.

In the special figure fluctuation start process, first, it is determined whether or not the reserved information is stored in any of the first special figure holding area 115 and the second special drawing holding area 116 (step S1001). In step S1001, a negative determination is made when the value of the first special figure holding number counter 118 is "0" and the value of the second special figure holding number counter 119 is "0". If a negative determination is made in step S1001, the special figure change start process is terminated as it is.

When an affirmative determination is made in step S1001, it is determined whether or not the value of the second special figure hold number counter 119 is 1 or more (step S1002), and the value of the second special figure hold number counter 119 is set. If it is not 1 or more (step S1002: NO), the first special figure data setting process is executed (step S1003). On the other hand, when the value of the second special figure reservation counter 119 is 1 or more (step S1002: YES), the second special figure data setting process is executed (step S1004). In this way, when the number of reserved figures in the second special figure holding area 116 is not "0", that is, when the holding information for variable display is stored for the second special figure display unit 37b, the first special figure The data stored in the second special figure holding area 116 is set for variable display regardless of whether or not the number of holdings in the holding area 115 is 1 or more. As a result, when the hold information is stored in both the first special figure hold area 115 and the second special figure hold area 116, it is stored in the second special figure hold area 116 corresponding to the second operating port 34. The reserved information is prioritized as the start target of the game round.

In the data setting process for the first special figure in step S1003, first, the data stored in the first area 115a of the first special figure hold area 115 is moved to the execution area 117 for the special figure, and the first special figure hold. The value of the number counter 118 is subtracted by 1. After that, the process of shifting the data stored in the storage area of the first special figure holding area 115 is executed. This data shift process is a process of sequentially shifting the data stored in the first to fourth areas 115a to 115d to the lower area side, clearing the data of the first area 115a and → the second area 115b →. The data in each area is shifted such as 1st area 115a, 3rd area 115c → 2nd area 115b, 4th area 115d → 3rd area 115c. After that, the second special figure flag provided in the work area 121 for specific control is cleared to "0". The second special figure flag is a flag for specifying whether the start of the current variation display is the first special figure display unit 37a or the second special figure display unit 37b. After that, a shift command, which is information for causing the sound / light side CPU 93 to recognize that the data in the first special figure holding area 115 has been shifted, is output, and the data setting process for the first special figure is completed. do. By transmitting the command corresponding to the received shift command to the display control device 89, the sound light side CPU 93 displays the number of hold information corresponding to the first special figure hold area 115 in the symbol display device 41. Change in response to the decrease in. Further, when the number of hold information in the first special figure hold area 115 decreases as described above, the first special figure hold display unit 37c is performed in the display control process of step S514 in the timer interrupt process (FIG. 26). On the other hand, the display control is performed so that the display content is changed according to the decrease in the number of pending items.

In the second special figure data setting process in step S1004, first, the data stored in the first area 116a of the second special figure holding area 116 is moved to the execution area 117 for the special figure. After that, the process of shifting the data stored in the storage area of the second special figure holding area 116 is executed. This data shift process is a process of sequentially shifting the data stored in the first to fourth areas 116a to 116d to the lower area side, clearing the data of the first area 116a and the second area 116b →. The data in each area is shifted such as 1st area 116a, 3rd area 116c → 2nd area 116b, 4th area 116d → 3rd area 116c. After that, "1" is set in the second special figure flag in the work area 121 for specific control. After that, a shift command is output, which is information for causing the sound / light side CPU 93 to recognize that the data in the second special figure holding area 116 has been shifted, and the data setting process is terminated. By transmitting the command corresponding to the received shift command to the display control device 89, the sound light side CPU 93 displays the number of hold information corresponding to the second special figure hold area 116 in the symbol display device 41. Change in response to the decrease in. Further, when the number of hold information in the second special figure hold area 116 decreases as described above, the second special figure hold display unit 37d is performed in the display control process of step S514 in the timer interrupt process (FIG. 26). On the other hand, the display control is performed so that the display content is changed according to the decrease in the number of pending items.

When the process of step S1003 is executed, or when the process of step S1004 is executed, is "1" set in the high probability mode flag provided in the mode data area in the work area 121 for specific control? By determining whether or not it is, it is determined whether or not it is in the high probability mode (step S1005). The high-probability mode flag is a flag for the main CPU 63 to specify that the winning / failing lottery mode is the high-probability mode. The high-probability mode flag is set to "1" when the open / close execution mode ends regardless of the type of jackpot result that triggered the execution. The high probability mode flag is set in the second bit in the mode data area. In step S1005, an affirmative determination is made when "1" is set in the high probability mode flag.

If an affirmative determination is made in step S1005, a high-probability hit / fail determination process is executed (step S1006). As already described with reference to FIG. 13, the main ROM 64 has a high accuracy table 64g that is referred to regardless of whether the current setting value of the pachinko machine 10 is “setting 1” to “setting 6”. It is remembered. In the high-probability hit / fail determination process in step S1006, the hit / fail determination information among the information stored in the execution area 117 for the special figure, that is, the numerical information acquired from the hit random number counter C1, is referred to with reference to the high probability hit / miss table 64g. Is determined to match with the big hit numerical information or the small hit numerical information set in the high probability accuracy table 64g.

The work area 121 for specific control is provided with a hit / fail data area 158 in which data corresponding to the result of the hit / miss determination process is set. FIG. 36A is an explanatory diagram for explaining the configuration of the pass / fail data area 158. The pass / fail data area 158 is an area consisting of 1 byte. As shown in FIG. 36 (a), the small hit flag 158b is set in the 0th bit of the hit / fail data area 158, and the big hit flag 158a is set in the first bit. Further, the 2nd to 7th bits of the pass / fail data area 158 are unused bits that are not used. The jackpot flag 158a is a flag that enables the main CPU 63 to grasp that a jackpot result has been obtained in the hit / fail determination process, and the small hit flag 158b is a flag that enables the main side CPU 63 to know that a jackpot result has been obtained in the hit / fail determination process. This is a flag that can be grasped by the CPU 63.

In the high-probability hit / fail determination process in step S1006, when the numerical information acquired from the hit random number counter C1 matches the jackpot numerical information, the data "00000010B" is set in the hit / miss data area 158. As a result, "1" can be set in the jackpot flag 158a. Further, when the numerical information acquired from the hit random number counter C1 matches the small hit numerical information, the data "00000001B" is set in the hit / fail data area 158. As a result, "1" can be set in the small hit flag 158b.

FIG. 36 (b) is an explanatory diagram for explaining the contents of the high accuracy / rejection table 64g, and FIG. 36 (c) is an explanatory diagram for explaining the data structure of the high accuracy / rejection table 64g. As shown in FIG. 36 (c), the high-accuracy accuracy table 64g is stored in the address range of "9220H" to "945BH" in the main ROM 64.

As described above, the numerical information acquired from the hit random number counter C1 is an integer of 0 to 7999. As shown in FIG. 36 (b), 266 jackpot numerical information including "30", "60", "90" and "7999" are set in the high probability accuracy table 64g, and "75". Forty small hit numerical information including is set. Further, a determination value HVn (n is an integer of 1 to 572) for performing a hit / fail determination and flag data FDn (n is an integer of 1 to 572) corresponding to the determination value are set in the high probability accuracy table 64g. Has been done. The determination value HVn is 6-bit numerical data corresponding to any of the integers 1 to 31.

The flag data FDn is 2-bit data set in the lower 2 bits (0th to 1st bits) of the pass / fail data area 158. The flag data corresponding to the jackpot result such as the flag data FD2, FD4, FD8, FD572 is "10B". By setting the flag data corresponding to the jackpot result in the lower two bits of the hit / fail data area 158, "1" is set in the jackpot flag 158a and the value of the small hit flag 158b becomes "0". The flag data corresponding to the small hit result such as the flag data FD6 is "01B". By setting the flag data corresponding to the small hit result in the lower two bits of the hit / fail data area 158, "1" is set in the small hit flag 158b and the value of the big hit flag 158a becomes "0". Flag data The flag data corresponding to the off result such as FD1, FD3, FD5, FD7, FD571 is "00B". The value of the big hit flag 158a and the small hit flag 158b becomes "0" by setting the flag data corresponding to the deviation result in the lower two bits of the pass / fail data area 158.

Next, the high-probability hit / miss determination process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 37 (a). The high-probability hit / fail determination process is executed in step S1006 of the special figure variation start process (FIG. 35). The high-probability hit / fail determination process is executed by using the program for specific control and the data for specific control.

In the high-probability hit / fail determination process, the instruction "LD HL, 1150H" is first executed (step S1101). "LD" is an LD instruction, "HL" is a content for designating the HL register 107 as a transfer destination, and "1100H" is 2-byte numerical information. In the pass / fail determination data acquisition process (step S1103), which will be described later, one of the 572 determination values HV1 to HV572 set in the high-accuracy hit / fail table 64 g (FIGS. 36 (b) and (c)) is determined value HVn. The LDB update instruction "LDB WA, (HL +) .5" is executed in order to acquire (n is any of 1 to 572) in the WA register 104, and the determination value HVn acquired in the WA register 104 is executed. The LDB update instruction "LDB B, (HL +) .1" is executed in order to acquire the flag data FDn corresponding to the above in the B register 105a. In the high-probability hit / fail determination process (FIG. 37 (a)), the processes of steps S1103 to S1105 are repeatedly executed until an affirmative determination is made in step S1105. The combination of the determination value HVn and the flag data FDn acquired in the WA register 104 and the B register 105a in the pass / fail determination data acquisition process in step S1103 is a combination of HV1 and FD1 → a combination of HV2 and FD2 → a combination of HV3 and FD3. →… → The combination of HV572 and FD572 is updated in this order. The numerical value "1100H" is the determination value HV1 and the flag data in the WA register 104 and the B register 105a when the pass / fail determination data acquisition process (step S1103) is executed for the first time in the current processing times (game times). It is a numerical value for acquiring the combination of FD1. By executing the instruction "LD HL, 1150H" in step S1101, "1100H" is loaded into the HL register 107. The numerical value "1100H" and the details of the LDB update command will be described later.

After loading "1100H" into the HL register 107 in step S1101, any of the information for determining whether or not the result is stored in the execution area 117 for the special figure, that is, 0 to 7999 acquired from the winning random number counter C1. The numerical information (2 bytes) is set in the DE register 106 (step S1102).

After that, the data acquisition process for determining whether the result is correct or not is executed (step S1103). As described above, one of the 572 determination values HV1 to HV572 set in the high-accuracy accuracy table 64g (FIGS. 36 (b) and (c)) by executing the accuracy determination data acquisition process. The determination value HVn is set in the WA register 104, and the flag data FDn corresponding to the determination value HVn set in the WA register 104 is set in the B register 105a. The details of the data acquisition process for determining whether or not the result is correct will be described later.

After that, the value of the WA register 104 is subtracted from the value of the DE register 106 (step S1104). As described above, the DE register 106 is set with 2-byte numerical information (any of 0 to 7999) acquired from the random number counter C1 in step S1102, and the WA register 104 is determined in step S1103. The value HVn is set. Therefore, when the process of step S1104 is executed for the first time in the current process times (game times), the process of subtracting the determination value HV1 from the numerical information acquired from the hit random number counter C1 is executed in the step S1104. .. Further, when the processing of step S1104 is executed at the (m + 1) th time (m is an integer of any of 1 to 571) in the current processing round (game round), the numerical value acquired from the random number counter C1 in the step S1104. The process of subtracting the determination value HV (m + 1) from the numerical information after the m determination values HV1 to HVm are subtracted from the information is executed.

After that, it is determined whether or not the value of the DE register 106 is less than "0" (step S1105). When the calculation result of step S1104 is "0" or more, the value of the carry flag becomes "0", and when the calculation result is less than "0", "1" is set in the carry flag. Will be done. In step S1105, an affirmative determination is made when the carry flag is set to "1". If the value of the DE register 106 is not less than "0" (step S1105: NO), the process returns to step S1103. Then, the processes of steps S1103 to S1105 are repeatedly executed until an affirmative determination is made in step S1105. As a result, the determination value HVn is subtracted from the numerical information acquired from the random number counter C1 to the DE register 106 in step S1102 in the order of HV1 → HV2 → HV3 → ... → HV572, and the calculation result is less than “0”. The flag data FDn corresponding to the determined determination value HVn can be specified as the winning flag data.

When an affirmative determination is made in step S1105, the flag data FDn stored in the B register 105a, that is, the winning flag data FDn is set in the hit / fail data area 158 in the work area 121 for specific control. (Step S1106), the high probability hit / fail determination process is terminated. In step S1106, when the flag data FDn corresponding to the big hit result is set in the hit / fail data area 158, "1" is set in the big hit flag 158a, and the flag data FDn corresponding to the small hit result is set in the hit / fail data area 158. When set to, "1" is set in the small hit flag 158b. Further, when the flag data FDn corresponding to the deviation result is set in the hit / fail data area 158, the values of the big hit flag 158a and the small hit flag 158b become “0”.

<LDB update order>
Next, the LDB update command included in the hit / fail determination data acquisition process will be described prior to the description of the hit / fail determination data acquisition process (step S1103). As described above, the data acquisition process for determining whether or not the result is correct includes the LDB update instructions "LDB WA, (HL +) .5" and "LDB B, (HL +) .1". As shown in FIG. 9, the main MPU 62 includes an LDB update execution circuit 161 which is a dedicated circuit for executing an LDB update command, and the main CPU 63 can execute the LDB update command.

The instruction code of the LDB update instruction has a configuration of "LDB transfer destination, (acquisition data specification +). Acquisition bit number specification". The LDB update instruction is updated by adding the number of acquisition bits to the acquisition data specification data stored in the "acquisition data specification" register after the processing is executed, in addition to the processing executed by the LDB instruction. It is an instruction that enables processing to be executed with one instruction.

In the LDB update instruction, a general-purpose register or a pair register is set as a "transfer destination" as in the LDB instruction. The general-purpose register set as the "forwarding destination" in the LDB update instruction is the W register 104a or the B register 105a. The pair register set as the "forwarding destination" in the LDB update instruction is the WA register 104. In the LDB update instruction, the A register 104b, the C register 105b, the D register 106a, the E register 106b, the H register 107a, or the L register 107b may be set as the "transfer destination" general-purpose register. Further, the BC register 105 or the DE register 106 may be set as the pair register of the "transfer destination" in the LDB update instruction.

In the LDB update command, "(HL +)" is set as the "acquisition data designation". In the LDB update instruction, as in the LDB instruction, acquisition start of data to be loaded in the "transfer destination" register based on the acquisition data specification data stored in the HL register 107 set as "acquisition data specification". The address and the acquisition start bit are specified.

When a 1-byte general-purpose register (W register 104a or B register 105a) is set as the "transfer destination", in the LDB update instruction, a numerical value of any one of "0" to "7" is set as the "acquisition bit number specification". Is set. Further, when the 2-byte WA register 104 is set as the "transfer destination", any numerical value of "0" to "15" is set as the "acquisition bit number designation" in the LDB update instruction.

In the LDB update instruction, in the main ROM 64, the data for the number of acquisition bits set after the acquisition bit at the acquisition start address is loaded into the lower area of the WA register 104, which is the "transfer destination", and at the same time. The area on the upper side of the WA register 104 is masked with "0". After that, the number of acquired bits this time is added to the value of the HL register 107 in which the acquired data designation data is stored, and the acquisition data designation data stored in the HL register 107 is updated.

By using the LDB update command, the process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111. , The process of specifying the acquisition start bit corresponding to the 0th to 2nd bits (lower 3 bits) of the acquisition designation data, and the acquisition bit set after the acquisition start bit at the acquisition start address in the main ROM 64. The process of loading a few minutes of data into the lower bits in the "transfer destination" register, the process of masking the upper bits in the "transfer destination" register with "0", and the process of masking the upper bits in the "transfer destination" register with the value of the HL register 107 this time. The process of adding the number of acquired bits and updating the acquired data specified data can be executed with one instruction. These processes are executed by the LDB update execution circuit 161. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

Next, the hit / fail determination data acquisition process executed in step S1103 of the high-probability hit / fail determination process (FIG. 37 (a)) will be described.

FIG. 37B is an explanatory diagram for explaining the program contents of the data acquisition process for determining whether or not the result is correct. Further, FIG. 37 (c) is an explanatory diagram for explaining how the determination value HVn is set in the WA register 104, and FIG. 37 (d) explains how the flag data FDn is set in the B register 105a. It is explanatory drawing for this.

As shown in FIG. 37 (b), "1801" to "1803" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

As shown in FIG. 37 (b), the command "LDB WA, (HL +) .5" is set in the line number of "1801". “LDB” is an LDB update instruction by the LDB update execution circuit 161. “WA” is a content that specifies WA register 104 as a “transfer destination”, and “(HL +)” is stored in HL register 1072. It is the content to specify the byte data as the acquisition data specification data and to instruct to update the acquisition data specification data stored in the HL register 107 after loading the data, and "5" is "5" as the acquisition bit number specification data. 5 ”is the content to be set.

38 (a) to 38 (e) show the start address of the high accuracy table 64 g, the acquisition data designation data in the LDB instruction (“LDB WA, (HL +). 5”), the acquisition start address, the acquisition start bit, It is explanatory drawing for demonstrating the acquired data designation data after the update. As described above, the numerical information "1100H" is set in the HL register 107 in step S1101 of the high accuracy determination process (FIG. 37 (a)). As shown in FIG. 38B, the “1100H” is acquired data designation data when the LDB instruction “LDB WA, (HL +) .5” is executed for the first time. As described above, the starting address of the high accuracy / rejection table 64g is “9220H” (see FIG. 38 (a)). "1100H" is numerical information calculated by the formula "{(start address of high probability accuracy table 64g) -9000H} x 8". As shown in FIG. 38 (b), the 3rd to 14th bits in the acquired data designation data (“1100H”) are in “9220H” (FIG. 38 (a)) which is the start address of the high accuracy / rejection table 64g. The data of the 0th to 11th bits is set.

As described above, the acquisition start address is the reference address of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquired data specified data by "8" ("1000B"), "9000H". Is calculated by the operation of adding. When the LDB update instruction is executed with "1100H" stored in the HL register 107 as the acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1100H" by "8". Is calculated by the calculation of adding "9220H". As shown in FIG. 38 (c), the data of the 0th to 11th bits at the acquisition start address is the data of the 3rd to 14th bits of the acquisition data designated data (the 0th at the start address of the high accuracy / rejection table 64g). The data of the twelfth to fifteenth bits at the acquisition start address is the data of the twelfth to fifteenth bits at the reference address of the data table. The acquisition start address "9220H" is the start address of the high probability accuracy table 64g.

As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte of the acquisition data designated data and "000000111H". When the LDB update instruction is executed with "1100H" stored in the HL register 107 as the acquisition data designation data, the acquisition start bit is the lower 1 byte ("0000000000B") and "000000111H" of the acquisition data designation data. It becomes "0000000000B" ("0") which is a logical product of. As shown in FIG. 38 (d), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the lower 3 bits (0th to 2nd bits) in the acquisition data designation data (FIG. 38 (b)). The data of the upper 5 bits (3rd to 7th bits) in the acquisition start bit is "0" as well as the data of (bits).

Since the numerical value "5" is set as the acquisition bit designation data in the LDB update instruction "LDB WA, (HL +) .5", the number of acquisition bits is obtained by adding "1" to the "5". It becomes "6" obtained. When the LDB update instruction "LDB WA, (HL +) .5" is executed while "1100H" is stored in the HL register 107, as shown in FIG. 37 (c), in the high accuracy table 64g. The data (HV1) for the number of acquisition bits (6 bits) set after the acquisition start bit (0th bit) in the area corresponding to the acquisition start address "9220H" is the transfer destination WA. It is loaded into the 0th to 5th bits (lower 6 bits) of the register 104, and the 6th to 15th bits (upper 10 bits) of the WA register 104 are masked with "0". As a result, the determination value HV1 can be set in the WA register 104.

As described above, the number of acquisition bits in the LDB update instruction "LDB WA, (HL +) .5" is "6". Therefore, in the LDB update instruction, after 6-bit data is loaded into the 0th to 5th bits of the WA register 104, the number of acquired bits (“6”) is set in the value (“1100H”) of the HL register 107. After being added, the value of the HL register 107 is updated to "1106H" as shown in FIG. 38 (e).

"1106H" is numerical information in which the acquisition start address is "9220H" and the acquisition bit is the sixth bit when the next LDB update instruction is executed with the "1106H" as the acquisition data designation data. .. In this way, when the LDB update instruction is executed and the acquired data designation data stored in the HL register 107 is updated, the LDB update instruction is executed next to the LDB update instruction by the number of acquired bits in the LDB update instruction. The data acquisition start position in the LDB update instruction shifts.

In this way, the determination value data DV1 acquired from the high-accuracy accuracy table 64g using the LDB update instruction is set in the WA register 104 to update the acquired data designation data, whereby 2-byte acquisition data designation is performed. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the data and the reference address of the data table set in the TP register 111, and the 0th to 2nd bits (lower 3) of the acquisition designation data. The process of specifying the acquisition start bit corresponding to the bit) and the process of loading the determination value data DV1 acquired from the high accuracy / rejection table 64g into the 0th to 5th bits (lower 6 bits) of the WA register 104. The process of masking the 6th to 15th bits (upper 10 bits) of the WA register 104 with "0", the process of adding the number of acquired bits this time to the value of the HL register 107, and the process of updating the acquired data specified data. Can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The command "LDB B, (HL +). 1" is set in the line number of "1802". “LDB” is an LDB update instruction by the LDB update execution circuit 161. “B” is a content that specifies B register 105a as a “transfer destination”, and “(HL +)” is stored in HL register 1072. It is the content to specify the byte data as the acquisition data specification data and to instruct to update the acquisition data specification data stored in the HL register 107 after the data transfer, and "1" is "1" as the acquisition bit number specification data. Is the content to set.

39 (a) to 39 (c) show the acquisition data designation data, the acquisition start address, the acquisition start bit, and the updated acquisition data designation data in the LDB instruction (“LDB B, (HL +). 1”). It is explanatory drawing for demonstrating. As described above, the acquisition start address is the reference address (“9000H”) of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquired data specified data by “8” (“1000B”). ) Is added. When the LDB update instruction is executed with "1106H" stored in the HL register 107 as the acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1106H" by "8". Is calculated by the calculation of adding "9220H". As shown in FIG. 39 (a), the data of the 0th to 11th bits at the acquisition start address is the data of the 3rd to 14th bits of the acquisition data designated data, and the data of the twelfth to the twelfth at the acquisition start address. The 15th bit data is the 12th to 15th bit data at the reference address of the data table. The acquisition start address "9220H" is the start address of the high probability accuracy table 64g.

As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte of the acquisition data designated data and "000000111H". When the LDB update instruction is executed with "1106H" stored in the HL register 107 as the acquisition data designation data, the acquisition start bit is the lower 1 byte ("00000011B") and "00000011H" of the acquisition data designation data. It becomes "00000011B" ("6") which is a logical product of. As shown in FIG. 39 (b), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the data of the lower 3 bits (0th to 2nd bits) in the acquisition data designated data. , The data of the upper 5 bits (3rd to 7th bits) in the acquisition start bit is "0".

Since the numerical value "1" is set as the acquisition bit designation data in the LDB update instruction "LDB B, (HL +) .1", the number of acquisition bits is obtained by adding "1" to the "1". It becomes "2" to be obtained. When the LDB update instruction "LDB B, (HL +) .1" is executed while "1106H" is stored in the HL register 107, as shown in FIG. 37 (d), in the high accuracy table 64g. , The data (flag data FD1) for the number of acquisition bits (2 bits) set after the acquisition start bit (6th bit) in the area corresponding to the acquisition start address "9220H" is the transfer destination. It is loaded into the 0th to 1st bits (lower 2 bits) of a certain D register 106a, and the 2nd to 7th bits (upper 6 bits) of the D register 106a are masked with "0". As a result, the flag data FD1 corresponding to the determination value HV1 stored in the WA register 104 can be set in the D register 106a.

As described above, the number of acquisition bits in the LDB update instruction "LDB B, (HL +). 1" is "2". Therefore, in the LDB update instruction, after 2 bits of data are loaded into the 0th to 1st bits of the B register 105a, the number of acquired bits (“2”) is set in the value (“1106H”) of the HL register 107. After being added, the value of the HL register 107 is updated to "1108H" as shown in FIG. 39 (c).

"1108H" is numerical information in which the acquisition start address is "9221H" and the acquisition bit is the 0th bit when the next LDB update instruction is executed with the "1108H" as the acquisition data designation data. .. In this way, when the LDB update instruction is executed and the acquired data designation data stored in the HL register 107 is updated, the LDB update instruction is executed next to the LDB update instruction by the number of acquired bits in the LDB update instruction. The data acquisition start position in the LDB update instruction shifts.

By executing the LDB update instruction "LDB WA, (HL +) .5" and the LDB update instruction "LDB B, (HL +) .1", the determination value HV1 and the flag data are set in the WA register 104 and the D register 106a. FD1 is set. Further, by increasing the value of the HL register 107 by "8" (the sum of "6" and "2"), the LDB update instruction "LDB WA, (HL +) .5" and "LDB B, (HL +). The acquisition start address in the LDB update command "1" is increased by "1".

In this way, the flag data FD1 acquired from the high-accuracy accuracy table 64g using the LDB update instruction is set in the B register 105a to update the acquired data designation data, so that the two-byte acquisition data designation data is updated. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits and the reference address of the data table set in the TP register 111, and the 0th to 2nd bits (lower 3) of the acquisition designation data. B One instruction is the process of masking the 2nd to 7th bits (upper 6 bits) of the register 105a with "0" and the process of adding the number of acquired bits to the value of the HL register 107 and updating the acquired data specified data. Can be done with. These processes are executed by the LDB update execution circuit 161. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

An instruction "RET" is set in the line number of "1803". As described above, the hit / fail determination data acquisition process is a subroutine executed in step S1103 of the high-probability hit / fail determination process (FIG. 37 (a)). Therefore, by executing the instruction "RET", the process proceeds to step S1104 of the high-probability hit / miss determination process.

As described above, in the high probability hit / fail determination process (FIG. 37 (a)), the processes of steps S1103 to S1105 are repeatedly executed until an affirmative determination is made in step S1105. FIG. 40 shows the number of times the LDB update instruction “LDB WA, (HL +) .5” and the LDB update instruction “LDB B, (HL +) .1” are executed, and the WA register 104 and the B register 105a by these LDB update instructions. It is explanatory drawing for demonstrating with the data acquired in. As shown in FIG. 40, in the second line number "1801", "LDB WA, (HL +) .5" is executed with "1108H" as the acquisition data designation data, and the determination value HV2 is set in the WA register 104. To. Then, the value of the HL register 107 is updated to "110EH". Further, in the second line number "1802", "LDB B, (HL +) .1" is executed with "110EH" as the acquisition data designation data, and the flag data FD2 corresponding to the determination value HV2 is set in the B register 105a. Will be done. Then, the value of the HL register 107 is updated to "1110H".

In this way, the combination of the determination value HVn and the flag data FDn set in the high accuracy accuracy table 64g is combined with 1 by configuring the configuration to repeatedly execute the accuracy determination data acquisition process using the high accuracy accuracy / rejection table 64g. The pairs can be loaded into the WA register 104 and the B register 105a in order.

Returning to the description of the special figure fluctuation start process (FIG. 35), when a negative determination is made in step S1005, that is, in the low probability mode, the low probability accuracy determination process is executed (step S1007). As already described with reference to FIG. 13, the main ROM 64 stores the low accuracy tables 64a to 64f for the setting 1 to the setting 6. In the low-accuracy determination process in step S1007, the accuracy determination is made out of the information stored in the execution area 117 for special figures with reference to the low-accuracy accuracy / rejection tables 64a to 64f corresponding to the current set values of the pachinko machine 10. Information, that is, whether or not the numerical information acquired from the hit random number counter C1 matches the big hit numerical information or the small hit numerical information set in the low accuracy tables 64a to 64f is determined. When the numerical information acquired from the hit random number counter C1 matches the jackpot numerical information for low probability corresponding to the set value, the jackpot flag 158a is set by setting the data "00000010B" in the hit / fail data area 158. Set to "1". Further, when the numerical information acquired from the hit random number counter C1 matches the small hit numerical information, the data "00000001B" is set in the hit / fail data area 158 to set the small in the work area 121 for specific control. Set "1" to the hit flag 158b.

When the process of step S1006 is performed or the process of step S1007 is performed, it is determined whether or not "1" is set in the jackpot flag 158a (step S1008), and "1" is set in the jackpot flag 158a. When is set (step S1008: YES), the first result correspondence process is executed (step S1009). In the first result handling process, a process for sorting the jackpot type is executed, and the variable type number corresponding to the jackpot type is set in the variable type number counter provided in the work area 121 for specific control. For the variation type number, the result of the hit / fail judgment, the result of the distribution judgment, the result of the reach generation lottery, the stop result data corresponding to the number of hold of the special figure hold areas 115 and 116, and the display duration data are obtained from the change pattern table described later. It is the data to be acquired. The variation type number is numerical information of any of 0 to 23. The variable type number counter is a counter that enables the main CPU 63 to grasp the variable type number. The variable type number counter consists of 1 byte. The details of the first result handling process will be described later.

If a negative determination is made in step S1008, a second result correspondence process corresponding to the small hit result or the missed result is executed (step S1010). In the second result correspondence process, when "1" is set in the small hit flag 158b, the variable type number corresponding to the small hit result is set in the variable type number counter. If "1" is not set in the small hit flag 158b, that is, if the result is out of order, a reach generation lottery is performed, and the variation type number corresponding to the result of the reach generation lottery is set in the variation type number counter. .. The details of the second result handling process will be described later.

Here, the first special figure distribution process and the second special figure distribution process performed in the first result correspondence process (step S1009) will be described.

In the first special figure distribution process and the second special figure distribution process, the result is divided into 4R high-accuracy jackpot result, 8R high-accuracy jackpot result, and 16R high-accuracy jackpot result. The work area 121 for specific control is provided with a distribution data area 162 in which the result of distribution determination is set. FIG. 41A is an explanatory diagram for explaining the configuration of the distribution data area 162. The distribution data area 162 is an area consisting of 1 byte.

As shown in FIG. 41 (a), the 4R high accuracy flag 162a is set in the 0th bit of the distribution data area 162, the 8R high accuracy flag 162b is set in the first bit, and the second bit is set. The 16R high accuracy flag 162c is set in the bit. Further, the 3rd to 7th bits of the distribution data area 162 are unused bits that are not used. The 4R high-accuracy flag 162a is a flag that enables the main CPU 63 to grasp that a 4R high-accuracy jackpot result has occurred, and the 8R high-accuracy flag 162b is a flag that allows the main CPU 63 to know that an 8R high-accuracy jackpot result has occurred. The 16R high-accuracy flag 162c is a flag that enables the main CPU 63 to grasp that a 16R high-accuracy jackpot result has occurred.

When the data is distributed to the 4R high-accuracy jackpot result in the first special figure distribution process or the second special figure distribution process, the data "00000001B" is set in the distribution data area 162. As a result, "1" is set in the 4R high accuracy flag 162a. Further, when the data is distributed to the 8R high-accuracy jackpot result in these distribution processes, the data "00000010B" is set in the distribution data area 162. As a result, "1" is set in the 8R high accuracy flag 162b. Furthermore, when the data is distributed to the 16R high-accuracy jackpot results in these distribution processes, the data "00000100B" is set in the distribution data area 162. As a result, "1" is set in the 16R high accuracy flag 162c.

In the first special figure distribution process, the first special figure distribution table 64h in the main ROM 64 is used. As shown in FIG. 14 (a), in the first special figure distribution table 64h, when the value acquired from the jackpot type counter C2 is any of 0 to 39, it is sorted into the 4R high-accuracy jackpot results and the jackpot. When the value acquired from the type counter C2 is any of 40 to 79, it is distributed to the 8R high-accuracy jackpot result. Further, when the value acquired from the jackpot type counter C2 is any of 80 to 99, it is distributed to the 16R high-accuracy jackpot result.

In the distribution table 64h for the first special figure, "20" is set as the first distribution value FVA1 before addition corresponding to the 4R high accuracy jackpot result, and before the second addition corresponding to the 8R high accuracy jackpot result. "20" is set as the distribution value FVA2, and "0" is set as the third addition pre-distribution value FVA3 corresponding to the 16R high-accuracy jackpot result. These pre-addition distribution values FVAn (n is an integer of 1 to 3) are 5-bit data. In the first special figure distribution process, by uniformly adding "20" to these pre-addition distribution values FVAn, the first distribution value is "40" and the second distribution value is obtained. "40" and "20" which is the third distribution value are calculated. Then, these distribution values are subtracted from the values acquired from the jackpot type counter C2 in the order of the first distribution value → the second distribution value → the third distribution value, and the subtraction result is less than “0”. When this happens, the flag data FDAn corresponding to the distribution value is set in the distribution data area 162. As a result, the result of the distribution determination can be grasped by the main CPU 63.

As shown in FIG. 14A, a 3-bit "001B" is set as the first flag data FDA1 corresponding to the 4R high accuracy jackpot result in the distribution table 64h for the first special figure, and the height is 8R. A 3-bit "010B" is set as the second flag data FDA2 corresponding to the probability jackpot result, and a 3-bit "100B" is set as the third flag data FDA3 corresponding to the 16R high accuracy jackpot result. These flag data FDA1 to FDA3 are set in the lower 3 bits (3rd to 2nd bits) of the distribution data area 162, and the upper 5 bits (3rd to 7th bits) of the distribution data area 162 are "0". Is masked.

FIG. 41B is an explanatory diagram for explaining the data structure of the first special drawing distribution table 64h. As shown in FIG. 41 (b), the first special figure distribution table 64h is stored in the address range of "9252H" to "9252H" in the main ROM 64. The first addition pre-distribution value FVA1 corresponding to the 4R high-accuracy jackpot result is set in the 0th to 4th bits of "9250H" which is the start address of the distribution table 64h for the first special figure, and the first The first flag data FDA1 is set in the 5th to 7th bits. The second pre-addition distribution value FVA2 corresponding to the 8R high-accuracy jackpot result is set in the 0th to 4th bits of "9251H" following "9251H", and the second bit is set in the 5th to 7th bits. Flag data FDA2 is set. The 3rd addition pre-distribution value FVA3 corresponding to the 16R high accuracy jackpot result is set in the 0th to 4th bits of "9252H" following "9251H", and the 3rd bit is set in the 5th to 7th bits. Flag data FDA3 is set.

As shown in FIG. 41 (b), the flag data FDAn is 3-bit data, and the pre-addition distribution value FVAn is 5-bit data. Since the combination of the corresponding flag data FDAn and the pre-addition distribution value FVAn is 1-byte data, the combination of the three flag data FDAn and the pre-addition distribution value FVAn is stored in a 3-byte storage area. Can be left. The second distribution value "40" ("101000B") is 6-bit numerical information in binary notation. In order to store the combination of the second flag data FDA2 and the second distribution value, a storage area of 9 bits or more is required. Therefore, assuming that the first special figure distribution table 64h stores the combination of the three flag data FDAn and the distribution value, the data of the first special figure distribution table 64h in the main ROM 64 The capacity will increase. On the other hand, since the combination of the flag data FDAn and the pre-addition distribution value FVAn obtained by subtracting the distribution value by 20 is stored in the distribution table 64h for the first special figure, the main ROM 64 has a configuration. The data capacity of the distribution table 64h for the first special figure can be reduced.

In the second special figure distribution process, the second special figure distribution table 64j in the main ROM 64 is used. As shown in FIG. 14 (b), in the second special figure distribution table 64j, when the value acquired from the jackpot type counter C2 is any of 0 to 29, it is sorted into the 4R high-accuracy jackpot results and the jackpot. When the value acquired from the type counter C2 is any of 30 to 79, it is distributed to the 8R high-accuracy jackpot result. Further, when the value acquired from the jackpot type counter C2 is any of 80 to 99, it is distributed to the 16R high-accuracy jackpot result.

In the distribution table 64j for the second special figure, "10" is set as the first distribution value FVB1 corresponding to the 4R high-accuracy jackpot result, and before the second addition corresponding to the 8R high-accuracy jackpot result. “30” is set as the distribution value FVB2, and “0” is set as the third addition pre-distribution value FVB3 corresponding to the 16R high accuracy jackpot result. These pre-addition distribution values FVBn (n is an integer of 1 to 3) are 5-bit data. In the second special figure distribution process, by uniformly adding "20" to these pre-addition distribution values FVBn, the first distribution value is "30" and the second distribution value is obtained. "50" and "20" which is the third distribution value are calculated. Then, these distribution values are subtracted from the values acquired from the jackpot type counter C2 in the order of the first distribution value → the second distribution value → the third distribution value, and the subtraction result is less than “0”. In this case, the flag data FDBn corresponding to the case is set in the distribution data area 162.

As shown in FIG. 14B, a 3-bit "001B" is set as the first flag data FDB1 corresponding to the 4R high accuracy jackpot result in the distribution table 64j for the second special figure, and the height is 8R. A 3-bit "010B" is set as the second flag data FDB2 corresponding to the probability jackpot result, and a 3-bit "100B" is set as the third flag data FDB3 corresponding to the 16R high accuracy jackpot result. These flag data FDB1 to FDB3 are set in the lower 3 bits of the distribution data area 162, and the upper 5 bits of the distribution data area 162 are masked with "0".

FIG. 41 (c) is an explanatory diagram for explaining the data structure of the second special figure distribution table 64j. As shown in FIG. 41 (c), the second special figure distribution table 64j is stored in the address range of "9253H" to "9255H" in the main ROM 64. The first addition pre-distribution value FVB1 corresponding to the 4R high-accuracy jackpot result is set in the 0th to 4th bits of "9253H" which is the start address of the second special figure distribution table 64j, and the first The first flag data FDB1 is set in the 5th to 7th bits. The second pre-addition distribution value FVB2 corresponding to the 8R high-accuracy jackpot result is set in the 0th to 4th bits of "9254H" following "9253H", and the second bit is set in the 5th to 7th bits. Flag data FDB2 is set. The 3rd addition pre-distribution value FVB3 corresponding to the 16R high accuracy jackpot result is set in the 0th to 4th bits of "9255H" following "9254H", and the 3rd bit is set in the 5th to 7th bits. Flag data FDB3 is set.

Next, the first result correspondence process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 42. The first result correspondence process is executed in step S1009 of the special figure variation start process (FIG. 35). The first result correspondence process is executed by using the program for specific control and the data for specific control.

In the first result handling process, first, among the reserved information stored in the execution area 117 for the special figure, the information for distribution determination, that is, the numerical information (random number of the jackpot type) acquired from the jackpot type counter C2 is stored in the A register 104b. Set (step S1201). After that, it is determined whether or not "1" is set in the second special figure flag in the work area 121 for specific control (step S1202). As described above, the second special figure flag is set to "1" when the second special figure data setting process (step S1004) is executed in the special figure variation start process (FIG. 35). When "1" is set in the second special figure flag, it means that the start of the fluctuation display this time is the second special figure display unit 37b.

When "1" is not set in the second special figure flag (step S1202: NO), the instruction "LD HL, 1280H" is executed (step S1203). "LD" is an LD instruction, "HL" is a content for designating the HL register 107 as a transfer destination, and "1280H" is 2-byte numerical information. In the distribution data acquisition process (step S1205), which will be described later, if "1" is not set in the second special figure flag, it is set in the first special figure distribution table 64h (FIG. 41 (b)). “LDB W, (HL +). 4 to acquire the pre-addition distribution value FVAn (n is any of 1 to 3) of the three pre-addition distribution values FVA1 to FVA3 in the W register 104a. The LDB update instruction "LDB B, (HL +) .2" is executed, and the flag data FDAn corresponding to the pre-addition distribution value FVAn acquired in the W register 104a is acquired in the B register 105a. The LDB update command is executed. In the first result correspondence process (FIG. 42), the process of steps S1205 to S1208 is repeatedly executed until an affirmative determination is made in step S1208. The combination of the pre-addition distribution value FVAn and the flag data FDAn acquired in the W register 104a and the B register 105a in the distribution data acquisition process in step S1205 is a combination of FVA1 and FDA1 → a combination of FVA2 and FDA2 → FVA3 and. It is updated in the order of FDA3 combination. The numerical value "1280H" is the distribution value FVA1 before addition to the W register 104a and the B register 105a when the distribution data acquisition process (step S1205) is executed for the first time in the current processing time (game time). And is a numerical value for acquiring the combination of flag data FDA1. By executing the instruction "LD HL, 1280H" in step S1203, "1280H" is loaded into the HL register 107. As described above, the start address of the first special figure distribution table 64h is "9250H". "1280H" is the data calculated by "{(start address of the first special figure distribution table 64h) -9000H} x 8". The acquired data designation data set in the HL register 107 is used when the LDB update instruction is executed in the distribution data acquisition process (step S1205).

On the other hand, when "1" is set in the second special figure flag (step S1202: YES), the instruction "LD HL, 1298H" is executed (step S1204). "LD" is an LD instruction, "HL" is a content for designating the HL register 107 as a transfer destination, and "1298H" is 2-byte numerical information. In the distribution data acquisition process (step S1205) described later, when "1" is set in the second special figure flag, it is set in the second special figure distribution table 64j (FIG. 41 (c)). “LDB W, (HL +). 4 to acquire the pre-addition distribution value FVBn (n is any of 1 to 3) of the three pre-addition distribution values FVB1 to FVB3 in the W register 104a. The LDB update instruction "LDB B, (HL +) .2" is executed, and the flag data FDBn corresponding to the pre-addition distribution value FVBn acquired in the W register 104a is acquired in the B register 105a. The LDB update command is executed. As described above, in the first result correspondence process (FIG. 42), the processes of steps S1205 to S1208 are repeatedly executed until an affirmative determination is made in step S1208. The combination of the pre-addition distribution value FVBn and the flag data FDBn acquired in the W register 104a and the B register 105a in the distribution data acquisition process in step S1205 is a combination of FVB1 and FDB1 → a combination of FVB2 and FDB2 → FVB3 and. It is updated in the order of the combination of FDB3. The numerical value "1298H" is the distribution value FVB1 before addition to the W register 104a and the B register 105a when the distribution data acquisition process (step S1205) is executed for the first time in the current processing times (game times). And, it is a numerical value for acquiring the combination of flag data FDB1. By executing the instruction "LD HL, 1298H" in step S1204, "1298H" is loaded into the HL register 107. As described above, the start address of the second special figure distribution table 64j is "9253H". "1298H" is the data calculated by "{(start address of the second special figure distribution table 64j) -9000H} x 8". The acquired data designation data set in the HL register 107 is used when the LDB update instruction is executed in the distribution data acquisition process (step S1205).

When the process of step S1203 is performed or the process of step S1204 is performed, the distribution data acquisition process is executed (step S1205). As described above, in the distribution data acquisition process, when "1" is not set in the second special figure flag, it is set in the first special figure distribution table 64h (FIG. 41 (b)) 3 One of the pre-addition distribution values FVA1 to FVA3, the pre-addition distribution value FVAn, is set in the W register 104a, and the flag data FDAn corresponding to the pre-addition distribution value FVAn set in the W register 104a. Is set in the B register 105a. Further, as described above, in the distribution data acquisition process (step S1205), when "1" is set in the second special figure flag, the second special figure distribution table 64j (FIG. 41 (c)). The pre-addition distribution value FVBn of one of the three pre-addition distribution values FVB1 to FVB3 set in is set in the W register 104a, and the pre-addition distribution value FVBn set in the W register 104a is set. The flag data FDBn corresponding to is set in the B register 105a. The details of the distribution data acquisition process will be described later.

After that, in a state where the pre-addition distribution value FVAn or the pre-addition distribution value FVBn is stored in the W register 104a, "20" is added to the value of the W register 104a (step S1206). As a result, when any of the first pre-addition distribution values FVA1 and FVB1 is stored in the W register 104a before addition, the value of the W register 104a is updated to the corresponding first distribution value. Further, when any of the second pre-addition distribution values FVA2 and FVB2 are stored in the W register 104a before addition, the value of the W register 104a is updated to the corresponding second distribution value, and at the same time. When any of the third pre-addition distribution values FVA3 and FVB3 are stored in the W register 104a before addition, the value of the W register 104a is updated to the corresponding third distribution value.

After that, the value of the W register 104a is subtracted from the value of the A register 104b (step S1207). As described above, the numerical information (random number of the jackpot type) acquired from the jackpot type counter C2 is set in the A register 104b in step S1201, and any distribution value is set in the W register 104a in step S1206. It will be in the set state. Therefore, when the process of step S1207 is executed for the first time in the current process times (game times), the process of subtracting the distribution value from the numerical information acquired from the jackpot type counter C2 is executed in the step S1207. .. Further, when the processing of step S1207 is executed at the (m + 1) th time (m is 1 or 2) in the current processing round (game round), in the step S1207, m pieces are obtained from the numerical information acquired from the jackpot type counter C2. The process of subtracting the (m + 1) th distribution value from the numerical information after the distribution value is subtracted is executed.

After that, it is determined whether or not the value of the A register 104b is less than "0" (step S1208). When the calculation result of step S1207 is "0" or more, the value of the carry flag becomes "0", and when the calculation result is less than "0", "1" is set in the carry flag. Will be done. In step S1208, an affirmative determination is made when the carry flag is set to "1". If the value of the A register 104b is not less than "0" (step S1208: NO), the process returns to step S1205. Then, the processes of steps S1205 to S1208 are repeatedly executed until an affirmative determination is made in step S1208. As a result, the distribution value is subtracted from the numerical information acquired from the jackpot type counter C2 to the A register 104b in step S1201 in the order of the first distribution value → the second distribution value → the third distribution value. The flag data FDAn and FDBn corresponding to the distribution value whose calculation result is less than "0" can be specified as the winning flag data. In step S1208, each jackpot result is subject to distribution determination in the order of 4R high-accuracy jackpot result → 8R high-accuracy jackpot result → 16R high-accuracy jackpot result, and the swing corresponding to the jackpot type random number acquired from the jackpot type counter C2. The result of the minute determination is specified.

When an affirmative determination is made in step S1208, the flag data FDAn and FDBn stored in the B register 105a are set in the distribution data area 162 in the work area 121 for specific control (step S1209). In step S1209, when the first flag data FDA1 and FDB1 corresponding to the 4R high-accuracy jackpot result are set in the distribution data area 162, "1" is set in the 4R high-accuracy flag 162a and the 8R high-accuracy jackpot. When the second flag data FDA2 and FDB2 corresponding to the result are set in the distribution data area 162, "1" is set in the 8R high accuracy flag 162b. Further, when the third flag data FDA3 and FDB3 corresponding to the 16R high accuracy jackpot result are set in the distribution data area 162, "1" is set in the 16R high accuracy flag 162c. As a result, the result of the distribution determination can be grasped by the main CPU 63.

Next, the distribution data acquisition process executed in step S1205 of the first result correspondence process (FIG. 42) will be described. Hereinafter, a case where the distribution data acquisition process is executed will be described by taking as an example a case where the distribution data acquisition process is executed using the first special figure distribution table 64h.

FIG. 43A is an explanatory diagram for explaining the program contents of the distribution data acquisition process. Further, FIG. 43 (b) is an explanatory diagram for explaining how the first pre-addition distribution value FVA1 is set in the W register 104a, and FIG. 43 (c) shows the first flag data FDA1 in the B register 105a. It is explanatory drawing for demonstrating how is set.

As shown in FIG. 43 (a), "1901" to "1903" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

As shown in FIG. 43 (a), the command "LDB W, (HL +) .4" is set in the line number of "1901". "LDB" is an LDB update instruction by the LDB update execution circuit 161. "W" is a content for designating the W register 104a as a "transfer destination", and "(HL +)" is stored in the HL register 107. It is the content to specify the byte data as the acquisition data specification data and to instruct to update the acquisition data specification data stored in the HL register 107 after loading the data, and "4" is "4" as the acquisition bit number specification data. 4 ”is the content to be set.

44 (a) to 44 (e) show the start address of the distribution table 64h for the first special figure, the acquisition data designation data in the LDB update command (“LDB W, (HL +) .4”), the acquisition start address, and It is explanatory drawing for demonstrating the acquisition start bit and the acquisition data designation data after update. As described above, the numerical information "1280H" is set in the HL register 107 in step S1203 of the first result correspondence process (FIG. 42). As shown in FIG. 44 (b), the “1280H” is acquired data designation data when the LDB instruction “LDB W, (HL +) .4” is executed for the first time. As described above, the start address of the distribution table 64h for the first special figure is “9250H” (see FIG. 44 (a)). "1280H" is numerical information calculated by the formula "{(start address of the first special figure distribution table 64h) -9000H} x 8". As shown in FIG. 44 (b), the 3rd to 14th bits in the acquired data designation data (“1280H”) are “9250H” (FIG. 44 (FIG. 44), which is the start address of the first special figure distribution table 64h. The data of the 0th to 11th bits in a)) are set.

As described above, the acquisition start address is the reference address (“9000H”) of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquired data specified data by “8” (“1000B”). ) Is added. When the LDB update instruction is executed with "1280H" stored in the HL register 107 as the acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1280H" by "8". Is calculated by the calculation of adding "9250H". As shown in FIG. 44 (c), the data of the 0th to 11th bits at the acquisition start address is the data of the 3rd to 14th bits of the acquisition data designated data (start of the first special figure distribution table 64h). The data in the 0th to 11th bits in the address), and the data in the 12th to 15th bits in the acquisition start address are the data in the 12th to 15th bits in the reference address of the data table. The acquisition start address "9250H" is the start address of the first special figure distribution table 64h.

As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte of the acquisition data designated data and "000000111H". When the LDB update instruction is executed with "1280H" stored in the HL register 107 as the acquisition data designation data, the acquisition start bit is the lower 1 byte ("10000000B") and "00000011H" of the acquisition data designation data. It becomes "0000000000B" ("0") which is a logical product of. As shown in FIG. 44 (d), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the data of the lower 3 bits (0th to 2nd bits) in the acquisition data designated data. , The data of the upper 5 bits (3rd to 7th bits) in the acquisition start bit is "0".

Since the numerical value "4" is set as the acquisition bit designation data in the LDB update instruction "LDB W, (HL +) .4", the number of acquisition bits is obtained by adding "1" to the "4". It becomes "5" obtained. When the LDB update instruction "LDB W, (HL +) .4" is executed while "1280H" is stored in the HL register 107, as shown in FIG. 43 (b), the first special figure vibration is performed. In the minute table 64h, the data for the number of acquisition bits (5 bits) set after the acquisition start bit (0th bit) of the area corresponding to the acquisition start address "9250H" (distribution before addition). The value FVA1) is loaded into the 0th to 4th bits (lower 5 bits) of the W register 104a which is the transfer destination, and the 5th to 7th bits (upper 3 bits) of the W register 104a are "0". Be masked. As a result, the determination value HV1 can be set in the W register 104a.

As described above, the number of acquisition bits in the LDB update instruction "LDB W, (HL +) .4" is "5". Therefore, in the LDB update instruction, after the 5-bit data is loaded into the 0th to 4th bits of the W register 104a, the number of acquired bits (“5”) is set in the value (“1280H”) of the HL register 107. After being added, the value of the HL register 107 is updated to "1285H" as shown in FIG. 44 (e).

"1285H" is numerical information in which the acquisition start address is "9250H" and the acquisition bit is the fifth bit when the next LDB update instruction is executed with the "1285H" as the acquisition data designation data. .. In this way, when the LDB update instruction is executed and the acquired data designation data stored in the HL register 107 is updated, the LDB update instruction is executed next to the LDB update instruction by the number of acquired bits in the LDB update instruction. The data acquisition start position in the LDB update instruction shifts.

In this way, the pre-addition distribution value FVA1 acquired from the distribution table 64h for the first special figure is set in the W register 104a by using the LDB update command, and the acquired data designation data is updated. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111, and the 0th to 0th of the acquisition designation data. The process of specifying the acquisition start bit corresponding to the second bit (lower 3 bits) and the pre-addition distribution value FVA1 acquired from the first special figure distribution table 64h are the 0th to 4th bits of the W register 104a. The process of loading to (lower 5 bits), the process of masking the 5th to 7th bits (upper 3 bits) of the W register 104a with "0", and the process of adding the number of acquired bits to the value of the HL register 107. And the process of updating the acquired data specified data can be executed with one instruction. These processes are executed by the LDB update execution circuit 161. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The command "LDB B, (HL +) .2" is set in the line number of "1902". “LDB” is an LDB update instruction by the LDB update execution circuit 161. “B” is a content that specifies B register 105a as a “transfer destination”, and “(HL +)” is stored in HL register 1072. It is the content to specify the byte data as the acquisition data specification data and to instruct to update the acquisition data specification data stored in the HL register 107 after the data transfer, and "2" is "2" as the acquisition bit number specification data. Is the content to set.

45 (a) to 45 (c) show the acquisition data designation data, the acquisition start address, the acquisition start bit, and the updated acquisition data designation data in the LDB instruction (“LDB B, (HL +) .2”). It is explanatory drawing for demonstrating. As described above, the acquisition start address is the reference address (“9000H”) of the data table stored in the TP register 111 for the quotient data of the operation of dividing the acquired data specified data by “8” (“1000B”). ) Is added. When the LDB update instruction is executed with "1285H" stored in the HL register 107 as the acquisition data designation data, the acquisition start address is "9000H" for the quotient data of the operation of dividing "1285H" by "8". Is calculated by the calculation of adding "9250H". As shown in FIG. 45 (a), the data of the 0th to 11th bits at the acquisition start address is the data of the 3rd to 14th bits of the acquisition data designated data, and the data of the twelfth to the twelfth at the acquisition start address. The 15th bit data is the 12th to 15th bit data at the reference address of the data table. As described above, the acquisition start address "9250H" is the start address of the first special figure distribution table 64h.

As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte of the acquisition data designated data and "000000111H". When the LDB update instruction is executed with "1285H" stored in the HL register 107 as the acquisition data designation data, the acquisition start bit is the lower 1 byte ("10000101B") and "00000011H" of the acquisition data designation data. It becomes "00000101B" ("5") which is a logical product of. As shown in FIG. 45 (b), the data of the lower 3 bits (0th to 2nd bits) in the acquisition start bit is the data of the lower 3 bits (0th to 2nd bits) in the acquisition data designated data. , The data of the upper 5 bits (3rd to 7th bits) in the acquisition start bit is "0".

Since the numerical value "2" is set as the acquisition bit designation data in the LDB update instruction "LDB B, (HL +) .2", the number of acquisition bits is obtained by adding "1" to the "2". It becomes "3" to be obtained. When the LDB update instruction "LDB B, (HL +) .2" is executed while "1285H" is stored in the HL register 107, as shown in FIG. 43 (c), the first special figure vibration is performed. Data for the number of acquisition bits (3 bits) set after the acquisition start bit (fifth bit) of the area corresponding to the acquisition start address "9250H" in the minute table 64h (flag data FDA1). Is loaded into the 0th to 2nd bits (lower 3 bits) of the D register 106a, which is the transfer destination, and the 3rd to 7th bits (upper 5 bits) of the D register 106a are masked with "0". .. As a result, the flag data FDA1 corresponding to the pre-addition distribution value FVA1 stored in the WA register 104 can be set in the D register 106a.

As described above, the number of acquisition bits in the LDB update instruction "LDB B, (HL +) .2" is "3". Therefore, in the LDB update instruction, after the 3-bit data is loaded into the 0th to 2nd bits of the B register 105a, the number of acquired bits (“3”) is set in the value (“1285H”) of the HL register 107. After being added, the value of the HL register 107 is updated to "1288H" as shown in FIG. 45 (c).

"1288H" is numerical information in which the acquisition start address is "9251H" and the acquisition bit is the 0th bit when the next LDB update instruction is executed with the "1288H" as the acquisition data designation data. .. In this way, when the LDB update instruction is executed and the acquired data designation data stored in the HL register 107 is updated, the LDB update instruction is executed next to the LDB update instruction by the number of acquired bits in the LDB update instruction. The data acquisition start position in the LDB update instruction shifts.

By executing the LDB update instruction "LDB W, (HL +) .4" and the LDB update instruction "LDB B, (HL +) .2", the pre-addition distribution value FVA1 is added to the W register 104a and the D register 106a. And the flag data FDA1 is set. Further, by increasing the value of the HL register 107 by "8" (the sum of "5" and "3"), the LDB update instruction "LDB W, (HL +) .4" and "LDB B, (HL +). The acquisition start address in the LDB update command of "2" is increased by "1".

In this way, the flag data FDA1 acquired from the distribution table 64h for the first special figure is set in the B register 105a by using the LDB update instruction, and the acquired data designation data is updated. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the acquisition data designation data and the reference address of the data table set in the TP register 111, and the 0th to 2nd bits of the acquisition designation data. The process of specifying the acquisition start bit corresponding to the bit (lower 3 bits) and the flag data FDA1 acquired from the first special figure distribution table 64h are the 0th to 2nd bits (lower 3 bits) of the B register 105a. The process of loading into the B register 105a, the process of masking the 3rd to 7th bits (upper 5 bits) of the B register 105a with "0", and the process of adding the number of acquired bits to the value of the HL register 107 to obtain the acquired data designation data. The update process can be executed with a single instruction. These processes are executed by the LDB update execution circuit 161. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

An instruction "RET" is set in the line number of "1903". As described above, the distribution data acquisition process is a subroutine executed in step S1205 of the first result correspondence process (FIG. 42). Therefore, when the instruction "RET" is executed, the process proceeds to step S1206 of the first result correspondence process.

As described above, in the first result correspondence process (FIG. 42), the processes of steps S120 to S1208 are repeatedly executed until a positive determination is made in step S1208. FIG. 46 shows the number of times the LDB update instruction “LDB W, (HL +) .4” and the LDB update instruction “LDB B, (HL +) .2” are executed, and the W register 104a and the B register 105a by these LDB update instructions. It is explanatory drawing for demonstrating with the data acquired in. As shown in FIG. 46, in the second line number “1901”, “LDB W, (HL +) .4” is executed with “1288H” as the acquisition data designation data, and the pre-addition distribution value FVA2 is executed in the W register 104a. Is set. Then, the value of the HL register 107 is updated to "128DH". Further, in the second line number "1902", "LDB B, (HL +) .2" is executed with "128DH" as the acquisition data designation data, and the flag data FD2 corresponding to the pre-addition distribution value FVA2 is the B register. It is set to 105a. Then, the value of the HL register 107 is updated to "1290H".

In this way, by using the first special figure distribution table 64h to repeatedly execute the distribution data acquisition process, the addition pre-swing set in the first special figure distribution table 64h A combination of the fractional value FVAn and the flag data FDAn can be sequentially loaded into the W register 104a and the B register 105a one by one. Further, by using the second special figure distribution table 64j to repeatedly execute the distribution data acquisition process (FIG. 43 (a)), the first special figure distribution table 64h is used. As in the case of repeatedly executing the distribution data acquisition process (FIG. 43 (a)), the combination of the pre-addition distribution value FVBn and the flag data FDBn set in the second special figure distribution table 64j is used. One set can be loaded into the W register 104a and the B register 105a in order.

Next, prior to the description of the process of steps S121-10 to S1216 of the first result correspondence process (FIG. 42), the setting mode of the variation type number will be described. As already explained, the variation type number includes the result of the hit / fail judgment, the result of the distribution judgment, the result of the reach occurrence lottery, and the stop result data corresponding to the number of hold of the special figure hold areas 115 and 116 from the change pattern table described later. It is data for acquiring display duration data.

FIG. 47 is an explanatory diagram for explaining the correspondence between the variation type number, the result of the hit / fail determination, the result of the distribution determination, the result of the reach generation lottery, and the number of reservations in the first special figure reservation area 115. First, a case where the variable display is started triggered by the hold information of the first special figure hold area 115 will be described. As shown in FIG. 47, "0" is set in the type number counter in the work area 121 for specific control in response to the occurrence of the 4R high accuracy jackpot result, and the type number corresponds to the occurrence of the 8R high accuracy jackpot result. "1" is set in the counter, "2" is set in the type number counter in response to the occurrence of the 16R high accuracy jackpot result, and "3" is set in the type number counter in response to the occurrence of the small hit result. To. In addition, if a loss result occurs in the hit / fail judgment and the reach effect is not won in the reach generation lottery described later, if the number of holds in the first special figure hold area 115 is "0", the type number counter is set to "4". Is set, and if the hold number is "1", "5" is set in the type number counter, and if the hold number is "2", "6" is set in the type number counter, and the hold number is set. If it is "3", "7" is set in the type number counter. Furthermore, if a missed result occurs in the hit / fail judgment and the reach effect is won in the reach generation lottery, if the number of holds in the first special figure hold area 115 is "0", "8" is set in the type number counter. If the number of holdings is "1", "9" is set in the type number counter, if the number of holdings is "2", "10" is set in the type number counter, and the number of holdings is "3". If so, "11" is set in the type number counter.

Next, a case where the variable display is started triggered by the hold information of the second special figure hold area 116 will be described. As shown in FIG. 47, "12" is set in the type number counter in the work area 121 for specific control in response to the occurrence of the 4R high accuracy jackpot result, and the type number corresponds to the occurrence of the 8R high accuracy jackpot result. "13" is set in the counter, "14" is set in the type number counter corresponding to the occurrence of the 16R high accuracy jackpot result, and "15" is set in the type number counter in response to the occurrence of the small hit result. To. In addition, if a loss result occurs in the hit / fail judgment and the reach effect is not won in the reach generation lottery described later, if the number of holds in the first special figure hold area 115 is "0", the type number counter is set to "16". Is set, and if the hold number is "1", "17" is set in the type number counter, and if the hold number is "2", "18" is set in the type number counter, and the hold number is set. If it is "3", "19" is set in the type number counter. Furthermore, if a missed result occurs in the hit / fail judgment and the reach effect is won in the reach generation lottery, if the number of holds in the first special figure hold area 115 is "0", "20" is set in the type number counter. If the number of holdings is "1", "21" is set in the type number counter, if the number of holdings is "2", "22" is set in the type number counter, and the number of holdings is "3". If so, "23" is set in the type number counter.

Returning to the description of the first result correspondence process (FIG. 42), after performing the process of step S1209, it is determined whether or not "1" is set in the second special figure flag in the work area 121 for specific control. If "1" is not set in the second special figure flag (step S1210: NO), "0" is set in the variation type number counter (step S1211). In this way, when a jackpot result occurs in the hit / fail determination executed with the hold information of the first special figure hold area 115 as a trigger, "0" is first set in the variation type number counter.

On the other hand, when "1" is set in the second special figure flag (step S1210: YES), "12" is set in the variation type number counter (step S1212). In this way, when a jackpot result occurs in the hit / fail determination executed with the hold information of the second special figure hold area 116 as a trigger, "12" is first set in the variable type number counter.

When the process of step S1211 is performed or the process of step S1212 is performed, it is determined whether or not "1" is set in the 8R high accuracy flag 162b (step S1213), and the 8R high accuracy flag 162b is determined. When "1" is set in (step S1213: YES), the value of the variable type number counter is incremented by 1 (step S1214). As a result, when "1" is not set in the second special figure flag, "1" corresponding to the 8R high-accuracy jackpot result can be set in the variation type number counter, and the second special figure flag can be set. 2 When "1" is set in the special figure flag, it can be set to the state in which "13" corresponding to the 8R high-accuracy jackpot result is set in the variation type number counter.

When a negative determination is made in step S1213, it is determined whether or not "1" is set in the 16R high accuracy flag 162c (step S1215), and "1" is set in the 16R high accuracy flag 162c. If so (step S1215: YES), the value of the variation type number counter is added by 2 (step S1216), and the first result correspondence process is terminated. By adding 2 to the value of the variation type number counter, if "1" is not set in the 2nd special figure flag, "2" corresponding to the 16R high accuracy jackpot result is set in the variation type number counter. When "1" is set in the second special figure flag, it is assumed that "14" corresponding to the 16R high-accuracy jackpot result is set in the variation type number counter. be able to.

If "1" is not set in any of the 8R high accuracy flag 162b and the 16R high accuracy flag 162c (step S1213: NO, step S1215: NO), the first result correspondence process is terminated as it is. As a result, when "1" is not set in the second special figure flag, it is possible to maintain the state in which "0" corresponding to the 4R high-accuracy jackpot result is set in the variation type number counter. When "1" is set in the second special figure flag, it is possible to maintain the state in which "12" corresponding to the 4R high-accuracy jackpot result is set in the variation type number counter.

Next, the second result correspondence process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The second result correspondence process is executed in step S1010 of the special figure variation start process (FIG. 35). The second result correspondence process is executed by using the program for specific control and the data for specific control.

In the second result correspondence process, first, it is determined whether or not "1" is set in the small hit flag 158b in the hit / miss data area 158 (step S1301), and when "1" is set in the small hit flag 158b. In (step S1301: YES), it is determined whether or not "1" is set in the second special figure flag in the work area 121 for specific control (step S1302). If a negative determination is made in step S1302, "3" is set in the variation type number counter (step S1303), and the second result correspondence process is terminated. In this way, when a small hit result occurs in the hit / fail determination executed with the hold information of the first special figure hold area 115 as a trigger, "3" is set in the variation type number counter.

If an affirmative determination is made in step S1302, "15" is set in the variation type number counter (step S1304), and the second result correspondence process is terminated. In this way, when a small hit result occurs in the hit / fail determination executed with the hold information of the second special figure hold area 116 as a trigger, "15" is set in the variation type number counter.

When a negative determination is made in step S1301, that is, when a failure result is obtained in the hit / fail determination, the information for the reach generation lottery among the information stored in the execution area 117 for the special figure, that is, the reach random number counter C3 The numerical information of any of 0 to 238 acquired from is grasped (step S1305), and the reach generation lottery table is read from the main side ROM 64 (step S1306). In the reach generation lottery table, a winning value corresponding to the result of winning the reach effect and a winning value corresponding to the result of not winning the reach effect are set so that the probability of winning the reach effect is about 1/10. ing.

After that, it is determined whether or not the reach effect has been won by collating the numerical information grasped in step S1305 with the reach generation lottery table read out in step S1306 (step S1307), and when the reach effect is won (step S1307). In S1307: YES), "1" is set in the reach generation flag provided in the work area 121 for specific control (step S1308). The reach generation flag is a flag that enables the main CPU 63 to grasp that the reach effect has been won in the reach generation lottery.

When a negative determination is made in step S1307 or when the process of step S1308 is performed, it is determined whether or not "1" is set in the second special figure flag in the work area 121 for specific control. (Step S1309) When "1" is not set in the second special figure flag (step S1309: NO), it is determined whether or not "1" is set in the reach generation flag (step S1310). .. If a negative determination is made in step S1310, "4" is set in the variation type number counter (step S1311). In this way, if a missed result occurs in the win / fail judgment executed triggered by the hold information of the first special figure hold area 115 and the reach effect is not won in the reach generation lottery, the variable type number counter is first set. "4" is set.

If an affirmative determination is made in step S1310, "8" is set in the variation type number counter (step S1312). In this way, when a missed result occurs in the hit / fail judgment executed with the hold information of the first special figure hold area 115 as a trigger and the reach effect is won in the reach generation lottery, first, "8" is set in the variable type number counter. "Is set.

When the processing of step S1311 is performed or the processing of step S1312 is performed, the number of holdings of the first special figure holding area 115 is added to the value of the variation type number counter (step S1313), and the second step is performed. End the result handling process. By adding the number of holdings of the first special figure holding area 115 to the value of the variation type number counter, an error result occurs and a reach occurs in the hit / fail judgment executed with the holding information of the first special figure holding area 115 as a trigger. If the reach effect is not won in the lottery, if the number of holds in the first special figure hold area 115 is "0", "4" is set in the type number counter, and the number of holds is "1". If, "5" is set in the type number counter, and if the number of holds is "2", "6" is set in the type number counter, and the number of holds is "3". If so, "7" is set in the type number counter. In addition, when a loss result occurs in the hit / fail judgment and the reach effect is won in the reach generation lottery, if the number of holds in the first special figure hold area 115 is "0", "8" is set in the type number counter. If the number of holds is "1", the type number counter is set to "9", and if the number of holds is "2", the type number counter is set to "10". If the number of holdings is "3", the type number counter is set to "11".

When an affirmative determination is made in step S1309, it is determined whether or not "1" is set in the reach generation flag (step S1314). If a negative determination is made in step S1314, "16" is set in the variation type number counter (step S1315). In this way, if a missed result occurs in the win / fail judgment executed with the hold information of the second special figure hold area 116 as a trigger and the reach effect is not won in the reach generation lottery, the variable type number counter is first set. "16" is set.

If an affirmative determination is made in step S1314, "20" is set in the variation type number counter (step S1316). In this way, when a missed result occurs in the win / fail judgment executed with the hold information of the second special figure hold area 116 as a trigger and the reach effect is won in the reach generation lottery, first, the variable type number counter is set to "20". "Is set.

When the processing of step S1315 is performed or the processing of step S1316 is performed, the number of holdings of the second special figure holding area 116 is added to the value of the variation type number counter (step S1317), and the second step is performed. End the result handling process. By adding the number of holdings of the second special figure holding area 116 to the value of the variation type number counter, an error result occurs and a reach occurs in the hit / fail judgment executed with the holding information of the second special figure holding area 116 as a trigger. If the reach effect is not won in the lottery, if the number of reservations in the second special figure reservation area 116 is "0", "16" is set in the type number counter, and the number of reservations is "1". If, "17" is set in the type number counter, and if the number of holds is "2", "18" is set in the type number counter, and the number of holds is "3". If so, "19" is set in the type number counter. In addition, when a loss result occurs in the hit / fail judgment and the reach effect is won in the reach generation lottery, if the number of holds in the second special figure hold area 116 is "0", "20" is set in the type number counter. If the number of holds is "1", the type number counter is set to "21", and if the number of holds is "2", the type number counter is set to "22". If the number of holdings is "3", the type number counter is set to "23".

Returning to the description of the special figure variation start process (FIG. 35), when the process of step S1009 is performed or the process of step S1010 is performed, the variation start address acquisition process is executed (step S1011). In the variation start address acquisition process, the start address of the variation pattern table corresponding to the variation type number stored in the variation type number counter is acquired from the variation start table 64r stored in the main ROM 64 to the HL register 107. .. The main ROM 64 stores 24 variation pattern tables corresponding to the result of the hit / fail determination, the result of the distribution determination, the result of the reach generation lottery, and the number of reservations in the first special figure reservation area 115. In the fluctuation pattern table, the stop result data and the display duration data of the fluctuation display corresponding to the result of the hit / fail judgment, the result of the distribution judgment, the result of the reach occurrence lottery, and the number of holdings of the special figure holding areas 115 and 116 are set. Has been done. The start address of the variation pattern table consists of 2 bytes, and the upper 4 bits of the start address are all "9H". In the fluctuation start table 64r, the start address of the fluctuation pattern table corresponding to the result of the hit / fail judgment based on the fluctuation type number, the result of the distribution judgment, the result of the reach generation lottery, and the number of holdings of the special figure holding areas 115 and 116. The lower 12 bits of the start address are set as the data for acquiring.

FIG. 49 is an explanatory diagram for explaining the data configuration of the fluctuation start table 64r, and FIG. 50 (a) is an explanatory diagram for explaining the acquisition mode of the start address of the fluctuation pattern table.

As shown in FIG. 49, the fluctuation start table 64r is stored in the address range of "9135H" to "9158H" in the main ROM 64. In the variation start table 64r, the lower 12 bits at the start addresses SB0 to SB23 of the variation pattern table corresponding to the variation type numbers 0 to 23 are set. The variation start table 64r is a data structure in which the lower 12 bits of the two start addresses SBn are set in the area corresponding to the three consecutive addresses. For example, the lower 12 bits of the start address SB0 and the lower 12 bits of the start address SB1 are set in an area of a total of 3 bytes corresponding to "9135H" to "9137H", and the lower 12 bits of the start address SB2 and the start address. The lower 12 bits of SB3 are set in an area of a total of 3 bytes corresponding to "9138H" to "913AH".

In the variable start table 64r, the lower 12 bits of the 24 start addresses SB0 to SB23 are set in a storage area of 36 bytes in total. On the other hand, assuming that the entire data (2 bytes) of one start address SBn (n is an integer of 0 to 23) is stored in the area corresponding to two consecutive addresses, 24 start addresses are used. A 48-byte storage area is required in the main ROM 64 in order to store the fluctuation start table 64r in which SB0 to SB23 are set. In this way, by adopting a data structure in which the lower 12 bits of the two start addresses SBn are set in the area corresponding to the three consecutive addresses, the data capacity of the variable start table 64r in the main ROM 64 is reduced. be able to.

In the variation start address acquisition process in step S1011 of the special figure variation start process (FIG. 35), as shown in FIG. 50 (a), the variation type number “n” (n is an integer of 0 to 23) is assigned. The lower 12 bits of the start address SBn of the corresponding variation pattern table are acquired. For example, when the variation type number is "0", "5CFH" which is the lower 12 bits of the start address SB0 is acquired, and when the variation type number is "1", the lower 12 bits of the start address SB1 are acquired. The bit "5D9H" is acquired.

Next, the program contents of the variation start address acquisition process executed in step S1011 of the special figure variation start process (FIG. 35) will be described with reference to the explanatory diagram of FIG. 50 (b). As shown in FIG. 50 (b), "2001" to "2005" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LD W, (HSBCNT)" is set in the line number of "2001". “LD” is an LD instruction, and “W” is a content that specifies the W register 104a as a transfer destination. “HSBCNT” is the address of the variable type number counter in the work area 121 for specific control, and “(HSBCNT)” is the content of loading the data stored in the variable type number counter into the “forwarding destination”. As described above, the variable type number counter stores numerical data of any of 0 to 23. By executing "LD W, (HSBCNT)", the data of the variable type number counter is loaded into the W register 104a of the "transfer destination".

The instruction "LD B, 0CH" is set in the line number of "2002". "LD" is an LD instruction, "B" is a content that specifies the B register 105a as a transfer destination, and "0CH" is a content that specifies numerical data of "0CH" ("12") as a "transfer source". Is. “0CH” is the number of bits (number of acquisition bits) of the address data acquired from the variation start table 64r (FIG. 49) in the address acquisition execution process (FIG. 33 (e)) called by the row number “2004” described later. be. By executing "LD B, 0CH", the number of bits ("12") of the address data acquired from the fluctuation start table 64r is set in the B register 105a of the "transfer destination".

The command "LD HL, TBL_HDK_B" is set in the line number of "2003". “LD” is an LD instruction, and “HL” is a content that specifies the HL register 107 as a transfer destination. "TBL_HDK_B" is 2-byte numerical data for using the acquisition start address as the start address of the variable start table 64r, and is specifically "09A8H". By executing "LD HL, TBL_HDK_B", "09A8H" is loaded into the HL register 107 of the "transfer destination".

"TBL_HDK_B" is calculated by the formula "{(start address of variable start table 64r) -9000H} x 8". The data of the 0th to 11th bits at the start address "9135H" are set in the 3rd to 14th bits in "TBL_HDK_B". As described above, in the LDB instruction, the data of the 3rd to 14th bits in the acquisition data designation data is set to the 0th to 11th bits of the acquisition start address, and the 12th to 15th bits of the acquisition start address are set. The 12th to 15th bit data at the reference address (“9000H”) of the data table is set. By setting "TBL_HDK_B" calculated by the formula of "{(start address of variable start table 64r) -9000H} x 8" as acquisition data designation data, the start address of the variable start table 64r is acquired. Can be.

In the address acquisition execution process (FIG. 33 (e)) called by the line number "2004", when the value of the variation type number counter is "0", "09A8H" stored in the HL register 107 specifies the acquisition data. Used as data. On the other hand, when the value of the variation type number counter is "1" or more, the numerical information stored in the HL register 107 becomes the numerical information corresponding to the value of the variation type number counter before the LDB instruction is executed. Be changed.

An instruction "CALLS LDBADGET" is set in the line number of "2004". “LDBADGET” is the address acquisition execution process already described with reference to FIG. 33 (e). The instruction "CALLS LDBADGET" is an instruction for calling a subroutine called an address acquisition execution process. Although the details will be described later, the start address (any of SB0 to SB23) corresponding to the value of the variation type number counter is set in the HL register 107 by executing the address acquisition execution process at the line number "2004". To. When the subroutine of the address acquisition execution process is completed, the process proceeds to the line number of "2005".

An instruction "RET" is set in the line number of "2005". As described above, the variation start address acquisition process is a subroutine executed in step S1011 of the special figure variation start process (FIG. 35). Therefore, when the instruction "RET" is executed, the process proceeds to step S1012 of the special figure variation start process (FIG. 35).

Next, refer to FIG. 33 (e) again for the case where the address acquisition execution process (FIG. 33 (e)) is executed at the line number “2004” of the variable start address acquisition process (FIG. 50 (b)). I will explain while.

As described above, "LDBADGET" is set for the line number "1701", but since this is not an instruction, the line number "1701" proceeds to the line number "1702" without executing any instruction. ..

As described above, in the variable start address acquisition process (FIG. 50 (b)), the number of bits (number of acquired bits) to be acquired from the variable start table 64r is specified in the B register 105a "0CH" ("12"). Is set. Therefore, by executing "LD A, B" at the line number "1702", "0CH" is set in the A register 104b of the "transfer destination".

As described above, in the variable start address acquisition process (FIG. 50 (b)), the value of the variable type number counter (an integer of 0 to 23) is set in the W register 104a. Further, as described above, "0CH", which is the number of acquired bits, is stored in the A register 104b. Therefore, when "MUL W, A" is executed at the line number "1703", the calculation result of "(value of variable type number counter) x 0CH" is stored in the WA register 104. As described above, in the line number “2003” of the variable start address acquisition process (FIG. 50 (b)), the HL register 107 has the acquired data designation data (“0” corresponding to the value of the variable type number counter (“0”). 09A8H ") is stored. For the data of the calculation result of "(value of variable type number counter) x (number of acquired bits)", the acquired data specified data stored in the HL register 107 is changed to the data corresponding to the value of the variable type number counter. Used for.

As described above, in the line number "1603" of the variable start address acquisition process (FIG. 50 (b)), the acquired data designation data ("09A8H" corresponding to the value of "0" in the variable type number counter is stored in the HL register 107. ") Is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(value of variable type number counter) x (number of acquired bits)". By adding the calculation result data of "(variable type number counter value) x (number of acquired bits)" stored in the WA register 104 to the acquired data designation data stored in the HL register 107. The acquired data designation data corresponding to the value of the variation type number counter can be stored in the HL register 107.

As described above, in the variable start address acquisition process (FIG. 50 (b)), "0CH" ("12") for designating the number of acquisition bits is set in the B register 105a. Therefore, by executing "LD A, B" at the line number "1705", "0CH" is set in the A register 104b of the "transfer destination". As described above, "0CH" stored in the B register 105a was also used in the calculation of "(value of variable type number counter) x (number of acquired bits)". In this way, "0CH" stored in the B register 105a in advance is used for the calculation of "(value of variable type number counter) × (number of acquired bits)" and also specifies the number of acquired bits in the LDB instruction. Is used to set the data for the A register 104b.

As described above, "0CH", which is the number of acquired bits, is stored in the A register 104b. Therefore, when "DEC A" is executed at the line number "1706", "0BH" is stored in the A register 104b. “0BH” is a value obtained by subtracting “1” from “12” which is the number of bits of data acquired from the fluctuation start table 64r.

As described above, when the LDB instruction "LDB HL, (HL) .A" is executed, the LDB execution circuit 157 performs an operation of adding 1 to the value of the A register 104b, and the value after the 1 addition. Is used as data for the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b at the line number "1706", the number of bits of the data acquired from the special figure special electric address table 64q in the LDB instruction can be set to "12". ..

As described above, the instruction "LDB HL, (HL) .A" is set in the line number of "1707". "LDB" is a transfer instruction called an LDB instruction already described, "HL" is a content that specifies an HL register 107 as a "transfer destination", and "(HL)" is a 2-byte stored in the HL register 107. Is the content for designating the data of 1 to the acquisition data designation data, and “A” is the content for designating the 1-byte data stored in the A register 104b as the acquisition bit number designation data. As described above, the HL register 107 is in a state in which the acquisition data designation data corresponding to the value of the variation type number counter is stored, and the A register 104b is "1" from the number of acquisition bits ("0CH"). Is stored in "0BH" obtained by subtracting. Further, the TP register 111 is in a state in which "9000H", which is a reference address of the data table, is stored. In this state, when the instruction "LDB HL, (HL) .A" is executed at the line number "1707", the variable type number counter is set in the 0th to 11th bits of the HL register 107 which is the transfer destination. The lower 12 bits of data at the start addresses SB0 to SB23 corresponding to the value of are loaded, and the 12th to 15th bits of the HL register 107 are masked with "0". Specifically, as shown in FIG. 50A, when the value of the variation type number counter is "0", the acquisition start address is "9135H" and the acquisition start bit is "0". The lower 12 bits of the start address SB0, "05CFH", are loaded into the 0th to 11th bits of the HL register 107. When the value of the variation type number counter is "1", the acquisition start address becomes "9136H" and the acquisition start bit becomes "4", and the start address is set to the 0th to 11th bits of the HL register 107. The lower 12 bits of SB1 "05D9H" are loaded. Furthermore, when the value of the variable type number counter is "2", the acquisition start address becomes "9138H" and the acquisition start bit becomes "0", which starts at the 0th to 11th bits of the HL register 107. The lower 12 bits of the address SB2, "05E1H", is loaded. In this way, every time the value of the fluctuation type counter increases by 1, the position where data acquisition is started is shifted by 12 bits in the fluctuation start table 64r (FIG. 49).

The acquisition data designation data of 2 bytes is configured by loading the lower 12 bits of the start addresses SB0 to SB23 acquired from the fluctuation start table 64r using the LDB instruction into the 0th to 11th bits of the HL register 107. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits and the reference address of the data table set in the TP register 111, and the 0th to 2nd bits (lower 3 bits) of the acquisition designation data. ), The process of specifying the acquisition start bit th, the process of loading the lower 12 bits of the start address SBn acquired from the variable start table 64r into the lower 12 bits of the HL register 107, and the process of loading the lower 12 bits of the HL register 107. The process of masking bits with "0" can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

As described above, the instruction "ADD HL, 9000H" is set in the line number of "1708". By executing "ADD HL, 9000H", "9000H", which is a reference address of the data table, is added to the value of the HL register 107. By executing "ADD HL, 9000H" at the line number "1708", the entire start address (any of the start addresses SB0 to SB23) corresponding to the value of the variation type number counter is set in the HL register 107. Can be in the state of being. Specifically, when the value of the variation type number counter is "n" (n is an integer of 0 to 23), the entire start address SBn is set in the HL register 107.

As described above, the instruction "RET" is set in the line number of "1709". The address acquisition execution process is a subroutine executed by the line number “2004” of the variable start address acquisition process (FIG. 50 (b)). Therefore, by executing the instruction "RET", the process proceeds to the line number "2005" of the variable start address acquisition process.

In this way, by using the LDB instruction, the lower 12 bits of the start addresses SB0 to SB23 can be acquired from the fluctuation start table 64r. Further, after the execution of the LDB instruction, the entire start addresses SB0 to SB23 can be acquired by adding "9000H" corresponding to the upper 4 bits common to the start addresses SB0 to SB23 to the lower 12 bits. can. Therefore, the address data set in the fluctuation start table 64r can be limited to the lower 12 bits of the start addresses SB0 to SB23. As a result, the data capacity of the variation start table 64r in the main ROM 64 can be reduced as compared with the configuration in which the entire 2-byte start addresses SB0 to SB23 are set in the variation start table 64r.

Returning to the description of the special figure variation start process (FIG. 35), after the variation start address acquisition process is executed in step S1011, the variation information setting process is executed (step S1012). In the variation information setting process, the variation pattern table is specified based on the start address SBn (n is any of 0 to 23) acquired in the HL register 107 in step S1011, and the specified variation pattern table is used. Set the stop result data and display duration data in this game.

Here, the data structure of the variation pattern table will be described by taking as an example the variation pattern table corresponding to the variation type number of “0”. FIG. 51A is an explanatory diagram for explaining the data configuration of the variation pattern table 64t corresponding to the variation type number of “0”.

As shown in FIG. 51 (a), the variation pattern table 64t is set to the addresses of "95CFH" to "95D8H" in the main ROM 64. In "95CFH", which is the start address of the variation pattern table 64t, stop result data corresponding to the mode of the pattern to be stopped and displayed on the first special figure display unit 37a is set. Further, although not shown, the start address of the variation pattern table corresponding to the variation type numbers of "1" to "23" is also stopped and displayed on the first special figure display unit 37a or the second special figure display unit 37b. The stop result data corresponding to the aspect of the picture is set. The stop result data is 1 byte data. The type of the pattern mode that is stopped and displayed on the first special figure display unit 37a or the second special figure display unit 37b is set differently for each type of the result of the hit / miss determination and the result of the distribution determination.

As shown in FIG. 51 (a), at the addresses of "95D0H" to "95D8H", three display duration data HK1 to HK3 and three determination values HVB1 to corresponding to the display duration data HK1 to HK3. HVB3 is set. Specifically, the determination value HVB1 corresponding to the display duration data HK1 is set in the address of "95D0H", and the display duration data is set in the addresses of "95D1H" to "95D2H" following "95D0H". HK1 is set. Further, the determination value HVB2 corresponding to the display duration data HK2 is set in the address of "95D3H", and the display duration data HK2 is set in the addresses of "95D4H" to "95D5H" following "95D3H". Has been done. Furthermore, the determination value HVB3 corresponding to the display duration data HK3 is set at the address of "95D6H", and the display duration data HK3 is set at the addresses of "95D7H" to "95D8H" following "95D6H". It is set.

The determination values HVB1 to HVB3 are 1-byte data, and the display duration data HK1 to HK3 are 2-byte data. The determination values HVB1 to HVB3 are used for a display duration lottery in which one display duration data is selected from the three display duration data HK1 to HK3. The display duration data HK1 is "1000", and when the display duration data HK1 is won, the display duration is 4 seconds. The display duration data HK2 is "1500", and when the display duration data HK2 is won, the display duration is 6 seconds. The display duration data HK3 is "2000", and when the display duration data HK3 is won, the display duration is 8 seconds.

In the display duration lottery, 1-byte numerical information (any of "0" to "255") acquired from a random number generator (counter circuit) provided in the main MPU 62 is used. The determination value HVB1 and the determination value HVB2 are "102", and the determination value HVB3 is "51". In the variation pattern table 64t, the probability of winning the display duration data HK1 and the probability of winning the display duration data HK2 are 2/5, and the probability of winning the display duration data HK3 is 1/5.

FIG. 51B is an explanatory diagram for explaining the configuration of the area for storing the stop result data and the display duration data HK1 to HK3 in the work area 121 for specific control. As shown in FIG. 51 (b), in the work area 121 for specific control, the stop result counter 141 is provided at the address of "0031H", and the display is continued at the addresses of "0032H" to "0033H". A time counter 142 is provided. The stop result counter 141 is a counter that enables the main CPU 63 to grasp the stop result data in the current game round. The stop result counter 141 consists of 1 byte. The display duration counter 142 is a counter that allows the main CPU 63 to grasp the display duration in the current game round. The display duration counter 142 consists of 2 bytes.

As described above, in the main ROM 64, in addition to the variation pattern table 64t corresponding to the variation type number of "0", 23 variation pattern tables corresponding to the variation type numbers of "1" to "23" are stored. Has been done. In the variation pattern table corresponding to the variation type numbers of "1" to "23", combinations of two to four display durations and determination values are set. The intervals between the start addresses in the 24 variation pattern tables stored in the main ROM 64 are irregular. Therefore, it is not possible to calculate the start address of the variation pattern table corresponding to the variation type number based only on the variation type number. In the configuration of acquiring the start address of the variation pattern table corresponding to the variation type number using the variation start table 64r, only the lower 12 bits of the variation start table 64r are set instead of the entire 2-byte start address. As a result, the data capacity of the fluctuation start table 64r is reduced.

Next, the fluctuation information setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The variation information setting process is executed in step S1012 of the special figure variation start process (FIG. 35). The fluctuation information setting process is executed by using the program for specific control and the data for specific control.

In the fluctuation information setting process, first, the instruction "LD (0031H), (HL +)" is executed (step S1401). "LD" is an LD update instruction by the LD update execution circuit 151, "0031H" is a content that specifies a stop result counter 141 in the work area 121 for specific control as a transfer destination, and "(HL +)" is a transfer source. The content specifies the stop result data stored in the area corresponding to the address stored in the HL register 107, and after loading the stop result data, the value of the HL register 107 is added by 1 to the HL register. It is a content instructing to update the address stored in 107. By executing "LD (0031H), (HL +)", the stop result data (" 3") corresponding to the address data ("95CFH") stored in the HL register 107 is loaded into the stop result counter 141. Will be done. As a result, the stop result data in this game can be grasped by the main CPU 63. Further, after loading the stop result data, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "95D0H". As a result, the determination value HVB1 can be grasped based on the address stored in the HL register 107.

In this way, by using the LD update instruction, the process of loading the stop result data set at the start address of the fluctuation pattern table 64t into the stop result counter 141, and after loading the stop result data, the HL register 107 The process of adding 1 to the value and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

A variation pattern table is specified based on the start address SBn acquired in the HL register 107 in the variation start address acquisition process (step S1011 of the special figure variation start process (FIG. 35)), and based on the specified variation pattern table. With the configuration for acquiring the stop result data, the stop result data corresponding to the result of the hit / fail determination and the result of the distribution determination can be set in the stop result counter 141.

Assuming that the stop result table for acquiring the stop result data corresponding to the current hit / fail judgment result and the distribution judgment result is stored in the main ROM 64 separately from the fluctuation pattern table, the start address of the stop result table is assumed. In addition to the need to specify, it becomes necessary to specify the area corresponding to the current hit / miss judgment result and the distribution judgment result in the stop result table. On the other hand, in the variable start address acquisition process (step S1011, FIG. 50 (b)), the variable pattern table is specified based on the start address SBn acquired in the HL register 107, and the specified variable pattern table is used. By the configuration for acquiring the stop result data and the display duration data, the configuration for acquiring the stop result data and the display duration data can be simplified.

After executing the command "LD (0031H), (HL +)" in step S1401, 1-byte numerical information for lottery is acquired from the random number generator (counter circuit) provided in the main MPU 62. The acquired numerical information is stored in a random number counter for fluctuation provided in the work area 121 for specific control (step S1402). The random number counter for fluctuation is a counter in which numerical information for lottery used for lottery of display duration data is set. The random number counter for fluctuation is a 1-byte counter provided in the storage area corresponding to the address of "0105H". Numerical information of any one of "0" to "255" is stored in the random number counter for fluctuation.

As described above, the storage area such as the counters that frequently appear in the program to execute the processing for specific control, such as the jackpot type counter C2 and the jackpot type maximum value counter CN2, is the work area 121 for characteristic control. Is set in the address range (“0000H” to “00FFH”) that is the target of the LDY instruction (the first LDY instruction and the second LDY instruction described later), while the processing for specific control is executed like the random number counter for fluctuation. The storage area such as a counter that appears less frequently in the program is not the target of the LDY instruction (the first LDY instruction and the second LDY instruction described later) in the work area 121 for characteristic control ("0100H" to "02FFH"). ") Is set. As a result, the data capacity of the program for executing the process for specific control is reduced.

After acquiring the numerical information for lottery in the random number counter for fluctuation in step S1402, the command "LD D, (HL +)" is executed (step S1403). "LD" is an LD update instruction by the LD update execution circuit 151, "D" is a content for designating the D register 106a as the transfer destination, and "(HL +)" is stored in the HL register 107 as the transfer source. The content specifies the determination value HVB1 stored in the area corresponding to the address, and after loading the stop result data, the value of the HL register 107 is added by 1 to update the address stored in the HL register 107. It is the content to instruct to do. By executing "LD D, (HL +)", the determination value HVB1 ("102") corresponding to the address data ("95D0H") stored in the HL register 107 is loaded into the D register 106a. Further, after the determination value HVB1 is loaded, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "95D1H". As a result, the display duration data HK1 (“1000”) corresponding to the determination value HVB1 can be grasped based on the address stored in the HL register 107.

In this way, by using the LD update instruction, the process of loading the determination value HVB1 set in the fluctuation pattern table 64t into the D register 106a and the value of the HL register 107 are added by 1 after the determination value HVB1 is loaded. Then, the process of updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

After that, a subtraction process of subtracting the value of the D register 106a from the value of the random number counter for fluctuation in the work area 121 for specific control is executed (step S1404). If the subtraction process is executed while the value equal to the value of the D register 106a or the value larger than the value of the D register 106a is stored in the random number counter for fluctuation, "0" is set in the carry flag. It will be in the state of being. On the other hand, when the subtraction process is executed in a state where a value smaller than the value of the D register 106a is stored in the random number counter for fluctuation, the carry flag is set to "1".

After that, it is determined whether or not "1" is set in the carry flag (step S1405), and if "1" is not set in the carry flag (step S1405: NO), the value of the HL register 107 is set. Add 2 (step S1406). As a result, the value of the HL register 107 becomes "95D3H", and the determination value HVB2 can be grasped based on the address stored in the HL register 107. When the process of step S1406 is performed, the process proceeds to step S1403, and the processes of steps S1403 to S1406 are repeatedly executed until an affirmative determination is made in step S1405.

If an affirmative determination is made in step S1405, the command "LD (0032H), HL" is executed (step S1407), and the fluctuation information setting process is terminated. In step S1407, "LD" is an LD instruction, "(0032H)" is a content that specifies a display duration counter 142 in the work area 121 for specific control as a transfer destination, and "HL" is an HL as a transfer source. This is the content that specifies the register 107. When "1" is set in the carry flag by the subtraction process of subtracting the determination value HVB1 stored in the D register 106a from the value of the random number counter for fluctuation in the work area 121 for specific control, the display is continued in step S1407. The display duration data HK1 is set in the time counter 142. Further, when "1" is set in the carry flag by the subtraction process of subtracting the determination value HVB2 stored in the D register 106a from the value of the variable random number counter, the display continues in the display duration counter 142 in step S1407. When the time data HK2 is set and the carry flag is set to "1" by the subtraction process of subtracting the determination value HVB3 stored in the D register 106a from the value of the variable random number counter, it is displayed in step S1407. The display duration data HK3 is set in the duration counter 142.

A variation pattern table is specified based on the start address SBn acquired in the HL register 107 in the variation start address acquisition process (step S1011 of the special figure variation start process (FIG. 35)), and based on the specified variation pattern table. Display duration Due to the configuration in which the lottery is performed, the display duration data corresponding to the result of the hit / fail judgment, the result of the distribution judgment, the result of the reach generation lottery, and the number of holds in the first special figure hold area 115 is displayed. It can be set in the counter 142.

By executing the fluctuation information setting process (FIG. 52) in this way, the stop result data in the current game round is set in the stop result counter 141, and the display duration counter 142 is won in the display duration lottery. The display duration data HK1 to HK3 that have become are set.

Returning to the description of the special figure variation start process (FIG. 35), after executing the variation information setting process in step S1012, the special figure special electric timer counter setting process provided in the work area 121 for specific control is executed. (Step S1013). The special figure special electric timer counter is a timer counter that is decremented by 1 in the timer update process in step S509 of the timer interrupt process (FIG. 26) and updated. As an effect for the game round, the variation display of the pattern on the first special symbol display unit 37a or the second special symbol display unit 37b and the variation display of the symbol on the symbol display device 41 are performed, and each variation display is completed. In that case, the final stop is displayed over the final stop time in a state where the stop result of the game round is displayed (in the symbol display device 41, a predetermined combination of symbols is waiting on the effective line). In this case, the display duration acquired in step S1012 is the total time for one game, and in the setting process of the special figure special electric timer counter in step S1013, the final display duration is obtained from the display duration acquired in step S1012. The information of the time after deducting the stop time is set in the special figure special electric timer counter.

After that, the variable command transmission process is executed (step S1014). In the transmission process, the variable command is transmitted to the sound / light side CPU 93. The variation command includes identification data indicating that the command is a variation command, and display duration data set in the display duration counter 142 in step S1012. The sound / light side CPU 93 grasps that it is the start timing of the fluctuation display of the symbol in the symbol display device 41 based on the variation command, and also grasps the display duration in the variation display of the symbol. The details of the variable command transmission process will be described later.

After that, the type command transmission process is executed (step S1015). In the transmission process, the type command is transmitted to the sound / light side CPU 93. The type commands include identification data indicating that the command is a type command, data corresponding to the result of the hit / fail judgment process, data corresponding to the result of the distribution judgment, and data indicating whether or not the mode is high probability mode. It contains data on whether or not it is in high frequency support mode. When the sound / light side CPU 93 receives the variation command and the type command, the light emission control of the display light emitting unit 53 is performed in order to display the variation of the symbol corresponding to the result of the pass / fail determination process, the result of the distribution determination, and the display duration. , Sound output control of the speaker unit 54 and display control of the symbol display device 41 are performed. Further, when the sound / light side CPU 93 receives the type command, it sets the data of whether or not it is in the high probability mode and the data of whether or not it is in the high frequency support mode.

After that, of the first special figure display unit 37a and the second special figure display unit 37b, the display unit on the execution target side of the current game round starts the variable display of the pattern (step S1016). After that, the special figure special electric counter is added by 1 (step S1017), and the present special figure fluctuation start process is terminated. Since the numerical information of the special figure special electric counter is "0" when the special figure fluctuation start processing is executed, the numerical information of the special figure special electric counter becomes "1" when the processing of step S1017 is executed. ..

<Processing during special figure change>
Next, the special figure changing process in step S905 of the special figure special electric control process (FIG. 30) will be described.

In the special figure change processing, it is determined whether or not the timing is before the final stop display during the duration of the game round, and if it is before the final stop display, the first special figure display unit 37a and the second special figure are displayed. In the figure display unit 37b, a process for regularly changing the display mode of the pattern on the execution target side of the game round this time is executed. This regular change is continued until it is time to start the final stop display. In addition, this regular change is performed in a certain manner regardless of whether or not a hit result is obtained and whether or not a reach display occurs.

In addition, instead of waiting in the special figure changing process until the final stop display timing is reached, if it is not the final stop display timing, after executing the above-mentioned regular change processing, this special figure End the variable processing. Therefore, after the effect for the game round is started, the special figure changing process is started every time the special figure special electric control process is started until the final stop display timing is reached. Further, when it is time to display the final stop, the symbol display device 41 sends a final stop command to the sound / light side CPU 93 in order to display the stop result of the current game round as the final stop, and at the same time, the first stop is displayed. Of the special figure display unit 37a and the second special figure display unit 37b, the display mode of the pattern on the execution target side of the current game round is set to the display mode corresponding to the lottery result of the current game round. Further, the information of the final stop time (0.5 seconds) of the game round is read from the main ROM 64 and set in the special figure special electric timer counter. Then, by adding 1 to the value of the special figure special electric counter, the value of the counter is updated from the one corresponding to the special figure changing process to the one corresponding to the special figure finalizing process.

<Processing during special drawing confirmation>
Next, the process during special figure determination in step S906 of the special figure special electric control process (FIG. 30) will be described.

In the process of confirming the special figure, it is determined whether or not the final stop time of the current game round has elapsed, and if the final stop time has elapsed, the result of the hit / fail judgment that triggered the current game round. Is a big hit result or a small hit result. If the winning / failing judgment result that triggered this game round is neither a big hit result nor a small hit result, "1" is set in the high probability mode flag of the data mode area in the work area 121 for specific control. Determine if it is. The main CPU 63 determines whether or not the high probability mode flag is set to "1" in the hit / fail determination process when starting the game round, so that the high probability / hit / fail table 64g and the low probability / hit / fail table 64a are used as the hit / miss tables. It is specified which of ~ 64f should be referred to. As described above, the high probability mode flag is set to "1" when the open / close execution mode ends regardless of the type of the jackpot result that triggered the execution. When the high probability mode flag is set to "1", the value of the high probability continuation counter provided in the work area 121 for specific control is subtracted by 1. The high-probability continuation counter specifies whether or not the number of times the game has been digested (specifically, "8") after the open / close execution mode has ended is the number of times that triggers the end of the high-probability mode. It is a counter to do. When the value of the high-probability continuation counter after 1 subtraction is "0", the high-probability mode flag is cleared by "0" and the high-frequency support mode flag is cleared by "0".

On the other hand, in the process of determining the special figure (step S906), when it is determined that the result of the hit / fail judgment that triggered the game round is a big hit result or a small hit result, it is stored in advance in the main ROM 64. The information of the opening time (for example, 4 seconds) is read out, and the information of the opening time is set in the special figure special electric timer counter. After that, the opening command is transmitted to the sound light side CPU 93. The opening command is a command for causing the sound-light side CPU 93 to recognize that it is the timing to start the effect for the open / close execution mode. The opening command also includes information indicating which of the various big hit results and small hit results is the game result that triggered the open / close execution mode. Therefore, the sound / light side CPU 93 can execute the effect of the opening / closing execution mode in a mode corresponding to the game result that triggered the opening / closing execution mode. After that, by adding 1 to the value of the special figure special electric counter, the value of the special figure special electric counter in which "2" is stored is changed to "3", and the processing during the determination of the special figure is terminated.

<Special electric start processing>
Next, the special electric start processing in step S907 of the special figure special electric control process (FIG. 30) will be described.

In the special electric start processing, it is determined whether or not the opening time in the opening / closing execution mode has elapsed, and if it is determined that the opening time has elapsed, the execution trigger of the opening / closing execution mode is one of the jackpot results. It is determined whether or not it is. When it is determined that the execution trigger of the current open / close execution mode is one of the jackpot results, the round counter provided in the work area 121 for specific control is used to indicate the number of round games corresponding to the current jackpot result. A value (“4”, “8” or “16”) is set, and “10” is set in the winning counter provided in the work area 121 for specific control. The round counter is a counter for specifying the number of remaining round games in the open / close execution mode by the main CPU 63, and the winning counter is an upper limit number of game balls in one round game or one open / close number specified mode. This is a counter for the main CPU 63 to specify whether or not a prize has been won. After that, the read processing of the open duration corresponding to the jackpot result is executed.

On the other hand, if it is determined that the execution trigger of the current open / close execution mode is not any big hit result, that is, if the execution trigger of the current open / close execution mode is a small hit result, the work area 121 for specific control is provided. "5" is set in the open / close counter, and "10" is set in the winning counter provided in the work area 121 for specific control. The open / close counter is a counter for specifying the number of times the special electric winning device 32 is opened / closed by the main CPU 63 in the open / close execution mode of the open / close number specified mode. After that, the read processing of the open duration corresponding to the small hit result is executed. The opening duration is stored in advance in the main ROM 64, and specifically, it is 0.05 seconds, which is shorter than the firing cycle (0.6 seconds) of the game ball.

When it is determined that the execution trigger of the current open / close execution mode is one of the jackpot results, the above-mentioned read processing of the open duration is executed, or the execution trigger of the current open / close execution mode is not any jackpot result. When the above-mentioned information on the open duration is read out, the read open duration information is set in the special electric timer counter, and the special electric winning device 32 is opened to be in the open state. Execute the setting process. After that, the release command is output. The release command is a command for causing the sound / light side CPU 93 to recognize that the special electric winning device 32 is released. Upon receiving the release command, the sound / light side CPU 93 executes control for switching the effect in the open / close execution mode accordingly. After that, by adding 1 to the special figure special electric counter, the value of the special figure special electric counter in which "3" is stored is changed to "4", and the special electric special electric start processing is terminated.

<Processing while the special electric train is open>
Next, the processing during opening of the special power in step S908 of the special power control processing (FIG. 30) will be described.

In the special electric open processing, if the opening / closing execution mode this time is the round number regulation mode, it is determined whether or not the end condition of one round game is satisfied, and if the end condition is satisfied, it is determined. The special electric winning device 32 is closed, and a closing command is transmitted to the sound / light side CPU 93. The closing command is a command for causing the sound / light side CPU 93 to recognize that the special electric winning device 32 is closed. Further, it is determined whether or not the value of the round counter after 1 subtraction is "0", and if it is not "0", the closing time is set in the special figure special electric timer counter. The closing time is constant regardless of the type of the game result that triggered the transition to the open / close execution mode, and specifically, it is 2 seconds, which is longer than the firing cycle of the game ball. Further, when the special electric winning device 32 is closed, the special electric special electric counter is incremented by 1 regardless of whether or not the value of the round counter is "0". In this case, since the value of the special figure special electric counter is "4" when the special electric electric opening processing is executed, it becomes "5" after 1 addition.

When the opening / closing execution mode this time is the opening / closing number regulation mode, the special electric winning device 32 is closed when the opening duration of the special electric winning device 32 has elapsed, and the closing command is issued to the sound / light side CPU 93. Send to. Then, it is determined whether or not the value of the open / close counter after 1 subtraction is "0", and if it is not "0", the closing time is set in the special figure special electric timer counter. As described above, the closing time is constant regardless of the type of game result that triggered the transition to the opening / closing execution mode. Further, if the opening duration has not elapsed, it is determined whether or not a prize has been generated in the special electric winning device 32, and if a prize has been generated, the winning counter is decremented by 1. When the value of the winning counter after subtraction of 1 is "0", the open / close counter is cleared to "0" and the special electric winning device 32 is closed. Further, when the special electric winning device 32 is closed, the special electric special electric counter is incremented by 1 regardless of whether or not the value of the open / close counter is "0". In this case, since the value of the special figure special electric counter is "4" when the special electric electric opening processing is executed, it becomes "5" after 1 addition.

<Processing while the special electric train is closed>
Next, the special electric closing process in step S909 of the special drawing special electric control process (FIG. 30) will be described.

In the special electric closing processing, it is determined whether or not both the round counter and the open / close counter are "0". If either one is not "0", it is determined whether or not the closing time has elapsed. If the closing time has not passed, the processing during closing of this special electric power is terminated as it is, and if the closing time has passed, the special electric power winning device 32 is opened and the execution trigger of the opening / closing execution mode this time. Set the opening duration corresponding to the hit result in the special figure special electric timer counter. Further, when the special electric winning device 32 is in the open state, the release command is transmitted to the sound / light side CPU 93. Then, after subtracting 1 from the special figure special electric counter, the processing during closing of the special electric power is terminated. In this case, since the value of the special figure special electric counter is "5" when the special electric power closing process is executed, it becomes "4" after 1 subtraction.

On the other hand, when both the round counter and the open / close counter are "0", the ending command is transmitted to the sound / light side CPU 93. The ending command is a command for causing the sound / light side CPU 93 to recognize that it is the timing to start the effect for ending. The ending command also includes information indicating which of the various big hit results and small hit results is the game result that triggered the open / close execution mode. Therefore, the sound / light side CPU 93 can execute the ending effect in a manner corresponding to the game result that triggered the opening / closing execution mode. Further, the information of the ending time (for example, 6 seconds) stored in advance in the main ROM 64 is read out, and the information of the ending time is set in the special figure special electric timer counter. Incidentally, the ending time is constant regardless of the type of the game result that triggered the transition to the open / close execution mode. Then, after the special figure special electric counter is added by 1, the processing during closing of the special electric power is terminated. In this case, since the value of the special figure special electric counter is "5" when the special electric power closing process is executed, it becomes "6" after 1 addition.

<Special train end processing>
Next, the special electric stop processing in step S910 of the special figure special electric control process (FIG. 30) will be described.

In the special electric end processing, it is determined whether or not the ending time has elapsed. When it is determined that the ending time has elapsed, the game state transition process is executed, the special figure special electric counter is cleared to "0", and the special electric electric end process is terminated. Here, the game state transition process will be described.

In the game state transition process, if the result of the hit / fail judgment that triggered the transition of the open / close execution mode ended this time is a big hit result, the high probability mode flag and the high frequency support mode of the data area in the work area 121 for specific control Along with setting "1" to the flag, "8" is set to the high probability continuation counter in the work area 121 for specific control. As a result, the game state after the open / close execution mode is the high probability mode and becomes the high frequency support mode, and the game state is continued until the game times are exhausted eight times.

In the game state transition process, if the hit result that triggered the transition of the open / close execution mode that ended this time is a small hit result, "30" is set in the small hit post-counter provided in the work area 121 for specific control. Then, the game state transition process is terminated. The small hit after counter is a counter for the main CPU 63 to specify whether or not the game times of the standard number of small hits after the small hit result has already been consumed. The value of the counter after the small hit is subtracted by 1 each time the game round is completed. Further, when the open / close execution mode is changed, the value of the counter after a small hit is cleared to "0". When the value of the counter after the small hit is 1 or more, the selection of the display duration in the game round is performed in the corresponding manner after the result of the small hit.

Next, prior to the description of the display control process executed in step S514 of the timer interrupt process (FIG. 26), the hold display data table 64s stored in the main ROM 64 will be described. The hold display data table 64s is a data table for controlling the display of the first special figure hold display unit 37c, the second special figure hold display unit 37d, and the normal figure hold display unit 38b.

FIG. 53A is an explanatory diagram for explaining the data configuration of the hold display data table 64s, and FIG. 53B is an explanatory diagram for explaining an acquisition mode of hold display data corresponding to the number of holds. 53 (c) is an explanatory diagram for explaining the data structure of the conventional hold display data table shown for comparison. As shown in FIG. 53 (a), the hold display data table 64s is stored in the address range of "9190H" to "9192H" in the main ROM 64. As shown in FIG. 53B, the hold display data HR0 to HR4 are 1-byte data, and the upper 4 bits of the hold display data HR0 to HR4 are common to "0000B".

As shown in FIG. 53 (a), in the hold display data table 64s, the lower 4 bits of the five hold display data HR0 to HR4 corresponding to the number of holds of "0" to "4" are set. Specifically, the lower 4 bits (3rd to 3rd bits) of the 1-byte area corresponding to the start address "9190H" of the hold display data table 64s are the lower 4 bits (lower 4 bits) of the 0th hold display data HR0. "0000B") is set, and the lower 4 bits ("0001B") of the first hold display data HR1 are set in the upper 4 bits (4th to 7th bits) of the area. The lower 4 bits (“0011B”) of the second hold display data HR2 are set in the lower 4 bits of the 1-byte area corresponding to “9191H” following “9190H”, and the upper 4 bits of the area are set. Is set to the lower 4 bits (“0111B”) of the third hold display data HR3. The lower 4 bits ("1111B") of the 4th hold display data HR4 are set in the lower 4 bits of the 1-byte area corresponding to "9191H" following "9191H", and the upper 4 bits of the area are set. Is set to "0000B" as adjustment data that is not used.

In the display control process (FIG. 54) described later, in the first special figure hold display data acquisition process in step S1501, the second special figure hold display data acquisition process in step S1503, and the normal figure hold display data acquisition process in step S1505, the number of holds. The lower 4 bits of the hold display data HRn (n is an integer of 0 to 4) corresponding to the above are loaded into the lower 4 bits (3rd to 3rd bits) of the W register 104a, and the W register 104a. The upper 4 bits (4th to 7th bits) are masked with "0". As a result, the entire hold display data HR0 to HR4 corresponding to the number of holds can be set in the W register 104a.

As shown in FIG. 53A, the lower 4 bits of the 5 hold display data HR0 to HR4 in the hold display data table 64s are set in an area of a total of 3 bytes in the main ROM 64. On the other hand, assuming that the entire 1-byte hold display data HR0 to HR4 is stored in the hold display data table 64s, the five hold display data HR0 to HR4 are stored as shown in FIG. 53 (c). A total of 5 bytes of area is required for setting. As described above, since only the lower 4 bits of the five hold display data HR0 to HR4 have the data configuration set in the hold display data table 64s, the hold display data table 64s is stored in the main ROM 64. The data capacity of is reduced.

Next, the display control process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The display control process is executed in step S514 of the timer interrupt process (FIG. 26). The display control process is executed by using the program for specific control and the data for specific control.

In the display control process, first, the first special figure hold display data acquisition process is executed (step S1501). In the first special figure holding display data acquisition process, the number of holdings of the first special drawing holding area 115 is grasped with reference to the first special figure holding number counter 118 in the work area 121 for specific control. After that, the lower 4 bits of the hold display data HRn (n is an integer of 0 to 4) corresponding to the grasped number of holds based on the hold display data table 64s in the main ROM 64 are set to the lower 4 bits of the W register 104a. It is loaded into (0th to 3rd bits), and the upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". As a result, the entire hold display data HRn corresponding to the value of the first special figure hold number counter 118 can be set in the W register 104a. The details of the first special figure hold display data acquisition process will be described later.

After that, the hold display data HRn set in the W register 104a in step S1501 is set in the first special figure hold display area provided in the work area 121 for specific control (step S1502). The first special figure hold display area is a storage area in which display data for performing display control of the first special figure hold display unit 37c is set. The first special figure reservation display area consists of 1 byte. The hold display data HRn set in the first special figure hold display area is a driver for the first special figure provided on the main control board 61 in order to control the display of the first special figure hold display unit 37c in step S1507. It is output to the circuit.

After that, the second special figure hold display data acquisition process is executed (step S1503). In the second special figure hold display data acquisition process, the number of holds in the second special figure hold area 116 is grasped with reference to the second special figure hold number counter 119 in the work area 121 for specific control. After that, the lower 4 bits of the hold display data HRn corresponding to the grasped number of holds based on the hold display data table 64s in the main ROM 64 are set to the lower 4 bits (3rd to 3rd bits) of the W register 104a. , The upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". As a result, the entire hold display data HRn corresponding to the value of the second special figure hold number counter 119 can be set in the W register 104a. The details of the second special figure hold display data acquisition process will be described later.

After that, the hold display data HRn set in the W register 104a in step S1503 is set in the second special figure hold display area provided in the work area 121 for specific control (step S1504). The second special figure hold display area is a storage area in which display data for performing display control of the second special figure hold display unit 37d is set. The second special figure hold display area consists of 1 byte. The hold display data HRn set in the second special figure hold display area is a second special figure driver circuit provided on the main control board 61 for display control of the second special figure hold display unit 37d in step S1507. Is output to.

After that, the normal figure hold display data acquisition process is executed (step S1505). In the normal figure hold display data acquisition process, the number of hold of the normal figure hold area 114 is grasped by referring to the normal figure hold number counter 127 in the work area 121 for specific control. After that, the lower 4 bits of the hold display data HRn corresponding to the grasped number of holds based on the hold display data table 64s in the main ROM 64 are set in the lower 4 bits (3rd to 3rd bits) of the W register 104a. , The upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". As a result, the entire hold display data HRn corresponding to the value of the normal figure hold number counter 127 can be set in the W register 104a. The details of the normal map hold display data acquisition process will be described later.

After that, the hold display data HRn set in the W register 104a in step S1505 is set in the normal figure hold display area provided in the work area 121 for specific control (step S1506). The normal figure hold display area is a storage area in which display data for performing display control of the normal figure hold display unit 38b is set. The normal figure hold display area consists of 1 byte. The hold display data HRn set in the normal figure hold display area is output to the normal figure driver circuit provided on the main control board 61 in order to control the display of the normal figure hold display unit 38b in step S1507.

After that, various display data output processes are executed (step S1507), and the present display control process is terminated. In the output processing of various display data in step S1507, the hold display data HRn set in the first special figure hold display area in the work area 121 for specific control is output to the first special figure driver circuit, and the second special figure is output. The hold display data HRn stored in the figure hold display area is output to the second special figure driver circuit, and the hold display data HRn stored in the normal figure hold display area is output to the normal figure driver circuit.

Next, the program contents of the first special figure display data acquisition process executed in step S1501 of the display control process (FIG. 54) will be described with reference to the explanatory diagram of FIG. 55 (a). As shown in FIG. 55 (a), "2101" to "2105" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LD W, (THRYUH1)" is set in the line number of "2101". “LD” is an LD instruction, and “W” is a content that specifies the W register 104a as a transfer destination. "THRYUH1" is the address of the first special figure hold number counter 118 in the work area 121 for specific control, and "(THRYUH1)" is the "transfer destination" of the data stored in the first special figure hold number counter 118. It is the content to be loaded into. As described above, the first special figure hold number counter 118 stores numerical data of any one of 0 to 4. By executing "LD W, (THRYUH1)", the data of the first special figure hold number counter 118 is loaded into the W register 104a of the "transfer destination".

The command "LD B, 04H" is set in the line number of "2102". "LD" is an LD instruction, "B" is a content for designating the B register 105a as a transfer destination, and "04H" is a content for designating numerical data "04H" as a "transfer source". “04H” is the number of bits (number of acquisition bits) of the address data acquired from the hold display data table 64s in the hold display data acquisition execution process (FIG. 55 (b)) called by the line number “2104” described later. By executing "LD B, 04H", the number of bits ("4") of the address data acquired from the hold display data table 64s is set in the B register 105a of the "transfer destination".

The command "LD HL, TBL_LEDHYU_B" is set in the line number of "2103". “LD” is an LD instruction, and “HL” is a content that specifies the HL register 107 as a transfer destination. "TBL_LEDHYU_B" is 2-byte numerical data for setting the acquisition start address to the start address ("9190H") of the hold display data table 64s, and is specifically "0C80H". By executing "LD HL, TBL_LEDHYU_B", "0C80H" is loaded into the HL register 107 of the "transfer destination".

"TBL_LEDHYU_B" is calculated by the formula "{(start address of hold display data table 64s) -9000H} x 8". The data of the 0th to 11th bits at the start address "9190H" are set in the 3rd to 14th bits in "TBL_LEDHYU_B". As described above, in the LDB instruction, the data of the 3rd to 14th bits in the acquisition data designation data is set to the 0th to 11th bits of the acquisition start address, and the 12th to 15th bits of the acquisition start address are set. The 12th to 15th bit data at the reference address (“9000H”) of the data table is set. By setting "TBL_LEDHYU_B" calculated by the formula of "{(start address of hold display data table 64s) -9000H} x 8" as acquisition data designation data, the start address of hold display data table 64s can be acquired. Can be.

In the hold display data acquisition execution process (FIG. 55 (b)) called by the line number "2104", when the value of the first special figure hold number counter 118 is "0", it is stored in the HL register 107. "0C80H" is used as the acquired data designation data. On the other hand, when the value of the first special figure hold number counter 118 is "1" or more, the numerical information stored in the HL register 107 is the first special figure hold number counter 118 before the LDB instruction is executed. It is changed to the numerical information corresponding to the value of.

An instruction "CALLS LDBGET" is set in the line number of "2104". “LDBGET” is a hold display data acquisition execution process (FIG. 55 (b)) described later. The instruction "CALLS LDBGET" is an instruction for calling a subroutine called a hold display data acquisition execution process. Although the details will be described later, the hold display data HRn corresponding to the value of the first special figure hold number counter 118 is set in the W register 104a by executing the hold display data acquisition execution process at the line number “2104”. To. When the subroutine of the hold display data acquisition execution process is completed, the process proceeds to the line number of "2105".

An instruction "RET" is set in the line number of "2105". As described above, the first special figure display data acquisition process is a subroutine executed in step S1501 of the display control process (FIG. 54). Therefore, when the instruction "RET" is executed, the process proceeds to step S1502 of the display control process (FIG. 54).

Next, the hold display data acquisition execution process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 55 (b). FIG. 55B is an explanatory diagram for explaining the program contents of the hold display data acquisition execution process. The hold display data acquisition execution process is executed at the line number “2104” of the first special figure hold display data acquisition process (FIG. 55 (a)). Further, the hold display data acquisition execution process includes the line number “2304” of the second special figure hold display data acquisition process (FIG. 55 (c)) described later, and the general figure hold display data acquisition process (FIG. 55 (d)) described later. )) Is also executed at the line number "2404". First, a case where the hold display data acquisition execution process is executed at the line number “2104” of the first special figure hold display data acquisition process (FIG. 55 (a)) will be described.

As shown in FIG. 55 (b), "2201" to "2208" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

As shown in FIG. 55 (b), "LDBGET" is set for the line number of "2201". This is not an instruction but data that is referred to when the developer of the pachinko machine 10 confirms the program. Therefore, at the line number "2201", the process proceeds to the line number "2202" without executing any instruction.

The command "LD A, B" is set in the line number of "2202". “LD” is an LD instruction, “A” is a content that specifies A register 104b as a transfer destination, and “B” is a content that specifies B register 105a as a transfer source. As described above, in the first special figure reservation display data acquisition process (FIG. 55 (a)), the number of acquisition bits “04H” is set in the B register 105a. Therefore, by executing "LD A, B", "04H" is set in the A register 104b of the "transfer destination".

The command "MUL W, A" is set in the line number of "2203". "MUL" is an operation instruction called a MUL instruction, "W" is a content for designating the W register 104a, and "A" is a content for designating the A register 104b. By executing "MUL W, A", an operation of multiplying the value of the W register 104a and the value of the A register 104b is performed, and the result of the operation is stored in the WA register 104. As described above, in the line number "2103" of the first special figure hold display data acquisition process (FIG. 55 (a)), the HL register 107 corresponds to the value of "0" in the first special figure hold number counter 118. The acquired data designation data (“0C80H”) to be acquired is stored. The data of the calculation result of "(value of the first special figure holding number counter 118) x (number of acquired bits)" is the acquired data designation data stored in the HL register 107 of the first special figure holding number counter 118. Used to change to the data corresponding to the value.

The command "ADD HL, WA" is set in the line number of "2204". "ADD" is an operation instruction called an ADD instruction, "HL" is a content for designating an HL register 107, and "WA" is a content for designating a WA register 104. By executing "ADD HL, WA", the sum of the value of the HL register 107 and the value of the WA register 104 is stored in the HL register 107. As described above, in the line number "2103" of the first special figure hold display data acquisition process (FIG. 55 (a)), the HL register 107 corresponds to the value of "0" in the first special figure hold number counter 118. The acquired data designation data (“0C80H”) is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(value of the first special figure holding number counter 118) x (number of acquired bits)". The data of the calculation result of "(value of the first special figure hold count counter 118) x (number of acquisition bits)" stored in the WA register 104 is added to the acquisition data designation data stored in the HL register 107. By doing so, it is possible to set the state in which the acquired data designation data corresponding to the value of the first special figure hold number counter 118 is stored in the HL register 107.

As with the line number "2202", the command "LD A, B" is set in the line number of "2205". As described above, in the first special figure hold display data acquisition process (FIG. 55 (a)), “04H” is set as the number of acquisition bits in the B register 105a. Therefore, when "LD A, B" is executed, "04H" is loaded in the A register 104b of the "transfer destination". As described above, the "04H" stored in the B register 105a was also used in the calculation of "(value of the first special figure holding number counter 118) x (number of acquired bits)". In this way, "04H" stored in the B register 105a in advance is used for the calculation of "(value of the first special figure hold number counter 118) × (number of acquisition bits)", and is also an acquisition bit in the LDB instruction. It is used to set the data for specifying the number in the A register 104b.

An instruction "DEC A" is set in the line number of "2206". "DEC" is an operation instruction called a DEC instruction, and "A" is a content that specifies A register 104b. When "DEC A" is executed, the value of the A register 104b is decremented by 1. As described above, "04H" is stored in the A register 104b. Therefore, when "DEC A" is executed at the line number "2206", "03H" is stored in the A register 104b. “03H” is a value obtained by subtracting “1” from “4” which is the number of bits acquired from the hold display data table 64s.

When the LDB instruction "LDB W, (HL) .A" is executed at the line number "2207", the LDB execution circuit 157 performs an operation of adding 1 to the value of the A register 104b, and after the 1 addition. The value of is used as the data of the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b at the line number “2206”, the number of bits of the data acquired from the hold display data table 64s in the LDB instruction can be set to “4”.

The command "LDB W, (HL) .A" is set in the line number of "2207". "LDB" is an LDB instruction by the LDB execution circuit 157, "HL" is a content that specifies the HL register 107 as a "transfer destination", and "(HL)" is a 2-byte stored in the HL register 107. "A" is the content for designating the data as the acquisition data designation data, and "A" is the content for designating the 1-byte data stored in the A register 104b as the acquisition bit number designation data. As described above, the HL register 107 is in a state in which the acquisition data designation data corresponding to the value of the first special figure hold number counter 118 is stored, and the A register 104b is the number of acquisition bits (“04H”). It is a state in which "03H" obtained by subtracting "1" from is stored. Further, the TP register 111 is in a state in which "9000H", which is a reference address of the data table, is stored. In this state, when the instruction "LDB W, (HL) .A" is executed at the line number "2207", the first special figure is assigned to the 0th to 3rd bits of the W register 104a which is the transfer destination. The lower 4 bits of the hold display data HRn corresponding to the value of the hold number counter 118 are loaded, and the 4th to 7th bits of the W register 104a are masked with "0".

Specifically, as shown in FIG. 53 (b), when the value of the first special figure hold number counter 118 is "0", the acquisition start address is "9190H" and the acquisition start bit is "0". , And the lower 4 bits of the hold display data HR0 are loaded into the 0th to 3rd bits of the W register 104a. When the value of the first special figure hold number counter 118 is "1", the acquisition start address becomes "9190H" and the acquisition start bit becomes "4", and the acquisition start bit is held in the 0th to 3rd bits of the W register 104a. The lower 4 bits of the display data HR1 are loaded. When the value of the first special figure hold number counter 118 is "2", the acquisition start address becomes "9191H" and the acquisition start bit becomes "0", and the acquisition start bit is held in the 0th to 3rd bits of the W register 104a. The lower 4 bits of the display data HR2 are loaded. When the value of the first special figure hold number counter 118 is "3", the acquisition start address becomes "9191H" and the acquisition start bit becomes "4", and the acquisition start bit is held in the 0th to 3rd bits of the W register 104a. The lower 4 bits of the display data HR3 are loaded. When the value of the first special figure hold number counter 118 is "4", the acquisition start address becomes "9192H" and the acquisition start bit becomes "0", and the acquisition start bit is held in the 0th to 3rd bits of the W register 104a. The lower 4 bits of the display data HR4 are loaded. In this way, each time the value of the first special figure hold number counter 118 is incremented by 1, the data acquisition start position in the hold display data table 64s is shifted by 4 bits.

The configuration is such that the lower 4 bits of the hold display data HRn acquired from the hold display data table 64s by using the LDB instruction are loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, so that the data is 2 bytes. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the acquisition data designation data and the reference address of the data table set in the TP register 111, and the 0th to 2nd bits of the acquisition designation data. The process of specifying the acquisition start bit corresponding to (lower 3 bits), the process of loading the lower 4 bits of the hold display data HRn acquired from the hold display data table 64s into the lower 4 bits of the W register 104a, and the process of loading the lower 4 bits of the W register 104a. The process of masking the upper 4 bits of the register 104a with "0" can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

An instruction "RET" is set in the line number of "2208". When the hold display data acquisition execution process is executed at the line number "2104" of the first special figure hold display data acquisition process (FIG. 55 (a)), the command "RET" is executed. The process proceeds to the line number "2105" of the first special figure hold display data acquisition process.

In this way, by using the LDB instruction, the lower 4 bits of the hold display data HRn are acquired from the hold display data table 64s to the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are set to "0". It is possible to acquire the entire hold display data HRn by masking with. Therefore, the hold display data HRn set in the hold display data table 64s can be set to only the lower 4 bits of the hold display data HRn. As a result, the data capacity of the hold display data table 64s in the main ROM 64 can be reduced as compared with the configuration in which the entire hold display data HRn of 1 byte is set in the hold display data table 64s. Further, it is possible to execute a process of loading the lower 4 bits of the hold display data HRn into the lower 4 bits of the W register 104a and a process of masking the upper 4 bits of the W register 104a with "0" with one instruction. Therefore, it is possible to simplify the configuration of the program for executing the hold display data acquisition execution process as compared with the configuration in which a plurality of instructions are set to execute these processes, and the program concerned. The data capacity in the main ROM 64 can be reduced.

Next, the program contents of the second special figure display data acquisition process executed in step S1503 of the display control process (FIG. 54) will be described with reference to the explanatory diagram of FIG. 55 (c). As shown in FIG. 55 (c), "2301" to "2305" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LD W, (THRYUH2)" is set in the line number of "2301". “LD” is an LD instruction, and “W” is a content that specifies the W register 104a as a transfer destination. "THRYUH2" is the address of the second special figure hold number counter 119 in the work area 121 for specific control, and "(THRYUH2)" is the "transfer destination" of the data stored in the second special figure hold number counter 119. It is the content to be loaded into. As described above, the second special figure hold number counter 119 stores numerical data of any one of 0 to 4. By executing "LD W, (THRYUH2)", the data of the second special figure hold number counter 119 is loaded into the W register 104a of the "transfer destination".

In the line number of "2302", the instruction "LD B, 04H" is set as in the line number "2102" of the first special figure reservation display data acquisition process (FIG. 55 (a)). “04H” is the number of bits (number of acquisition bits) of the address data acquired from the hold display data table 64s in the hold display data acquisition execution process (FIG. 55 (b)) called by the line number “2304” described later. By executing "LD B, 04H", the number of bits ("4") of the address data acquired from the hold display data table 64s is set in the B register 105a of the "transfer destination".

In the line number of "2303", the instruction "LD HL, TBL_LEDHYU_B" is set as in the line number "2103" of the first special figure hold display data acquisition process (FIG. 55 (a)). By executing "LD HL, TBL_LEDHYU_B", "0C80H" is set in the HL register 107 of the "transfer destination". “0C80H” is the hold display data HRn corresponding to the value of the second special figure hold number counter 119 from the hold display data table 64s in the hold display data acquisition execution process (FIG. 55 (b)) called by the line number “2304”. It is stored in the HL register 107 to acquire the lower 4 bits (n is an integer of 0 to 4).

In the line number of "2304", the instruction "CALLS LDBGET" is set as in the line number "2104" of the first special figure hold display data acquisition process (FIG. 55 (a)). As described above, the instruction "CALLS LDBGET" is an instruction for calling a subroutine called a hold display data acquisition execution process. By executing the hold display data acquisition execution process at the line number “2304”, the hold display data HRn corresponding to the value of the second special figure hold number counter 119 is loaded into the W register 104a. In this way, the hold corresponding to the value of the second special figure hold number counter 119 is used by using the program of the subroutine common to the first special figure hold display data acquisition process (FIG. 55 (a)) and the hold display data table 64s. With the configuration for acquiring the display data HRn, it is possible to reduce the data capacity of the program and the data for acquiring the hold display data HRn. When the acquisition processing subroutine ends, the process proceeds to the line number of "2305".

An instruction "RET" is set in the line number of "2305". As described above, the second special figure display data acquisition process is a subroutine executed in step S1503 of the display control process (FIG. 54). Therefore, when the instruction "RET" is executed, the process proceeds to step S1504 of the display control process (FIG. 54).

Next, the program contents of the normal map display data acquisition process executed in step S1505 of the display control process (FIG. 54) will be described with reference to the explanatory diagram of FIG. 55 (d). As shown in FIG. 55 (d), "2401" to "2405" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LD W, (HHRYUH)" is set in the line number of "2401". “LD” is an LD instruction, and “W” is a content that specifies the W register 104a as a transfer destination. "HHRYUH" is the address of the normal figure hold number counter 127 in the work area 121 for specific control, and "(HHRYUH)" is the content to load the data stored in the normal figure hold number counter 127 to the "transfer destination". Is. As described above, the numerical data of any of 0 to 4 is stored in the normal figure hold number counter 127. By executing "LD W, (THRYUH2)", the data of the normal figure hold number counter 127 is loaded into the W register 104a of the "transfer destination".

In the line number of "2402", the line number "2102" of the first special figure hold display data acquisition process (FIG. 55 (a)) and the line of the second special figure hold display data acquisition process (FIG. 55 (c)) Similar to the number "2302", the instruction "LD B, 04H" is set. “04H” is the number of bits (number of acquisition bits) of the address data acquired from the hold display data table 64s in the hold display data acquisition execution process (FIG. 55 (b)) called by the line number “2404” described later. By executing "LD B, 04H", the number of bits ("4") of the address data acquired from the hold display data table 64s is set in the B register 105a of the "transfer destination".

In the line number of "2403", the line number "2103" of the first special figure hold display data acquisition process (FIG. 55 (a)) and the line of the second special figure hold display data acquisition process (FIG. 55 (c)). Similar to the number "2303", the instruction "LD HL, TBL_LEDHYU_B" is set. By executing "LD HL, TBL_LEDHYU_B", "0C80H" is loaded into the HL register 107 of the "transfer destination". “0C80H” is the hold display data HRn (n) corresponding to the value of the hold display data counter 127 from the hold display data table 64s in the hold display data acquisition execution process (FIG. 55 (b)) called by the line number “2404”. Is stored in the HL register 107 to acquire the lower 4 bits of (an integer of 0 to 4).

In the line number of "2404", the line number "2104" of the first special figure hold display data acquisition process (FIG. 55 (a)) and the line of the second special figure hold display data acquisition process (FIG. 55 (c)). Similar to the number "2304", the instruction "CALLS LDBGET" is set. As described above, the instruction "CALLS LDBGET" is an instruction for calling a subroutine called a hold display data acquisition execution process. By executing the hold display data acquisition execution process at the line number “2404”, the hold display data HRn corresponding to the value of the normal figure hold number counter 127 is set in the W register 104a. In this way, the program of the subroutine and the hold display data table 64s common to the first special figure hold display data acquisition process (FIG. 55 (a)) and the second special figure hold display data acquisition process (FIG. 55 (c)) can be obtained. It is possible to reduce the data capacity of the program and data for acquiring the hold display data HRn by using the configuration for acquiring the hold display data HRn corresponding to the value of the hold number counter 127. When the acquisition processing subroutine ends, the process proceeds to the line number of "2405".

An instruction "RET" is set in the line number of "2405". As described above, the normal map display data acquisition process is a subroutine executed in step S1505 of the display control process (FIG. 54). Therefore, when the instruction "RET" is executed, the process proceeds to step S1506 of the display control process (FIG. 54).

<Management processing>
Next, the management process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 56 (a). The management process is executed in step S518 of the timer interrupt process (FIG. 26). The management process is executed by using the program for specific control and the data for specific control.

In the management process, first, the interrupt disable setting is set in order to prohibit the occurrence of the timer interrupt process (FIG. 26) (step S1601). As a result, the timer interrupt process (FIG. 26), which is the process corresponding to the specific control, is not interrupted and started in the middle of the management execution process (FIG. 57), which is the process corresponding to the non-specific control. It becomes possible to do so.

After that, as "PUSH PSW", the information of the flag register of the main CPU 63 is saved in the stack area 123 for specific control by a push instruction (step S1602). As described above, the flag register includes the zero flag ZF, the carry flag, the P / V flag, the sine flag, the half carry flag, and the like, and the information in the flag register changes depending on the execution result of the operation instruction, the rotate instruction, the input / output instruction, and the like. Will be done. By saving the information of such a flag register before the program of the subroutine corresponding to the management execution process is started, the information of the flag register in the state before the call of the subroutine or the change after the start of the subroutine can be obtained. It is possible to save it in the stack area 123 for specific control.

After that, the management execution process is started by reading the program of the subroutine corresponding to the management execution process set in the program for non-specific control (step S1603). In this case, information for specifying the return address of the management process after the execution of the management execution process is written in the stack area 123 for specific control by the push instruction. Then, when the management execution process is completed, the information for specifying the return address is read by the pop instruction, and the program returns to the management process program indicated by the return address.

When the program returns to the management processing program after the management execution processing is executed, the information of the flag register saved in the stack area 123 for specific control in step S1602 by the pop instruction as "POP PSW" is stored in the main CPU 63. It returns to the flag register of (step S1604). As a result, the information in the flag register of the main CPU 63 is restored to the information at the time when step S1602 is executed. That is, the information in the flag register of the main CPU 63 is restored to the information for executing the specific control.

After that, as "LD IY, 0000H", "0000H" is set as the specific control reference address used when the address of the work area 121 for specific control is specified in the IY register 109 by the LD instruction (step S1605). ). As a result, the specific control reference address can be used when the first LDY instruction is executed in the specific control process.

After that, in order to switch from the state in which the generation of the timer interrupt process (FIG. 26) is prohibited to the state in which the timer interrupt process is permitted, the interrupt enable setting is set (step S1606), and this management process is terminated. By setting the interrupt permission, new execution of timer interrupt processing becomes possible.

Next, prior to the description of the management execution process (FIG. 57) executed by the main CPU 63, setting modes of various buffers 163a to 163e in the work area 122 for non-specific control will be described. FIG. 56B is an explanatory diagram for explaining a setting mode of various buffers 163a to 163e in the work area 122 for non-specific control.

As shown in FIG. 56B, in the work area 122 for non-specific control, the information of the WA register 104 at the start of the processing for non-specific control is stored in the storage area corresponding to the addresses "0340H" to "0341H". A WA buffer 163a is provided to save the information in the BC register 105 at the start of the non-specific control process in the storage area corresponding to the addresses "0342H" to "0343H". A buffer 163b is provided, and a DE buffer 163c for saving the information of the DE register 106 at the start of the non-specific control process is provided in the storage area corresponding to the addresses "0344H" to "0345H". In the storage area corresponding to the addresses of "0346H" to "0347H", an HL buffer 163d for saving the information of the HL register 107 at the start of the non-specific control process is provided, and "0348H" to "0348H". An IX buffer 163e for saving the information of the IX register 108 at the start of the non-specific control process is provided in the storage area corresponding to the address of "0349H". These buffers 163a to 163e consist of 2 bytes. When the processing for non-specific control is started, the information of the corresponding register is saved in these buffers. When the processing for non-specific control is completed, the information saved in these buffers is returned to the corresponding buffer.

<2nd LDY command>
Next, prior to the description of the management execution process (FIG. 57) executed by the main CPU 63, the second LDY instruction included in the program of the management execution process will be described.

In the management execution process (FIG. 57) described later, the second LDY of "LDY WA, (40H)", "LDY BC, (42H)", "LDY DE, (44H)" and "LDY HL, (46H)" Instructions are included. As shown in FIG. 9, the main MPU 62 includes a second LDY execution circuit 164. The second LDY execution circuit 164 is a dedicated circuit for executing the second LDY instruction. The main CPU 63 can execute the second LDY instruction as a transfer instruction for transferring data.

The instruction code of the second LDY instruction has a configuration of "LDY transfer destination, (transfer source)". In the second LDY instruction, a pair register is set as the "transfer destination". The pair register set as the "forwarding destination" in the second LDY instruction is the WA register 104, the BC register 105, the DE register 106, or the HL register 107. In the second LDY instruction, a 1-byte numerical value (for example, "(40H)") is set as "(transfer source)".

In the second LDY instruction, the 2-byte address is calculated by adding the 2-byte numerical information set in the IY register 109 to the 1-byte numerical information set in "(transfer source)". The 2-byte data stored in the area corresponding to the address and the area corresponding to the address obtained by adding 1 to the address in the side RAM 65 is loaded into the pair register set as the "transfer destination". As described above, in the present embodiment, the IY register 109 is set to "0000H" as the specific control reference address at the start of the specific control process, and the non-specific control is set at the start of the non-specific control process. "0300H" is set as the reference address.

By executing "LDY WA, 40H" in a state where "0300H" is set in the IY register 109 in advance, the main RAM 65 is executed in the same manner as when "LD WA, (0340H)" is executed. The 2-byte data stored in the WA buffer 163a in the area corresponding to "0340H" and "0341H", that is, the work area 122 for non-specific control is loaded into the WA register 104.

In the machine language of the second LDY instruction (for example, "LDY WA, (40H)"), 1-byte data (40H) is set as data for designating "(transfer source)". On the other hand, in the machine language of the LD instruction (for example, "LD WA, (0340H)"), 2-byte data (0340H) is set as data for designating "(transfer source)". The data capacity of the machine language of the second LDY instruction is smaller than the data capacity of the machine language of the LD instruction. Therefore, in the state where "0300H" is stored in the IY register 109, the 2-byte data stored in the work area 122 for non-specific control is stored in the WA register 104, the BC register 105, the DE register 106, or the HL register. When loading to 107, the data capacity of the program in the main ROM 64 can be reduced by using the second LDY instruction instead of the LD instruction.

Next, the management execution process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 57. The management execution process is executed in step S1603 of the management process (FIG. 56 (a)). The management execution process is executed by the main CPU 63 using the program for non-specific control and the data for non-specific control.

First, as "LD SP, 04AFH", the LD instruction causes the stack pointer provided on the main CPU 63 to have "04AFH", which is the final address of the stack area 124 for non-specific control, as a fixed address at the start of non-specific control. Set (step S1701). The stack pointer is a register in which information is written to the stack areas 123 and 124. The address information stored in the stack pointer is updated when the information is written to the stack areas 123 and 124 by the push instruction.

After that, as "LD (0340H), WA", the information of the WA register 104 of the main CPU 63 is saved in the WA buffer 163a by the LD instruction (step S1702). After that, as "LD (0342H), BC", the information of the BC register 105 of the main CPU 63 is saved in the BC buffer 163b by the LD instruction (step S1703). After that, as "LD (0344H), DE", the information of the DE register 106 of the main CPU 63 is saved in the DE buffer 163c by the LD instruction (step S1704). After that, as "LD (0346H), HL", the information of the HL register 107 of the main CPU 63 is saved in the HL buffer 163d by the LD instruction (step S1705). After that, as "LD (0348H), IX", the information of the IX register 108 of the main CPU 63 is saved in the IX buffer 163e by the LD instruction (step S1706).

After that, as "LD IY, 0300H", "0300H" is set as the non-specific control reference address used when the address of the work area 122 for non-specific control is specified in the IY register 109 by the LD instruction (. Step S1707). As a result, the non-specific control reference address can be used when the first LDY instruction and the second LDY instruction are executed in the non-specific control process.

As described above, when the non-specific control process ends, the specific control reference address (“0000H”) is set in the IY register 109 in step S1605 of the management process (FIG. 56 (a)). .. The non-specific control reference address (“0300H”) is set in the IY register 109 at the start of the management execution process (FIG. 57), which is a process for non-specific control, and the IY is performed at the end of the management execution process (FIG. 57). By returning the information in the register 109 to the specific control reference address (“0000H”), the specific control reference address can be used by the first LDY instruction and the second LDY instruction during the execution of the specific control process, but not. The non-specific control reference address can be made available by the first LDY instruction and the second LDY instruction during the execution of the management execution process which is the process for the specific control. Since the specific control reference address and the non-specific control reference address can be used by switching the data stored in one register, the non-specific control reference address is separated from the register in which the specific control reference address is stored. The number of registers reserved for making these reference addresses available can be reduced as compared to a configuration that reserves registers for which reference addresses are set.

As described above, the main CPU 63 has various general-purpose registers, auxiliary registers, and index registers. In steps S1702 to S1706, the information of WA register 104, BC register 105, DE register 106, HL register 107, and IX register 108, which are some of these various general-purpose registers, auxiliary registers, and index registers, is displayed. It is saved in the corresponding buffer in the work area 122 for non-specific control.

These WA register 104, BC register 105, DE register 106, HL register 107, and IX register 108 are registers used in the check process (step S1708), which is a process corresponding to non-specific control. By saving the information set in such registers to the work area 122 for non-specific control prior to the execution of the check process (step S1708), the information of these registers used for specific control is non-specifically controlled. Can be evacuated before the start of. Therefore, even if these registers are overwritten during the non-specific control, when the non-specific control is terminated, the information saved in the work area 122 for the non-specific control is returned to these registers to return the status of these registers. Can be returned to the state corresponding to the specific control before the non-specific control is executed.

Further, instead of saving all the information of various general-purpose registers, auxiliary registers, and index registers to the work area 122 for non-specific control, WA to be used in the check process, which is a process corresponding to non-specific control. By selectively saving the information of the register 104, the BC register 105, the DE register 106, the HL register 107, and the IX register 108 to the work area 122 for non-specific control, the information of the register in the work area 122 for non-specific control It is possible to reduce the capacity to be secured in order to evacuate. Therefore, it is possible to save the register information as described above while securing a large capacity of the work area 122 for non-specific control that can be used in the check process. As a matter of course, among various general-purpose registers, auxiliary registers and index registers in the main CPU 63, registers other than WA register 104, BC register 105, DE register 106, HL register 107, IX register 108 and IY register 109 are , The information set before the process corresponding to the non-specific control is started is stored and retained until the process corresponding to the non-specific control ends and the process corresponding to the specific control is restarted.

Further, by saving the register information in the work area 122 for non-specific control instead of saving it in the stack area 124 for non-specific control, the capacity of the stack area 124 for non-specific control can be suppressed to a small size. It will be possible. Further, when the stack area 124 for non-specific control is used, the writing order of the information is read first from the later information as described above, so that the reading order of the information is displaced due to some noise or the like. If this happens, all the information in the subsequent read order will be returned to different registers. The probability of occurrence of such an event increases as the amount of information saved in the stack area 124 for non-specific control increases. On the other hand, by saving the register information to the work area 122 for non-specific control, it is possible to prevent the above-mentioned event from occurring even when there is a large amount of information to be saved. ..

After that, the check process is executed (step S1708). When the check process is executed, the program of the subroutine corresponding to the check process set in the program for non-specific control is executed, but when the program of the subroutine is executed, the management after the execution of the check process is executed. Information for specifying the return address of the execution process is written in the stack area 124 for non-specific control by a push instruction. Then, when the check process is completed, the information for specifying the return address is read by the pop instruction, and the program returns to the program of the management execution process indicated by the return address. The details of the check process will be described later.

After executing the check process, Y (r + α) is set as “LD SP, Y (r + α)” in the stack pointer of the main CPU 63 as a fixed address when returning to the specific control by the load instruction (step S1709). ). The address of Y (r + α) is set as an address between “0403H” and “044FH” in the stack area 123 for specific control.

Immediately before the subroutine of the management execution process is executed in step S1603 of the management process (FIG. 56 (a)), the amount of information stored in the stack area 123 for specific control is always constant, and the information is accordingly. The information of the stack pointer of the main CPU 63 (that is, the value of the stack pointer) at the timing is constant. In this case, the information stored in the stack area 123 for specific control includes, for example, the information of the return address of the management process (FIG. 56 (a)) after the management execution process (FIG. 57) is completed, and the management. Information on the return address of the timer interrupt process (FIG. 26) after the process (FIG. 56 (a)) is completed can be mentioned. The above-mentioned constant information of the stack pointer is Y (r + α). Therefore, when the check process corresponding to the non-specific control is completed and the process returns to the process corresponding to the specific control, Y (r + α), which is certain information, is set in the stack pointer of the main CPU 63. This makes it possible to restore the information of the stack pointer to the information immediately before the processing corresponding to the non-specific control is started. By setting fixed information in the stack pointer in this way, the information of the stack pointer is restored to the information immediately before the processing corresponding to the non-specific control is started, so that the processing corresponding to the non-specific control is started. It is not necessary to save the information of the stack pointer of the main CPU 63 corresponding to the specific control to the main RAM 65 before starting. Therefore, it is possible to reduce the processing load, and it is not necessary to secure the area for evacuation in the main RAM 65.

After that, as "LDY WA, (40H)", the information saved in the WA buffer 163a of the work area 122 for non-specific control is overwritten in the WA register 104 of the main CPU 63 by the second LDY instruction (step S1710). “LDY” is the second LDY instruction by the second LDY execution circuit 164, “WA” is the WA register 104, and “(40H)” is the lower area (lower 1) of the WA buffer 163a in the work area 122 for non-specific control. It is the lower 1 byte in the address (“0340H”) of the byte area). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, the information of the WA buffer 163a specified by the address of "0340H" obtained by adding the non-specific control reference address to "40H" by executing "LDY WA, (40H)". Can be restored to the WA register 104. When using the LD instruction, the address data of the WA buffer 163a included in the instruction code of the LD instruction needs to be the entire 2-byte address data ("0340H"), while the second LDY instruction is used. The address data included in the instruction code of the second LDY instruction can be only the lower 1 byte (“40H”) of the 2-byte address data. By using the second LDY instruction to restore the information saved in the WA buffer 163a to the WA buffer 163a, the program is compared with the configuration in which the LD instruction is used to restore the information to the WA buffer 163a. Data capacity can be reduced.

After that, as "LDY BC, (42H)", the information saved in the BC buffer 163b of the work area 122 for non-specific control is overwritten in the BC register 105 of the main CPU 63 by the second LDY instruction (step S1711). “LDY” is the second LDY instruction by the second LDY execution circuit 164, “BC” is the BC register 105, and “(42H)” is the lower area (lower 1) of the BC buffer 163b in the work area 122 for non-specific control. It is the lower 1 byte in the address (“0342H”) of the byte area). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, the information of the BC buffer 163b specified by the address of "0342H" obtained by adding the non-specific control reference address to "42H" by executing "LDY BC, (42H)". Can be restored to the BC register 105. The entire address (2 bytes) must be set by using the second LDY instruction that can specify the address of the BC register 105 by setting only the lower 1 byte in the address of the BC register 105. Compared with the case of using the LD instruction, the data capacity of the instruction for overwriting the information saved in the BC buffer 163b to the BC register 105 can be reduced.

After that, as "LDY DE, (44H)", the information saved in the DE buffer 163c of the work area 122 for non-specific control is overwritten in the DE register 106 of the main CPU 63 by the second LDY instruction (step S1712). “LDY” is the second LDY instruction by the second LDY execution circuit 164, “DE” is the DE register 106, and “(44H)” is the lower area (lower 1) of the DE buffer 163c in the work area 122 for non-specific control. It is the lower 1 byte in the address (“0344H”) of the byte area). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, the information of the DE buffer 163c specified by the address of "0344H" obtained by adding the non-specific control reference address to "44H" by executing "LDY DE, (44H)". Can be restored to the DE register 106. The entire address (2 bytes) must be set by using the second LDY instruction that can specify the address of the DE register 106 by setting only the lower 1 byte in the address of the DE register 106. Compared with the case of using the LD instruction, the data capacity of the instruction for overwriting the information saved in the DE buffer 163c in the DE register 106 can be reduced.

After that, as "LDY HL, (46H)", the information saved in the HL buffer 163d of the work area 122 for non-specific control is overwritten in the HL register 107 of the main CPU 63 by the second LDY instruction (step S1713). "LDY" is the second LDY instruction by the second LDY execution circuit 164, "HL" is the HL register 107, and "(46H)" is the lower area (lower 1) of the HL buffer 163d in the work area 122 for non-specific control. It is the lower 1 byte in the address (“0346H”) of the byte area). As described above, the non-specific control reference address (“0300H”) is stored in the IY register 109 in step S1707. Therefore, the information of the HL buffer 163d specified by the address of "0346H" obtained by adding the non-specific control reference address to "46H" by executing "LDY HL, (46H)". Can be restored to the HL register 107. The entire address (2 bytes) must be set by using the second LDY instruction that can specify the address of the HL register 107 by setting only the lower 1 byte in the address of the HL register 107. Compared with the case of using the LD instruction, the data capacity of the instruction for overwriting the information saved in the HL buffer 163d in the HL register 107 can be reduced.

In this way, the information of the WA register 104, the BC register 105, the DE register 106, and the HL register 107 of the main CPU 63 is returned to the information corresponding to the specific control immediately before the processing corresponding to the non-specific control is started. By using the second LDY instruction in the process (steps S171 to S1713), the data capacity of the program for executing the process is increased as compared with the configuration in which the LD instruction is used in the process. Can be reduced.

After executing the process of step S1713, the information saved in the IX buffer 163e of the work area 122 for non-specific control is stored in the IX register 108 of the main CPU 63 by the LD instruction as "LD IX, (0348H)". Overwrite (step S1714), and this management execution process ends. By executing the processes of steps S171 to S1714, the information of the WA register 104, the BC register 105, the DE register 106, the HL register 107, and the IX register 108 of the main CPU 63 can be processed to correspond to the non-specific control. It is possible to return to the information corresponding to the specific control immediately before the start.

Here, the information stored in the flag register of the main CPU 63 and various registers when the process corresponding to the non-specific control is executed is not saved in the main RAM 65 when the process corresponding to the specific control is restarted. .. As a result, it is not necessary to secure a storage area for saving the above information in the work area 121 for specific control and the stack area 123 for specific control.

Further, when the process corresponding to the non-specific control is executed, the information stored in the flag register and various registers of the main CPU 63 is subjected to the process corresponding to the non-specific control after returning to the process corresponding to the specific control. Information that will not be used if it is restarted. That is, the information required for multiple processing times of the processing corresponding to the non-specific control executed with the processing corresponding to the specific control in between is the work area 122 for the non-specific control or the stack area for the non-specific control. It is stored in 124, and is not stored in the flag register and various registers of the main CPU 63. Therefore, even if the information stored in the flag register of the main CPU 63 and various registers is not saved in the main RAM 65 when the process corresponding to the non-specific control is executed, the process corresponding to the non-specific control is executed. Does not cause any problems.

Next, the check process executed by calling the subroutine program in step S1708 will be described. In the check process, a process for collecting game history information, a process for deriving a game history management result, and a process for notifying the management result are executed. That is, the process for collecting the game history information, the process for deriving the game history management result, and the process for notifying the management result are executed as the processes corresponding to the non-specific control.

Prior to the explanation of the check process, the contents of various counters 171a to 171g, 172a to 172g, and 173a to 173g of the work area 122 for non-specific control used for managing the game history will be described. FIG. 58 is an explanatory diagram for explaining the configuration of the work area 122 for non-specific control.

As shown in FIG. 58, in the work area 122 for non-specific control, the first general winning counter 171a for normal use is provided at the addresses of "0303H" to "0304H", and "0305H" to "0306H". The second general winning counter 171b for normal use is provided at the address of, and the third general winning counter 171c for normal use is provided at the addresses of "0307H" to "0308H", and "0309H" to "0309H". The address of "030AH" is provided with a special electric winning counter 171d for normal use, and the addresses of "030BH" to "030CH" are provided with a first operation counter 171e for normal use, and "030DH" to "030EH" are provided. A second operation counter 171f for normal use is provided at the address of "", and an out counter 171g for normal use is provided at the addresses of "030FH" to "0310H".

In the normal ball entry management process (FIG. 60) described later, the address of the lower area (lower 1-byte area) of the target counter is set in the HL register 107. The work area 122 for non-specific control sets the address of "0303H" corresponding to the lower area of the first general winning counter 171a for normal use in the HL register 107, and then adds 2 to the value of the HL register 107. By repeatedly executing the above, in the normal ball entry management process (FIG. 60), the first general winning counter 171a for normal use → the second general winning counter 171b for normal use → the third general winning counter 171c for normal use → normal use The target counter can be updated in the order of the special electric winning counter 171d → the first operation counter 171e for normal use → the second operation counter 171f for normal use → the out counter 171g for normal use.

As shown in FIG. 58, in the work area 122 for non-specific control, the first general winning counter 172a for the open / close execution mode is provided at the addresses of "0311H" to "0312H", and "0313H" to "0313H". The address of "0314H" is provided with the second general winning counter 172b for the opening / closing execution mode, and the addresses of "0315H" to "0316H" are provided with the third general winning counter 172c for the opening / closing execution mode. , The special electric winning counter 172d for the open / close execution mode is provided at the addresses of "0317H" to "0318H", and the first operation counter 172e for the open / close execution mode is provided at the addresses of "0319H" to "031AH". A second operation counter 172f for the open / close execution mode is provided at the addresses of "031BH" to "031CH", and an out counter 172g for the open / close execution mode is provided at the addresses of "031DH" to "031EH". Is provided.

In the ball entry management process (step S1805 of the check process (FIG. 59)) in the open / close execution mode described later, the address of the lower area (lower 1 byte area) of the target counter is set in the HL register 107. In the work area 122 for non-specific control, the address of "0311H" corresponding to the lower area of the first general winning counter 172a for the open / close execution mode is set in the HL register 107, and then the value of the HL register 107 is added by 2. In the ball entry management process in the open / close execution mode, the first general winning counter 172a for the open / close execution mode → the second general winning counter 172b for the open / close execution mode → the third for the open / close execution mode. General winning counter 172c → Special electric winning counter 172d for open / close execution mode → 1st operation counter 172e for open / close execution mode → 2nd operation counter 172f for open / close execution mode → Out counter 172g for open / close execution mode The data structure is such that the counter can be updated.

As shown in FIG. 58, in the work area 122 for non-specific control, the first general winning counter 173a for the high frequency support mode is provided at the addresses of "031FH" to "0320H", and "0321H" to "0321H". The address of "0322H" is provided with the second general winning counter 173b for the high frequency support mode, and the addresses of "0323H" to "0324H" are provided with the third general winning counter 173c for the high frequency support mode. The special electric winning counter 173d for the high frequency support mode is provided at the addresses of "0325H" to "0326H", and the first address for the high frequency support mode is provided at the addresses of "0327H" to "0328H". The operation counter 173e is provided, the second operation counter 173f for the high frequency support mode is provided at the addresses of "0329H" to "032AH", and the high frequency is provided at the addresses of "032BH" to "032CH". An out counter 173 g for the support mode is provided.

In the ball entry management process (step S1806 of the check process (FIG. 59)) in the high-frequency support mode described later, the address of the lower area (lower 1-byte area) of the target counter is set in the HL register 107. The work area 122 for non-specific control sets the address of "031FH" corresponding to the lower area of the first general winning counter 173a for the high frequency support mode in the HL register 107, and then sets the value of the HL register 107 to 2. By repeatedly executing the addition process, the first general winning counter 173a for the high frequency support mode → the second general winning counter 173b for the high frequency support mode → high frequency support in the ball entry management process during the high frequency support mode. 3rd general winning counter 173c for mode → special electric winning counter 173d for high frequency support mode → 1st operation counter 173e for high frequency support mode → 2nd operation counter 173f for high frequency support mode → for high frequency support mode The data structure is such that the target counter can be updated in the order of the out counter 173 g.

The general winning counters 171a to 171c, 172a to 172c, and 173a to 173c are counters for measuring the number of game balls entering the general winning opening 31 from a predetermined measurement start trigger. The special electric winning counters 171d, 172d, and 173d are counters for measuring the number of game balls entering the special electric winning device 32 from a predetermined measurement start trigger. The first operation counters 171e, 172e, and 173e are counters for measuring the number of game balls entering the first operation port 33 from a predetermined measurement start trigger. The second operation counters 171f, 172f, and 173f are counters for measuring the number of game balls entering the second operation port 34 from a predetermined measurement start trigger. The out counters 171g, 172g, and 173g are counters for measuring the number of game balls entering the out port 24a from a predetermined measurement start trigger.

Each of the counters 171a to 171g for normal use is a ball entry portion 24a, 31 to 34, which is a target in a situation where the front door frame 14 is in a closed state and is neither an open / close execution mode nor a high frequency support mode. It is used to measure the number of game balls that have entered the door. Each of the counters 172a to 172g for the open / close execution mode is a game in which the front door frame 14 is in the closed state and the ball is entered into the target ball entry portions 24a, 31 to 34 in the open / close execution mode. It is used to measure the number of spheres. Each of the counters 173a to 173g for the high frequency support mode enters the ball entry portions 24a and 31 to 34, which are the targets in the situation where the front door frame 14 is closed and the high frequency support mode is used. It is used to measure the number of game balls played.

The situation where the front door frame 14 is in the open state is not subject to measurement because the game ball enters the ball entry portions 24a, 31 to 34 with the front door frame 14 open. This is to exclude the number of balls entered from the measurement target when the ball is hit. However, the present invention is not limited to this, and the situation where the front door frame 14 is in the open state may be configured to be the measurement target in the same manner as the situation where the front door frame 14 is in the closed state.

As shown in FIG. 58, the work area 122 for non-specific control is provided with a calculation result storage area 174. The calculation result storage area 174 is the management result of the game history calculated by using the counters 171a to 171g for normal use, the counters 172a to 172g for the open / close execution mode, and the counters 173a to 173g for the high frequency support mode. This is an area for storing information. The game history management result information stored in the calculation result storage area 174 is stored and retained until the newly calculated information is overwritten by newly calculating the game history management result information.

FIG. 59 is a flowchart showing a check process executed by calling the subroutine program in step S1708. The processing of steps S1801 to S1808 in the check processing, including the processing of the subroutine, is executed by the main CPU 63 using the program for non-specific control and the data for non-specific control. When executing the processing of the subroutine, the information of the return address after the execution of the processing of the subroutine is written in the storage area corresponding to the value of the current stack pointer of the main CPU 63 in the stack area 124 for non-specific control. At the same time, the value of the stack pointer is updated to the information of the address of the storage area to be stored in the next order. Further, when the processing of the subroutine is completed, the information of the return address is read from the storage area corresponding to the value in the previous order with respect to the value of the current stack pointer of the main CPU 63, and the information of the return address is corresponded to. At the same time as returning to the program, the value of the stack pointer is updated to the information of the address of the storage area from which the information of the return address is read.

In the check process, when the front door frame 14 is in the open state (step S1801: YES), the normal ball entry management process (step S1804), the ball entry management process in the open / close execution mode (step S1805), and the high frequency. The result calculation process (step S1807) and the display process (step S1808), which will be described later, are executed without executing any of the ball entry management processes (step S1806) in the support mode. Since the game area PA is formed by the space divided back and forth by the back surface of the window panel 52 provided on the front door frame 14 and the front surface of the game board 24, when the front door frame 14 is opened. Even if the game area PA is opened toward the front and the game ball is launched toward the game area PA in that situation, the game ball cannot normally flow down the game area PA. In addition, when the front door frame 14 is in the open state and the game ball enters the ball entry portions 24a, 31 to 34, the game hall manager may use it for maintenance and to solve the problem. This is a case where the front door frame 14 is opened and a game ball enters due to maintenance or the like. Since the entry of such a game ball is not the entry of a game ball in the normal game execution status, it is not necessary to manage the entry of such a game ball. Therefore, in the check process, when the front door frame 14 is in the open state as described above, none of the processes of steps S1804 to S1806 is executed.

When the front door frame 14 is in the closed state and is neither in the open / close execution mode nor the high frequency support mode (steps S1801 to S1803: NO), a normal ball entry management process is executed (step S1804). Further, when the front door frame 14 is in the closed state and is in the open / close execution mode (step S1801: NO, step S1802: YES), the ball entry management process in the open / close execution mode is executed (step S1805). Further, when the front door frame 14 is in the closed state and is in the high frequency support mode (step S1801: NO, step S1803: YES), the ball entry management process in the high frequency support mode is executed (step S1806).

FIG. 60 is a flowchart showing a normal ball entry management process in step S1804.

In the normal ball entry management process, the command "LDY HL, 03H" is first executed (step S1901). "LDY" is the first LDY instruction by the first LDY execution circuit 156, "HL" is the content for setting the HL register 107 as the "transfer destination", and "03H" is the lower level of the first general winning counter 171a for normal use. It is the lower 1 byte of "0303H" which is the address where the area is set. As described above, the IY register 109 stores "0300H" as a reference address for non-specific control. When "LDY HL, 03H" is executed, "0303H" obtained by adding the non-specific control reference address stored in the IY register 109 to the "03H" is the "transfer destination". It is loaded into the HL register 107. As a result, the address of the lower area in the first general winning counter 171a for normal use can be set in the HL register 107. In the ball entry management process in the open / close execution mode in step S1805 of the check process (FIG. 59), "LDY HL, 11H" is executed to correspond to the lower area of the first general winning counter 172a for the open / close execution mode. By setting the address "0311H" in the HL register 107 and executing "LDY HL, 1FH" in the ball entry management process during the high frequency support mode in step S1806, the first general prize for the high frequency support mode is won. The address "031FH" corresponding to the lower area of the counter 173a is set in the HL register 107.

As described above, when the LD instruction is used, the address data included in the instruction code of the LD instruction must be the entire 2-byte address data, while when the first LDY instruction is used, the first LDY instruction is used. The address data included in the instruction code of the 1LDY instruction can be only the lower 1 byte of the 2-byte address data. By using the first LDY instruction to set the address corresponding to the lower area of the first general winning counters 171a to 173a in the HL register 107, the address is set in the HL register 107 by using the LD instruction. The data capacity of the program can be reduced as compared with the configuration.

As described above, in the normal ball entry management process, the address of the lower area of the target counter is set in the HL register 107. By setting the address corresponding to the lower area of the normal first general winning counter 171a in the HL register 107 in step S1901, the normal first general winning counter 171a is selected as the target counter. be able to. The target counter is updated by adding "2" to the value of the HL register 107 in step S1905, which will be described later.

After executing the process of step S1901, the information of the first winning opening detection sensor 42a corresponding to the first general winning counter 171a for normal use is set as the information of the target detection sensor (step S1902). The information of the target detection sensor is updated in step S1907 described later.

After that, it is determined whether or not a fall from the HI state of the detection signal received from the target detection sensor to the LOW state is detected (step S1903), and when the fall is detected (step S1903: YES). Is added by 1 to the value of the target counter (step S1904). As described above, the target counter is grasped based on the address data stored in the HL register 107.

When a negative determination is made in step S1903, or when the process of step S1904 is performed, the target counter is updated by adding 2 to the value of the HL register 107 (step S1905). In step S1905, the first general winning counter 171a for normal use → the second general winning counter 171b for normal use → the third general winning counter 171c for normal use → the special electric winning counter 171d for normal use → the first operation counter 171e for normal use. → The target counter is updated in the order of the second operation counter 171f for normal use → the out counter 171 g for normal use. In the ball entry management process (step S1805) in the open / close execution mode, the first general winning counter 172a for the open / close execution mode → the second general winning counter 172b for the open / close execution mode → the third general winning counter for the open / close execution mode. Counter 172c → Special electric winning counter 172d for open / close execution mode → 1st operation counter 172e for open / close execution mode → 2nd operation counter 172f for open / close execution mode → Out counter 172g for open / close execution mode In addition to being updated, in the ball entry management process (step S1806) during the high frequency support mode, the first general winning counter 173a for the high frequency support mode → the second general winning counter 173b for the high frequency support mode → high frequency support 3rd general winning counter 173c for mode → special electric winning counter 173d for high frequency support mode → 1st operation counter 173e for high frequency support mode → 2nd operation counter 173f for high frequency support mode → for high frequency support mode The target counter is updated in the order of the out counter 173g.

After that, it is determined whether or not "0311H", which is the end address of the normal ball entry management process, is stored in the HL register 107 (step S1906). If a negative determination is made in step S1906, the target detection sensor is updated to the detection sensor corresponding to the target counter after being updated in step S1905. In step S1907, the first winning opening detection sensor 42a → the second winning opening detection sensor 43a → the third winning opening detection sensor 44a → the special electric detection sensor 45a → the first operating opening detection sensor 46a → the second operating opening detection sensor 47a → out. The target detection sensor is updated in the order of the mouth detection sensor 48a.

After that, the process returns to step S1903, and the processes of steps S1903 to S1907 are executed for the combination of the target counter and the target detection sensor updated in steps S1905 and S1907. The processes of steps S1903 to S1907 are repeatedly executed until a positive determination is made in step S1906. As a result, the processing of steps S1903 to S1907 can be executed with all of the normal counters 171a to 171g as target counters. If an affirmative judgment is made in step S1907, the normal ball entry management process is terminated.

As described above, in the normal ball entry management process, the values of the normal counters 171a to 171g corresponding to the case where one game ball is detected by the detection sensors 42a to 48a are added by 1. As a result, the number of balls entering the ball entry portions 24a, 31 to 34 in a situation that is neither the open / close execution mode nor the high frequency support mode can be grasped by the main CPU 63. Further, in the ball entry management process in the open / close execution mode, the values of the counters 172a to 172g for the open / close execution mode corresponding to the case where one game ball is detected by the detection sensors 42a to 49a are added by 1. .. This makes it possible for the main CPU 63 to grasp the number of balls entering the ball entry portions 24a, 31 to 34 in the open / close execution mode. Furthermore, in the ball entry management process during the high frequency support mode, the value of each counter 173a to 173g for the high frequency support mode corresponding to the case where one game ball is detected by the detection sensors 42a to 49a is 1. Will be added. This makes it possible for the main CPU 63 to grasp the number of balls entering the ball entry portions 24a, 31 to 34 in the high frequency support mode.

By executing the processes of steps S1804 to S1806 in the check process (FIG. 59), the number of game balls entered into the general winning opening 31 uses the general winning counters 171a to 171c, 172a to 172c, and 173a to 173c. The number of game balls entering the special electric winning device 32 is measured using the special electric winning counters 171d, 172d, and 173d, and the number of gaming balls entering the first operating port 33 is the first operation. The counters 171e, 172e, and 173e are used to measure, and the number of game balls entering the second operating port 34 is measured using the second operating counters 171f, 172f, and 173f, and the game balls to the out port 24a are measured. The number of balls entered is measured using the out counters 171 g, 172 g, and 173 g. This makes it possible for the main CPU 63 to grasp the history of ball entry into each of the ball entry units 24a, 31 to 34. Further, since the counters 171a to 171g for normal use, the counters 172a to 172g for the open / close execution mode, and the counters 173a to 173g for the high frequency support mode are separately provided, the open / close execution mode and the high are provided. The main CPU 63 has a history of entering each of the ball entry units 24a and 31 to 34 by distinguishing between a situation in which neither the frequency support mode is available, a situation in which the open / close execution mode is used, and a situation in which the high frequency support mode is used. It becomes possible to grasp.

Returning to the explanation of the check process (FIG. 59), when an affirmative determination is made in step S1801, the process of step S1804 is executed, the process of step S1805 is executed, or the process of step S1806 is executed. , The result calculation process is executed (step S1807). In the result calculation process, the values of the normal counters 171a to 171g, the values of the open / close execution mode counters 172a to 172g, and the values of the high frequency support mode counters 173a to 173g are all summed up. The number is calculated, and it is determined whether or not the calculated total number is equal to or greater than the calculation reference number "6000". Then, when the total number is equal to or greater than the calculation reference number, various parameters are calculated so that the game history can be grasped, and the calculation result is stored in the work area 122 for non-specific control. Store in area 174. After that, the values of the counters 171a to 171g for the normal use, the values of the counters 172a to 172g for the open / close execution mode, and the values of the counters 173a to 173g for the high frequency support mode are cleared by "0".

After performing the result calculation process in step S1807, the display process is executed (step S1808), and the present check process is completed. In the display process in step S1808, the first to third notification display devices 69a to display corresponding to the management result of the game history are performed based on the calculation result stored in the calculation result storage area 174. The display of 69c is controlled. The manager of the game hall can confirm the management result of the game history by confirming the display of the first to third notification display devices 69a to 69c.

As described above, when the non-specific control process ends, the specific control reference address (“0000H”) is set in the IY register 109 in step S1605 of the management process (FIG. 56 (a)). The non-specific control reference address (“0300H”) is set in the IY register 109 at the start of the management execution process (FIG. 57), which is a process for non-specific control, and the IY is performed at the end of the management execution process (FIG. 57). By returning the information in the register 109 to the specific control reference address (“0000H”), the specific control reference address can be used by the first LDY instruction and the second LDY instruction during the execution of the specific control process, but not. The non-specific control reference address can be made available by the first LDY instruction and the second LDY instruction during the execution of the management execution process which is the process for the specific control. Since the specific control reference address and the non-specific control reference address can be used by switching the data stored in one register, the non-specific control reference address is separated from the register in which the specific control reference address is stored. The number of registers reserved for making these reference addresses available can be reduced as compared to a configuration that reserves registers for which reference addresses are set.

In steps S171 to S1713 of the management execution process (FIG. 57), the WA registers 104 and BC corresponding to the information saved in the WA buffer 163a, the BC buffer 163b, the DE buffer 163c, and the HL buffer 163d by using the second LDY instruction. The configuration for returning to the registers 105, DE registers 106, and HL registers 107 is compared with the configuration for returning the information saved in these buffers 163a to 163e to these registers 104 to 107 by using the LD instruction. Therefore, the data capacity of the program for restoring the information can be reduced.

In step S1901 of the normal ball entry management process (FIG. 60), the address of the lower area (“0303H”) in the normal first general winning counter 171a is set by using the first LDY command (“LDY HL, 03H”). By setting the address in the HL register 107, the data capacity of the program for setting the address in the HL register 107 is reduced as compared with the configuration in which the address is set in the HL register 107 by using the LD instruction. can do. Further, in the ball entry management process in the open / close execution mode in step S1805 of the check process (FIG. 59), the first general winning counter 172a for the open / close execution mode is used by using the first LDY command (“LDY HL, 11H”). By setting the address corresponding to the lower area (“0311H”) in the HL register 107, the address is set in the HL register 107 as compared with the configuration in which the address is set in the HL register 107 using the LD instruction. The data capacity of the program for setting in 107 can be reduced. Furthermore, in the ball entry management process during the high frequency support mode in step S1806 of the check process (FIG. 59), the first general prize for the high frequency support mode is used by using the first LDY command (“LDY HL, 1FH”). By setting the address (“031FH”) corresponding to the lower area of the counter 173a in the HL register 107, the address is set in the HL register 107 as compared with the configuration in which the LD instruction is used to set the address in the HL register 107. The data capacity of the program for setting the HL register 107 can be reduced.

Next, communication between the main CPU 63 and the sound / light side CPU 93 or the payout side CPU 83 will be described.

As described above with reference to FIG. 8, the main control board 61 is provided with the first transmission circuit 101, the second transmission circuit 102, and the reception circuit 103. The first transmission circuit 101 is a circuit for transmitting various commands from the main CPU 63 to the sound light side CPU 93. The first transmission circuit 101 is provided with a transmission standby buffer 175 (FIG. 61) in which a command to be transmitted is temporarily stored, and the main CPU 63 has a command to be transmitted in the transmission standby buffer 175 (described later). Command for communication) is set. The first transmission circuit 101 transmits a command set in the transmission standby buffer 175 to the sound / light side reception circuit 96 by communicating with the sound / light side reception circuit 96 provided on the voice emission control board 91. The sound light side receiving circuit 96 is provided with a post-reception standby buffer 178 (FIG. 61) in which received commands are temporarily stored, and commands received from the main CPU 63 are stored in the post-reception standby buffer 178. Then, it can be used by the sound and light side CPU 93. The details of communication between the main CPU 63 and the sound light side CPU 93 will be described later.

The second transmission circuit 102 is a circuit for transmitting various commands from the main CPU 63 to the payout side CPU 83. The second transmission circuit 102 is provided with a transmission standby buffer (not shown) for temporarily storing a command to be transmitted, and the main CPU 63 sets a command to be transmitted in the transmission standby buffer. The second transmission circuit 102 transmits the command set in the transmission standby buffer to the payout side reception circuit 87 by communicating with the payout side reception circuit 87 provided on the payout control board 81. The payout side receiving circuit 87 is provided with a post-reception standby buffer (not shown) in which received commands are temporarily stored, and commands received from the main CPU 63 are stored in the post-reception standby buffer and are dispensed. It can be used by the side CPU 83.

The receiving circuit 103 is a circuit for receiving various commands transmitted from the payout side CPU 83. The payout control board 81 is provided with a payout side transmission circuit (not shown) for transmitting various commands from the payout side CPU 83 to the main side CPU 63. The payout side transmission circuit is provided with a transmission standby buffer (not shown) in which a command to be transmitted is temporarily stored, and the payout side CPU 83 sets a command to be transmitted in the transmission standby buffer. The payout side transmission circuit transmits the command set in the transmission standby buffer to the reception circuit 103 by communicating with the reception circuit 103 provided on the main control board 61. The receiving circuit 103 is provided with a post-reception standby buffer (not shown) in which received commands are temporarily stored, and commands received from the payout side CPU 83 are stored in the post-reception standby buffer and are stored in the main CPU 63. It will be available at.

<Data structure of commands transmitted from the main CPU 63>
Next, the data structure of the command transmitted from the main CPU 63 to the payout side CPU 83 or the sound light side CPU 93 will be described by taking as an example the data structure of the command transmitted from the main side CPU 63 to the sound light side CPU 93. ..

FIG. 61 is an explanatory diagram for explaining the electrical configuration of the main control board 61 and the sound emission control board 91 for transmitting a command from the main CPU 63 to the sound light side CPU 93. As described above, the main control board 61 is provided with the first transmission circuit 101, and the voice emission control board 91 is provided with the sound light side reception circuit 96. As shown in FIG. 61, the first transmission circuit 101 is provided with a transmission standby buffer 175 in which a command to be transmitted to the sound / light side CPU 93 (a command for communication described later) is set. The transmission standby buffer 175 is a ring buffer consisting of 30 bytes. Among the commands transmitted from the main CPU 63 to the sound and light side CPU 93, the command with the largest amount of data is the normal return command, and the normal return command set in the transmission standby buffer 175 (normal return command for communication described later). ) Is 14 bytes.

When it is time to set a new command while the command being transmitted remains in the transmission standby buffer 175, the new command is next to the area in which the command being transmitted is set in the transmission standby buffer 175. It is set in the subsequent area and enters the transmission standby state. Further, when it is time to set a new command in a state where a command being transmitted and a command waiting for transmission exist in the transmission waiting buffer 175, the new command is waiting for transmission in the transmission waiting buffer 175. It is set to the area after the area where the command of is set and the transmission standby state is set. The first transmission circuit 101 transmits the commands set in the transmission standby buffer 175 to the sound / light side receiving circuit 96 in the order set in the transmission standby buffer 175. The data capacity of the transmission standby buffer 175 is set to be larger than the total data capacity of a plurality of commands that may exist in the transmission standby buffer 175 at the same time. Therefore, at the timing when each command is set in the transmission standby buffer 175, a free area for setting the command is secured.

The first transmission circuit 101 is provided with a transmission buffer 176 in which data to be transmitted to the sound / light side CPU 93 is set. The transmission buffer 176 consists of 1 byte. The command set in the transmission standby buffer 175 is set in the transmission buffer 176 byte by byte and transmitted to the sound / light side CPU 93. Specifically, when a command is set in the transmission standby buffer 175, the first transmission circuit 101 first transmits the 1-byte data existing at the beginning of the plurality of bytes of data included in the command. It is set in the buffer 176, and the 1-byte data is transmitted to the sound / light side CPU 93. After that, the first transmission circuit 101 sets the 1-byte data set next to the first 1-byte data among the plurality of bytes included in the command in the transmission buffer 176, and sets the 1-byte data in the transmission buffer 176. Data is transmitted to the sound / light side CPU 93. In this way, the first transmission circuit 101 sets one byte of the plurality of bytes of data contained in the command in the transmission buffer 176 until the entire transmission of the command stored in the transmission standby buffer 175 is completed. The process of transmitting the 1-byte data set in the transmission buffer 176 to the sound-light side CPU 93 is repeatedly executed while sequentially updating the data of.

As shown in FIG. 61, the sound light side receiving circuit 96 has a reception buffer 177 in which 1-byte data received from the first transmission circuit 101 is stored, and a command received from the main CPU 63 after reception. A standby buffer 178 is provided. The post-reception standby buffer 178 is a ring buffer composed of 30 bytes, similar to the transmission standby buffer 175 in the first transmission circuit 101 described above. The storage capacity of the post-reception standby buffer 178 is set to be larger than the total amount of data in a plurality of commands that may exist in the post-reception standby buffer 178 at the same time.

The sound light side RAM 95 is provided with a command storage buffer 179 in which commands received from the main side CPU 63 are stored in a state in which the sound light side CPU 93 can be used. The command storage buffer 179 is a ring buffer consisting of 30 bytes. After receiving, the command stored in the standby buffer 178 is transferred to the command storage buffer 179 and stored in the command storage buffer 179 until it is used by the sound and light side CPU 93. The storage capacity of the command storage buffer 179 is set to be larger than the total amount of data in a plurality of commands that may exist in the command storage buffer 179 at the same time.

The sound light side receiving circuit 96 can receive the next 1-byte data by setting the 1-byte data stored in the receiving buffer 177 in the standby buffer 178 after receiving and clearing the receiving buffer 177 to "0". Make it a state. Then, a receivable signal is output to the first transmission circuit 101. When the first transmission circuit 101 is receiving the receivable signal and the data is set in the transmission buffer 176, the first transmission circuit 101 uses the 1-byte data set in the transmission buffer 176 on the sound light side. It transmits to the receiving circuit 96.

Next, a case where a command having a data amount of 3 bytes or more at the time of transmission is transmitted from the main CPU 63 to the sound light side CPU 93 will be described. The command transmitted from the main CPU 63 to the sound light side CPU 93 includes the header HD and the footer FT. 62 (a) is an explanatory diagram for explaining the data structure of the header HD, and FIG. 62 (b) is an explanatory diagram for explaining the data structure of the footer FT.

As shown in FIG. 62 (a), the header HD is 1-byte data composed of the 0th to 7th bits. Command identification data that enables the type of command to be grasped is set in the 0th to 7th bits of the header HD. The sound light side CPU 93 grasps the type of the received command based on the command identification data.

The most significant bit (7th bit) of the command identification data is a header identification bit that makes it possible to identify the header HD. "1" is set in the header identification bit. Of the 1-byte data included in the command, the data in which "1" is set in the most significant bit is only the header HD. The sound light side receiving circuit 96 determines whether or not "1" is set in the most significant bit of the 1-byte data stored in the reception buffer 177, so that the 1-byte data is the header HD. Know if or not. When the sound light side receiving circuit 96 receives a plurality of commands from the first transmission circuit 101, the sound light side receiving circuit 96 can grasp the demarcation position of these commands based on the position of the header HD. In addition, "0" may be set in the header identification bit, and "1" may be set in the most significant bit (7th bit) of the data other than the header HD. In the configuration, the sound / light side receiving circuit 96 determines whether or not "0" is set in the most significant bit of the 1-byte data stored in the reception buffer 177, so that the 1-byte data can be stored. It is possible to grasp whether or not the header HD is used.

As shown in FIG. 62 (b), the footer FT is 1-byte data composed of the 0th to 7th bits. The footer FT includes footer identification data indicating that it is a footer FT, and an error detection bit that enables the sound light side receiving circuit 96 to confirm that the content of the command data has not changed due to the influence of noise. Is set. The upper 7 bits (1st to 7th bits) of the footer FT are set with the data "0101010" as the footer identification data. Of the 1-byte data included in the command transmitted from the main CPU 63 to the sound light side CPU 93, the data in which the "0101010" is set in the upper 7 bits is only the footer FT. The sound light side receiving circuit 96 determines whether or not the footer identification data is set in the upper 7 bits of the 1-byte data stored in the reception buffer 177, and thus determines whether the 1-byte data is the footer FT. Know if or not. The sound light side receiving circuit 96 grasps the start position of the command by recognizing the header HD, and grasps the end position of the command by recognizing the footer FT. Then, a series of data starting from the header HD and ending with the footer FT is recognized as one command.

An error detection bit is set in the 0th bit of the footer FT. The error detection bit is set to "0" or "1" so that the total number of "1" in the information of "0" and "1" included in the command is an even number. When a command is stored in the standby buffer 178 after reception, the sound light side receiving circuit 96 determines whether or not the total number of "1" contained in the command is an even number, and determines whether or not the total number of "1" is even. If is not an even number, know that a communication error has occurred. As a result, it is possible to prevent the command rewritten by noise from being used as it is in the sound light side CPU 93.

The sound light side receiving circuit 96 receives the footer FT after receiving the header HD and when the 1-byte data received next to the footer FT from the first transmission circuit 101 is data other than the header HD. It is grasped that the communication error has occurred even when the next header HD is received without. As a result, it is possible to prevent data different from the data included in the command set in the transmission standby buffer 175 by the main CPU 63 from being used by the sound and light side CPU 93.

When the sound light side receiving circuit 96 identifies the occurrence of a communication error, it outputs a retransmission request signal to the first transmitting circuit 101. If the first transmission circuit 101 does not receive the retransmission request signal after the transmission of the command is completed, the first transmission circuit 101 deletes the data of the command whose transmission has been completed this time from the transmission standby buffer 175. Then, when the next command is set in the transmission standby buffer 175, the transmission of the next command is started. On the other hand, when the retransmission request signal is received after the transmission of the command is completed, the command stored in the transmission standby buffer 175 is transmitted again.

As shown in FIG. 61, the sound light side receiving circuit 96 is provided with a communication error counter 181 that counts the number of consecutive communication errors. Numerical information of "0" to "3" is stored in the communication error counter 181. The sound / light side receiving circuit 96 adds 1 to the value of the communication error counter 181 when the retransmission request signal is output, and communicates when the occurrence of a communication error is not confirmed for the command received after the output of the retransmission request signal. Clear the error counter 181 to "0". When the value of the communication error counter 181 reaches "3", the sound / light side CPU 93 controls the light emission of the display light emitting unit 53, controls the sound output of the speaker unit 54, and displays the symbol 41 so that the communication error notification is performed. Display control is performed. As a result, it is possible to notify the manager of the game hall that the command is not normally transmitted from the main CPU 63 to the sound / light side CPU 93.

The command stored in the transmission standby buffer 175 and the 1-byte data stored in the transmission buffer 176 are partially cleared (step S107) or completely cleared (step S114) in the main process (FIG. 15). Cleared if done.

When one or more 1-byte data other than the header HD and the footer FT are set in the command transmitted from the main CPU 63 to the sound and light side CPU 93, the main CPU 63 is a command for communication in which the amount of data is 4 bytes or more. Is generated, and the command for the communication is set in the transmission standby buffer 175. The command for communication is transmitted from the first transmission circuit 101 to the sound light side reception circuit 96, and is stored in the standby buffer 178 after reception. When the amount of command data stored in the post-reception standby buffer 178 is 4 bytes or more, that is, when the post-reception standby buffer 178 stores a command for communication, the sound and light side CPU 93 performs the communication. After conversion, the command for is converted into a command and stored in the command storage buffer 179. Then, the effect is performed based on the converted command stored in the command storage buffer 179.

In addition to the header HD and the footer FT, the variation command transmitted to the sound light side CPU 93 in the variation command transmission process (FIG. 68) in step S1014 of the special figure variation start process (FIG. 35) includes specific control. The display duration data stored in the display duration counter 142 (FIG. 51 (b)) in the work area 121 is set. As described above, the display duration data is 2-byte numerical data. If the data stored in the display duration counter 142 is set between the header HD and the footer FT to generate the variable command, the frame (1 byte) other than the header HD included in the variable command is generated. There is a possibility that "1" is set in the most significant bit (7th bit) in the data). In the configuration, if the variable command is set in the transmission standby buffer 175 as it is, the frame other than the header HD (the frame in which the display duration data is set) in the sound light side receiving circuit 96 is the header HD. Is mistakenly recognized. In the present embodiment, the main CPU 63 generates a variable command for communication in which the most significant bit (7th bit) in a frame other than the header HD is changed to "0", and waits for transmission of the variable command for communication. Set to buffer 175. As a result, the header HD and the frame other than the header HD are identified by the sound light side receiving circuit 96, assuming that "0" is always set for the most significant bit (7th bit) in the frame other than the header HD. It can be possible. Hereinafter, in the present specification, the 1-byte data included in the command is also referred to as a “frame”.

On the other hand, for example, the return command at the time of clearing all transmitted to the sound light side CPU 93 in step S116 of the main process (FIG. 15) is a 2-byte command consisting of only the header HD and the footer FT. As described above, the most significant bit (7th bit) of the footer FT is "0". Therefore, in the 2-byte command consisting only of the header HD and the footer FT, whether or not the most significant bit (7th bit) of each frame is "0" is determined to determine whether the frame is the header HD. It is a command that can identify whether or not. In the present embodiment, when data other than the header HD and the footer FT is not set in the command transmitted from the main CPU 63 to the sound light side CPU 93, the main CPU 63 keeps the 2-byte command consisting of only the header HD and the footer FT. Set to the transmission standby buffer 175. The command is transmitted from the first transmission circuit 101 to the sound light side reception circuit 96, and is stored in the standby buffer 178 after reception. When the data amount of the command stored in the standby buffer 178 after reception is 2 bytes, the sound and light side CPU 93 stores the command as it is in the command storage buffer 179.

In the following, the data structure of the command including the frame other than the header HD and the footer FT will be described by taking a variable command and a normal return command as an example.

First, the data structure of the variable command will be described. FIG. 62 (c) is an explanatory diagram for explaining the data structure of the variable command for communication, and FIG. 62 (d) is an explanatory diagram for explaining the data structure of the variable command after conversion.

As shown in FIG. 62 (c), the variable command for communication includes five frames in the order of header HD → first data frame FR1 → second data frame FR2 → first highest frame SF1 → footer FT. Is set. As described above, 1 byte of data is set in each frame. The data stored in the lower area of the display duration counter 142 is set in the first data frame FR1, and the data stored in the upper area of the display duration counter 142 is set in the second data frame FR2. It is set. However, the data set in the most significant bit (7th bit) of these data frames FR1 and FR2 is changed to "0" so that the header HD and these data frames FR1 and FR2 can be distinguished. To.

The number of data frames FRm (m is an integer of 1 to 10) included in the command for communication varies depending on the type of command. A maximum of 10 data frames FRm are set in the command for communication. The first most significant frame SF1 is a frame that makes it possible to grasp the data of the most significant bit changed to "0" among the data set in the first to seventh data frames FR1 to FR7. The first highest frame SF1 is set between the last data frame FRm and the footer FT when the number of data frames FRm included in the command for communication is 7 or less. The first (m-1) bit (m is an integer of any of 1 to 7) of the first most significant frame SF1 corresponds to the most significant bit of the mth data frame FRm. For example, the 0th bit of the first most significant frame SF1 corresponds to the most significant bit of the first data frame FR1, and the first bit of the first most significant frame SF1 corresponds to the most significant bit of the second data frame FR2. It corresponds. The data of the most significant bit in the lower area of the display duration counter 142 is set to the 0th bit of the first most significant frame SF1, and the data of the most significant bit in the upper area of the display duration counter 142 is the first most significant bit. It is set to the first bit of the frame SF1.

As described above, the number of data frames FRm included in the variable command for communication is two, and there is no corresponding data frame in the second to sixth bits in the first highest frame SF1. As shown in FIG. 62 (c), “0” is set in the second to sixth bits of the first highest frame SF1 in the variable command for communication. As described above, the number of data frame FRm included in the command for communication is 6 or less, and among the 0th to 6th bits in the first highest-level frame SF1, the bits in which the corresponding data frame FRm does not exist are set to "0". Is set. “0” is always set in the most significant bit (7th bit) in the first most significant frame SF1. Thereby, the header HD and the first highest frame SF1 can be distinguished in the sound light side receiving circuit 96.

As shown in FIG. 62 (d), a header HD, a first data frame FR1, a second data frame FR2, and a footer FT are set in the post-conversion variation command. The header HD of the variable command for communication, the header HD of the variable command for communication, the header HD of the variable command for communication in the header HD of the variable command after conversion, the 0th to 6th bits of the first data frame FR1, the 0th to 6th bits of the second data frame FR2, and the footer FT. The data of the 0th to 6th bits of the first data frame FR1, the 0th to 6th bits of the second data frame FR2, and the footer FT are set. Further, in the most significant bit of the data frames FR1 and FR2 of the post-conversion variable command, the data of the corresponding bit in the first most significant frame SF1 of the variable command for communication is set. Specifically, the most significant bit of the first data frame FR1 of the post-conversion variable command contains the data of the 0th bit corresponding to the most significant bit in the first most significant frame SF1 of the variable command for communication. It is set. Further, in the most significant bit of the second data frame FR2 of the post-conversion variable command, the data of the first bit corresponding to the most significant bit in the first most significant frame SF1 of the variable command for communication is set. There is.

In this way, the first most significant frame SF1 that collects the information of the most significant bits of the first and second data frames FR1 to FR2 is set in the variable command for communication. As a result, while making it possible to distinguish between the header HD and the frame other than the header HD in the variable command for communication, the data of the most significant bit in various counters in which the data is set in the variable command for communication is stored in the sound / optical side CPU93. It can be grasped at.

As shown in FIG. 61, the work area 121 for specific control is provided with a first evacuation area 182 and a second evacuation area 183. The first evacuation area 182 is an area where the data of the first highest frame SF1 is set, and the second evacuation area 183 is an area where the data of the second highest frame SF2, which will be described later, is set. These evacuation areas 182 and 183 consist of 1 byte. When the communication command transmitted from the main CPU 63 to the sound light side CPU 93 includes 1 to 7 data frames FRm, the first save area 182 includes the first to m data frames FR1 to FRm (1 to FRm). The data of the most significant bit (m is an integer of 1 to 7) is set. When the communication command transmitted from the main CPU 63 to the sound light side CPU 93 includes 8 to 10 data frames FRm, the first save area 182 includes the first to seventh data frames FR1 to FR7. The data of the most significant bit is set, and the data of the most significant bit of the 8th to mth data frames (m is an integer of 8 to 10) is set in the second save area 183.

FIG. 63 is an explanatory diagram for explaining a mode of generating a variable command for communication. The data of the most significant bit in the lower area of the display duration counter 142 is set to the 0th bit of the first save area 182, and the data of the most significant bit in the upper area of the display duration counter 142 is set to the first save area 182. Is set to the first bit of. Further, "0" is set in the second to sixth bits in which the corresponding counter does not exist in the first evacuation area 182. Furthermore, "0" is always set in the most significant bit (7th bit) of the first save area 182. As described above, the sound and light side reception is configured so that "0" is always set in the most significant bit (7th bit) in the data of the first highest frame SF1 stored in the first evacuation area 182. In the circuit 96, the header HD and the first most significant frame SF1 can be distinguished from each other.

As shown in FIG. 61, the first transmission circuit 101 is provided with a write pointer 186. The write pointer 186 is a pointer that allows the main CPU 63 to grasp the command write start position in the transmission standby buffer 175. The main CPU 63 grasps the free area of the transmission standby buffer 175 based on the value of the write pointer 186. Then, the data of the header HD, the data stored in the lower area of the display duration counter 142, the data stored in the upper area of the display duration counter 142, and the data stored in the first save area 182 are stored in the grasped empty area. Set the data and footer FT data. In the transmission standby buffer 175, the most significant bit (7th bit) in the area where data other than the header HD and the footer FT is set is cleared to "0". As a result, a variable command for communication is set in the transmission standby buffer 175.

Next, the data structure of the normal return command will be described. FIG. 64 is an explanatory diagram for explaining the data structure of the normal return command for communication, and FIG. 65 is an explanatory diagram for explaining the data structure of the converted normal return command.

As shown in FIG. 64, the normal return command for communication includes header HD → 1st data frame FR1 to 7th data frame FR7 → 1st highest frame SF1 → 8th data frame FR8 to 10th data frame FR10 →. 14 frames are set in the order of the second highest frame SF2 → footer FT. As described above, 1 byte of data is set in each frame.

The data stored in the set value counter in the work area 121 for specific control is set in the first data frame FR1 in the normal return command for communication. This makes it possible for the sound / light side CPU 93 to grasp the current set value of the pachinko machine 10. The data stored in the first special figure hold number counter 118 in the work area 121 for specific control is set in the second data frame FR2, and the data stored in the work area 121 for specific control is set in the third data frame FR3. The data stored in the second special figure hold number counter 119 is set. As a result, the number of holdings in the first special drawing holding area 115 and the number of holdings in the second special drawing holding area 116 can be grasped by the sound light side CPU 93. The data stored in the mode data area in the work area 121 for specific control is set in the fourth data frame FR4. As described above, the high frequency support mode flag and the open / close execution mode flag are set in the mode data area. Since the data in the mode data area is included in the normal return command, it is possible for the sound and light side CPU 93 to grasp whether or not the high frequency support mode and the open / close execution mode are used. The data stored in the round counter in the work area 121 for specific control is set in the fifth data frame FR5. As a result, the number of remaining round games in the open / close execution mode can be grasped by the sound / light side CPU 93. In the sixth data frame FR6, the data stored in the hit / fail data area 158 in the work area 121 for specific control is set. As described above, the small hit flag 158b is set in the 0th bit of the pass / fail data area 158, and the big hit flag 158a is set in the first bit. Since the data of the hit / fail data area 158 is included in the normal return command, it is possible for the sound / light side CPU 93 to know that the big hit result has occurred and that the small hit result has occurred. The data stored in the distribution data area 162 is set in the seventh data frame FR7. As described above, the 4R high accuracy flag 162a is set in the 0th bit of the distribution data area 162, the 8R high accuracy flag 162b is set in the first bit, and the 16R high accuracy flag is set in the second bit. The probability flag 162c is set. It sounds that the 4R high-accuracy jackpot result has occurred, the 8R high-accuracy jackpot result has occurred, and the 12R high-accuracy jackpot result has occurred because the data in the distribution data area 162 is included in the normal return command. It can be grasped by the optical side CPU 93. The data stored in the game round area is set in the eighth data frame FR8. As described above, the game round flag is set in the 0th bit of the game round area. Since the normal return command includes the data of the game round area, it is possible for the sound and light side CPU 93 to grasp whether or not the game round is being executed. As described above, based on the winning of any of the operating ports 33 and 34, the display is started by any of the special figure display units 37a and 37b and the symbol display device 41, and the predetermined result is displayed and ended. Until it is done, it corresponds to one game. The data stored in the lower area of the special figure special electric timer counter in the work area 121 for specific control is set in the ninth data frame FR9, and the upper side of the special figure special electric timer counter is set in the tenth data frame FR10. The data stored in the area is set. As a result, when the game round is being executed, the remaining display duration in the game round can be grasped by the sound / light side CPU 93. However, the data set in the most significant bit (7th bit) of these data frames FR1 to FR10 is changed to "0" so that the header HD and these data frames FR1 to FR10 can be distinguished. To.

Assuming that the data stored in the display duration counter 142 is set in the 9th to 10th data frames FR9 to FR10 to generate a normal return command, the most significant bit (7th bit) of these frames FR9 and FR10 is generated. ) May be set to "1". In this configuration, if the normal return command is set in the transmission standby buffer 175 as it is, the frames other than the header HD (9th data frame FR9 and 10th data frame FR10) in the sound light side receiving circuit 96 are in the header HD. If there is, it will be mistakenly recognized. In the present embodiment, the main CPU 63 generates a normal return command for communication in which the most significant bit (7th bit) in a frame other than the header HD is changed to "0", and waits for transmission of the normal return command for the communication. Set to buffer 175. As a result, the header HD and the frame other than the header HD are identified by the sound light side receiving circuit 96, assuming that "0" is always set for the most significant bit (7th bit) in the frame other than the header HD. It can be possible.

As described above, the first most significant frame SF1 is a frame that makes it possible to grasp the data of the most significant bit changed to "0" among the data set in the first to seventh data frames FR1 to FR7. .. The first highest frame SF1 is set between the 7th data frame FR7 and the 8th data frame FR8 when the number of data frames FRm included in the command is 8 or more. The m-th bit (m is an integer of 0 to 6) of the first most significant frame SF1 corresponds to the most significant bit of the first (m + 1) data frame FR (m + 1). The data of the most significant bit in the set value counter is set to the 0th bit of the first most significant frame SF1, and the data of the most significant bit in the first special figure hold number counter 118 is set to the first bit of the first most significant frame SF1. The data of the most significant bit in the second special figure hold number counter 119 is set to the second bit of the first most significant frame SF1, and the data of the most significant bit in the mode data area is the first of the first most significant frame SF1. Set to 3 bits. Further, the data of the most significant bit in the round counter is set in the 4th bit of the 1st most significant frame SF1, and the data of the most significant bit in the pass / fail data area 158 is set in the 5th bit of the 1st most significant frame SF1. The data of the most significant bit in the distribution data area 162 is set to the sixth bit of the first most significant frame SF1.

The second most significant frame SF2 is a frame that makes it possible to grasp the data of the most significant bit changed to "0" among the data set in the eighth data frame FR8 to the tenth data frame FR10. The second highest frame SF2 is set between the last data frame (10th data frame FR10) and the footer FT when the number of data frames FRm included in the command is 8 or more. The (m-8) bit (m is an integer of 8 to 10) of the second most significant frame SF2 corresponds to the most significant bit of the mth data frame FRm. The most significant bit data in the game area is set to the 0th bit of the 2nd most significant frame SF2, and the most significant bit data in the lower area of the special electric timer counter is set to the 1st bit of the 2nd most significant frame SF2. The data of the most significant bit in the upper area of the special figure special electric timer counter is set to the second bit of the second most significant frame SF2.

As shown in FIG. 65, the header HD, the first data frame FR1 to the tenth data frame FR10, and the footer FT are set in the post-conversion normal return command. The header HD of the normal return command after conversion, the header HD of the normal return command for communication, the 1st to 10th data frames FR1 are used in the 0th to 6th bits of the 1st to 10th data frames FR1 to FR10 and the footer FT. ~ The data of the 0th to 6th bits of FR10 and the footer FT are set. Further, the data of the corresponding bit in the first most significant frame SF1 of the normal return command for communication is set in the most significant bit of the first to seventh data frames FR1 to FR7 of the converted normal return command. Furthermore, the data of the corresponding bit in the second most significant frame SF2 of the normal return command for communication is set in the most significant bit of the 8th to 10th data frames FR8 to FR10 of the post-conversion normal return command. ..

The normal return command for communication includes the most significant bits of the first most significant frame SF1 and the eighth to tenth data frames FR8 to FR10, which collect information on the most significant bits of the first to seventh data frames FR1 to FR7. The second most significant frame SF2 that collects information is set. As a result, while making it possible to distinguish between the header HD and the frame other than the header HD in the normal return command for communication, the data of the most significant bit in various counters in which the data is set in the normal return command for communication is stored in the sound light side CPU 93. It can be grasped at.

FIG. 66 is an explanatory diagram for explaining a mode of generating a normal return command for communication. As shown in FIG. 66, the data of the most significant bit of the set value counter is set to the 0th bit of the first save area 182, and the data of the most significant bit of the first special figure hold number counter 118 is set to the first save area 182. The data of the most significant bit of the second special figure hold number counter 119 is set to the second bit of the first save area 182, and the data of the most significant bit of the mode data area is set to the first bit of the first save area. It is set to the third bit of 182. Further, the data of the most significant bit of the round counter is set in the 4th bit of the 1st save area 182, and the data of the most significant bit of the pass / fail data area 158 is set in the 5th bit of the 1st save area 182, and the data is distributed. The data of the most significant bit in the data area 162 is set in the sixth bit of the first save area 182.

The data of the most significant bit in the game round area is set to the 0th bit of the second save area 183, and the data of the most significant bit in the lower area of the special figure special electric timer counter is set to the first bit of the second save area 183. The data of the most significant bit in the upper area of the special figure special electric timer counter is set to the second bit of the first save area 182. "0" is set in the third to sixth bits in which the corresponding counter does not exist in the second save area 183.

As described above, "0" is always set in the most significant bit (7th bit) of the first save area 182. Further, "0" is always set in the most significant bit (7th bit) of the second save area 183. The data stored in the first evacuation area 182 is the data of the first highest frame SF1, and the data stored in the second evacuation area 183 is the data of the second highest frame SF2. Since the most significant bit (7th bit) of these most significant frames SF1 and SF2 is always set to "0", the header HD and these most significant frames SF1 and SF2 are set in the sound light side receiving circuit 96. Can be made identifiable.

The main CPU 63 grasps the free area of the transmission standby buffer 175 based on the value of the write pointer 186. Then, in the grasped empty area, the header HD data, the set value counter, the first special figure hold number counter 118, the second special figure hold number counter 119, the mode data area, the round counter, the pass / fail data area 158, and the distribution data. The data stored in the area 162, the game round area, the lower area of the special figure special electric timer counter, the upper area of the special figure special electric timer counter, and the footer FT data are set. In the transmission standby buffer 175, the most significant bit (7th bit) in the area where data other than the header HD and the footer FT is set is cleared to "0". As a result, a normal return command for communication is set in the transmission standby buffer 175.

As described above, the main CPU 63 also transmits a communication command other than the communication variable command and the communication normal return command to the sound / light side CPU 93. The number of data frames FRm included in the command for communication is one of "1" to "12". When the number of data frame FRm included in the command for communication is a multiple of "7", the number of data frame FRm included in the command for communication is divided by "7". The highest frame SFp of the number of quotients is set in the command for the communication. If the number of data frame FRm included in the communication command is not a multiple of "7", the number of data frame FRm included in the communication command is divided by "7". The highest frame SFp in a number "1" larger than the number of quotients in the case is set in the command for the communication. As a result, the information set in the most significant bit in all the data frame FRm included in the communication command after receiving the communication command can be set in the most significant frame SFp.

Next, a case where the sound / light side receiving circuit 96 receives a command for communication (a variable command for communication and a normal return command for communication) will be described.

The communication command received by the sound light side receiving circuit 96 from the main side CPU 63 is stored in the standby buffer 178 after receiving. As shown in FIG. 61, the sound / optical side RAM 95 has a pre-conversion area 184 in which a command for communication is stored, and a post-conversion area for converting a command for communication stored in the pre-conversion area 184 into a post-conversion command. Area 185 is provided. The pre-conversion area 184 is a storage area consisting of 14 bytes, and the post-conversion area 185 is a storage area consisting of 12 bytes. As described above, the maximum data capacity of the communication command received by the sound light side receiving circuit 96 from the first transmitting circuit 101 is 14 bytes. The maximum data capacity of the converted command is 12 bytes. The sound and light side CPU 93 sets the communication command stored in the reception standby buffer 178 in the pre-conversion area 184, and converts the communication command into the post-conversion command in the post-conversion area 185. Then, the converted command is stored in the command storage buffer 179. As a result, the converted command can be used by the sound / light side CPU 93.

FIG. 67A is an explanatory diagram for explaining a conversion mode of a variable command for communication, and FIG. 67B is an explanatory diagram for explaining a conversion mode of a normal return command for communication. As shown in FIGS. 67A and 67B, the pre-conversion area 184 is provided with the first to 14th areas RA1 to RA14, and the converted area 185 is provided with the first to 12th areas RB1 to RB12. Is provided. These areas RA1 to RA14 and RB1 to RB12 are storage areas consisting of 1 byte.

In the sound and light side CPU 93, when the amount of data of the command stored in the post-reception standby buffer 178 is 2 bytes, that is, the command stored in the post-reception standby buffer 178 is composed only of the header HD and the footer FT. If so, the command is stored in the command storage buffer 179 without being converted. On the other hand, when the amount of data of the command stored in the post-reception standby buffer 178 is 3 bytes or more, that is, one or more data frames FRm for the command stored in the post-reception standby buffer 178. If is included, the command is converted into a converted command in the converted area 185.

As shown in FIG. 67 (a), in the conversion of the variable command for communication, the header HD included in the variable command for communication set in the pre-conversion area 184, the first and second data frames FR1 The data of the header HD excluding the first highest frame SF1 among the FR2, the first highest frame SF1 and the footer FT, the first and second data frames FR1 to FR2 and the footer FT are loaded into the converted area 185. The header HD stored in the first area RA1 of the pre-conversion area 184 is loaded into the first area RB1 of the post-conversion area 185, and is stored in the second to third areas RA2 to RA3 of the pre-conversion area 184. The 1st and 2nd data frames FR1 to FR2 are loaded into the 2nd to 3rd areas RB2 to RB3 of the converted area 185, and the footer FT stored in the 5th area RA5 of the pre-conversion area 184 is the converted area 185. It is loaded into the 4th area RB4.

After that, the information of "0" or "1" stored in the s bit (s is an integer of 0 to 1) of the first most significant frame SF1 included in the variable command for communication is the first (s + 1). ) Set to the most significant bit (7th bit) of the data frame FR (s + 1). As a result, the post-conversion variation command is stored in the post-conversion area 185. The sound light side CPU 93 stores the post-conversion variation command stored in the converted area 185 in the command storage buffer 179. As a result, the post-conversion variation command can be used by the sound / light side CPU 93.

As shown in FIG. 67 (b), in the conversion of the normal return command for communication, the header HD included in the normal return command for communication set in the pre-conversion area 184, the first to tenth data frames FR1 ~ FR10, 1st highest frame SF1, 2nd highest frame SF2, header HD excluding 1st highest frame SF1 and 2nd highest frame SF2 among footer FT, 1st to 10th data frames FR1 to FR10 and The footer FT data is loaded into the converted area 185. The header HD stored in the first area RA1 of the pre-conversion area 184 is loaded into the first area RB1 of the post-conversion area 185, and is stored in the second to eighth areas RA2 to RA8 of the pre-conversion area 184. The 1st to 7th data frames FR1 to FR7 are loaded into the 2nd to 8th areas RB2 to RB8 of the converted area 185, and are stored in the 10th to 12th areas RA10 to RA12 of the pre-conversion area 184. The tenth data frames FR8 to FR10 are loaded into the ninth to eleventh areas RB9 to RB11 of the converted area 185, and the footer FT stored in the 14th area RA14 of the unconverted area 184 is the twelfth of the converted area 185. Loaded in area RB12.

After that, the information of "0" or "1" stored in the s bit (s is an integer of 0 to 6) of the first most significant frame SF1 included in the normal return command for communication is the first (s + 1). ) The t-bit (t is 0 to 2) of the second most significant frame SF2 included in the normal return command for communication while being set to the most significant bit (7th bit) of the data frame FR (s + 1). The information of "0" or "1" stored in the integer) is set in the most significant bit (7th bit) of the (t + 8) th data frame FR (t + 8). As a result, the converted normal return command is stored in the converted area 185. The sound light side CPU 93 stores the post-conversion normal return command stored in the converted area 185 in the command storage buffer 179. As a result, the normal return command after conversion can be used by the sound and light side CPU 93.

As shown in FIG. 61, the sound light side RAM 95 is provided with a first top-level counter 188 and a second top-level counter 189. The first top-level counter 188 is a counter that enables the sound-light side CPU 93 to grasp the area Ran (n is an integer of any of 3 to 9) in which the first-level top frame SF1 is stored in the pre-conversion area 184. At the same time, the second top-level counter 189 grasps the area RAm (m is an integer of 11 to 13) in which the second top-level frame SF2 is stored in the pre-conversion area 184 by the sound / light side CPU 93. It is a counter that enables it. The first-level counter 188 and the second-level counter 189 are composed of 1 byte. In the pre-conversion area 184, the first highest frame SF1 is stored in any of the third area RA3 to the ninth area RA9. Numerical information of any one of "3" to "9" corresponding to the area RAn in which the first highest frame SF1 is stored in the pre-conversion area 184 is set in the first uppermost counter 188. In the pre-conversion area 184, the second highest frame SF2 is stored in any of the 11th area RA11 to the 13th area RA13. In the second top counter 189, any numerical information of "11" to "13" corresponding to the area RAm in which the second top frame SF2 is stored in the pre-conversion area 184 is set. When the command for communication stored in the pre-conversion area 184 is 10 bytes or less, that is, when the command for communication does not include the second highest frame SF2, the second highest frame SF2 is set to ". 0 ”is set. The sound light side CPU 93 can grasp the position of the first highest frame SF1 in the pre-conversion area 184 based on the value of the first highest counter 188. Further, the sound / light side CPU 93 grasps whether or not the second highest frame SF2 is included in the communication command stored in the pre-conversion area 184 based on the value of the second highest counter 189. At the same time, the position of the second highest frame SF2 in the pre-conversion area 184 can be grasped.

Next, the variable command transmission process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 68 (a). The change command transmission process is executed in step S1014 of the special figure change start process (FIG. 35). The variable command transmission process is executed by using the specific control program and the specific control data.

In the variable command transmission process, first, the first evacuation area 182 in the work area 121 for specific control is cleared to "0" (step S2001). After that, in step S2004 described later, the 0th bit is set as the destination bit to be the data transfer destination (step S2002). In the command transmission process for this variation (FIG. 68 (a)), the information of the destination bit is set in the W register 104a. In step S2002, the W register 104a is cleared to "0".

After that, "9430H", which is the start address of the variable command generation table 64u (FIG. 68 (b)) stored in the main ROM 64, is set in the HL register 107 (step S2003). The variable command generation table 64u is a data table that allows the main CPU 63 to grasp the data set in the variable command for communication.

FIG. 68B is an explanatory diagram for explaining the data structure of the variable command generation table 64u. As shown in FIG. 68 (b), the variable command generation table 64u is set to the addresses of "9430H" to "9435H" in the main ROM 64. The addresses of "9430H" and "9431H", which are the start addresses of the variable command generation table 64u, are set to the addresses of the lower areas of the display duration counter 142 in the work area 121 for specific control, and "9432H". And the address of the upper area of the display duration counter 142 is set as the address of "9433H". Further, "00H" is set as the end data at the address of "9434H", and command identification data of the variable command is set at the address of "9435H". As described above, "1" is set in the most significant bit (7th bit) of the command identification data of the variable command.

In the variable command transmission process (FIG. 68 (a)), the address of the movement source area is set in the HL register 107. The movement source area is an area that becomes a data movement source in step S2004 described later. By setting "9430H" in the HL register 107 in step S2003, the lower area of the display duration counter 142 is set as the movement source area.

After the processing of step S2003 is performed, the processing of steps S2004 to S2007 is performed in a state where the value of the W register 104a is "0", that is, in a state where the 0th bit is set as the movement destination bit. Specifically, first, the data of "0" or "1" stored in the most significant bit (7th bit) in the lower area of the display duration counter 142, which is the movement source area, is transferred to the first evacuation area 182. Load to the destination bit (step S2004). As described above, the 0th bit is set as the move destination bit in step S2002. Therefore, in step S2004, the data stored in the most significant bit in the lower area of the display duration counter 142 is loaded into the 0th bit of the first save area 182.

After that, the value of the HL register 107 is added by 2 to obtain "9432H" (step S2005). As described above, the address of the upper area of the display duration counter 142 is set in "9432H" and "9433H" of the variable command generation table 64u (FIG. 68 (b)). By updating the value of the HL register 107 to "9432H", the movement source area is updated to the upper area of the display duration counter 142.

After that, it is determined whether or not the end data (“00H”) is set in the area corresponding to the address stored in the HL register 107 (step S2006). As described above, the value of the HL register 107 is "9432H", and the end data is not set in the area corresponding to the "9432H". Therefore, in step S2006, a negative determination is made and the move destination bit is set to the first bit. Update to (step S2007). In step S2007, the value of the W register 104a is added by 1 to obtain "1".

After that, the processes of steps S2004 to S2006 are performed in a state where the value of the W register 104a is "1", that is, in a state where the first bit is set as the movement destination bit. Specifically, first, the data of "0" or "1" stored in the most significant bit (7th bit) in the upper area of the display duration counter 142, which is the movement source area, is transferred to the first evacuation area 182. Load to the destination bit (step S2004). As described above, the destination bit is updated to the first bit in step S2007. Therefore, the data stored in the most significant bit in the upper area of the display duration counter 142 is loaded into the first bit of the first save area 182.

After that, the value of the HL register 107 is added by 2 to obtain "9434H" (step S2005), and whether or not the end data ("00H") is set in the area corresponding to the address stored in the HL register 107. Is determined (step S2006). As described above, since the end data is set in "9434H" of the variable command generation table 64u (FIG. 68 (b)), an affirmative judgment is made in step S2006, and the variable command setting process is executed. Then (step S2008), the command transmission process for this variation is terminated.

Next, the variable command setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The variable command setting process is executed in step S2008 of the variable command transmission process (FIG. 68 (a)). The variable command setting process is executed by using the specific control program and the specific control data.

In the variable command setting process, the value of the write pointer 186 corresponding to the transmission standby buffer 175 is stored in the head storage area provided in the work area 121 for specific control (step S2101). The head storage area is a storage area that allows the main CPU 63 to grasp the head area of the area in which the command this time is set in the transmission standby buffer 175. The head storage area consists of 2 bytes. By storing the value of the write pointer 186 in step S2101, it is possible to grasp the area in which the current command is set in the transmission standby buffer 175 in step S2113 described later, and it is included in the command. It is possible to grasp the total number of "1" s.

After that, the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated from "9434H" to "9435H" (step S2102). As described above, the command identification data of the variable command is set in the area corresponding to "9435H" in the variable command generation table 64u (FIG. 68 (b)). After that, the command identification data is set in the area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2103). As described above, "1" is set as the header identification bit in the most significant bit (7th bit) of the command identification data. Thereby, the header HD and the frame other than the header HD can be distinguished by the sound light side receiving circuit 96.

After that, the setting destination area in the transmission standby buffer 175 is updated by adding 2 to the value of the write pointer 186 (step S2104). After that, “9430H”, which is the start address of the variable command generation table 64u (FIG. 68 (b)), is set in the HL register 107 (step S2105), and the process proceeds to step S2106. As described above, the addresses of the lower areas of the display duration counter 142 are stored in the “9430H” and “9431H” of the variable command generation table 64u.

The processes of steps S2106 to S2110 are repeated twice until an affirmative determination is made in step S2110. In the first step S2106 executed while the address of the lower area of the display duration counter 142 is stored in the HL register 107, the data stored in the lower area of the display duration counter 142 is stored in the transmission standby buffer. In 175, the setting destination area corresponding to the value of the write pointer 186 is set (step S2106), and the most significant bit (7th bit) of the setting destination area is cleared to "0" (step S2107).

After that, the setting destination area in the transmission standby buffer 175 is updated by adding 2 to the value of the write pointer 186 (step S2108). After that, the value of the HL register 107 is added by 2, and the address stored in the HL register 107 is updated to "9432H" (step S2109). As described above, in the variable command generation table 64u (FIG. 68 (b)), the addresses of the upper areas of the display duration counter 142 are stored in the addresses of "9432H" and "9433H".

After that, it is determined whether or not the end data (“00H”) is set in the area corresponding to the address stored in the HL register 107 in the variable command generation table 64u (step S2110). Since the upper 1 byte of the display duration data is set in the area and the end data is not set, a negative determination is made in step S2110, and the process proceeds to step S2106.

In the second step S2106 executed with the address of the upper area of the display duration counter 142 stored in the area corresponding to the value of the HL register 107, the data is stored in the upper area of the display duration counter 142. The existing data is set in the setting destination area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2106), and the most significant bit (7th bit) of the setting destination area is cleared to "0" (step S2107). ..

After that, the setting destination area in the transmission standby buffer 175 is updated by adding 2 to the value of the write pointer 186 (step S2108). After that, the value of the HL register 107 is added by 2, and the address stored in the HL register 107 is updated to "9434H" (step S2109). As described above, the end data (“00H”) is stored in the address “9434H” in the variable command generation table 64u (FIG. 68 (b)). After that, an affirmative determination is made in step S2110 for determining whether or not the end data is set in the area corresponding to the value of the HL register 107, and the process proceeds to step S2111.

In step S2111, the data stored in the first evacuation area 182 in the work area 121 for specific control is set in the setting destination area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2111). After that, the value of the write pointer 186 is added by 2 to update the setting destination area (step S2112), and the footer identification data stored in the main ROM 64 is set in the updated setting destination area (step S2113). , Ends the command setting process for this change. In step S2113, the footer FT is set next to the first highest frame SF1. Further, in step S2113, it is determined whether or not the total number of "1" among the data of "0" and "1" included in the communication variable command stored in the transmission standby buffer 175 is an even number. If the total number of "1" included in the variable command for communication is not an even number, the error detection bit of the footer FT is set to "1". The main CPU 63 sets a variable command for communication in the transmission standby buffer 175 based on the value of the first write pointer 186 stored in the head storage area in step S2101 and the value of the current write pointer 186. Understand the area you are in. On the other hand, when the total number of "1" included in the variable command for communication is an even number, the state in which "0" is set in the error detection bit of the footer FT is maintained. By setting the total number of "1" s included in the variable command for communication to an even number, it is possible to grasp the occurrence of a communication error in the sound / light side receiving circuit 96.

Next, the return command transmission process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The return command transmission process is executed in step S113 of the main process (FIG. 15). The return command transmission process is executed by using the program for specific control and the data for specific control.

In the return command transmission process, first, the first evacuation area 182 and the second evacuation area 183 in the work area 121 for specific control are cleared to "0" (step S2201). After that, in step S2207 described later, the 0th bit is set as the destination bit to be the data transfer destination (step S2202). In the command transmission process for this variation (FIG. 70), the information of the movement destination bit is set in the W register 104a. In step S2202, the W register 104a is cleared to "0".

After that, it is determined whether or not "1" is set in the partial clear flag in the work area 121 for specific control (step S2203). As described above, the partial clear flag is set to "1" in step S108 when the partial clear process (step S107) is executed in the main process (FIG. 15). When "1" is set in the partial clear flag (step S2203: YES), the return command transmission process at the time of partial clear is executed (step S2204), and the return command transmission process is terminated. In the return command transmission process (step S2204) at the time of partial clearing, the data of the header HD, the data stored in the set value counter in the work area 121 for specific control, and the data of the footer FT are partially cleared. The return command of is transmitted to the sound light side CPU 93. The header HD, the first data frame FR1, the first highest frame SF1 and the footer FT are set in the return command at the time of partial clearing for communication. The header HD contains the command identification data of the return command at the time of partial clearing. In the first data frame FR1, the data of the 0th to 6th bits of the set value counter in the work area 121 for specific control are set. In the 0th bit of the 1st most significant frame SF1, "0" which is the data of the most significant bit (7th bit) of the set value counter is set. By receiving the return command at the time of partial clearing, the sound light side CPU 93 grasps that the partial clearing process (step S107) has been executed in the main process (FIG. 15), and at the same time, the pachinko machine 10 at present. Grasp the set value.

When a negative determination is made in step S2203, "9450H", which is the start address of the normal return command generation table 64v (FIG. 71) stored in the main ROM 64, is set in the HL register 107 (step S2205). .. The normal return command generation table 64v is a data table that allows the main CPU 63 to grasp the data set in the normal return command for communication.

FIG. 71 is an explanatory diagram for explaining the data structure of the normal return command generation table 64v. As shown in FIG. 71, the normal return command generation table 64v is set to the addresses of "9450H" to "9466H" in the main ROM 64. The addresses of the set value counters in the work area 121 for specific control are set in the addresses of "9450H" and "9451H" which are the start addresses of the normal return command generation table 64v, and are the addresses of "9452H" and "9453H". Is set to the address of the first special figure hold number counter 118 in the work area 121 for specific control, and the addresses of "9454H" and "9455H" are set to hold the second special figure in the work area 121 for specific control. The address of the number counter 119 is set, and the address of the mode data area in the work area 121 for specific control is set in the addresses of "9456H" and "9457H", and the addresses of "9458H" and "9459H" are set. The address of the round counter in the work area 121 for specific control is set in, and the address of the pass / fail data area 158 in the work area 121 for specific control is set in the addresses of "945AH" and "945BH". , The addresses of the distribution data area 162 in the work area 121 for specific control are set as the addresses of "945CH" and "945DH". At the address of "945EH", "0001H" is stored as the first termination data. The addresses of "945FH" and "9460H" are set to the addresses of the game times area in the work area 121 for specific control, and the addresses of "9461H" and "9462H" are special features in the work area 121 for specific control. The address of the lower area of the special electric timer counter is set, and the address of the upper area of the special electric timer counter in the work area 121 for specific control is set as the address of "9463H" and "9464H". The address of "9465H" stores "0002H" as the second termination data, and the address of "9466H" stores the command identification data of the normal return command.

In the normal return command transmission process (FIG. 70), the address of the movement source area to which the data is moved is set in the HL register 107 in step S2207 described later. By setting "9450H" in the HL register 107 in step S2205, the set value counter is set as the movement source area.

After that, in step S2207 described later, the first evacuation area 182 is set as the movement destination area to be the data movement destination area (step S2206). In the return command transmission process (FIG. 70), the address of the destination area is stored in the DE register 106. In step S2206, the address of the first evacuation area 182 is stored in the DE register 106.

After that, the address of the first evacuation area 182 is stored in the DE register 106, that is, the first evacuation area 182 is set as the movement destination area, and the value of the W register 104a is "0". In a certain state, that is, in a state where the 0th bit is set as the movement destination bit, the processes of steps S2207 to S2211 are performed. Specifically, first, the data stored in the set value counter currently set as the movement source area to be grasped based on the address stored in the HL register 107 is stored in the first evacuation area which is the movement destination area. It is loaded into the 0th bit, which is the destination bit of 182 (step S2207).

After that, the value of the HL register 107 is added by 2 and updated to "9452H" (step S2208). As described above, the address of the first special figure hold number counter 118 is set in "9452H" and "9453H" of the normal return command generation table 64v (FIG. 71). By updating the value of the HL register 107 to "9452H", the first special figure hold number counter 118 is set as the movement source area.

After that, it is determined whether or not the second end data (“0002H”) is set in the movement source area grasped based on the address stored in the HL register 107 (step S2209). As described above, the value of the HL register 107 is "9452H", and since the second end data is not set in the area corresponding to the "9452H", a negative determination is made in step S2209, and the process proceeds to step S2210.

In step S2210, it is determined whether or not the first end data (“0001H”) is set in the movement source area (step S2211). As described above, the value of the HL register 107 is "9452H", and since the first end data is not set in the area corresponding to the "9452H", a negative determination is made in step S2210, and the process proceeds to step S2211.

In step S2211, the value of the W register 104a is added by 1 and updated to "1". As a result, the destination bit is updated to the first bit. Then, the process proceeds to step S2207. Then, the address of the first evacuation area 182 is stored in the DE register 106, that is, the first evacuation area 182 is set as the data movement destination area, and the value of the W register 104a is "1". , That is, in a state where the first bit is set as the movement destination bit, the processes of steps S2207 to S2211 are performed.

As described above, the processes of steps S2207 to S2211 are executed while the 0th bit of the first save area 182 is set as the data move destination and the set value counter is set as the move source area. By doing so, the data of the most significant bit (7th bit) in the set value counter is loaded into the 0th bit of the first save area 182. Further, the data movement destination is updated to the first bit of the first evacuation area 182, and the movement source area is updated to the first special figure hold number counter 118. The processes of steps S2207 to S2211 are repeated 7 times until an affirmative determination is made in step S2210. Each time the processing of steps S2207 to S2211 is executed, the movement source area is set value counter → 1st special figure hold number counter 118 → 2nd special figure hold number counter 119 → mode data area → round counter → pass / fail data area. The data is updated in the order of 158 → distribution data area 162, and the data movement destination is the 0th bit → the first bit → the second bit → the third bit → the fourth bit → the fifth bit in the first save area 182. It is updated in the order of the 6th bit. Thereby, the data of the most significant bit (7th bit) in these counters and areas can be set to the corresponding bits in the first save area 182. Specifically, the most significant bit of the set value counter is set to the 0th bit, the most significant bit of the first special figure hold number counter 118 is set to the first bit, and the most significant bit of the second special figure hold number counter 119 is set. The high-order bit is set to the second bit, the most significant bit of the mode data area is set to the third bit, the most significant bit of the round counter is set to the fourth bit, and the most significant bit of the pass / fail data area 158 is the fifth bit. It is set to the bit, and the most significant bit of the distribution data area 162 is set to the sixth bit.

When the process of step S2208 is performed while "945CH" is stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "945EH". As described above, the first end data (“0001H”) is set in the area corresponding to “945EH” in the normal return command generation table 64v (FIG. 71). Therefore, a negative determination is made in step S2209, an affirmative determination is made in step S2210, and the process proceeds to step S2212.

In step S2212, the destination area is updated to the second evacuation area 183 by setting the address of the second evacuation area 183 in the work area 121 for specific control in the DE register 106. After that, by clearing the value of the W register 104a to "0", the 0th bit is set as the move destination bit (step S2213). As a result, the 0th bit of the second save area 183 is set as the data movement destination.

After that, the value of the HL register 107 is added by 1 and updated to "945FH" (step S2214). As described above, the address of the gaming area is set in the area corresponding to "945FH" in the normal return command generation table 64v (FIG. 71), and the gaming area is set as the movement source area. Become. After that, the process proceeds to step S2207 in a state where the game round area is set as the movement source area and the 0th bit of the second evacuation area 183 is set as the data movement destination.

The processes of steps S2207 to S2211 are repeated three times until an affirmative determination is made in step S2209. Each time the processes of steps S2207 to S2211 are executed, the movement source area is the game round area → the lower area of the special figure special electric timer counter → the special figure special electric timer counter based on the normal return command generation table 64v (FIG. 71). The data is updated in the order of the upper area, and the data movement destination is updated in the order of the 0th bit → the first bit → the second bit in the second save area 183. Thereby, the data of the most significant bit (7th bit) in these counters and areas can be set to the corresponding bits in the second save area 183. Specifically, the most significant bit of the gaming area is set to the 0th bit, the most significant bit of the lower area of the special figure special electric timer counter is set to the first bit, and the most significant bit of the upper area of the special figure special electric timer counter is set. The high-order bit is set to the second bit.

When the process of step S2208 is performed while "9463H" is stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "9465H". As described above, the second end data (“0002H”) is set in the area corresponding to “9465H” in the normal return command generation table 64v (FIG. 71). Therefore, an affirmative determination is made in step S2209, and the process proceeds to step S2215. In step S2215, the normal return command setting process for setting the normal return command for communication in the transmission standby buffer 175 is executed, and the main return command transmission process is terminated.

Next, the normal return command setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 72. The normal return command setting process is executed in step S2215 of the normal return command transmission process (FIG. 70). The normal return command setting process is executed by using the program for specific control and the data for specific control.

In the normal return command setting process, first, the value of the write pointer 186 corresponding to the transmission standby buffer 175 is stored in the head storage area in the work area 121 for specific control (step S2301). As a result, in step S2317, which will be described later, the area in which the normal return command for communication is set in the transmission standby buffer 175 can be grasped by the main CPU 63.

After that, the value of the HL register 107 is added by 1 (step S2302). As described above, in step S2208 of the return command transmission process (FIG. 70), "9465H" is stored in the HL register 107. In step S2302, the address stored in the HL register 107 is updated to "9466H". As described above, the command identification data of the normal return command is set in the area corresponding to "9466H" in the normal return command generation table 64v (FIG. 71). After that, the command identification data is set in the setting destination area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2303). As described above, "1" is set as the header identification bit in the most significant bit (7th bit) of the command identification data. Thereby, the header HD and the frame other than the header HD can be distinguished by the sound light side receiving circuit 96.

After that, the setting destination area in the transmission standby buffer 175 is updated to the next area by adding 2 to the value of the write pointer 186 (step S2304). After that, "9450H" which is the start address of the normal return command generation table 64v (FIG. 71) is set in the HL register 107 (step S2305), and the process proceeds to step S2306. As described above, the addresses of the set value counters in the work area 121 for specific control are stored in the "9450H" and "9451H" of the normal return command generation table 64v. By setting "9450H" in the HL register 107, the set value counter is set as the movement source area.

The processes of steps S2306 to S2311 are repeated 7 times until an affirmative determination is made in step S2311. In the first step S2306 executed with the set value counter set as the move source area, the data stored in the set value counter which is the move source area is converted to the value of the write pointer 186 in the transmission standby buffer 175. It is set in the corresponding setting destination area (step S2306), and the most significant bit (7th bit) of the setting destination area is cleared to "0" (step S2307).

After that, the setting destination area in the transmission standby buffer 175 is updated to the next area by adding 2 to the value of the write pointer 186 (step S2308). After that, the value of the HL register 107 is added by 2, and the address stored in the HL register 107 is updated to "9452H" (step S2309). As described above, in the normal return command generation table 64v (FIG. 71), the addresses of the first special figure hold number counter 118 are stored in the addresses of "9452H" and "9453H". As a result, the first special figure hold number counter 118 is set as the movement source area.

After that, it is determined whether or not the second end data (specifically, "0002H") is set in the area corresponding to the address stored in the HL register 107 in the normal return command generation table 64v (step S2310). ). As described above, since the second end data is not set in "9452H", a negative determination is made in step S2310, and the process proceeds to step S2311. In step S2311, it is determined whether or not the first end data (specifically, "0001H") is set in the area corresponding to the address stored in the HL register 107 in the normal return command generation table 64v. As described above, since the first end data is not set in "9452H", a negative determination is made in step S2311 and the process proceeds to step S2306.

The processes of steps S2306 to S2311 are repeated 7 times until an affirmative determination is made in step S2311. In the first step S2306 executed with the set value counter set as the move source area, the data stored in the set value counter which is the move source area is converted to the value of the write pointer 186 in the transmission standby buffer 175. It is set in the corresponding setting destination area (step S2306), and the most significant bit (7th bit) of the setting destination area is cleared to "0" (step S2307).

As described above, when the processing of steps S2306 to S2311 is executed while the set value counter is set as the movement source area, the data stored in the set value counter is the setting destination area of the transmission standby buffer 175. At the same time, the most significant bit in the setting destination area is cleared to "0". Further, the movement source area is updated to the first special figure hold number counter 118, and the setting destination area in the transmission standby buffer 175 is updated to the next area. As described above, the processes of steps S2306 to S2311 are repeated 7 times until an affirmative determination is made in step S2311. Each time the processing of steps S2306 to S2311 is executed, the movement source area is set value counter → 1st special figure hold number counter 118 → 2nd special figure hold based on the normal return command generation table 64v (FIG. 71). The number counter 119 → mode data area → round counter → pass / fail data area 158 → distribution data area 162 are updated in this order, and the setting destination area in the transmission standby buffer 175 is updated in order. As a result, the data stored in the 0th to 6th bits of these counters and areas can be set in the transmission standby buffer 175.

When the process of step S2309 is performed while "945CH" is stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "945EH". As described above, the first end data (“0001H”) is set in the area corresponding to “945EH” in the normal return command generation table 64v (FIG. 71). Therefore, an affirmative determination is made in step S2311, and the process proceeds to step S2312.

In step S2312, the data stored in the first evacuation area 182 in the work area 121 for specific control is set in the area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2312). As a result, the first highest frame SF1 can be set next to the seventh data frame FR7.

After that, the value of the write pointer 186 is added by 1, and the setting destination area in the transmission standby buffer 175 is updated to the next area (step S2313). After that, the value of the HL register 107 is added by 1 and updated to "945FH" (step S2314). As described above, in the normal return command generation table 64v (FIG. 71), the address of the game round area in the work area 121 for specific control is stored in the address of "945FH". By updating the address stored in the HL register 107 to "945FH", the game round area is set as the movement source area. After that, the process proceeds to step S2306, and the processes of steps S2306 to S2311 are repeatedly executed until an affirmative determination is made in step S2310. The processes of steps S2306 to S2311 are executed three times.

By executing the processes of steps S2306 to S2311 while the game round area is set as the movement source area, the data stored in the game round area is set in the setting destination area of the transmission standby buffer 175. At the same time, the most significant bit in the setting destination area is cleared to "0". Further, the movement source area is updated to the lower area of the special figure special electric timer counter, and the setting destination area in the transmission standby buffer 175 is updated to the next area. Each time the processes of steps S2306 to S2311 are executed, the movement source area is the game round area → the lower area of the special figure special electric timer counter → the upper side of the special electric timer counter based on the normal return command generation table 64v (FIG. 71). The area is updated in the order of the area, and the setting destination area in the transmission standby buffer 175 is updated in the order. As a result, the data stored in the 0th to 6th bits of these counters and areas can be set in the transmission standby buffer 175.

When the process of step S2309 is performed while "9463H" is stored in the HL register 107, the value of the HL register 107 is incremented by 2 and updated to "9465H". As described above, the second end data (“0002H”) is set in the area corresponding to “9465H” in the normal return command generation table 64v (FIG. 71). Therefore, an affirmative determination is made in step S2310, and the process proceeds to step S2315.

In step S2315, the data stored in the second evacuation area 183 in the work area 121 for specific control is set in the area corresponding to the value of the write pointer 186 in the transmission standby buffer 175 (step S2315). As a result, the second highest frame SF2 can be set next to the tenth data frame FR10.

After that, the value of the write pointer 186 is added by 1, and the setting destination area in the transmission standby buffer 175 is updated to the next area (step S2316). After that, the footer identification data stored in the main ROM 64 is set in the setting destination area in the transmission standby buffer 175 (step S2317), and the normal return command setting process is terminated. In step S2317, the footer FT is set next to the second highest frame SF2. Further, in step S2317, it is determined whether or not the total number of "1" among the data of "0" and "1" included in the normal return command for communication stored in the transmission standby buffer 175 is an even number. If the determination is made and the total number of "1" included in the normal return command for communication is not an even number, "1" is set in the error detection bit of the footer FT. The main CPU 63 sets a normal return command for communication in the transmission standby buffer 175 based on the value of the first write pointer 186 stored in the head storage area in step S2301 and the value of the current write pointer 186. Understand the area you are in. On the other hand, when the total number of "1" included in the normal return command for communication is an even number, the state in which "0" is set in the error detection bit of the footer FT is maintained. By setting the total number of "1" s included in the normal return command for communication to an even number, it is possible to grasp the occurrence of a communication error in the sound / light side receiving circuit 96.

Next, the command reception correspondence process executed by the sound light side CPU 93 will be described with reference to the flowchart of FIG. 73. The command reception correspondence process is periodically executed in the sound light side CPU 93 at a cycle of 4 milliseconds.

In the command reception correspondence process, first, it is determined whether or not the header HD is stored in the post-reception standby buffer 178 in the sound light side reception circuit 96 (step S2401). In step S2401, it is determined whether or not there is an area in the wait buffer 178 after reception in which the most significant bit (7th bit) is set to "1", and the most significant bit is set to "1". An affirmative judgment is made when the existing area exists. If a negative determination is made in step S2401, the command reception correspondence process is terminated as it is.

If an affirmative determination is made in step S2401, it is determined whether or not the footer FT is stored in the wait buffer 178 after reception (step S2402). In step S2402, it is determined whether or not there is an area in which the footer identification data is set in the post-reception standby buffer 178, and if an area in which the footer identification data is set exists, an affirmative determination is performed. .. If a negative determination is made in step S2402, the command reception correspondence process is terminated as it is. If only the header HD is stored in the wait buffer 178 after reception and the footer FT is not stored (step S2401: YES, step S2402: NO), that is, if the command reception is not completed, step S2403 or later. Processing is not executed.

When an affirmative determination is made in step S2402, that is, when a command is stored in the wait buffer 178 after reception, there is a free area in the command storage buffer 179 in the sound light side RAM 95 where the command can be stored. Whether or not it is determined (step S2403). If there is a free area in the command storage buffer 179 that can store the command (step S2403: YES), whether or not the amount of data of the command stored in the wait buffer 178 after reception is 3 bytes or more. (Step S2404).

When the amount of data of the command stored in the post-reception buffer 178 is 3 bytes or more (step S2404: YES), that is, the command stored in the post-reception wait buffer 178 includes one or more data frames FRm. In the case of a command for communication, the pre-conversion area 184 and the post-conversion area 185 in the sound light side RAM 95 are cleared to "0" (step S2405), and the first highest counter 188 and the second highest counter in the sound light side RAM 95 are the second highest. Clear the upper counter 189 to "0" (step S2406). As described above, the first top-level counter 188 sets the area RAn (n is an integer of 3 to 9) in which the first top-level frame SF1 is stored in the pre-conversion area 184 on the sound light side CPU 93. The second top-level counter 189 is a counter that can be grasped, and the second top-level counter 189 emits light in the area RAm (m is an integer of 11 to 13) in which the second top-level frame SF2 is stored in the pre-conversion area 184. It is a counter that can be grasped by the side CPU 93.

After that, the communication command stored in the wait buffer 178 after reception is read out to the pre-conversion area 184 (step S2407). In step S2407, when the number of bytes of the command for communication stored in the wait buffer 178 after reception is "n + 3" (n is an integer of any of 1 to 7), the first area RA1 of the pre-conversion area 184 is RA1. Frames are set in the first (n + 3) area RA (n + 3) in the order of header HD → first data frame FR1 to nth data frame FRn → first highest frame SF1 → footer FT. Further, in step S2407, when the number of bytes of the communication command stored in the post-reception standby buffer 178 is "m + 4" (m is an integer of 8 to 10), the first of the pre-conversion area 184 is Area RA1 to 1st (m + 4) In area RA (m + 4), header HD → 1st to 7th data frames FR1 to FR7 → 1st highest frame SF1 → 8th data frame FR8 to mth data frame FRm → 2nd most Frames are set in the order of upper frame SF2 → footer FT. After that, the first command conversion process is executed (step S2408). In the first command conversion process, the communication command stored in the pre-conversion area 184 is converted into the post-conversion command in the post-conversion area 185. The details of the first command conversion process will be described later.

When a negative determination is made in step S2404, or when the process of step S2408 is executed, the write destination is grasped based on the value of the write pointer 187 of the command storage buffer 179 provided in the sound light side RAM 95 ( Step S2409), the command writing process is executed (step S2410). The write pointer 187 is a pointer that enables the sound / light side CPU 93 to grasp the write destination of the command in the command storage buffer 179. If the command is not stored in the post-conversion area 185, that is, if the command stored in the post-reception wait buffer 178 is a 2-byte command, in step S2410, the 2-byte stored in the post-reception wait buffer 178. Command is stored in the command storage buffer 179. Further, when the command is stored in the converted area 185, that is, when the command stored in the post-reception standby buffer 178 is a communication command, in step S2410, the conversion stored in the converted area 185 is performed. The post-command is stored in the command storage buffer 179.

After that, the write pointer 187 of the command storage buffer 179 is updated (step S2411). In step S2411, the value corresponding to the number of bytes of the command written in the command storage buffer 179 in step S2410 is added to the value of the write pointer 187, and the value of the write pointer 187 after the addition is the write pointer 187. When the maximum value is exceeded, the value obtained by subtracting "1" from the maximum value is subtracted from the value of the write pointer 187. As a result, the next write destination in the command storage buffer 179 can be grasped by the sound / light side CPU 93.

After that, the process of clearing the wait buffer 178 after reception is executed (step S2412). In the clear process, the area in which the command is stored in the wait buffer 178 after reception is cleared by "0". After that, it is determined in step S2412 whether or not the header HD is stored in the post-reception standby buffer 178 after the post-reception standby buffer 178 is cleared (step S2413), and the header HD is not stored. In (step S2413: NO), this command reception correspondence process is terminated as it is.

When an affirmative determination is made in step S2413, it is determined whether or not the footer FT is stored in the wait buffer 178 after reception (step S2414), and when the footer FT is not stored (step S2414: NO). Is the process for receiving this command. On the other hand, when the header HD and the footer FT are stored in the post-reception wait buffer 178 (step S2413: YES, step S2414: YES), that is, when other commands are stored in the post-reception wait buffer 178. Returning to step S2403, the processes of steps S2403 to S2414 are executed for the command.

Next, the first command conversion process executed by the sound light side CPU 93 will be described with reference to the flowchart of FIG. The first command conversion process is executed in step S2408 of the command reception correspondence process (FIG. 73).

In the first command conversion process, first, by grasping the area Ran (n is an integer of any of 4 to 14) in which the footer identification data is stored in the pre-conversion area 184, the area Ran in which the footer FT is stored is stored. (Step S2501). After that, based on the area RAn in which the footer FT grasped in step S2501 is stored, it is determined whether or not the number of bytes of the communication command stored in the pre-conversion area 184 is 11 bytes or more (). Step S2502). In step S2502, a negative determination is made when the footer FT is stored in any of the 4th to 10th areas RA4 to RA10, and the footer FT is stored in any of the 11th to 14th areas RA11 to RA14. If so, make an affirmative judgment.

When a negative determination is made in step S2502, that is, when only the first highest frame SF1 is set in the command for communication, the area RAn (n is) in which the footer FT is stored in the pre-conversion area 184. The value corresponding to the area RA (n-1) immediately before (an integer of 4 to 10) is set in the first highest counter 188 in the sound light side RAM 95 (step S2503). In step S2503, when the footer FT is set to the nth area RAn, "n-1" is set in the first highest counter 188. As a result, the position of the first highest frame SF1 in the pre-conversion area 184 can be grasped by the sound light side CPU 93. Further, in step S2503, the state in which the value of the second highest counter 189 is "0" is maintained. As a result, it is possible for the sound / optical side CPU 93 to grasp that the second highest frame SF2 is not included in the communication command stored in the pre-conversion area 184.

On the other hand, when an affirmative determination is made in step S2502, that is, when the first highest-level frame SF1 and the second highest-level frame SF2 are set in the communication command, the first highest level in the sound / light side RAM 95 is set. “9” is set in the counter 188 (step S2504). As a result, it is possible for the sound and light side CPU 93 to know that the first highest frame SF1 is stored in the ninth area RA9 of the pre-conversion area 184. After that, the value corresponding to the area RA (m-1) immediately before the area RAm (m is an integer of any of 11 to 14) in which the footer FT is stored in the pre-conversion area 184 is set in the sound / light side RAM 95. It is set in the second highest counter 189 (step S2505). In step S2505, when the footer FT is set to the m-th area RAm, "m-1" is set in the second highest counter 189. As a result, the position of the second highest frame SF2 in the pre-conversion area 184 can be grasped by the sound light side CPU 93.

When the processing of step S2503 is performed or the processing of step S2505 is performed, the value corresponding to the number of bytes of the command stored in the pre-conversion area 184 is set to the movement count counter provided in the sound / light side RAM 95. (Step S2506). The movement counter counts the number of times the information stored in the pre-conversion area 184 is loaded into the post-conversion area 185 in order to convert the communication command stored in the pre-conversion area 184 into the post-conversion command. It is a counter that can be grasped by the side CPU 93. In step S2506, the number of bytes of the communication command stored in the pre-conversion area 184 is grasped based on the position of the footer FT in the pre-conversion area 184 grasped in step S2501. After that, the first area RA1 of the pre-conversion area 184 is set as the information transfer source area in step S2509 described later (step S2507), and the first area RB1 of the converted area 185 is set as the information transfer destination area in step S2509 described later. Is set (step S2508).

After that, the data stored in the movement source area (first area RA1) is loaded into the movement destination area (first area RB1) (step S2509). After that, the value of the movement count counter is subtracted by 1 (step S2510), and it is determined whether or not the value after the 1 subtraction is "0" (step S2511). If a negative determination is made in step S2511, the movement source area is updated (step S2512). In step S2512, the movement source area is updated in the order of the first area RA1 → the second area RA2 → ... → the eighth area RA8 → the ninth area RA9 in the pre-conversion area 184. After that, the destination area is updated (step S2513). In step S2513, the destination area is updated in the order of the first area RB1 → the second area RB2 → ... → the eighth area RB8 → the ninth area RB9 in the converted area 185.

After that, it is determined whether or not the movement source area updated in step S2513 is the first highest frame SF1 or the second highest frame SF2 in the conversion area 184 (step S2514). In step S2514, the position of the first highest frame SF1 in the pre-conversion area 184 is grasped based on the value of the first highest counter 188 in the sound light side RAM 95. Further, the presence / absence of the second highest frame SF2 in the pre-conversion area 184 and the position of the second highest frame SF2 are grasped based on the value of the second highest counter 189 in the sound / light side RAM 95. Then, an affirmative determination is made when the movement source area updated in step S2513 is the first highest frame SF1 or when the movement source area is the second highest frame SF2.

If an affirmative determination is made in step S2514, the movement source area is updated to the area next to the first highest-level frame SF1 or the second highest-level frame SF2 in the pre-conversion area 184 (step S2515). In step S2515, when the movement source area is the first highest frame SF1 of the conversion area 184, the movement destination area is updated to the area next to the first highest frame SF1 and the movement destination area is before conversion. In the case of the second highest frame SF2 of the area 184, the movement source area is updated to the area next to the second highest frame SF2. After that, the value of the movement count counter is subtracted by 1 (step S2516).

If a negative determination is made in step S2514, or if the process of step S2516 is performed, the process returns to step S2509 and the processes of steps S2509 to S2516 are executed until an affirmative determination is made in step S2511. As a result, the header HD, the data frame FRm, the highest frame SF1 and SF2, and the footer FT data other than the highest frame SF1 and SF2 stored in the pre-conversion area 184 are converted into the corresponding areas of the post-conversion area 185. Can be loaded.

If an affirmative determination is made in step S2511, the second command conversion process is executed (step S2517), and the first command conversion process is terminated. In the second command conversion process in step S2517, the information stored in the most significant frames SF1 and SF2 of the pre-conversion area 184 is loaded into the most significant bit (7th bit) in the corresponding data frame FRm of the post-conversion area 185. .. FIG. 75 is a flowchart showing the second command conversion process.

In the second command conversion process, first, a value corresponding to the number of bytes of the command stored in the pre-conversion area 184 in the sound light side RAM 95 is set in the movement count counter in the sound light side RAM 95 (step S2601). In step S2601, the area RAn (n is an integer of any of 4 to 14) in which the footer FT is stored in the pre-conversion area 184 is grasped, and the value corresponding to the area RAn is set in the movement count counter.

After that, "2" is subtracted from the movement count counter (step S2602). As a result, the number of frames included in the communication command stored in the pre-conversion area 184, excluding the header HD and the footer FT, is set in the movement count counter.

After that, it is determined whether or not the value of the second highest counter 189 in the sound / light side RAM 95 is “0” (step S2603). As described above, when the communication command stored in the pre-conversion area 184 includes only the first highest-level frame SF1, the value of the second highest-level counter 189 in the sound light side RAM 95 is "0". Is. On the other hand, when the command for communication includes the first highest-level frame SF1 and the second highest-level frame SF2, the value of the second highest-level counter 189 is any of "11" to "13". When an affirmative determination is made in step S2603, that is, when only the first highest frame SF1 is included in the communication command stored in the pre-conversion area 184, the movement count counter in the sound / optical side RAM 95 The value of is subtracted by 1 (step S2604). On the other hand, when a negative determination is made in step S2604, that is, when the communication command stored in the pre-conversion area 184 includes the first highest-level frame SF1 and the second highest-level frame SF2, The value of the movement count counter in the sound / light side RAM 95 is subtracted by 2 (step S2605). By executing the process of step S2604 or step S2605, the data frame FRm excluding the header HD, the footer FT, and the uppermost frame SFp (p is 1 or 2) in the communication command stored in the pre-conversion area 184. The value corresponding to the number can be set in the movement count counter.

When the processing of step S2604 is performed or the processing of step S2605 is performed, the first highest-level frame SF1 is stored in the pre-conversion area 184 based on the value of the first highest-level counter 188 in the sound-light side RAM 95. The area Ran (n is an integer of any of 4 to 9) is grasped, and the area Ran is set as the information movement source area in step S2609 described later (step S2606). After that, the 0th bit of the first highest frame SF1 is set as the information transfer source bit in step S2609 described later (step S2607). After that, the second area RB2 of the converted area 185 is set as the information movement destination area in step S2609 described later (step S2608). As already described with reference to FIG. 67, the second area RB2 is an area in which the first data frame FR1 of the converted command is set.

After that, the information of "0" or "1" stored in the movement source bit in the movement source area is loaded into the most significant bit (7th bit) of the movement destination area (step S2609), and the movement count counter is decremented by 1. (Step S2610). After that, it is determined whether or not the value after the 1 subtraction is "0" (step S2611), and if the value of the movement count counter is not "0" (step S2611: NO), the movement source bit is set. Update (step S2612). In step S2612, the movement source bits are updated in the order of 0th bit → 1st bit → ... → 7th bit → 8th bit. After that, the destination area is updated (step S2613). In step S2613, the destination area is updated to the area next to the current destination area in the converted area 185.

After that, it is determined whether or not the movement source bit after updating in step S2612 is the eighth bit (step S2614). If the highest-level frame SFp (p is 1 or 2) included in the communication command stored in the pre-conversion area 184 is only the first highest-level frame SF1, an affirmative determination is made in step S2614. It is not performed, and an affirmative determination is made in step S2611 after the processes of steps S2609 to S2614 are repeated. On the other hand, when the communication command stored in the pre-conversion area 184 includes the first highest-order frame SF1 and the second highest-order frame SF2, after the processes of steps S2609 to S2614 are repeated. Since the movement source bit after the update in step S2612 becomes the eighth bit, an affirmative determination is made in step S2614.

When an affirmative determination is made in step S2614, the area RAm (m is) in which the second highest frame SF2 is stored in the pre-conversion area 184 based on the value of the second highest counter 189 in the sound / light side RAM 95. (An integer of 11 to 13) is grasped, and the area RAm is set as the information movement source area (step S2615). After that, the process returns to step S2609, and the processes of steps S2609 to S2615 are repeatedly executed until the value of the movement count counter becomes "0". As a result, the information stored in each bit of the most significant frame SFp (p is 1 or 2) in the pre-conversion area 184 is loaded into the most significant bit (7th bit) in the corresponding area of the post-conversion area 185. At the same time, the command before conversion can be stored in the converted area 185. When the value of the movement count counter becomes "0" (step S2611: YES), the second command conversion process is terminated.

According to the present embodiment described in detail above, the following excellent effects are obtained.

The IY register 109 stores "0000H", which is a reference address for specific control, at the start of the main process (FIG. 15), which is a process for specific control. As a result, when any of "0000H" to "00FFH" is specified in the first LDY instruction by the first LDY execution circuit 156, the data of the address specification is limited to the lower 1 byte in the 2-byte address information. Is possible. Therefore, the data capacity of the program can be reduced.

In the IY register 109, "0300H" is used as the non-specific control reference address used when the address of the work area 122 for non-specific control is specified in the management execution process (FIG. 57), which is the process for non-specific control. Is set. As a result, the non-specific control reference address can be used when the first LDY instruction and the second LDY instruction are executed in the non-specific control process.

When the management execution process (FIG. 57), which is a process for non-specific control, is completed, the IY register 109 is set to "0000H" as the reference address for specific control. As a result, the specific control reference address can be used when the first LDY instruction and the second LDY instruction are executed in the process for specific control.

The machine language data capacity of the first LDY instruction is 3 bytes in total. On the other hand, the data capacity of the machine language of the LD instruction is 4 bytes in total. Therefore, when "0000H" is stored in the IY register 109 and the address of the data table stored in the main ROM 64 is loaded into a pair register such as the BC register 105, the LD instruction is used instead. By using the first LDY instruction, the machine language of the instruction for loading the data of the "transfer source" to the "transfer destination" can be reduced by one byte. As a result, the data capacity of the program in the main ROM 64 can be reduced.

The storage area such as the counters that frequently appear in the program to execute the processing for specific control, such as the jackpot type counter C2 and the jackpot type maximum value counter CN2, is the LDY instruction (No. 1) in the work area 121 for characteristic control. While it is set in the address range (“0000H” to “00FFH”) that is the target of the 1LDY instruction and the 2nd LDY instruction), it appears in the program to execute the processing for specific control like a random number counter for fluctuation. The storage area such as a counter having a small number of times is set in the address range (“0100H” to “02FFH”) that is not the target of the LDY instruction (the first LDY instruction and the second LDY instruction) in the work area 121 for characteristic control. As a result, the data capacity of the program for executing the process for specific control is reduced.

The configuration is such that the address data (2 bytes) of the jackpot type maximum value counter CN2 is set in the BC register 105 by using the 1st LDY instruction that sets 1 byte of address data and specifies the address. A program for executing the maximum value setting start process (FIG. 24 (b)) in comparison with the configuration in which the address data is set in the BC register 105 by using the LD instruction for setting the address data and specifying the address. Data capacity can be reduced.

By using the first LDY instruction that sets 1-byte address data and specifies the address, the address data (2 bytes) of the jackpot type counter C2 is loaded into the HL register 107, so that the 2-byte address data can be stored. A program for executing the update start setting process (FIG. 27 (b)) in comparison with the configuration in which the address data of the jackpot type counter C2 is loaded into the HL register 107 by using the LD instruction for setting and specifying the address. Data capacity can be reduced.

The configuration is such that the address data (2 bytes) of the jackpot type maximum value counter CN2 is loaded into the BC register 105 by using the 1st LDY instruction that sets 1 byte of address data and specifies the address. Update start setting processing (FIG. 27 (b)) as compared with the configuration in which the address data of the jackpot type maximum value counter CN2 is loaded into the BC register 105 by using the LD instruction that sets the address data and specifies the address. It is possible to reduce the data capacity of the program for executing.

When the first LDY instruction is used, the address data included in the instruction code of the first LDY instruction can be only the lower 1 byte of the 2-byte address data. On the other hand, when the LD instruction is used, the address data included in the instruction code of the LD instruction needs to be the entire 2-byte address data. By using the first LDY instruction to set the address corresponding to the lower area of the first general winning counters 171a to 173a in the HL register 107, the address is set in the HL register 107 by using the LD instruction. The data capacity of the program can be reduced as compared with the configuration.

The upper 4 bits of the address corresponding to the area where the data table is stored in the main ROM 64 are common to "9H". In the main process (FIG. 15) executed at the start of supplying the operating power to the main CPU 63, the reference address "9000H" of the data table is stored in the TP register 111. As a result, when any of "9000H" to "94FFH" and "9903H" to "9BFFH" is specified in the LDT instruction by the LDT execution circuit 149, the data of the address specification is lower in the 2-byte address information. It is possible to use only 12 bits. Therefore, the data capacity of the program can be reduced. Further, the reference address of the data table stored in the TP register 111 can be used in the LDB instruction by the LDB execution circuit 157 and the LDB update instruction in the LDB update execution circuit 161.

The machine language data capacity of the LDT instruction is 2 bytes in total. On the other hand, the data capacity of the machine language of the LD instruction is 4 bytes in total. Therefore, when "9000H" is stored in the TP register 111 and the address of the data table stored in the main ROM 64 is loaded into a pair register such as the HL register 107, the LD instruction is used instead. By using the LDT instruction, the machine language of the instruction for loading the data of the "transfer source" to the "transfer destination" can be reduced by 2 bytes. As a result, the data capacity of the program in the main ROM 64 can be reduced.

By using the LDT instruction to set the start address of the first initialization table 64k in the HL register 107, the configuration is compared with the configuration in which the LD instruction is used to set the start address in the HL register 107. The data capacity of the program for executing the power-on setting process (FIG. 17 (c)) can be reduced.

By using the LDT instruction to set the start address of the random number maximum value table 64p in the HL register 107, the maximum is compared with the configuration in which the start address is set in the HL register 107 using the LD instruction. The data capacity of the program for executing the value setting start process (FIG. 24 (b)) can be reduced.

By using the LDT instruction that sets 12-bit numerical information and specifies the address, the start address of the second initialization table 64m is loaded into the HL register 107, so that 2-byte numerical information is set. Compared with the configuration in which the start address is loaded in the HL register 107 using the LD instruction that specifies the address, the data capacity of the program for executing the initialization process for fraud detection (FIG. 29 (b)) is reduced. can do.

In the power-on setting process (FIG. 17 (c)), the upper 1 byte of the address for specifying the storage area where "0" is cleared and the initial setting is performed is common to "00H". In the power-on setting process, the "00H" is set in the D register 106a, and the lower 1 byte of the address is read from the data table and set in the E register 106b, so that the entire address (2 bytes) is set in the DE register 106. ) Is stored. Then, the area for clearing "0" and initializing is specified by using the address information stored in the DE register 106. This makes it possible to reduce the data capacity of the data stored in the main ROM 64 for address designation.

By using the common high-order 1-byte data (“00H”) stored in the D register 106a in advance to specify the address of the fraudulent radio wave detection counter 133, it is stored in the first initialization table 64k. The address data to be used can be only the lower 1 byte in the address data (2 bytes) of the fraudulent radio wave detection counter 133. Therefore, the data capacity of the first initialization table 64k can be reduced as compared with the configuration in which the entire address data (2 bytes) in the fraudulent radio wave detection counter 133 is stored in the first initialization table 64k. Further, the first initialization table 64k is configured to specify the address of the fraudulent magnetism detection counter 134 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in can be only the lower 1 byte in the address data (2 bytes) of the fraudulent magnetism detection counter 134. Therefore, the data capacity of the first initialization table 64k can be reduced as compared with the configuration in which the entire address data (2 bytes) of the fraudulent magnetism detection counter 134 is stored in the first initialization table 64k. Furthermore, the first initialization table is configured to specify the address of the abnormal vibration detection counter 135 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in 64k can be only the lower 1 byte in the address data (2 bytes) of the abnormal vibration detection counter 135. Therefore, the data capacity of the first initialization table 64k can be reduced as compared with the configuration in which the entire address data (2 bytes) of the abnormal vibration detection counter 135 is stored in the first initialization table 64k.

The address data stored in the second initialization table 64m is stored in the second initialization table 64m by configuring the configuration in which the address of the power failure area 131 is specified by using the common upper 1 byte (“00H”) stored in the D register 106a in advance. Only the lower 1 byte in the address data (2 bytes) of the power failure area 131 can be used. Therefore, the data capacity of the second initialization table 64m can be reduced as compared with the configuration in which the entire address data (2 bytes) of the power failure area 131 is stored in the second initialization table 64m. Further, the second initial stage is configured by specifying the address of the lower area of the fraud monitoring timer counter 132 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in the conversion table 64m can be only the lower 1 byte in the address data (2 bytes) in the lower area of the fraud monitoring timer counter 132. Therefore, the data capacity of the second initialization table 64m can be reduced as compared with the configuration in which the entire address data (2 bytes) in the lower area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can. Furthermore, the second is configured by specifying the address of the upper area of the fraud monitoring timer counter 132 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in the initialization table 64m can be only the lower 1 byte in the address data (2 bytes) in the upper area of the fraud monitoring timer counter 132. Therefore, the data capacity of the second initialization table 64m can be reduced as compared with the configuration in which the entire address data (2 bytes) in the upper area of the fraud monitoring timer counter 132 is stored in the second initialization table 64m. can.

By using the LDT instruction to set the start address of the clear setting table 64n in the HL register 107, it is cleared as compared with the configuration in which the start address is set in the HL register 107 using the LD instruction. The data capacity of the program for executing the time setting process (FIG. 22 (b)) can be reduced.

The address stored in the clear setting table 64n is configured to specify the address of the security signal area 153 by using the common high-order 1-byte data (“00H”) stored in the D register 106a in advance. The data can be only the lower 1 byte in the address data (2 bytes) of the security signal area 153. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the security signal area 153 is stored in the clear setting table 64n. In addition, the clear setting table is configured to specify the address of the first special figure display counter 154 by using the common upper 1-byte data (“00H”) stored in the D register 106a in advance. The address data stored in 64n can be only the lower 1 byte in the address data (2 bytes) of the first special figure display counter 154. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the first special figure display counter 154 is stored in the clear setting table 64n. Furthermore, by using the common high-order 1-byte data (“00H”) stored in the D register 106a in advance to specify the address of the second special figure display counter 155, it is set at the time of clearing. The address data stored in the table 64n can be only the lower 1 byte in the address data (2 bytes) of the second special figure display counter 155. Therefore, the data capacity of the clear setting table 64n can be reduced as compared with the configuration in which the entire address data (2 bytes) of the second special figure display counter 155 is stored in the clear setting table 64n. ..

By using the LDB instruction, the process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111, and The process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data, the process of loading the data of the number of acquisition bits from the acquisition start bit of the acquisition start address to the "transfer destination" register, and the "transfer". It is possible to execute the process of masking the bits existing on the higher side of the loaded data among the "previous" registers with "0" with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB instruction to load the lower 12 bits of the start address acquired from the special electric address table 64q into the HL register 107, the data of the 3rd to 15th bits in the 2-byte acquisition data designation data. And the process of specifying the acquisition start address corresponding to the reference address of the data table set in the TP register 111, the process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data, and the special figure special electric train. The process of loading the lower 12 bits of the start address acquired from the address table 64q into the lower 12 bits of the HL register 107 and the process of masking the upper 4 bits of the HL register 107 with "0" are executed by one instruction. Can be done. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB instruction, the lower 12 bits of the start addresses SA0 to SA6 can be loaded into the HL register 107 from the special figure special electric address table 64q. Further, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SA0 to SA6 to the value of the HL register 107 after the execution of the LDB instruction, the entire start address SA0 to SA6 is added to the HL register 107. Can be obtained. Therefore, the address data set in the special figure special electric address table 64q can be limited to the lower 12 bits of the start addresses SA0 to SA6. As a result, the data capacity of the special figure special electric address table 64q in the main ROM 64 can be reduced as compared with the configuration in which the entire 2-byte start addresses SA0 to SA6 are set in the special figure special electric address table 64q.

By using the LDB instruction to load the lower 12 bits of the start address acquired from the fluctuation start table 64r into the HL register 107, the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and The process of specifying the acquisition start address corresponding to the reference address of the data table set in the TP register 111, the process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data, and the variable start table. The process of loading the lower 12 bits of the start address SBn acquired from 64r into the lower 12 bits of the HL register 107 and the process of masking the upper 4 bits of the HL register 107 with "0" are executed by one instruction. Can be done. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The configuration is such that the lower 4 bits of the hold display data HRn acquired from the hold display data table 64s using the LDB instruction are loaded into the lower 4 bits of the W register 104a, so that the third to 3rd in the acquired data designation data of 2 bytes are configured. The process of specifying the acquisition start address corresponding to the data of the 15th bit and the reference address of the data table set in the TP register 111, and the process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data. The process of loading the lower 4 bits of the hold display data HRn acquired from the hold display data table 64s into the lower 4 bits of the W register 104a, and the process of masking the upper 4 bits of the W register 104a with "0". Can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB instruction, a process of loading the lower 4 bits of the hold display data HRn into the lower 4 bits of the W register 104a and a process of masking the upper 4 bits of the W register 104a with "0" are combined. Since it can be executed by instructions, the configuration of the program for executing the hold display data acquisition execution process should be simplified compared to the configuration in which multiple instructions are set to execute these processes. At the same time, the data capacity in the main ROM 64 of the program can be reduced.

In the variation start table 64r, the lower 12 bits at the start addresses SB0 to SB23 of the variation pattern table corresponding to the variation type numbers 0 to 23 are set. The variation start table 64r is a data structure in which the lower 12 bits of the two start addresses SBn are set in the area corresponding to the three consecutive addresses. In the variable start table 64r, the lower 12 bits of the 24 start addresses SB0 to SB23 are set in a storage area of 36 bytes in total. On the other hand, assuming that the entire data (2 bytes) of one start address SBn (n is an integer of 0 to 23) is stored in the area corresponding to two consecutive addresses, 24 start addresses are used. A 48-byte storage area is required in the main ROM 64 in order to store the fluctuation start table 64r in which SB0 to SB23 are set. In this way, by adopting a data structure in which the lower 12 bits of the two start addresses SBn are set in the area corresponding to the three consecutive addresses, the data capacity of the variable start table 64r in the main ROM 64 is reduced. be able to.

By using the LDB instruction, the lower 12 bits of the start addresses SB0 to SB23 can be acquired from the fluctuation start table 64r. Further, after the LDB instruction is executed, the entire start addresses SB0 to SB23 can be acquired by adding "9000H" corresponding to the upper 4 bits common to the start addresses SB0 to SB23 to the lower 12 bits. can. Therefore, the address data set in the fluctuation start table 64r can be limited to the lower 12 bits of the start addresses SB0 to SB23. As a result, the data capacity of the variation start table 64r in the main ROM 64 can be reduced as compared with the configuration in which the entire 2-byte start addresses SB0 to SB23 are set in the variation start table 64r.

In the hold display data table 64s, the lower 4 bits of the five hold display data HR0 to HR4 are set in an area of a total of 3 bytes in the main ROM 64. On the other hand, if the entire 1-byte hold display data HR0 to HR4 is stored in the hold display data table 64s, a total area of 5 bytes is used to set the five hold display data HR0 to HR4. You will need it. As described above, since only the lower 4 bits of the five hold display data HR0 to HR4 have the data configuration set in the hold display data table 64s, the hold display data table 64s is stored in the main ROM 64. The data capacity of is reduced.

By using the LDB instruction, the lower 4 bits of the hold display data HRn are acquired from the hold display data table 64s to the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are masked with "0". The entire hold display data HRn can be acquired. Therefore, the hold display data HRn set in the hold display data table 64s can be set to only the lower 4 bits of the hold display data HRn. As a result, the data capacity of the hold display data table 64s in the main ROM 64 can be reduced as compared with the configuration in which the entire hold display data HRn of 1 byte is set in the hold display data table 64s.

One instruction is a process of loading data by using an LD update instruction and a process of adding 1 to the value of the HL register 107 after loading the data and updating the address stored in the HL register 107. Can be done with. Therefore, compared with the configuration in which the LD instruction for loading the data and the instruction for adding 1 to the value of the HL register 107 after loading the data are set, the data is loaded and the address is assigned after the data is loaded. The data capacity of the program for updating can be reduced.

By using the LD update instruction, the process of loading the data set in the second area of the first initialization table 64k into the E register 106b and the value of the HL register 107 being added by 1 to the HL register 107. The process of updating the stored address can be executed with a single instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

By using the LD update instruction, the process of loading the maximum value data selected as the setting target in the random number maximum value table 64p into the A register 104b and the value of the HL register 107 being added by 1 after loading the maximum value data. Then, the process of updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

By using the LDH update instruction, the data of the upper 4 bits and the data of the lower 4 bits in the 1-byte area of the main ROM 64 can be read into different general-purpose registers, and the data is read. The upper 4 bits in each general-purpose register can be masked with "0".

By using the LDH update instruction, the WA register 104 in which the upper 4 bits of data in the area corresponding to the address stored in the HL register 107 of the "transfer source" is set as the "transfer destination" Processing to load the lower 4 bits of one of the general-purpose registers (W register 104a) and mask the upper 4 bits of the general-purpose register with "0", and set the data of the upper 4 bits in the area to "transfer destination". A process of loading into the lower 4 bits of the other general-purpose register (A register 104b) of the WA registers 104 and masking the upper 4 bits of the general-purpose register with "0", and "transferring" after executing these processes. The process of adding "1" to the address stored in the "original" HL register 107 and updating the address can be executed with one instruction. Therefore, the configuration of the program can be simplified and the data capacity of the program can be reduced as compared with the configuration in which a plurality of instructions are set in the program in order to execute these three processes.

By using the LDH update instruction, the data set in the upper 4 bits of the first area in the 1st initialization table 64k is set in the lower 4 bits of the W register 104a, and the upper 4 bits of the W register 104a are set. The process of masking with "0" and the process of setting the data set in the lower 4 bits of the first area to the lower 4 bits of the A register 104b and masking the upper 4 bits of the A register 104b with "0". And the process of adding 1 to the value of the HL register 107 and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the data setting execution process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these three processes.

By using the LDB update command, the process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111. , The process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data, and the process of loading the data of the number of acquisition bits from the acquisition start bit of the acquisition start address to the lower bit in the "transfer destination" register. And, the process of masking the upper bits in the "transfer destination" register with "0" and the process of adding the number of acquired bits to the acquired data specified data after data transfer and updating can be executed with one instruction. .. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The determination value data DV1 acquired from the high accuracy table 64g using the LDB update instruction is set in the WA register 104 to update the acquired data designation data, so that the third byte of the acquisition data designation data is the third. ~ The process of specifying the acquisition start address corresponding to the data of the 15th bit and the reference address of the data table set in the TP register 111, and the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data are specified. Processing, processing to load the judgment value data DV1 acquired from the high accuracy / rejection table 64g into the lower 6 bits of the WA register 104, processing to mask the upper 10 bits of the WA register 104 with "0", and specification of acquired data. The process of adding the number of acquired bits to the data and updating it can be executed with a single instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

By setting the flag data FD1 acquired from the high accuracy table 64g using the LDB update command in the B register 105a and updating the acquired data designation data, the third to third in the acquisition data designation data of 2 bytes. The process of specifying the acquisition start address corresponding to the data of the 15th bit and the reference address of the data table set in the TP register 111, and the process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition specified data. And, the process of loading the flag data FD1 acquired from the high accuracy table 64g into the lower 2 bits of the B register 105a, the process of masking the upper 6 bits of the B register 105a with "0", and the acquisition data designation data. The process of adding and updating the number of acquired bits can be executed with a single instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The configuration is such that the first pre-addition distribution value FVA1 acquired from the distribution table 64h for the first special figure is loaded into the W register 104a by using the LDB update command and the acquired data designation data is updated, so that 2 bytes are used. Corresponds to the process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the acquisition data designation data and the reference address of the data table set in the TP register 111, and the lower 3 bits of the acquisition designation data. The process of specifying the acquisition start bit to be performed, the process of loading the first pre-addition distribution value FVA1 acquired from the distribution table 64h for the first special figure into the lower 5 bits of the W register 104a, and the process of loading the W register 104a. It is possible to execute a process of masking the upper 3 bits with "0" and a process of adding the number of acquired bits to the acquired data specified data and updating the data with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB update command to load the first flag data FDA1 acquired from the distribution table 64h for the first special figure into the B register 105a and updating the acquired data designation data, 2-byte acquisition data is obtained. The process of specifying the acquisition start address corresponding to the data of the 3rd to 15th bits in the designated data and the reference address of the data table set in the TP register 111, and the acquisition start corresponding to the lower 3 bits of the acquisition designated data. The process of specifying the bit th, the process of loading the first flag data FD1 acquired from the first special figure distribution table 64h into the lower 3 bits of the B register 105a, and the process of loading the upper 5 bits of the B register 105a into "0". The process of masking with "" and the process of adding the number of acquired bits to the acquired data specified data and updating it can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

Using the program of the data setting execution process (FIG. 19 (c)) also used in the power-on setting process (FIG. 17 (c)) and the data of the second initialization table 64 m, the fraudulent radio wave detection counter 133 and the fraudulent magnetism By configuring the detection counter 134 and the abnormal vibration detection counter 135 to be initialized, a dedicated program for initializing these detection counters 133 to 135 in the fraud detection initialization process (FIG. 29 (b)) and a dedicated program. Compared with the configuration for storing data, the data capacity of the program and data in the main ROM 64 can be reduced.

In the second special figure hold display data acquisition process (FIG. 55 (c)), the subroutine program and the hold display data table 64s common to the first special figure hold display data acquisition process (FIG. 55 (a)) are used. The hold display data HRn corresponding to the value of the second special figure hold number counter 119 is acquired. Therefore, it is possible to reduce the data capacity of the program and data for acquiring the hold display data HRn.

In the normal figure hold display data acquisition process (FIG. 55 (d)), the first special figure hold display data acquisition process (FIG. 55 (a)) and the second special figure hold display data acquisition process (FIG. 55 (c)) The hold display data HRn corresponding to the value of the normal figure hold number counter 127 is acquired by using the program of the common subroutine and the hold display data table 64s. Therefore, it is possible to reduce the data capacity of the program and data for acquiring the hold display data HRn.

In the first special figure distribution process, by uniformly adding "20" to the pre-addition distribution value FVAn set in the first special figure distribution table 64h, the first distribution value is used. A certain "40", a second distribution value "40", and a third distribution value "20" are calculated. The data structure is such that the first to third pre-addition distribution values FVA1 to FVA3 obtained by subtracting "20" from the first to third distribution values are set in the distribution table 64h for the first special figure. Compared with the data configuration in which the first to third distribution values are set, the data capacity of the distribution table 64h for the first special figure in the main ROM 64 can be reduced.

In the second special figure distribution process, "20" is uniformly added to the pre-addition distribution value FVBn set in the second special figure distribution table 64j, so that the first distribution value is used. A certain "30", a second distribution value "50", and a third distribution value "20" are calculated. The data structure is such that the first to third pre-addition distribution values FVB1 to FVB3 obtained by subtracting "20" from the first to third distribution values are set in the distribution table 64j for the second special figure. Compared with the data configuration in which the first to third distribution values are set, the data capacity of the second special figure distribution table 64j in the main ROM 64 can be reduced.

In the LDB instruction and the LDB update instruction, the reference address (“9000H”) of the data table stored in the TP register 111 with respect to the data obtained by dividing the 16-bit acquisition data designation data by “8” (“1000B”). The acquisition start address is calculated by performing the operation of adding "). "8" used to calculate the acquisition start address is a numerical range represented by "3" bits, which is the number of bits of the data for designating the acquisition start bit among the acquisition data designation data ("0" to "". It is a value obtained by adding "1" to "7", which is the maximum value of "7"), and is the cube of "2". By dividing the acquired data designated data by the "8" ("1000B"), the information of "0" or "1" set in the 3rd to 15th bits of the acquired data designated data is 3 bits lower. It can be shifted to the side and set to the lower 13 bits (13th to 12th bits) in the quotient data after division, and the upper 3 bits (13th to 15th bits) in the quotient data after the division can be set to ". 0 "can be set. As a result, only the data for specifying the acquisition start address is selected from the 16-bit acquisition data specification data in which the data for specifying the acquisition start address and the data for specifying the acquisition start bit are aggregated and set. It can be taken out and made available.

In the LDB instruction and the LDB update instruction, the lower 3 bits of the acquired data specified data are extracted by calculating the logical product of the lower 1 byte of the acquired data specified data and "000000111B". The data of the lower 3 bits is data for specifying the acquisition start bit. By calculating the logical product of the lower 1 byte of the acquired data specified data and "00000011B", the data for specifying the acquisition start address and the data for specifying the acquisition start bit are aggregated and set. Only the data for specifying the acquisition start bit from the 16-bit acquisition data designation data can be extracted and made available.

The data for specifying the acquisition start address and the data for specifying the acquisition start bit are collectively set in the acquisition data designation data consisting of 2 bytes. As a result, the data capacity of the acquired data designated data is reduced, and the data capacity of the machine language of the LDB instruction and the LDB update instruction is reduced.

A header identification bit that enables identification of the header HD is set in the header HD. The header identification bit is the most significant bit (7th bit) of the header HD. "1" is set in the header identification bit. Of the 1-byte data included in the command, the data in which "1" is set in the most significant bit is only the header HD. Therefore, the sound / light side receiving circuit 96 determines whether or not "1" is set in the most significant bit of the 1-byte data stored in the reception buffer 177, so that the 1-byte data is used as a header. It is possible to grasp whether or not it is HD. As a result, it is possible to grasp the demarcation position between a plurality of commands received from the first transmission circuit 101 in the sound light side reception circuit 96.

The communication command (variation command for communication and normal return command for communication) includes a header HD and a footer FT. The sound and light side CPU 93 can grasp the start position of the command for communication by using the header HD, and can grasp the end position of the command for communication by using the footer FT.

The sound light side receiving circuit 96 receives the footer FT from the first transmission circuit 101 when the 1-byte data received next to the footer FT is data other than the header HD, and does not receive the footer FT after receiving the header HD. It is understood that a communication error has occurred even when the next header HD is received. As a result, it is possible to prevent data different from the command set in the transmission standby buffer 175 by the main CPU 63 from being used by the sound and light side CPU 93.

When transmitting a command including 1 or more data frame FRm (m is an integer of 1 or more), the main CPU 63 generates a converted command in which the most significant bit of each data frame FRm is changed to "0". In the post-conversion command, the most significant frame SFp (p is 1 or 2) that collects the information of the most significant bit of each data frame FRm is set. As a result, the header HD and the data other than the header HD can be identified by the sound light side receiving circuit 96 while the information of the most significant bit of each data frame FRm can be grasped.

The sound and light side CPU 93 sets the communication command (communication variable command and communication normal return command) stored in the standby buffer 178 after reception in the pre-conversion area 184, and sets the communication command in the pre-conversion area 184. Converted to a command after conversion in the converted area 185. Then, the converted command is stored in the command storage buffer 179. As a result, the converted command can be used by the sound / light side CPU 93.

The sound-light side CPU 93 grasps the number and position of the highest frame SFp (p is 1 or 2) in the command for communication based on the number of bytes of the command for communication received. Therefore, it is not necessary to set the information indicating the position of the highest frame SFp in the communication command. As a result, it is possible to prevent the data capacity of the communication command from increasing, and it is possible to reduce the processing load for generating the communication command. In addition, the data capacity of the program for generating commands for communication can be reduced.

The sound light side CPU 93 identifies the data frame FRm corresponding to the bit based on the position of the bit in the highest frame SFp. Therefore, it is not necessary to set the information indicating the correspondence between each bit of the highest frame SFp and the data frame FRm in the command for communication. As a result, it is possible to prevent the data capacity of the communication command from increasing, and it is possible to reduce the processing load for generating the communication command. In addition, the data capacity of the program for generating commands for communication can be reduced.

The number of data frames FRm included in the communication command transmitted from the main CPU 63 to the sound light side CPU 93 is any one of "1" to "12". When the number of data frame FRm included in the command for communication is a multiple of "7", the number of data frame FRm included in the command for communication is divided by "7". The highest frame SFp of the number of quotients is set in the command for the communication. If the number of data frame FRm included in the communication command is not a multiple of "7", the number of data frame FRm included in the communication command is divided by "7". The highest frame SFp in a number "1" larger than the number of quotients in the case is set in the command for the communication. As a result, the information set in the most significant bit in all the data frame FRm included in the communication command after receiving the communication command can be set in the most significant frame SFp.

<Second embodiment>
This embodiment is different from the first embodiment in that the process of setting the maximum value of the numerical information to be updated is executed in the hard random number circuit provided on the main control board 61. Hereinafter, a configuration different from that of the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 76 is an explanatory diagram for explaining the configuration of the main control board 61 in the present embodiment. As shown in FIG. 76, the main control board 61 has a jackpot type update circuit 191 for updating numerical information used for determining a jackpot type, and a reach generation lottery when the symbol display device 41 is disengaged and fluctuates. The numerical information used for the reach random number update circuit 192, which updates the numerical information used for the operation, and the lottery for whether or not to open the electric service 34a of the second operating port 34 is updated. A normal electric random number update circuit 193 is provided. These update circuits 191 to 193 are hard random number circuits.

The lottery counter area 112 (FIG. 11) in the work area 121 for specific control is provided with a hit random number counter C1, a random number initial value counter C4, and a variation type counter C5 already described in the first embodiment. .. Similar to the first embodiment, the numerical information updated by the hit random number counter C1 is used for the lottery for the occurrence of a hit, and the numerical information updated by the random number initial value counter C4 is the hit random number counter C1. Used for initial value setting. Further, the numerical information updated by the variation type counter C5 is used to determine the display duration in each of the special figure display units 37a and 37b and the symbol display device 41.

The numerical information updated by the jackpot type update circuit 191, the numerical information updated by the reach random number update circuit 192, and the numerical information updated by the general electric random number update circuit 193 are the numerical information updated in these update circuits 191 to 193. 1 is added to the previous value each time it is updated, and it returns to 0 after reaching the maximum value. Numerical information is updated at short intervals in each update circuit 191 to 193. Each numerical information of the jackpot type update circuit 191 and the reach random number update circuit 192 is stored in the special figure holding area 113 when a prize is generated in the first operation port 33 or the second operation port 34. Further, similarly to the first embodiment, when a prize is generated in the first operating port 33 or the second operating port 34, the numerical information of the winning random number counter C1 is also stored in the special figure holding area 113. .. The numerical information updated by the normal number random number update circuit 193 is stored in the normal figure holding area 114 when a prize is won in the through gate 35.

As shown in FIG. 76, the jackpot type update circuit 191 is provided with a jackpot type maximum value counter 191a in which the maximum value of the numerical information updated by the jackpot type update circuit 191 is set, and the reach random number is updated. The circuit 192 is provided with a reach random number maximum value counter 192a in which the maximum value of the numerical information updated by the reach random number update circuit 192 is set, and the normal electric random number update circuit 193 is provided with a general electric random number update. A general random number maximum value counter 193a for setting the maximum value of the numerical information updated by the circuit 193 is provided.

FIG. 77A is an explanatory diagram for explaining the maximum value of the update circuits 191 to 193. The maximum value is set in the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a, and the general electric random number maximum value counter 193a when the power is turned on. As shown in FIG. 77 (a), "99" is set in the jackpot type maximum value counter 191a, "238" is set in the reach random number maximum value counter 192a, and "238" is set in the general random number maximum value counter 193a. 250 "is set.

The address of "1111H" is set in the jackpot type maximum value counter 191a, the address of "1112H" is set in the reach random number maximum value counter 192a, and "1113H" is set in the general random number maximum value counter 193a. Address is set. By designating these addresses, the main CPU 63 can set the maximum value in the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a, and the general electric random number maximum value counter 193a.

The main ROM 64 stores a hard random number maximum value table 64w used for setting the maximum values of the jackpot type update circuit 191 and the reach random number update circuit 192 and the general electric random number update circuit 193. FIG. 77B is an explanatory diagram for explaining the data structure of the hard random number maximum value table 64w.

As shown in FIG. 77 (b), the hard random number maximum value table 64w is set in the address range of "9420H" to "9426H" in the main ROM 64. The hard random number maximum value table 64w has a data structure in which the first area and the second area are alternately repeated. The first area is a lower 1-byte area in the address of the update circuit 191 to 193 or a 1-byte area in which the end data is set, and the second area is the update circuit 191 to 193 corresponding to the address of the immediately preceding first area. This is a 1-byte area in which the maximum value data of is set.

As shown in FIG. 77 (a), the upper 1 byte at each address of the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a, and the general electric random number maximum value counter 193a is common to "11H". In the present embodiment, the main CPU 63 stores "1100H" in advance in the IY register 109 as the upper 1-byte data of these maximum value counters 191a to 193a, and sets the maximum value of the update circuits 191 to 193. The main CPU 63 reads the lower 1 byte at the address of each maximum value counter 191a to 193a from the main side ROM 64, and adds the data for the upper 1 byte and the data of the lower 1 byte to the maximum value counters 191a to 193a. Identify the address.

As shown in FIG. 77 (b), in the hard random number maximum value table 64w, "11H", which is the lower 1 byte of the address of the jackpot type maximum value counter 191a, is set in the first area corresponding to 9420H. In the second area corresponding to the "9421H" following the "9420H", the maximum value data "63H" ("99") set in the jackpot type maximum value counter 191a is set. In the first area corresponding to "9422H" following "9421H", "12H" which is the lower 1 byte of the address of the reach random number maximum value counter 192a is set, and "9423H" following the "9422H" is set. In the corresponding second area, "EEH" ("238"), which is the maximum value data set in the reach random number maximum value counter 192a, is set. In the first area corresponding to "9424H" following "9423H", "13H" which is the lower 1 byte of the address of the normal random number maximum value counter 193a is set, and "9425H" following the "9424H" is set. In the second area corresponding to, "FAH" ("250"), which is the maximum value data set in the general electric random number maximum value counter 193a, is set. The end data "00H" is set in the first area corresponding to "9426H" following "9425H".

The data set in the hard random number maximum value table 64w to specify the addresses of the maximum value counters 191a to 193a is only the lower 1 byte of the address. Therefore, in the hard random number maximum value table 64w, the data capacity (1 byte) of the data for specifying the address of the maximum value counters 191a to 193a and the data of the maximum value data set in the maximum value counters 191a to 193a. The capacity (1 byte) can be the same as the data capacity. As a result, the data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 78 (a). The random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed by using the program for specific control and the data for specific control.

In the random number maximum value setting process, the update circuit setting process is first executed (step S2701). In the update circuit setting process, the maximum value "99" of the jackpot type update circuit 191 is set in the jackpot type maximum value counter 191a, and the maximum value "238" of the reach random number update circuit 192 is set to the reach random number maximum value counter 192a. Is set to, and "250", which is the maximum value of the Fuden random number update circuit 193, is set in the Fuden random number maximum value counter 193a. The details of the update circuit setting process will be described later.

After executing the update circuit setting process in step S2701, the maximum value setting process of the hit random number counter C1 is executed (step S2702). In the maximum value setting process, "7999", which is the maximum value of the hit random number counter C1, is set in the hit maximum value counter CN1. After that, the maximum value setting process of the random number initial value counter C4 is executed (step S2703). In the maximum value setting process, "7999", which is the maximum value of the random number initial value counter C4, is set in the initial value maximum value counter CN4. After that, the maximum value setting process of the variation type counter C5 is executed (step S2704), and the random number maximum value setting process is completed. In the maximum value setting process of the variable type counter C5, the maximum value “250” of the variable type counter C5 is set in the variable type maximum value counter CN5.

Next, the program contents of the update circuit setting process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 78 (b). The update circuit setting process is executed in step S2701 of the random number maximum value setting process (FIG. 78 (a)). As shown in FIG. 78 (b), "2501" to "2504" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The command "LDT HL, 420H" is set in the line number of "2501". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "420H" sets 12-bit numerical information of "420H" as a transfer source. The content. As already described in the first embodiment, the TP register 111 is set to "9000H" as the reference address of the data table in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 420H", "9420H" obtained by adding "9000H" set in the TP register 111 to "420H" set as the "transfer source" is added to "9420H". Is set in the HL register 107. “9420H” is the start address of the hard random number maximum value table 64w (FIG. 77 (b)) in the main ROM 64.

In this way, the start address of the hard random number maximum value table 64w is loaded into the HL register 107 by using the LDT instruction that sets the 12-bit numerical information and specifies the address, so that the 2-byte numerical information is used. The data capacity of the program for executing the random number update circuit setting process in comparison with the configuration in which the start address of the hard random number maximum value table 64w is loaded into the HL register 107 using the LD instruction that sets and specifies the address. Can be reduced.

The command "LD IY, 1100H" is set in the line number of "2502". "LD" is an LD instruction, "IY" is a content that specifies the IY register 109 as a transfer destination, and "1100H" is a higher-order common to the addresses of the random number update circuits 191 to 193 as the "transfer source". This is the content for setting 1-byte data. By executing "LD IY, 1100H", "1100H" set as the "transfer source" is loaded into the IY register 109. As a result, the data for the upper 1 byte can be stored in the IY register 109.

An instruction "CALLS HRSDSET" is set in the line number of "2503". “HRSDSET” is a maximum value setting execution process (FIG. 78 (c)) described later. The instruction "CALLS HRSDSET" is an instruction for calling a subroutine called the maximum value setting execution process. The details will be described later, but by executing the maximum value setting execution process at the line number "2503", the maximum value data is stored in the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a, and the general random number maximum value counter 193a. Is set. The details of the maximum value setting execution process will be described later.

When the subroutine of the maximum value setting execution process is completed, the process proceeds to the line number of "2504". An instruction "RET" is set in the line number of "2504". As described above, the update circuit setting process is a subroutine executed in step S2701 of the random number maximum value setting process (FIG. 78 (a)). Therefore, by executing the instruction "RET", the process proceeds to step S2702 of the random number maximum value setting process (FIG. 78 (a)).

FIG. 78 (c) is an explanatory diagram for explaining the program contents of the maximum value setting execution process executed by the main CPU 63. The maximum value setting execution process is executed at the line number “2503” of the update circuit setting process (FIG. 78 (b)). As shown in FIG. 78 (c), a special LD instruction "LD (IY + A), W" is set in the line number "2605" of the maximum value setting execution process.

Prior to the description of the maximum value setting execution process (FIG. 78 (c)), the special LD instruction included in the maximum value setting execution process will be described. As shown in FIG. 76, the main control board 61 is provided with a special LD execution circuit 194 as a dedicated circuit for executing a special LD instruction.

The instruction code of the special LD instruction has a configuration of "LD (index register + general-purpose register), transfer source" such as "LD (IY + A), W". In the special LD instruction, the IY register 109 is set as the "index register" and the A register 104b is set as the "general purpose register". Further, in the special LD instruction, the W register 104a in which 1 byte of data is stored is set as the “transfer source”. In the special LD instruction, the IX register 108 or the TP register 111 may be set as the "index register", and the W register 104a, the B register 105a, the C register 105b, the D register 106a, and the E register may be set as the "general purpose register". The 106b, the H register 107a, or the L register 107b may be set, and the A register 104b, the B register 105a, and the C register 105b, in which 1 byte of data or the 1-byte data is stored as the "transfer source", may be used. The D register 106a, the E register 106b, the H register 107a, or the L register 107b may be set.

In the special LD instruction, the "index register + general-purpose register" is the sum of the 2-byte data stored in the index register (IY register 109) and the 1-byte data stored in the general-purpose register (A register 104b). The addition operation result) and "(index register + general-purpose register)" mean 1-byte data stored in the area corresponding to the sum address. When the special LD instruction is executed, the 1-byte data stored in the W register 104a set as the "transfer source" is loaded into the area corresponding to the operation result address of the "index register + general-purpose register". Will be done.

In this way, by using the special LD instruction, the process of calculating the sum of the data stored in the IY register 109 and the data stored in the A register 104b to calculate the forwarding address, and " The process of loading 1-byte data stored in the W register 104a of the "transfer source" to the transfer destination can be executed by one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

Next, the program contents of the maximum value setting execution process executed by the main CPU 63 will be described with reference to FIG. 78 (c). As described above, the maximum value setting execution process is executed at the line number “2503” of the update circuit setting process (FIG. 78 (b)). As shown in FIG. 78 (c), "2601" to "2606" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

As shown in FIG. 78 (c), "HRSDSET" is set in the line number of "2601". This is not an instruction but data that is referred to when the developer of the pachinko machine 10 confirms the program. Therefore, the line number “2601” advances to the line number “2602” without executing any instruction.

The command "LDA, (HL +)" is set in the line number of "2602". "LD" is an LD update instruction by the LD update execution circuit 151, "A" is a content that specifies A register 104b as a transfer destination, and "(HL +)" is stored in the HL register 107 as a transfer source. The content is to specify a storage area corresponding to 2-byte address data and to instruct to add 1 to the value of the HL register 107 and update after loading the data. As described above, the HL register 107 stores "9420H" which is the start address of the hard random number maximum value table 64w (FIG. 77 (b)), and is set as the start address in the hard random number maximum value table 64w. In the corresponding first area, the lower 1 byte (“11H”) at the address of the jackpot type maximum value counter 191a is set. Therefore, when "LD A, (HL +)" is executed, "11H" is loaded in the A register 104b. Further, "9421H" is stored in the HL register 107.

An instruction "RET Z" is set in the line number of "2603". "RET Z" ends the maximum value setting execution process when the end data of the maximum value setting execution process (FIG. 78 (c)) is set in the A register 104b, and also ends the maximum value setting execution process in the A register 104b. If the end data is not set, this is an instruction to proceed to the next line number. When the end data ("00H") is set in the A register 104b at the line number "2602", "RET Z" is executed at the line number "2603" to execute this maximum value setting execution process. (FIG. 78 (c)) is terminated. On the other hand, if the data set in the A register 104b at the line number "2602" is data other than the end data, the maximum value is set even if "RET Z" is executed at the line number "2603". The execution process (FIG. 78 (c)) does not end, and the process proceeds to line number “2604”.

The command "LD W, (HL +)" is set in the line number of "2604". "LD" is an LD update instruction by the LD update execution circuit 151, "W" is a content for designating the W register 104a as a transfer destination, and "(HL +)" is stored in the HL register 107 as a transfer source. The content is to specify a storage area corresponding to 2-byte address data and to instruct to add 1 to the value of the HL register 107 and update after loading the data. As described above, "9421H" is stored in the HL register 107, and the maximum value of the jackpot type is stored in the second area corresponding to the "9421H" in the hard random number maximum value table 64w (FIG. 77 (b)). The maximum value data "63H" ("99") set in the counter 191a is set. Therefore, by executing "LD W, (HL +)", "63H" is loaded in the W register 104a, and the address data stored in the HL register 107 is updated to "9422H".

The command "LD (IY + A), W" is set in the line number of "2605". "LD" is a special LD instruction by the special LD execution circuit 194, and "(IY + A)" is a storage area corresponding to the address data obtained by adding the data of the A register 104b to the data of the IY register 109 as the transfer destination. It is the content to be specified, and "W" is the content to specify the W register 104a as the transfer source. As described above, the IY register 109 stores the upper 1-byte data (“1100H”) of the update circuits 191 to 193 in advance, and the A register 104b contains the address data of the jackpot type maximum value counter 191a. The lower 1 byte (“11H”) is stored. Further, the maximum value data (“63H”) corresponding to the jackpot type maximum value counter 191a is stored in the W register 104a. Therefore, by executing "LD (IY + A), W", the maximum value data "63H" is loaded into the jackpot type maximum value counter 191a.

In this way, by using the special LD instruction, the process of calculating the transfer destination address by adding the data stored in the A register 104b to the data stored in the IY register 109, and the W. The process of loading the maximum value data stored in the register 104a to the transfer destination can be executed by one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

An instruction "JR HRSDSET" is set in the line number of "2606". "JR" is a JR instruction as a jump instruction, and "HRSDSET" is a content that specifies the first line number "2601" in the maximum value setting execution process as a jump destination. By executing "JR HRSDSET", the process proceeds to the line number "2601" of the maximum value setting execution process.

After that, the processes of the line numbers "2602" to "2606" are executed with "9422H" stored in the HL register 107. As a result, the maximum value data "EEH" ("238") is loaded into the reach random number maximum value counter 192a, and the address data stored in the HL register 107 is updated to "9424H".

After that, the processes of the line numbers "2602" to "2606" are executed with "9424H" stored in the HL register 107. As a result, the maximum value data "FAH" is loaded into the general random number maximum value counter 193a, and the address data stored in the HL register 107 is updated to "9426H".

After that, the processes of the line numbers "2602" to "2606" are executed with "9426H" stored in the HL register 107. By executing "LDA, (HL +)" at the line number "2602", the end data "00H" is loaded into the A register 104b. After that, when "RET Z" is executed at the line number "2603" in the state where the end data is set in the A register 104b, the maximum value setting execution process is terminated. As described above, the maximum value setting execution process is a subroutine executed by the line number “2503” of the update circuit setting process (FIG. 78 (b)). Therefore, by executing "RET Z", the maximum value setting execution process is terminated, and the process proceeds to the line number "2504" of the update circuit setting process (FIG. 78 (b)).

In this way, by executing the update circuit setting process (FIG. 78 (b)) using the hard random number maximum value table 64w (FIG. 77 (b)), the jackpot type maximum value counter 191a and the reach random number maximum value counter are executed. The maximum value data can be set in the 192a and the general random number maximum value counter 193a.

After performing the process of setting the upper 1-byte data (“1100H”) in the IY register 109, the special LD instruction using the upper 1-byte data stored in the IY register 109 is issued a plurality of times (specifically). Is executed 3 times). Therefore, the entire address data (2 bytes) of the maximum value counters 191a to 193a is stored in the hard random number maximum value table 64w (FIG. 77 (b)) without setting the data for the upper 1 byte in the IY register 109. The data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced as compared with the configuration.

According to the present embodiment described in detail above, the following excellent effects are obtained.

By using the special LD instruction, the process of calculating the transfer destination address by adding the data stored in the A register 104b to the data stored in the IY register 109 and storing it in the W register 104a. The process of loading the maximum value data that has been set to the transfer destination can be executed with a single instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

The upper 1 byte at each address of the jackpot type maximum value counter 191a, the reach random number maximum value counter 192a, and the general electric random number maximum value counter 193a is common to "11H". "1100H" is stored in the IY register 109 in advance as data for the upper 1 byte of these maximum value counters 191a to 193a. The main CPU 63 reads the lower 1 byte at the addresses of the maximum value counters 191a to 193a from the main ROM 64, and adds the upper 1 byte data and the lower 1 byte data stored in the IY register 109. The address of each maximum value counter 191a to 193a is specified. This makes it easy to specify the addresses of the maximum value counters 191a to 193a.

After performing the process of setting "1100H" as the upper 1-byte data in the IY register 109, the special LD instruction using the upper 1-byte data stored in the IY register 109 is executed a plurality of times (specifically,). 3 times) Execute. Therefore, compared with the configuration in which the entire address data (2 bytes) of each maximum value counter 191a to 193a is stored in the hard random number maximum value table 64w without setting the data for the upper 1 byte in the IY register 109. The data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced.

The data set in the hard random number maximum value table 64w to specify the addresses of the maximum value counters 191a to 193a is only the lower 1 byte of the address. Therefore, in the hard random number maximum value table 64w, the data capacity (1 byte) of the data for specifying the address of the maximum value counters 191a to 193a and the data of the maximum value data set in the maximum value counters 191a to 193a. The capacity (1 byte) can be the same as the data capacity. As a result, the data capacity of the hard random number maximum value table 64w in the main ROM 64 can be reduced.

By using the LDT instruction that sets 12-bit numerical information and specifies the address, the start address of the hard random number maximum value table 64w is loaded into the HL register 107, so that 2-byte numerical information is set. Compared with the configuration in which the start address of the hard random number maximum value table 64w is loaded into the HL register 107 using the LD instruction that specifies the address, the data capacity of the program for executing the random number update circuit setting process is reduced. Can be done.

<Third embodiment>
In the present embodiment, the processing content of the display control processing is different from that of the first embodiment. Hereinafter, a configuration different from that of the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 79 is a flowchart showing a display control process executed by the main CPU 63 in the present embodiment. As already described in the first embodiment, the display control process is executed in step S514 of the timer interrupt process (FIG. 26). The display control process is executed by using the program for specific control and the data for specific control.

In the display control process, first, the D register 106a is cleared to "0" (step S2801). After that, the value of the first special figure hold number counter 118 in the work area 121 for specific control is set in the E register 106b (step S2802). After that, the process for acquiring the hold display is executed (step S2803). In the hold display acquisition process, the 4-bit data corresponding to the number of holds stored in the E register 106b from the hold display data table 64x (FIG. 80 (a)) stored in the main ROM 64 is stored in the W register 104a. The lower 4 bits (0th to 3rd bits) are loaded, and the upper 4 bits (4th to 7th bits) of the W register 104a are masked with "0". As a result, the hold display data HRn (n is an integer of 0 to 4) corresponding to the number of holds stored in the E register 106b can be set in the W register 104a.

FIG. 80A is an explanatory diagram for explaining the data structure of the hold display data table 64x. As shown in FIG. 80 (a), the hold display data table 64x is stored in the 1-byte area corresponding to the address of "9195H". "1" is set in the lower 4 bits (0th to 3rd bits) of the 1-byte area, and "0" is set in the upper 4 bits (4th to 7th bits). ..

FIG. 80B is an explanatory diagram for explaining the correspondence between the number of reservations and the acquisition mode of the reservation display data HRn. In the hold display acquisition execution process (FIG. 80 (d)) described later, the hold display data corresponding to the number of holds (any of "0" to "4") is set in the HL register 107 in order to set the hold display data in the W register 104a. “LDB W, (HL) .A ”is executed. In the LDB instruction, 4-bit data from the hold display data table 64x (FIG. 80 (a)) is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and the W register 104a is the third bit. The 4th to 7th bits are masked with "0".

As shown in FIG. 80 (b), the acquired data designation data corresponding to the reserved number “4” is “0CA8H”. Further, the acquired data designation data corresponding to the hold number "3" is "0CA9H", the acquisition data designation data corresponding to the hold number "2" is "0CAAH", and the acquisition data corresponding to the hold number "1". The designated data is "0CABH", and the acquired data designated data corresponding to the reserved number "0" is "0CACH". “0CA8H”, which is the acquired data designation data corresponding to the number of holds “4”, is numerical information calculated by the formula “{(start address of hold display data table 64x) −9000H} × 8”. The acquired data designation data corresponding to the number of holdings of "0" to "4" is numerical information calculated by subtracting the number of holdings from "0CACH" which is the acquisition data designation data corresponding to the number of holdings "0". Is.

When the LDB instruction "LDB W, (HL) .A" is executed while the acquisition data designation data ("0CACH") corresponding to the hold number "0" is stored in the HL register 107, the acquisition data is acquired. The start address becomes "9195H" and the acquisition start bit becomes "4". Then, the 4-bit data (“0000B”) set in the 4th and subsequent bits of the area corresponding to “9195H” is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , The 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". Thereby, the hold display data HR0 (“0000000000B”) corresponding to the hold number “0” can be set in the W register 104a. When the LDB instruction "LDB W, (HL) .A" is executed while the acquisition data designation data ("0CABH") corresponding to the hold number "1" is stored in the HL register 107, the acquisition data is acquired. The start address becomes "9195H" and the acquisition start bit becomes "3". Then, the 4-bit data (“0001B”) set in the third and subsequent bits of the area corresponding to “9195H” is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , The 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". Thereby, the hold display data HR0 (“00000001B”) corresponding to the hold number “1” can be set in the W register 104a. When the LDB instruction "LDB W, (HL) .A" is executed while the acquisition data designation data ("0CAAH") corresponding to the hold number "2" is stored in the HL register 107, the acquisition data is acquired. The start address becomes "9195H" and the acquisition start bit becomes "2". Then, the 4-bit data (“0011B”) set in the second and subsequent bits of the area corresponding to “9195H” is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , The 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". Thereby, the hold display data HR0 (“00000011B”) corresponding to the hold number “2” can be set in the W register 104a. When the LDB instruction "LDB W, (HL) .A" is executed while the acquisition data designation data ("0CA9H") corresponding to the hold number "3" is stored in the HL register 107, the acquisition data is acquired. The start address becomes "9195H" and the acquisition start bit becomes "1". Then, the 4-bit data (“0111B”) set in the first and subsequent bits of the area corresponding to “9195H” is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , The 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". Thereby, the hold display data HR0 (“000000111B”) corresponding to the hold number “3” can be set in the W register 104a. When the LDB instruction "LDB W, (HL) .A" is executed while the acquisition data designation data ("0CA8H") corresponding to the hold number "4" is stored in the HL register 107, the acquisition data is acquired. The start address becomes "9195H" and the acquisition start bit becomes "0". Then, the 4-bit data (“1111B”) set in the 0th and subsequent bits of the area corresponding to “9195H” is loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a. , The 4th to 7th bits (upper 4 bits) of the W register 104a are masked with "0". Thereby, the hold display data HR0 (“000011111B”) corresponding to the hold number “4” can be set in the W register 104a.

Next, the process for acquiring the hold display executed by the main CPU 63 will be described with reference to the flowchart of FIG. 80 (c). The hold display acquisition process is executed in step S2803 of the display control process (FIG. 79). Further, the hold display acquisition process is also executed in step S2806 and step S2809 of the display control process (FIG. 79).

In the hold display acquisition process, first, the above-mentioned "0CACH" is set in the HL register 107 (step S2901). After that, the value of the DE register 106 is subtracted from the value of the HL register 107 (step S2902). As described above, the value of the D register 106a is cleared to "0" in step S2801 of the display control process (FIG. 79), and the E register 106b is set to the first special figure hold number counter 118 in step S2802. The value is set. Therefore, by subtracting the value of the DE register 106 from the value of the HL register 107, the value obtained by subtracting the number of holdings of the first special figure holding area 115 from "0CACH" in the HL register 107, that is, the first special figure holding. The acquired data specification data corresponding to the value of the number counter 118 is stored. When the hold display acquisition process (FIG. 80 (c)) is executed in step S2806 of the display control process (FIG. 79), the process of step S2902 is executed so that the HL register 107 is second. The acquisition data designation data corresponding to the value of the special figure hold number counter 119 is stored, and the hold display acquisition process (FIG. 80 (c)) is performed in step S2809 of the display control process (FIG. 79). When it is executed, the process of step S2902 is executed, so that the acquired data designation data corresponding to the value of the normal figure hold number counter 127 is stored in the HL register 107.

After that, the hold display acquisition execution process is executed (step S2903), and the hold display acquisition process ends. FIG. 80D is an explanatory diagram for explaining the program contents of the hold display acquisition execution process. As shown in FIG. 80 (d), "2701" to "2703" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

As shown in FIG. 80 (d), the instruction "LDA, 03H" is set in the line number of "2702". "LD" is an LD instruction, "A" is a content for designating the A register 104b as a transfer destination, and "03H" is a content for designating 1-byte numerical information of "03H" as a transfer source. “03H” is a value obtained by subtracting “1” from the number of bits (“4”) acquired from the hold display data table 64x by the LDB instruction set in the line number “2702”. By executing "LD A, 03H", "03H" is loaded into the A register 104b of the "transfer destination". When the LDB instruction "LDB W, (HL) .A" is executed in the hold display acquisition execution process (FIG. 80 (d)) described later, the operation of adding 1 to the value of the A register 104b in the LDB execution circuit 157 is performed. At the same time, the value after the addition of 1 is used as the data of the number of acquired bits. Therefore, by storing "03H" in the A register 104b at the line number "2701", the number of bits of data acquired from the hold display data table 64x in the LDB instruction can be set to "4".

The command "LDB W, (HL) .A" is set in the line number of "2702". "LDB" is an LDB instruction by the LDB execution circuit 157, "W" is a content for designating the W register 104a as a "transfer destination", and "(HL)" is a 2-byte stored in the HL register 107. "A" is the content for designating the data as the acquisition data designation data, and "A" is the content for designating the 1-byte data stored in the A register 104b as the acquisition bit number designation data. As described above, the HL register 107 stores the acquired data designation data corresponding to the number of holds, and the A register 104b stores "03H". Further, "9000H", which is a reference address of the data table, is stored in the TP register 111. As shown in FIG. 80 (b), the acquisition start address is "9195H" in which the hold display data table 64x is stored, regardless of whether the number of holds is "0" to "4". As described above, by executing "LDB W, (HL) .A", the hold display data HRn (n is an integer of 0 to 4) corresponding to the hold number "n" is stored in the W register 104a. Can be set to.

In this way, the lower 4 bits of the hold display data HRn acquired from the hold display data table 64x using the LDB instruction are loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and the W register 104a is loaded. By masking the upper 4 bits of the data with "0", it corresponds to the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference address of the data table set in the TP register 111. The process of specifying the acquisition start address, the process of specifying the acquisition start bit corresponding to the 0th to 2nd bits (lower 3 bits) of the acquisition designation data, and the hold display data HRn acquired from the hold display data table 64x. The process of loading the lower 4 bits of the W register 104a into the 0th to 3rd bits (lower 4 bits) of the W register 104a and the process of masking the upper 4 bits of the W register 104a with "0" are executed by one instruction. be able to. These processes are executed by the LDB execution circuit 157. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

An instruction "RET" is set in the line number of "2703". As described above, the hold display acquisition execution process is a subroutine executed in step S2903 of the hold display acquisition process (FIG. 80 (c)). Therefore, when the instruction "RET" is executed, the hold display acquisition execution process ends and the hold display acquisition process also ends.

In this way, by using the LDB instruction, it is possible to acquire the lower 4 bits of the hold display data HRn by shifting the acquisition start bit in the mode corresponding to the hold number in the hold display data table 64x. Therefore, the data capacity of the hold display data table 64x can be reduced to 1 byte.

Returning to the description of the display control process (FIG. 79), after executing the hold display acquisition process in step S2803, the hold display data HRn stored in the W register 104a is the first in the work area 121 for specific control. It is set in the special figure hold display area (step S2804). As a result, the first special figure holding display unit 37c can display the number corresponding to the number of holdings of the first special drawing holding area 115.

After that, the value of the second special figure hold number counter 119 in the work area 121 for specific control is set in the E register 106b (step S2805), and the above-mentioned hold display acquisition process (FIG. 80 (c)) is executed (FIG. 80 (c)). Step S2806). As a result, the hold display data HRn corresponding to the value of the second special figure hold number counter 119 can be acquired in the W register 104a.

After that, the hold display data HRn stored in the W register 104a is set in the second special figure hold display area in the work area 121 for specific control (step S2807). As a result, the second special figure holding display unit 37d can display the number corresponding to the number of holdings of the second special drawing holding area 116.

After that, the value of the normal figure hold number counter 127 in the work area 121 for specific control is set in the E register 106b (step S2808), and the above-mentioned hold display acquisition process (FIG. 80 (c)) is executed (step S2809). ). As a result, the hold display data HRn corresponding to the value of the normal figure hold number counter 127 can be acquired in the W register 104a.

After that, the hold display data HRn stored in the W register 104a is set in the normal figure hold display area in the work area 121 for specific control (step S2810). As a result, it is possible to display the number of reserved areas 125 in the reserved area 125 on the reserved display unit 38b. After that, various display data output processes are executed (step S2811), and the present display control process is terminated.

According to the present embodiment described in detail above, the following excellent effects are obtained.

The lower 4 bits of the hold display data HRn acquired from the hold display data table 64x using the LDB instruction are loaded into the 0th to 3rd bits (lower 4 bits) of the W register 104a, and the 4th to 4th bits of the W register 104a are loaded. By masking the 7th bit (upper 4 bits) with "0", the data of the 3rd to 15th bits in the 2-byte acquisition data designation data and the reference of the data table set in the TP register 111. The process of specifying the acquisition start address corresponding to the address, the process of specifying the acquisition start bit corresponding to the 0th to 2nd bits (lower 3 bits) of the acquisition designation data, and the process of specifying the acquisition start bit, which was acquired from the hold display data table 64x. The process of loading the lower 4 bits of the hold display data HRn into the 0th to 3rd bits (lower 4 bits) of the W register 104a and the 4th to 7th bits (upper 4 bits) of the W register 104a are "0". The process of masking with can be executed with one instruction. These processes are executed by the LDB execution circuit 157. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

By using the LDB instruction, the lower 4 bits of the hold display data HRn can be acquired by shifting the acquisition start bit in the mode corresponding to the number of holds in the hold display data table 64x. Therefore, the data capacity of the hold display data table 64x can be set to 1 byte. The configuration in which the entire 5 types of hold display data HRn corresponding to the 5 types of hold numbers are set in the hold display data table, and the 5 types of hold display data HRn corresponding to the 5 types of hold numbers in the hold display data table. The data capacity of the hold display data table 64x can be reduced as compared with the configuration in which the lower 4 bits of are set.

<Fourth Embodiment>
This embodiment differs from the first embodiment in that the final address of the second initialization table and the start address of the random number maximum value table are common addresses. Hereinafter, a configuration different from that of the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 81 (a) is an explanatory diagram for explaining the data structure of the first initialization table 64y in the present embodiment, and FIG. 81 (b) is a description for explaining the data structure of the second initialization table 64z. FIG. 81 (c) is an explanatory diagram for explaining the data structure of the random number maximum value table 64α.

The first initialization table 64y is used in the fraudulent radio wave detection counter 133, the fraudulent magnetic detection counter 134, and the abnormal vibration detection counter 135, similarly to the first initialization table 64k (FIG. 18A) in the first embodiment. In addition to being a data table for setting initial values, the second initialization table 64z is a power failure area 131 and an invalidity as in the second initialization table 64m (FIG. 18B) in the first embodiment. This is a data table for clearing the monitoring timer counter 132 to "0". Further, the random number maximum value table 64α has the same as the random number maximum value table 64p (FIG. 23A) in the first embodiment, that is, the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the random number initial value. It is a data table used for setting the maximum value data in the maximum value counters CN1 to CN6 corresponding to the counter C4, the variation type counter C5, and the general electric random number counter C6.

As shown in FIG. 81 (a), the first initialization table 64y is the same as the first initialization table 64k (FIG. 18 (a)) in the first embodiment, from “9400H” to “9400H” in the main ROM 64. It is set to the address of "9405H". As shown in FIG. 81 (b), the second initialization table 64z is the same as the second initialization table 64 m (FIG. 18 (b)) in the first embodiment, and is "9406H" in the main ROM 64. It is set to the address of "940BH". As shown in FIG. 81 (c), the random number maximum value table 64α is set to the addresses of “940BH” to “9413H” in the main ROM 64.

As shown in FIG. 81 (b), the final address of the second initialization table 64z is “940BH”, and as shown in FIG. 81 (c), the “940BH” is also the start address of the random number maximum value table 64α. One byte of data called "63H" is set in the "940BH". “63H” is the maximum value data of the maximum value counter CN2 for the jackpot type as shown in FIG. 81 (c), and the data setting execution process (FIG. 82 (b)) described later as shown in FIG. 81 (b). ) End data.

As described above, "63H" which is the maximum value data of the maximum value counter CN2 for the jackpot type and the end data of the data setting execution process (FIG. 82 (b)) in the area corresponding to one address in the main ROM 64. Is set, so that the data setting execution process (FIG. 82 (b)) is terminated separately from the area where the maximum value data of the maximum value counter CN2 for the jackpot type is set in the main ROM 64. Compared with the configuration in which the area where the data is set is provided, the total data capacity of the second initialization table 64z and the random number maximum value table 64α is reduced in the main ROM 64.

FIG. 82A is an explanatory diagram for explaining the program contents of the power-on setting process executed by the main CPU 63. As already described in the first embodiment, the power-on setting process is executed in step S118 of the main process (FIG. 15). As shown in FIG. 82 (a), "2801" to "2806" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

The line numbers of "2801" to "2802" are set with the same instructions as the line numbers of "1001" to "1002" in the power-on setting process (FIG. 82 (a)) in the first embodiment. There is. Specifically, the command "LDT HL, 400H" is set in the line number of "2801". "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "400H" sets 12-bit numerical information of "400H" as a transfer source. The content. As already described in the first embodiment, the reference address (“9000H”) of the data table is set in the TP register 111 in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 400H", "9400H" obtained by adding "9000H" set in the TP register 111 to "400H" set as the transfer source is obtained. It is loaded into the HL register 107. As a result, the start address of the first initialization table 64y (FIG. 81 (a)) can be set in the HL register 107.

The command "XOR D, D" is set in the line number of "2802". "XOR" is an exclusive OR instruction called an XOR instruction, and "D" before and after the comma specifies the D register 106a. By executing "XOR D, D", the operation result of the exclusive OR of the value of the D register 106a and the value of the D register 106a is set in the D register 106a specified by "D" before the comma. Will be done. Specifically, "00H" is set in the D register 106a regardless of the value of the D register 106a. That is, the D register 106a is cleared to "0". As already described with reference to FIG. 16A in the first embodiment, the upper 1 byte in the area to be power-on setting process and the address of the counter is common to "00H". The instruction of the line number "2802" is an instruction for setting the common upper 1 byte ("00H") in the D register 106a.

An instruction "CALL 4BTS20" is set in the line number of "2803". “4BTS20” is a data setting execution process (FIG. 82 (b)) described later. The instruction "CALL 4BTS20" is an instruction for calling a subroutine called data setting execution processing. In the line number "2803", the data setting execution process is executed in a state where the start address of the first initialization table 64y is set in the HL register 107 and "00H" is stored in the D register 106a. As described above, the first initialization table 64y is a data table for setting initial values in the fraudulent radio wave detection counter 133, the fraudulent magnetism detection counter 134, and the abnormal vibration detection counter 135. By executing the data setting execution process at the line number "2803", "5" is set as the initial value in the fraudulent radio wave detection counter 133, and "10" is set as the initial value in the fraudulent magnetic detection counter 134. Then, "15" is initially set in the abnormal vibration detection counter 135. When the subroutine of the data setting execution process called based on the instruction of the line number "2803" is completed, the process proceeds to the line number of "2804". Although the details will be described later, when the data setting execution process is executed at the line number “2803”, “9405H” is set in the HL register 107.

An instruction "INC HL" is set in the line number of "2804". "INC HL" is an arithmetic instruction that adds 1 to the value of the HL register 107. When "INC HL" is executed at the line number "2804", the value of the HL register 107 is incremented by 1 and updated to "9406H". As a result, the start address of the second initialization table 64z (FIG. 81 (c)) in the main ROM 64 can be set in the HL register 107.

In the line number of "2805", the instruction "CALL 4BTS20" is set as in the line number of "2803" described above. At the line number "2805", the data setting execution process is executed in a state where the start address of the second initialization table 64z is set in the HL register 107 and "00H" is stored in the D register 106a. By executing the data setting execution process at the line number "2805", the power failure area 131 and the fraud monitoring timer counter 132 are cleared to "0". When the subroutine of the data setting execution process called based on the instruction of the line number "2805" is completed, the process proceeds to the line number of "2806".

An instruction "RET" is set in the line number of "2806". As described above, the power-on setting process is a subroutine executed in step S118 of the main process (FIG. 15). Therefore, when the instruction "RET" is executed, the process proceeds to step S119 of the main process (FIG. 15).

Next, the program contents of the data setting execution process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 82 (b). As described above, the data setting execution process is called by executing "CALL 4BTS20" at the line number "2803" and the line number "2805" of the power-on setting process (FIG. 82 (a)). As shown in FIG. 82 (b), "2901" to "2911" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

First, a case where the data setting execution process is executed at the line number “2803” of the power-on setting process (FIG. 82 (a)) will be described. As described above, in the row number “2803”, “9400H” which is the start address of the first initialization table 64y (FIG. 81 (a)) is stored in the HL register 107, and the fraudulent radio wave detection counter 133, The data setting execution process is executed in a state where the upper 1 byte (“00H”) common to the address data of the fraudulent magnetic detection counter 134 and the abnormal vibration detection counter 135 is stored in the D register 106a.

In the data setting execution process executed by the line number "2803", first, the data set in the address range of "9400H" to "9402H" in the first initialization table 64y (FIG. 81A) is used. The commands of line numbers "2902" to "2911" are executed. As shown in FIG. 81 (a), the initial value “5” is set in the fraudulent radio wave detection counter 133 for the upper 4 bits of the first area corresponding to the start address “9400H” of the first initialization table 64y. "0101B" is set as the initial setting data for setting, and as the initial setting data for setting the initial value "10" in the fraudulent magnetism detection counter 134 in the lower 4 bits of the first area. "1010B" is set. In the second area corresponding to "9401H" following "9400H", "21H", which is the lower 1 byte of the address of the fraudulent radio wave detection counter 133, is set. Further, in the third area corresponding to "9402H" following "9401H", "22H", which is the lower 1 byte of the address of the fraudulent magnetism detection counter 134, is set.

As shown in FIG. 82 (b), "4BTS20" is set for the line number of "2901". This is not an instruction but data that is referred to when the developer of the pachinko machine 10 confirms the program. Therefore, at the line number "2901", the process proceeds to the line number "2902" without executing any instruction.

The command "LDH WA, (HL +)" is set in the line number of "2902". “LDH” is an LDH update instruction by the LDH update execution circuit 152, and “WA” is a content that specifies the WA register 104 as the transfer destination. Further, "(HL +)" is a content that specifies the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source, and the value of the HL register 107 is set to 1 after the data is loaded. It is a content instructing to add and update the address stored in the HL register 107. As described above, in the first initialization table 64y, "0101B" is set as the initial setting data in the upper 4 bits of the first area corresponding to "9400H", and the lower 4 bits of the first area are set. "1010B" is set as the initial setting data. Therefore, by executing "LDH WA, (HL +)" at the line number "2902", "0101B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a. At the same time, the upper 4 bits of the W register 104a are masked with "0". Further, "1010B", which is the lower 4 bits of the first area, is set in the lower 4 bits of the A register 104b, and the upper 4 bits of the A register 104b are masked by "0". As a result, the data "000000101B" for initial setting can be stored in the W register 104a, and the data "00001010B" for initial setting is stored in the A register 104b. be able to. Further, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9401H".

The command "LDE, (HL)" is set in the line number of "2903". “LD” is an LD instruction, and “E” is a content that specifies the E register 106b as the transfer destination. Further, "(HL)" is a content for designating the data stored in the area corresponding to the address stored in the HL register 107 as the transfer source. As described above, in the second area corresponding to "9401H" in the first initialization table 64y, "21H", which is the lower 1 byte in the address of the fraudulent radio wave detection counter 133, is set. By executing "LDE, (HL)" at the line number "2903", "21H" is stored in the E register 106b. As a result, the address "0021H" of the fraudulent radio wave detection counter 133 can be stored in the DE register 106.

An instruction "RET Z" is set in the line number of "2904". "RET Z" in the line number "2904" ends the data setting execution process when the end data is set in the E register 106b, and when the end data is not set in the E register 106b. Is an instruction to proceed to the next line number. In this embodiment, "63H" is set as the end data. As described above, since "21H" is stored in the E register 106b at the immediately preceding line number "2903", the process proceeds to the line number "2905".

An instruction "INC HL" is set in the line number of "2905". By executing "INC HL" at the line number "2905", "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9402H". In the present embodiment, the main MPU 62 does not include the LD update execution circuit 151. The update of the address stored in the HL register 107 is performed by using the operation instruction "INC".

The command "LD (DE), W" is set in the line number of "2906". "LD" is an LD instruction, "(DE)" is a content that specifies an area corresponding to an address stored in the DE register 106 as a transfer destination, and "W" specifies a W register 104a as a transfer source. It is the content to be done. As described above, the DE register 106 stores the address “0021H” of the fraudulent radio wave detection counter 133, and the W register 104a stores the data “000000101B” for initial setting. Therefore, by executing "LD (DE), W" at the line number "2905", the data for the initial setting is loaded into the fraudulent radio wave detection counter 133. As a result, the initial value "5" can be set in the fraudulent radio wave detection counter 133.

As with the line number of "2903", the command "LDE, (HL)" is set in the line number of "2907". As described above, "9402H" is stored in the HL register 107. As described above, in the third area corresponding to "9402H" in the first initialization table 64y (FIG. 81A), "22H", which is the lower 1 byte in the address of the fraudulent magnetic detection counter 134, is set. ing. By executing "LDE, (HL)" at the line number "2907", "22H" is loaded into the E register 106b. As a result, the DE register 106 can be in a state in which "0022H", which is the address of the fraudulent magnetism detection counter 134, is stored.

As with the line number of "2904", the command "RET Z" is set in the line number of "2908". In the "RET Z" in the line number "2908", as in the "RET Z" in the line number "2904", this data setting execution process is performed when the end data "63H" is set in the E register 106b. If the end data is not set in the E register 106b, the process proceeds to the next line number. As described above, since "22H" is stored in the E register 106b at the immediately preceding line number "2907", the process proceeds to the line number "2909".

In the line number of "2909", the instruction "INC HL" is set as in the line number of "2905". By executing "INC HL" at the line number "2909", "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9403H".

The command "LD (DE), A" is set in the line number of "2910". "LD" is an LD instruction, "(DE)" is a content that specifies an area corresponding to an address stored in the DE register 106 as a transfer destination, and "A" specifies an A register 104b as a transfer source. It is the content to be done. As described above, the DE register 106 stores the address “0022H” of the illicit magnetic detection counter 134, and the A register 104b stores the data “000001010B” for initial setting. Therefore, when "LD (DE), A" is executed at the line number "2910", the data for the initial setting is loaded into the fraudulent magnetism detection counter 134. As a result, "10" can be set as the initial value in the fraudulent magnetism detection counter 134.

An instruction "JR 4BTS20" is set in the line number of "2911". "JR" is a JR instruction as an unconditional jump instruction, and "4BTS20" is a content for designating a start address of data setting execution processing as a jump destination. When "JR 4BTS20" is executed, the process proceeds to the line number "2901" of this data setting execution process.

After that, the instructions of line numbers "2902" to "2911" are executed using the data set in the address range of "9403H" to "9405H" in the first initialization table 64y (FIG. 81A). To. As shown in FIG. 81 (a), initial setting data for setting “5” as an initial value in the abnormal vibration detection counter 135 in the upper 4 bits of the first area corresponding to “9403H” following “9402H”. "1111B" is set as. Further, "0000B" is set as adjustment data that is not used in the lower 4 bits of the first area. In the second area corresponding to "9404H" following "9403H", "23H", which is the lower 1 byte of the address of the abnormal vibration detection counter 135, is set. Further, "00H" is set as end data in the third area corresponding to "9405H" following "9404H".

Returning to the description of the data setting execution process (FIG. 82 (b)), the line number “2901” proceeds to the line number “2902” without executing any instruction. As described above, in the first initialization table 64y, the initial setting data ("1111B") is set in the upper 4 bits of the first area corresponding to the address of "9403H", and the lower 4 bits are adjusted. Data ("0000B") is set. By executing "LDH WA, (HL)" at the line number "2902", "1111B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the said The upper 4 bits of the W register 104a are masked with "0". Further, "0000B", which is the lower 4 bits of the first area, is set in the lower 4 bits of the A register 104b, and the upper 4 bits of the A register 104b are masked by "0". As a result, the data "00001111B" for initial setting can be stored in the W register 104a. The A register 104b is in a state in which "0000000000B" for adjustment is stored. Further, 1 is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9404H".

As described above, in the second area corresponding to "9404H" in the first initialization table 64y, "23H", which is the lower 1 byte of the address corresponding to the abnormal vibration detection counter 135, is set. By executing "LDE, (HL)" at the line number "2903", "23H" is stored in the E register 106b. As a result, the address "0023H" of the abnormal vibration detection counter 135 can be stored in the DE register 106. After that, in the line number "2904", since the data stored in the E register 106b is "23H" and not the end data ("63H"), the process proceeds to the line number "2905". At the line number "2905", when "INC HL" is executed, the value of the HL register 107 is incremented by 1 and updated to "9405H".

As described above, the DE register 106 stores the address “0023H” of the abnormal vibration detection counter 135, and the W register 104a stores the data “000011111B” for initial setting. Therefore, when "LD (DE), W" is executed at the line number "2906", the data for the initial setting is loaded into the abnormal vibration detection counter 135. As a result, "15" can be set as the initial value in the abnormal vibration detection counter 135.

As described above, the end data "63H" is set in the third area corresponding to "9405H". By executing "LDE, (HL)" at the line number "2907", "63H" is loaded into the E register 106b. After that, in the state where the end data ("63H") is stored in the E register 106b, "RET Z" is executed at the line number "2908", and this data setting process ends. As described above, when the data setting execution process is completed at the line number “2803” of the power-on setting process (FIG. 82 (a)), the process proceeds to the line number “2804”.

Next, a case where the data setting execution process (FIG. 82 (b)) is executed at the line number “2805” of the power-on setting process (FIG. 82 (a)) will be described in detail. In the line number "2805", "9406H" which is the start address of the second initialization table 64z is stored in the HL register 107, and the power failure area 131, the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer counter 132. The data setting execution process is executed in a state where the upper 1-byte data (“00H”) common to the addresses in the upper area of is stored in the D register 106a.

In the data setting process executed by the line number "2805", first, the data set in the address range of "9406H" to "9408H" in the second initialization table 64z is used to form the line numbers "2902" to "2902". 2911 ”is executed. As shown in FIG. 81 (b), the upper 4 bits of the first area corresponding to the start address “9406H” of the second initialization table 64z are “0” as data for clearing the power failure area 131. "0000B" is set, and "0000B" is set as "0" clear data for clearing the lower area of the fraud monitoring timer counter 132 to "0" in the lower 4 bits of the first area. In the second area corresponding to "9407H" following "9406H", "01H", which is the lower 1 byte of the address of the power failure area 131, is set. Further, in the third area corresponding to "9408H" following "9407H", "08H", which is the lower 1 byte of the address corresponding to the lower area of the fraud monitoring timer counter 132, is set.

In the line number "2901" of the data setting execution process (FIG. 82 (b)), as described above, the process proceeds to the line number "2902" without executing any instruction. As described above, in the second initialization table 64z, "0" clear data ("0000B") is set in the upper 4 bits and the lower 4 bits of the first area corresponding to "9406H". Therefore, by executing "LDH WA, (HL +)" at the line number "2902", "0000B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a. At the same time, the upper 4 bits of the W register 104a are masked with "0". Further, the lower 4 bits of the A register 104b are set to "0000B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "0000000000B" for clearing "0" can be stored in the W register 104a and the A register 104b. Further, the value of the HL register 107 is added by "1", and the address stored in the HL register 107 is updated to "9407H".

As described above, in the second area corresponding to "9407H" in the second initialization table 64z, "01H", which is the lower 1 byte in the address of the power failure area 131, is set. By executing "LDE, (HL)" at the line number "2903", "01H" is stored in the E register 106b. As a result, the address "0001H" of the power failure area 131 can be stored in the DE register 106. Although "RET Z" is set in the following line number "2904", the data stored in the E register 106b is "01H" and is not the end data ("63H"), so the line number " 2905 ”. At the line number "2905", by executing "INC HL", the value of the HL register 107 is incremented by 1 and updated to "9408H".

As described above, the DE register 106 stores the address “0001H” of the power failure area 131, and the W register 104a stores the data “0000000000B” for clearing “0”. Therefore, when "LD (DE), W" is executed at the line number "2906", the data for clearing the "0" is loaded in the power failure area 131, and the power failure area 131 clears "0". Will be done. As described above, the power failure flag 131a is provided in the least significant bit of the power failure area 131. Therefore, the power failure flag 131a can be cleared by "0" by clearing the power failure area 131 by "0".

As shown in FIG. 81 (b), in the third area corresponding to “9408H” in the second initialization table 64z (FIG. 81 (b)), the lower 1 byte in the address of the lower area of the fraud monitoring timer counter 132 Is set to "08H". By executing "LDE, (HL)" at the line number "2907", "08H" is loaded into the E register 106b. As a result, the DE register 106 can be in a state in which "0008H", which is the address of the lower area of the fraud monitoring timer counter 132, is stored. Although "RET Z" is set in the following line number "2908", the data stored in the E register 106b is "08H" and is not the end data ("63H"), so the line number " Proceed to "2909". At the line number "2909", by executing "INC HL", the value of the HL register 107 is incremented by 1 and updated to "9409H".

As described above, the DE register 106 stores "0008H", which is the address of the lower area of the fraud monitoring timer counter 132, and the A register 104b contains "0000000000B", which is the data for clearing "0". It is stored. Therefore, when "LD (DE), A" is executed at the line number "2910", the data for clearing "0" is loaded in the lower area of the fraud monitoring timer counter 132, and the fraud monitoring timer The lower area of the counter 132 is cleared to "0".

After that, by executing "JR 4BTS20" at the line number "2911", the process proceeds to the line number "2901" of this data setting execution process. Then, this time, the instructions of the line numbers "2902" to "2911" are executed using the data set in the address range of "9409H" to "940BH" of the second initialization table 64z.

As shown in FIG. 81 (b), "0000B" is used as data for clearing "0" in the upper area of the fraud monitoring timer counter 132 in the upper 4 bits of the first area corresponding to "9409H" following "9408H". Is set. Further, "0000B" is set as adjustment data that is not used in the lower 4 bits of the first area. In the second area corresponding to "940AH" following "9409H", "09H", which is the lower 1 byte of the address ("0009H") corresponding to the upper area of the fraud monitoring timer counter 132, is set. Further, "63H" is set as end data in the third area corresponding to "940BH" following "940AH".

Returning to the description of the data setting execution process (FIG. 82 (b)), the line number “2901” proceeds to the line number “2902” without executing any instruction. As described above, in the second initialization table 64z, data for clearing "0" ("0000B") is set in the upper 4 bits of the first area corresponding to the address of "9409H", and the lower 4 bits are set. The adjustment data (“0000B”) is set in. By executing "LDH WA, (HL +)" at the line number "2902", "0000B", which is the upper 4 bits of the first area, is set in the lower 4 bits of the W register 104a, and the said The upper 4 bits of the W register 104a are masked with "0". Further, the lower 4 bits of the A register 104b are set to "0000B", which is the lower 4 bits of the first area, and the upper 4 bits of the A register 104b are masked with "0". As a result, the data "0000000000B" for clearing "0" can be stored in the W register 104a and the A register 104b. Further, the value of the HL register 107 is added by 1, and the address stored in the HL register 107 is updated to "940AH".

As described above, in the second area corresponding to 940 AH in the second initialization table 64z (FIG. 81 (b)), "09H", which is the lower 1 byte of the address corresponding to the upper area of the fraud monitoring timer counter 132, is located. It has been set. By executing "LDE, (HL)" at the line number "2903", "09H" is stored in the E register 106b. As a result, the address "0009H" in the upper area of the fraud monitoring timer counter 132 can be stored in the DE register 106. Although "RET Z" is set in the following line number "2904", the data stored in the E register 106b is "09H" and is not the end data ("63H"), so the line number " 2905 ”.

At the line number "2905", by executing "INC HL", the value of the HL register 107 is incremented by 1 and updated to "940BH". As a result, "940BH", which is the final address of the second initialization table 64z and the start address of the random number maximum value table 64α, is stored in the HL register 107.

As described above, the DE register 106 stores "0009H" which is the address of the upper area of the fraud monitoring timer counter 132, and the W register 104a contains "0000000000B" which is the data for clearing "0". It is stored. Therefore, by executing "LD (DE), W" at the line number "2906", the data for clearing the "0" is loaded in the upper area of the fraud monitoring timer counter 132. As a result, the upper area of the fraud monitoring timer counter 132 can be cleared to "0".

As described above, the end data "63H" is set in the third area corresponding to 940BH. By executing "LDE, (HL)" at the line number "2907", "63H" is loaded into the E register 106b. After that, in the state where the end data (“63H”) is stored in the E register 106b, “RET Z” is executed at the line number “2908”, so that the data setting execution process ends.

As described above, when the data setting execution process called by the line number “2805” of the power-on setting process (FIG. 82 (a)) is completed, the process proceeds to the line number “2806”. As already described with reference to FIG. 82 (a), the instruction "RET" is set in the line number of "2806", and when the "RET" is executed, the power-on setting process is completed. do.

In this way, in a state where "940BH", which is the final address of the second initialization table 64z and the start address of the random number maximum value table 64α, is stored in the HL register 107, step S118 of the main process (FIG. 15). The power-on setting process in step S119 is completed, and the random number maximum value setting process in step S119 is executed. Therefore, at the start of the random number maximum value setting process, the process for setting the start address of the random number maximum value table 64α in the HL register 107 can be omitted. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

The random number maximum value setting process (FIG. 83) is executed using the random number maximum value table 64α. As shown in FIG. 81 (c), the addresses of "940BH" to "9413H" in the random number maximum value table 64α are the "9200H" of the random number maximum value table 64p (FIG. 23 (a)) in the first embodiment. The same data as the data set in the addresses of "9208H" is set. Specifically, "63H" which is the maximum value data of the jackpot type counter C2 is set in "940BH", and "EEH" which is the maximum value data of the reach random number counter C3 is set in "940CH". In "940DH", "FAH" which is the maximum value data of the fluctuation type counter C5 is set, and in "940EH", "C6H" which is the maximum value data of the general electric random number counter C6 is set. There is. Further, "1F3FH" ("7999"), which is the maximum value data of the random number counter C1, is set in "940FH" to "9410H", and "9411H" to "9412H" of the random number initial value counter C4. The maximum value data "1F3FH" is set. Furthermore, "00H" is set in "9413H" as data for ending the random number maximum value setting process.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. As already described in the first embodiment, the random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed by using the program for specific control and the data for specific control.

In the random number maximum value setting process, first, the command "LDY BC, 19H" is executed (step) in the same manner as the line number "1302" of the maximum value setting start process (FIG. 24 (b)) in the first embodiment. S3001). "LDY" is the first LDY instruction by the first LDY execution circuit 156, "BC" is the content that specifies the BC register 105 as the transfer destination, and "19H" is a 1-byte numerical value of "19H" as the "transfer source". It is the content to set the information. As already described in the first embodiment, the IY register 109 is set to "0000H" as the reference address for specific control in step S103 of the main process (FIG. 15). Therefore, by executing "LDY BC, 19H", "0019H" obtained by adding "0000H" set in the IY register 109 to "19H" set as the "transfer source" is added. Is loaded into the BC register 105. As a result, the address of the jackpot type maximum value counter CN2 in the work area 121 for specific control can be set in the BC register 105.

As described above, the random number maximum value setting process (FIG. 83) is executed in a state where the start address “940BH” of the random number maximum value table 64α is stored in the HL register 107. As a result, the process for setting the start address in the HL register 107 can be omitted.

After performing the process of step S3001, the instruction "LDA, (HL)" is executed (step S3002). "LD" is an LD instruction, "A" is a content that specifies A register 104b as a transfer destination, and "(HL)" is stored in the area corresponding to the address stored in the HL register 107 as a transfer source. It is the content to specify the maximum value data that is set. By executing "LD A, (HL)", the maximum value data ("63H") corresponding to the address data ("940BH") stored in the HL register 107 is loaded into the A register 104b. As a result, the maximum value data to be set can be set in the A register 104b.

After that, the instruction "INC HL" is executed (step S3003). When "INC HL" is executed, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "940CH". As a result, the maximum value data to be set can be updated.

The processes of steps S3002 to S3006 are repeatedly executed until an affirmative determination is made in step S3004 described later. Every time the process of step S3003 is executed, the maximum value data of the jackpot type counter C2 → the maximum value data of the reach random number counter C3 → the maximum value data of the variation type counter C5 → the maximum value data of the general electric random number counter C6 → the winning random number. Lower 1 byte of the maximum value data of the counter C1 → Higher 1 byte of the maximum value data of the winning random number counter C1 → Lower 1 byte of the maximum value data of the random number initial value counter C4 → Upper 1 of the maximum value data of the random number initial value counter C4 The maximum value data to be set is updated in the order of bytes. Further, when the process of step S3002 is executed with the address stored in the HL register 107 updated to "9413H", the end data ("00H") is set in the A register 104b.

After performing the processing of step S3003, in steps S3004 to S3006, the same processing as in steps S303 to S305 of the random number maximum value setting processing (FIG. 23B) in the first embodiment is executed. Specifically, first, it is determined whether or not "00H", which is the end data, is set in the A register 104b (step S3004), and when the end data is set in the A register 104b (step S3004:). If YES), the random number maximum value setting process is terminated.

On the other hand, when the end data is not set in the A register 104b (step S3004: NO), the maximum value data setting process is executed (step S3005). In the maximum value data setting process, the instruction "LD (BC), A" is executed. "LD" is a load instruction, "(BC)" is a content that specifies a setting target counter corresponding to an address stored in the BC register 105 as a transfer destination, and "A" is an A register 104b as a transfer source. Is the content to specify. By executing "LD (BC), A", the maximum value data stored in the A register 104b is loaded into the counter selected as the setting target counter among the maximum value counters CN1 to CN6. As a result, the maximum value data can be set in the setting target counter.

After that, the setting target update process is executed (step S3006). In the setting target update process, the command "INC BC" is executed. "INC" is an instruction to add "1" to the addition target, and "BC" is a content to specify the value of the BC register 105 as the addition target. When "INC BC" is executed, "1" is added to the value of the BC register 105. As a result, the maximum value counters CN1 to CN6 selected as the setting target counters are updated. Every time the setting target update process is executed in step S3006, the maximum value counter for jackpot type CN2 → maximum value counter for reach CN3 → maximum value counter for variable type CN5 → maximum value counter for general electric power CN6 → maximum value for hit The setting target counter is updated in the order of the lower area of the counter CN1 → the upper area of the hit maximum value counter CN1 → the lower area of the initial value maximum value counter CN4 → the upper area of the initial value maximum value counter CN4.

After executing the setting target update process in step S3006, the process returns to step S3002, and the processes of steps S3002 to S3006 are repeated until the end data is stored in the A register 104b and an affirmative determination is made in step S3004. Run. Thereby, the maximum value data can be set in the maximum value counters CN1 to CN6.

According to the present embodiment described in detail above, the following excellent effects are obtained.

The final address of the second initialization table 64z and the start address of the random number maximum value table 64α are common addresses. “940BH” is the final address of the second initialization table 64z and the start address of the random number maximum value table 64α. In the area corresponding to the address of "940BH" in the main ROM 64, "63H" which is the maximum value data of the maximum value counter CN2 for the jackpot type is set. The "63H" is set as the end data of the data setting execution process (FIG. 82 (b)) executed in the power-on setting process (FIG. 82 (a)). Power-on setting in step S118 of the main process (FIG. 15) with "940BH", which is the final address of the second initialization table 64z and the start address of the random number maximum value table 64α, stored in the HL register 107. The process is completed, and the random number maximum value setting process in step S119 is executed. Therefore, at the start of the random number maximum value setting process, the process for setting the start address of the random number maximum value table 64α in the HL register 107 can be omitted. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

In the main ROM 64, "63H", which is the maximum value data of the jackpot type maximum value counter CN2 and the end data of the data setting execution process (FIG. 82 (b)), is set in the area corresponding to one address. Due to this configuration, the data for ending the data setting execution process (FIG. 82 (b)) is set separately from the area where the maximum value data of the maximum value counter CN2 for the jackpot type is set in the main ROM 64. The total data capacity of the second initialization table 64z and the random number maximum value table 64α is reduced in the main ROM 64 as compared with the configuration in which the area is provided.

<Fifth Embodiment>
In the present embodiment, the power-on setting process is completed with "19H", which is the lower 1 byte of the address of the jackpot type maximum value counter CN2, stored in the E register 106b, and the "19H" is used. It differs from the first embodiment in that the random number maximum value setting process is executed. Hereinafter, a configuration different from that of the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 84A is an explanatory diagram for explaining the data structure of the second initialization table 64β in the present embodiment. The second initialization table 64β (FIG. 84 (a)) is the same as the second initialization table 64 m (FIG. 18 (b)) in the first embodiment, and is “9406H” to “940BH” in the main ROM 64. It is set to the address of.

As shown in FIG. 84 (a), in the third area corresponding to the address of "940BH", "19H", which is the lower 1 byte of the address of the jackpot type maximum value counter CN2, is set as the end data. ing. As already described in the first embodiment, the power-on setting process (FIG. 17 (c)) is executed in step S118 of the main process (FIG. 15). In the data setting execution process (FIG. 20 (c)) executed at the line number “1004” of the power-on setting process, the command “RET Z” is executed at the line number “1107”. At the line number "1107", when the end data is set in the E register 106b, the data setting execution process ends and the power-on setting process ends. After that, the random number maximum value setting process is executed in step S119 of the main process (FIG. 15).

In this embodiment, "19H" is set as the end data of the data setting execution process (FIG. 20 (c)). Therefore, in the line number "1107", when "19H" is set as the end data in the E register 106b, the data setting execution process ends and the power-on setting process ends. Further, as already described in the first embodiment, "00H" is set in the D register 106a in the line number "1002" of the power-on setting process (FIG. 17). Therefore, the random number maximum value setting process (step S119) can be started in a state where the address “0019H” of the jackpot type maximum value counter CN2 is stored in the DE register 106.

In the random number maximum value setting process (FIG. 84 (b)) in the present embodiment, the maximum value counter CN2 for the jackpot type, which is set to the address of "0019H" in the work area 121 for specific control, is set to the address of "001AH". Maximum value counter CN3 for reach that is set, maximum value counter CN5 for variation type that is set to the address of "001BH", maximum value counter CN6 for general electric that is set to the address of "001CH", "001DH" ~ Set among the maximum value counter CN1 for hits set at the address of "001EH" and the maximum value counter CN4 for initial values set at the addresses of "001FH" to "0020H" (see FIG. 12 (b)). The address of the maximum value counter selected as the target counter is set in the DE register 106. As described above, in the random number maximum value setting process (FIG. 84 (b)), the DE register 106 stores the address “0019H” of the maximum value counter CN2 for the jackpot type, that is, the jackpot type as the setting target counter. It is started with the maximum value counter CN2 set. Therefore, at the start of the random number maximum value setting process, it is possible to omit the process of setting "0019H" in the DE register 106 in order to set the jackpot type maximum value counter CN2 as the setting target counter. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

Next, the random number maximum value setting process executed by the main CPU 63 will be described with reference to the flowchart of FIG. 84 (b). As already described in the first embodiment, the random number maximum value setting process is executed in step S119 of the main process (FIG. 15). The random number maximum value setting process is executed by using the program for specific control and the data for specific control.

In the random number maximum value setting process, first, the command "LDT HL, 200H" is executed (step) in the same manner as the line number "1301" in the maximum value setting start process (FIG. 24 (b)) in the first embodiment. S3101). "LDT" is an LDT instruction by the LDT execution circuit 149, "HL" is a content that specifies the HL register 107 as a transfer destination, and "200H" sets 12-bit numerical information of "200H" as a transfer source. The content. As already described in the first embodiment, the TP register 111 is set with "9000H", which is the reference address of the data table, in step S104 of the main process (FIG. 15). Therefore, by executing "LDT HL, 200H", "9000H" obtained by adding "9000H" set in the TP register 111 to "200H" set as the "transfer source" is added to "9200H". Is loaded into the HL register 107. As a result, the start address of the random number maximum value table 64p (FIG. 23 (a)) can be set in the HL register 107.

In this way, by using the LDT instruction to set the start address of the random number maximum value table 64p in the HL register 107, the LD instruction is used to set the start address of the random number maximum value table 64p in the HL register 107. Compared with the configuration to be set, the data capacity of the program for executing the maximum value setting start process can be reduced.

After that, in steps S3102 to S3103, the same processes as in steps S302 to S303 of the random number maximum value setting process (FIG. 23 (b)) in the first embodiment are executed. Specifically, first, the instruction "LD A, (HL +)" is executed (step S3102). "LD" is an LD update instruction by the LD update execution circuit 151, "A" is a content for designating the A register 104b as a transfer destination, and "(HL +)" is stored in the HL register 107 as a transfer source. The content specifies the maximum value data stored in the area corresponding to the address, and after loading the maximum value data, the value of the HL register 107 is added by 1 to update the address stored in the HL register 107. It is the content to instruct to do. By executing "LD A, (HL +)", the maximum value data ("63H") corresponding to the address data ("9200H") stored in the HL register 107 is loaded into the A register 104b. As a result, the maximum value data to be set can be set in the A register 104b. Further, after loading the maximum value data, "1" is added to the value of the HL register 107, and the address stored in the HL register 107 is updated to "9201H". As a result, the maximum value data to be set can be updated.

In this way, by using the LD update instruction, the process of loading the maximum value data selected as the setting target in the random number maximum value table 64p into the A register 104b, and the process of loading the maximum value data into the HL register 107. The process of adding 1 to the value and updating the address stored in the HL register 107 can be executed with one instruction. Therefore, the data capacity of the program for executing the random number maximum value setting process can be reduced as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes.

The processes of steps S3102 to S3105 are repeatedly executed until an affirmative determination is made in step S3103 described later. Every time the process of step S3102 is executed, the maximum value data of the jackpot type counter C2 → the maximum value data of the reach random number counter C3 → the maximum value data of the variation type counter C5 → the maximum value data of the general electric random number counter C6 → the winning random number. Lower 1 byte of the maximum value data of the counter C1 → Higher 1 byte of the maximum value data of the winning random number counter C1 → Lower 1 byte of the maximum value data of the random number initial value counter C4 → Upper 1 of the maximum value data of the random number initial value counter C4 The maximum value data to be set is updated in the order of bytes. Further, when the process of step S3102 is executed with the address stored in the HL register 107 updated to "9208H", the end data ("00H") is set in the A register 104b.

After executing the process of step S3102, it is determined whether or not the end data (“00H”) is set in the A register 104b (step S3103), and the end data is set in the A register 104b. In (step S3103: YES), the random number maximum value setting process (FIG. 84 (b)) is terminated.

If a negative determination is made in step S3103, the instruction "LD (DE), A" is executed (step S3104). "LD" is a load instruction, "(DE)" is a content that specifies a setting target counter corresponding to an address stored in the DE register 106 as a transfer destination, and "A" is an A register 104b as a transfer source. Is the content to specify. By executing "LD (DE), A", the maximum value data stored in the A register 104b is loaded into the maximum value counter selected as the setting target counter among the maximum value counters CN1 to CN6. .. As a result, the maximum value data can be set in the setting target counter.

After that, the setting target update process is executed (step S3105). In the setting target update process, the instruction "INC DE" is executed. "INC" is an instruction to add "1" to the addition target, and "DE" is a content to specify the value of the DE register 106 as the addition target. When "INC DE" is executed, "1" is added to the value of the DE register 106. As a result, the maximum value counters CN1 to CN6 selected as the setting target counters are updated. Every time the setting target update process is executed in step S3105, the maximum value counter for jackpot type CN2 → maximum value counter for reach CN3 → maximum value counter for variable type CN5 → maximum value counter for general electric power CN6 → maximum value for hit The setting target counter is updated in the order of the lower area of the counter CN1 → the upper area of the hit maximum value counter CN1 → the lower area of the initial value maximum value counter CN4 → the upper area of the initial value maximum value counter CN4.

After executing the setting target update process in step S3105, the process returns to step S3102, and the process of steps S3102 to S3105 is repeated until the end data is stored in the A register 104b and an affirmative determination is made in step S3103. Run. Thereby, the maximum value data can be set in the maximum value counters CN1 to CN6.

According to the present embodiment described in detail above, the following excellent effects are obtained.

In the random number maximum value setting process (FIG. 84 (b)), the address of the maximum value counter selected as the setting target counter among the six maximum value counters CN1 to CN6 set in the work area 121 for specific control is It is set in the DE register 106. In the second initialization table 64β, “19H”, which is the lower 1 byte of the address of the jackpot type maximum value counter CN2, is set as the end data of the data setting execution process (FIG. 20 (c)). The power-on setting process is performed in the state where the address "0019H" of the jackpot type maximum value counter CN2 is stored in the DE register 106, that is, the jackpot type maximum value counter CN2 is set as the setting target counter. Upon completion, the random number maximum value setting process is started. Therefore, at the start of the random number maximum value setting process, it is possible to omit the process of setting "0019H" in the DE register 106 in order to set the jackpot type maximum value counter CN2 as the setting target counter. As a result, the data capacity of the program for executing the random number maximum value setting process can be reduced.

<Sixth Embodiment>
This embodiment differs from the first embodiment in that the special LDB instruction is executed by the main MPU 62. Hereinafter, a configuration different from that of the first embodiment will be described. The description of the same configuration as that of the first embodiment is basically omitted.

In the present embodiment, in order to acquire the start addresses SA0 to SA6 corresponding to the value of the special figure special electric counter in the work area 121 for specific control in the HL register 107, the address acquisition execution process (FIG. 88) described later is step S3208. The special LDB instruction "LDB HL, (HL) .A" is executed at. FIG. 85A is an explanatory diagram for explaining the configuration of the main MPU 62 in the present embodiment. As shown in FIG. 85A, the main MPU 62 includes a special LDB execution circuit 201 which is a dedicated circuit for executing a special LDB instruction, and the main CPU 63 can execute the special LDB instruction.

In the special LDB instruction, the acquisition start address is calculated using the data of the upper 12 bits (4th to 15th bits) of the 2-byte acquisition data designation data, and the lower 4 bits of the acquisition data designation data. The acquisition start bit is calculated using the data (0th to 3rd bits).

The instruction code of the special LDB instruction has a configuration of "LDB transfer destination, acquisition data designation. Acquisition bit number designation", similarly to the instruction code of the LDB instruction in the first embodiment. In the special LDB instruction, a pair register is set as the "forwarding destination". The pair register set as the "forwarding destination" in the special LDB instruction is the HL register 107. The WA register 104, the BC register 105, or the DE register 106 may be set as the "transfer destination" pair register in the LDB instruction.

In the special LDB instruction, data having any number of bits 1 to 16 is loaded into the HL register 107 of the “transfer destination”. When data having any number of bits 1 to 15 is loaded into the "transfer destination" HL register 107, the data is loaded into the lower bit in the HL register 107 and the upper bit in the HL register 107. The bit on the side is masked with "0". For example, when 12-bit data is loaded into the "transfer destination" HL register 107, the data is loaded into the 0th to 11th bits existing on the lower side of the HL register 107, and the data is loaded on the upper side. The existing 12th to 15th bits are masked with "0".

In the special LDB instruction, "(HL)" is set as "acquisition data designation". In the special LDB instruction, the data is transferred to the "transfer destination" register based on the 2-byte data (hereinafter referred to as "acquired data specified data") stored in the HL register 107 set as "acquired data specification". The data acquisition start address and acquisition start bit are specified.

In the special LDB instruction, a general-purpose register in which any numerical value of "0" to "15" is stored is set as "designation of the number of acquired bits". The general-purpose register set as "specify the number of acquired bits" in the special LDB instruction is the A register 104b. In the special LDB instruction, the B register 105a, the C register 105b, the D register 106a, or the E register 106b may be set as the general-purpose register for "specifying the number of acquired bits".

The "acquisition bit number designation" is data for designating the number of bits of data to be loaded in the HL register 107 of the "transfer destination" (acquisition bit number designation data). In the special LDB instruction, the operation of adding "1" to the value of the A register 104b set in the "designation of the number of acquired bits" in the special LDB execution circuit 201 is performed, and the number of bits corresponding to the operation result is calculated. The data is loaded into the "destination". That is, the data of the number of bits corresponding to the value obtained by adding "1" to the "designation of the number of acquired bits" is loaded in the "transfer destination". Therefore, a value obtained by subtracting "1" from the number of bits of data to be loaded in the "transfer destination" is set in the "specified number of acquired bits". Specifically, when the A register 104b in which the numerical value "11" is stored is set as the "specified number of acquired bits", "1" is added to the "11" in the "transfer destination" register. The 12-bit data obtained by the above is loaded.

When the special LDB instruction is executed, the data of the bit number corresponding to the "acquisition bit number specification" is loaded into the "transfer destination" register from the acquisition start bit of the area corresponding to the acquisition start address in the main ROM 64. To.

85 (b) to 85 (e) are explanatory diagrams for explaining the process of calculating the acquisition start address and the acquisition start bit from the acquisition data designated data. As described above, the upper 12 bits (4th to 15th bits) of the 2-byte acquisition data designation data are data for designating the acquisition start address, and the lower 4 bits (0th to 3rd bits) are. This is the data for specifying the acquisition start bit. The acquisition start address is the reference address (9000H) of the data table stored in the TP register 111 with respect to the data (quotient data after division) obtained by dividing the acquired data specified data by "16" (10000H). It is an address obtained by adding. As already described in the first embodiment, "9000H" is set as the reference address of the data table in the TP register 111. "16" (10000H) used for division of acquired data specified data is a numerical range ("0") represented by the number of bits ("4") of the data for designating the acquisition start bit among the acquired data specified data. "15"), which is the maximum value of "15" plus "1", which is the fourth power of "2". As described above in the first embodiment, when a 2-byte binary number is divided by the nth power of "2" (n is an integer of 1 to 15), the nth bit in the 2-byte binary number is obtained. The information of "0" or "1" set in the 15th bit is shifted to the lower side of n bits and set in the lower (16-n) bits in the quotient data after division, and after the division. "0" is set in the upper n bits ((16-n) bits to 15th bits) in the quotient data. In the LDB instruction in the present embodiment, the acquired data designation data, which is a 2-byte binary number, is divided by "16" (10000H), which is the fourth power of "2". When the acquired data specified data is divided by "16", the information of "0" or "1" set in the 4th to 15th bits of the acquired data specified data is shifted to the lower side of 4 bits and after the division. The lower 12 bits (12th to 11th bits) in the quotient data are set, and "0" is set in the upper 4 bits (12th to 15th bits) in the quotient data after the division.

Specifically, as shown in FIG. 85B, a case where “180CH” is set as the acquired data designation data will be described. As shown in FIG. 85 (c), "16" (10000H) is a value obtained by adding "1" to "15", which is the maximum value of the numerical range ("0" to "15") represented by 4 bits. ) Divides the acquired data specified data (“180CH”), and “00011000000” set in the 4th to 15th bits of the acquired data specified data shifts to the lower side by 4 bits in the divided quotient data. The lower 12 bits (0th to 11th bits) are set, and "0" is set in the upper 4 bits (12th to 15th bits) in the quotient data after the division. As a result, as shown in FIG. 85 (c), the quotient data after division becomes "000000011000000". After that, by adding the reference address (“9000H”) of the data table stored in the TP register 111 to the quotient data after the division, the acquisition start address (“9180H”) is added as shown in FIG. 85 (d). ") Is calculated. The 4th to 15th bits of the acquisition data designation data (FIG. 85 (b)) are set in the 0th to 11th bits of the acquisition start address, and the 12th to 15th bits of the acquisition start address are set. Is set to "1001B" ("9H"), which is the data of the 12th to 15th bits at the reference address of the data table.

As described above, in the special LDB instruction, the data of the 4th to 15th bits of the acquisition data designation data is set in the 1st to 11th bits of the acquisition start address, and the 12th to 15th bits of the acquisition start address are set. The 12th to 15th bit data at the reference address of the data table stored in the TP register 111 is set.

The acquisition start bit is calculated by the operation of the logical product of the lower 1 byte of the acquired data designated data and "000011111B" ("0FH"). The "00001111B" used in the calculation for calculating the acquisition start bit separates only the lower 4 bits (0th to 3rd bits) of the acquired data specified data from the 2-byte acquisition data specified data. It is the data to make it available. In the calculation of the logical product of the lower 1 byte of the acquired data specified data and "000011111B", the lower 4 bits (0th to 3rd bits) of the acquired data specified data are the lower 4 bits (0th to 3rd bits) of the operation result. 3 bits), and "0" is set in the upper 4 bits (4th to 7th bits) of the calculation result. Specifically, as shown in FIG. 85B, when "180CH" is set as the acquisition data designation data, the lower 1 byte of the acquisition data designation data is "000001100B" ("0CH"). In this case, the acquisition start bit calculated by the operation of the logical product of the lower 1 byte of the acquired data designated data and "000011111B" is "00001100B" ("12") as shown in FIG. 85 (e). .. The data of the 0th to 3rd bits in the acquisition data designation data (FIG. 85 (b)) is set in the 0th to 3rd bits of the acquisition start bit, and the 4th to 7th bits of the acquisition start bit are set. Is set to "0".

No data is set in the instruction code of the special LDB instruction to specify that "00001111B" is used in the operation for calculating the acquisition start bit. The operation of the logical product of the lower 1 byte of the acquired data designated data and "00001111B" is automatically executed by the special LDB execution circuit 201 when the special LDB instruction set in the program is executed. Therefore, the instruction of the special LDB instruction is compared with the configuration in which it is necessary to set the data for designating that "000011111B" is used in the operation for calculating the acquisition start bit in the instruction code of the special LDB instruction. The data capacity of the code can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

The acquisition start bit in the special LDB instruction is an integer of any of "0" to "15". First, a case where the acquisition start bit is an integer of any of "0" to "7" will be described. When the acquisition start bit is "n" (n is an integer of 0 to 7), the nth and subsequent bits (nth bit) of the 0th to 7th bits of the area corresponding to the acquisition start address in the main ROM 64 The data of "0" or "1" for the number of acquired bits set in (7th bit) is transferred to the HL register 107 of the "transfer destination". When the number of "0" or "1" data existing after the acquisition start bit (nth bit to 7th bit) in the area corresponding to the acquisition start address is less than the number of acquisition bits this time. , The data after the acquisition start bit at the acquisition start address (data in the nth to 7th bits at the acquisition start address) and the data after the 0th bit at the address next to the acquisition start address are "transfer destinations". Loaded into. Here, the address next to the acquisition start address is an address obtained by adding "1" to the acquisition start address.

For example, "9000H" is stored in the TP register 111 as a reference address, "1800H" ("6144") is stored in the HL register 107 as acquisition data designation data, and the acquisition bit number designation data is stored in the A register 104b. When the special LDB instruction "LDB HL, (HL) .A" is executed in the state where "BH" (11) is stored, the "transfer destination" is the HL register 107. As already explained, the data for specifying the acquisition start address is set in the upper 12 bits of the acquisition data specification data, and the data for specifying the acquisition start bit is in the lower 4 bits of the acquisition data specification data. It is set. The acquisition start address is "9180H" obtained by adding the reference address ("9000H") to "0180H" ("384") obtained by dividing the acquisition data designated data by "16". As the acquisition start bit, the lower 4 bits of the acquisition data designated data are extracted and become "0000000000B" ("0"). As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte (“0000000000B”) of the acquired data designated data and “000000111H”. The number of acquired bits is "0CH" ("12") obtained by adding "1" to "0BH". Therefore, when the special LDB instruction "LDB HL, (HL) .A" is executed in this state, the area corresponding to the acquisition start address "9180H" (see FIG. 31) in the main ROM 64. It is set after the 0th bit in the area corresponding to the 8-bit data set after the acquisition start bit (0th bit) and "9181H" which is the next address of the acquisition start address. The 4-bit data and the HL register 107, which is the transfer destination, are set to the 0th to 11th bits, and the 12th to 15th bits of the HL register 107 are masked with "0". Specifically, the data of the 0th to 7th bits of the area corresponding to "9180H" and the data of the 0th to 3rd bits of the area corresponding to "9181H" are set to the 0th to 11th bits of the HL register 107. Set.

Next, a case where the acquisition start bit is an integer of any of "8" to "15" will be described. When the acquisition start bit is "m" (m is an integer of 8 to 15), the third (m-8) of the 0th to 7th bits in the area corresponding to the address next to the acquisition start address in the main ROM 64. ) The data of "0" or "1" for the number of acquired bits set in the bits and after (the (m-8) bits to the 7th bit) is transferred to the HL register 107 of the "transfer destination". As described above, the address next to the acquisition start address is an address obtained by adding "1" to the acquisition start address. The number of "0" or "1" data existing in the (m-8) th and subsequent bits ((m-8) bits to the 7th bit) in the area corresponding to the address next to the acquisition start address. If is less than the number of acquired bits this time, the data after the (m-8)th bit at the address next to the acquisition start address (the (m-8) bits to the third bit at the address next to the acquisition start address). The 7-bit data) and the data after the 0th bit at the address next to the acquisition start address are loaded into the "transfer destination". Here, the address next to the acquisition start address is an address obtained by adding "2" to the acquisition start address.

For example, "9000H" is stored in the TP register 111 as a reference address, "180CH" ("6156") is stored in the HL register 107 as acquisition data designation data, and the acquisition bit number designation data is stored in the A register 104b. When the special LDB instruction "LDB HL, (HL) .A" is executed in the state where "BH" (11) is stored, the "transfer destination" is the HL register 107. As already explained, the data for specifying the acquisition start address is set in the upper 12 bits of the acquisition data specification data, and the data for specifying the acquisition start bit is in the lower 4 bits of the acquisition data specification data. It is set. The acquisition start address is "9180H" obtained by adding the reference address ("9000H") to "0180H" ("384") obtained by dividing the acquisition data designated data by "16". As the acquisition start bit, the lower 4 bits of the acquisition data designated data are extracted and become "000001100B" ("12"). As described above, the acquisition start bit is calculated by the operation of the logical product of the lower 1 byte (“000001100B”) of the acquired data designated data and “000011111H”. The number of acquired bits is "0CH" ("12") obtained by adding "1" to "0BH". The acquisition start bit is "12", which exceeds "7". Therefore, when the special LDB instruction "LDB HL, (HL) .A" is executed in this state, the address "9181H" (9181H) next to the acquisition start address "9180H" in the main ROM 64. (See FIG. 31), the 4-bit data set after the (12-8) bit (fourth bit) in the area corresponding to the acquisition start address, and "9182H" which is the next address after the acquisition start address. The 8-bit data set after the 0th bit in the area corresponding to is set to the 0th to 11th bits of the HL register 107 which is the transfer destination, and the 12th to 11th bits of the HL register 107 are set. The 15th bit is masked with "0". Specifically, the data of the 4th to 7th bits of the area corresponding to "9181H" and the data of the 0th to 7th bits of the area corresponding to "9182H" are set to the 0th to 11th bits of the HL register 107. Set.

FIGS. 86 (a) and 86 (b) are explanatory diagrams for explaining how the start address SA1 is acquired from the special figure special electric address table 64q to the HL register 107. As already described in the first embodiment, in the special figure special electric address table 64q (FIG. 31), the start address SA1 is set in the 4th to 7th bits of "9181H" and the 0th to 7th bits of "9182H". The lower 12 bits of are set. By executing "LDB HL, (HL) .A", as shown in FIG. 86 (a), the lower 12 bits of the start address SA1 are loaded into the lower 12 bits of the HL register 107. In the address acquisition execution process (FIG. 88) described later, after executing the LDB instruction, "9000H", which is the reference address of the data table, is added to the value of the HL register 107. As a result, as shown in FIG. 86 (b), the entire start address SA1 can be acquired in the HL register 107.

By using the special LDB instruction, the process of specifying the acquisition start address corresponding to the 4th to 15th bits of the 2-byte acquisition data designation data, and the lower 4 bits (0th to 3rd bits) of the acquisition designation data. ), The process of specifying the acquisition start bit, the process of loading the data for the number of acquisition bits from the acquisition start bit of the acquisition start address into the "transfer destination" register, and the "transfer destination" register. It is possible to execute the process of masking the bits existing on the upper side of the loaded data with "0" with one instruction. These processes are executed by the special LDB execution circuit 201. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

Next, the program contents of the special figure special electric address acquisition process executed by the main CPU 63 will be described with reference to the explanatory diagram of FIG. 86 (c). As already described in the first embodiment, the special figure special electric address acquisition process is executed in step S902 of the special figure special electric control process (FIG. 30). As shown in FIG. 86 (c), "3001" to "3005" are set as line numbers in this program. The instructions of the program are executed in the order from the smallest line number to the larger line number, except when a call instruction or a jump instruction is executed.

In the line numbers of "3001" to "3002", the same commands as "1601" to "1602" of the special figure special electric address acquisition process (FIG. 33 (a)) in the first embodiment are set. .. Specifically, the command "LD W, (TZTDCNT)" is set in the line number of "3001". “LD” is an LD instruction, and “W” is a content that specifies the W register 104a as a transfer destination. As already described in the first embodiment, "TZTDNTT" is the address of the special figure special electric counter in the work area 121 for specific control, and "(TZTDCNT)" is the data stored in the special figure special electric counter. It is the content to be transferred to the "transfer destination". Similar to the first embodiment, the special figure special electric counter stores numerical data of any one of 0 to 6. By executing "LD W, (TZTDCNT)", the data (1 byte) of the special figure special electric counter is loaded into the W register 104a of the "transfer destination".

An instruction "LD B, 0CH" is set in the line number of "3002". "LD" is an LD instruction, "B" is a content that specifies the B register 105a as a transfer destination, and "0CH" is a content that specifies numerical data of "0CH" ("12") as a "transfer source". Is. “0CH” is the number of bits of the address data acquired from the special figure special electric address table 64q in the address acquisition execution process (FIG. 88) described later. By executing "LD B, 0CH", the number of bits ("12") of the address data acquired from the special figure special electric address table 64q is set in the B register 105a of the "transfer destination".

The command "LD HL, TBL_TZTD2_B" is set in the line number of "3003". “LD” is an LD instruction, and “HL” is a content that specifies the HL register 107 as a transfer destination. "TBL_TZTD2_B" is 2-byte numerical data for using the acquisition start address as the start address of the special figure special electric address table 64q, and is specifically "1800H". By executing "LD HL, TBL_TZTD2_B", "1800H" is loaded into the HL register 107 of the "transfer destination".

"TBL_TZTD2_B" is calculated by the formula "{(start address of special figure special electric address table 64q) -9000H} x 16". FIGS. 86 (d) to 86 (f) are explanatory diagrams for explaining a process of calculating "TBL_TZTD2_B". When "9000H", which is the reference address of the data table, is subtracted from "9180H" (FIG. 86 (d)), which is the start address of the special figure special electric address table 64q, the subtracted data is shown in FIG. 86 (e). The data of the 0th to 11th bits at the start address "9180H" (FIG. 86 (d)) is set in the 0th to 11th bits in the above. Then, when the subtracted data is multiplied by "16" (10000H), "TBL_TZTD2_B" is calculated as shown in FIG. 86 (f). "16" used for the multiplication for calculating "TBL_TZTD2_B" is a numerical range ("4") represented by the number of bits ("4") of the data for designating the acquisition start bit among the acquisition data designation data. It is a value obtained by adding "1" to "15" which is the maximum value of "0" to "15"). As described above in the first embodiment, when a 2-byte binary number is multiplied by the nth power of "2" (n is an integer of 1 to 15), the 0th bit in the 2-byte binary number is obtained. The information of "0" or "1" set in the (15-n) th bit is shifted to the upper side of the n bits and set in the upper (16-n) bit in the multiplied data, and the relevant bit is set. "0" is set in the lower n bits (0th bit to (n-1) bit) of the data after multiplication.

In the calculation of "TBL_TZTD2_B", the value obtained by subtracting "9000H", which is the reference address of the data table, from the start address of the special electric address table 64q (data after subtraction) is the fourth power of "2", "16". Is multiplied. As a result, the data of the 0th to 12th bits in the data after subtraction (FIG. 86 (e)) is shifted to the upper side by 4 bits, and the upper 12 bits (fourth) in the data after multiplication (FIG. 86 (f)). ~ 15th bit) is set, and "0" is set in the lower 4 bits (0th bit to 3rd bit) of the data after the multiplication. As shown in FIG. 86 (f), the start address "9180H" (FIG. 86 (d)) is assigned to the 4th to 15th bits in "TBL_TZTD2_B" which is the data after multiplication by "16" (data after multiplication). )), The data of the 0th to 11th bits is set. As described above, in the special LDB instruction, the acquisition start address is calculated by adding "9000H", which is the reference address of the data table, to the value obtained by dividing the acquired data designation data by "16" (10000H). .. Further, as already explained, the acquisition data designation data is divided by "16" in the process of calculating the acquisition start address in the special LDB instruction, so that the upper 12 bits (4th to 15th bits) in the acquisition data designation data are obtained. The data set in is shifted to the lower side by 4 bits. When the special LDB instruction is executed with "TBL_TZTD2_B" derived by shifting the data of the 0th to 12th bits in the subtracted data (FIG. 86 (e)) to the upper side by 4 bits as the acquisition data designation data. In the process of calculating the acquisition start address, "TBL_TZTD2_B" is divided by "16". In the quotient data after division, the data of the 0th to 12th bits in the data after subtraction, which has been shifted to the upper side of 4 bits, is shifted to the lower side of 4 bits. Then, the start address of the special figure special electric address table 64q is calculated as the acquisition start address by the calculation of adding "9000H" which is the reference address of the data table to the quotient data after the division.

In this way, "TBL_TZTD2_B" calculated by the formula "{(start address of special figure special electric address table 64q) -9000H} x 16" starts to acquire the start address of special figure special electric address table 64q in the special LDB instruction. Acquired data specified data to be used as an address. By setting "TBL_TZTD2_B" as the acquisition data designation data, the start address of the special figure special electric address table 64q can be set as the acquisition start address of the special LDB instruction.

In the address acquisition execution process (FIG. 88) described later, when the value of the special figure special electric counter is "0", "1800H" stored in the HL register 107 is used as the acquisition data designation data. On the other hand, when the value of the special figure special electric counter is "1" or more, the numerical information stored in the HL register 107 is the numerical information corresponding to the value of the special figure special electric counter before the special LDB instruction is executed. Will be changed to.

The command "CALLS LDBADGET20" is set in the line number of "3004" in the special figure special electric address acquisition process (FIG. 86 (c)). “LDBADGET20” is an address acquisition execution process (FIG. 88) described later. The instruction "CALLS LDBADGET20" is an instruction for calling a subroutine called an address acquisition execution process. Although the details will be described later, the start address (any of SA0 to SA6) corresponding to the value of the special figure special electric counter is set in the HL register 107 by executing the address acquisition execution process at the line number "3004". To. When the subroutine of the address acquisition execution process is completed, the process proceeds to the line number of "3005".

An instruction "RET" is set in the line number of "3005". As already described in the first embodiment, the special figure special electric address acquisition process is a subroutine executed in step S902 of the special figure special electric control process (FIG. 30). Therefore, by executing the command "RET", the process proceeds to step S903 of the special figure special electric control process (FIG. 30).

Next, prior to the explanation of the address acquisition execution process (FIG. 88), a mode of acquiring the lower 12-bit data of the start addresses SA0 to SA6 corresponding to the value of the special figure special electric counter from the special figure special electric address table 64q will be described. .. FIG. 87 is an explanatory diagram for explaining the correspondence between the value of the special figure special electric counter and the start addresses SA0 to SA6 acquired in the HL register 107.

As already described with reference to FIG. 31 in the first embodiment, the special figure special electric address table 64q is stored in the address range of "9180H" to "918AH" in the main ROM 64, and the special figure special electric power is stored in the address range. In the address table 64q, the data of the lower 12 bits in the start addresses SA0 to SA6 corresponding to the value of the special figure special electric counter is set.

As described above, "1800H" is stored in the HL register 107 at the line number "3003" of the special figure special electric address acquisition process (FIG. 86 (c)). As shown in FIG. 87, when the value of the special figure special electric counter is “0”, the special LDB instruction is executed with the “1800H” as the acquisition data designation data. In the special figure special electric address table 64q, the data of the lower 12 bits of the start address SA0 corresponding to the value of "0" of the special figure special electric counter is the 0th to 7th bits of "9180H" and the 0th to 0th of "9181H". It is set to the third bit. The data of the lower 12 bits of the start address SA0 is set to a position that can be acquired by setting the 0th bit of the area corresponding to "9180H" as the acquisition start position and setting the number of acquisition bits to "12". .. The data of the lower 12 bits of the start address SA0 has the acquisition start address in the special LDB instruction (“LDB HL, (HL) .A”) executed in step S3208 of the address acquisition execution process (FIG. 88) described later. It is acquired when it becomes "9180H" and the acquisition start bit becomes "0".

In the special figure special electric address table 64q, the lower 12-bit data of the start addresses SA1 to SA6 corresponding to the values of "1" to "6" of the special figure special electric counter has the value of the special figure special electric counter "0". Based on the acquisition start position (the 0th bit of the area corresponding to "9180H"), the acquisition start position is shifted to the rear by the "(number of acquisition bits) x (value of the special electric power counter)" bit. It is set to a position where it can be acquired. In the present embodiment, the "rear side" as the direction for shifting the acquisition start position is the direction in which the acquisition start bit th increases (the direction from the 0th bit to the 7th bit) and the direction in which the acquisition start address increases. (Direction from "9180H" to "918AH").

As shown in FIG. 31, the data of the lower 12 bits of the start address SA1 corresponding to the value of “1” of the special figure special electric counter are the 4th to 7th bits of “9181H” and the 0th to 7th bits of “9182H”. It is set to 7 bits. For the data of the lower 12 bits of the start address SA1, the acquisition start position is set to only "number of acquisition bits x 1" bits (12 bits) with reference to the acquisition start position when the value of the special electric power counter is "0". It is set to a position that can be acquired by shifting it to the rear side. For the data of the lower 12 bits of the start address SA1, the acquisition start position is set to the 4th bit of the area corresponding to the address next to "9180H" ("9181H"), and the number of acquisition bits is set to "12". It is set to a position where it can be acquired. As shown in FIG. 87, the data of the lower 12 bits of the start address SA1 is a special LDB instruction (“LDB HL, (HL) .A” executed in step S3208 of the address acquisition execution process (FIG. 88) described later. ), The acquisition start address becomes "9180H" and the acquisition start bit becomes "12".

As shown in FIG. 31, the data of the lower 12 bits of the start address SA2 corresponding to the value of "2" of the special figure special electric counter are the 0th to 7th bits of "9183H" and the 0th to 7th bits of "9184H". It is set to 3 bits. For the data of the lower 12 bits of the start address SA2, the acquisition start position is set to "the number of acquisition bits x 2" bits (24 bits) based on the acquisition start position when the value of the special electric power counter is "0". It is set to a position that can be acquired by shifting it to the rear side. For the data of the lower 12 bits of the start address SA2, the 0th bit of the area corresponding to the address next to "9182H" ("9183H") is set as the acquisition start position, and the number of acquisition bits is set to "12". It is set to a position where it can be acquired. As shown in FIG. 87, the data of the lower 12 bits of the start address SA2 is a special LDB instruction (“LDB HL, (HL) .A” executed in step S3208 of the address acquisition execution process (FIG. 88) described later. ), The acquisition start address becomes "9182H" and the acquisition start bit becomes "8".

As shown in FIG. 31, the data of the lower 12 bits of the start address SA3 corresponding to the value of “3” of the special figure special electric counter are the 4th to 7th bits of “9184H” and the 0th to 7th bits of “9185H”. It is set to 7 bits. For the data of the lower 12 bits of the start address SA3, the acquisition start position is set to "the number of acquisition bits x 3" bits (36 bits) based on the acquisition start position when the value of the special electric power counter is "0". It is set to a position that can be acquired by shifting it to the rear side. The data of the lower 12 bits of the start address SA3 is set to a position that can be acquired by setting the fourth bit of the area corresponding to "9184H" as the acquisition start position and setting the number of acquisition bits to "12". .. As shown in FIG. 87, the data of the lower 12 bits of the start address SA3 is a special LDB instruction (“LDB HL, (HL) .A” executed in step S3208 of the address acquisition execution process (FIG. 88) described later. ), The acquisition start address becomes "9184H" and the acquisition start bit becomes "4".

As shown in FIG. 31, the data of the lower 12 bits of the start address SA4 corresponding to the value of "4" of the special figure special electric counter are the 0th to 7th bits of "9186H" and the 0th to 7th bits of "9187H". It is set to 4 bits. For the data of the lower 12 bits of the start address SA4, the acquisition start position is set to "the number of acquisition bits x 4" bits (48 bits) based on the acquisition start position when the value of the special electric power counter is "0". It is set to a position that can be acquired by shifting it to the rear side. The data of the lower 12 bits of the start address SA4 is set to a position that can be acquired by setting the 0th bit of the area corresponding to "9186H" as the acquisition start position and setting the number of acquisition bits to "12". .. As shown in FIG. 87, the data of the lower 12 bits of the start address SA4 is a special LDB instruction (“LDB HL, (HL) .A” executed in step S3208 of the address acquisition execution process (FIG. 88) described later. ), The acquisition start address becomes "9186H" and the acquisition start bit becomes "0".

As shown in FIG. 31, the data of the lower 12 bits of the start address SA5 corresponding to the value of “5” of the special figure special electric counter are the 4th to 7th bits of “9187H” and the 0th to 7th bits of “9188H”. It is set to 7 bits. For the data of the lower 12 bits of the start address SA5, the acquisition start position is set to "the number of acquisition bits x 5" bits (60 bits) based on the acquisition start position when the value of the special electric power counter is "0". It is set to a position that can be acquired by shifting it to the rear side. For the data of the lower 12 bits of the start address SA5, the acquisition start position is set to the 4th bit of the area corresponding to the address next to "9186H" ("9187H"), and the number of acquisition bits is set to "12". It is set to a position where it can be acquired. As shown in FIG. 87, the data of the lower 12 bits of the start address SA5 is a special LDB instruction (“LDB HL, (HL) .A” executed in step S3208 of the address acquisition execution process (FIG. 88) described later. ), The acquisition start address becomes "9186H" and the acquisition start bit becomes "12".

As shown in FIG. 31, the data of the lower 12 bits of the start address SA6 corresponding to the value of “6” of the special figure special electric counter is the 0th to 7th bits of “9189H” and the 0th to 7th bits of “918AH”. It is set to 4 bits. For the data of the lower 12 bits of the start address SA6, the acquisition start position is set to "the number of acquisition bits x 6" bits (72 bits) based on the acquisition start position when the value of the special electric power counter is "0". It is set to a position that can be acquired by shifting it to the rear side. For the data of the lower 12 bits of the start address SA6, the 0th bit of the area corresponding to the address next to "9188H" ("9189H") is set as the acquisition start position, and the number of acquisition bits is set to "12". It is set to a position where it can be acquired. As shown in FIG. 87, the data of the lower 12 bits of the start address SA6 is a special LDB instruction (“LDB HL, (HL) .A” executed in step S3208 of the address acquisition execution process (FIG. 88) described later. ), The acquisition start address becomes "9188H" and the acquisition start bit becomes "8".

Next, the address acquisition execution process executed by the main CPU 63 will be described with reference to the flowchart of FIG. The address acquisition execution process is executed by the line number "3004" of the special figure special electric address acquisition process (FIG. 86 (c)). The address acquisition execution process is executed by using the program for specific control and the data for specific control.

As described above, in the line number "3003" of the special figure special electric address acquisition process (FIG. 86 (c)), the acquisition data designation data ("0" corresponding to the value of "0" in the special figure special electric counter is stored in the HL register 107. 1800H ") is stored. The processes of steps S3201 to S3205 are executed to change the acquired data designation data stored in the HL register 107 to the data corresponding to the value of the special figure special electric counter.

In steps S3201 to S3203 in the address acquisition execution process, the same instructions as the line numbers "1702" to "1704" of the address acquisition execution process (FIG. 33 (e)) in the first embodiment are executed. Specifically, first, the instruction "LD A, B" is executed (step S3201). “LD” is an LD instruction, “A” is a content that specifies A register 104b as a transfer destination, and “B” is a content that specifies B register 105a as a transfer source. As described above, in the special figure special electric address acquisition process (FIG. 86 (c)), "0CH" ("12") for designating the number of bits (number of acquisition bits) to be acquired from the special figure special electric address table 64q in the B register 105a. ) Is set. Therefore, by executing "LD A, B", "0CH" is set in the A register 104b of the "transfer destination".

After that, the instruction "MUL W, A" is executed (step S3202). "MUL" is an operation instruction called a MUL instruction, "W" is a content for designating the W register 104a, and "A" is a content for designating the A register 104b. By executing "MUL W, A", an operation of multiplying the value of the W register 104a and the value of the A register 104b is performed, and the result of the operation is stored in the WA register 104. As described above, in the special figure special electric address acquisition process (FIG. 86 (c)), the value of the special figure special electric counter (an integer of 0 to 6) is set in the W register 104a. Further, as described above, "0CH", which is the number of acquired bits, is stored in the A register 104b. Therefore, when "MUL W, A" is executed in step S3202, the calculation result of "(value of special figure special electric counter) × (number of acquired bits)" is stored in the WA register 104.

After that, the instruction "ADD HL, WA" is executed (step S3203). "ADD" is an operation instruction called an ADD instruction, "HL" is a content for designating an HL register 107, and "WA" is a content for designating a WA register 104. By executing "ADD HL, WA", the sum of the value of the HL register 107 and the value of the WA register 104 is stored in the HL register 107. As described above, in the line number "3003" of the special figure special electric address acquisition process (FIG. 86 (c)), the acquisition data designation data ("1800H" corresponding to the value of "0" in the special figure special electric counter is stored in the HL register 107. ") Is stored. Further, as described above, the WA register 104 stores the data of the calculation result of "(value of special figure special electric counter) x (number of acquired bits)". By executing the instruction "ADD HL, WA" in step S3203, "(special figure) is stored in the HL register 107 in which the acquired data designation data corresponding to the value of" 0 "in the special figure special electric counter is stored. The calculation result of "value of special electric counter) x (number of acquired bits)" is added. As a result, the lower 4 bits of the acquired data designated data are updated in a manner corresponding to the value of the special figure special electric counter. As described above, in the special LDB instruction, the lower 4 bits of the acquired data designation data are used to specify the acquisition start bit.

By executing the instruction "ADD HL, WA" in step S3203, the calculation result of "(number of acquired bits) x (value of special electric power counter)" stored in the WA register 104 is "16". The acquisition data designation data stored in the HL register 107 is updated in such a manner that the acquisition start address is increased by the quotient divided by. As already described in the first embodiment, in the special figure special electric address table 64q, 8-bit data is set for one address. On the other hand, in the special LDB instruction in the present embodiment, the acquisition start bit is specified in the numerical range of "0" to "15". Therefore, in the special LDB instruction, it is necessary to increase the acquisition start address by "2" every time the acquisition start bit increases by "16". In order to update the data of the upper 12 bits of the acquired data specified data stored in the HL register 107 in a manner corresponding to the value of the special figure special electric counter, "(number of acquired bits) x (value of the special figure special electric counter)". It is necessary to increase the acquisition start address by twice the quotient obtained by dividing the calculation result of ")" by "16". However, just by executing the instruction in step S3203, the acquisition start address is increased only by the quotient obtained by dividing the calculation result by "16". Therefore, by executing the processes of step S3204 and step S3205, the acquisition start address is further increased by the quotient obtained by dividing the calculation result by "16".

Specifically, first, the logical product of the value of the WA register 104 and "1111111111110000B" is calculated, and the calculation result is stored in the WA register 104, so that the 2-byte data stored in the WA register 104 is stored. The data of the lower 4 bits is changed to "0000B" (step S3204). As described above, the WA register 104 stores the calculation result of "(number of acquired bits) x (value of special figure special electric counter)". In step S3204, by changing the lower 4 bits of the calculation result stored in the WA register 104 to "0000B", the value obtained by dividing the calculation result by "16" and multiplying it by "16" is WA. It is assumed that the state is stored in the register 104.

After that, the instruction "ADD HL, WA" is executed in the same manner as in step S3203 (step S3205). As a result, the acquisition start address is stored in the HL register 107 in such a manner that the acquisition start address is increased by the quotient obtained by dividing the calculation result of "(number of acquisition bits) x (value of the special electric power counter)" by "16". The acquired data specified data is updated.

By executing the processes of steps S3201 to S3205 in this way, it corresponds to the data acquisition start position (“9180H”) when the value of the special figure special electric counter is “0” in the special figure special electric address table 64q. The acquisition start position is stored in the HL register 107 in such a manner that the acquisition start position is shifted to the rear side by "(number of acquisition bits) x (value of special electric power counter)" with reference to the 0th bit of the area to be acquired. Data specification Data can be updated. As described above, in the special figure special electric address table 64q, when the start addresses SA1 to SA6 corresponding to the values of "1" to "6" of the special figure special electric counter have the value of the special figure special electric counter "0". With reference to the data acquisition start position (the 0th bit of the area corresponding to "9180H") in It is set to a position that can be acquired by shifting it.

In steps S3206 to S3209, the same instructions as the line numbers of "1705" to "1708" in the address acquisition execution process (FIG. 33 (e)) in the first embodiment are executed. Specifically, first, as in step S3201, the instruction "LD A, B" is executed (step S3206). As described above, in the special figure special electric address acquisition process (FIG. 86 (c)), "0CH" ("12") for designating the number of acquisition bits is set in the B register 105a. Therefore, by executing "LD A, B", "0CH" is set in the A register 104b of the "transfer destination". As described above, "0CH" stored in the B register 105a was also used for the calculation of "(value of special figure special electric counter) × (number of acquired bits)". In this way, "0CH" stored in the B register 105a in advance is used for the calculation of "(value of the special electric power counter) × (number of acquired bits)" and also specifies the number of acquired bits in the LDB instruction. Is used to set the data for the A register 104b.

After that, the instruction "DEC A" is executed (step S3207). "DEC" is an operation instruction called a DEC instruction, and "A" is a content that specifies A register 104b. When "DEC A" is executed, the value of the A register 104b is decremented by 1. As described above, "0CH", which is the number of acquired bits, is stored in the A register 104b. Therefore, when "DEC A" is executed in step S3207, "0BH" is stored in the A register 104b. "0BH" is a value obtained by subtracting "1" from "12" which is the number of bits acquired from the special figure special electric address table 64q.

As described above, when the LDB instruction "LDB HL, (HL) .A" is executed, the LDB execution circuit 157 performs an operation of adding 1 to the value of the A register 104b, and the value after the 1 addition. Is used as data for the number of acquired bits. Therefore, by subtracting 1 from the value of the A register 104b in step S3207, the number of bits of the data acquired from the special figure special electric address table 64q in the LDB instruction can be set to "12".

After that, the instruction "LDB HL, (HL) .A" is executed (step S3208). "LDB" is a special LDB instruction by the special LDB execution circuit 201, "HL" before the comma is the content to specify the HL register 107 as the "transfer destination", and "(HL)" before the period is HL. The content is that the 2-byte data stored in the register 107 is specified as the acquisition data specification data, and "A" is the content that the 1-byte data stored in the A register 104b is the acquisition bit number specification data. .. As described above, the HL register 107 is in a state where the acquired data designation data corresponding to the value of the special electric power counter is stored, and the A register 104b is "1" from the number of acquired bits ("0CH"). Is stored in "0BH" obtained by subtracting. Further, the TP register 111 is in a state where the reference address "9000H" is stored. In this state, when the instruction "LDB HL, (HL) .A" is executed in step S3208, the value of the special electric power counter is set to the 0th to 11th bits of the HL register 107 which is the transfer destination. The lower 12 bits of data at the corresponding start addresses SA0 to SA6 are loaded, and the 12th to 15th bits of the HL register 107 are masked with "0".

Specifically, as shown in FIG. 87, when the value of the special figure special electric counter is "0", the acquisition start address becomes "9180H" and the acquisition start bit becomes "0", and the HL register 107 The lower 12 bits of the start address SA0, "700H", are loaded into the 0th to 11th bits. When the value of the special figure special electric counter is "1", the acquisition start address becomes "9180H" and the acquisition start bit becomes "12", and the 0th to 11th bits of the HL register 107 are lower than the start address SA1. The 12-bit "712H" is loaded. When the value of the special figure special electric counter is "2", the acquisition start address becomes "9182H" and the acquisition start bit becomes "8", and the lower bits of the start address SA2 are in the 0th to 11th bits of the HL register 107. The 12-bit "71FH" is loaded. When the value of the special figure special electric counter is "3", the acquisition start address becomes "9184H" and the acquisition start bit becomes "4", and the lower bits of the start address SA3 are in the 0th to 11th bits of the HL register 107. The 12-bit "731H" is loaded. When the value of the special figure special electric counter is "4", the acquisition start address becomes "9186H" and the acquisition start bit becomes "0", and the 0th to 11th bits of the HL register 107 are lower than the start address SA4. The 12-bit "740H" is loaded. When the value of the special figure special electric counter is "5", the acquisition start address becomes "9186H" and the acquisition start bit becomes "12", and the lower bits of the start address SA5 are in the 0th to 11th bits of the HL register 107. The 12-bit "74CH" is loaded. When the value of the special figure special electric counter is "6", the acquisition start address becomes "9188H" and the acquisition start bit becomes "8", and the lower bits of the start address SA6 are in the 0th to 11th bits of the HL register 107. The 12-bit "753H" is loaded. In this way, every time the value of the special figure special electric counter increases by 1, the data acquisition start position in the special figure special electric address table 64q is shifted to the rear side by 12 bits.

The acquisition data of 2 bytes is configured by loading the lower 12 bits of the start addresses SA0 to SA6 acquired from the special figure special electric address table 64q using the special LDB instruction into the 0th to 11th bits of the HL register 107. The process of specifying the acquisition start address corresponding to the 4th to 15th bits of the specified data, the process of specifying the acquisition start bit corresponding to the lower 4 bits (3rd to 3rd bits) of the acquisition specified data, and the process of specifying the acquisition start bit. The process of loading the lower 12 bits of the start addresses SA0 to SA6 acquired from the special figure special electric address table 64q into the lower 12 bits of the HL register 107, and the process of masking the upper 4 bits of the HL register 107 with "0". It can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

After that, the instruction "ADD HL, 9000H" is executed (step S3209), and the address acquisition execution process is terminated. "ADD" is an operation instruction called an ADD instruction, "HL" is a content for designating an HL register 107, and "9000H" is 2-byte numerical data. By executing "ADD HL, 9000H", "9000H", which is a reference address of the data table, is added to the value of the HL register 107. As a result, as shown in FIG. 87, the entire start address SA0 to SA6 (2 bytes) corresponding to the values of "0" to "6" in the special electric special figure counter can be set. Specifically, when the value of the special figure special electric counter is "0", the start address SA0 "9700H" is set in the HL register 107, and when the value of the special figure special electric counter is "1". Is set to the start address SA1 "9712H" in the HL register 107, and when the value of the special figure special electric counter is "2", the start address SA2 "971FH" is set in the HL register 107. When the value of the special electric counter is "3", the start address SA3 "9731H" is set in the HL register 107, and when the value of the special electric special electric counter is "4", the start address is set in the HL register 107. When "9740H" which is SA4 is set and the value of the special figure special electric counter is "5", "974CH" which is the start address SA5 is set in the HL register 107 and the value of the special figure special electric counter is "6". , The start address SA6 is set to "9753H" in the HL register 107.

As described above, the address acquisition execution process (FIG. 88) is a subroutine executed by the line number "3004" of the special figure special electric address acquisition process (FIG. 86 (c)). Therefore, when the address acquisition execution process is completed, the process proceeds to the line number “1605” of the special figure special electric address acquisition process.

In this way, by using the special LDB instruction, the lower 12 bits of the start addresses SA0 to SA6 can be loaded into the HL register 107 from the special figure special electric address table 64q. Further, by adding "9000H" corresponding to the upper 4 bits common to the start addresses SA0 to SA6 to the value of the HL register 107 after executing the special LDB instruction, the start addresses SA0 to SA6 are added to the HL register 107. You can get the whole thing. Therefore, the address data set in the special figure special electric address table 64q can be limited to the lower 12 bits of the start addresses SA0 to SA6. As a result, the data capacity of the special figure special electric address table 64q in the main ROM 64 can be reduced as compared with the configuration in which the entire 2-byte start addresses SA0 to SA6 are set in the special figure special electric address table 64q.

According to the present embodiment described in detail above, the following excellent effects are obtained.

In the special LDB instruction, the acquisition start address of the data in the main ROM 64 is specified based on the data of the upper 12 bits (4th to 15th bits) in the 2-byte acquisition data designation data, and the lower order in the acquisition data designation data is specified. The acquisition start bit of the data in the main ROM 64 is specified based on the data of the 4 bits (3rd to 3rd bits). Therefore, the data of the acquired data specified data is compared with the configuration in which 2-byte data for specifying the acquisition start address and 1-byte data for specifying the acquisition start bit are set in the acquired data specified data. The capacity can be reduced by 1 byte.

In the special LDB execution circuit 201, the operation of the logical product of the lower 1 byte of the acquired data designated data and "00001111B" is performed in order to specify the acquisition start bit. No data is set in the instruction code of the special LDB instruction to specify that "00001111B" is used in the operation for calculating the acquisition start bit. The operation of the logical product of the lower 1 byte of the acquired data designated data and "000011111B" is automatically executed by the special LDB execution circuit 201 when the special LDB instruction set in the program is executed. Therefore, the instruction of the special LDB instruction is compared with the configuration in which it is necessary to set the data for designating that "000011111B" is used in the operation for calculating the acquisition start bit in the instruction code of the special LDB instruction. The data capacity of the code can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

In the special LDB execution circuit 201, an operation of dividing the acquired data designation data by "16" is performed in order to specify the acquisition start address. "16" used in the calculation for specifying the acquisition start address is a numerical range represented by 4 bits, which is the number of bits of the data set to specify the acquisition start bit in the acquisition data specification data ("16". It is a value obtained by adding "1" to "15" which is the maximum value of "0" to "15"). This is to specify the acquisition start bit in the configuration in which the data for specifying the acquisition start address and the data for specifying the acquisition start bit are set in the 2-byte acquisition data specification data. Data for specifying the acquisition start address can be set independently of the data in.

In the special LDB execution circuit 201, an operation of dividing the acquired data designation data by "16" is performed in order to specify the acquisition start address. No data is set in the instruction code of the special LDB instruction to specify that "16" is used in the operation for calculating the acquisition start address. The operation of dividing the acquired data specified data by "16" is automatically executed by the special LDB execution circuit 201 when the special LDB instruction set in the program is executed. Therefore, the instruction code of the special LDB instruction is compared with the configuration in which it is necessary to set the data for specifying that "16" is used in the operation for calculating the acquisition start address in the instruction code of the special LDB instruction. The data capacity of the program can be reduced, and the data capacity of the program in the main ROM 64 can be reduced.

The acquisition data of 2 bytes is configured by loading the lower 12 bits of the start addresses SA0 to SA6 acquired from the special figure special electric address table 64q using the special LDB instruction into the 0th to 11th bits of the HL register 107. The process of specifying the acquisition start address corresponding to the 4th to 15th bits of the specified data, the process of specifying the acquisition start bit corresponding to the lower 4 bits (3rd to 3rd bits) of the acquisition specified data, and the process of specifying the acquisition start bit. The process of loading the lower 12 bits of the start addresses SA0 to SA6 acquired from the special figure special electric address table 64q into the lower 12 bits of the HL register 107, and the process of masking the upper 4 bits of the HL register 107 with "0". It can be executed with one instruction. As a result, the configuration of the program can be simplified and the data capacity of the program in the main ROM 64 can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes. can.

<Other embodiments>
It should be noted that the description is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the spirit of the present invention. For example, it may be changed as follows. Incidentally, the following configuration of another embodiment may be applied individually or in combination to the configuration of the above embodiment.

(1) In each of the above embodiments, instead of the configuration in which the data of the number of bits of the value obtained by adding "1" to the value of the data for specifying the number of acquired bits is acquired when the LDB instruction is executed by the LDB execution circuit 157. , The data of the number of bits corresponding to the value of the specified data for the number of acquired bits may be acquired. As already described in the first embodiment, the instruction code of the LDB instruction has a configuration of "LDB transfer destination, acquisition data designation. Acquisition bit number designation". In this configuration, the number of bits of data acquired from the data table stored in the main ROM 64 can be set to "specify the number of acquired bits" in the instruction code of the LDB instruction. Further, in each of the above embodiments, instead of the configuration in which the data of the number of bits of the value obtained by adding "1" to the value of the data for specifying the number of acquired bits is acquired when the special LDB instruction is executed by the special LDB execution circuit 201. Therefore, the data of the number of bits corresponding to the value of the data for specifying the number of acquired bits may be acquired. As already described in the sixth embodiment, the instruction code of the special LDB instruction has a configuration of "LDB transfer destination, acquisition data designation. Acquisition bit number designation". In this configuration, the number of bits of data acquired from the data table stored in the main ROM 64 can be set to "specify the number of acquired bits" in the instruction code of the special LDB instruction.

(2) In each of the above embodiments, when the LDB update command is executed by the LDB update execution circuit 161, the data of the number of bits of the value obtained by adding "1" to the value of the data for specifying the number of acquired bits is acquired. Alternatively, the configuration may be such that the data of the number of bits corresponding to the value of the data for specifying the number of acquired bits is acquired. As already described in the first embodiment, the instruction code for updating the LDB instruction has a configuration of "LDB transfer destination, (acquisition data designation +). Acquisition bit number designation". In this configuration, the number of bits of data acquired from the data table stored in the main ROM 64 can be set to "specify the number of acquired bits" in the instruction code of the LDB update instruction.

(3) The LDH execution circuit, which is a dedicated circuit for executing the LDH instruction, may be provided on the main MPU 62. The main CPU 63 can execute the LDH instruction. The instruction code of the LDH instruction has a configuration of "LDH transfer destination, transfer source". In the LDH instruction, the WA register 104 is set as the "transfer destination" and the HL register 107 is set as the "transfer source". The LDH instruction is a WA register 104 in which the upper 4 bits of the 1-byte data stored in the area corresponding to the address stored in the HL register 107 of the "transfer source" is set as the "transfer destination". A process of loading into the lower 4 bits of one of the general-purpose registers (W register 104a) and masking the upper 4 bits of the general-purpose register with "0", and a process of masking the lower 4 bits of the 1-byte data as a "transfer destination". Of the WA registers 104 set in, the process of loading into the lower 4 bits of the other general-purpose register (A register 104b) and masking the upper 4 bits of the general-purpose register with "0" can be executed with one instruction. It is an instruction to. By using the LDH instruction, the program configuration can be simplified and the data capacity of the program can be simplified as compared with the configuration in which a plurality of instructions are set to execute these two processes. Can be reduced. The BC register 105, DE register 106 or HL register 107 may be set as the "transfer destination" in the LDH instruction, and the WA register 104, BC register 105 or DE register 106 may be set as the "transfer source" in the LDH instruction. It may be a configuration to be set.

(4) In each of the above embodiments, when the situation shifts from the situation where the process for specific control is executed to the situation where the process for non-specific control is executed, and the process for non-specific control is executed. The reference address of the data table stored in the TP register 111 may be changed when the situation shifts from the situation to the situation where the processing for specific control is being executed. Specifically, in the main ROM 64, the data for specific control is set in the address range of "9000H" to "94FFH", and the data for non-specific control is set in the address range of "8903H" to "8BFFF". It is set. The main CPU 63 is the data for specific control when the supply of operating power is started and when the situation shifts from the situation where the process for non-specific control is executed to the situation where the process for specific control is executed. “9000H” is set in the TP register 111 as the reference address of the table. The "9000H" is the upper 4 bits ("9H") common to the address range referred to in the situation where the processing for specific control is executed in the address range in which the data table is stored in the main ROM 64. Information that can be specified. By executing the LDT instruction in the process for specific control, the "9000H" stored in the TP register 111 is diverted while the address specification data set in the program is the lower 12 bits of the 2-byte address. Allows the entire 2-byte address to be specified. The main CPU 63 sets "8000H" as the reference address of the data table for non-specific control when shifting from the situation where the process for specific control is executed to the situation where the process for non-specific control is executed. Set. The "8000H" is the upper 4 bits ("8H") common to the address range referred to in the situation where the processing for non-specific control is executed in the address range in which the data table is stored in the main ROM 64. It is information that makes it possible to identify. By executing the LDT instruction in the non-specific control process, the "8000H" stored in the TP register 111 is diverted while the address specification data set in the program is the lower 12 bits of the 2-byte address. This makes it possible to specify the entire 2-byte address. In this way, among the address ranges in which the data table is stored in the main ROM 64, the upper 4 bits common to the addresses corresponding to the storage area to be referenced in the situation where the non-specific control processing is being executed are the upper 4 bits. Even in a configuration that is different from the upper 4 bits common to the address corresponding to the storage area to be referenced in the situation where the processing for specific control is being executed, it is not specified from the situation where the processing for specific control is being executed. It is stored in the TP register 111 when shifting to the situation where the control processing is being executed or when shifting from the situation where the non-specific control processing is being executed to the situation where the specific control processing is being executed. The LDT instruction can be made available in each situation by changing the reference address of the data table.

(5) In the sixth embodiment, the number of bits of data set to specify the acquisition start bit in the acquisition data designation data of the special LDB instruction may be "5" or more. Specifically, the acquired data designation data is 2-byte data as in the sixth embodiment. When the number of bits of the data set to specify the acquisition start bit in the acquired data specified data is "n" (n is an integer of 5 to 15), the higher order (16-) in the acquired data specified data. The n) bit is used in the operation for specifying the acquisition start address, and the lower n bits in the acquisition data designated data are used in the operation for specifying the acquisition start bit. The acquisition start address is calculated by adding the reference address (“9000H”) of the data table stored in advance in the TP register 111 to the value obtained by dividing the acquired data specified data by “2 to the nth power”. It is calculated. The data "2 to the nth power" used in the operation for specifying the acquisition start address is represented by n bits, which is the number of bits of the data set to specify the acquisition start bit in the acquisition data specification data. It is a value obtained by adding "1" to "(2 to the nth power) -1" which is the maximum value in the numerical range ("0" to "(2 to the nth power) -1"). When the acquired data specified data is divided by the "2 to the nth power", the information of "0" or "1" set in the nth to 15th bits of the acquired data specified data is shifted to the lower side by n bits. The lower (16-n) bits (0th to (15th-n) bits) in the quotient data after division are set, and the upper n bits ((16-n) to (16-n) to) in the quotient data after division are set. "0" is set in the 15th bit). The acquisition start bit is the data of the lower n bits of the acquisition data designated data. The acquisition start bit is an integer of any of "0" to "(2 to the nth root) -1".

For example, when the number of bits of the data set to specify the acquisition start bit in the acquired data specified data is "5", the upper 11 bits in the acquired data specified data are used in the calculation for specifying the acquisition start address. At the same time, the lower 5 bits in the acquired data designated data are used in the calculation for specifying the acquisition start bit. The acquisition start address is calculated by adding the reference address (“9000H”) of the data table stored in advance in the TP register 111 to the value obtained by dividing the acquired data specified data by “32”. .. The data "32" used in the operation to specify the acquisition start address is a numerical range represented by 5 bits, which is the number of bits of the data set to specify the acquisition start bit in the acquisition data specification data ( It is a value obtained by adding "1" to "31", which is the maximum value of "0" to "31"), and is the fifth power of "2". When the acquired data designated data is divided by the "32" (100,000H), the information of "0" or "1" set in the 5th to 15th bits of the acquired data designated data is shifted to the lower side by 5 bits. The lower 11 bits (0th to 10th bits) of the divided quotient data are set, and "0" is set to the upper 5 bits (11th to 15th bits) of the divided quotient data. .. The minimum value of the acquisition start address that can be set in this configuration is "1001000000000000" (9000H), and the maximum value of the acquisition start address that can be set is "1001011111111111" (97FFH). The acquisition start bit is the data of the lower 5 bits of the acquisition data designated data. The acquisition start bit is calculated by calculating the logical product of the lower 1 byte of the acquired data designated data and "00011111B" ("1FH"). The "00011111B" used in the calculation for calculating the acquisition start bit extracts only the lower 5 bits (0th to 4th bits) of the acquisition data designation data from the 16-bit acquisition data designation data. It is the data for. The acquisition start bit is an integer of any of "0" to "31".

(6) In the sixth embodiment, the data structure of the main ROM 64 may be a structure in which a storage area of 2 bytes is set for one address. By adding predetermined numerical information to the acquisition data designation data of the special LDB instruction, the acquisition start address is calculated by the quotient in the calculation result of the operation of dividing the predetermined numerical information by "16" (2 to the 4th power). In addition to being able to update, the acquisition start bits can be updated by the remainder of the calculation result.

(7) In each of the above embodiments, two different registers (W register 104a and W register 104a) among the 1-byte data set in the data table of the main ROM 64 when the LDH update instruction is executed by the LDH update execution circuit 152. The combination of the number of bits of data read into the A register 104b) is not limited to the combination of the upper 4 bits and the lower 4 bits. When the LDH update instruction is executed, the combination of the number of bits of the data read into two different registers of the 1-byte data is a combination of the upper 1 bit and the lower 7 bits, a combination of the upper 2 bits and the lower 6 bits, It may be a combination of upper 3 bits and lower 5 bits, a combination of upper 5 bits and lower 3 bits, a combination of upper 6 bits and lower 2 bits, or a combination of upper 7 bits and lower 1 bit.

(8) In the LDH update instruction, the area where the upper 4 bits data and the lower 4 bits data are set in the 1-byte area of the data table is set to the lower 4 bits of the W register 104a and the lower 4 bits of the A register 104b. There is no limitation. For example, in the LDH update instruction, the data of the upper 4 bits in the 1-byte area is set in the 1st to 4th bits of the W register 104a, and the data of the lower 4 bits in the 1-byte area is set in the A register 104b. The configuration may be set to the first to fourth bits. In this configuration, "0" is set in the 0th bit and the 5th to 7th bits for which data is not set in the W register 104a, and the 0th bit and the fifth bit in which data is not set in the A register 104b are set. ~ "0" is set in the 7th bit. When setting a plurality of types of 1-byte data in which the 0th bit and the 5th to 7th bits are common to "0" in the data table, only the 1st to 4th bits of each 1-byte data are set in the data table. The data capacity of the data table can be reduced by collectively setting.

(9) In the LDB instruction and the LDB update instruction, the area in which the data acquired from the data table is set is not limited to the lower area in the "transfer destination" register. For example, in the LDB instruction and the LDB update instruction, the 3-bit data acquired from the data table may be set to the first to third bits in the B register 105a of the “transfer destination”. When the 3-bit data is set in the B register 105a, "0" is set in the 0th bit and the 4th to 7th bits in which the data is not set in the B register 105a. When setting a plurality of types of 1-byte data in which the 0th bit and the 4th to 7th bits are common to "0" in the data table, only the 1st to 3rd bits of each 1-byte data are set in the data table. The data capacity of the data table can be reduced by collectively setting.

(10) The specific control reference address and the non-specific control reference address preset in the IY register 109 are not limited to the configuration used to specify the upper 4 bits of the address, and these standards are used. The address may be configured to be used to specify a part or the whole of the address. Specifically, in the main RAM 65, the work area for specific control is set in the address range of "1050H" to "134DH", and the work area for non-specific control is the address of "1350H" to "14FFH". It is set to the range. In the IY register 109, "1050H" is set as the reference address for specific control at the start of the process for specific control, and "1350H" is set as the reference address for non-specific control at the start of the process for non-specific control. Will be done. By executing the first LDY instruction "LDY BC, 19H" in the state where "1050H" is set in the IY register 109, "1069H" calculated by adding "19H" to "1050H" is BC. It can be stored in the register 105. Further, "1353H" calculated by adding "03H" to "1350H" by executing the first LDY instruction "LDY HL, 03H" while "1350H" is set in the IY register 109. Can be stored in the HL register 107.

(11) An operation of adding a specific control reference address (“0000H”) or a non-specific control reference address (“0300H”) set in the IY register 109 and 1-byte numerical information (for example, “19H”). The processing and the setting processing for setting the result of the arithmetic processing in the pair register such as the BC register 105 may be performed by a subroutine on the program. This makes it possible to specify an address that diverts the specific control reference address or non-specific control reference address stored in the IY register 109 in advance, while eliminating the need to provide a dedicated circuit for executing these two processes. Can be. Further, by configuring the subroutine for executing these two processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these two processes can be increased. Can be reduced.

(12) An arithmetic process for adding the reference address (“9000H”) of the data table set in the TP register 111 and 12-bit numerical information (for example, “400H”), and the result of the arithmetic process (“9400H””. ) May be set in a pair register such as the HL register 107, and the setting process may be performed by a subroutine on the program. This makes it possible to specify an address by diverting the reference address of the data table stored in the TP register 111 in advance, while eliminating the need to provide a dedicated circuit for executing these two processes. Further, by configuring the subroutine for executing these two processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these two processes can be increased. Can be reduced.

(13) The process of specifying the acquisition start address corresponding to the 3rd to 15th bits of the acquisition data designation data, the process of specifying the acquisition start bit corresponding to the lower 3 bits of the acquisition designation data, and the acquisition start address. The process of loading the data for the number of acquired bits from the acquisition start bit of the "transfer destination" register to the "transfer destination" register, and the bits existing on the higher side of the loaded data in the "transfer destination" register are set to "0". The masking process may be performed by a subroutine in the program. This eliminates the need to provide a dedicated circuit for executing these four processes, while specifying the information set in the data table in bit units and maintaining the order of the bit array as the "transfer destination". It can be loaded into a register (for example, HL register 107), and the bits existing on the higher side of the loaded data in the register can be masked with "0". Further, by configuring the subroutines for executing these four processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these four processes can be increased. Can be reduced.

(14) The transfer destination address (“1100H”) is calculated by calculating the sum of the data stored in the IY register 109 (specifically, “1100H”) and the data stored in the A register 104b (for example, “11H”). The process of calculating 1111H ") and the process of loading 1-byte data stored in the W register 104a of the" transfer source "to the transfer destination may be performed by a subroutine on the program. This makes it possible to specify an address by diverting the information stored in the IY register 109 in advance, while eliminating the need to provide a dedicated circuit for executing these two processes. Further, by configuring the subroutine for executing these two processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these two processes can be increased. Can be reduced.

(15) The process of loading the data (for example, the determination value HVB1) set in the data table (for example, the fluctuation pattern table 64t) into a register such as the D register 106a, and adding 1 to the value of the HL register 107 after loading the data. The process of updating the address stored in the HL register 107 may be performed by a subroutine on the program. This makes it unnecessary to provide a dedicated circuit for executing these two processes. Further, in each program, the data capacity of the program can be reduced as compared with the configuration in which the process of updating the address stored in the HL register 107 is set after the execution of the subroutine.

(16) The process of specifying the acquisition start address corresponding to the 3rd to 15th bits of the acquisition data designation data, and the process of specifying the acquisition start bit corresponding to the 1st to 2nd bits of the acquisition designation data. In the main ROM 64, the process of loading the data for the number of acquisition bits set after the acquisition start bit at the acquisition start address into the lower bits in the "transfer destination" register and the upper bits in the "transfer destination" register are performed. The process of masking with "0" and the process of adding the number of acquired bits this time to the value of the HL register 107 after data transfer and updating the acquired data specified data may be performed by a subroutine on the program. This eliminates the need to provide a dedicated circuit for executing these five processes, while specifying the information set in the data table in bit units and maintaining the order of the bit array as the "transfer destination". It can be loaded into a register (for example, HL register 107), and the bits existing on the higher side of the loaded data in the register can be masked with "0". Further, after the data is loaded, the acquired data designation data can be updated by adding the number of acquired bits this time to the value of the HL register 107. By configuring the subroutines for executing these five processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these five processes is reduced. be able to.

(17) A process of specifying the acquisition start address corresponding to the 4th to 15th bits of the acquisition data designation data, a process of specifying the acquisition start bit corresponding to the 1st to 3rd bits of the acquisition designation data, and a process of specifying the acquisition start bit. In the main ROM 64, the process of loading the data for the number of acquisition bits set after the acquisition start bit at the acquisition start address into the lower bits in the "transfer destination" register and the upper bits in the "transfer destination" register are performed. The process of masking with "0" may be performed by a subroutine on the program. This eliminates the need to provide a dedicated circuit for executing these four processes, while specifying the information set in the data table in bit units and maintaining the order of the bit array as the "transfer destination". It can be loaded into a register (for example, HL register 107), and the bits existing on the higher side of the loaded data in the register can be masked with "0". By configuring the subroutines for executing these four processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these four processes is reduced. be able to.

(18) A process of setting the data set in the upper 4 bits of the 1-byte area in the data table to the lower 4 bits of the W register 104a and masking the upper 4 bits of the W register 104a with "0". The process of setting the data set in the lower 4 bits of the 1-byte area to the lower 4 bits of the A register 104b and masking the upper 4 bits of the A register 104b with "0", and the value of the HL register 107. The process of adding 1 to update the address stored in the HL register 107 may be performed by a subroutine on the program. This makes it unnecessary to provide a dedicated circuit for executing these three processes, and reads the upper 4-bit data and the lower 4-bit data set in the 1-byte area to different general-purpose registers. It can be made available, and the value stored in the HL register 107 can be updated by adding 1 to the value of the HL register 107. Further, by configuring the subroutines for executing these three processes to be commonly used in a plurality of processes, the data capacity of the program set in the main ROM 64 for executing these three processes can be increased. Can be reduced.

(19) In each of the above embodiments, the highest frame SFp (p is 1 or 2) in the communication command (communication variable command and communication normal return command) is the header HD and the first data frame FR1. It may be a configuration set between. In the variable command for communication including the two data frames FR1 and FR2, the frames are set in the order of header HD → first highest frame SF1 → first data frame FR1 → second data frame FR2 → footer FT. Further, in the normal return command for communication including 10 data frames FR1 to FR10, the header HD → the first highest frame SF1 → the second highest frame SF2 → the first data frame FR1 to the tenth data frame FR10 → the footer. Frames are set in the order of FT. When the data capacity of the communication command stored in the pre-conversion area 184 is 3 to 9 bytes, the sound-light side CPU 93 has the first highest frame SF1 in the second area RA2 in the pre-conversion area 184. Can be grasped that is set. Further, when the data capacity of the communication command stored in the pre-conversion area 184 is 10 to 12 bytes, the sound / light side CPU 93 is the first highest in the second area RA2 in the pre-conversion area 184. It can be understood that the frame SF1 is set and the second highest frame SF2 is set in the third area RA3 in the pre-conversion area 184.

(20) In each of the above embodiments, the highest frame SFp (p is 1 or 2) in the communication command (communication variable command and communication normal return command) is set immediately before the footer FT. May be. In the variable command for communication including the two data frames FR1 and FR2, the frames are set in the order of header HD → first data frame FR1 → second data frame FR2 → first highest frame SF1 → footer FT. Further, in the normal return command for communication including 10 data frames FR1 to FR10, the header HD → the first data frame FR1 to the tenth data frame FR10 → the first highest frame SF1 → the second highest frame SF2 → the footer. Frames are set in the order of FT. When the data capacity of the communication command stored in the pre-conversion area 184 is 3 to 9 bytes, the sound-light side CPU 93 is one of the areas in which the footer FT is stored in the pre-conversion area 184. It can be grasped that the first highest frame SF1 is set in the previous area. Further, when the data capacity of the communication command stored in the pre-conversion area 184 is 10 to 12 bytes, the sound / light side CPU 93 is located in the pre-conversion area 184 where the footer FT is stored. It is understood that the first highest frame SF1 is set in the area two before and the second highest frame SF2 is set in the area immediately before the area in which the footer FT is stored. Can be done.

(21) In each of the above embodiments, the bit used for distinguishing the header HD from the data other than the header HD is not limited to the most significant bit (7th bit) in each frame. For example, the bit used for distinguishing the header HD from the data other than the header HD may be the least significant bit (0th bit) in each frame. In the communication command (variation command for communication and normal return command for communication), the information "1" is set in the least significant bit of the header HD, while the least significant bit in the data other than the header HD. The information of "0" is set. The sound light side receiving circuit 96 can grasp whether or not the frame is the header HD based on the state of the least significant bit in each frame. In this configuration, the command for communication is set to the least significant frame in which the information of "0" or "1" in the least significant bit of each data frame FRm is collected. The nth bit (n is an integer of any of 1 to 7) of the first lowest frame corresponds to the nth data frame FRn. Further, the p-bit (p is an integer of 1 to 3) of the second lowest frame corresponds to the (p + 7) data frame FR (p + 7). The sound and light side CPU 93 sets the information of each bit of the lowest frame included in the communication command to the least significant bit of the data frame FRm corresponding to the bit in the converted command. As a result, during communication, the command for communication that can distinguish between the header HD and the frame other than the header HD is used, and the command for communication is used as the least significant bit of the data frame FRm before being used by the sound and light side CPU 93. Can be converted to a post-conversion command that can be set to "1".

(22) In each of the above embodiments, instead of the configuration in which the data set in the uppermost frames SF1 and SF2 are saved in the save areas 182 and 183, they are saved in registers (for example, D register 106a and E register 106b). It may be configured to be placed. Specifically, when a variable command for communication including two data frames FR1 and FR2 is set in the transmission standby buffer 175, the most significant bit (7th) in the data set in each data frame FR1 and FR2 in advance. The data of (bit) is saved in the D register 106a. Further, when a normal return command for communication including 10 data frames FR1 to FR10 is set in the transmission standby buffer 175, the most significant bit in the data set in advance in the first to seventh data frames FR1 to FR7 (the most significant bit (). The data of the 7th bit) is saved in the D register 106a, and the data of the most significant bit (7th bit) in the data set in the 8th to 10th data frames FR8 to FR10 is saved in the E register 106b. Keep it. By configuring the configuration in which the data of the most significant bit is saved in the register in this way, it is possible to eliminate the need for a dedicated area for saving the data of the most significant bit in the work area 121 for specific control.

(23) A configuration may be configured in which three or more uppermost frames are set in the communication command transmitted from the main CPU 63 to the sound light side CPU 93. For example, when 15 data frames FR1 to FR16 are set in the communication command, the information of the most significant bit in the first to seventh data frames FR1 to FR7 is aggregated in the communication command. The first most significant frame SF1, the second most significant frame SF2 in which the information of the most significant bits in the 8th to 14th data frames FR8 to FR14 are aggregated, and the most significant bit in the 15th to 16th data frames FR15 to FR16. The third most significant frame SF3, in which bit information is aggregated, is set. As already described in the first embodiment, when the number of data frames FRm included in the communication command is a multiple of "7", the data frame included in the communication command is included. The highest frame SFp of the number of quotients when the number of FRm is divided by "7" is set in the command for the communication. If the number of data frame FRm included in the communication command is not a multiple of "7", the number of data frame FRm included in the communication command is divided by "7". The highest frame SFp in a number "1" larger than the number of quotients in the case is set in the command for the communication. As a result, the information set in the most significant bit in all the data frame FRm included in the communication command after receiving the communication command can be set in the most significant frame SFp.

(24) In each of the above embodiments, the sound / light side RAM 95 may be configured to have a dedicated area for storing the command in a one-to-one correspondence with the command received from the main CPU 63. Specifically, the sound / light side RAM 95 is provided with a variation command storage area for storing the post-conversion variation command and a normal return command storage area for storing the post-conversion normal return command. The variable command storage area is an area consisting of 4 bytes, and the normal return command storage area is an area consisting of 12 bytes. When the sound and light side CPU 93 receives the communication variable command from the main CPU 63, the communication variable command is converted into the converted variable command and stored in the variable command storage area. As a result, until the converted variable command is used in the sound / light side CPU 93, the command is stored in the variable command storage area while preventing the command from being overwritten by another command. Can be done. When the sound and light side CPU 93 receives the normal return command for communication from the main CPU 63, the normal return command for communication is converted into the normal return command after conversion and stored in the normal return command storage area. As a result, the command is stored in the normal return command storage area while preventing the command from being overwritten by another command until the converted normal return command is used in the sound and light side CPU 93. Can be done.

(25) In each of the above embodiments, the main ROM 64 is "set" instead of the configuration in which only one type of high accuracy / rejection table 64g common to "setting 1" to "setting 6" is stored in the main ROM 64. A high-accuracy table may be stored in a one-to-one correspondence with the setting states of "1" to "setting 6". These high-probability tables are set so that the higher the set value, the higher the winning probability of the jackpot result. Specifically, 250 values that result in big hits are set in the high accuracy / rejection table for setting 1. When the high accuracy table for setting 1 is referred to, a big hit result is obtained at 1/32. In the high accuracy table for setting 2, 260 values that result in big hits are set. When the high accuracy table for setting 2 is referred to, a big hit result is obtained at about 1 / 30.8. In the high accuracy table for setting 3, 270 values that result in big hits are set. When the high accuracy table for setting 3 is referred to, a big hit result is obtained at about 1 / 29.6. In the high accuracy table for setting 4, 280 values that result in big hits are set. When the high accuracy table for setting 4 is referred to, a big hit result is obtained at about 1 / 28.6. In the high accuracy / rejection table for setting 5, 290 values that result in big hits are set. When the high accuracy table for setting 5 is referred to, a big hit result is obtained at about 1 / 27.6. In the high accuracy table for setting 6, 300 values that result in big hits are set. When the high accuracy table for setting 6 is referred to, a big hit result is obtained at about 1 / 26.7. When the setting state of the pachinko machine 10 is a high setting value, a big hit result is likely to occur in the high probability mode, and it is advantageous for the player. As a result, it is possible to improve the interest of the game.

(26) In each of the above embodiments, the setting value update process is executed and the setting confirmation according to the operation mode of the setting key insertion unit 68a and the reset button 68c at the start of supplying the operating power to the pachinko machine 10. There may be a case where the process is executed and a case where the RAM clear process is executed. Specifically, when the supply of operating power to the pachinko machine 10 is started while the setting key insertion unit 68a is being turned on and the reset button 68c is being turned on. Is executed a set value update process that enables the set value of the pachinko machine 10 to be updated, and is also executed a RAM clear process that clears the information stored in the main RAM 65 after the setting value update process is completed. .. Further, when the supply of operating power to the pachinko machine 10 is started while the setting key insertion unit 68a is being turned on and the reset button 68c is not being turned on, the pachinko machine is used. The setting confirmation process that enables the confirmation of the current setting value in the machine 10 is executed. Furthermore, when the supply of operating power to the pachinko machine 10 is started while the setting key insertion unit 68a is not turned on and the reset button 68c is turned on, the pachinko machine 10 is supplied with operating power. The RAM clear process described above is executed. In this way, depending on the operation mode of the setting key insertion unit 68a and the reset button 68c at the start of supplying the operating power to the pachinko machine 10, the setting value update process is executed and the setting confirmation process is executed. It is possible to facilitate the management of the pachinko machine 10 by the manager of the game hall by setting the case and the case where the RAM clearing process is executed.

(27) Display control based on the command transmitted from the main control device 60 instead of the configuration in which the display control device 89 is controlled by the voice emission control device 90 based on the command transmitted from the main control device 60. The device 89 may be configured to control the voice emission control device 90. Further, instead of the configuration in which the voice emission control device 90 and the display control device 89 are separately provided, a configuration in which both control devices are provided as one control device may be used, and the function of one of the two control devices may be provided. May be integrated in the main control device 60, and both functions of both control devices may be integrated in the main control device 60. Further, the content of the command transmitted from the main control device 60 to the voice emission control device 90 and the content of the command transmitted from the voice emission control device 90 to the display control device 89 are also arbitrary.

(28) Other types of pachinko machines different from the above embodiments, for example, a pachinko machine in which an electric accessory is opened a predetermined number of times when a game ball enters a specific area of a special device, or a game ball in a specific area of a special device. The present invention can also be applied to a pachinko machine, which is a big hit when a right is entered, a pachinko machine equipped with other accessories, an arrange ball machine, a game machine such as a sparrow ball, and the like.

In addition, it is equipped with a non-bullet type gaming machine, for example, a plurality of reels with a plurality of types of symbols attached in the circumferential direction, the reels are started to rotate by inserting medals and operating the start lever, and the stop switch is operated. After the reel has stopped after a predetermined time has passed, if a specific symbol or a combination of specific symbols is established on the effective line that can be seen from the display window, the player is given a privilege such as paying out a medal. The present invention can also be applied to a slot machine.

In addition, the main body of the gaming machine supported by the outer frame so as to be openable and closable is equipped with a storage unit and a take-in device, and the start lever is operated after a predetermined number of game balls stored in the storage unit are taken in by the take-in device. The present invention can also be applied to a gaming machine in which a pachinko machine and a slot machine are fused to start rotation of a reel.

<About the invention group extracted from each of the above embodiments>
Hereinafter, the characteristics of the invention group extracted from each of the above-described embodiments will be described while showing the effects and the like as necessary. In the following, for the sake of easy understanding, the corresponding configurations in each of the above embodiments are appropriately shown in parentheses or the like, but the present invention is not limited to the specific configurations shown in the parentheses or the like.

<Characteristic A group>
Features A1. Specific means for specifying a predetermined address of the storage area to be used (an address that specifies a transfer source in the first LDY instruction, the second LDY instruction, the LDT instruction, the LDB instruction, the LDB update instruction, and the special LDB instruction) (according to the first LDY execution circuit 156). A function to execute the first LDY instruction, a function to execute the LDT instruction by the LDT execution circuit 149, a function to execute the LDB instruction by the LDB execution circuit 157, a function to execute the LDB update instruction by the LDB update execution circuit 161 and a second LDY execution circuit. A function to execute the second LDY instruction by 164, a function to execute a special LD instruction in the special LD execution circuit 194, a function to execute a special LDB instruction in the special LDB execution circuit 201), and
A predetermined process execution means (execution of a first LDY instruction by the first LDY execution circuit 156) that executes a predetermined process (a process of transferring information of a transfer source) using a storage area corresponding to the predetermined address specified by the specific means. Function to execute, a function to execute an LDT instruction by the LDT execution circuit 149, a function to execute an LDB instruction by the LDB execution circuit 157, a function to execute an LDB update instruction by the LDB update execution circuit 161 and a second LDY instruction by the second LDY execution circuit 164. , A function to execute a special LD instruction in the special LD execution circuit 194, a function to execute a special LDB instruction in the special LDB execution circuit 201), and
In a gaming machine equipped with
It is possible to store the first predetermined address information (specific control reference address, non-specific control reference address, data table reference address) which is information of some of the plurality of bits included in the predetermined address. A predetermined storage means (IY register 109, TP register 111) is provided.
The specific means is a second predetermined address information (in the first LDY instruction, the second LDY instruction, and the special LD instruction, the address information is information of a bit different from the partial bit among the plurality of bits included in the predetermined address. The lower 1 byte, the lower 12 bits of the address information in the LDT instruction, the LDB instruction, the LDB update instruction and the special LDB instruction) are specified from the program, and the specified second predetermined address information and the second predetermined storage means are stored. 1 A gaming machine characterized in that the predetermined address is specified from the predetermined address information.

According to the feature A1, in order to specify the predetermined address from the second predetermined address information specified from the program and the first predetermined address information stored in the predetermined storage means, the entire predetermined address is compared with the configuration set in the program. Therefore, the data capacity of the information set in the program for specifying the predetermined address can be reduced.

Feature A2. The gaming machine according to feature A1, wherein the predetermined storage means is a predetermined register (IY register 109, TP register 111) provided in the control means.

According to the feature A2, the control means can easily access a predetermined register in which the first predetermined address information used for specifying the predetermined address is stored. It is possible to eliminate the need to provide a dedicated storage area for storing the first predetermined address information in addition to the predetermined register provided in the control means.

Feature A3. The range of the predetermined address specified by the specific means is the first address range (“0000H” to “0000H” to which the first predetermined address information is common, which is information of some of the plurality of bits included in the predetermined address. From "00FFH"), the second address range ("0303H" to "03FFH") in which the first predetermined address information, which is the information of the part of the bit, is common to the address information ("0300H") different from the first address range. ”), A function of executing the process of step S1707 in the main CPU 63 to change the information of the predetermined storage means from the first predetermined address information to the different address information (“0300H”). The gaming machine according to the feature A1 or A2, characterized in that it is provided with).

According to the feature A3, in the situation where the specific means specifies the predetermined address within the first address range, the first predetermined address information stored in the predetermined storage means can be used, and the specific means has the second address range. In a situation where a predetermined address is specified within, different address information stored in the predetermined storage means can be used.

Feature A4. The first specific process execution means (function for executing the process for specific control in the main CPU 63) for executing the first specific process (process for specific control), and
A second specific process execution means (a function of executing a process for non-specific control in the main CPU 63) for executing a second specific process (process for non-specific control), and
Equipped with
In a situation where the first specific process is being executed, the predetermined process executing means uses the storage area corresponding to the predetermined address specified by the specific means from the first address range to determine the predetermined process. In a situation where the process is executed and the second specific process is being executed, the predetermined process is performed by using the storage area corresponding to the predetermined address specified by the specific means from the second address range. Run and
The changing means changes the information of the predetermined storage means from the first predetermined address information to the different address information when the second specific process is started in the situation where the first specific process is executed. The gaming machine according to feature A3.

According to the feature A4, in the situation where the first specific process is being executed, the first predetermined address information stored in the predetermined storage means can be used to specify the specific address, and the second specific process is executed. In this situation, different address information stored in a predetermined storage means can be used to specify a specific address.

Feature A5. The predetermined processing executing means is included in the first address range by utilizing the first predetermined address information stored in the predetermined storage means in a situation where the first specific processing is being executed. An address in a third address range (“0100H” to “02FFH”) that identifies a predetermined address and does not overlap with the first address range and the second address range without using the information stored in the predetermined storage means. The gaming machine according to feature A4, which is characterized by specifying.

According to the feature A5, the predetermined address in the first address range and the address in the third address range can be specified in the situation where the first specific process is executed. Therefore, the range of addresses that can be specified in the situation where the first specific process is executed is limited to the configuration in which only the predetermined address in the first address range is specified in the situation where the first specific process is executed. Can be secured widely. When the predetermined address in the first address range is specified in the situation where the first specific process is executed, the first predetermined address information stored in the predetermined storage means is used, while the third address range When the address is specified, the information stored in the predetermined storage means is not used. Therefore, in the situation where the first specific process is being executed, the state in which the first predetermined address information is set in the predetermined storage means can be fixed. This makes it possible to eliminate the need for the process of changing the information set in the predetermined storage means and the process of returning the information of the predetermined storage means to the information before the change in the situation. Therefore, the data capacity of the program for executing the first specific process can be reduced.

Feature A6. The number of times the second predetermined address information for specifying the predetermined address in the first address range appears in the program for executing the first specific process specifies the address in the third address range in the program. The gaming machine according to feature A5, characterized in that the number of times the information for the game appears is greater than the number of times the information is displayed.

According to the feature A6, the data capacity of the program for executing the first specific process can be reduced.

Feature A7. Features A1 to A6 characterized by being provided with information setting means (a function of executing the process of step S103 in the main CPU 63) for setting the first predetermined address information in the predetermined storage means at the start of supply of operating power. The gaming machine according to any one of.

According to the feature A7, by setting the first predetermined address information in the predetermined storage means at the start of supply of the operating power, the first stored in the predetermined storage means in order to specify the specific address immediately after the start of the supply of the operating power. Predetermined address information can be made available.

Feature A8. Equipped with an information storage means (main side ROM 64) in which an address is set for each storage area.
As the predetermined address, the specific means specifies the address of the storage area of the information storage means from the second predetermined address information specified from the program and the first predetermined address information stored in the predetermined storage means. The gaming machine according to any one of the features A1 to A7.

According to the feature A8, when the address of the storage area in the information storage means is specified, the first predetermined address information stored in the predetermined storage means can be used. Therefore, it is set in the program to specify the address of the storage area in the information storage means as compared with the configuration in which the entire information of the address is set in the program to specify the address of the storage area in the information storage means. The data capacity of information can be reduced.

Feature A9. Information storage means (main side ROM64) in which an address is set for each storage area, and
The first process (power-on in the fourth embodiment) using the first information group (first initialization table 64y and second initialization table 64z in the fourth embodiment) stored in the information storage means. The first processing execution means (function for executing the processing of line numbers "2801" to "2806" in the main CPU 63) for executing the setting processing), and
A second process (random number maximum value setting process in the fourth embodiment) is executed using the second information group (random number maximum value table 64α in the fourth embodiment) stored in the information storage means. 2 processing execution means (a function of executing the processing of steps S3001 to S3006 in the main CPU 63) and
Equipped with
At the start of the first process, the specific means identifies the second predetermined address information from the program, and from the specified second predetermined address information and the first predetermined address information stored in the predetermined storage means. As a predetermined address, a means for specifying the first address in the specific address range (address range of "9400H" to "940BH") in which the first information group is set in the information storage means (main in the fourth embodiment). It has a function to execute the process of the line number "2801" of the side CPU 63).
The last address in the specific address range is the same common address (“940BH”) as the first address in the address range in which the second information group is set in the information storage means. The gaming machine according to any one of A8.

According to the feature A9, the information is compared with the configuration in which the last address in the address range in which the first information group is set and the first address in the address range in which the second information group is set are different addresses. The total data capacity of the first information group and the second information group in the storage means can be reduced. In order to specify the first address in the specific address range from the second predetermined address information specified from the program and the first predetermined address information stored in the predetermined storage means, the entire address is compared with the configuration set in the program. Therefore, the data capacity of the information set in the program to specify the first address in the specific address range can be reduced.

Feature A10. Predetermined common information (“63H”) is set in the storage area corresponding to the common address in the information storage means.
The first process executing means ends the first process by using the predetermined common information, and the first process is executed.
The gaming machine according to feature A9, wherein the second process executing means sets the predetermined common information in the information setting area at the start of the second process.

According to the feature A10, the first process is terminated by using the predetermined common information set in the information setting area in the second process. Therefore, as compared with the configuration in which the information for terminating the first process is set in the information storage means separately from the predetermined common information set in the information setting area, the first information group in the information storage means and The total data capacity of the second information group can be reduced.

Feature A11. The first processing execution means is
Instruction of predetermined common setting means (line number "2903" in main CPU 63) for setting predetermined common information ("63H") set in the storage area corresponding to the common address in predetermined common storage means (E register 106b). Function to execute) and
A predetermined end means (a function of executing an instruction of line number "2904" in the main CPU 63) to end the first process based on the predetermined common information being set in the predetermined common storage means.
Equipped with
The second process is described in feature A10, wherein the second process executing means executes the second process by using the predetermined common information set in the predetermined common storage means at the end of the first process. Gaming machine.

According to the feature A11, it is possible to omit the process of setting the predetermined common information in the predetermined common storage means at the start of the second process. As a result, the data capacity of the program for executing the second process can be reduced.

In addition, with respect to the composition of the features A1 to A11, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

According to the invention according to the above-mentioned feature A group, the following problems can be solved.

Pachinko machines and slot machines are known as game machines. For example, the pachinko machine is provided with a dish storage section for storing the game balls given to the player on the front portion of the game machine, and the game balls stored in the dish storage section are guided to the game ball launcher. It is fired toward the game area according to the player's firing operation. Then, for example, when the game ball enters the ball entry section provided in the game area, the game ball is dispensed from the payout device to the dish storage section, for example. Further, in a pachinko machine, a configuration in which an upper plate storage unit and a lower plate storage unit are provided as a plate storage unit is also known. In this case, the game ball stored in the upper plate storage unit is a game ball launching device. The game ball that has become surplus in the upper dish storage section is discharged to the lower dish storage section.

Further, in the slot machine, when the start lever is operated and a new game is started in the situation where the medal is bet, the lottery process is executed by the control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means operates. The rotation of the reel is stopped by executing the rotation stop control. Then, when the stop result after the reel rotation is stopped corresponds to the winning combination in the lottery process, the privilege corresponding to the winning combination is given to the player.

Here, in a gaming machine such as the above example, various processes need to be suitably executed, and there is still room for improvement in this respect.

<Characteristic B group>
Feature B1. Multiple address information (lower 12 bits of start addresses SA0 to SA6 in the first embodiment, lower 12 bits of start addresses SB0 to SB23, lower 1 byte of addresses of maximum value counters 191a to 193a in the second embodiment). The specific address to be referenced by using the set specific address information group (special figure special electric address table 64q in the first embodiment, fluctuation start table 64r, hard random number maximum value table 64w in the second embodiment). Address specifying means (a function of executing the instruction of the line number "1708" in the main CPU 63, a function of executing the instruction of the line number "2605" in the main CPU 63), and
Specific processing using the storage area corresponding to the specific address specified by the address specifying means (processing of steps S903 to S910 of the main CPU 63 in the first embodiment, main CPU 63 in the second embodiment). Specific processing execution means for executing the maximum value setting execution process in the first embodiment (function for executing the processes of steps S903 to S910 of the main CPU 63 in the first embodiment, maximum value setting in the main CPU 63 in the second embodiment). (Function to execute execution process) and
In a gaming machine equipped with
The specific address specified by the address specifying means using the specific address information group is information of a predetermined range of bits among a plurality of bits included in the specific address (reference address of data table, maximum value counter 191a to The upper 1 byte common to the address of 193a) is common,
The gaming machine includes specific storage means (IY register 109, TP register 111) capable of storing bit information in the predetermined range.
The address information included in the specific address information group includes information other than the bits in the predetermined range among the plurality of bits included in the specific address (lower 12 bits of start addresses SA0 to SA6, start addresses SB0 to SB23). The lower 12 bits of the game machine, the lower 1 byte of the address of the maximum value counters 191a to 193a) is set.

According to the feature B1, the specific address can be specified by using the address information set in the specific address information group. Since the address information set in the specific address information group is information other than the bits in the predetermined range among the plurality of bits included in the specific address, the address set in the specific address information group to specify the specific address. The data capacity of information can be reduced, and the data capacity of the specific address information group can be reduced.

Feature B2. The gaming machine according to feature B1, wherein the specific storage means is a predetermined register (IY register 109, TP register 111) provided in the control means.

According to feature B2, the control means can easily access a predetermined register in which information of a predetermined range of bits used for specifying a specific address is stored. It is possible to eliminate the need to provide a dedicated storage area for storing information of a predetermined range of bits other than the predetermined register provided in the control means.

Feature B3. The specific address information group includes address information of a plurality of setting target areas (data of the lower 1 byte at the addresses of the maximum value counters 191a to 193a set in the hard random number maximum value table 64w in the second embodiment). , Numerical information set in the plurality of setting target areas (maximum value data corresponding to the maximum value counters 191a to 193a of the hard random number maximum value table 64w in the second embodiment) is set.
The address specifying means uses the specific address information group to specify the address of the setting target area to be referred to, and the address specifying means determines the address of the setting target area.
As the specific process, the specific process executing means executes a process of setting the numerical information in the setting target area corresponding to the address specified by the address specifying means.
Of the plurality of bits included in the address of the setting target area, the information of the bits in the predetermined range is common.
In the specific address information group, information other than the bits in the predetermined range among the plurality of bits included in the address of the setting target area is set.
The gaming machine according to feature B1 or B2, wherein the address information of the setting target area set in the specific address information group has the same data capacity as the numerical information.

According to the feature B3, the address information of the setting target area set in the specific address information group is set to the information other than the bits in the predetermined range, so that the address information of the setting target area set in the specific address information group can be obtained. The data capacity of the numerical information can be the same as the data capacity. Therefore, the data capacity of the specific address information group can be reduced as compared with the configuration in which the adjustment data that is not used for the specific address information group is set.

Feature B4. Features B1 to B3 characterized in that the specific storage means is provided with setting means (a function of executing the process of step S103 in the main CPU 63) to set information of bits in the predetermined range at the start of supply of operating power. The gaming machine according to any one of.

According to the feature B4, by setting the information of a predetermined range of bits in the specific storage means at the start of supply of the operating power, the predetermined storage means stored in the specific storage means to specify the specific address immediately after the start of the supply of the operating power. Bit information in the range can be made available.

Feature B5. The bit information in the predetermined range stored in the specific storage means can be referred to by using another address information group (variation start table 64r in the first embodiment) in which a plurality of address information is set. The gaming machine according to any one of features B1 to B4, which is also used when specifying another address (starting address SB0 to SB23).

According to the feature B5, the information of a predetermined range of bits stored in the specific storage means is used not only when specifying a specific address but also when specifying another address. Therefore, it is possible to eliminate the need for the process of changing the information stored in the specific storage means.

Feature B6. The game according to any one of features B1 to B5, wherein the information other than the bits in the predetermined range is information arranged on the lower side of the information of the bits in the predetermined range at the specific address. Machine.

According to the feature B6, the information set in the program for specifying the specific address can be limited to the information other than the bits in the predetermined range lower than the bits in the predetermined range at the specific address.

In addition, with respect to the composition of the features B1 to B6, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

According to the invention according to the above-mentioned feature B group, the following problems can be solved.

Pachinko machines and slot machines are known as game machines. For example, the pachinko machine is provided with a dish storage section for storing the game balls given to the player on the front portion of the game machine, and the game balls stored in the dish storage section are guided to the game ball launcher. It is fired toward the game area according to the player's firing operation. Then, for example, when the game ball enters the ball entry section provided in the game area, the game ball is dispensed from the payout device to the dish storage section, for example. Further, in a pachinko machine, a configuration in which an upper plate storage unit and a lower plate storage unit are provided as a plate storage unit is also known. In this case, the game ball stored in the upper plate storage unit is a game ball launching device. The game ball that has become surplus in the upper dish storage section is discharged to the lower dish storage section.

Further, in the slot machine, when the start lever is operated and a new game is started in the situation where the medal is bet, the lottery process is executed by the control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means operates. The rotation of the reel is stopped by executing the rotation stop control. Then, when the stop result after the reel rotation is stopped corresponds to the winning combination in the lottery process, the privilege corresponding to the winning combination is given to the player.

Here, in a gaming machine such as the above example, it is necessary to make the data structure of the information group suitable, and there is still room for improvement in this respect.

<Characteristic C group>
Features C1. Predetermined correspondence processing (processing to transfer information by LD update instruction, information transfer by LDH update instruction) using the storage area corresponding to the specified address (transfer source address in LD update instruction, LDH update instruction and LDB update instruction) Processing, processing to transfer information by LDB update command) (function to execute LD update command by LD update execution circuit 151, function to execute LDH update command by LDH update execution circuit 152, LDB Function to execute LDB update instruction by update execution circuit 161) and
Address update means for updating the designated address when the predetermined correspondence process is executed (a function of executing an LD update instruction by the LD update execution circuit 151, a function of executing an LDH update instruction by the LDH update execution circuit 152, and an LDB update). (Function to execute LDB update instruction by execution circuit 161) and
Equipped with
The feature is that the instructions for executing the predetermined correspondence process and updating the designated address after the execution of the predetermined correspondence process are aggregated into predetermined instructions (LD update instruction, LDH update instruction, LDB update instruction). A game machine to play.

According to the feature C1, the storage area corresponding to the designated address can be updated by updating the designated address when the predetermined correspondence process is executed. The process of updating the designated address after executing the predetermined response process and the predetermined response process can be executed with one instruction. Therefore, the configuration of the program for executing these two processes can be simplified and the program can be simplified as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes. Data capacity can be reduced.

Feature C2. The predetermined correspondence process is a process of reading the information stored in the storage area corresponding to the designated address to the read destination area (transfer destination in the instruction code of the LD update instruction, the LDH update instruction and the LDB update instruction). The gaming machine according to the feature C1.

According to the feature C2, the process of reading the information stored in the storage area corresponding to the designated address to the read destination area and the process of updating the designated address after the execution of the process can be executed by one instruction.

Feature C3. The predetermined instruction includes information for designating the designated address and information for designating the read destination area, and does not include information for designating the update amount of the designated address by the address update means. The gaming machine according to the feature C2.

According to the feature C3, since the predetermined instruction does not include the information for specifying the update amount of the specified address, the predetermined instruction is compared with the configuration in which the information for specifying the update amount of the specified address is included. The data capacity of the instruction can be reduced.

Feature C4. The gaming machine according to any one of features C1 to C3, wherein the update amount of the designated address updated by the address update means when the predetermined command is executed is fixed.

According to the feature C4, the designated address can be updated in a certain manner after the predetermined correspondence process is executed by executing the predetermined command.

Feature C5. The gaming machine according to feature C4, wherein the update amount of the designated address updated by the address update means when the predetermined command is executed is "1".

According to the feature C5, the designated address can be updated by "1" after the predetermined correspondence process is executed by executing the predetermined instruction.

Feature C6. After the initial designated address is set, a predetermined instruction executing means for repeatedly executing the predetermined instruction until an end determination is made (a function of executing the processes of steps S301 to S305 of the main CPU 63 in the first embodiment). The gaming machine according to any one of features C1 to C5, characterized in that it is provided with a function of executing processing of line numbers "1101" to line numbers "1109" of the main CPU 63).

According to the feature C6, while updating the designated address, the predetermined correspondence process is executed using the storage area corresponding to the designated address, and the process of updating the designated address is repeatedly executed after the execution of the predetermined correspondence process. Can be done.

It should be noted that, with respect to the configuration of the features C1 to C6, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic D group>
Feature D1. In a gaming machine in which an address is set for each storage area of a predetermined byte unit (1 byte unit) among the storage areas provided in the information storage means (main side ROM 64).
Designated address information (in the LDH update instruction, the transfer source address information stored in the HL register 107, in the LDB instruction, the LDB update instruction, and the special LDB instruction, the acquisition calculated from the acquisition data specified data stored in the HL register 107. Area specifying means for specifying the storage area in predetermined byte units corresponding to the start address (start address) (function to execute LDH update instruction in LDH update execution circuit 152, function to execute LDB instruction by LDB execution circuit 157, LDB update execution circuit) A function to execute an LDB update instruction by 161 and a function to execute a special LDB instruction by the special LDB execution circuit 201),
Bit specifying means for specifying a part of the bits in the storage area specified by the area specifying means (a function of executing the LDH update instruction in the LDH update execution circuit 152, executing the LDB instruction by the LDB execution circuit 157). Function to execute, a function to execute an LDB update command by the LDB update execution circuit 161, a function to execute a special LDB instruction by the special LDB execution circuit 201), and
A gaming machine characterized by being equipped with.

According to the feature D1, some bits in the storage area of a predetermined byte unit can be specified as a usage target. Since information can be aggregated in the information storage means in units smaller than a predetermined byte, the data capacity of the information stored in the information storage means can be reduced.

Feature D2. A means (in the LDH update execution circuit 152) for specifying a part of the other bits (lower 4 bits in the 1-byte area of the main ROM 64) of the storage area of the predetermined byte unit specified by the area specifying means as a usage target. The gaming machine according to feature D1, characterized in that it has a function of executing an LDH update command).

According to the feature D2, the configuration of the feature D1 is provided, and in the configuration in which some bits of the storage area of the predetermined byte unit specified by the area specifying means are specified as the usage target, the other part of the storage area is specified. Bits are also specified for use. Since some bits and some other bits stored in the storage area of one predetermined byte unit can be specified as usage targets, two pieces of information (some bits and some other bits) can be specified. ) Can be aggregated and set in one storage area in predetermined byte units. As a result, the data capacity of the information set in the information storage means can be reduced.

Feature D3. Among the storage areas of the predetermined byte unit specified by the area specifying means, the bit number (4 bits) of the part of the bit specified as the object of use and the other part of the bit is the same. The gaming machine according to the feature D2.

According to the feature D3, since some bits having the same number of bits and some other bits can be specified as usage targets in the storage area of one predetermined byte unit, the number of bits is the same 2. One piece of information (some bits and some other bits) can be aggregated and set in a storage area in a predetermined byte unit.

Feature D4. A first read means (LDH update execution circuit) that reads out a part of the bits specified as a use target in the storage area of the predetermined byte unit specified by the area specifying means to the first read target area (W register 104a). Function to execute the LDH update command in 152) and
A second read means (LDH update) that reads out some of the other bits specified as usage targets in the storage area of the predetermined byte unit specified by the area specifying means to the second read target area (A register 104b). (Function to execute LDH update instruction in the execution circuit 152) and
The gaming machine according to the feature D2 or D3, wherein the gaming machine is characterized by the above.

According to the feature D4, a part of the storage area of the predetermined byte unit specified by the area specifying means, which is specified as the target of use, is read out to the first read target area to be separated from the other bit. Can be used. Further, by reading some other bits specified as the target of use in the storage area to the second read target area, the bits can be separated from some bits and used.

Feature D5. It is determined that the bit information in which the information is not read in the first read target area and the second read target area becomes predetermined binary information (information of "0") which is one of the binary information. The gaming machine according to the feature D4.

According to the feature D5, a state in which a part of the storage area of the predetermined byte unit specified by the area specifying means and the predetermined binary information are set in the first read target area. Can be. Further, it is possible to set the second read target area in a state in which some other bits specified as the use target in the storage area of the predetermined byte unit and the predetermined binary information are set.

Feature D6. To specify the storage area of the predetermined byte unit corresponding to the designated address information, to specify a part of the storage area specified by the area specifying means as a usage target, and to specify the part of the bit. Reading to the first read target area, specifying the other part of the storage area specified by the area specifying means as a use target, and specifying the other part of the bit as the second read. The gaming machine according to feature D4 or D5, wherein the instructions to be read into the target area are aggregated into a specific instruction (LDH update instruction).

According to the feature D6, a process of specifying a storage area in a predetermined byte unit corresponding to the designated address information, a process of specifying a part of the storage area specified by the area specifying means as a usage target, and a part of the process. A process of reading a bit into the first read target area, a process of specifying another part of the storage area specified by the area specifying means as a use target, and a process of specifying the other part of the bit as a second read target area. The process of reading to can be executed with a single instruction. Therefore, the configuration of the program for executing these processes can be simplified as compared with the configuration in which a plurality of instructions are set in the program to execute these processes, and the data of the program can be simplified. The capacity can be reduced.

Feature D7. The specific instruction includes information that specifies the designated address information (for example, information of "(HL +)" in the LDH update instruction "LDH WA, (HL +)"), and information that specifies the first read target area (for example, Information of "WA" in the LDH update command "LDH WA, (HL +)") and information specifying the second read target area (information of "WA" in the LDH update command "LDH WA, (HL +)"). ) Is set, and information that specifies the number of bits of the part of the bit and the other part of the bit (the number of bits of information read in the W register 104a and the number of bits of the information read in the A register 104b). Is the gaming machine according to feature D6, which is characterized in that it is not set.

According to the feature D7, a specific instruction can be executed by designating the designated address information, the first read target area, and the second read target area. The data capacity of a particular instruction can be reduced as compared to a configuration in which information specifying the bit allocation of some bits and some other bits is set for a particular instruction.

Feature D8. Among the storage areas specified by the area specifying means, some of the bits specified as usage targets are bits having a continuous arrangement order in the storage area.
Among the storage areas specified by the area specifying means, some of the other bits specified as usage targets are bits having a continuous arrangement order in the storage area. The gaming machine according to any one of D7.

According to the feature D8, some bits and some other bits can be specified as usage targets from the storage area of a predetermined byte unit provided in the information storage means while maintaining the arrangement order.

Feature D9. The description according to any one of the features D1 to D8, wherein the partial bit specified as a usage target by the bit specifying means is a partial bit in the storage area of one predetermined byte unit. Game machine.

According to the feature D9, a part of the bits of the storage area can be specified as a usage target from the storage area of one predetermined byte unit.

Feature D10. Reference bit information (LDB instruction, LDB update instruction and special) that makes it possible to specify a bit to be used as a reference for a bit group including some bits among a plurality of bits in the storage area specified by the area specifying means. Bits to be specified as the usage target based on the reference number information (data for specifying the number of acquisition bits in the LDB instruction, LDB update instruction, and special LDB instruction) that can specify the acquisition start bit in the LDB instruction) and the number of bits to be used as the reference. It is characterized by having specific means (a function of executing an LDB instruction in the LDB execution circuit 157, a function of executing an LDB update instruction in the LDB update execution circuit 161 and a function of executing a special LDB instruction in the special LDB execution circuit 201). The gaming machine according to the feature D1.

According to the feature D10, among the plurality of bits in the storage area specified by the area specifying means in the configuration in which the address is set for each storage area in a predetermined byte unit among the storage areas provided in the information storage means. A bit group including some bits can be specified as a usage target. In addition, information can be aggregated bit by bit in the information storage means. As a result, the data capacity of the information stored in the information storage means can be reduced.

Feature D11. The reference bit information is characterized by being information (acquisition start bit th) that designates a start bit of the bit group specified as a usage target by the bit specifying means in the storage area specified by the area specifying means. The gaming machine according to the feature D10.

According to the feature D11, it is possible to specify the start bit of the bit group specified as the usage target in the storage area specified by the area specifying means by the reference bit information.

Feature D12. The gaming machine according to feature D10 or D11, wherein the bit group is a bit having a continuous arrangement order in the information storage means.

According to the feature D12, the bits having a continuous arrangement order can be specified as a bit group to be used in the information storage means.

Feature D13. The bit group specified as a usage target by the bit specifying means is read into the predetermined byte unit area (W register 104a or HL register 107 of the transfer destination in the LDB instruction, WA register 104 of the transfer destination in the LDB update instruction, W register). Information reading means (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161) read to 104a or B register 105a, transfer destination HL register 107 in special LDB instruction, special A function to execute a special LDB instruction by the LDB execution circuit 201) is provided.
Any of the features D10 to D12 characterized in that the information of the bit for which the information was not read in the read target area is the same information (information of "0") which is one of the binary information. The gaming machine described in 1.

According to the feature D13, the bit group specified by the bit specifying means as the usage target in the information storage means can be read out to the read target area and used. The bit group can be used in such a manner that each bit in the area where the bit group is not read in the read target area is one of the binary information and has the same information.

Feature D14. Described in feature D13, the number of bits of the bit group read by the information reading means into the read target area is larger than the number of bits of information set in the storage area in one predetermined byte unit. Game machine.

According to the feature D14, information having a data capacity exceeding a predetermined byte can be read out from the information storage means to the read target area. In addition, information having a data capacity exceeding a predetermined byte can be aggregated in the information storage means.

Feature D15. The reference bit information and the bit group including some bits among the plurality of bits in the storage area specified by the area specifying means to specify the storage area in the predetermined byte unit corresponding to the designated address information are used as the reference bit information. Specifying as a use target based on the reference number information, reading the bit group specified as a use target by the bit specifying means into the read target area, and bits for which information was not read in the read target area. It is characterized in that the instruction to make one of the above binary information the same information is aggregated as a specific instruction (LDB instruction, LDB update instruction, special LDB instruction). The gaming machine according to the feature D13 or D14.

According to the feature D15, the process of specifying the storage area in predetermined byte units corresponding to the designated address information, the bit group including some bits among the plurality of bits in the storage area specified by the area specifying means is used as the reference bit information. The processing of specifying the bit group as the usage target based on the reference number information, the processing of reading the bit group specified as the usage target by the bit specifying means into the reading target area, and the information of the bits for which the information was not read in the reading target area are 2 It is possible to execute a process of making one of the value information the same information with one instruction. Therefore, the configuration of the program for executing these processes can be simplified as compared with the configuration in which a plurality of instructions are set in the program to execute these processes, and the data of the program can be simplified. The capacity can be reduced.

Feature D16. In the specific instruction, information (acquired data designation data) that specifies predetermined information (acquired data designation data) used for calculating the designated address information and the reference bit information is stored in the HL register 107. The gaming machine according to the feature D15, wherein the designated address information and the reference bit information are not set.

According to the feature D16, predetermined information used for calculating the designated address information and the reference bit information is set in the specific instruction, and the designated address information and the reference bit information are not set. Compared with the configuration in which the designated address information and the reference bit information are set in the instruction, the data capacity of the information set in the specific instruction can be reduced.

Feature D17. The gaming machine according to feature D16, wherein the reference number information is set in the specific command.

According to the feature D17, the number of bits to be used as the reference for use can be specified by setting the reference number information in the specific instruction.

Feature D18. The gaming machine according to feature D16 or D17, wherein the specific instruction is not set with information that specifies a method of calculating the designated address information and the reference bit information using the predetermined information.

According to the feature D18, the data capacity of the information set in the specific instruction is reduced as compared with the configuration in which the information specifying the method for calculating the designated address information and the reference bit information is set in the specific instruction. Can be done.

Feature D19. The first predetermined information (in the first embodiment, the acquired data designation data in the LDB instruction and the LDB update instruction) of the first predetermined number of bits (“13” in the first embodiment, “12” in the sixth embodiment). The upper 13-bit data, in the sixth embodiment, the upper 12-bit data of the acquired data designation data in the special LDB instruction) and the second predetermined number of bits arranged on the lower side of the first predetermined information (first). The second predetermined information (in the first embodiment, the data of the lower three bits of the acquired data designation data in the LDB instruction and the LDB update instruction, the sixth) of the second predetermined information (“3” in the embodiment and “4” in the sixth embodiment). In the embodiment of the above, a means for reading predetermined information (acquired data designation data) having (lower 4 bits of data of the acquisition data designation data in the special LDB instruction) (a function of executing the LDB instruction by the LDB execution circuit 157, LDB update execution circuit 161). It has a function to execute the LDB update command by the special LDB execution circuit 201 and a function to execute the special LDB command by the special LDB execution circuit 201).
The area specifying means
By executing a predetermined arithmetic process on the predetermined information, the quotient is obtained by dividing by a binary value "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. Derivation means for deriving the corresponding information (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, function to execute special LDB instruction by special LDB execution circuit 201) ,
Address generation means for generating the designated address information using the information derived by the derivation means (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, special A function to execute a special LDB instruction by the LDB execution circuit 201) and
The gaming machine according to any one of features D10 to D18.

According to the feature D19, by executing a predetermined arithmetic process on the predetermined information, the division is performed by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. Information corresponding to the quotient of the case can be derived. Then, the designated address information can be generated by using the information derived by the derivation means.

Feature D20. The first predetermined information and the second predetermined information are continuous in the order of arrangement of bits.
The lowest bit of the second predetermined information is the lowest bit of the predetermined information.
The information derived by the derivation means is characterized in that the information is arranged so that the lowest bit in the bit array of the first predetermined information is the lowest bit of the derived information. The gaming machine described in D19.

According to the feature D20, by executing a predetermined arithmetic process on the predetermined information, the lowest bit in the bit array of the first predetermined information becomes the lowest bit of the derived information. The first predetermined information in the information can be shifted to the lower side by the number of the second predetermined bits.

Feature D21. Information derived by the derivation means (in the LDB instruction and the LDB update instruction, the quotient data when the acquired data designation data is divided by "8", and in the special LDB instruction, the quotient when the acquisition data designation data is divided by "16". The feature D19 or the feature D19 characterized in that each bit existing on the upper side of the bit array of the first predetermined information in the data) becomes the same information (information of "0") which is one of the binary information. The gaming machine described in D20.

According to the feature D21, by executing a predetermined arithmetic process on the predetermined information, the same information, which is one of the binary information, is generated in each bit existing on the upper side of the bit array of the first predetermined information. The set information can be generated and the information can be used.

Feature D22. The bit specifying means is an information extraction means (a function of executing an LDB instruction by the LDB execution circuit 157, an LDB update by the LDB update execution circuit 161) that extracts the second predetermined information from the predetermined information and generates the reference bit information. The gaming machine according to any one of features D19 to D21, characterized in that it has a function of executing a command and a function of executing a special LDB command by a special LDB execution circuit 201).

According to the feature D22, in a configuration in which the first predetermined information and the second predetermined information are aggregated into the predetermined information, the second predetermined information can be extracted from the predetermined information to generate the reference bit number information.

Feature D23. The information extracting means includes information including the second predetermined information (lower 1 byte of acquired data designation data) and mask data (data "000000111B" in the LDB instruction and LDB update instruction, and data "000001111B" in the special LDB instruction. The gaming machine according to feature D22, characterized in that the second predetermined information is extracted from the predetermined information by the calculation of the logical product with).

According to the feature D23, by using the mask data, the first predetermined information included in the predetermined information can be masked and the second predetermined information included in the predetermined information can be extracted.

Feature D24. The gaming machine according to any one of features D19 to D23, wherein the predetermined information is information in units of the predetermined bytes.

According to the feature D24, the first predetermined information and the second predetermined information can be aggregated into predetermined information in predetermined byte units. Therefore, it is possible to reduce the total data capacity of these information as compared with the configuration in which the information that enables the second predetermined information is present separately from the information that enables the first predetermined information. can.

It should be noted that, with respect to the configuration of the features D1 to D24, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic E group>
Features E1. In a gaming machine in which an address is set for each storage area of a predetermined byte unit (1 byte unit) among the storage areas provided in the information storage means (main side ROM 64).
Area specification that specifies the storage area in predetermined byte units corresponding to the specified address information (acquisition start address calculated from the acquired data specified data stored in the HL register 107 in the LDB instruction, LDB update instruction, and special LDB instruction). Means (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, function to execute special LDB instruction by special LDB execution circuit 201), and
Reference bit information (acquisition start bit) and usage target that make it possible to specify a bit to be used as a reference for a bit group including some bits among a plurality of bits in the storage area specified by the area specifying means. Bit specifying means (function for executing LDB instruction by LDB execution circuit 157, LDB by LDB update execution circuit 161) to be specified as a target to be used based on reference number information (acquired bit number designation data) that enables specification of the reference number of bits. A function to execute an update instruction, a function to execute a special LDB instruction by the special LDB execution circuit 201), and
A gaming machine characterized by being equipped with.

According to the feature E1, a bit group including some bits among a plurality of bits in the storage area of a predetermined byte unit specified by the area specifying means can be specified as a usage target. Since the information of the bit group can be aggregated and set in the information storage means, the data capacity of the information stored in the information storage means can be reduced.

Feature E2. The reference bit information is characterized by being information (acquisition start bit th) that designates a start bit of the bit group specified as a usage target by the bit specifying means in the storage area specified by the area specifying means. The gaming machine according to the feature E1.

According to the feature E2, it is possible to specify the start bit of the bit group specified as the usage target in the storage area specified by the area specifying means by the reference bit information.

Feature E3. The gaming machine according to feature E1 or E2, wherein the bit group is a bit having a continuous arrangement order in the information storage means.

According to the feature E3, the bits having a continuous arrangement order can be specified as a bit group to be used in the information storage means.

Feature E4. The bit group specified as a usage target by the bit specifying means is read into the predetermined byte unit area (W register 104a or HL register 107 of the transfer destination in the LDB instruction, WA register 104 of the transfer destination in the LDB update instruction, W register). Information reading means (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161) read to 104a or B register 105a, transfer destination HL register 107 in special LDB instruction, special A function to execute a special LDB instruction by the LDB execution circuit 201) is provided.
Any of the features E1 to E3 characterized in that the information of the bit for which the information was not read in the read target area is the same information (information of "0") which is one of the binary information. The gaming machine described in 1.

According to the feature E4, the bit group specified by the bit specifying means as the usage target in the information storage means can be read out to the read target area and used. The bit group can be used in such a manner that each bit in the area where the bit group is not read in the read target area is one of the binary information and has the same information.

Feature E5. Described in feature E4, the number of bits of the bit group read by the information reading means into the read target area is larger than the number of bits of information set in the storage area in one predetermined byte unit. Game machine.

According to the feature E5, information having a data capacity exceeding a predetermined byte can be read out from the information storage means to the read target area. In addition, information having a data capacity exceeding a predetermined byte can be aggregated in the information storage means.

Feature E6. The reference bit information and the bit group including some bits among the plurality of bits in the storage area specified by the area specifying means to specify the storage area in the predetermined byte unit corresponding to the designated address information are used as the reference bit information. Specifying as a use target based on the reference number information, reading the bit group specified as a use target by the bit specifying means into the read target area, and bits for which information was not read in the read target area. It is characterized in that the instruction to make one of the above binary information the same information is aggregated as a specific instruction (LDB instruction, LDB update instruction, special LDB instruction). The gaming machine according to the feature E4 or E5.

According to the feature E6, the process of specifying the storage area in predetermined byte units corresponding to the designated address information, and the bit group including some bits among the plurality of bits in the storage area specified by the area specifying means are used as reference bit information. The processing of specifying the bit group as the usage target based on the reference number information, the processing of reading the bit group specified as the usage target by the bit specifying means into the reading target area, and the information of the bits for which the information was not read in the reading target area are 2 It is possible to execute a process of making one of the value information the same information with one instruction. Therefore, the configuration of the program for executing these processes can be simplified as compared with the configuration in which a plurality of instructions are set in the program to execute these processes, and the data of the program can be simplified. The capacity can be reduced.

Feature E7. In the specific instruction, information (acquired data designation data) that specifies predetermined information (acquired data designation data) used for calculating the designated address information and the reference bit information is stored in the HL register 107. The gaming machine according to feature E6, wherein the designated address information and the reference bit information are not set.

According to the feature E7, the specified address information and the reference bit information are set in the specific instruction and the predetermined information used for calculating the designated address information and the reference bit information is set, and the designated address information and the reference bit information are not set. Compared with the configuration in which the designated address information and the reference bit information are set in the instruction, the data capacity of the information set in the specific instruction can be reduced.

Feature E8. The gaming machine according to feature E7, wherein the reference number information is set in the specific command.

According to the feature E8, the number of bits to be used as the reference for use can be specified by setting the reference number information in the specific instruction.

Feature E9. The gaming machine according to feature E7 or E8, wherein the specific instruction is not set with information that specifies a method of calculating the designated address information and the reference bit information using the predetermined information.

According to the feature E9, the data capacity of the information set in the specific instruction is reduced as compared with the configuration in which the information specifying the method for calculating the designated address information and the reference bit information is set in the specific instruction. Can be done.

Feature E10. The first predetermined information (in the first embodiment, the acquired data designation data in the LDB instruction and the LDB update instruction) of the first predetermined number of bits (“13” in the first embodiment, “12” in the sixth embodiment). The upper 13-bit data, in the sixth embodiment, the upper 12-bit data of the acquired data designation data in the special LDB instruction) and the second predetermined number of bits arranged on the lower side of the first predetermined information (first). The second predetermined information (in the first embodiment, the data of the lower three bits of the acquired data designation data in the LDB instruction and the LDB update instruction, the sixth) of the second predetermined information (“3” in the embodiment and “4” in the sixth embodiment). In the embodiment of the above, a means for reading predetermined information (acquired data designation data) having (lower 4 bits of data of the acquisition data designation data in the special LDB instruction) (a function of executing the LDB instruction by the LDB execution circuit 157, LDB update execution circuit 161). It has a function to execute the LDB update command by the special LDB execution circuit 201 and a function to execute the special LDB command by the special LDB execution circuit 201).
The area specifying means
By executing a predetermined arithmetic process on the predetermined information, the quotient is obtained by dividing by a binary value "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. Derivation means for deriving the corresponding information (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, function to execute special LDB instruction by special LDB execution circuit 201) ,
Address generation means for generating the designated address information using the information derived by the derivation means (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, special A function to execute a special LDB instruction by the LDB execution circuit 201) and
The gaming machine according to any one of features E1 to E9.

According to the feature E10, by executing a predetermined arithmetic process on the predetermined information, the division is performed by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. Information corresponding to the quotient of the case can be derived. Then, the designated address information can be generated by using the information derived by the derivation means.

Feature E11. The first predetermined information and the second predetermined information are continuous in the order of arrangement of bits.
The lowest bit of the second predetermined information is the lowest bit of the predetermined information.
The information derived by the derivation means is characterized in that the information is arranged so that the lowest bit in the bit array of the first predetermined information is the lowest bit of the derived information. The gaming machine described in E10.

According to the feature E11, by executing a predetermined arithmetic process on the predetermined information, the lowest bit in the bit array of the first predetermined information becomes the lowest bit of the derived information. The first predetermined information in the information can be shifted to the lower side by the number of the second predetermined bits.

Feature E12. Of the information derived by the derivation means, each bit existing on the upper side of the bit array of the first predetermined information is the same information (information of "0") which is one of the binary information. The gaming machine according to the feature E10 or E11.

According to the feature E12, by executing a predetermined arithmetic process on the predetermined information, the same information, which is one of the binary information, is generated in each bit existing on the upper side of the bit array of the first predetermined information. The set information can be generated and the information can be used.

Feature E13. The bit specifying means is an information extraction means (a function of executing an LDB instruction by the LDB execution circuit 157, an LDB update by the LDB update execution circuit 161) that extracts the second predetermined information from the predetermined information and generates the reference bit information. The gaming machine according to any one of features E10 to E12, characterized in that it has a function of executing an instruction and a function of executing a special LDB instruction by a special LDB execution circuit 201).

According to the feature E13, in a configuration in which the first predetermined information and the second predetermined information are aggregated into the predetermined information, the second predetermined information can be extracted from the predetermined information to generate the reference bit number information.

Feature E14. The information extracting means includes information including the second predetermined information (lower 1 byte of acquired data designation data) and mask data (data "000000111B" in the LDB instruction and LDB update instruction, and data "000001111B" in the special LDB instruction. The gaming machine according to feature E13, characterized in that the second predetermined information is extracted from the predetermined information by the calculation of the logical product with).

According to the feature E14, by using the mask data, the first predetermined information included in the predetermined information can be masked and the second predetermined information included in the predetermined information can be extracted.

Feature E15. The gaming machine according to any one of features E10 to E14, wherein the predetermined information is information in units of the predetermined bytes.

According to the feature E15, the first predetermined information and the second predetermined information can be aggregated into predetermined information in predetermined byte units. Therefore, it is possible to reduce the total data capacity of these information as compared with the configuration in which the information that enables the second predetermined information is present separately from the information that enables the first predetermined information. can.

It should be noted that, with respect to the configuration of the features E1 to E15, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1. Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic F group>
Features F1. In a gaming machine in which an address is set for each storage area of a predetermined byte unit (1 byte unit) among the storage areas provided in the information storage means (main side ROM 64).
Area specification that specifies the storage area in predetermined byte units corresponding to the specified address information (acquisition start address calculated from the acquired data specified data stored in the HL register 107 in the LDB instruction, LDB update instruction, and special LDB instruction). Means (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, function to execute special LDB instruction by special LDB execution circuit 201), and
The information stored in some bits of the storage area specified by the area specifying means is read into the predetermined byte unit read target area (W register 104a or HL register 107 of the transfer destination in the LDB instruction, LDB update instruction). The information of the bit that was read to the transfer destination WA register 104, W register 104a or B register 105a, and the transfer destination HL register 107) in the special LDB instruction and the information was not read in the read target area is binary information. Information reading means (function for executing LDB instruction by LDB execution circuit 157, LDB update instruction by LDB update execution circuit 161) to be predetermined binary information (information of "0") which is one of the two. Function, function to execute special LDB instruction by special LDB execution circuit 201),
A gaming machine characterized by being equipped with.

According to the feature F1, the information stored in some bits of the storage area of a predetermined byte unit can be read out to the read target area and used. A state in which the information stored in some of the bits is read in the read target area, and the information of the bits in which the information is not read in the read target area is the predetermined binary information. As a result, the information of the read target area can be used. Since the information stored in some bits of the storage area in a predetermined byte unit can be read out to the read target area and used, the information can be aggregated and set in the information storage means. As a result, the data capacity of the information stored in the information storage means can be reduced.

Feature F2. To specify the storage area of the predetermined byte unit corresponding to the designated address information, and to read the information stored in some bits of the storage area specified by the area specifying means into the read target area. The instruction to make the information of the bit for which the information is not read in the read target area becomes the predetermined binary information is aggregated into the predetermined transfer instruction (LDB instruction, LDB update instruction, special LDB instruction). The gaming machine according to the feature F1 characterized by being present.

According to the feature F2, the process of specifying the storage area in predetermined byte units corresponding to the designated address information and the information stored in some bits of the storage area specified by the area specifying means are read out to the read target area. The process of making the information of the bit for which the information is not read in the read target area becomes the predetermined binary information can be executed by one instruction. Therefore, the configuration of the program can be simplified and the data capacity of the program can be reduced as compared with the configuration in which a plurality of instructions are set to execute these processes.

Feature F3. The information reading means stores information stored in some bits of the storage area specified by the area specifying means in a lower area including the lowest bit in the read target area (lower of WA register 104). Bits, lower bits of the W register 104a, lower bits of the B register 105a, lower bits of the HL register 107), and the upper area (WA) arranged on the upper side of the lower area in the read target area. Described in the feature F1 or F2, wherein the predetermined binary information is set in each bit in the upper bit of the register 104, the upper bit of the W register 104a, the upper bit of the B register 105a, and the upper bit of the HL register 107). Game machine.

According to the feature F3, the information stored in some bits of the storage area specified by the area specifying means can be set in the lower area of the read target area. Predetermined binary information is set for each bit in the upper region in the read target area. Therefore, while eliminating the need for the process of clearing the read target area in advance, only the information stored in some bits of the storage area specified by the area specifying means and the predetermined binary information are set in the read target area. It can be in the state of being.

Features F4. Features F1 to F3 characterized in that the information read by the information reading means into the read target area is information of some bits having a continuous arrangement order in the storage area specified by the area specifying means. The gaming machine according to any one of.

According to the feature F4, the information stored in some bits of the storage area specified by the area specifying means is read out to the read target area and used in such a manner that the arrangement order of the some bits is maintained. can do.

Feature F5. The gaming machine according to any one of features F1 to F4, wherein the number of bits of information read into the read target area by the information reading means is a bit number larger than the predetermined byte.

According to the feature F5, in the information storage means, information having a larger number of bits than the number of bits of information set in the storage area of one predetermined byte corresponding to one address can be read out to the read target area.

Feature F6. The read target area is a predetermined register provided in the control means (W register 104a or HL register 107 of the transfer destination in the LDB instruction, WA register 104, W register 104a or B register 105a of the transfer destination in the LDB update instruction, special. The gaming machine according to any one of features F1 to F5, characterized in that it is a transfer destination HL register 107) in an LDB instruction.

According to the feature F6, the control means can easily access a predetermined register from which the information stored in some bits of the storage area specified by the area specifying means is read.

Feature F7. The information reading means is a bit number specifying means for specifying the number of bits of information to be read from the storage area specified by the area specifying means to the read target area (a function of executing an LDB instruction in the LDB execution circuit 157, LDB update). The gaming machine according to any one of features F1 to F6, characterized in that it has a function of executing an LDB update command in the execution circuit 161 and a function of executing a special LDB command in the special LDB execution circuit 201).

According to the feature F7, information can be read out to the read target area by designating the number of bits from the information storage means. Therefore, information can be aggregated and set in the information storage means in bit units. As a result, the data capacity of the information stored in the information storage means can be reduced.

It should be noted that, with respect to the configuration of the features F1 to F7, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic G group>
Features G1. The first predetermined information (in the first embodiment, the acquired data designation data in the LDB instruction and the LDB update instruction) of the first predetermined number of bits (“13” in the first embodiment, “12” in the sixth embodiment). The upper 13-bit data, in the sixth embodiment, the upper 12-bit data of the acquired data designation data in the special LDB instruction) and the second predetermined number of bits arranged on the lower side of the first predetermined information (first). The second predetermined information (in the first embodiment, the data of the lower three bits of the acquired data designation data in the LDB instruction and the LDB update instruction, the sixth) of the second predetermined information (“3” in the embodiment and “4” in the sixth embodiment). In the embodiment of the above, a means for reading predetermined information (acquired data designation data) having (lower 4 bits of data of the acquisition data designation data in the special LDB instruction) (a function of executing the LDB instruction by the LDB execution circuit 157, LDB update execution circuit 161). (Function to execute LDB update command by, function to execute special LDB command by special LDB execution circuit 201),
When a predetermined arithmetic process is executed on the read predetermined information and the binary number is divided by a binary value "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. Derivation means for deriving information corresponding to the quotient (function to execute LDB instruction by LDB execution circuit 157, function to execute LDB update instruction by LDB update execution circuit 161, function to execute special LDB instruction by special LDB execution circuit 201). )When,
A gaming machine characterized by being equipped with.

According to the feature G1, by executing a predetermined arithmetic process on the predetermined information, the division is performed by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. Information corresponding to the quotient of the case can be derived.

Feature G2. The first predetermined information and the second predetermined information are continuous in the order of arrangement of bits.
The lowest bit of the second predetermined information is the lowest bit of the predetermined information.
The information derived by the derivation means is characterized in that the information is arranged so that the lowest bit in the bit array of the first predetermined information is the lowest bit of the derived information. The gaming machine described in G1.

According to the feature G2, by executing a predetermined arithmetic process on the predetermined information, the lowest bit in the bit array of the first predetermined information becomes the lowest bit of the derived information. The first predetermined information in the information can be shifted to the lower side by the number of the second predetermined bits.

Feature G3. Of the information derived by the derivation means, each bit existing on the upper side of the bit array of the first predetermined information is the same information (information of "0") which is one of the binary information. The gaming machine according to the feature G1 or G2.

According to the feature G3, by executing a predetermined arithmetic process on the predetermined information, the same information, which is one of the binary information, is generated in each bit existing on the upper side of the bit array of the first predetermined information. The set information can be generated and the information can be used.

Features G4. Information extraction means for extracting the second predetermined information from the predetermined information (a function of executing an LDB instruction by the LDB execution circuit 157, a function of executing an LDB update instruction by the LDB update execution circuit 161), and a special LDB by the special LDB execution circuit 201. The gaming machine according to any one of features G1 to G3, characterized in that it has a function of executing a command).

According to the feature G4, in a configuration in which the first predetermined information and the second predetermined information are aggregated into the predetermined information, the second predetermined information can be extracted from the predetermined information and the second predetermined information can be used independently. can.

Feature G5. The information extracting means includes information including the second predetermined information (lower 1 byte of acquired data designation data) and mask data (data "000000111B" in the LDB instruction and LDB update instruction, and data "000001111B" in the special LDB instruction. The gaming machine according to feature G4, characterized in that the second predetermined information is extracted from the predetermined information by the calculation of the logical product with).

According to the feature G5, by using the mask data, the first predetermined information included in the predetermined information can be masked and the second predetermined information included in the predetermined information can be extracted.

Feature G6. The quotient when the predetermined information is divided by a binary value "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits by executing the predetermined arithmetic processing. The instruction for deriving the information corresponding to the above and extracting the second predetermined information from the predetermined information is aggregated into a predetermined instruction (LDB instruction, LDB update instruction, special LDB instruction). Features The gaming machine according to G4 or G5.

According to the feature G6, by executing a predetermined arithmetic process on the predetermined information, the division is performed by a binary value that is "1" larger than the maximum value of the binary numerical information that can be set by the second predetermined number of bits. The process of deriving the information corresponding to the quotient of the case and the process of extracting the second predetermined information from the predetermined information can be executed with one command. Therefore, the configuration of the program for executing these two processes can be simplified and the program can be simplified as compared with the configuration in which a plurality of instructions are set in the program to execute these two processes. Data capacity can be reduced.

Feature G7. The gaming machine according to any one of features G1 to G6, wherein the predetermined information is information in units of predetermined bytes.

According to the feature G7, the first predetermined information and the second predetermined information can be aggregated into predetermined information in predetermined byte units. Therefore, it is possible to reduce the total data capacity of these information as compared with the configuration in which the information that enables the second predetermined information is present separately from the information that enables the first predetermined information. can.

Features G8. The gaming machine according to any one of features G1 to G7, wherein the data capacity of the predetermined information is 2 bytes.

According to the feature G8, the data capacity of the predetermined information in which the first predetermined information and the second predetermined information are aggregated can be suppressed to 2 bytes.

Feature G9. Information storage means (main side ROM64) in which an address is set for each storage area in a predetermined byte unit (1 byte unit), and
Area specifying means for specifying the storage area in predetermined byte units using the information derived by the derivation means (a function of executing the LDB instruction by the LDB execution circuit 157, and executing the LDB update instruction by the LDB update execution circuit 161). Function, function to execute special LDB instruction by special LDB execution circuit 201),
Bit identification means for specifying a bit group including some bits among a plurality of bits in the storage area specified by the area identification means (a function of executing an LDB instruction by the LDB execution circuit 157, LDB update execution). A function to execute an LDB update instruction by the circuit 161 and a function to execute a special LDB instruction by the special LDB execution circuit 201), and
The gaming machine according to any one of the features G1 to G8.

According to the feature G9, the storage area in predetermined byte units can be specified by using the information derived by the derivation means using the predetermined information. A bit group including some bits among a plurality of bits in the storage area specified by the area specifying means can be specified as a usage target. Since the information can be aggregated in the information storage means in bit units, the data capacity of the information stored in the information storage means can be reduced.

Feature G10. Information extraction means for extracting the second predetermined information from the predetermined information (a function of executing an LDB command by the LDB execution circuit 157, a function of executing an LDB update command by the LDB update execution circuit 161), and a special LDB by the special LDB execution circuit 201. Equipped with a function to execute instructions)
The bit specifying means uses the second predetermined information extracted by the information extracting means to obtain a bit group including some bits among a plurality of bits in the storage area specified by the area specifying means. The gaming machine according to feature G9, which is characterized by being specified as a target of use.

According to the feature G10, in a configuration having the configuration of the feature G9 and capable of specifying a storage area in predetermined byte units by using predetermined information, the second predetermined information extracted from the predetermined information is used. , A bit group including some bits among a plurality of bits in the storage area specified by the area specifying means can be specified as a usage target. Information for specifying a storage area in units of predetermined bytes and information for specifying a bit group to be used can be aggregated in predetermined information. As a result, it is possible to reduce the total data capacity of the information for specifying the storage area in predetermined byte units and the information for specifying the bit group to be used.

It should be noted that, with respect to the configuration of the features G1 to G10, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to H1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

According to the inventions relating to the feature C group, the feature D group, the feature E group, the feature F group, and the feature G group, the following problems can be solved.

Pachinko machines and slot machines are known as game machines. For example, the pachinko machine is provided with a dish storage section for storing the game balls given to the player on the front portion of the game machine, and the game balls stored in the dish storage section are guided to the game ball launcher. It is fired toward the game area according to the player's firing operation. Then, for example, when the game ball enters the ball entry section provided in the game area, the game ball is dispensed from the payout device to the dish storage section, for example. Further, in a pachinko machine, a configuration in which an upper plate storage unit and a lower plate storage unit are provided as a plate storage unit is also known. In this case, the game ball stored in the upper plate storage unit is a game ball launching device. The game ball that has become surplus in the upper dish storage section is discharged to the lower dish storage section.

Further, in the slot machine, when the start lever is operated and a new game is started in the situation where the medal is bet, the lottery process is executed by the control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means operates. The rotation of the reel is stopped by executing the rotation stop control. Then, when the stop result after the reel rotation is stopped corresponds to the winning combination in the lottery process, the privilege corresponding to the winning combination is given to the player.

Here, in a gaming machine such as the above example, various processes need to be suitably executed, and there is still room for improvement in this respect.

<Characteristic H group>
Features H1. A transmission means for transmitting a predetermined information group (command for communication) (a function of executing the processing of steps S2001 to S2008 in the main CPU 63, a function of executing the processing of steps S2101 to S2113 in the main CPU 63, and a main CPU 63. The function of executing the process of steps S2201 to S2215 in the main CPU 63, and the function of executing the process of steps S2301 to S2317 in the main CPU 63) are provided.
The predetermined information group includes a plurality of unit information (header HD, data frames FR1 to FR10, highest frame SF1, SF2, footer FT) in predetermined byte units (1 byte unit).
In the unit information of the predetermined byte unit at the beginning of the predetermined information group, the information of the bit (most significant bit) at the predetermined position is the specific bit information (information of "1").
The gaming machine characterized in that the unit information of the predetermined byte unit other than the head in the predetermined information group is the information of the bit at the predetermined position other than the specific bit information (information of "0").

According to the feature H1, the discrimination between the unit information of the first predetermined byte unit and the unit information of the predetermined byte unit other than the beginning is based on the state of the bit at the predetermined position in the unit information of each predetermined byte unit of the predetermined information group. Can be made possible. By making it possible to grasp the unit information of the first predetermined byte unit, it is possible to grasp the demarcation position between the predetermined information groups when a plurality of predetermined information groups are received.

Feature H2. The gaming machine according to feature H1, wherein the bit at the predetermined position is 1 bit.

According to the feature H2, the number of bits of the bit set in the unit information of each predetermined byte unit is minimized so that the unit information of the predetermined byte unit at the beginning and the unit information of the predetermined byte unit other than the beginning can be distinguished. Can be "1". As a result, in the unit information of each predetermined byte unit, the number of bits in which information other than the information for making it possible to distinguish between the unit information of the predetermined predetermined byte unit at the beginning and the unit information of the predetermined byte unit other than the beginning is increased. Can be secured.

Feature H3. The gaming machine according to feature H1 or H2, wherein the bit at the predetermined position is the most significant bit (7th bit) in the unit information of the predetermined byte unit.

According to the feature H3, it is possible to distinguish between the unit information of the first predetermined byte unit and the unit information of the predetermined byte unit other than the first, based on the state of the most significant bit in the unit information of each predetermined byte unit. can.

Features H4. In the predetermined information group, one or more predetermined unit information (data frames FR1 to FR10) as unit information of the predetermined byte unit other than the head thereof, and the predetermined unit information in the predetermined unit information after receiving the predetermined information group. The gaming machine according to any one of the features H1 to H3, characterized in that the aggregated unit information (highest frame SF1, SF2) in which the information set in the position bit is aggregated is set.

According to the feature H4, in the configuration in which the bit at the predetermined position in the unit information of the predetermined byte unit other than the head is the information other than the specific bit information in the predetermined information group, it is based on the aggregate unit information set in the predetermined information group. It is possible to grasp the information set in the bit at the predetermined position in the predetermined unit information after receiving the predetermined information group. Further, the number of times of transmission / reception of the information group can be reduced as compared with the configuration in which the information of the bit at the predetermined position in the predetermined unit information is transmitted as another information group.

Feature H5. The gaming machine according to feature H4, wherein the information of the bit at the predetermined position in the aggregate unit information is information other than the specific bit information.

According to the feature H5, it is possible to distinguish between the unit information of the first predetermined byte unit and the aggregate unit information based on the information of the bit at the predetermined position in the unit information of the predetermined byte unit.

Feature H6. The gaming machine according to feature H5, wherein no identification information indicating that the aggregated unit information is set is set in the aggregated unit information.

According to the feature H6, as compared with the configuration in which the identification information indicating that the aggregated unit information is set is set in the aggregated unit information, the bit at a predetermined position in the predetermined unit information is set after the predetermined information group is received in the aggregated unit information. It is possible to prevent the number of bits for which the information to be set can be set to decrease.

Feature H7. The unit information is information in 1-byte units.
The gaming machine according to any one of features H4 to H6, wherein one aggregated unit information is set for seven predetermined unit information set in the predetermined information group.

According to the feature H7, by setting the information of the bit at the predetermined position in the seven predetermined unit information in the aggregate unit information, it is possible to grasp the information of the bit at the predetermined position in the seven predetermined unit information. can. In the aggregate unit information, one bit in which the information of the bit at the predetermined position in the predetermined unit information is not set can be used to make it possible to distinguish the unit information of the first 1-byte unit and the aggregate unit information.

Feature H8. When the number of the predetermined unit information included in the predetermined information group is a multiple of "7", the number of the predetermined unit information included in the predetermined information group is divided by "7". When the aggregated unit information of the number of quotients is set in the predetermined information group and the number of the predetermined unit information included in the predetermined information group is not a multiple of "7", the predetermined information group is used. A feature characterized in that a number of aggregated unit information larger than the number of quotients when the number of included predetermined unit information is divided by "7" is set in the predetermined information group. The gaming machine according to any one of H4 to H7.

According to the feature H8, for all the predetermined unit information included in the predetermined information group, the information set in the bit at the predetermined position in the predetermined unit information after the reception of the predetermined information group is set in the aggregate unit information. Can be done.

Feature H9. In the predetermined information group, the aggregated unit information in which the information set in the bit at the predetermined position in the six or less consecutive predetermined unit information including the last predetermined unit information is aggregated is the last predetermined unit. The gaming machine according to any one of features H4 to H8, which is set as unit information in the predetermined byte unit after one of the information.

According to the feature H9, based on the aggregated unit information set after one of the last predetermined unit information, it is set to a bit at a predetermined position in six or less consecutive predetermined unit information including the last predetermined unit information. It is possible to grasp the information to be received. By setting the aggregated unit information after one of the last predetermined unit information, it is possible to easily grasp the position of the aggregated unit information.

Feature H10. In the predetermined information group, the aggregation in which the bits at the predetermined positions in the seven consecutive predetermined unit information are aggregated in the unit information of the predetermined byte unit immediately after the seven consecutive predetermined unit information. The gaming machine according to any one of features H4 to H9, characterized in that unit information is set.

According to the feature H10, it is possible to grasp the information set in the bit at the predetermined position in the seven consecutive predetermined unit information set before the aggregate unit information based on the aggregate unit information. .. Even when seven or more predetermined unit information is set in the predetermined information group, the information set in the bit at the predetermined position in all the predetermined unit information included in the predetermined information group is set as the aggregate unit information. It can be grasped.

Features H11. The tail information (footer FT) is set at the tail of the predetermined information group, and the tail information (footer FT) is set.
The gaming machine according to any one of features H4 to H10, wherein the aggregated unit information is set as unit information of the predetermined byte unit immediately before the last information.

According to the feature H11, it is possible to easily grasp the position of the aggregate unit information set immediately before the last information with the tail information as a reference. In addition, it is possible to easily grasp the tail of the predetermined information group based on the tail information.

Feature H12. Predetermined information storage means (display duration counter 142) in which predetermined information (display duration data) is set, and
Predetermined process execution means (process of steps S904 to S906 in the main CPU 63) for executing a predetermined process (process for grasping the display duration in the game round) using the predetermined information set in the predetermined information storage means. Function to execute) and
Equipped with
When the predetermined information group is set with the predetermined information stored in the predetermined information storage means as the predetermined unit information, the transmission means sets the bit at the predetermined position in the predetermined unit information as the aggregation unit. Features H4 to H11 characterized in that the information is set to the bit corresponding to the predetermined unit information so that the information of the bit at the predetermined position is the information on the side of the binary information that is not the specific bit information. The gaming machine according to any one of.

According to the feature H12, the information of the bit at the predetermined position in the predetermined unit information included in the predetermined information group is the binary information while preventing the predetermined information stored in the predetermined information storage means from being changed. Of these, the information can be set to be information on the side that is not specific bit information. Therefore, the predetermined information stored in the predetermined information storage means can be used even after the transmission of the predetermined information group.

Feature H13. In the predetermined information group, one or more predetermined unit information (data frames FR1 to FR10) as unit information of the predetermined byte unit other than the head thereof, and the predetermined unit information in the predetermined unit information after receiving the predetermined information group. Aggregation unit information (highest frame SF1, SF2), in which the information set in the position bits is aggregated, is set.
A predetermined conversion means (sound / light side CPU 93) that converts the received predetermined information group into a predetermined conversion information group (command after conversion) in which the specific bit information can be set for the bit at the predetermined position in the predetermined unit information. The gaming machine according to any one of features H1 to H12, characterized in that it has a function of executing a first command conversion process in the above, and a function of executing a second command conversion process in the sound and light side CPU 93).

According to the feature H13, the configuration of the feature H1 is provided, and the unit information of the first predetermined byte unit and the predetermined byte unit other than the first are based on the state of the bit at the predetermined position in the unit information of each predetermined byte unit of the predetermined information group. The predetermined information group can be converted into a predetermined post-conversion information group in which specific bit information can be set for a bit at a predetermined position in the predetermined unit information at the time of use, while having a configuration that can be distinguished from the unit information of.

Feature H14. In the predetermined information group, aggregated unit information (highest-order frames SF1 and SF2) in which the information set in the bit at the predetermined position in the predetermined unit information is aggregated after the reception of the predetermined information group is set.
The predetermined conversion means sets the predetermined information group to the bit (seventh bit) at the predetermined position in the predetermined unit information corresponding to the bit by setting the information set in the bit of the aggregate unit information. The gaming machine according to feature H13, which is characterized in that it is converted into an information group after a predetermined conversion.

According to the feature H14, the received predetermined information group is converted into a predetermined converted information group in which the information set in the bit of the aggregate unit information is set in the bit at the predetermined position in the predetermined unit information corresponding to the bit. be able to.

Feature H15. The predetermined conversion means obtains the predetermined unit information corresponding to the bit of the aggregate unit information included in the predetermined information group based on the position of the bit in the aggregate unit information and the data capacity of the predetermined information group. The gaming machine according to feature H13 or H14, which is characterized by grasping.

According to the feature H15, the predetermined unit information corresponding to the bit is grasped based on the position of the bit in the aggregated unit information included in the predetermined information group and the data capacity of the predetermined information group. It is possible to reduce the data capacity of the predetermined information group by eliminating the need to set the dedicated information for making it possible to grasp the predetermined unit information corresponding to the bit in the predetermined information group.

It should be noted that, with respect to the configuration of the features H1 to H15, the features A1 to A11, the features B1 to B6, the features C1 to C6, the features D1 to D24, the features E1 to E15, the features F1 to F7, the features G1 to G10, and the features H1 to 1 Any one or more configurations of H15 may be applied. This makes it possible to produce a synergistic effect due to the combined configuration.

According to the invention according to the above-mentioned feature H group, the following problems can be solved.

Pachinko machines and slot machines are known as game machines. For example, the pachinko machine is provided with a dish storage section for storing the game balls given to the player on the front portion of the game machine, and the game balls stored in the dish storage section are guided to the game ball launcher. It is fired toward the game area according to the player's firing operation. Then, for example, when the game ball enters the ball entry section provided in the game area, the game ball is dispensed from the payout device to the dish storage section, for example. Further, in a pachinko machine, a configuration in which an upper plate storage unit and a lower plate storage unit are provided as a plate storage unit is also known. In this case, the game ball stored in the upper plate storage unit is a game ball launching device. The game ball that has become surplus in the upper dish storage section is discharged to the lower dish storage section.

Further, in the slot machine, when the start lever is operated and a new game is started in the situation where the medal is bet, the lottery process is executed by the control means. Further, when the lottery process is executed, the rotation start control is executed by the control means to start the rotation of the reel, and when the stop button is operated during the rotation of the reel, the control means operates. The rotation of the reel is stopped by executing the rotation stop control. Then, when the stop result after the reel rotation is stopped corresponds to the winning combination in the lottery process, the privilege corresponding to the winning combination is given to the player.

Here, in a gaming machine such as the above example, it is necessary to preferably transmit an information group, and there is still room for improvement in this respect.

The following shows the basic configuration of a gaming machine to which each of the above features can be applied or is applied to each feature.

Pachinko gaming machine: An operating means operated by a player, a game ball launching means for launching a game ball based on the operation of the operating means, a ball passage for guiding the launched game ball to a predetermined game area, and a game. A gaming machine that includes each gaming component arranged in an area and grants a privilege to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

Rotating machine such as a slot machine: Equipped with a picture display device that variably displays a plurality of pictures, the variable display of the plurality of pictures is started due to the operation of the start operation means, and is caused by the operation of the stop operation means. A gaming machine in which the variable display of the plurality of symbols is stopped after a lapse of a predetermined time, and a privilege is given to the player according to the symbols after the stop.

10 ... Pachinko machine, 63 ... Main CPU, 64 ... Main ROM, 64q ... Special electric address table, 64r ... Fluctuation start table, 64w ... Hard random maximum value table, 64y ... First initialization table, 64z ... 2nd initialization table, 64α ... random maximum value table, 93 ... sound light side CPU, 104 ... W register, 104a ... W register, 104b ... A register, 105a ... B register, 106b ... E register, 107 ... HL register, 109 ... IY register, 111 ... TP register, 142 ... Display continuation counter, 149 ... LDT execution circuit, 151 ... LD update execution circuit, 152 ... LDH update execution circuit, 156 ... 1st LDY execution circuit, 157 ... LDB execution circuit, 161 ... LDB update execution circuit, 164 ... 2nd LDY execution circuit, 191a ... jackpot type maximum value counter, 192a ... reach random number maximum value counter, 193a ... general electric random number maximum value counter, 201 ... special LDB execution circuit, FR1 to FR10 ... data Frame, FT ... footer, HD ... header, SA0 to SA6 ... start address, SB0 to SB23 ... start address, SF1 ... first highest frame, SF2 ... second highest frame.

Claims (6)

An address identification means for specifying a specific address to be referred to by using a specific address information group in which a plurality of address information is set, and
A specific process execution means that executes a specific process using the storage area corresponding to the specific address specified by the address specific means, and a specific process execution means.
In a gaming machine equipped with
The specific address specified by the address specifying means by using the specific address information group has common information of a predetermined range of bits among a plurality of bits included in the specific address.
The gaming machine is provided with specific storage means capable of storing information in the predetermined range of bits.
A gaming machine characterized in that information other than the bits in the predetermined range among the plurality of bits included in the specific address is set in the address information included in the specific address information group. The gaming machine according to claim 1, wherein the specific storage means is a predetermined register provided in the control means. In the specific address information group, address information of a plurality of setting target areas and numerical information set in the plurality of setting target areas are set.
The address specifying means uses the specific address information group to specify the address of the setting target area to be referred to, and the address specifying means determines the address of the setting target area.
As the specific process, the specific process executing means executes a process of setting the numerical information in the setting target area corresponding to the address specified by the address specifying means.
Of the plurality of bits included in the address of the setting target area, the information of the bits in the predetermined range is common.
In the specific address information group, information other than the bits in the predetermined range among the plurality of bits included in the address of the setting target area is set.
The gaming machine according to claim 1 or 2, wherein the address information of the setting target area set in the specific address information group has the same data capacity as the numerical information. The gaming machine according to any one of claims 1 to 3, wherein the specific storage means includes a setting means for setting bit information in the predetermined range at the start of supply of operating power. The bit information in the predetermined range stored in the specific storage means is also used when specifying another address to be referred to by using another address information group in which a plurality of address information is set. The gaming machine according to any one of claims 1 to 4, wherein the gaming machine is characterized by the above. The information according to any one of claims 1 to 5, wherein the information other than the bits in the predetermined range is information arranged on the lower side of the information of the bits in the predetermined range at the specific address. Game machine.

Images