JP7252492B2 - 同期検波装置、同期検波方法及びプログラム - Google Patents
同期検波装置、同期検波方法及びプログラム Download PDFInfo
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- JP7252492B2 JP7252492B2 JP2021534500A JP2021534500A JP7252492B2 JP 7252492 B2 JP7252492 B2 JP 7252492B2 JP 2021534500 A JP2021534500 A JP 2021534500A JP 2021534500 A JP2021534500 A JP 2021534500A JP 7252492 B2 JP7252492 B2 JP 7252492B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1255—Synchronisation of the sampling frequency or phase to the input frequency or phase
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/06—Demodulator circuits; Receiver circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Description
(第1実施形態)
図1は、フィードバックシステム1aの構成の例を示す図である。フィードバックシステム1aは、同期検波装置10a(同期検波回路)を備える。
図5は、フィードバックシステム1aの動作の例を示すフローチャートである。波形補正部106の補正部400は、ディザ信号が重畳された波形(モニタ部14aの出力)のサンプリングデータを、ディザ信号の周期「Td」に応じたリファレンスクロック(RefClk)の周期「Td/m」(mは、自然数であり、例えば「3」)ごとに補正する(ステップS101)。
第2実施形態では、周波数「fd」ではなくm次(mは、奇数の自然数)の高調波「m×fd」のディザ成分が同期検波される点が、第1実施形態と相違する。第2実施形態では、第1実施形態との相違点を説明する。
-(dK_3+dK_4+dK_7+dK_8+dK_11+dK_12)
…(3)
正しい識別結果は「Hi-Hi-Lo-Lo-Hi-Hi-Lo-Lo-Hi-Hi-Lo-Lo」であるが、「d2_5」及び「d2_6」の識別結果が誤りである。
正しい識別結果は「Lo-Lo-Hi-Hi-Lo-Lo-Hi-Hi-Lo-Lo-Hi-Hi」であるが、「d2_5」及び「d2_6」以外の各識別結果が誤りである。
第3実施形態では、ディザ信号発生器の出力が、正値と負値とを交互に繰り返す信号(交番信号)ではなく、特定パターンを繰り返す信号である点が、第1実施形態及び第2実施形態と相違する。第3実施形態では、第1実施形態及び第2実施形態との相違点を説明する。
波形補正部106は、添字「K」のサンプリングデータ「dK_L」を、図4に示された例と同様に、定数「dmax」と定数「dmin」とに2値化する。
Claims (6)
- ディザ信号が重畳された波形のサンプリングデータを、前記ディザ信号の周期に応じたリファレンス信号の周期ごとに補正する補正部と、
前記リファレンス信号のレベルごとに異なる重み係数であって、前記リファレンス信号のタイミングに対応付けられた前記重み係数を、補正された前記サンプリングデータに乗算する乗算部と、
補正された前記サンプリングデータと前記重み係数との乗算結果の平均を検波結果として導出する平均化部と
を備える同期検波装置。 - 前記補正部は、前記リファレンス信号の強度変化とは相関しない強度変化が前記サンプリングデータにおいて検出された場合、前記サンプリングデータの強度変化を抑圧する、請求項1に記載の同期検波装置。
- 前記補正部は、前記リファレンス信号との一定値以上の相関又は逆相関を有する強度変化が前記波形において検出された場合、前記波形に重畳されている前記ディザ信号の周波数成分を強調する、請求項1に記載の同期検波装置。
- 前記補正部は、前記リファレンス信号の符号パターンに対して矛盾する強度変化が前記波形において検出された場合、前記強度変化を抑圧する、請求項1に記載の同期検波装置。
- 同期検波装置が実行する同期検波方法であって、
ディザ信号が重畳された波形のサンプリングデータを、前記ディザ信号の周期に応じたリファレンス信号の周期ごとに補正する補正ステップと、
前記リファレンス信号のレベルごとに異なる重み係数であって、前記リファレンス信号のタイミングに対応付けられた前記重み係数を、補正された前記サンプリングデータに乗算する乗算ステップと、
補正された前記サンプリングデータと前記重み係数との乗算結果の平均を検波結果として導出する平均化ステップと
を含む同期検波方法。 - 請求項1から請求項4のいずれか一項に記載の同期検波装置としてコンピュータを機能させるためのプログラム。
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PCT/JP2019/029147 WO2021014629A1 (ja) | 2019-07-25 | 2019-07-25 | 同期検波装置、同期検波方法及びプログラム |
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JPWO2021014629A1 JPWO2021014629A1 (ja) | 2021-01-28 |
JP7252492B2 true JP7252492B2 (ja) | 2023-04-05 |
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US (1) | US11711198B2 (ja) |
JP (1) | JP7252492B2 (ja) |
WO (1) | WO2021014629A1 (ja) |
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US11711198B2 (en) * | 2019-07-25 | 2023-07-25 | Nippon Telegraph And Telephone Corporation | Synchronous detection apparatus, synchronous detection method, and program |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000261314A (ja) | 1999-03-11 | 2000-09-22 | Nec Ic Microcomput Syst Ltd | クロックディザリング回路を用いたpll回路 |
Family Cites Families (80)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5170401A (en) * | 1988-06-02 | 1992-12-08 | Rockwell International Corporation | High integrity single transmission line communication system for critical aviation information |
US5187481A (en) * | 1990-10-05 | 1993-02-16 | Hewlett-Packard Company | Combined and simplified multiplexing and dithered analog to digital converter |
US5134399A (en) * | 1990-10-05 | 1992-07-28 | Hewlett-Packard Company | Subranging analog-to-digital converter with dither |
US5189418A (en) * | 1992-04-16 | 1993-02-23 | Hewlett-Packard Company | Dither error correction |
ES2125961T3 (es) * | 1993-02-26 | 1999-03-16 | Schlumberger Ind Sa | Convertidor de analogico a digital con una señal de activacion modulada. |
US5493298A (en) * | 1993-03-01 | 1996-02-20 | Hewlett-Packard Company | Dithered analog-to-digital converter |
US5530443A (en) * | 1994-04-25 | 1996-06-25 | The United States Of America As Represented By The Secretary Of The Navy | Digital circuit for the introduction of dither into an analog signal |
US5510790A (en) * | 1994-04-25 | 1996-04-23 | The United States Of America As Represented By The Secretary Of The Navy | Digital circuit for the introduction of dither into an analog signal |
US5745061A (en) * | 1995-07-28 | 1998-04-28 | Lucent Technologies Inc. | Method of improving the stability of a sigma-delta modulator employing dither |
US5629703A (en) * | 1995-08-09 | 1997-05-13 | Tektronix, Inc. | Method for reducing harmonic distortion in an analog-to-digital converter system |
US5646569A (en) * | 1995-08-30 | 1997-07-08 | Hewlett-Packard Company | Method and apparatus for AC coupling |
US5786951A (en) * | 1996-06-05 | 1998-07-28 | Cirrus Logic, Inc. | Sampled amplitude read channel employing a discrete time noise generator for calibration |
US6008703A (en) * | 1997-01-31 | 1999-12-28 | Massachusetts Institute Of Technology | Digital compensation for wideband modulation of a phase locked loop frequency synthesizer |
US5793318A (en) * | 1997-02-05 | 1998-08-11 | Hewlett-Packard Company | System for preventing of crosstalk between a raw digital output signal and an analog input signal in an analog-to-digital converter |
US6016113A (en) * | 1997-06-26 | 2000-01-18 | Binder; Yehuda | System for enhancing the accuracy of analog-digital-analog conversions |
US6028543A (en) * | 1997-10-03 | 2000-02-22 | Eg&G Instruments, Inc. | Apparatus for improvement of the speed of convergence to sub-least-significant-bit accuracy and precision in a digital signal averager and method of use |
JP2000022258A (ja) | 1998-07-07 | 2000-01-21 | Nippon Telegr & Teleph Corp <Ntt> | アレイレーザ光源の波長安定化装置 |
AUPQ122699A0 (en) * | 1999-06-25 | 1999-07-22 | Lake Dsp Pty Limited | Sigma delta modulator with buried data |
EP1277304B1 (en) * | 2000-04-28 | 2009-07-01 | Broadcom Corporation | High-speed serial data transceiver systems and related methods |
EP1289150A1 (en) * | 2001-08-24 | 2003-03-05 | STMicroelectronics S.r.l. | A process for generating a variable frequency signal, for instance for spreading the spectrum of a clock signal, and device therefor |
US8000428B2 (en) * | 2001-11-27 | 2011-08-16 | Texas Instruments Incorporated | All-digital frequency synthesis with DCO gain calculation |
US6661360B2 (en) * | 2002-02-12 | 2003-12-09 | Broadcom Corporation | Analog to digital converter that services voice communications |
US7457538B2 (en) * | 2002-05-15 | 2008-11-25 | Nortel Networks Limited | Digital performance monitoring for an optical communications system |
US7346122B1 (en) * | 2002-08-21 | 2008-03-18 | Weixun Cao | Direct modulation of a power amplifier with adaptive digital predistortion |
US6611221B1 (en) * | 2002-08-26 | 2003-08-26 | Texas Instruments Incorporated | Multi-bit sigma-delta modulator employing dynamic element matching using adaptively randomized data-weighted averaging |
TWI235000B (en) * | 2002-09-24 | 2005-06-21 | Mstar Semiconductor Inc | Apparatus and method for masking interference noise contained in signal source |
US7126378B2 (en) * | 2003-12-17 | 2006-10-24 | Rambus, Inc. | High speed signaling system with adaptive transmit pre-emphasis |
US7230981B2 (en) * | 2003-05-09 | 2007-06-12 | Stmicroelectronics, Inc. | Integrated data jitter generator for the testing of high-speed serial interfaces |
US7181180B1 (en) * | 2003-05-15 | 2007-02-20 | Marvell International Ltd. | Sigma delta modulated phase lock loop with phase interpolation |
US6965224B1 (en) * | 2003-05-16 | 2005-11-15 | Cisco Technology, Inc. | Method and apparatus for testing synchronization circuitry |
US7075466B1 (en) * | 2003-05-20 | 2006-07-11 | Pixelworks, Inc. | System and method for improving performance of an analog to digital converter |
US7627029B2 (en) * | 2003-05-20 | 2009-12-01 | Rambus Inc. | Margin test methods and circuits |
US7590175B2 (en) * | 2003-05-20 | 2009-09-15 | Rambus Inc. | DFE margin test methods and circuits that decouple sample and feedback timing |
US7457350B2 (en) * | 2003-07-18 | 2008-11-25 | Artimi Ltd. | Communications systems and methods |
US7561635B2 (en) * | 2003-08-05 | 2009-07-14 | Stmicroelectronics Nv | Variable coder apparatus for resonant power conversion and method |
US8019035B2 (en) * | 2003-08-05 | 2011-09-13 | Stmicroelectronics Nv | Noise shaped interpolator and decimator apparatus and method |
US7015733B2 (en) * | 2003-10-10 | 2006-03-21 | Oki Electric Industry Co., Ltd. | Spread-spectrum clock generator using processing in the bitstream domain |
US7277519B2 (en) * | 2003-12-02 | 2007-10-02 | Texas Instruments Incorporated | Frequency and phase correction in a phase-locked loop (PLL) |
US6950048B1 (en) * | 2004-04-02 | 2005-09-27 | Tektronix, Inc. | Dither system for a quantizing device |
US7460612B2 (en) * | 2004-08-12 | 2008-12-02 | Texas Instruments Incorporated | Method and apparatus for a fully digital quadrature modulator |
DE102004050411B4 (de) * | 2004-10-15 | 2006-08-31 | Infineon Technologies Ag | Modulator mit geregelter Übertragungsbandbreite und entsprechendes Verfahren zum Regeln der Übertragungsbandbreite |
US7015851B1 (en) * | 2004-10-26 | 2006-03-21 | Agilent Technologies, Inc. | Linearizing ADCs using single-bit dither |
ATE436119T1 (de) * | 2004-11-18 | 2009-07-15 | Research In Motion Ltd | Verfahren und vorrichtung zur präzisen abstimmung in offener schleife der referenzfrequenz innerhalb einer drahtlosen einrichtung |
GB2422991B (en) * | 2005-02-03 | 2009-06-17 | Agilent Technologies Inc | Method of equalising a channel and apparatus therefor |
US7680173B2 (en) * | 2005-07-06 | 2010-03-16 | Ess Technology, Inc. | Spread spectrum clock generator having an adjustable delay line |
US7129879B1 (en) * | 2005-07-12 | 2006-10-31 | Analog Devices, Inc. | Method of and apparatus for characterizing an analog to digital converter |
US7221704B2 (en) * | 2005-08-01 | 2007-05-22 | Marvell World Trade Ltd. | All digital implementation of clock spectrum spreading (dither) for low power/die area |
US7936229B2 (en) * | 2005-08-11 | 2011-05-03 | Texas Instruments Incorporated | Local oscillator incorporating phase command exception handling utilizing a quadrature switch |
US7466254B2 (en) * | 2006-02-03 | 2008-12-16 | L&L Engineering Llc | Systems and methods for digital control utilizing oversampling |
US7277033B1 (en) * | 2006-02-13 | 2007-10-02 | Honeywell International, Inc. | System and method for subtracting dither reference during analog-to-digital conversion |
US7817747B2 (en) * | 2006-02-15 | 2010-10-19 | Texas Instruments Incorporated | Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter |
US20070189431A1 (en) * | 2006-02-15 | 2007-08-16 | Texas Instruments Incorporated | Delay alignment in a closed loop two-point modulation all digital phase locked loop |
US7782235B1 (en) * | 2007-04-30 | 2010-08-24 | V Corp Technologies, Inc. | Adaptive mismatch compensators and methods for mismatch compensation |
US8165255B2 (en) * | 2008-12-19 | 2012-04-24 | Freescale Semiconductor, Inc. | Multirate resampling and filtering system and method |
US8174418B2 (en) * | 2009-07-14 | 2012-05-08 | Honeywell International Inc. | Inexpensively improving resolution and reducing noise of low-noise signals |
JP5261779B2 (ja) * | 2009-09-08 | 2013-08-14 | 日本電信電話株式会社 | 光信号送信器、及びバイアス電圧制御方法 |
GB2475878A (en) * | 2009-12-03 | 2011-06-08 | St Microelectronics | Obtaining dithered image data word by adding noise contribution |
US20110235694A1 (en) * | 2010-02-02 | 2011-09-29 | Tektronix, Inc. | Apparatus and Method for Generating a Waveform Test Signal Having Crest Factor Emulation of Random Jitter |
WO2013061272A1 (en) * | 2011-10-28 | 2013-05-02 | Koninklijke Philips Electronics N.V. | Data communication with interventional instruments |
US8471740B2 (en) * | 2011-11-14 | 2013-06-25 | Analog Devices, Inc. | Reducing the effect of non-linear kick-back in switched capacitor networks |
JP5779511B2 (ja) * | 2012-01-20 | 2015-09-16 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
US20130243056A1 (en) * | 2012-03-16 | 2013-09-19 | Lsi Corporation | Voltage margin based baud rate timing recovery in a communication system |
US9071407B2 (en) * | 2012-05-02 | 2015-06-30 | Ramnus Inc. | Receiver clock test circuitry and related methods and apparatuses |
JP2014007518A (ja) * | 2012-06-22 | 2014-01-16 | Panasonic Corp | アナログデジタル変換器のノイズ低減システム、およびノイズ低減方法 |
IL231163A (en) * | 2014-02-26 | 2016-05-31 | Elta Systems Ltd | A system and method for improving the dynamic range of a multi-channel digital receiver that targets transmitted signals |
US9503116B2 (en) * | 2014-12-17 | 2016-11-22 | Analog Devices, Inc. | Efficient calibration of errors in multi-stage analog-to-digital converter |
US9941891B2 (en) * | 2015-06-01 | 2018-04-10 | University Of Southern California | Adaptive spur cancellation techniques and multi-phase injection locked TDC for digital phase locked loop circuit |
WO2017082349A1 (ja) * | 2015-11-12 | 2017-05-18 | 日本電信電話株式会社 | 光送信器及びバイアス電圧の制御方法 |
US9768793B2 (en) * | 2015-12-17 | 2017-09-19 | Analog Devices Global | Adaptive digital quantization noise cancellation filters for mash ADCs |
US11159242B2 (en) * | 2016-02-23 | 2021-10-26 | Nippon Telegraph And Telephone Corporation | Optical transmitter |
US9900145B2 (en) * | 2016-05-19 | 2018-02-20 | Omnivision Technologies, Inc. | Clock generator and method for reducing electromagnetic interference from digital systems |
US10823989B2 (en) * | 2017-07-14 | 2020-11-03 | Nippon Telegraph And Telephone Corporation | Bias control circuit and bias control method |
US10659069B2 (en) * | 2018-02-02 | 2020-05-19 | Analog Devices, Inc. | Background calibration of non-linearity of samplers and amplifiers in ADCs |
US10911061B2 (en) * | 2018-03-23 | 2021-02-02 | The Boeing Company | System and method for demodulation of resolver outputs |
US11397363B2 (en) * | 2018-08-31 | 2022-07-26 | Nippon Telegraph And Telephone Corporation | Automatic bias control circuit |
US11711198B2 (en) * | 2019-07-25 | 2023-07-25 | Nippon Telegraph And Telephone Corporation | Synchronous detection apparatus, synchronous detection method, and program |
US11437980B2 (en) * | 2019-12-06 | 2022-09-06 | The Regents Of The University Of California | Frequency to digital converter, asynchronous phase sampler and digitally controlled oscillator methods |
US11822161B2 (en) * | 2019-12-11 | 2023-11-21 | Nippon Telegraph And Telephone Corporation | Bias voltage adjustment apparatus and IQ optical modulation system |
US11652491B2 (en) * | 2020-08-07 | 2023-05-16 | Analog Devices International Unlimited Company | High-pass shaped dither in continuous-time residue generation systems for analog-to-digital converters |
US11728821B2 (en) * | 2021-02-22 | 2023-08-15 | Mediatek Singapore Pte. Ltd. | LSB dithering for segmented DACs |
-
2019
- 2019-07-25 US US17/628,041 patent/US11711198B2/en active Active
- 2019-07-25 JP JP2021534500A patent/JP7252492B2/ja active Active
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Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000261314A (ja) | 1999-03-11 | 2000-09-22 | Nec Ic Microcomput Syst Ltd | クロックディザリング回路を用いたpll回路 |
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