JP7233387B2 - semiconductor module - Google Patents

Description

The present disclosure relates to semiconductor modules, and more particularly to semiconductor modules with power switching devices.

Active gate control technology that dynamically controls gate voltage and gate current has been proposed as a technology for improving the trade-off between surge voltage and switching loss during switching operation for power switching devices. Specifically, Patent Document 1 proposes a drive circuit for a power switching device having a sense current control circuit, a switch circuit, and a plurality of MOS (Metal Oxide Semiconductor) transistors. A technique for controlling the output current with high accuracy regardless of the current is disclosed.

Further, Patent Document 2 discloses a control method according to the operation mode of a double gate IGBT (Insulated Gate Bipolar Transistor) that applies independent gate voltages to a plurality of gate electrodes provided in a reverse conducting switching device. ing.

Japanese Unexamined Patent Application Publication No. 2015-195700 JP 2017-135255 A

By combining Patent Documents 1 and 2, the idea of active gate control of a double-gate IGBT can be conceived, but from a practical point of view, it is difficult to apply complicated control to the inverter circuit according to the operation mode. This is because the inverter circuit has a high potential side (high side) IGBT and a low potential side (low side) IGBT, and the ON/OFF signal to the high side IGBT is the emitter reference potential (VS VS reference potential), all control signals for performing complex active gate control according to the operation mode must be transmitted to the circuit that uses the VS reference potential as a reference. A level shift circuit can be used to transmit a control signal to a high-side circuit based on the VS reference potential. For this purpose, the number of types of control signals increases, and the number of level shift circuits increases correspondingly, resulting in a large increase in circuit scale.

An object of the present disclosure is to solve the above problems, and to provide a semiconductor module that realizes active gate control of transistors without increasing the circuit scale.

A semiconductor module according to the present disclosure has a first region that receives a first control signal at its first gate for switching operation and a second region that receives a second control signal for switching operation at its second gate. A transistor with a double-gate structure, and a drive control circuit that controls driving of the transistor, the drive control circuit including a first drive circuit that outputs a first drive current based on a first input signal. a second driving circuit for outputting a second driving current for enhancing the first driving current based on the first input signal and the second input signal; the first input signal and the second driving circuit; and a third drive circuit that outputs a third drive current based on the input signal of the first gate and the output of the first and second drive circuits as the first control signal. and the output of the third driving circuit is applied to the second gate as the second control signal.

According to the above semiconductor module, the first control signal obtained by enhancing the first drive current with the second drive current is applied to the first gate of the transistor, whereby the first gate is charged at high speed, Transistor switching can be performed at high speed. On the other hand, if the first drive current is not augmented with the second drive current, charging of the charge to the first gate becomes slow, and the switching of the transistor can be performed at a slow speed. Since the output of the second drive circuit is controlled by the first input signal and the second input signal, the control signal required for active gate control of the transistor can be reduced, and the circuit scale of the active gate control of the transistor can be reduced. It can be realized without increasing.

2 is a circuit diagram showing the configuration of the semiconductor module of Embodiment 1; FIG. 3 is a circuit diagram showing the configuration of a drive circuit configured with a 3-state buffer; FIG. FIG. 10 is a diagram showing an input/output truth table of a 3-state buffer; It is a figure which shows the planar structure of double gate IGBT. FIG. 4 is a diagram showing a truth table of inputs and outputs of a drive circuit; FIG. 4 shows the gate current applied to the double-gate IGBT with respect to the input signal; FIG. 4 is a diagram showing collector current characteristics with respect to gate voltage of a double-gate IGBT; It is a figure which shows an example of control of double gate IGBT by an input signal. 3 is a diagram showing an inverter circuit configured by the semiconductor module of Embodiment 1; FIG. FIG. 8 is a circuit diagram showing the configuration of a semiconductor module according to a second embodiment; FIG. 10 is a circuit diagram showing a configuration of a semiconductor module of Modification 1 of Embodiment 2; FIG. 11 is a circuit diagram showing a configuration of a semiconductor module of Modification 2 of Embodiment 2;

<Embodiment 1>
FIG. 1 is a circuit diagram showing the configuration of a semiconductor module 100 according to Embodiment 1. FIG. A semiconductor module 100 shown in FIG. 1 includes a double-gate IGBT 10 and a drive control circuit 20 for controlling ON/OFF of the double-gate IGBT 10. The double-gate IGBT 10 is connected between power lines S and N in parallel. An equivalent circuit is shown as an N-type main IGBT Q1 and an N-type sub-IGBT Q2 that are connected. A freewheel diode FD is connected antiparallel to the main IGBT Q1 and the sub IGBT Q2.

The drive control circuit 20 receives an input signal Main_IN (first input signal), an inverter U1 that inverts and outputs the input signal, and a main control signal Main_OUT (first control signal) that receives the output of the inverter U1 and controls the main IGBT Q1. ), and a driving circuit D1 (first driving circuit) for outputting .

Further, a drive circuit D2 (second drive circuit) that receives the output Add_IN of the inverter U1 and outputs a drive current _IA that enhances the drive capability (drive current) of the drive circuit D1, an input signal Main_IN and an input signal Sub_IN ( A logic circuit U2 that receives the second input signal) and outputs a logical product, an inverter U3 that receives the output of the logic circuit U2, inverts it, and outputs it, and a sub control signal that receives the output of the inverter U3 and controls the sub IGBT Q2. and a drive circuit D3 (third drive circuit) that outputs Sub_OUT (second control signal).

It also has an inverter U4 that receives an input signal Sub_IN, inverts it, and outputs a switching signal Tri_IN, and the output of the inverter U4 is given to the control input of the drive circuit D2. Here, the input signal Main_IN is a signal for switching ON and OFF of the double-gate IGBT, and the input signal Sub_IN changes the current capacity (collector current) of the double-gate IGBT 10. This is a signal for switching the number of operating IGBTQ2.

The driving circuit D2 is composed of a 3-state buffer so that the driving capability can be switched according to the input signals Main_IN and Sub_IN. FIG. 2 shows the configuration of the driving circuit D2.

As shown in FIG. 2, the drive circuit D2 includes a P-type MOS transistor PM and an N-type MOS transistor NM connected in series between the power supply potential VT and the reference potential GD, the output Add_IN of the inverter U1, and the switching signal. A logic circuit U10 that receives Tri_IN and outputs a logical product, an inverter U11 that receives and inverts the switching signal Tri_IN and outputs it, and a logic circuit U12 that receives the output Add_IN of the inverter U1 and the output of the inverter U11 and outputs a logical sum. ,have.

The output of the logic circuit U12 is input to the gate of the MOS transistor PM, and the output of the logic circuit U10 is input to the gate of the MOS transistor NM. A signal Add_OUT is output from a connection node with the MOS transistor NM.

The signal Add_OUT becomes an inverted signal of the input when the potential of the switching signal Tri_IN is high potential (H), and becomes high impedance (HiZ) when the potential of the switching signal Tri_IN is low potential (L). FIG. 3 shows the truth table for the input and output of the 3-state buffer. Note that although the potential H and the potential L may be referred to as a first potential and a second potential, respectively, the names may be reversed.

FIG. 4 shows a planar configuration of the double-gate IGBT 10. As shown in FIG. FIG. 4 is a top view of the double gate IGBT 10 through which the main current flows in the thickness direction, viewed from the emitter electrode side. gate) is provided. Although illustration is omitted, the double gate IGBT 10 includes a main region (first region) that performs a switching operation in response to the main control signal Main_OUT (ON signal and OFF signal) input to the main gate MG, and a sub-gate. It has a sub-region (second region) that performs a switching operation upon receiving a sub-control signal Sub_OUT (ON signal and OFF signal) input to SG.

Here, the areas of the effective areas of the main area and the sub-area are set so that the main area is larger than the sub-area (Sub<Main), and only the main area is switched, or the main area and the sub-area are switched. can be used according to the operation mode, such as switching operation of both.

The main IGBT Q1 shown as an equivalent circuit in FIG. 1 corresponds to the main region, the sub IGBT Q2 corresponds to the sub region, and the main gate current (IG _main ) corresponding to the input signal Main_IN is supplied from the drive circuit D1 to the main gate MG. Alternatively, the sub-gate SG is supplied with or withdrawn a sub-gate current (IG _sub ) from the drive circuit D3 according to the input signal Main_IN.

FIG. 5 shows a truth table of the operation of the drive circuits D1 and D3 with respect to the input signal Main_IN and the input signal Sub_IN. As shown in FIG. 5, when the input signal Main_IN is H, the drive circuit D1 operates, so the main control signal Main_OUT is H. At this time, if the input signal Sub_IN is L, the switching signal Tri_IN becomes H, so that the drive circuit D2 operates. On the other hand, the sub control signal Sub_OUT is L because the logical product does not hold for the driving circuit D3. When the input signal Main_IN is L and the input signal Sub_IN is L, the driving circuit D1 does not operate, the main control signal Main_OUT becomes L, and the sub control signal Sub_OUT also becomes L.

When the input signal Main_IN is H and the input signal Sub_IN is H, both the main control signal Main_OUT and the sub control signal Sub_OUT are H. At this time, the switching signal Tri_IN becomes L, so the driving circuit D2 does not operate. When the input signal Main_IN is L and the input signal Sub_IN is H, the driving circuit D1 does not operate, the main control signal Main_OUT becomes L, and the sub control signal Sub_OUT also becomes L. At this time, the switching signal Tri_IN becomes L, so the driving circuit D2 does not operate.

Next, the effect of switching the input signal Sub_IN on the switching speed of the double gate IGBT 10 will be described with reference to FIG.

FIG. 6 shows the gate current applied to the double gate IGBT 10 with respect to the input signal Sub_IN. As shown in FIG. 6, when the input signal Main_IN is H and the input signal Sub_IN is L, the driving circuit D2 operates. At this time, since the drive current I _A (second drive current) is supplied from the MOS transistor PM, which is the output part of the three-state buffer of the drive circuit D2, the main gate current (IG _main ) of the double-gate IGBT 10 is Combined with the drive current I _M (first drive current) supplied from the circuit D1, it is represented by the following formula.
IG _main (H, L) = I _M + I _A

On the other hand, since the sub-control signal Sub_OUT input to the drive circuit D3 is L, no drive current is supplied to the sub-gate of the double-gate IGBT 10, and the sub-gate current IG _sub is represented by the following formula.
IG _sub (H, L)=0

Therefore, only the main gate of the double-gate IGBT 10 is charged at high speed, and the switching speed becomes high.

Further, when the input signal Main_IN is H and the input signal Sub_IN is H, the driving circuit D2 does not operate, so the main gate current (IG _main ) of the double gate IGBT 10 is expressed by the following formula.
IG _main (H, H) = I _M

On the other hand, since the sub-control signal Sub_OUT input to the drive circuit D3 is H, the sub-gate of the double-gate IGBT 10 is supplied with the drive current I _S (third drive current), and the sub-gate current IG _sub is given by the following formula: expressed.
IG _sub (H, H)=I _S

Therefore, the main gate and sub-gate of the double-gate IGBT 10 are charged, but since the main gate current (IG _main ) is reduced, the charging of the main gate is slow, resulting in a slow switching speed. can.

When the input signal Main_IN is L, the discharge operation is performed, and the sign of the current is reversed because the gate current is drawn to the drive circuit.

Next, the effect of switching the input signal Sub_IN on the output characteristics of the double gate IGBT 10 will be described with reference to FIG.

FIG. 7 is a diagram showing the collector current characteristics (Vg-Ic characteristics) with respect to the gate voltage of the double-gate IGBT 10 with respect to the input signal Sub_IN, where the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the collector current (Ic). show.

As described with reference to FIG. 6, when the input signal Sub_IN is H, the double gate IGBT 10 switches both the main region and the sub region. On the other hand, if the input signal Sub_IN is L, the sub-area does not perform switching operation, and only the main area performs switching operation. Here, when input signal Main_IN is H and gate bias voltage Vg_bias is applied to double-gate IGBT 10, characteristics C1 when input signal Sub_IN is H and characteristics C2 when input signal Sub_IN is H are compared. If there is, the switching operation area of the double-gate IGBT 10 is the main area and the sub-area, and the switching operation area is wide, so the collector current Ic increases.

Thus, in the semiconductor module 100 of Embodiment 1, switching the input signal Sub_IN makes it possible to control the switching speed and output characteristics of the double-gate IGBT 10 .

A practical example of the semiconductor module 100 will be described below. For example, when starting a motor using an inverter circuit configured by a power device, the output current (Io) of the inverter circuit increases because a rush current flows through the motor at the time of starting. On the other hand, the junction temperature of the power device is low due to the low transient thermal resistance. Therefore, in this state, the semiconductor module should have a high current capability and a low switching speed to suppress switching noise and surge.

Here, it is assumed that an inverter circuit is configured by combining a plurality of semiconductor modules 100 of the first embodiment. When an H signal is input as the input signal Sub_IN from a microcomputer or the like for controlling the module, the switching speed of the double-gate IGBT 10 becomes low at startup as described with reference to FIG. Thus, the current capability (collector current) of the double-gate IGBT 10 can be increased.

As time passes and the motor reaches a steady state and the output current (Io) of the inverter circuit becomes low, the current capability of the double gate IGBT 10 may be low, but the increase in the junction temperature (Tj) of the double gate IGBT 10 is suppressed. Therefore, high-speed switching is desired. In particular, in the case of a drive circuit using CMOS (Complementary MOS) transistors like the drive circuit D2 shown in FIG. can lead to a decline in

However, when an L signal is input as the input signal Sub_IN from a microcomputer or the like, it becomes possible to increase the switching speed of the double gate IGBT 10 as described with reference to FIG.

FIG. 8 shows an example of control of the double gate IGBT 10 by the input signal Sub_IN described above. In FIG. 8, the upper part shows the time change of the output current (Io) of the inverter circuit, the lower part shows the time change of the junction temperature (Tj) of the double-gate IGBT 10, and the lower part shows the timing chart of the input signal Sub_IN. It is shown that switching the signal Sub_IN from H to L reduces the output current (Io). The switching timing of the input signal Sub_IN may be after the junction temperature of the double gate IGBT 10 is saturated.

In addition, although the short-circuit resistance of an IGBT generally decreases at high temperatures, by setting the input signal Sub_IN to L in the first embodiment, the collector current of the double-gate IGBT 10 decreases as shown in FIG. The energy generated at times is reduced, and a decrease in short-circuit withstand capability can be suppressed.

FIG. 9 shows an example of configuring an inverter circuit using the semiconductor module 100 of the first embodiment. FIG. 9 shows a three-phase inverter circuit 1000 composed of a U-phase inverter circuit UF, a V-phase inverter circuit VF, and a W-phase inverter circuit WF. Each phase inverter circuit is a high-side drive control circuit (HVIC). and an IPM (Intelligent Power Module) with a low-side drive control circuit (LVIC). In FIG. 9, only the U-phase inverter circuit UF shows a specific configuration, but the V-phase inverter circuit VF and the W-phase inverter circuit WF can also have similar configurations. W-phase inverter circuit WF has output nodes V and U, respectively. In addition, in FIG. 9, the same reference numerals are assigned to the same configurations as those of the semiconductor module 100 described with reference to FIG. 1, and overlapping descriptions will be omitted.

The U-phase inverter circuit UF includes a double gate IGBT 10 composed of an N-type main IGBT Q1 and an N-type sub-IGBT Q2 connected in parallel between a power line P (upper arm) and a U-phase output node U; Double gate IGBT 11 composed of N-type main IGBT Q11 and N-type sub-IGBT Q12 connected in parallel between U-phase output node U and power line UN (lower arm), double gate IGBTs 10 and 11 ON , and a drive control circuit 20 and a drive control circuit 21 for controlling OFF, respectively. Freewheel diodes FD1 and FD2 are connected in anti-parallel to the double gate IGBTs 10 and 11, respectively.

In the drive control circuit 20, a signal transmission circuit ST1 including a level shift circuit that receives an input signal UP_IN and level-shifts it to the emitter reference potential of the high-side IGBT and outputs it, and an input signal Sub_IN that receives the input signal Sub_IN and outputs the signal of the high-side IGBT and a signal transmission circuit ST2 including a level shift circuit for level-shifting up to the emitter reference potential and outputting the same.

The drive control circuit 21 has a signal transmission circuit ST11 that receives and outputs the input signal UN_IN, and a signal transmission circuit ST12 that includes a delay circuit that receives and delays the input signal Sub_IN and outputs the same. As the input signal Sub_IN, a common signal is given to the drive control circuit 20 and the drive control circuit 21. However, considering the signal transmission delay time, the signal transmission circuit ST12 is provided with a delay circuit for adjustment. .

Thus, if the drive control circuit 20 for the high-side double-gate IGBT 10 has a level shift circuit for level-shifting the input signal UP_IN (corresponding to the input signal Main_IN) and a level-shift circuit for level-shifting the input signal Sub_IN, Therefore, even complex control of active gate control can be realized without greatly increasing the circuit scale.

In addition, the semiconductor module 100 can be realized by conventional circuit processes, known double-gate IGBT technology, and a wiring process for connecting them, and it is necessary to establish a new process technology according to the first embodiment. It is also practical in that there is no

<Embodiment 2>
In the semiconductor module 100 of the first embodiment, the input signal Sub_IN is input from an external microcomputer or the like, but in the semiconductor module 100A of the second embodiment shown in FIG. It has a configuration that generates with 10, the same components as those of the semiconductor module 100 described with reference to FIG. 1 are denoted by the same reference numerals, and overlapping descriptions are omitted.

As shown in FIG. 10, the semiconductor module 100A has an analog temperature detection circuit TC in the drive control circuit 20A of the double-gate IGBT 10, and the detected temperature in the drive control circuit 20A detected by the temperature detection circuit TC is the threshold value. By generating the input signal Sub_IN based on whether or not the temperature exceeds the temperature, the input signal Sub_IN can be switched autonomously according to the device temperature of the double-gate IGBT 10 .

As an example of the temperature detection circuit TC, a diode DD having good temperature characteristics is used as a detection element, and a current source I1, a diode DD and a resistor R1 are connected in series between the power supply potential VT and the reference potential GD. is used as an output node.

The reference voltage REF is output from the connection node between the resistors R11 and R12, with the resistors R11 and R12 connected in series between the power supply potential VT and the reference potential GD.

The temperature detection voltage at temperature detection circuit TC, that is, the voltage at the anode of diode DD, is input to the inverting input terminal of comparator U5, the reference voltage REF is input to the non-inverting input terminal of comparator U5, and the output of comparator U5 is It is input to the inverter U6 and inverted by the inverter U6 to become the input signal Sub_IN.

Therefore, when the device temperature of the double-gate IGBT 10 is low, the reference voltage REF (threshold) is set so that the input signal Sub_IN becomes H, thereby slowing down the switching speed. On the other hand, when the device temperature of the double-gate IGBT 10 rises and exceeds the reference voltage REF (threshold), the switching speed can be increased by setting the input signal Sub_IN to L.

In this way, in the semiconductor module 100A, the input signal Sub_IN is automatically generated according to the device temperature of the double-gate IGBT 10, so independent drive control according to the device temperature is possible without using an external signal. becomes.

<Modification 1>
In the semiconductor module 100A of the second embodiment described above, the analog temperature detection circuit TC is provided in the drive control circuit 20A to indirectly measure the device temperature of the double gate IGBT 10. The device temperature of the IGBT 10 may be directly measured.

FIG. 11 is a circuit diagram showing the configuration of a semiconductor module 100B of Modification 1 of Embodiment 2. As shown in FIG. As shown in FIG. 11, in the semiconductor module 100B, the temperature sensing diode TD is incorporated in the double gate IGBT 10, and the temperature sensing voltage of the temperature sensing diode TD is compared with the reference voltage REF in the drive control circuit 20B. The input signal Sub_IN can be switched autonomously according to the device temperature of the double-gate IGBT 10 .

As an example of temperature detection by the temperature sensing diode TD, a current source I10, a temperature sensing diode TD and a resistor R10 are connected in series between the power supply potential VT and the reference potential GD, and the voltage of the anode of the temperature sensing diode TD is detected by a comparator. A configuration in which the voltage is input to the inverting input terminal of U5 and the reference voltage REF is input to the non-inverting input terminal of the comparator U5 can be cited. The output of the comparator U5 is input to the inverter U6 and inverted by the inverter U6 to become the input signal Sub_IN. Note that the reference voltage REF may be generated by the configuration shown in FIG.

The configuration of FIG. 11 requires a process of forming the temperature sensing diode TD in the double-gate IGBT 10 and wiring for feedback of the temperature detection voltage. More accurate drive control can be performed according to the temperature.

<Modification 2>
In the semiconductor module 100A of Embodiment 2 and the semiconductor module 100B of Modification 1 thereof, the double-gate IGBT 10 is used as a power device, so there is an advantage that the ON voltage can be lowered. may be used as a reverse conducting transistor such as a reverse conducting MOS transistor or a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT) using as a freewheel diode.

FIG. 12 is a circuit diagram showing the configuration of a semiconductor module 100C according to Modification 2 of Embodiment 2. As shown in FIG. As shown in FIG. 12, in a semiconductor module 100C, a double-gate MOS transistor 30 using a body diode as a freewheel diode is used as a power device. 12, the same components as those of the semiconductor module 100B shown in FIG. 11 are denoted by the same reference numerals, and overlapping descriptions are omitted.

In FIG. 12, double gate MOS transistor 30 is shown in an equivalent circuit as N-type main MOS transistor Q10 and N-type sub MOS transistor Q20 connected in parallel between power line S and power line N. FIG. Main MOS transistor Q10 and sub MOS transistor Q20 use body diodes as freewheel diodes.

Reverse-conducting devices such as MOS transistors and RC-IGBTs are energized even during the freewheeling operation, so that the change in junction temperature (ΔTj) is small and temperature controllability is improved.

In addition, within the scope of the disclosure, each embodiment can be freely combined, or each embodiment can be appropriately modified or omitted.

10 double gate IGBT, 20 drive control circuit, D1, D2, D3 drive circuit, TC temperature detection circuit, TD temperature sense diode.

Claims (8)

a double-gate structure transistor having a first region for performing switching operation upon receiving a first control signal at its first gate and a second region for performing switching operation upon receiving a second control signal at its second gate;
A drive control circuit that controls driving of the transistor,
The drive control circuit is
a first drive circuit that outputs a first drive current based on a first input signal;
a second drive circuit that outputs a second drive current that enhances the first drive current based on the first input signal and the second input signal;
a third drive circuit that outputs a third drive current based on the first input signal and the second input signal;
outputs of the first and second drive circuits are provided to the first gate as the first control signal;
The semiconductor module according to claim 1, wherein the output of the third drive circuit is given to the second gate as the second control signal. The first and second regions are
2. The semiconductor module according to claim 1, wherein the area of said first region is larger than the area of said second region. The second drive circuit,
When the first input signal has a first potential and the second input signal has a second potential different from the first potential, the second drive current is output, enhances the drive current of the first region for switching operation;
The third drive circuit is
When the first input signal is at the first potential and the second input signal is at the second potential, the third driving current is not output, and switching operation is performed in the second region. 2. The semiconductor module according to claim 1, wherein no. The second drive circuit,
When the first input signal is at the first potential and the second input signal is at the first potential, the second driving current is not output, and the first driving current is used to output the second driving current. switching the first region;
The third drive circuit is
When the first input signal is at the first potential and the second input signal is at the first potential, the third drive current is output to switch the second region. 4. The semiconductor module according to claim 3. The drive control circuit has a temperature detection circuit,
2. The semiconductor module according to claim 1, wherein said second control signal is generated based on whether the temperature detected by said temperature detection circuit exceeds a threshold. the transistor has a temperature sensing diode;
2. The semiconductor module according to claim 1, wherein said second control signal is generated based on whether the temperature detected by said temperature sensing diode exceeds a threshold. 2. The semiconductor module according to claim 1, wherein said transistor is an IGBT. 2. The semiconductor module according to claim 1, wherein said transistor is a reverse conducting MOS transistor or a reverse conducting IGBT.

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