JP7230291B2 - Semiconductor layout design method and semiconductor layout design device - Google Patents

Description

The present invention relates to a semiconductor layout design method and a semiconductor layout design apparatus.

In recent years, with the progress of miniaturization of LSI, delay due to wiring resistance has become a problem. For this reason, many proposals have been made to shorten the wiring length. It is

For example, Patent Document 1 discloses a semiconductor integrated circuit device using oblique wiring. However, when fabricating this semiconductor integrated circuit device, there is a problem that a large amount of computer resources are required to calculate the wiring length, and the semiconductor layout design device becomes large-scaled, resulting in a high cost.

Also, in the LSI manufacturing process, a wiring pattern is formed by an etching process. In this etching process, a difference occurs in the processing of the wiring pattern depending on the density of the pattern on the wafer. That is, the ratio of the area where the pattern exists to the total area where the pattern can be formed is called the coverage. occur.

Specifically, the higher the coverage, the slower the chemical reaction rate during etching, which may result in uncut portions. Conversely, the lower the coverage, the faster the chemical reaction rate during etching, which may cause a phenomenon called dishing, in which the pattern is removed more than expected.

In response to the above, Japanese Patent Laid-Open No. 2002-200002 discloses a technique for controlling the coverage of dummy patterns in a predetermined area. In this semiconductor manufacturing method, a dummy pattern area is provided around a macro cell in a chip, a dummy pattern is arranged in this dummy pattern area, and a coverage rate is set within a predetermined range. Specifically, the total peripheral length of the patterns formed on the wafer is set to be within a predetermined range on the wafer surface.

Japanese Patent Application Laid-Open No. 2001-230322 JP 2010-16044 A

SUMMARY OF THE INVENTION The present invention has been made in view of the current state of the semiconductor layout design apparatus as described above, and its object is to provide a semiconductor layout design method and apparatus that facilitates coverage adjustment while shortening the wiring length.

According to an embodiment of the present invention, the position where a layout pattern can be arranged is represented by pattern candidate line segments formed by connecting each side of each equilateral triangle when a plurality of equilateral triangles are continuously arranged. and wiring rule storage means storing wiring rule information relating to a wiring resistance value to be satisfied given to a layout pattern between macrocells, wherein the pattern candidate for one side of the equilateral triangle is provided . A layout pattern for connecting macrocells is arranged on a semiconductor substrate based on the information in the pattern position information storage means by using a semiconductor layout designing device in which the resistance value of a line segment is defined as a predetermined value , and this layout pattern is obtained. The wiring resistance of the layout pattern is calculated based on how many times the length is one side of the equilateral triangle, and the layout pattern is wired so that the calculated wiring resistance satisfies the wiring rule of the wiring rule storage means. a pattern arrangement step, and a dummy for arranging a dummy pattern by selecting from patterns of a plurality of areas prepared in advance at the arrangement possible position where the layout pattern is not arranged, based on the information in the pattern position information storage means. a pattern arrangement step, obtaining a coverage ratio of an area occupied by the layout pattern and the dummy pattern , detecting whether or not a predetermined reference pattern coverage ratio is satisfied, and arranging the dummy pattern so as to satisfy the reference pattern coverage ratio; and a coverage control step for controlling the steps.

1 is a configuration diagram of a first embodiment of a semiconductor layout design apparatus according to the present invention; FIG. FIG. 4 is a diagram showing an example of pattern candidate line segments used in the embodiment of the semiconductor layout design apparatus of the present invention; 1 is a diagram showing an example of a layout pattern wired in an embodiment of a semiconductor layout design device of the present invention; FIG. 1 is a diagram showing an example of layout patterns and dummy patterns wired in an embodiment of a semiconductor layout design apparatus of the present invention; FIG. FIG. 4 is a diagram showing the relationship between the mask and the area whose coverage is controlled by the semiconductor layout designing apparatus of the present invention; 4 is a flow chart for explaining the operation of the semiconductor layout design apparatus according to the first embodiment of the present invention; FIG. 2 is a configuration diagram of a semiconductor layout design apparatus according to a second embodiment of the present invention; FIG. 7 is a diagram showing an example of dummy pattern candidate information stored in the semiconductor layout design apparatus according to the second embodiment of the present invention; FIG. 7 is a diagram showing an example of layout patterns and square dummy patterns wired in the second embodiment of the semiconductor layout design apparatus of the present invention; 1 is a diagram showing an example of a layout pattern wired in an embodiment of a semiconductor layout designing apparatus of the present invention and a regular hexagonal dummy pattern; FIG. 6 is a flow chart for explaining the operation of the second embodiment of the semiconductor layout design apparatus according to the present invention;

A semiconductor layout designing method and a semiconductor layout designing apparatus according to embodiments of the present invention will be described below with reference to the accompanying drawings. In each figure, the same components are denoted by the same reference numerals, and overlapping descriptions are omitted.

(First embodiment)
FIG. 1 shows a configuration diagram of a semiconductor layout design apparatus according to the first embodiment. This semiconductor layout design apparatus is provided with a computer section 10 and an information storage section 20 , and the computer section 10 performs processing using information in the information storage section 20 . The computer unit 10 is connected to an input device 31 composed of a keyboard, a pointing device, etc., and a display device 32 composed of an LED, an LCD display, etc. for displaying information. Further, the computer section 10 may be connected to output means such as a printer, or may be connected to a communication section for transmitting and receiving information via a network or the like.

From the input device 31, it is possible to select and instruct a dummy pattern to be wired, instruct to change the wired dummy pattern, and confirm the selection result. On the display device 32, it is possible to display the intermediate progress and result of the processing by the semiconductor layout design device in the size of an area, in a size obtained by enlarging a part of the area, or in the size of a mask. be. If output means such as a printer is connected, the information displayed on the display device 32 can be printed out or the like.

The information storage unit 20 includes a circuit information area storing circuit information such as circuit diagram information, netlist, and layout information for designing LIS, and a circuit information area storing wiring rules and coverage rules necessary for wiring. A rule area is provided in which various kinds of rule information are stored.

The information storage unit 20 is provided with pattern position information storage means 21 . In the pattern position information storage unit 21, positions where layout patterns can be arranged are stored as information expressed by pattern candidate line segments formed by connecting a plurality of equilateral triangles. An example of this pattern candidate line segment is shown in FIG. In the example of FIG. 2, a pattern candidate line segment is formed by a line grid in which one side of a plurality of adjacent equilateral triangles is vertically aligned. This candidate line segment is represented by the minimum line width and minimum pitch allowed as a layout pattern. The minimum pitch corresponds to the height of an equilateral triangle. That is, the line grids are wired at positions that can be connected to the terminals in the macrocell (element or group of elements). Further, the pattern candidate line segment in the pattern position information storage unit 21 may include a layer mask that is prohibited from being used as a dummy pattern. The part of the layer mask where the dummy pattern cannot be placed is an area where the dummy placement prohibited area information is set and the dummy pattern cannot be placed. ) may be displayed.

The computer section 10 is provided with pattern placement means 11 , dummy pattern placement means 12 , and coverage control means 13 . Based on the information in the pattern position information storage means 21, the pattern arrangement means 11 arranges a layout pattern for connecting the macro cells on the semiconductor substrate. A specific example of the layout pattern LP is shown in FIG. The pattern candidate line segments are indicated by dashed lines, and the layout pattern LP indicates that the required line segments of the pattern candidate line segments are wired by solid lines thicker than the pattern candidate line segments. The line width of the layout pattern LP is defined for this semiconductor and can be stored in the rule area.

The dummy pattern arrangement means 12 arranges dummy patterns at positions where the layout pattern is not arranged in the dashed lines of the pattern candidate line segments based on the information in the pattern position information storage means 21 . FIG. 4 shows an example of a dummy pattern DP wired following the layout pattern LP. As with the layout pattern LP, the dummy pattern DP indicates that the required line segment of the pattern candidate line segment is wired with a hatched line thicker than the pattern candidate line segment. A plurality of types of line widths of the dummy pattern DP are set and can be selected according to the coverage rate.

The coverage control means 13 obtains the coverage of the area occupied by the layout pattern and the dummy pattern, and controls the dummy pattern placement means 12 so as to satisfy a predetermined reference pattern coverage. The coverage control means 13 divides the mask into a plurality of areas having the same area, and controls the dummy pattern placement means 12 so that each area satisfies a predetermined reference pattern coverage. For example, when the mask M is one large area as shown in FIG. 5, the mask M is divided into areas E11, E12, . Areas E11, E12, . . . , Emn do not coincide with the positions of the chips.

In the first embodiment configured as described above, the operation is performed by a program corresponding to the flowchart shown in FIG. 6, so the operation will be described according to this flowchart.

The macrocells are connected by the layout pattern LP along the pattern candidate line segment (S11), and it is detected whether or not the wiring resistance satisfies the wiring rule (S12). Since the pattern candidate line segment is a set of one side of an equilateral triangle, the wiring resistance can be easily calculated by multiplying the resistance value of one side of the equilateral triangle. If NO in step S12, the process returns to step S11, and the layout pattern LP is wired by a path whose wiring resistance satisfies the rule. In this embodiment, step S12 for detecting whether or not the wiring resistance satisfies the wiring rule is provided before the next step S13, but this is only an example, and it is determined whether the wiring resistance satisfies the wiring rule. It does not prevent the process of detecting whether or not to be performed in a process procedure different from this flowchart.

If YES in step S12, the coverage ratio is obtained for each area, and the required amount of dummy patterns is arranged (S13). At this time, placement of dummy patterns is avoided for pattern candidate line segments that are prohibited from being used as dummy patterns. Next, it is determined whether the coverage rate is satisfied in the area (S14), and if NO, the dummy pattern is adjusted (S15). An appropriate coverage is set such that the difference from the coverage of other areas is within a predetermined range.

If YES in step S14, it is detected whether or not the coverage has been adjusted in all areas (S16), and if not in all areas, the process returns to step S13. On the other hand, if YES in step S16, it is detected whether the coverage of the entire mask is satisfied (S17). Perform processing to return to If YES in step S17, the process ends.

(Second embodiment)
FIG. 7 shows a configuration diagram of a semiconductor layout design apparatus according to the second embodiment. In the second embodiment, an information storage section 20A corresponding to the information storage section 20 in the first embodiment comprises dummy pattern candidate storage means 22. FIG. The dummy pattern candidate storage means 22 stores information on dummy pattern candidates having different dummy pattern shapes and/or areas.

In other words, the dummy pattern candidate storage means 22 stores dummy patterns having shapes centered on the intersections of the pattern candidate lines, in addition to the dummy patterns wired along the pattern candidate lines. there is This figure can be a regular polygon.

FIG. 8 shows an example of information on dummy pattern candidates stored in the dummy pattern candidate storage unit 22. As shown in FIG. The uppermost row is a dummy pattern wired along the pattern candidate line segments, and has different line widths and different areas. The length is the length of one side of an equilateral triangle formed by pattern candidate line segments. The second column is a square-shaped dummy pattern. When arranged, they are arranged, for example, as shown in FIG. 9 so as to form a figure centered on the intersection of the pattern candidate line segments. The third column is a regular hexagonal dummy pattern. When arranged, they are arranged as shown in FIG. 10, for example, so as to form a figure centered on the intersection of the pattern candidate line segments. The dummy pattern candidate storage means 22 may store dummy patterns of various shapes other than this example.

The coverage control unit 13 according to the present embodiment controls the dummy pattern placement unit 12 using the information in the dummy pattern candidate storage unit 22 so that each area satisfies a predetermined reference pattern coverage. In particular, the coverage control means 13 controls the dummy pattern placement means 12 so that the coverage of each area is balanced and each area satisfies a predetermined reference pattern coverage.

The semiconductor layout design apparatus according to the second embodiment differs from the first embodiment in the above configuration. In the second embodiment configured as described above, the operation is performed by a program corresponding to the flow chart shown in FIG. 11, so the operation will be described according to this flow chart.

In this embodiment, as in the first embodiment, the macrocells are connected by the layout pattern LP along the pattern candidate line segment (S11), and it is detected whether the wiring resistance satisfies the wiring rule (S12). . Since the pattern candidate line segment is a set of one side of an equilateral triangle, the wiring resistance can be easily calculated by multiplying the resistance value of one side of the equilateral triangle. If NO in step S12, the process returns to step S11, and the layout pattern LP is wired by a path whose wiring resistance satisfies the rule.

If YES in step S12, a dummy pattern of a predetermined shape (for example, a square with the second largest area) selected from the dummy pattern candidate storage means 22 is set for all areas (S21), and the coverage rate for each area is set. is obtained in all areas to calculate the average coverage (S22). Furthermore, the difference between the average coverage rate and the coverage rate for each area is obtained (S23).

For an area with a large difference, the area is changed by changing the shape and size of the dummy pattern selected from the dummy pattern candidate storage means 22 to reduce the difference and balance the coverage of each area (S24). Next, it is detected whether the difference from the average coverage is within a predetermined range in all areas (S25), and if NO, the process returns to step S24.

On the other hand, if YES in step S25, it is detected whether the coverage of the entire mask is satisfied (S17). A process to return to step S17 is performed. If YES in step S17, the process ends.

According to this embodiment, it can be expected that the coverage ratio of each area will be approximately the same value, and the phenomenon called dishing, in which the pattern is removed more than expected, will not occur easily, and the same chemical reaction will occur over the entire mask. It can be expected that the processing accuracy will be uniform because of the speed.

In the first embodiment, the shape of the dummy pattern is a kind of dummy pattern wired along the pattern candidate line segments. A dummy pattern (especially, a regular polygonal dummy pattern such as a square or a regular hexagon) may be used.

REFERENCE SIGNS LIST 10 computer section 11 pattern arrangement means 12 dummy pattern arrangement means 13 coverage control means 20 information storage section 20A information storage section 21 pattern position information storage means 22 dummy pattern candidate storage means 31 input device 32 display device

Claims (16)

pattern position information storage means for storing positions where layout patterns can be arranged as information represented by pattern candidate line segments formed by connecting each side of each equilateral triangle when a plurality of equilateral triangles are continuously arranged; and wiring rule storage means storing wiring rule information relating to a wiring resistance value to be satisfied given to the layout pattern between the macro cells, wherein the resistance value of the pattern candidate line segment on one side of the equilateral triangle is a predetermined value . Using a semiconductor layout design device specified as
A layout pattern for connecting macrocells is arranged on a semiconductor substrate based on the information in the pattern position information storage means , and wiring of the layout pattern is determined based on how many times the length of the layout pattern is one side of the equilateral triangle. a pattern placement step of calculating the resistance and wiring the layout pattern so that the calculated wiring resistance satisfies the wiring rule of the wiring rule storage means;
a dummy pattern placement step of selecting from patterns having a plurality of areas prepared in advance and placing a dummy pattern at the placement possible position where the layout pattern is not placed, based on the information in the pattern position information storage means;
Covering for determining the coverage of the area occupied by the layout pattern and the dummy pattern, detecting whether a predetermined reference pattern coverage is satisfied, and controlling the dummy pattern placement step so as to satisfy the reference pattern coverage. A semiconductor layout design method comprising: performing a rate control step; The information stored in the pattern position information storage means and expressed by a pattern candidate line segment formed by connecting a plurality of sides of the equilateral triangle is expressed by a minimum line width and a minimum pitch allowed as a layout pattern. 2. The semiconductor layout design method according to claim 1. 3. The semiconductor layout design method according to claim 1, wherein in said dummy pattern placement step, a dummy pattern is placed along said pattern candidate line segment. 4. The semiconductor layout design method according to any one of claims 1 to 3, wherein, in said dummy pattern placement step, the dummy patterns are placed using a figure having a shape centered on intersections of said pattern candidate line segments. 5. The semiconductor layout design method according to claim 4, wherein said figure is a regular polygon. 2. In the coverage control step, the mask is divided into a plurality of areas having the same area, and the dummy pattern placement step is controlled so that each area satisfies a predetermined reference pattern coverage. 6. The semiconductor layout design method according to any one of items 1 through 5. 7. The method according to claim 6, wherein in the coverage control step, the dummy pattern placement step is controlled so that the coverage of each area is balanced and each area satisfies a predetermined reference pattern coverage. semiconductor layout design method. The semiconductor layout design apparatus further comprises dummy pattern candidate storage means for storing information on dummy pattern candidates having different dummy pattern shapes and/or areas,
7. In said coverage control step, the dummy pattern placement step is controlled so that each area satisfies a predetermined reference pattern coverage using the information in said dummy pattern candidate storage means. 8. The semiconductor layout design method according to 7. pattern position information storage means for storing positions where layout patterns can be arranged as information represented by pattern candidate line segments formed by connecting each side of each equilateral triangle when a plurality of equilateral triangles are continuously arranged; ,
wiring rule storage means for storing wiring rule information relating to a wiring resistance value to be satisfied given to a layout pattern between macrocells;
a one-side resistance value defining unit that defines a resistance value of a pattern candidate line segment on one side of the equilateral triangle as a predetermined value;
A layout pattern for connecting macrocells is arranged on a semiconductor substrate based on the information in the pattern position information storage means , and wiring of the layout pattern is determined based on how many times the length of the layout pattern is one side of the equilateral triangle. a pattern placement unit that calculates a resistance and performs wiring of a layout pattern so that the calculated wiring resistance satisfies the wiring rule of the wiring rule storage unit;
dummy pattern placement means for selecting from patterns of a plurality of areas prepared in advance and placing a dummy pattern at the placeable position where the layout pattern is not placed, based on the information in the pattern position information storage means;
Covering for obtaining a coverage of an area occupied by a layout pattern and a dummy pattern, detecting whether a predetermined reference pattern coverage is satisfied, and controlling the dummy pattern placement means so as to satisfy the reference pattern coverage. A semiconductor layout design apparatus comprising: rate control means; 10. The semiconductor layout designing apparatus according to claim 9, wherein the information expressed by pattern candidate line segments formed by connecting a plurality of sides of said equilateral triangle is expressed by a minimum line width and a minimum pitch allowed as a layout pattern. . 11. The semiconductor layout design apparatus according to claim 9, wherein said dummy pattern placement means places dummy patterns along said pattern candidate line segments. 12. The semiconductor layout design apparatus according to claim 9, wherein said dummy pattern arrangement means arranges dummy patterns according to a figure having a shape centered on intersections of said pattern candidate lines. 13. The semiconductor layout design apparatus according to claim 12, wherein said figure is a regular polygon. 9. The coverage control means divides the mask into a plurality of areas having the same area, and controls the dummy pattern placement means so that each area satisfies a predetermined reference pattern coverage. 14. The semiconductor layout design apparatus according to any one of 13. 15. The dummy pattern arrangement unit according to claim 14, wherein said coverage control means controls the dummy pattern placement means so that the coverage of each area is balanced and each area satisfies a predetermined reference pattern coverage. Semiconductor layout design equipment. a dummy pattern candidate storage means for storing information on dummy pattern candidates having different dummy pattern shapes and/or areas;
16. The coverage control means controls the dummy pattern placement means so that each area satisfies a predetermined reference pattern coverage using the information in the dummy pattern candidate storage means. 2. The semiconductor layout design device according to claim 1.

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