JP2001028353A - Method of generating planarization pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of generating a planarization pattern with which a planarization pattern can be generated easily and calculation load can be reduced. SOLUTION: A region, where a planarization pattern is generated, is divided into a grid and an LSI layout pattern is placed (100). The LSI layout pattern is enlarged by a value L (102). Whether grid coordinates are in a region outside the enlarged figure is determined (104). If the grid coordinates are located in the outside region, a planarization pattern is generated (106, 108).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a flattening pattern, and more particularly to a method for generating a flattening pattern in an LSI layout pattern for flattening the LSI layout pattern.

[0002]

2. Description of the Related Art In order to separate a plurality of elements provided on a semiconductor substrate with the recent increase in density and miniaturization of a semiconductor device, grooves (trench grooves) are provided between the elements to electrically connect the elements. Isolation trench isolation technology has been introduced.

Generally, after an insulating film is deposited along the surface of a substrate having irregularities formed by separating elements by trench grooves, the surface is flattened. One of the surface flattening processes is chemical polishing. -Mechanical polishing method (C) for mechanically and chemically polishing a substrate surface using a polishing agent and a polishing pad.
MP method).

The CMP method is a method of polishing a substrate surface with a polishing pad while adding a chemical polishing agent, thereby chemically and mechanically polishing and flattening the substrate surface. This method has a feature that a high degree of mirror surface can be obtained because the processing unit is small, a high degree of mirror surface is used because a viscoelastic polisher is not used, and further, there is very little processing deterioration due to the use of a chemical reaction. I have.

However, in the CMP method, since the polishing pad is polished along the surface of the insulating film formed on the surface of the substrate, for example, the insulating film portion formed so as to fill a step portion such as a large trench groove is formed. As described above, when polishing a region having a slightly concave surface, the surface is polished along the concave shape of the insulating film surface.

Therefore, the surface of the finally obtained substrate is partially concave, the corners forming the steps of the pattern are cut off, and a fine pattern surrounded by a large trench is polished. In some cases, or the insulating film at the center of the trench may be partially polished and dug down.

In order to reduce such a polishing step by the CMP method, an auxiliary pattern (hereinafter, referred to as a flattening pattern) is provided in a region where no LSI layout pattern exists.
Have been proposed in order to uniform the pattern density in an LSI chip. By making the pattern density uniform by inserting the flattening pattern, it is possible to reduce the polishing step by the CMP method.

FIG. 1 shows a conventional flattening pattern generation method.
Actual LSI layout pattern 300 shown in FIG.
Is subjected to an inversion process to generate a graphic pattern 302 shown in FIG. Next, reduction processing of the inverted figure 302 is performed so that a portion of the inverted figure 302 corresponding to the LSI layout pattern 300 is enlarged, and a figure 304 indicated by a solid line in FIG. 10D is generated. next,
An AND operation is performed between the flattening pattern 306 in which the square figures shown in FIG. 10B are arranged in an array and the generated figure 304, and the flattening pattern 308 in FIG.
Generate Subsequently, the generated flattening pattern 308
Is reduced with the minimum value A that satisfies the design criterion, and the flattening pattern 310 shown in FIG. Then, a graphic enlarging process is performed on the generated flattening pattern 310 with the minimum value A that satisfies the design criteria,
The flattening pattern 312 shown in FIG. Subsequently, finally, an LSI layout pattern 300 shown in FIG. 10A and a flattening pattern 312 shown in FIG.
By performing a logical sum operation with the above, a graphic pattern in which the LSI layout pattern and the flattening pattern shown in FIG.

[0009]

However, according to the conventional method for generating a flattening pattern, a flattening pattern is generated by a complicated combination of enlargement, reduction, and logical operation processing of a figure. There's a problem. Further, in the conventional method of generating a flattening pattern,
A flattening pattern can be generated only in a region outside the LSI layout pattern in the same layer.
Therefore, there is a problem that a flattening pattern cannot be generated in an area inside an LSI pattern in a different layer or an area other than a boundary of an LSI layout pattern.

If the density of the LSI layout pattern in a certain area satisfies the process standard, it is not necessary to generate a flattening pattern in that area. In addition, a flattening pattern is generated for all regions where no LSI layout pattern exists, regardless of the density of the LSI layout pattern. Therefore, since a flattening pattern is also generated in a region where a flattening pattern is not necessary (a region where the density of the LSI layout pattern is high), there has been a problem that the processing for the flattening pattern becomes complicated and the load of calculation processing increases. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and a flattening pattern generation method capable of generating a flattening pattern by a simple method and reducing the load of calculation processing. The primary purpose is to provide.

It is a second object of the present invention to provide a method for generating a flattening pattern capable of generating a flattening pattern according to the density of an LSI layout pattern.

[0013]

According to one aspect of the present invention, there is provided a method for generating a flattening pattern for flattening an LSI chip surface on which an LSI layout pattern is arranged. Wherein said LSI
A first process of dividing a chip area into a grid, a second process of enlarging or reducing the LSI layout pattern to a predetermined size, and a grid divided by the first process. A third processing for determining whether the area is inside or outside the area of the LSI layout pattern converted by the second processing, and a generation position of the flattening pattern is determined based on the third processing. And a fourth process.

According to the first aspect of the present invention, in the first processing, the area of the LSI chip is divided into a grid and
In the process (1), the layout pattern of the LSI is enlarged or reduced to a predetermined size. And in the third processing,
It is determined whether each of the grids divided by the first processing is inside or outside the area of the LSI layout pattern converted by the second processing. And in the fourth processing,
By determining the generation position of the flattening pattern based on the result determined by the third processing, it is possible to generate the flattening pattern in a region outside or inside the LSI layout pattern on the surface of the LSI chip.

That is, a flattening pattern can be generated by a simple method without complicatedly combining enlargement / reduction of a figure and logical operation processing, and the load of calculation processing can be reduced.

According to a second aspect of the present invention, in the first aspect, the predetermined size is based on a distance between the LSI layout pattern and the flattening pattern and a size of the flattening pattern to be generated. It is characterized by the following.

According to the invention described in claim 2, according to claim 1
In the invention described in the above, when performing enlargement conversion or reduction conversion to a predetermined size in the second processing, the predetermined size is set to the distance between the LSI layout pattern and the flattening pattern and the size of the flattening pattern to be generated. Based on this, it is possible to generate a flattening pattern.

For example, the minimum design and manufacturing distance between the flattening pattern and the LSI layout pattern is L1, the size (maximum) of the flattening pattern is L2, and the predetermined size to be converted is L = Assuming that the value satisfies the equation of L1 + L2 / 2, a flattening pattern is generated at the position determined by the third processing and determined at the fourth processing, thereby forming a flattening pattern on the boundary region of the LSI layout pattern. , It is possible to generate a flattening pattern in a region outside or inside a LSI layout pattern.

According to a third aspect of the present invention, in the first or second aspect, the LSI layout pattern is enlarged and converted by the second processing, and the grid determined by the third processing is converted. Among them, a flattening pattern is generated on a grid determined to be outside the area of the LSI layout pattern subjected to the enlargement conversion.

According to the invention of claim 3, according to claim 1,
Alternatively, in the invention described in claim 2, the LSI layout pattern is enlarged and converted to a predetermined size by the conversion in the second processing. Then, in the third processing, the first
When the respective grids divided by the above processing are outside the area of the enlarged and converted LSI layout pattern, a flattening pattern is generated. That is, a flattening pattern can be generated in a region outside the LSI layout pattern. Therefore, LS can be performed in a simple manner without complicatedly combining the enlargement / reduction of the figure and the logical operation processing.
A flattening pattern can be generated in an area outside the I layout pattern area, and the load of calculation processing can be reduced.

According to a fourth aspect of the present invention, in the first or second aspect, the LSI layout pattern is reduced and converted by the second processing, and the grid determined by the third processing is converted. Among them, a flattening pattern is generated on a grid determined to be inside the area of the reduced and converted LSI layout pattern.

According to the invention described in claim 4, according to claim 1,
Alternatively, in the invention according to claim 2, the layout pattern is converted into a reduced figure having a predetermined size by the conversion in the second processing. Then, in the third processing, the first
When the respective grids divided by the above processing are inside the area of the reduced and converted LSI layout pattern, a flattening pattern is generated. That is, a flattening pattern can be generated in a region inside the LSI layout pattern. Therefore, LS can be performed in a simple manner without complicatedly combining the enlargement / reduction of the figure and the logical operation processing.
A flattening pattern can be generated in an area inside the I layout pattern area, and the load of calculation processing can be reduced.

According to a fifth aspect of the present invention, there is provided a flattening pattern generating method for flattening an LSI chip surface on which an LSI layout pattern is arranged,
A first process of dividing the area of the LSI chip into a grid, a second process of enlarging and converting the LSI layout pattern to a predetermined size, and a second process of reducing and converting the LSI layout pattern to a predetermined size. A fourth process of determining whether each grid divided by the first process is inside or outside an area of the LSI layout pattern converted by the second process; and A fifth process of determining whether each grid divided by the first process is inside or outside the area of the LSI layout pattern converted by the third process; and a fourth process and a fifth process. And a sixth process of determining a generation position of the flattening pattern based on the process.

According to the fifth aspect of the present invention, in the first processing, the area of the LSI chip is divided into grids,
In the process (3), the layout pattern of the LSI is enlarged and converted into a predetermined size, and in the third process, the LSI layout pattern is reduced and converted into a predetermined size. Then, in the fourth processing, it is determined whether each of the grids divided in the first processing is inside or outside the area of the LSI layout pattern converted in the second processing, and in the fifth processing, It is determined whether each of the grids divided by the first process is inside or outside the area of the LSI layout pattern converted by the third process. In the sixth process, the generation position of the flattening pattern is determined based on the result determined by the fourth and fifth processes, so that the flattening pattern is formed on the surface of the LSI chip other than the boundary region of the LSI layout pattern. Can be generated.

That is, it is possible to generate a flattening pattern in a region other than the boundary region of the LSI layout pattern by a simple method without complicatedly combining the enlargement / reduction of the figure and the logical operation processing, thereby reducing the load of the calculation processing. it can.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, the predetermined size is based on a distance between the LSI layout pattern and the flattening pattern and a size of the flattening pattern to be generated. It is characterized by the following.

According to the invention described in claim 6, according to claim 5,
In the invention described in the above, when performing the enlargement conversion to a predetermined size by the second process and when performing the reduction conversion to the predetermined size by the third process, the predetermined size is flattened with the LSI layout pattern. By determining based on the distance from the pattern and the size of the flattening pattern to be generated, the flattening pattern can be generated in a region other than the boundary region of the LSI layout pattern.

For example, the minimum distance between the flattening pattern in design and manufacture and the LSI layout pattern is L.
1. If the size (maximum) of the flattening pattern is L2 and the predetermined size to be converted is a value that satisfies the formula of L = L1 + L2 / 2, it is determined by the fourth and fifth processes and the sixth process is performed. By generating a flattening pattern at the position determined by the processing, it is possible to generate a flattening pattern outside the boundary region of the LSI layout pattern without generating a flattening pattern on the boundary region of the LSI layout pattern. .

According to a seventh aspect of the present invention, in the invention according to the fifth or sixth aspect, of the grid determined in the fourth processing, the grid outside the area of the enlarged and converted LSI layout pattern. A flattening pattern is generated on the grid determined to be the same, and a flattening pattern is generated on the grid determined to be inside the area of the reduced and converted LSI layout pattern among the grids determined in the fifth processing. It is characterized in that a conversion pattern is generated.

[0030] According to the invention described in claim 7, according to claim 5 of the present invention.
Alternatively, in the invention according to claim 6, a flattening pattern is generated in a grid determined to be outside the area of the LSI layout pattern subjected to the enlargement conversion by the fourth processing, and the reduction conversion is performed by the fifth processing. By generating a flattening pattern on a grid determined to be inside the area of the LSI layout pattern thus set, a flattening pattern can be generated in an area other than the boundary area of the LSI layout pattern.

The invention according to claim 8 is a LS having a multilayer structure.
Claims 1 to 7 for the I layout pattern.
The flattening pattern is generated by using the flattening pattern generating method according to any one of the above.

According to the invention described in claim 8, the planarization according to any one of claims 1 to 5, for an LSI layout pattern having a multilayer structure, that is, an LSI layout pattern on a plurality of layers. It is possible to use a pattern generation method.

According to a ninth aspect of the present invention, there is provided a flattening pattern generating method for flattening an LSI chip surface on which an LSI layout pattern is arranged,
A first process of dividing the area of the LSI chip into a grid, and calculating a density of an area including a periphery of the area divided into the grid by the first process, and flattening based on the calculated density. And a second process for generating a pattern.

According to the ninth aspect of the present invention, in the first processing, the area of the LSI chip is divided into grids. Further, in the second processing, the density of the area including the periphery of the area divided in the grid shape by the first processing is calculated, and based on the calculated density, for example, when the calculated density is low, flattening is performed. Generate a pattern. Therefore, it is possible to generate a flattening pattern according to the density of the LSI layout pattern.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

First, in describing a method of generating a flattening pattern, a flattening pattern to be generated and a grid for arranging the flattening pattern will be described.

FIG. 1A shows an LSI layout pattern 10 before a flattening pattern is inserted. FIG. 1 (c)
2 shows a rectangular flattening pattern 12 as an example of the flattening pattern to be generated. As shown in FIG. 1C, in the flattening pattern 12, the horizontal direction in FIG. 1 is the X direction, the vertical direction is the Y direction, the distance in the X direction of the flattening pattern is X, the distance in the Y direction is Y, The coordinates indicating the value of (X / 2, Y / 2) are defined as the center point 14 of the flattening pattern 12. Further, the minimum distance between the flattening pattern and the LSI layout pattern is set to L1, and the value of the distance X in the X direction of the flattening pattern 12 and the value of the distance Y in the Y direction are compared, and the larger value is set to L2. Note that L1 is the minimum value allowed in the LSI manufacturing process.

The shape of the flattening pattern to be generated is not limited to the rectangular flattening pattern 12 shown in FIG. 1C, but may be a flattening pattern of any shape, for example, 5 as shown in FIG. A rectangular flattening pattern 13 may be used. In this case, as in the case of the flattening pattern 12 shown in FIG. 1C, L2 is obtained by setting the distance in the X direction to X and the distance in the Y direction to Y.

FIG. 1B shows grid coordinates 16 representing each coordinate arrangement position at which the flattening pattern 12 is generated in a grid shape (grid shape). Here, the minimum value in the X direction of the generation region of the flattening pattern is SX1, the maximum value in the X direction is SX2,
The minimum value in the Y direction is SY1, and the maximum value in the Y direction is SY2.
Further, the pitch in the X direction for disposing the flattening pattern 12 is P
The pitch in the X and Y directions is PY. Note that the pitch in the X direction P
The pitches PY in the X and Y directions are values determined by restrictions on the LSI manufacturing process.

Here, the number of arrangements GNX in the X direction in the generation region of the flattening pattern 12 is SX2−SX1> PX × G
NX + L2 is the largest integer that satisfies NX + L2, and the minimum arrangement coordinate X0 in the X direction is X0 = SX1 + ((SX2-SX1)-
PX × GNX) / 2. Similarly, Y
The number of arrangements GNY in the direction is SY2−SY1> PX × GNY
+ L2 is the largest integer, and the minimum arrangement coordinate Y0 in the Y direction is Y0 = SY1 + ((SY2-SY1) -PY
X GNY) / 2.

Subsequently, when the flattening pattern 12 is generated in the area outside the LSI layout pattern 10 using the flattening pattern 12 and the grid coordinates 16 configured as described above, the area inside the LSI layout pattern 10 is generated. 5A and 5B, each of the cases where it is generated in a region other than the boundary of the LSI layout pattern 10 is shown in FIG.
This will be described in detail with reference to the flowchart of FIG.

A case where the flattening pattern 12 is generated in a region outside the LSI layout pattern will be described with reference to FIG.

In step 100, the LSI layout pattern 10 is arranged on the above-mentioned grid, and
Move to 2. In step 102, the LSI layout pattern 10 shown in FIG. 1A is subjected to graphic enlargement processing with a value L calculated by L = L1 + L2 / 2, and a graphic pattern (enlargement) shown by a solid line in FIG. Then, the process proceeds to step 104.

In step 104, for each grid coordinate 16, it is determined whether or not the grid coordinate 16 is a region outside the enlarged figure 20 (FIG. 2B). If the determination is affirmative, the process proceeds to step 106, where the grid coordinates 16 are set as the generation coordinate positions of the flattening pattern 12 (FIG. 2C). A flattening pattern is generated so as to overlap the coordinates 16 (FIG. 2D), and the process proceeds to step 110.

If the determination in step 104 is denied, it is determined that the grid coordinates 16 are inside the enlarged figure 20, and steps 106 and 108 are skipped and the process proceeds to step 110.

In step 110, it is determined whether or not the determination in step 104 has been completed for all the grid coordinates 16 described above. If the determination is affirmative, it is determined that the determination in step 104 has been completed for all grid coordinates 16, and a series of processing ends. If the determination in step 110 is negative, the process returns to step 104, and the above steps 104 to 110 are repeated until the determination in step 110 is affirmative.

With the above processing, as shown in FIG. 2E, a flattening pattern 12 can be generated in an area outside the LSI layout pattern 10 on an arbitrarily designated layer. Therefore, unlike the conventional method of generating a flattening pattern, it is possible to easily generate the flattening pattern 12 without performing a complicated combination of enlargement, reduction, and logical operation processing of a figure, and to reduce the load on the calculation processing. Can be reduced.

The flattening pattern 12 is generated on the same layer as the LSI layout pattern 10 or on a different layer.

A case where the flattening pattern 12 is generated in a region inside the LSI layout pattern will be described with reference to FIG.

In step 120, the LSI layout pattern 10 is arranged on the above-mentioned grid, and in step 12
Move to 2. In step 122, the LSI layout pattern 10 shown in FIG. 3A is subjected to a graphic reduction process using a value L calculated by L = L1 + L2 / 2, and a graphic pattern (reduced image) shown by a solid line in FIG. Then, the process proceeds to step 124.

In step 124, for each grid coordinate 16, it is determined whether or not the grid coordinate 16 is an area inside the reduced graphic 112 (FIG. 3B). If the determination is affirmative, the routine proceeds to step 126, where the grid coordinates 16 are set as the generation coordinate positions of the flattening pattern 12 (FIG. 3C).
Then, a flattening pattern is generated such that the center point 14 of (c) overlaps the grid coordinates 16 (FIG. 3D), and the process proceeds to step 130.

If the determination in step 124 is denied, it is determined that the grid coordinates 16 are outside the reduced graphic 112, and the process skips steps 126 and 128 and proceeds to step 130.

In step 130, it is determined whether or not the determination in step 124 has been completed for all the grid coordinates 16 described above. If the determination is affirmative, it is determined that the determination in step 124 has been completed for all grid coordinates 16, and a series of processing ends. If the determination in step 130 is negative, the process returns to step 124, and the above steps 124 to 130 are repeated until the determination in step 130 is affirmative.

By the above processing, as shown in FIG. 3E, a flattening pattern 12 can be generated in an area inside the LSI layout pattern 10 on an arbitrarily designated layer. Therefore, unlike the conventional method of generating a flattening pattern, it is possible to easily generate the flattening pattern 12 without performing a complicated combination of enlargement, reduction, and logical operation processing of a figure, and to reduce the load on the calculation processing. Can be reduced.

The flattening pattern 12 is generated in a different layer from the LSI layout pattern 10.

The case where the flattening pattern 12 is generated in a region other than the boundary of the LSI layout pattern 10 will be described.
This will be described with reference to FIG.

In step 150, the LSI layout pattern 102 is arranged on the grid described above, and in step 1
Move to 52. In step 152, the LSI layout pattern 10 shown in FIG. 4A is changed to L = L1 + L2 / 2.
The figure is enlarged by the value L calculated in step (a), and FIG.
Then, a graphic pattern (enlarged graphic) 20 as shown by the solid line is generated, and the process proceeds to step 154.

In step 154, the LSI layout pattern 10 is subjected to graphic reduction processing using a value L calculated by L = L1 + L2 / 2, and a graphic pattern (reduced graphic) 22 as shown in FIG. 4B is generated. , To step 156.

At step 156, for each grid coordinate 16, it is determined whether or not the grid coordinate 16 is an area outside the enlarged figure 20 obtained at step 152 (FIG. 4C). If the determination is affirmative, the process proceeds to step 158, where the grid coordinates 16 are set as the generation coordinate positions of the flattening pattern 12 (FIG. 4D), and
0 means that the center point 14 of the flattening pattern 12 is grid coordinate 1
6 is generated (FIG. 4).
(E)), and proceed to step 164.

If the determination in step 156 is negative, the process proceeds to step 162, where the grid coordinates 16
Is determined whether or not is an area inside the reduced graphic 112 obtained in step 154. If the determination is affirmative, the process proceeds to step 158, where the grid coordinates 16 are set as the generation coordinate positions of the flattening pattern 12 (FIG. 4D). A flattening pattern is generated so as to overlap the coordinates 16 (FIG. 4E).

If the determination in step 162 is negative, steps 158 and 160 are skipped, and the process proceeds to step 164.

In step 164, it is determined whether or not the determination in step 156 has been completed for all the grid coordinates 16 described above. If the determination is affirmative, it is determined that the determination in step 156 has been completed for all grid coordinates 16, and a series of processing ends. If the determination in step 164 is negative, the process returns to step 156, and the above steps 156 to 162 are repeated until the determination in step 164 is affirmative.

By the above processing, as shown in FIG. 4F, a flattening pattern 12 can be generated in an area other than the boundary of the LSI layout pattern 10 on an arbitrarily designated layer. Therefore, unlike the conventional method of generating a flattening pattern, it is possible to easily generate the flattening pattern 12 without performing a complicated combination of enlargement, reduction, and logical operation processing of a figure, and to reduce the load on the calculation processing. Can be reduced.

The flattening pattern 12 is generated in a different layer from the LSI layout pattern 10.

Subsequently, a flattening pattern 12 based on the density of the LSI layout pattern 10 according to the present invention
Will be described with reference to the flowchart of FIG.

As shown in FIG. 8A, the surface of the LSI chip is divided into a grid (grid), and the size of each grid in the X direction is GX, and the size in the Y direction is GY. For the grid sizes GX and GY, any value can be individually specified. In addition, the number of grid-like divisions is XN from X [0] to X [XN-1] in the X direction,
It is divided into YN grids from Y [0] to Y [YN-1] in the Y direction, and the number N of grids is N = XN ×
The number of grids is YN.

The LSI layout pattern 10 arranged on the LSI chip is divided into grids as described above, and the graphic patterns 24 and 26 shown in FIG.
28. The area is calculated for each of the divided graphic patterns 24, 26, and 28,
By calculating the sum, the area S2 of the target LSI layout pattern 10 can be calculated. The target LSI layout pattern 10 can be subjected to graphic pattern enlargement processing or reduction processing before division as necessary.

Then, in step 200, the area of the region for referring to the pattern density is calculated. As shown in FIG. 8C, the reference area 30 of the pattern density in Step 200 indicates an area including the peripheral areas of the odd-numbered grids XM and YM with each divided area 32 being the center, and the area S1 of the reference area is
It can be calculated as S1 = GX × GY × XM × YM.

In step 202, the area S 2 of the LSI layout pattern 10 existing in the reference area 30 is calculated, and the flow shifts to step 204.

In step 204, the area S 1 of the reference area 30 and the area S 2 of the LSI layout pattern 10 existing in the reference area 30 are calculated based on S 2 / S 1.
Is calculated. Here, the calculated pattern density is defined as the pattern density of the divided area 32.

In step 206, it is determined whether the pattern density calculated in step 204 is lower than a predetermined pattern density. If the determination is affirmative, step 208
The process proceeds to step 208, where a flattening pattern is generated in the divided region 32 in step 208, and the process proceeds to step 210. The flattening pattern generation in step 208 can be performed according to the flowchart described in any of FIGS.

If the determination in step 206 is negative, step 208 is skipped and the routine proceeds to step 210. That is, since the predetermined pattern density is satisfied, there is no need to generate a flattening pattern, and no flattening pattern is generated in the divided region.

In the following step 210, it is determined whether or not the calculation of the pattern density of all the divided areas has been completed. If the determination is affirmative, it is determined that a flattening pattern has been generated for all the divided areas based on the pattern density, and the series of processing ends.

If the determination in step 210 is negative, the process moves to step 212, moves the reference area 30 of pattern density, returns to step 200, and returns to step 21.
Until the determination of 0 is affirmative, the above-described steps 210-2
By repeating step 12, a flattening pattern is generated for each divided region based on the pattern density.

By the above processing, the flattening pattern 12 can be generated only in a portion having a low pattern density in the LSI chip. That is, the generation of the flattening pattern 12 is not performed in an area where the flattening pattern 12 does not need to be generated. Therefore, it is possible to prevent the process of generating the flattening pattern from being complicated, and to reduce the load of the calculation process.

Although the above embodiment has been described on the assumption that an LSI layout pattern is arranged,
For an area where there is no LSI layout pattern, the center point 14 of the flattening pattern 12 may be generated so as to overlap the grid coordinates 16 or the flattening pattern may not be generated.

[0077]

As described above, according to the present invention, a flattening pattern can be generated by a simple method, and the load of calculation processing can be reduced.

Further, there is an effect that a flattening pattern can be generated according to the density of the LSI layout pattern.

[Brief description of the drawings]

FIG. 1 is a diagram showing an LSI layout pattern, a grid, and a flattening pattern according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a case where a flattening pattern is generated in a region outside an LSI layout pattern.

FIG. 3 is a diagram showing a case where a flattening pattern is generated in a region inside an LSI layout pattern.

FIG. 4 is a diagram showing a case where a flattening pattern is generated in a region other than a boundary of an LSI layout pattern.

FIG. 5 is a flowchart showing processing when a flattening pattern is generated in an area outside an LSI layout pattern.

FIG. 6 is a flowchart showing processing when a flattening pattern is generated in an area inside an LSI layout pattern.

FIG. 7 is a flowchart showing processing when a flattening pattern is generated in an area other than the boundary of an LSI layout pattern.

FIG. 8 is a diagram showing a case where a flattening pattern is generated based on the density of an LSI layout pattern according to the embodiment of the present invention.

FIG. 9 is a flowchart illustrating a process when a flattening pattern is generated based on the density of an LSI layout pattern.

FIG. 10 is a diagram for explaining a conventional flattening pattern generation method.

[Explanation of symbols]

 Reference Signs List 10 LSI layout pattern 12 Flattening pattern 16 Grid coordinates 20 Enlarged figure 22 Reduced figure 30 Reference area 32 Division area

Claims (9)

[Claims] 1. A method for generating a flattening pattern generated for flattening the surface of an LSI chip on which an LSI layout pattern is arranged, comprising: a first process of dividing an area of the LSI chip into a grid. A second processing for enlarging or reducing the LSI layout pattern to a predetermined size, and grids divided by the first processing,
A third processing for determining whether the area is inside or outside the area of the LSI layout pattern converted by the second processing; and a third processing for determining a generation position of a flattening pattern based on the third processing. 4. A method for generating a flattening pattern, the method comprising: 2. The flattening pattern according to claim 1, wherein the predetermined size is determined based on a distance between the LSI layout pattern and the flattening pattern and a size of the flattening pattern to be generated. Generation method. 3. The LSI layout pattern is enlarged and converted by the second processing, and the grid determined by the third processing is determined to be outside the area of the enlarged and converted LSI layout pattern. 3. The method according to claim 1, wherein a flattening pattern is generated on the grid. 4. The LSI layout pattern is reduced and converted by the second processing, and the grid determined by the third processing is determined to be inside the area of the reduced and converted LSI layout pattern. 3. The method according to claim 1, wherein a flattening pattern is generated on the grid. 5. A method for generating a flattening pattern generated for flattening the surface of an LSI chip on which an LSI layout pattern is arranged, comprising: a first process of dividing the area of the LSI chip into a grid. A second process for enlarging and converting the LSI layout pattern to a predetermined size; a third process for reducing and converting the LSI layout pattern to a predetermined size; The grid
A fourth processing of determining whether the area is inside or outside the area of the LSI layout pattern converted by the second processing; and each grid divided by the first processing is:
Fifth processing for determining whether the area is inside or outside the area of the LSI layout pattern converted by the third processing; and determining a flattening pattern generation position based on the fourth and fifth processing. A flattening pattern generating method. 6. The flattening pattern according to claim 5, wherein the predetermined size is determined based on a distance between the LSI layout pattern and the flattening pattern and a size of the flattening pattern to be generated. Generation method. 7. A flattening pattern is generated on a grid determined to be outside the area of the enlarged and converted LSI layout pattern among grids determined in the fourth processing, and a fifth processing is performed. The flattening pattern is generated on a grid determined to be inside the area of the reduced and converted LSI layout pattern among the grids determined in (5). A method for generating a flattening pattern. 8. A flattening method, wherein a flattening pattern is generated for an LSI layout pattern having a multi-layer structure by using the flattening pattern generating method according to any one of claims 1 to 7. How to generate the pattern. 9. A method for generating a flattening pattern generated for flattening the surface of an LSI chip on which an LSI layout pattern is arranged, comprising: a first process of dividing an area of the LSI chip into a grid. A second process of calculating the density of an area including the periphery of the area divided into a grid by the first processing, and generating a flattening pattern based on the calculated density. A method for generating a flattening pattern.