JP7221198B2 - Fabricate unique chips using a charged particle multi-beamlet lithography system - Google Patents

Description

[0001] The present invention relates to methods of manufacturing or fabricating electronic devices, such as semiconductor chips. More particularly, the present invention relates to fabrication of unique chips using a charged particle multi-beamlet lithography machine, the uniqueness of a chip being defined by structures such as via structures on the chip. Consequently, the present invention equally improves not only the so-called "fabrication plant", i.e. the manufacturing facility that applies this new method, but also the unique chips that are produced using this new method of manufacture. maskless lithography exposure system adapted to carry out the method of fabrication. The invention further relates to a computer-implemented method for generating beamlet control data for controlling a maskless pattern writer to expose a wafer for fabrication of electronic devices. The invention also relates to a computer-implemented method for generating selection data for use in generating beamlet control data. The present invention further relates to data processing systems, computer program products, and computer readable storage media relating to computer-implemented methods.

[0002] In the semiconductor industry, lithography systems are commonly used to create or fabricate such electronic devices in the form of integrated circuits formed on silicon wafers, commonly referred to as semiconductor chips. Photolithography utilizes reusable photomasks to project images of patterns representing desired circuit structures onto silicon wafers as part of the manufacturing process. The mask is used repeatedly to image the same circuit structures onto different portions of the silicon wafer and onto the next wafer, resulting in a series of identical chips being fabricated with each wafer, each chip having the same circuit design. .

[0003] In modern times, a variety of technologies related to data security, traceability, and anti-counterfeiting have been developed for unique chips with unique circuits or codes, or other unique hardware features for chip versatility. creating a growing need. Such unique chips are known and often implement security-related operations in an obfuscated way that requires the chip to be truly unique. Known unique chips are typically manufactured using, for example, mask-based lithography to produce a series of identical chips and then interrupting certain connections of the chips after production, or during inspection and control of certain features of the chips. This is achieved after chip fabrication by later evaluating the uniqueness of . The masks used in this process are expensive to produce, and making a unique mask for each single chip is clearly far too expensive, so mask-based photolithography produces unique chips. is considered inappropriate for

[0004] Accordingly, it has been proposed to exploit maskless lithography to create unique chips. With maskless lithography, no mask is used, instead the required pattern representing the circuit design is transferred onto a target, e.g. a wafer, and exposed by a maskless lithography system. It is input to the maskless lithography system in the form of a data file, such as a file or OASIS file.

[0005] A maskless lithography and data entry system is disclosed in WO2010/134026 in the name of the applicant of the present invention. WO2010/134026 is incorporated herein by reference in its entirety. The disclosed maskless system uses charged particle beamlets, such as electron beamlets, to write patterns directly onto the wafer. Since the desired pattern for exposing each chip is represented as data instead of a mask, it is possible to exploit such a system for the production of unique chips. The pattern data input to the exposure system representing the unique electronic device or chip to be produced can be made unique by using a different GDSII input file for each unique electronic device to be produced.

[0006] WO 2011/117253 and WO 2011/051301, both assigned to the assignee of the present invention and incorporated herein by reference in their entirety, disclose electron Various examples of devices or chips are disclosed.

[0007] However, the simple method of creating secure, at least unique devices, ie, using known maskless exposure systems, is not optimized for safely producing unique electronic devices, but is at least adaptive. may not be Unfortunately, the processing of GDSII or OASIS files associated with this specification is typically performed in addition to the operations of the operator of the lithography system. Additionally, the processed GDSII/OASIS files may be used and stored over a longer period of time. Since the uniqueness of electronic devices or chips is typically used for data security, traceability, and anti-counterfeiting applications, the unique via design data used in the creation of unique electronic devices or chips for security reasons. Minimizing exposure and exposure time is considered desirable, insightfully fundamental, and a de facto part of the present invention.

[0008] The present invention provides a solution for the fabrication of unique electronic circuits by implementing different structures on different chips, while minimizing disclosure of the specific structures used in making the chips. can be done. Non-limiting examples of such structures are connections between metal layers, also known as vias, connections between metal layers and the gates of e.g. P-implant or N-implant of a specific part. One way to make a chip unique is by implementing different structures on different chips. For example, the number of vias and via locations may vary from chip to chip. The different paths created by the vias in this manner present the same data input to the chip, resulting in different data outputs from chip to chip. In this regard, for a particular portion of the electronic device layout, selection data is provided to define which of the vias are to be enabled within the chip, giving rise to discrete areas on the chip. be able to.

[0009] All possible structures from which a selection is made to treat a chip or batch of chips individually can be part of a general design layout data, such as a GDSII file or an OASIS file. be. The location of selectable structures can be provided as location metadata. Particular portions can be treated individually by enabling different sets of structures for different subsets of electronic devices based on location metadata and selection data. Structure selection can be made at a late processing stage near or within a maskless lithographic exposure system, thereby revealing specific structures used to individualize electronic devices. to a minimum.

[0010] When maskless lithographic processes are used to form non-common structures, such as connections between metal layers, these are formed by merging two conductive vias to form a double via. good.

[0011] According to an aspect of the invention, a method of manufacturing an electronic device using a maskless lithographic exposure system is proposed. A maskless lithographic exposure system can use a maskless pattern writer. The method may include generating beamlet control data for controlling a maskless pattern writer to expose a wafer for fabrication of electronic devices. Beamlet control data can be generated based on design layout data defining multiple structures for electronic devices manufactured from the wafer. The beamlet control data can be generated further based on selection data defining which structures of the design layout data are applicable for each electronic device manufactured from the wafer, the selection data being for different portions of the electronic device. Define different sets of structures for sets. Exposing the wafer according to the beamlet control data will expose patterns with different sets of structures for different subsets of electronic devices.

[0012] According to an aspect of the invention, a computer-implemented method for generating beamlet control data is proposed. Using a maskless lithography exposure system using a maskless pattern writer, the beamlet control data can be used to control the maskless pattern writer to expose wafers for the fabrication of electronic devices, thereby generating beamlets. Exposing the wafer according to the control data will expose patterns having different sets of structures for different subsets of electronic devices. The method may include receiving design layout data defining a plurality of structures for electronic devices manufactured from the wafer. The method may further include receiving selection data defining which structures of the design layout data are applicable for each electronic device manufactured from the wafer. The selection data can define different sets of structures for different subsets of electronic devices. The method may further include generating beamlet control data based on the received design layout data and the received selection data.

[0013] The maskless pattern writer may be a raster scan-based maskless pattern writer, in which case the beamlet control data may be in the form of pattern bitmap data. The maskless pattern writer may be a vector scan-based maskless pattern writer, in which case the beamlet control data may be formatted appropriately for vector scanning.

[0014] Electronic devices can be individually addressed or made unique by enabling different sets of structures, such as by creating different vias in each of the electronic devices.

[0015] Advantageously, the method allows the creation of discretely addressed regions of an electronic device to remain within the operation of a maskless lithography exposure system, and the design data of the discretely addressed regions can be Publishing time is kept to a minimum. A beneficial side effect is that the processing power and memory requirements can remain low in that the design layout data can be reused for the creation of multiple chips, a known method of creating unique chips. requires design layout data for each unique chip, and thus space and processing time for each unique chip design manufactured.

[0016] In an embodiment, the design layout data may include common design layout data defining structures applicable to all of the electronic devices. The design layout data may further include non-common design layout data defining structures applicable to a particular one of the electronic devices from which different sets of structures are selectable according to the selection data. In this way, structures may be located in common parts of an electronic device and in areas addressed individually.

[0017] In an embodiment, the selection data specifies, for each of the electronic devices, whether the beamlet control data includes or does not include data defining one or more of the structures defined in the design layout data. can.

[0018] The selection data may use a single bit to specify individual structures of structures defined in the design layout data that are included or not included in the beamlet control data. Advantageously, this minimized the size of the selection data.

[0019] The beamlet control data may include bitmap data representing a selected subset of structures defined in the design layout data, and representing non-selected structures within the structures defined in the design layout data. May not contain bitmap data.

[0020] The selected subset of structures may include structures indicated for selection in the selection data, and non-selected structures within the structures include structures not indicated for selection in the selection data. Sometimes.

[0021] The beamlet control data may be generated once per field.

[0022] In an embodiment, the design layout data includes only design layout data defining structures that are selectable according to the selection data. In this case optical lithography may be applied in conjunction with maskless lithography, and common parts of electronic devices are made using photolithography. Individually addressed regions of the electronic device are then created as described above.

[0023] In an embodiment, the method further comprises receiving design layout data via a first network path and receiving selection data via a second network path separate from the first network path. may include This allows provisioning of design layout data and selection data from different sources. The selection data is typically received from a source external to the maskless lithography exposure system, such as from a black box device in the production portion of the fab.

[0024] A large amount of data is usually involved, for example as design layout data in the form of GDSII data files or OASIS data files. Alternatively, the selection data may be in the form of relatively small files, and the first network path may have a higher data transmission bandwidth than the second network path. The first network path is based, for example, on fiber optic network connections. A second network path is based, for example, on a Category 6 Ethernet network connection.

[0025] In embodiments, generating beamlet control data may be further based on location metadata. Location metadata can specify the location of structures defined in the design layout data. Location metadata thus identifies the location of structures in the design layout. The selection data, on the other hand, identifies which structures are included in the beamlet control data for the creation of the electronic device. Advantageously, the size of the selection data and location metadata is typically small compared to the design layout data, and the location metadata uses relatively low bandwidth and low cost network connections, for example based on Category 6 Ethernet. and enable provisioning of select data to a maskless lithography exposure system.

[0026] In embodiments, one or more of the structures defined in the design layout data may be selected for inclusion in the beamlet control data based on both location metadata and selection data.

[0027] The design layout data may include location metadata. Accordingly, location metadata may be received at a maskless lithography exposure system along with design layout data. Location metadata may be embedded with design layout data or may be received as a separate file.

[0028] Alternatively, the location metadata may be received separately from the design layout data. Accordingly, the location metadata may be received via different network routes and/or addressed to different subsystems of the maskless lithography exposure system. Location metadata may be received with the selection data.

[0029] Selection data may be received in encrypted form to provide additional data security within the manufacturing plant in the process of creating a unique electronic device.

[0030] Beamlet control data may be encrypted to provide additional data security within the manufacturing plant in the process of creating unique electronic devices.

[0031] In embodiments, the method may further comprise generating wipeout mask data based on the location metadata and the selection data. Generating the beamlet control data may include merging the wipeout mask data with the design layout data or a derivative of the design layout data to remove unselected structures from the design layout data.

[0032] In an embodiment, the electronic device may be a semiconductor chip. A maskless pattern writer may be a charged particle multi-beamlet lithography machine or an e-beam machine.

[0033] According to an aspect of the present invention, an electronic device, such as a semiconductor chip, is proposed that is made using one or more of the methods described above.

[0034] In an embodiment, the electronic device may be a truly unique semiconductor chip that is different, eg functionally different, from any other semiconductor chip that uses the method of the invention.

[0035] In embodiments, a structure may be a connection between metal layers, also known as a via, a connection between a metal layer and the gate of a contact layer, a connection at a local interconnect layer, or a particular portion of a transistor or diode. at least one of a P implant or an N implant.

[0036] According to an aspect of the present invention, there is proposed a maskless lithographic exposure system configured to perform one or more of the methods described above.

[0037] In an embodiment, the maskless lithography exposure system is configured to generate selection data defining which structures of the design layout data are applicable to each electronic device manufactured from the wafer. The selection data defines different sets of structures for different subsets of electronic devices.

[0038] The black box may be owned by a third party, such as the owner of the IP block or the owner of the manufactured chip, or the owner of the key management infrastructure. Advantageously, the black box can be installed in a manufacturing plant close to the operation of the lithography machines, thereby minimizing exposure of selection data. This is in contrast to known chip manufacturing solutions where a black box for individually handling chips is usually installed outside the manufacturing plant and used to individually handle chips after they are made. be.

[0039] According to an aspect of the present invention, a semiconductor fab is proposed comprising a maskless lithographic exposure system as described above.

[0040] According to an aspect of the present invention, a lithography subsystem is proposed that includes a rasterizer and uses a maskless pattern writer, such as a charged particle multi-beamlet lithography machine or an e-beam machine. A rasterizer can be configured to generate beamlet control data for controlling a maskless pattern writer to expose a wafer for fabrication of electronic devices. Beamlet control data can be generated based on design layout data defining multiple via structures for electronic devices manufactured from the wafer. The beamlet control data may be generated further based on selection data defining which structures of the design layout data are applicable for each electronic device manufactured from the wafer, the selection data defining the electronic device. define different sets of structures for different subsets of Exposing the wafer according to the beamlet control data will expose a pattern with different subsets of via structures for different subsets of electronic devices.

[0041] In an embodiment, the rasterizer may be configured to receive pattern vector data in a format specific to the lithography subsystem, generated from the design layout data, for example based on the OASIS file format. The rasterizer can be further configured to receive selection data. The rasterizer can be further configured to specify respective locations of structures defined in the design layout data and to receive location metadata selectable according to the selection data. The rasterizer can be further configured to process pattern vector data, common via metadata, and unique via metadata to obtain beamlet control data.

[0042] According to one aspect of the present invention, an electronic device is proposed that can be produced using the lithography subsystem described above.

[0043] In an embodiment, the electronic device may be a truly unique semiconductor chip, different from any other manufactured semiconductor chip.

[0044] According to an aspect of the present invention, an electronic device is proposed that may include a semiconductor chip. A semiconductor chip may include multiple structures formed in three or more layers of the semiconductor chip. The semiconductor chips may be members of a collection of semiconductor chips, each semiconductor chip of the collection having a common structure present in all of the semiconductor chips of the collection and a non-common structure present only in a subset of the semiconductor chips of the collection. It has a set of structures. The non-common structure can be formed in at least a first layer of layers having a second layer of layers above the first layer and a third layer of layers below the first layer.

[0045] According to an aspect of the present invention, an electronic device is proposed that may include a semiconductor chip. A semiconductor chip may include multiple structures formed in multiple layers of the semiconductor chip. The semiconductor chips may be members of a collection of semiconductor chips, each semiconductor chip of the collection having a common structure present in all of the semiconductor chips of the collection and a non-common structure present only in a subset of the semiconductor chips of the collection. It has a set of structures. Non-common structures include connections between metal layers of multiple layers, connections between metal layers and gates of contact layers of multiple layers, connections at local interconnect layers of multiple layers, and connections within layers of multiple layers. It may include at least one of the P-doped or N-doped diffusion regions of a transistor or diode.

[0046] In embodiments, common and non-common structures of a semiconductor chip can be interconnected to form an electronic circuit.

[0047] In embodiments, the electronic device may include at least one input terminal for receiving the challenge and at least one output terminal for outputting the response. The electronic circuit can form a challenge-response circuit connected to at least one input terminal and at least one output terminal. A challenge-response circuit can be adapted to generate a response at the at least one output terminal based on a challenge applied to the at least one input terminal, the challenge and response having a predetermined relationship.

[0048] According to an aspect of the present invention, a data processing system comprising a processor configured to perform the method for generating beamlet control data of one or more of the embodiments described above. is proposed.

[0049] According to an aspect of the present invention, there is proposed a computer program product implemented on a computer-readable non-transitory storage medium, the computer-readable non-transitory storage medium comprising: Instructions are provided to cause a computer to perform the method for generating beamlet control data of one or more of the embodiments described above.

[0050] According to aspects of the present invention, instructions that, when executed by a computer, cause the computer to perform a method for generating beamlet control data of one or more of the embodiments described above. A computer-readable non-transitory storage medium comprising:

[0051] According to an aspect of the invention, a computer-implemented method for generating selection data is proposed. The selection data can define the structure of design layout data applicable to electronic devices manufactured from the wafer. The method may include generating the selection data by defining which structures of the design layout data are applicable for each electronic device manufactured from the wafer, whereby the selection data: Different sets of structures are defined for different subsets of electronic devices.

[0052] In an embodiment, generating the selection data may further include defining respective locations of structures in a design layout of the electronic device defined by the design layout data.

[0053] In embodiments, the method may further include encrypting the selection data.

[0054] According to an aspect of the present invention, a data processing system is proposed comprising a processor configured to perform the method for generating selection data of one or more of the embodiments described above. be done.

[0055] According to an aspect of the present invention, there is proposed a computer program product implemented on a computer-readable non-transitory storage medium, the computer-readable non-transitory storage medium comprising: Instructions are provided to cause a computer to perform the method for generating selection data of one or more of the embodiments described above.

[0056] According to an aspect of the present invention, a computer comprising instructions that, when executed by a computer, cause the computer to perform a method for generating selection data of one or more of the embodiments described above. A readable non-transitory storage medium is proposed.

[0057] Various aspects and embodiments of the present invention are further defined in the following detailed description and claims.

[0058] Hereinafter, embodiments of the invention are described in additional detail. However, it should be understood that these embodiments should not be construed as limiting the scope of protection of this invention.

[0059] Embodiments will now be described, by way of example only, with reference to the accompanying schematic drawings, in which corresponding reference characters indicate corresponding parts.
[0060] FIG. 6 illustrates a simplified unique chip and a wafer with a plurality of unique chips of an exemplary embodiment of the invention; [0061] FIG. 1 is a schematic diagram of a system involved in the manufacture of an electronic device, according to an exemplary embodiment of the invention; [0062] FIG. 6 is a functional flow diagram of the creation of pattern bitmap data in an exemplary embodiment of the invention; [0063] FIG. 7 depicts fields defined by design layout data and via location metadata in accordance with an exemplary embodiment of the present invention; [0064] Fig. 6 depicts selection data according to an exemplary embodiment of the present invention; [0065] FIG. 7 is a functional flow diagram of creating pattern bitmap data using wipeout bitmaps, in accordance with an exemplary embodiment of the present invention; [0066] Fig. 6 depicts a process for creating vias in accordance with an exemplary embodiment of the present invention; [0067] FIG. 2 is a simplified schematic diagram of an exemplary embodiment of a charged particle multi-beamlet lithography system; [0068] Fig. 2 is a conceptual diagram illustrating an exemplary maskless lithography system; [0069] FIG. 6 shows a side view of two merged vias between metal layers in an exemplary embodiment of the invention; [0070] FIG. 6 depicts a top view of two merged vias between metal layers of an exemplary embodiment of the invention; [0071] Fig. 12 shows a side view of two vias between metal layers. [0072] Fig. 12 depicts a top view of two vias between metal layers;

[0073] The diagrams are intended for illustrative purposes only and do not serve as a limitation of the scope or protection formulated by the claims.

[0074] Although semiconductor chips are referenced in the following examples, it is understood that the present invention is not limited to chips, but more generally applies to the creation of electronic devices that are treated individually, for example, with unique characteristics. should. The electronic device may be a read only memory (ROM). For example, batches of chips with independently addressed ROM loads can be made using the present invention. Such batches are typically small batches, eg made from one or less than one wafer.

[0075] The process performed by charged particle multi-beamlet lithography is also called electron beam or e-beam exposure. The electron beam exposure method is a maskless exposure method. An electron beam used to write a target such as a wafer during electron beam exposure is also called a beamlet.

[0076] Unique chips are designed to be unique with respect to other chips. This may be done, for example, to make a spare unique chip for use if the original unique chip becomes damaged, to make batches of the same chip, or for any other reason. We do not rule out the possibility that it could be used to create multiple unique chips. A unique semiconductor chip that is functionally different from any other semiconductor chip may be referred to as a truly unique chip. Also, creating a visually readable unique ID on the chip may be considered creating a unique chip. Copies of the unique chip may be created by repeating chip fabrication on different wafers, or a single wafer may contain one or more copies of the unique chip.

[0077] FIG. 1 shows an exemplary simplified unique chip 100 that includes a common portion 101 and a region 102 that is treated individually. Common portion 101 may be replicated in other chips fabricated on wafer 24, resulting in multiple chips having the same identical portion. Individually treated regions 102 may differ from other chips fabricated on wafer 24 . This is shown at the top of FIG. 1 where a wafer 24 containing a unique chip 100 and 39 other unique chips with each unique chip having a different individually treated area is shown. A combined common portion 101 and individually treated regions 102 may result in a unique chip 100 .

[0078] The individually addressed regions 102 may be realized by selecting and writing specific structures such as the vias shown in the middle part of Figure 1 by the black dots. Other unique chips may have different structures, such as vias, resulting in different interconnections within or between layers of the electrical circuit.

[0079] Instead of or in addition to specific vias, other connections between metal layers, connections between metal layers and gates in, for example, contact layers, connections in local interconnect layers, and/or the presence or absence of structures of diffusion regions (eg, P-doped regions or N-doped regions) of transistors or diodes may be selected and written to achieve individually addressed regions 102 .

[0080] The common portion 101 may be made using photolithography, but is preferably made using charged particle multi-beam lithography. The discretely addressed regions are typically created using charged particle multi-beam lithography.

[0081] Figure 2 illustrates a semiconductor fabrication plant 1000 that includes systems and processes involved in manufacturing unique semiconductor chips in accordance with an exemplary embodiment of the present invention. Where reference numbers used in FIG. 2 refer to processes or operations, these reference numbers may also refer to computational units that perform the processes or operations. Each of the processes and operations shown may be performed by a dedicated unit. Alternatively, one computing unit may perform multiple processes or operations shown in FIG. A computing unit is a computer system that includes one or more processors and memory, for example, for performing dedicated tasks or for executing programs under an operating system.

Semiconductor fab 1000 may include production setup portion 1002 and manufacturing portion 1003 . It is conceivable that no division is made into the two parts 1002 and 1003, or that another division is made. Manufacturing portion 1003 may include one or more lithography subsystems 1070 each using a maskless pattern writer 1073 . In this example, the maskless lithography exposure system is a charged particle multi-beamlet lithography system and the maskless pattern writer 1073 is a charged particle multi-beamlet lithography machine or an e-beam machine.

[0083] On the left hand side of FIG. Design layout data is typically generated in the GDSII data format or the OASIS data format. Standard IC design flows are known in the art and typically include a system/complete IC design stage 1010, a circuit design VHL/Verilog stage 1011, a logic verification stage 1012, a placement and routing (P&R) stage 1013, a physical simulation stage 1014, and/or including a design rule check (DRC) step 1015 .

[0084] The process design kit 1030, which includes add-ons and IP libraries, stores functional IP blocks as indicated by the arrows from the functional IP block storage 1031 to steps 1011, 1012, 1013, 1014, and 1015 of the standard IC design flow 1001. From storage 1031 the various steps of standard IC design flow 1001 may be provided with building blocks in the form of reusable units of logic, cell or chip layout design. The process design kit 1030 is typically located in the production setup portion 1002 of the fab 1000 as it may relate to functional IP blocks licensed to chip manufacturers by the IP block designer 1005 .

[0085] The design layout data that is produced typically includes a common design layout portion that defines layout structures, possibly including via structures, that are applicable to all of the chips that are produced. In addition, the design layout data defines structures such as via structures applicable to a particular electronic device from which different sets of structures can be selected to make the chip unique. May include a design layout portion. Looking at the design layout data, the distinction between common and non-common design layout parts is preferably not apparent. Location metadata may be generated along with the design layout data to enable selection of a set of structures from non-common design layout portions.

[0086] In the following examples, the selectable structure is a via structure and the location metadata is referred to as via location metadata.

[0087] Via location metadata may provide a location in the design layout for each selectable via. Via location metadata may be stored within the design layout data, but is preferably provided as a separate data file.

[0088] The output 2000 of the design flow 1001 may be provided to a charged particle multi-beamlet lithography system via a tapeout and finalization process 1016. More specifically, the output 2000 may include optical proximity correction (OPC) operations 1021, data creation (PEC, fragmentation) operations 1022, recipe/process program (PP) generation operations 1023, and/or order and production planning operations 1024. It may be entered into the preparation portion 1020 of the production setup 1002 that may be executed. The output of each of these operations passes verification step 1040 and may be forwarded to manufacturing portion 1003 .

[0089] When photolithographic exposure is performed on the wafer prior to maskless lithographic exposure, optical proximity correction (OPC) 1021 is applied to the GDSII design layout data to produce corrected GDSII data 2010. Often, corrected GDSII data 2011 may be input to mask shop 1081 along with mask order data. This may result in mask set 2011 , which may be input to reticle stocker 1082 , where reticles (masks) 2012 may be input to CMOS wafer flow 1080 . Wafer order data may be used to enter wafers 1083 into CMOS wafer flow 1080 when needed. The photolithographic exposure itself is not shown in FIG. The resulting exposed wafer is shown as wafer 2013 . Note that wafer 2013 may be an unexposed wafer if photolithographic exposure is not performed.

[0090] Data preparation unit 1022 may preprocess GDSII design layout data, shown as 2007, into preprocessed design layout data 2008. FIG. Preprocessed design layout data 2008 may include data specific to lithography subsystem 1070 . This off-line pre-processing of GDSII data 2007 may include steps such as bending, proximity correction, resist heating correction, and/or writing smart boundaries. Pattern vector data 2008 may be stored in reticle storage 1051 of manufacturing execution system (MES) 1050 .

[0091] Recipe/PP generation 1023 may generate instructions for the creation of process jobs (PJs). PPs and associated programs may be stored in Recipe/PP Database 1052 of MES 1050 . PP 2005 may be sent from MES 1050 to machine control 1072 of lithography subsystem 1070 to instruct machine control 1072 to create a PJ based on the PP. Additional commands may include abort and cancel commands.

[0092] For example, via orders and production plans 1024, manufacturing database 1053 of MES 1050 may be provided with manufacturing specific information. From here, the PJ input generator 1054 may be fed information. PJ input generator 1054 may provide PJ inputs to machine control 1072 and PJ 2006 may be generated to control portions of lithography subsystem 1070 , particularly rasterizer 1071 and pattern streamer (maskless pattern writer) 1073 .

[0093] The operation of the lithography subsystem 1070 may be controlled using a PP, which may include a sequence of operations to be performed. Machine Control 1072 may be loaded with PPs and may schedule and execute PPs as may be required by Recipe/Generate PPs 1023 . A PP may take the role of a recipe, for example as specified in the SEMI E40 standard. SEMI standards specify many requirements on how to address recipes, but standards sometimes conflict such that recipes are preferably avoided. Alternatively, editable and unformatted PPs may be used in the form of so-called Binary Large Objects (BLOBs).

[0094] A PP may determine the processing environment of a wafer and may be subject to change during a run or processing cycle by pre-planning and reusing sets of instructions, settings, and/or parameters. It may be a possible part. A PP may be designed by a lithography tool designer or produced by tooling.

[0095] The PP may be uploaded to the lithography system by the user. A PP may be used to create a PJ. A PJ may specify a process to be applied to a wafer or set of wafers by the lithography subsystem 1070 . A PJ may define which PP to use when processing a specified set of wafers, and may include parameters from the PP (and optionally from the user). A PJ may be a system activity initiated by the user or the host system.

[0096] The PP may be used not only to control the processing of wafers, but also for service actions, calibration functions, lithography component tests, component set point corrections, software updates and/or upgrades. Preferably, auto-initialization during module or subsystem power-up, periodic and unconditional operation of subsystems, and against unexpected power-off, emergency or EMO activation, as long as they do not affect PJ execution With the exception of certain permitted additional categories, such as responses, no subsystem actions other than those specified in the PP occur.

[0097] A PP may be divided into steps. Most steps usually contain a command and identify the subsystem that executes the command. Steps may also include parameters and parameter constraints used in executing commands. A PP may also include scheduling parameters to indicate when steps are executed, eg, in parallel, in sequence, or synchronously.

[0098] To execute a command step of PJ, machine control 1072 may send the command indicated in PJ to the subsystem indicated in the relevant step of PJ. Machine control 1072 may monitor timing and receive results from subsystems.

[0099] Pre-processed design layout data 2008 is typically stored in reticle storage 1051 in a tool input data format that is in vector format and includes dose information. Preprocessed design layout data 2008 may be provided from reticle storage 1051 to rasterizer 1071 of lithography subsystem 1070 where preprocessed design layout data 2008 exposes a wafer for chip fabrication. It may be processed into beamlet control data such as pattern bitmap data 2009 for controlling the maskless pattern writer 1073 to do so. The preprocessed design layout data 2008 may include all possible structures, in this example via structures, from which selections are made for the creation of unique chips. The selection may be made based on input from the protected fab black box device 1060, which of the via structures in the design layout data is applicable to each chip fabricated from the wafer. Selection data may be generated that define whether there are different sets of via structures for different subsets of chips.

[00100] Selection data, shown as 2004 in FIG. Preferably, selection data 2004 is encrypted. PJ input generator 1054 may send selection data 2004 to machine control 1072 where PJ 2006 is generated instructing rasterizer 1071 to generate pattern bitmap data 2009 based on selection data 2004. good.

[00101] Alternatively, black box device 1060 is configured to provide selection data 2004 directly to lithography subsystem 1070 for provisioning selection data 2004 to rasterizer 1071 without involving PJ input generator 1054. may be

[00102] When the preprocessed design layout data 2008 does not contain via location metadata, and thus selectable via locations cannot be derived from the preprocessed design layout data 2008, the rasterizer typically uses However, it may also receive via location metadata 2003, perhaps as a separate file.

[00103] Via location metadata 2003 may be received along with the GDSII design layout data in preparation portion 1020. FIG. From there, via location metadata 2003 may be provided to black box device 1060 via recipe/PP generator 1023 or via order and production plan 1024, for example. The latter situation is illustrated in FIG. 2 where via location metadata 2003 is routed through manufacturing database 2003 from orders and production plans 1024 to black box device 1060 .

[00104] Black box 1060 provides via location metadata 2003 to lithography subsystem 1070 that follows the same route as the selection data described above, eg, via PJ input generator 1054 or directly to lithography subsystem 1070. good.

[00105] Black box device 1060 is configured to provide to lithography subsystem 1070 only a subset of via location metadata 2003, for example, only a subset of via location metadata 2003 that includes only location information for vias that are enabled according to provided selection data 2004. good.

[00106] Black box device 1060 may include an ID/key manager 1061 and a selection data generator 1062 that cooperate in creating selection data 2004. FIG. ID/key manager 1061 may receive product ID/serial number information 2001 from manufacturing database 1053 and batches of ID/key pairs 2002 from a key management service 1006, possibly located external to the maskless lithography exposure system. Product ID/serial number information 2001 and batches of ID/key pairs 2002 may be used to control the generation of selection data 2004 . Additionally, the product ID/serial number information 2001 may be used to track the chip through the manufacturing process so that it can be matched to its ID/serial number after it is manufactured. Alternatively or additionally, product ID/serial number information 2001 may be used to include an ID/serial number in or on the chip by processes known per se, not shown.

[00107] Exposing the wafer 2013 according to the pattern bitmap data 2009 will expose a pattern having different subsets of via structures for different subsets of chips. In FIG. 2 this is shown as exposed wafer 2014 . Exposed wafer 2014 may be further processed according to standard CMOS wafer flow 1080, typically including inspection, etching, deposition CMP, and/or slicing steps. The resulting sliced chip 1007 may be a unique chip that may be used in end-user device 1008 for data security, traceability, and/or anti-counterfeiting applications, for example. Arrow 2015 indicates the provisioning of a unique chip to End User Device 1008 .

[00108] Process Programs (PP) and Process Jobs (PJ) are defined in, for example, SEMI E30 "Generic Model for Manufacturing Equipment Communication and Control (GEM)", SEMI E40 "Process Management Standard", SEMI E42 "Recipe Management Standards: Concepts, Behaviors, and Message Services” and/or SEMI standards such as SEMI E139 “Rule of Control for Recipes and Parameters (RaP)”.

[00109] FIG. 3 shows an exemplary functional flow diagram of a data path using number line rasterization that may be followed in generating pattern bitmap data 2009 from GDSII design layout data 2007. FIG. The functional flow diagram of FIG. 3 may be used with the maskless lithography exposure system of FIG. In FIG. 3, the functional flow diagram is divided into four sections. That is, 3010 is used to indicate the data format of the lower data output/input, 3020 indicates the process flow including data output/input (parallelogram) and functional element (rectangle), and 3030 is the upper functional element. 3040 is used to indicate how often the process step is typically performed, for example, once per design 3041, once per wafer 3042, or once per field 3043. Used to indicate what should be done. Roman letters I, II, and III indicate when via location metadata and/or selection data can be provided to the data path.

[00110] The input to the process may be GDSII design layout data 2007, or a design layout in any other suitable format, such as the OASIS data format. GDSII design layout data 2007 may include structures, such as via structures, from which a set of via structures are selected to make the chip unique.

[00111] The data preparation unit 1022 may preprocess the GDSII file 2007 as a normally offline preprocessing operation. Pre-processing operations typically include one or more of bending, proximity correction, resist heating correction, and/or smart border drawing operations, both shown as 3031 . The output of data creation 1022 may be preprocessed design layout data 2008, typically in vector format, including dose information, shown as 3011. FIG. The format of preprocessed design layout data 2008 is also known as the tool input data format. Data creation 1022 is typically performed once per design as indicated by arrow 3041, but may be performed once per wafer or once per field.

[00112] The pre-processing of data preparation unit 1022 preferably does not expose a specific or unique chip design. That is, selection data 2004 is preferably not available at this stage of the data path, advantageously allowing data preparation unit 1022 and production setup portion 1002 of the manufacturing plant to be located in less secure environments.

[00113] As mentioned above, it is desirable to minimize the exposure and exposure time of specific or unique chip design portions for security reasons. The security aspect is important because chip uniqueness is typically used for data security, traceability, and/or anti-counterfeiting applications. The processes within the dashed block, ie from software processing 1071A to hardware processing in pattern writer 1073, are typically performed within lithography subsystem 1070, allowing for a more secure operating environment. Additionally, by providing selection data 2004 only to software processes 1071A and beyond, the amount of time that the unique characteristics of the chip are used within the manufacturing portion 1003 of the fab can be minimized.

[00114] Selection data 2004 is typically provided and used once per field. Roman letter III indicates the provisioning of selection data 2004 to the data path at this stage. Alternatively, but less preferably, selection data 2004 may be provided and used once per wafer. Roman II indicates the provisioning of select data 2004 to the data path at this stage.

[00115] Location metadata 2003 may be provided to lithography subsystem 1070 along with selection data 2004, as described in FIG. Alternatively, if the selection data is embedded with the GDSII design layout data, location metadata may be provided once per design, as indicated by the Roman letter I.

[00116] Preprocessed GDSII design layout data 2008 may be input to rasterizer 1071, which may include software processing portion 1071A and streaming portion 1071B as shown in FIG. Depending on whether the selection data 2004 is used once per wafer, as indicated by Roman II, or once per field, as indicated by Roman III, software processing portion 1071A or streaming portion 1071B selects data along with via location metadata 2003 to enable a specific set of via structures as defined by select data 2004 in the preprocessed design layout data, thereby preparing for the creation of unique chips. 2004 may be used.

[00117] Inline processing of preprocessed design layout data 2008 may be performed in software processing portion 1071A to rasterize the vector data to generate pattern system stream delivery (PSS) data 3021. PSS data 3021 may be formatted as 4-bit grayscale bitmap data indicated at 3012 .

[00118] Rasterization may be performed in . A unique chip design portion may be implemented at this stage, as indicated by Roman II. Streaming portion 1071 B may then process PSS data 3021 to generate pattern bitmap data 2009 . The process performed by streaming portion 1071B involves full or partial pixel shifts in the X and/or Y directions for beam position calibration, field size adjustment, and/or field alignment for bitmap data. May contain corrections. Together these processes are indicated as 3032 . Alternatively, for entry point II, the unique design portion may be implemented at this stage as indicated by Roman letter III. Pattern bitmap data 2009 may be streamed to pattern writer 1073 for wafer exposure. This stream of pattern bitmap data 2009 is shown as 3022 .

[00119] Rasterization may be performed in the streaming stage 1071B, which may involve real-time processing performed in hardware. Corrections for beam position calibration, field size adjustment, and/or field position adjustment (both labeled 3032) may be applied to vector format PSS format data 3021, which is then rasterized into pattern bitmap data. can be converted to When corrections are performed on vector data, full pixel shifts, partial pixel shifts, and/or sub-pixel shifts in the X and Y directions may be performed.

[00120] Controlling the maskless pattern writer 1073 typically involves the blankers being controlled by the pattern bitmap data. The pattern bitmap data 2009 may be called blanker format data.

[00121] Figures 4 and 5 relate to an exemplary situation in which beamlet control data, such as pattern bitmap data, is generated once per field. FIG. 4 shows an exemplary embodiment of fields 103 defined by design layout data and location metadata 2003, such as via location metadata. Together with FIG. 4 , FIG. 5 represents selection data 2004 . In this example, the design layout data defines four unique chips in the field, each chip having a common portion 101 that may be the same for all four chips, and a selectable chip defined in the design layout data. After selecting a different set of structures, such as vias, from the same structure, each chip has regions 102 that will be treated individually, which may be different.

[00122] Roman letters I, II, and III indicate when respective data may be provided to the data path of FIG. 3 in this example.

[00123] Via location metadata 2003 may include a list of selectable vias in the design layout and the coordinates of each selectable via. In this example, the vias are numbered Via1 through ViaN, where N is any positive exponent. Any other identification of the via may be used instead, or the via identification uses the location of the X, Y coordinates in the file (e.g., counting row numbers) as the via identification and is excluded entirely. It is understood that In this example, the coordinates of each via are expressed as an X,Y location. It is understood that any other coordinate system or representation of locations in the design layout may be used instead. Similar to the example of FIG. 4, instead of via structures, any other type of structure may be identified in the location metadata.

[00124] In addition to the location of the structure, the location metadata may include additional information about the structure, such as the width and/or height of the structure. Location metadata may be optimized, for example, by including metadata common to multiple structures only once.

[00125] The selection data 2004 includes fields and Via1. . For each ViaN it may contain an n-bit list indicating whether the via is enabled (bit value '1') or disabled (bit value '0'). Here, the bit location matches the via location metadata 2003 via index. Instead of a single bit, multiple bits may be used to indicate selected vias and/or non-selected vias in the selection data. In this example, the fields are numbered Field1 through FieldM, where M is any positive exponent. Any other identification of the field may be used instead, or the field identification uses the position of each set of field bits in the file (e.g., counting line numbers) as the field It is understood that they may be excluded.

[00126] The rasterizer 1071 may receive the selection data 2004 or a subset of the selection data associated with the fields to be exposed on the wafer. Selection data 2004 may be used to enable and disable corresponding vias at locations in the design layout as defined by via location metadata 2003 .

[00127] Figure 6 depicts the flow of data in the portion of the data path involved in creating pattern bitmap data 2009, according to an illustrative embodiment of the invention. Data are shown as parallelograms and process steps are shown as rectangular boxes.

[00128] At the beginning of the left data stream, preprocessed design layout data 2008 is processed by rasterizer 1071, for example as shown in FIG. It may have been processed into an intermediate 4-bit per pixel gray level bitmap 3021B or any other suitable bitmap format. This intermediate 4 bpp gray level bitmap 3021B may include all structures, such as vias, among which selections are made to create unique chips. Optionally, the intermediate 4bpp gray level bitmap is in compressed format 3021A and is decompressed in decompression step 3035. ZIP compression or any other suitable compression format may be used as the compression format.

[00129] At the top right, location metadata 2003, eg, via location metadata, and selection data 2004 may be input into wipeout bitmap creation process 3033 for creation of wipeout bitmap 3023A. The wipeout bitmap will typically be of a form that allows the wipeout bitmap to act as a mask to erase vias in the intermediate 4bpp gray level bitmap. Wipeout bitmap 3023A may be stored immediately in compressed format and possibly decompressed in real-time prior to use in fusion operation 3034 .

[00130] In a fusion operation 3034, the intermediate 4bpp gray-level bitmap and the wipeout bitmap may be merged using, for example, an OR operation, resulting in the selected data defined and removed from the intermediate 4bpp gray-level bitmap. causes unselected vias to be reflected in the wipeout bitmap. In this regard, for example, the bits defining vias in the intermediate 4 bpp gray level bitmap are given a binary zero value for non-selected vias.

[00131] The resulting 4bpp grayscale bitmap 3021C may be processed for pattern streamer correction, and a B/W dithering operation may be performed, as shown in process step 3032A. Processing step 3032A may be similar to operation 3032 of FIG. This may result in pattern bitmap data 2009 for controlling a maskless pattern writer, such as maskless pattern writer 1073 of FIG.

Processes 3033 , 3034 , 3035 and 3032 A may be performed by rasterizer 1071 or any other processing unit, preferably part of lithography subsystem 1070 . Processes 3032A, 3034, and/or 3035 may be performed in real time. Typically, one or more of the process steps shown in FIG. 6 are performed in RAM memory, and wipeout bitmap 3032A, intermediate 4bpp gray level bitmap 3021B, and/or 4bpp grayscale bitmap 3021C, or portions thereof, are Stored in RAM memory only during processing of data into pattern bitmap data 2009 . For increased processing performance, the fusion operation 3034 and possibly also the decompression operation 3035 are preferably implemented in hardware, eg in an FPGA or ASIC.

[00133] In an exemplary embodiment, the intermediate 4bpp grayscale bitmap 3021B may define stripes of the wafer's field covering, for example, a 2 μm by 33 mm area of the wafer. Each 4-bit pixel of intermediate 4-bpp grayscale bitmap 3021B may cover an area of 5.4 nm by 5.4 nm. Wipeout bitmap 3023A may be, for example, a 1 bpp bitmap covering one stripe or scan line on the wafer covering an area of 2 μm by 300 mm. Each 1-bit pixel of wipeout bitmap 3023A may cover an area of 43.2 nm by 43.2 nm in this example. Thus, the wipeout bitmap may have an even lower resolution than the intermediate 4bpp grayscale bitmap, resulting in the fusion operation 3034 erasing a larger area than that of the intermediate 4bpp grayscale bitmap.

[00134] In another exemplary embodiment, an intermediate multi-level grayscale bitmap, such as 4bpp grayscale bitmap 3021B, defines stripes of the field of the wafer covering, for example, a 2 μm by 33 mm area of the wafer. good. Each 4-bit pixel of intermediate 4-bpp grayscale bitmap 3021B may cover an area of 5.4 nm by 5.4 nm. Wipeout bitmap 3023A may be, for example, a 4 bpp sparse bitmap covering one stripe on a wafer covering an area of 2 μm by 300 mm. Each 4-bit pixel of wipeout bitmap 3023A may cover an area of 5.4 nm by 5.4 nm in this example. Thus, the wipeout bitmap may have the same resolution as the intermediate 4bpp grayscale bitmap, causing the fusion operation 3034 to erase pixels at the exact locations defined by the wipeout bitmap 3023A.

[00135] Optionally, the wipeout bitmap data 3023A, particularly when in a sparse bitmap format, may be stored in RAM in a compressed format and decompressed on-the-fly when the fusion operation 3034 is executed.

[00136] In the example of Figure 6, the wipeout bitmap 3023A showing the vias to be removed is merged with the intermediate bitmap 3021B to yield a bitmap 3021C from which the vias are removed. Instead of operating on data in bitmap format, similar wipeout operations may be performed on data files in vector format. Instead of the intermediate 4bpp gray-level bitmap 3021B, a vector-based wipeout data file containing all selectable structures, such as vias, which define structures that are then deleted or disabled. may be merged with In this alternative, the result of the merge operation is typically a vector-based data format that may be converted into pattern bitmap data 2009 for controlling maskless pattern writers in one or more steps.

[00137] The wipeout bitmap and wipeout vector data may together be referred to as wipeout mask data.

[00138] Figure 7 illustrates a process for creating a unique chip according to an exemplary embodiment of the invention. A cross-sectional side view of the wafer is shown at the six stages (A)-(F) of creating a unique chip. At each stage a wafer is shown comprising several layers 201-206. Between stages (A)-(F), the same pattern indicates the same layer. In this example, the common portion 101 of the chip and the individually addressed regions 102 of the chip are fabricated using charged particle multi-beamlet lithography.

[00139] At the beginning of process (A), the wafer has five layers: a bottom metal layer 201, an insulating layer 202 (eg SiO2), lower layers 203 and 204 (eg SOC + SiARC HM), and a top e-beam resist layer 206 ( for example KrF resist).

[00140] The top layer 206 may be exposed using an e-beam exposure under the control of the pattern bitmap data 2009 indicated by the arrows at the top so that structures later defined by the e-beam are removed from the resist layer 206. Followed by a development step that is removed. The result of the development step is shown as stage (B). In an etch and strip step, these structures may be etched into the SOC underlayer 204 and the SiARC underlayer 203, and the resist may be removed. The results are shown as stage (C). Structures may then be etched into the insulating layer 202 and the underlying layers 203, 204 may be stripped, the result being shown as step (D).

[00141] Next, a conductive layer 207 may be applied over the etched and stripped insulating layer for both identical and unique portions of the chip, the result of which is shown as step (E). For example, chemical vapor deposition with tungsten (CVD-W) may be used. Chemical-mechanical planarization (CMP) removes excess conductive material, resulting in a step (F) in which the wafer may have a bottom metal layer 201 and layers thereon including insulating and conductive materials. Vias may be made of this conductive material.

[00142] In the example of Figure 7, the vias may be made in a single layer, the second layer from the bottom. The process may be modified to create conductive material in different layers for the creation of vias in different layers, and/or multiple layers with conductive material may be created for vias in multiple layers. good. The process may be modified to make a connection between the metal layer and, for example, the gate of the contact layer to make a connection to the local interconnect layer. Alternatively or additionally, the process may alter the formation or structure of diffusion regions (eg, P-doped regions or N-doped regions), or enable or disable P-implants or N-implants in certain portions of transistors or diodes. you can

[00143] The embodiment of Figure 7 is described above using the example of individually addressed portions of a chip with unique configurations of conductive vias formed using maskless lithography. The unique chip structure uses a maskless lithography process to effectively form a larger single via, as illustrated in the examples shown in FIGS. 10A (side view) and 10B (top view). A further improvement may be achieved by merging adjacent conductive vias created by . In a conventional method using mask-based photolithography, to form an electrical connection between two metal layers 211c, 211d, as illustrated in FIGS. 11A (side view) and FIG. 11B (top view). Multiple round vias 217d, 217e may be used. Merging these vias into a single larger elliptical via is difficult to achieve in practice due to the limitations of the optical systems used in conventional photolithography. Using a maskless charged particle lithography system, these constraints do not exist and the metal layers 211a, 211b can be connected, for example, by exposing two vias 217a, 217b in close proximity so that they merge, resulting in more A large oval single via 217c can be created. This allows a more reliable connection to be made between the two metal layers, which may conduct more current, resulting in further improvements in unique chips.

[00144] FIG. 8 depicts a simplified schematic diagram of an exemplary embodiment of a charged particle multi-beamlet lithography machine 1 that may be used to implement a maskless pattern writer 1073. As shown in FIG. Such a lithography machine suitably includes a beamlet generator to generate a plurality of beamlets, a beamlet modulator to pattern the beamlets into modulated beamlets, and a beamlet modulator to project the beamlets onto the surface of the target. Includes beamlet projector. A target is, for example, a wafer. A beamlet generator typically includes a source and at least one aperture array. A beamlet modulator is typically a beamlet blanker with a blanking deflector array and a beam stop array. A beamlet projector usually includes a scanning deflector and a projection lens system.

[00145] The lithography machine 1 may include an electron source 3 for producing a homogeneous, expanding electron beam 4. The beam energy is preferably kept relatively low in the range of about 1-10 keV. To accomplish this, the accelerating voltage is preferably low and the electron source is preferably maintained between about -1 and -10 kV relative to the target at ground potential, although other settings may be used.

[00146] An electron beam 4 from an electron source 3 may pass through a double octapole and then a collimator lens 5 to collimate the electron beam 4. FIG. As will be appreciated, the collimating lens 5 can be any type of collimating optical system. The electron beam 4 may then hit a beam splitter, which in one suitable embodiment is an aperture array 6A. Aperture array 6A may block portions of the beam and may allow multiple sub-beams 20 to pass through aperture array 6A. The aperture array preferably includes a plate with through holes. Thus, multiple parallel electron sub-beams 20 may be created.

[00147] The second aperture array 6B may create a number of beamlets 7 from each sub-beam. Beamlets are also called e-beams. The system produces a large number of beamlets 7, preferably between about 10,000 and 1,000,000 beamlets, although it is of course possible to use more or fewer beamlets. you can Note that other known methods may also be used to generate collimated beamlets. This allows sub-beam steering, which proves beneficial to system operation, especially when increasing the number of beamlets to 5,000 or more. For example, such manipulation may be performed by a condenser lens, collimator, or lens structure that concentrates the sub-beams on the optical axis, for example, at the plane of the projection lens.

A condenser lens array 21 (or set of condenser lens arrays) is included behind the sub-beams creating aperture array 6 A to focus the sub-beams 20 towards corresponding apertures in the beam stop array 10 . can be A second aperture array 6B may generate beamlets 7 from the sub-beams 20 . A beamlet-forming aperture array 6B is preferably included in combination with a beamlet blanker array 9 . For example, both may be assembled together to form a subassembly. In FIG. 8, the aperture array 6B produces three beamlets 7 from each sub-beam 20, the beamlets 7 correspondingly arranged such that the three beamlets are projected onto the target by the projection lens system of the end module 22. The beam stop array 10 is hit at the opening where the beam stops. In practice, a much larger number of beamlets may be produced by the aperture array 6B per end module 22 projection lens system. Although the number of beamlets per sub-beam can increase to 200 or more, in one embodiment 49 beamlets (arranged in a 7x7 array) may be generated from each sub-beam, with a single projection lens system directed through.

[00149] The step-by-step generation of beamlets 7 from beam 4 through intermediate stages of sub-beams 20 requires that the main optical operations be performed with a relatively limited number of sub-beams 20 and relatively far from the target. It has the advantage that it may be performed in position. One such operation is the focusing of the sub-beams to points corresponding to one of the projection lens systems. Preferably, the distance between the operation and the focal point is greater than the distance between the focal point and the target. Most suitably an electrostatic projection lens is used in combination with this. This focusing operation allows the system to meet the requirements of reduced spot size, increased current, and reduced point spread for robust charged particle beam lithography at advanced nodes, especially those with critical dimensions less than 90 nm. make it possible.

[00150] The beamlets 7 may then pass through an array of modulators 9; This array of modulators 9 may comprise a beamlet blanker array having a plurality of blankers each capable of deflecting one or more of the electron beamlets 7 . The blanker may more particularly be an electrostatic deflector comprising a first electrode and a second electrode, the second electrode being a ground electrode or a common electrode. The beamlet blanker array 9 constitutes a modulator together with the beam stop array 10 . Based on the beamlet control data, the modulating means 8 may apply patterns to the electron beamlets 7 . The pattern may be projected onto target 24 using components present in end module 22 .

[00151] In this embodiment, the beam stop array 10 comprises an array of apertures to allow beamlets to pass through. A beam stop array, in its basic form, may comprise a substrate with through holes, typically round holes, although other shapes may also be used. In one embodiment, the beam stop array substrate 8 may be formed from a silicon wafer having a regularly spaced array of through-holes and may be coated with a surface layer of metal to prevent surface charging. In one embodiment, the metal may be of a type that does not form a native oxide film, such as CrMo.

[00152] In one embodiment, the beam stop array 10 passages may be aligned with the beamlet blanker array 9 holes. The beamlet blanker array 9 and the beamlet stop array 10 normally work together to block or pass the beamlets 7 . When beamlet blanker array 9 deflects a beamlet, the beamlet does not pass through the corresponding aperture of beamlet stop array 10 , but is instead blocked by the substrate of beamlet block array 10 . However, if beamlet blanker array 9 does not deflect the beamlet, then the beamlet passes through the corresponding aperture of beamlet stop array 10 and is then projected as a spot on target surface 13 of target 24 .

[00153] Lithography machine 1 may further include a data path for supplying beamlet control data, for example in the form of pattern bitmap data 2009, to beamlet blanker array 9. FIG. Beamlet control data may be transmitted using optical fibers. The modulated light beams from each optical fiber end may be projected onto the light receiving elements of the beamlet blanker array 9 . Each light beam may carry a portion of the pattern data for controlling one or more modulators coupled to the photodetectors.

[00154] The electron beamlet 7 may then enter the end module. Hereinafter, the term "beamlet" refers to a modulated beamlet. Such modulated beamlets actually comprise a series of parts in time. Some of these series of sections may have lower intensity, preferably zero intensity - ie, the section stopped at the beam stop. Some portions may have zero intensity to allow positioning of the beamlets to the starting position during subsequent scans.

[00155] The end module 22 is preferably constructed as an insertable and replaceable unit that includes various components. In this embodiment, the end module may include a beam stop array 10, a scanning deflector array 11, and a projection lens arrangement 12, although not all of these need be included in the end module, they are arranged differently. may

[00156] After the modulated beamlets 7 pass through the beamlet stop array 10, each beamlet 7 in the X-direction and/or the Y-direction substantially perpendicular to the direction of the undeflected beamlet 7. It may pass through a scanning deflector array 11 that provides deflection. In this embodiment, the deflector array 11 may be a scanning electrostatic deflector that allows the application of relatively small drive voltages.

[00157] The beamlets may then pass through projection lens arrangement 12 and may be projected onto a target, typically a target surface 24 of a wafer, at the target plane. For lithographic applications, the target usually comprises a wafer with a charged particle sensitive layer or resist layer. Projection lens arrangement 12 may focus the beamlets to produce a geometric spot size of, for example, approximately 10-30 nanometers in diameter. A projection lens arrangement 12 of such design provides a reduction of about 100-500 times, for example. In this preferred embodiment, the projection lens arrangement 12 is advantageously located near the target surface.

[00158] In some embodiments, a beam protector may be located between the target surface 24 and the focusing projection lens arrangement 12. The beam protector may be a foil or plate with the required apertures to absorb resist particles emitted from the wafer before they can reach any of the photosensitive elements of the lithography machine. Alternatively or additionally, scanning deflection array 9 may be provided between projection lens arrangement 12 and target surface 24 .

[00159] In general terms, the projection lens arrangement 12 focuses the beamlets 7 onto the target surface 24. As shown in FIG. Therewith, the projection lens configuration 12 further ensures that the single pixel spot size is correct. Scan deflector 11 may deflect beamlets 7 on target surface 24 . Along with that, the scan deflector 11 must ensure that the position of the pixels on the target surface 24 is correct on the microscale. In particular, the operation of scan deflector 11 must ensure that the pixels ultimately fit well within the grid of pixels that make up the pattern on target surface 24 . It will be appreciated that macro-scale positioning of pixels on the target surface is suitably enabled by a wafer positioning system that resides below target 24 .

[00160] Such high quality projections can be relevant for obtaining a lithographic machine that provides reproducible results. Generally, target surface 24 comprises a resist film on top of the substrate. Portions of the resist film may be chemically modified by application of beamlets of charged particles, ie electrons. As a result, the irradiated portion of the film is more or less soluble in the developer and may give rise to a resist pattern on the wafer. The resist pattern on the wafer may then be transferred to the underlying layers, ie by mounting, etching and/or deposition steps known in the art of semiconductor fabrication. Obviously, if the irradiation is not uniform, the resist will not develop uniformly, which can lead to pattern errors. Moreover, many such lithography machines use multiple beamlets. No difference in illumination should result from the deflection step.

[00161] FIG. 9 shows a conceptual diagram of an exemplary charged particle lithography system 1A divided into three high-level subsystems: wafer positioning system 25, electro-optic column 20, and data path 30. FIG. A wafer positioning system 25 moves wafer 24 under electro-optic column 20 in the x-direction. Wafer position system 25 may include synchronization signals from datapath subsystem 30 to align the wafer with the electron beamlets produced by electron optical column 20 . Electron optical column 20 may include a charged particle multi-beamlet lithography machine 1 shown in FIG. The switching of beamlet blanker array 9 may also be controlled via datapath subsystem 30 using pattern bitmap data 2009 . Datapath subsystem 30 may be implemented according to FIG.

[00162] As shown in the example above, a maskless pattern writer may apply a raster scan to the wafer under control of the pattern bitmap data. Alternatively, a maskless pattern writer may apply a vector scan to the wafer. A vector scan typically differs from a raster scan in that it does not sequentially pass through every location of the wafer, instead it finishes exposing one local area and flies to the next. With vector scanning, a beam stabilization time is usually required before subsequent exposures can resume. This stabilization time is not normally required for raster scanning. Pattern bitmap data and control data for vector scanning may generally be referred to as beamlet control data.

[00163] One or more embodiments of the invention may be implemented as a computer program product for use with a computer system. Program product program(s) may define the functionality of embodiments (including the methods described herein) and may be contained on various computer-readable storage media. A computer-readable storage medium may be a non-transitory storage medium. Exemplary computer-readable storage media include (i) non-writable storage media on which information may be permanently stored (e.g., readable by a CD-ROM drive, ROM chip, or any type of solid-state non-volatile semiconductor memory; (ii) writable storage media in which changeable information may be stored (e.g., hard disk drives or any type of solid state random access semiconductor memory; flash memory), but not limited to them.

Claims (15)

A method of manufacturing an electronic device using a maskless lithographic exposure system using a maskless pattern writer, comprising:
generating beamlet control data for controlling the maskless pattern writer to expose a wafer for fabrication of the electronic device, the beamlet control data being fabricated from the wafer; design layout data defining a plurality of structures for an electronic device and defining which of said structures in said design layout data are applicable to each electronic device manufactured from said wafer and said electronic device and location metadata specifying locations of the structures defined in the design layout data ;
generating wipeout mask data based on the location metadata and the selection data ;
non-selected structures wherein said generating said beamlet control data merges said design layout data or a derivative of said design layout data with said wipeout mask data, thereby determining based on said selection data; from the design layout data;
A method, wherein exposing the wafer according to the beamlet control data results in exposing patterns having different sets of the structures for different subsets of the electronic devices. The design layout data is
common design layout data defining structures applicable to all of said electronic devices;
non-common design layout data defining structures applicable to a particular one of the electronic devices from which the different set of structures are selectable according to the selection data;
2. The method of claim 1, comprising: 3. The method of claim 1 or 2, wherein the wipeout mask data is in bitmap format. 4. The method of claim 3, wherein the design layout data or the derivative of the design layout data merged with the wipeout mask data is a multi-level grayscale bitmap. 5. The method of claim 4, wherein said multilevel grayscale bitmap is a 4bpp graylevel bitmap. 6. The method of claim 4 or 5, wherein the merging of the design layout data or the derivative of the design layout data and the wipeout mask data results in elimination of vias in the multi-level grayscale bitmap. Method. The wipeout mask data has a lower resolution than the multi-level grayscale bitmap, so that the merging erases an area at the location of the multi-level grayscale bitmap , where 7. The method of any one of claims 4 to 6, wherein the area defined at the location by the wipeout mask data is greater than the area defined by the multi-level grayscale bitmap. 8. A method according to any one of claims 3 to 7, wherein said wipeout mask data is a 1 bpp bitmap. 9. The method of claim 8, wherein the wipeout mask data covers one stripe or scan line on the wafer. said multi-level grayscale bitmap is a 4bpp grayscale bitmap and said wipeout mask data is a 4bpp sparse bitmap, whereby said merging provides an exact location defined by said wipeout bitmap 7. A method according to any one of claims 4 to 6, wherein pixels are erased with . 11. The method of any one of claims 1-10 , wherein the electronic device is a semiconductor chip and the maskless pattern writer is a charged particle multi-beamlet lithography machine. The structure is
connections between metal layers, also known as vias;
a connection between the metal layer and the gate of the contact layer;
connection at the local interconnect layer and
P-implants or N-implants of certain parts of transistors or diodes;
12. A method according to any preceding claim, comprising at least one of 13. The method of any one of claims 1-12 , wherein the non-common structure is formed on one layer of a semiconductor chip of the electronic device. A computer method for using a maskless lithography exposure system using a maskless pattern writer and generating beamlet control data for controlling the maskless pattern writer to expose a wafer for the fabrication of electronic devices. wherein exposing the wafer according to the beamlet control data results in exposing patterns having different sets of structures for different subsets of the electronic devices, the method but,
receiving design layout data defining a plurality of structures for the electronic device manufactured from the wafer;
receiving selection data defining which of the structures of the design layout data are applicable to each electronic device manufactured from the wafer, the selection data being different portions of the electronic device; receiving selection data defining different sets of said structures for sets;
receiving location metadata specifying the location of the structure defined in the design layout data;
generating wipeout mask data based on the location metadata and the selection data;
generating the beamlet control data by merging the design layout data or a derivative of the design layout data with the wipeout mask data, thereby removing unselected structures from the design layout data;
computer programs , including Using a maskless lithography exposure system using a maskless pattern writer and performing a method for generating beamlet control data for controlling the maskless pattern writer to expose a wafer for the fabrication of electronic devices to expose patterns having different sets of structures for different subsets of the electronic devices by exposing the wafer according to the beamlet control data. and the method is
receiving design layout data defining a plurality of structures for the electronic device manufactured from the wafer;
receiving selection data defining which of the structures of the design layout data are applicable to each electronic device manufactured from the wafer, the selection data being different portions of the electronic device; receiving selection data defining different sets of said structures for sets;
receiving location metadata specifying the location of the structure defined in the design layout data;
generating wipeout mask data based on the location metadata and the selection data;
generating the beamlet control data by merging the design layout data or a derivative of the design layout data with the wipeout mask data, thereby removing unselected structures from the design layout data;
A data processing system, including

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