JP7217116B2 - analog/digital converter - Google Patents

Description

The invention disclosed herein relates to analog-to-digital converters.

In recent years, successive approximation analog/digital converters have been used in various applications as means for converting analog signals into digital signals.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

JP 2004-180065 A

However, conventional analog/digital converters have room for further improvement in terms of improving reliability and shortening test time.

The invention disclosed in the present specification aims to provide an analog-to-digital converter with high reliability and short test time in view of the above problems found by the inventors of the present application.

The analog/digital converter disclosed in this specification compares binary values according to the magnitude relationship between a first analog signal input in a first phase and a second analog signal input in a second phase. a comparator that generates a signal; a digital/analog converter that generates an analog reference signal corresponding to a digital reference signal and outputs it to the comparator; operation control of the comparator, holding of the comparison signal, and the digital reference signal and, during self-diagnostic operation, the analog reference signals having different values are sequentially input to the comparator as the first analog signal and the second analog signal, respectively, to generate the comparison signal. A configuration (first configuration) in which expected value determination is performed is employed.

In the analog/digital converter having the first configuration, the expected value determination of the comparison signal during the self-diagnostic operation is performed each time the bit of the digital reference signal is switched (second configuration). should be

In addition, during normal operation, the analog/digital converter having the above-described first or second configuration converts the first analog signal and the second analog signal, respectively, into analog input signals to be converted or and the analog reference signal are sequentially input to the comparator, and a digital output signal is generated by sequentially determining the bit value of the digital reference signal according to the comparison signal (third configuration). do it.

Further, the analog/digital converter having the third configuration described above further includes a signal input/output unit that adjusts the signal level of the analog input signal to generate an adjusted analog input signal that falls within a predetermined input range (the 4).

In the analog/digital converter having the fourth configuration, the adjusted analog input signal is fixed to a predetermined reference value during the self-diagnostic operation, and the expected value of the digital output signal is determined (fifth configuration).

Further, the analog/digital converter having the above fourth or fifth configuration further includes an input switching unit that selects one of the multi-channel adjusted analog input signals and outputs it to the comparator (sixth configuration).

Further, in the analog/digital converter having the sixth configuration, the expected value of the digital output signal is judged while switching the adjusted analog input signal of each channel fixed to a different value during the self-diagnostic operation. A configuration (seventh configuration) is preferable.

Further, in the analog/digital converter having any one of the fourth to seventh configurations, the signal input/output unit has a function of switching a voltage division ratio of the analog input signal, and during the self-diagnostic operation, the A configuration (eighth configuration) in which the expected value determination of the digital output signal is performed while switching the voltage division ratio is preferable.

Further, the analog/digital converter having any one of the first to eighth configurations has a configuration (ninth configuration) in which the operation of the controller is checked using a digital self-diagnostic tool during the self-diagnostic operation. do it.

Further, the monitoring IC disclosed in this specification includes an analog/digital converter configured to convert an analog input signal to be monitored into a digital output signal, and the digital output and a logic unit that accepts signal input and determines whether the analog input signal is normal or not (a tenth configuration).

Further, the electronic device disclosed in this specification includes a power supply IC that generates an output voltage from an input voltage, and a monitoring IC that has the tenth configuration and determines whether the output voltage is normal. , and a microcomputer for receiving the determination result of the monitoring IC (eleventh configuration).

According to the invention disclosed in this specification, it is possible to provide an analog/digital converter with high reliability and short test time.

1 shows a first embodiment of an analog/digital converter; FIG. FIG. 4 is a diagram showing an example of self-diagnostic operation in the first embodiment; Diagram showing an example of setting a digital reference signal FIG. 2 shows a second embodiment of an analog/digital converter; A diagram showing an example of self-diagnostic operation in the second embodiment. FIG. 3 shows a third embodiment of an analog/digital converter; A diagram showing an example of self-diagnostic operation in the third embodiment. A diagram showing an example of an electronic device using an analog/digital converter

<Analog/digital converter (first embodiment)>
FIG. 1 shows a first embodiment of an analog/digital converter. The analog/digital converter 10 of this embodiment is a successive approximation type analog/digital converter ( It is a so-called SAR-ADC [Successive Approximation Register type Analog-to-Digital Converter]) and has a comparator 11 , a digital/analog converter 12 and a controller 13 .

The comparator 11 compares a first analog signal input in the first phase φ1 (analog input signal AIN during normal operation) and a second analog signal input in the second phase φ2 (analog reference signal AREF during normal operation). It is a chopper-type comparator that generates a binary comparison signal CMPO according to the magnitude relationship, and includes inverters INV1 and INV2, capacitors C1 and C2, and switches SW1 to SW4.

A first end of the switch SW1 is connected to an application end of the analog input signal AIN. A first end of the switch SW2 is connected to the application end of the analog reference signal AREF (=the output end of the digital/analog converter 12). A second end of each of the switches SW1 and SW2 is connected to a first end of the capacitor C1. A second end of the capacitor C1 is connected to an input end of the inverter INV1 and a first end of the switch SW3. The output end of the inverter INV1 and the second end of the switch SW3 are connected to the first end of the capacitor C2. A second end of the capacitor C2 is connected to the input end of the inverter INV2 and the first end of the switch SW4. The output end of the inverter INV2 and the second end of the switch SW4 are connected to the controller 13 and the logic section 20 as the output end of the comparison signal CMPO.

Note that the number of stages of inverters in the comparator 11 may be one, or may be three or more.

The digital/analog converter 12 converts an m-bit (for example, m=14) digital reference signal DREF input from the controller 13 into an analog reference signal AREF, and outputs the analog reference signal AREF to the comparator 11 .

The controller 13 controls the operation of the comparator 11 (=on/off control of the switches SW1 to SW4), sequentially holds the comparison signal CMPO, and digital reference signals DREF and It generates a digital output signal DOUT and the like. Further, the controller 13 receives inputs of a DAC [Digital-to-Analog] value S1 and a switch control signal S2 from the logic unit 20, and performs self-diagnostic operation in a test mode (so-called BIST [Built-In Self Test] operation). ).

The logic unit 20 receives the input of the digital output signal DOUT from the analog/digital converter 10 and performs various logical operations (for example, processing to determine whether the analog input signal AIN is normal). The logic unit 20 also has a function of receiving a test mode transition command from an external microcomputer (not shown) and outputting a DAC value S1 for self-diagnostic operation and a switch control signal S2 to the controller 13 .

<Normal operation>
First, normal operation of the analog/digital converter 10 will be described. During normal operation, the switch SW1 is turned on and the switch SW2 is turned off in the first phase φ1 (=sampling period). Accordingly, the analog input signal AIN is applied to the first end of the capacitor C1.

Also, in the first phase φ1, the switch SW3 is turned on. Therefore, the input potential INV1I and the output potential INV1O of the inverter INV1 are the same potential (=logical threshold TH1 of the inverter INV1). As a result, a charge corresponding to the potential difference (=AIN-TH1) between the analog input signal AIN and the logic threshold TH1 is stored across the capacitor C1.

Also, in the first phase φ1, the switch SW4 is turned on. Therefore, the input potential INV2I and the output potential INV2O of the inverter INV2 are the same potential (=logical threshold TH2 of the inverter INV2). As a result, a charge corresponding to the potential difference (=TH1-TH2) between the logic threshold TH1 and the logic threshold TH2 is stored across the capacitor C2.

By the above operation, the analog input signal AIN to be A/D converted is sampled in the first phase φ1.

Next, the analog/digital converter 10 is switched from the first phase φ1 to the second phase φ2 (=comparison period). In the second phase φ2, the switch SW1 is turned off and the switch SW2 is turned on. Accordingly, the analog reference signal AREF is applied to the first end of capacitor C1.

In the first comparison operation, the most significant bit (=MSB [Most Significant Bit]) of the digital reference signal DREF is set to "1" and all other bits are set to "0" to output the analog reference signal AREF. Set it to the middle value of the range. Note that during normal operation of the analog/digital converter 10, the digital reference signal DREF is equivalent to the digital output signal DOUT.

Also, in the second phase φ2, the switch SW3 is turned off. At this time, the charge accumulated in the first phase φ1 is held across the capacitor C1. Therefore, the input potential INV1I of the inverter INV1 becomes the potential obtained by subtracting the voltage across the capacitor C1 from the analog reference signal AREF (=AREF-(AIN-TH1)).

Here, when the input potential INV1I (=AREF−AIN+TH1) of the inverter INV1 is higher than the logic threshold TH1, the output potential INV1O of the inverter INV1 becomes low level L (=GND). , the output potential INV1O of the inverter INV1 becomes high level H (=AVDD).

Also, in the second phase φ2, the switch SW4 is turned off. At this time, the charge accumulated in the first phase φ1 is held across the capacitor C2. Therefore, the input potential INV2I of the inverter INV2 becomes a potential (=INV1O-(TH1-TH2)) obtained by subtracting the voltage across the capacitor C2 from the output potential INV1O (=AVDD or GND) of the inverter INV1.

Here, when the input potential INV2I (=INV1O-TH1+TH2) of the inverter INV2 is higher than the logic threshold TH2, the output potential INV2O of the inverter INV2 becomes low level L (=GND). , the output potential INV2O of the inverter INV2 becomes high level H (=AVDD).

That is, when AIN<AREF, INV1O=L (<TH1) and INV2O=H. Conversely, when AIN>AREF, INV1O=H (>TH1) and INV2O=L.

As a result, the comparison signal CMPO (=INV2O) becomes a binary logic signal corresponding to the magnitude relationship between the analog input signal AIN and the analog reference signal AREF. More specifically, CMPO=H when AIN<AREF and CMPO=L when AIN>AREF.

When CMPO=H, since AIN<AREF, the most significant bit value of the digital reference signal DREF should be determined to be "0". On the other hand, when CMPO=L, since AIN>AREF, the most significant bit value of the digital reference signal DREF should be set to "1".

After that, by repeating the same successive approximation operation from the second high-order bit of the digital reference signal DREF to the least significant bit (=LSB [Least Significant Bit]), the digital reference signal DREF (and eventually the digital output signal DOUT ) are determined.

In this manner, during normal operation of the analog/digital converter 10, the analog input signal AIN and the analog reference signal AREF are sequentially input to the comparator 11, and the bit values of the digital reference signal DREF are sequentially determined according to the comparison signal CMPO. By doing so, a digital output signal DOUT is generated.

<Self-diagnosis operation>
Next, the self-diagnostic operation of analog/digital converter 10 will be described. FIG. 2 is a flow chart showing an example of self-diagnosis operation in the first embodiment. The self-diagnostic operation in this figure includes a first self-diagnostic operation (step #100) for which the controller 13 is to be diagnosed, and a second self-diagnostic operation (step #100) for which the comparator 11 and the digital/analog converter 12 are to be diagnosed. Steps #101 to #107) are included.

When the self-diagnostic operation in the test mode is started, first, in step #100, by using the digital self-diagnostic tool (=digital BIST circuit such as scan path) introduced in the logic section 20, the controller 13 (and the logic section 20 itself) is verified.

When the first self-diagnostic operation (step #100) for diagnosing the controller 13 is completed, subsequently, the second self-diagnostic operation (steps #101 to #101) for the comparator 11 and the digital/analog converter 12 #107) is started.

First, at step #101, the check target bit of the digital/analog converter 12 is set. Specifically, the set value X of the digital reference signal DREF in the first phase φ1 and the set value Y of the digital reference signal DREF in the second phase φ2 are determined.

FIG. 3 is a table showing a setting example of the digital reference signal DREF, and the check target bit of the digital/analog converter 12 and the set values X and Y (respectively in binary notation and decimal notation) of the digital reference signal DREF are are mapped. In this figure, the digital/analog converter 12 is assumed to have 14 bits, and set values X and Y corresponding to the 1st bit (LSB) to the 14th bit (MSB) are listed.

In the first self-diagnostic loop, for example, the first bit (LSB) of the digital/analog converter 12 may be set as the check target bit. Specifically, the set value X of the digital reference signal DREF in the first phase φ1 is set to "00 0000 0000 0000b (=0d)", and the set value Y of the digital reference signal DREF in the second phase φ2 is set to "00 0000 0000 0001b". (=1d)".

Also, in the second self-diagnostic loop, for example, the second bit of the digital/analog converter 12 may be set as a check target bit. Specifically, the set value X of the digital reference signal DREF in the first phase φ1 is set to "00 0000 0000 0001b (=1d)", and the set value Y of the digital reference signal DREF in the second phase φ2 is set to "00 0000 0000 0010b". (=2d)".

More generalized, in the k-th (k=1, 2, . . . , 14) self-diagnostic loop, the k-th bit of the digital/analog converter 12 should be the bit to be checked. Specifically, the set value X of the digital reference signal DREF in the first phase φ1 is set to “(2 ^k−1 −1)d”, and the set value Y of the digital reference signal DREF in the second phase φ2 is set to “2 ^{k− 1} d". Note that the set value X and the set value Y may be exchanged with each other.

Returning to FIG. 2, the description of the flowchart is continued. When the setting of the check target bit in step #101 is completed, the analog/digital converter 10 is set to the first phase φ1 in steps #102 and #103. More specifically, at step #102, the switch SW1 is turned off and the switch SW2 is turned on. At this time, the digital reference signal DREF is set to the set value X in step #103. Therefore, an analog reference signal AREF (hereinafter referred to as an analog reference signal AREFX) corresponding to the set value X is applied to the first end of the capacitor C1.

Also, at step #102, the switch SW3 is turned on. Therefore, the input potential INV1I and the output potential INV1O of the inverter INV1 are the same potential (=TH1). As a result, a charge corresponding to the potential difference (=AREFX-TH1) between the analog reference signal AREFX and the logic threshold TH1 is stored across the capacitor C1.

Also, at step #102, the switch SW4 is turned on. Therefore, the input potential INV1I and the output potential INV1O of the inverter INV2 are the same potential (=TH2). As a result, a charge corresponding to the potential difference (=TH1-TH2) between the logic threshold TH1 and the logic threshold TH2 is stored across the capacitor C2.

By the above operation, the analog reference signal AREFX is sampled in the first phase φ1 (=steps #102 and #103).

Next, in steps #104 to #106, the analog/digital converter 10 is switched from the first phase φ1 to the second phase φ2. More specifically, at step #104, the switch SW1 is turned off and the switch SW2 is turned on. At this time, the digital reference signal DREF is set to the set value Y in step #105. Therefore, an analog reference signal AREF (hereinafter referred to as an analog reference signal AREFY) corresponding to the set value Y is applied to the first end of the capacitor C1.

Also, at step #104, the switch SW3 is turned off. At this time, the charge accumulated in the first phase φ1 is held across the capacitor C1. Therefore, the input potential INV1I of the inverter INV1 becomes the potential obtained by subtracting the voltage across the capacitor C1 from the analog reference signal AREFY (=AREFY-(AREFX-TH1)).

Here, when the input potential INV1I (=AREFY-AREFX+TH1) of the inverter INV1 is higher than the logic threshold TH1, the output potential INV1O of the inverter INV1 becomes low level L (=GND), and conversely, when it is lower than the logic threshold TH1. , the output potential INV1O of the inverter INV1 becomes high level H (=AVDD).

Also, at step #104, the switch SW4 is turned off. At this time, the charge accumulated in the first phase φ1 is held across the capacitor C2. Therefore, the input potential INV2I of the inverter INV2 becomes a potential (=INV1O-(TH1-TH2)) obtained by subtracting the voltage across the capacitor C2 from the output potential INV1O (=AVDD or GND) of the inverter INV1.

Here, when the input potential INV2I (=INV1O-TH1+TH2) of the inverter INV2 is higher than the logic threshold TH2, the output potential INV2O of the inverter INV2 becomes low level L (=GND). , the output potential INV2O of the inverter INV2 becomes high level H (=AVDD).

As described above, the set values X and Y of the digital reference signal DREF are set so as to satisfy X<Y (for example, X=0d, Y=1d). Therefore, if the check target bit of the digital/analog converter 12 is normal, AREFX<AREFY should be established, and the comparison signal CMPO (=INV2O) should be high level.

Therefore, in step #106, the expected value determination of the comparison signal CMPO (determination of whether or not CMPO=H) is performed. Here, if the comparison signal CMPO as expected is obtained, it is determined that the check target bit of the digital/analog converter 12 (or the comparator 11) is normal. On the other hand, if the expected comparison signal CMPO is not obtained, it is determined that the check target bit of the digital/analog converter 12 (or the comparator 11) is abnormal.

At subsequent step #107, it is determined whether or not the self-diagnostic operation has been completed up to the final bit (for example, the most significant bit) of the digital/analog converter 12 . Here, if the determination is YES, the series of flows described above is completed. On the other hand, if a negative determination is made, the flow is returned to step #101, and the check target bit of the digital/analog converter 12 is reset.

As described above, during the second self-diagnostic operation in which the comparator 11 and the digital/analog converter 12 are to be diagnosed, the analog reference signals AREFX and AREFY having different values are applied to the comparator while the input path of the analog input signal AIN is cut off. 11 to determine the expected value of the comparison signal CMPO.

With the analog/digital converter 10 of the present embodiment, the digital/analog The converter 12 (or comparator 11) can be structurally tested. Therefore, it is possible to improve the reliability of circuit operation in the analog/digital converter 10 .

In particular, it is desirable to determine the expected value of the comparison signal CMPO during the self-diagnostic operation each time the digital reference signal DREF is switched. For example, as shown in FIG. 3 above, when the digital/analog converter 12 has m bits, there are m combinations of set values X and Y of the digital reference signal DREF (X=(2 ^k− 1−1)d, Y=2 ^{k−1 d} , where k=1, 2, . According to such a sequence, it is possible to guarantee DNL [Differential Non-Linearity] of the digital/analog converter 12 with the minimum expected value determination operation.

Further, by performing the above-described self-diagnostic operation in the pre-shipment test of the analog/digital converter 10, it is possible to shorten the required time compared to the conventional pre-shipment test.

<Analog/Digital Converter (Second Embodiment)>
FIG. 4 shows a second embodiment of an analog/digital converter. The analog/digital converter 10 of the present embodiment further includes a signal input/output unit 14 and an input switching unit 15 in addition to the aforementioned components (the comparator 11, the digital/analog converter 12, and the controller 13). have.

The signal input/output unit 14 is a circuit block that adjusts the signal levels of the two-channel analog input signals AIN1 and AIN2 to generate adjusted analog input signals AIN1d and AIN2d that fall within a predetermined input range. , SWB, SWC, SWD, SWE, SWF) and four resistors (RA, RB, RC, RD).

A first end of the switch SWA is connected to the input end of the analog input signal AIN1. A first end of the switch SWB is connected to the application end of the first reference voltage REF1. A first end of the switch SWC is connected to the ground end. A second end of each of the switches SWA, SWB and SWC is connected to a first end of the resistor RA. A second end of the resistor RA and a first end of the resistor RB are connected to a first input end of the selector 15 as an output end of the adjusted analog input signal AIN1d. A second end of the resistor RB is connected to the ground end.

A first end of the switch SWD is connected to the input end of the analog input signal AIN2. A first end of the switch SWE is connected to the application end of the second reference voltage REF2. A first end of the switch SWF is connected to the ground end. A second end of each of the switches SWD, SWE and SWF is connected to a first end of the resistor RC. A second end of the resistor RC and a first end of the resistor RD are connected to the second input end of the selector 15 as the output end of the adjusted analog input signal AIN2d. A second end of the resistor RD is connected to the ground end.

The input switching unit 15 is a circuit block that outputs one of the adjusted analog input signals AIN1d and AIN2d as the analog input signal AIN to the comparator 11, and includes a selector SEL, a buffer BUF, a resistor Rf, and a capacitor Cf. include.

The selector SEL selects one of the adjusted analog input signals AIN1d and AIN2d and outputs it as the selector output signal SELO to the buffer BUF.

The buffer BUF outputs a buffer output signal BUFO corresponding to the selector output signal SELO (=AIN1d or AIN2d) to the subsequent stage.

A first end of the resistor Rf is connected to the output end of the buffer BUF. A second end of the resistor Rf and a first end of the capacitor Cf are connected to the input end of the comparator 11 as the output end of the input switching section 15 . A second end of the capacitor Cf is connected to the ground end. The resistor Rf and capacitor Cf connected in this way function as an RC filter for removing the noise component of the buffer output signal BUFO to generate the analog input signal AIN.

By providing the input switching unit 15, it is possible to convert multi-channel analog input signals (AIN1, AIN2, . It becomes possible to plan Moreover, it is possible to reduce the time required for the self-diagnosis as compared with the case where a plurality of analog/digital converters are provided.

In addition, in the analog/digital converter 10 of the second embodiment, a first self-diagnostic operation for diagnosing the controller 13 and a second self-diagnostic operation for diagnosing the comparator 11 and the digital/analog converter 12 are performed. In addition to the above, it is desirable to perform a third self-diagnostic operation targeting the signal input/output unit 14 and the input switching unit 15 for diagnosis. A detailed description will be given below.

FIG. 5 is a flow chart showing an example of the self-diagnostic operation (=the third self-diagnostic operation for diagnosing the signal input/output unit 14 and the input switching unit 15) in the second embodiment. When the flow starts, at step #201, the switches SWA and SWC are turned off and the switch SWB is turned on. As a result, the adjusted analog input signal AIN1d becomes the divided voltage value of the first reference voltage REF1 (=α×REF1, where α=RB/(RA+RB)).

Also, at step #202, the switches SWD and SWE are turned off, and the switch SWF is turned on. As a result, the adjusted analog input signal AIN2d becomes the ground potential GND.

In the subsequent step #203, the selector SEL is switched so that SELO=AIN1d.

Then, in step #204, the analog input signal AIN (=AIN1d) is converted into a digital signal DOUT, and the expected value determination (=determination of whether or not a digital value corresponding to the first reference voltage REF1 is obtained) is performed. done.

Further, in the subsequent step #205, the selector SEL is switched so that SELO=AIN2d.

Then, in step #206, the analog input signal AIN (=AIN2d) is converted into the digital signal DOUT, and the expected value determination (=determination as to whether or not a digital value corresponding to the ground potential GND is obtained) is performed. .

After that, at step #207, the switches SWA and SWB are turned off, and the switch SWC is turned on. As a result, the adjusted analog input signal AIN1d becomes the ground potential GND.

Also, at step #208, the switches SWD and SWF are turned off, and the switch SWE is turned on. As a result, the adjusted analog input signal AIN2d becomes the divided voltage value of the second reference voltage REF2 (=β×REF2, where β=RD/(RC+RD)).

In the subsequent step #209, the selector SEL is switched so that SELO=AIN1d.

Then, at step #210, the analog input signal AIN (=AIN1d) is converted into the digital signal DOUT, and the expected value determination (=determination as to whether or not a digital value corresponding to the ground potential GND is obtained) is performed. .

Further, in the subsequent step #211, the selector SEL is switched so that SELO=AIN2d.

Then, in step #212, the analog input signal AIN (=AIN2d) is converted into a digital signal DOUT, and the expected value determination (=determination of whether or not a digital value corresponding to the second reference voltage REF2 is obtained) is performed. done. This completes a series of self-diagnosis processing.

In this way, during the third self-diagnostic operation in which the signal input/output unit 14 and the input switching unit 15 are to be diagnosed, different reference values (for example, α×REF1 and GND, or GND and β×REF2) are fixed. The expected value determination of the digital output signal DOUT is performed while sequentially switching the adjusted analog input signals AIN1d and AIN2d of each channel.

With the analog/digital converter 10 of the present embodiment, signal input/output is performed by performing the self-diagnostic operation described above at system start-up or at arbitrary timing (for example, enable input timing to the logic unit 20). The unit 14 and the input switching unit 15 can be structurally tested. Therefore, it is possible to improve the reliability of circuit operation in the analog/digital converter 10 .

The number of input channels of the analog/digital converter 10 is not limited to "2", and may be "3" or more.

<Analog/Digital Converter (Third Embodiment)>
FIG. 6 shows a third embodiment of an analog/digital converter. In the analog/digital converter 10 of this embodiment, the signal input/output unit 14 has a function of switching the voltage division ratios of the analog input signals AIN1 and AIN2.

More specifically, the signal input/output unit 14 includes three resistors (RAx, RAy, RAz) as elements corresponding to the resistor RA, resistor RB, resistor RC, and resistor RD described above. , resistors (RBx, RBy, RBz), resistors (RCx, RCy, RCz), and resistors (RDx, RDy, RDz). In addition, the signal input/output unit 14 newly includes six switches (SWa, SWb, SWc, SWd, SWe, SWf).

A first end of the switch SWA is connected to the input end of the analog input signal AIN1. A first end of the switch SWB is connected to the application end of the first reference voltage REF1. A first end of the switch SWC is connected to the ground end. Second ends of the switches SWA, SWB and SWC are all connected to first ends of the resistors RAx, RAy and RAz. A second end of the resistor RAx and a first end of the resistor RBx are connected to a first end of the switch SWa as an output end of the adjusted analog input signal AIN1x. A second end of the resistor RAy and a first end of the resistor RBy are connected to a first end of the switch SWb as an output end of the adjusted analog input signal AIN1y. A second end of the resistor RAz and a first end of the resistor RBz are connected to a first end of the switch SWc as an output end of the adjusted analog input signal AIN1z. A second end of each of the resistors RBx, RBy and RBz is connected to the ground end. A second end of each of the switches SWa, SWb, and SWc is connected to a first input end of the selector 15 as an output end of the adjusted analog input signal AIN1d.

A first end of the switch SWD is connected to the input end of the analog input signal AIN2. A first end of the switch SWE is connected to the application end of the second reference voltage REF2. A first end of the switch SWF is connected to the ground end. A second end of each of the switches SWD, SWE and SWF is connected to a first end of each of the resistors RCx, RCy and RCz. A second end of the resistor RCx and a first end of the resistor RDx are connected to a first end of the switch SWd as an output end of the adjusted analog input signal AIN2x. A second end of the resistor RCy and a first end of the resistor RDy are connected to a first end of the switch SWe as an output end of the adjusted analog input signal AIN2y. A second end of the resistor RCz and a first end of the resistor RDz are connected to a first end of the switch SWf as an output end of the adjusted analog input signal AIN2z. A second end of each of the resistors RDx, RDy and RDz is connected to the ground end. A second end of each of the switches SWd, SWe, and SWf is connected to a second input end of the selector 15 as an output end of the adjusted analog input signal AIN2d.

In addition, in the analog/digital converter 10 of the third embodiment, the third self-diagnostic operation (see FIG. 5) for diagnosing the signal input/output unit 14 and the input switching unit 15 can be partially changed. desirable. A detailed description will be given below.

FIG. 7 is a flow chart showing an example of self-diagnosis operation in the third embodiment. This flowchart is basically the same as the previous FIG. 5, and steps #204 and #212 are replaced with steps #204' and #212', respectively. Therefore, redundant description of steps similar to those in FIG. 5 will be omitted, and steps #204' and #212' will be mainly described.

At step #204′, the analog input signal AIN (=AIN1d) is converted into the digital output signal DOUT, and the expected value determination (=determination of whether or not a digital value corresponding to the first reference voltage REF1 is obtained) is performed. done.

At this time, it is desirable to determine the expected value of the digital output signal DOUT while switching the voltage division ratio of the analog input signal AIN1 by turning on/off the switches SWa, SWb, and SWc.

Specifically, first, by turning on the switch SWa and turning off the switches SWb and SWc, the adjustment analog input signal AIN1x (=αx×REF1, where αx=RBx/(RAx+RBx)) is selectively output. , the expected value determination of the digital output signal DOUT is performed.

Next, by turning on the switch SWb and turning off the switches SWa and SWc, the adjusted analog input signal AIN1y (=αy×REF1, where αy=RBy/(RAy+RBy)) is selectively output, and the digital output signal Expected value determination of DOUT is performed.

Finally, by turning on the switch SWc and turning off the switches SWa and SWb, the digital output signal DOUT is output while the adjusted analog input signal AIN1z (=αz×REF1, where αz=RBz/(RAz+RBz)) is selectively output. expected value judgment is performed.

Further, in step #212′, the analog input signal AIN (=AIN2d) is converted into the digital output signal DOUT, and the expected value determination (=determination of whether or not the digital value corresponding to the second reference voltage REF2 is obtained) ) is performed.

At this time, it is desirable to determine the expected value of the digital output signal DOUT while switching the voltage division ratio of the analog input signal AIN2 by turning on/off the switches SWd, SWe, and SWf.

Specifically, first, by turning on the switch SWd and turning off the switches SWe and SWf, the adjustment analog input signal AIN2x (=βx×REF2, where βx=RDx/(RCx+RDx)) is selectively output. , the expected value determination of the digital output signal DOUT is performed.

Next, by turning on the switch SWe and turning off the switches SWd and SWf, the adjusted analog input signal AIN2y (=βy×REF2, where βy=RDy/(RCy+RDy)) is selectively output, and the digital output signal Expected value determination of DOUT is performed.

Finally, by turning on the switch SWf and turning off the switches SWd and SWe, the digital output signal DOUT is output while the adjusted analog input signal AIN2z (=βz×REF2, where βz=RDz/(RCz+RDz)) is selectively output. expected value judgment is performed.

At step #206, at least one of the switches SWd, SWe, and SWf should be turned on. Similarly, at step #210, at least one of the switches SWa, SWb, and SWc should be turned on.

With the analog/digital converter 10 of this embodiment, the voltage division ratio switching mechanism of the signal input/output unit 14 can be structurally tested. Therefore, it is possible to improve the reliability of circuit operation in the analog/digital converter 10 .

The number of voltage division ratios to be switched in the signal input/output unit 14 is not limited to "3", and may be "2", or may be "4" or more.

<Electronic equipment>
FIG. 8 is a diagram showing an example of an electronic device using an analog/digital converter. The electronic device X of this configuration example has a monitor IC 1 , a power supply IC 2 , and a microcomputer 3 .

The monitoring IC 1 is a semiconductor integrated circuit device that determines whether or not the output voltages VO1 to VO4 generated by the power supply IC 2 are normal and notifies the microcomputer 3 of the determination result. Logic part 20 is integrated.

The analog/digital converter 10 converts analog input signals AIN1 to AIN4 (=output voltages VO1 to VO4) to be monitored into an m-bit digital output signal DOUT and outputs the m-bit digital output signal DOUT to the logic unit 20 .

The analog/digital converter 10 is based on, for example, the second embodiment (FIG. 4) and the third embodiment (FIG. 6) described above, and the number of input channels is expanded to "4". Apply it. Alternatively, while the first embodiment (FIG. 1) is used as a base, it is also possible to extend the parallel number to "4" and apply it.

The logic unit 20 receives the input of the digital output signal DOUT from the analog/digital converter 10 and performs various logic operations (for example, determination processing as to whether or not the output voltages VO1 to VO4 are normal).

Further, the logic unit 20 performs two-way communication with the microcomputer 3 via an SPI [Serial Peripheral Interface] bus or the like, and notifies the microcomputer 3 of the determination results of the output voltages VO1 to VO4. The logic unit 20 also has a function of receiving a test mode shift command from the microcomputer 3 and controlling the self-diagnostic operation of the analog/digital converter 10 .

The self-diagnostic operation of the analog/digital converter 10 described above may be performed when the system of the electronic device X is activated (for example, when the power of the IC 1 to be monitored is turned on).

The power supply IC 2 is a semiconductor integrated circuit device (so-called PMIC [Power Management IC]) that generates four channels of output voltages VO1 to VO4 from the input voltage VI. A switching regulator, a linear regulator, or the like is used as the output stage of the power supply IC 2 .

The microcomputer 3 receives the determination results of the output voltages VO1 to VO4 obtained by the monitor IC 1 and controls the overall operation of the electronic device X in an integrated manner. For example, if any of the output voltages VO1 to VO4 is determined to be abnormal, the microcomputer 3 forcibly shuts down part or all of the electronic device X. Such a protection operation makes it possible to enhance the safety of the electronic device X. FIG.

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

The invention disclosed in this specification can be applied to general analog/digital converters used in various applications.

1 monitoring IC
2 Power supply IC (power management IC)
3 microcomputer 10 analog/digital converter 11 comparator 12 digital/analog converter 13 controller 14 signal input/output unit 15 input switching unit 20 logic unit BUF buffer C1, C2, Cf capacitor RA, RAx, RAy, RAz resistor RB, RBx, RBy, RBz Resistance RC, RCx, RCy, RCz Resistance RD, RDx, RDy, RDz Resistance Rf Resistance INV1, INV2 Inverter SEL Selector SW1, SW2, SW3, SW4 Switch SWA, SWB, SWC, SWD, SWE, SWF Switch SWa, SWb, SWc, SWd, SWe, SWf Switch X Electronic equipment

Claims (13)

a comparator that generates a binary comparison signal according to the magnitude relationship between the first analog signal input in the first phase and the second analog signal input in the second phase;
a digital/analog converter that generates an analog reference signal corresponding to the digital reference signal and outputs the analog reference signal to the comparator;
a controller that controls the operation of the comparator, holds the comparison signal, and generates the digital reference signal;
a logic unit that refers to a table in which a pattern of the digital reference signal is preset and controls the controller to generate the digital reference signal according to the pattern during a self-diagnostic operation;
has
During the self-diagnostic operation, the analog reference signals having different values are sequentially input to the comparator as the first analog signal and the second analog signal, respectively, and the expected value of the comparison signal is determined. An analog-to-digital converter wherein operation of the comparator and said digital-to-analog converter is diagnosed . 2. The method according to claim 1 , wherein the determination of the expected value of the comparison signal during the self-diagnostic operation is performed sequentially each time a bit of the digital reference signal is switched , with each bit of the digital/analog converter being checked . Analog/digital converter. In the table, a check target bit of the digital/analog converter is associated with a first setting value and a second setting value of the digital reference signal, and the first analog signal and the second analog signal having different values are associated with each other. 3. The analog-to-digital converter according to claim 2, wherein the number of combinations of said analog reference signals input as signals is equal to the number of bits of said digital-to-analog converter. Let m be the number of bits of the digital/analog converter, k be the number of bits to be checked of the digital/analog converter, where k=1, 2, . . . , m, and the first set value of the digital reference signal and the second setting values are X and Y respectively,
In the table, as a combination of the first setting value and the second setting value, m ways of X=(2 ^k-1 -1) d and Y=2 ^k-1 4. An analog-to-digital converter as claimed in claim 3, wherein d is provided. During normal operation, an analog input signal to be converted or a signal corresponding thereto and the analog reference signal are sequentially input to the comparator as the first analog signal and the second analog signal, respectively. 5. The analog/digital converter according to claim 1, wherein the digital output signal is generated by successively determining the bit values of said digital reference signal. 6. The analog/digital converter according to claim 5 , further comprising a signal input/output unit that adjusts the signal level of said analog input signal to generate an adjusted analog input signal that falls within a predetermined input range. 7. The analog/digital converter according to claim 6 , wherein during said self-diagnostic operation, said adjusted analog input signal is fixed at a predetermined reference value, and expected value determination of said digital output signal is performed. 8. The analog/digital converter according to claim 6, further comprising an input switching unit that selects one of said multi-channel adjusted analog input signals and outputs it to said comparator. 9. The analog/digital converter according to claim 8 , wherein during the self-diagnostic operation, the expected value of the digital output signal is determined while switching the adjusted analog input signals of each channel fixed to different values. The signal input/output unit has a function of switching the voltage division ratio of the analog input signal, and during the self-diagnostic operation, the expected value determination of the digital output signal is performed while switching the voltage division ratio . 10. Analog-to-digital converter according to any one of claims 9 . 11. The analog/digital converter according to any one of claims 1 to 10, wherein during said self-diagnostic operation, an operation check of said controller is performed using a digital self-diagnostic tool. an analog-to-digital converter according to any one of claims 1 to 11 , which converts an analog input signal to be monitored into a digital output signal;
a logic unit that receives the input of the digital output signal and determines whether the analog input signal is normal;
monitoring IC . a power supply IC that generates an output voltage from an input voltage;
The monitoring IC according to claim 12 , which determines whether the output voltage is normal;
a microcomputer that receives the determination result of the monitoring IC;
An electronic device having

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