JP7208889B2 - broadcasting system - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device and a broadcasting system.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification and the like relates to products, methods, or manufacturing methods. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter. Therefore, the technical fields of one embodiment of the present invention disclosed in this specification more specifically include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, processors, electronic devices, Examples include driving methods thereof, manufacturing methods thereof, inspection methods thereof, or systems thereof.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are modes of a semiconductor device. Storage devices, display devices, imaging devices, and electronic devices may include semiconductor devices.

2. Description of the Related Art Television (TV) is expected to be able to view high-definition video as the screen becomes larger. Therefore, ultra-high-definition TV (UHDTV) broadcasting is being put into practical use. In Japan, where UHDTV broadcasting is being promoted, 4K broadcasting service started in 2015 using communication (CS) satellites and optical circuits. In the future, test broadcasting of UHDTV (4K, 8K) by broadcasting (BS) satellites is scheduled to start. Therefore, various electronic devices have been developed to support 8K broadcasting (Non-Patent Document 1). In 8K practical broadcasting, 4K broadcasting and 2K broadcasting (full high-definition broadcasting) are scheduled to be used together.

Further, development is underway to add artificial intelligence (AI) using an artificial neural network or the like to various electronic devices, not limited to televisions. By using artificial neural networks, it is expected that computers with higher performance than conventional von Neumann computers can be realized, and in recent years, various researches have been conducted to construct artificial neural networks on electronic circuits. Non-Patent Document 2 describes a technique related to a chip having a self-learning function by an artificial neural network.

Further, Patent Document 1 discloses an invention in which a memory device using a transistor including an oxide semiconductor in a channel formation region holds weight data necessary for calculation using an artificial neural network.

U.S. Patent Publication No. 2016/0343452

S. Kawasaki, et al. , "13.3-In. 8K X 4K 664-ppi OLED Display Using CAAC-OS FETs," SID 2014 DIGEST, pp. 627-630. Yutaka Arima et al. , ``A Self-Learning Neural Network Chip with 125 Neurons and 10K Self-Organization Synapses'', IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 26, No. 4, APRIL 1991, pp. 607-611.

A new standard, H.264, is used as a video coding method for 8K broadcasting. 265 | MPEG-H HEVC (High Efficiency Video Coding) has been adopted. The video resolution (horizontal and vertical pixel count) of 8K broadcasting is 7680×4320, which is four times that of 4K (3840×2160) and 16 times that of 2K (1920×1080). Therefore, 8K broadcasting needs to handle large amounts of image data. Therefore, it is preferable that a transmission device provided on an artificial satellite, a radio tower, or the like compresses the image data before transmitting it. In this case, it is necessary to decompress the received image data in the receiving device provided in the TV or the like.

Compression of image data can be performed using an encoder. Further, decompression of compressed image data can be performed using a decoder. The encoder is provided, for example, in the transmitting device, and the decoder is provided, for example, in the receiving device.

An artificial neural network is a network that can perform calculations that imitate brain function, and by learning (optimizing parameters) using a large amount of learning data, it obtains the optimal answer to the desired problem. be able to.

One of the applications of artificial neural networks is an autoencoder. The autoencoder uses input image data as teacher data (or labels). That is, it corresponds to unsupervised learning. One of the features of autoencoders is that the input image can be compressed inside the artificial neural network and decompressed at the output. An autoencoder can therefore be viewed as an artificial neural network with an encoder and a decoder.

Increase the number of dimensions (number of neurons) of each intermediate layer included in the autoencoder as a method of suppressing image quality deterioration when compressing and decompressing image data by the autoencoder so that the autoencoder functions with high accuracy. or increase the depth (number of layers) of the intermediate layers included in the autoencoder. As a result, the autoencoder can perform more complicated learning, so that the autoencoder can function with high accuracy. However, if the circuit configuration of the autoencoder is complicated by increasing the number of dimensions of each intermediate layer of the autoencoder, or by increasing the depth (number of layers) of the intermediate layers included in the autoencoder, for example, the autoencoder There are problems that the time required for learning becomes longer and the number of parameters required for compressing and decompressing image data increases.

In view of the above problems, an object of one embodiment of the present invention is to provide a broadcasting system provided with an autoencoder having a small number of dimensions of each hidden layer and a small number of hidden layers, and an operation method thereof. Another object of one embodiment of the present invention is to provide a broadcasting system including an autoencoder with a simple circuit configuration and an operation method thereof. Another object of one embodiment of the present invention is to provide a broadcasting system provided with an autoencoder that requires a small number of parameters for operation and a method of operating the same. Another object of one embodiment of the present invention is to provide a broadcasting system provided with an autoencoder that operates at high speed, and an operation method thereof. Another object of one embodiment of the present invention is to provide a broadcasting system provided with an autoencoder capable of highly accurate compression and decompression, and an operation method thereof. Another object of one embodiment of the present invention is to provide a broadcasting system provided with an autoencoder with low power consumption and an operation method thereof. Another object of one embodiment of the present invention is to provide a broadcasting system including an arithmetic processing device with high calculation accuracy and an operation method thereof.

Another object of one embodiment of the present invention is to provide a semiconductor device with a simple circuit configuration and an operation method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device requiring a small number of parameters for operation and an operation method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device that operates at high speed and an operation method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device capable of performing highly accurate processing and an operation method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption and an operation method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device with high calculation accuracy and an operation method thereof.

Another object of one embodiment of the present invention is to provide a novel broadcasting system, a novel semiconductor device, and an operation method thereof.

Note that the problem of one embodiment of the present invention is not limited to the problems listed above. The issues listed above do not preclude the existence of other issues. Still other issues are issues not mentioned in this section, which will be described in the following description. Problems not mentioned in this section can be derived from descriptions in the specification, drawings, or the like by a person skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention is to solve at least one of the above-described problems and other problems. Note that one embodiment of the present invention does not necessarily solve all of the above-listed descriptions and other problems.

One aspect of the present invention includes a first circuit and an encoder, the first circuit and the encoder having functions of receiving first image data, the first circuit receiving the first The first circuit has a function of extracting features from image data, the first circuit has a function of extracting features from the first image data to generate attribute information representing the attributes of the first image data, and the encoder has a function of: , a second circuit, and a group of memories having two or more memory elements, the second circuit having a function of selecting one memory element from the group of memories based on attribute information. , the memory element has a function of holding first data corresponding to the attribute information, and the memory element stores a second image data corresponding to the first image data when selected by the second circuit. and the held first data to generate third data.

In the above aspect, the third data may be the product of the first data and the second data.

Further, in the above aspect, the encoder has a function of extracting features of the first image data based on the attribute information and outputting second image data obtained by compressing the first image, It may have a function of outputting the attribute information received from the first circuit.

Further, in the above aspect, the memory element may have a first transistor, and the first transistor may have a metal oxide in a channel formation region.

Further, in the above aspect, the memory element includes a second transistor and a first capacitor, and one of the source and the drain of the first transistor corresponds to the gate of the second transistor and the first capacitor. It is electrically connected to one of the pair of electrodes of the capacitive element, the first data is input to the other of the source or the drain of the first transistor, and the first capacitive element corresponds to the first data It may have a function of retaining electric charge.

Further, one aspect of the present invention includes a transmitting device and a receiving device, the transmitting device including a first circuit and an encoder, the receiving device including a decoder, an encoder, and and a decoder, forming an autoencoder, wherein the first circuit and the encoder have a function of receiving the first image data, and the first circuit has a function of extracting features from the first image data. , the first circuit has a function of generating attribute information representing attributes of the first image data by extracting features from the first image data, and the encoder generates the first image data based on the attribute information. The decoder has a function of generating second image data by compressing the first image data by extracting features from the image data. This is a broadcasting system that has a function to restore the original image data.

Further, in the above aspect, each of the encoder and the decoder has a second circuit and a group of memories having two or more memory elements, and the second circuit is based on the attribute information. , the memory element has a function of holding first data corresponding to the attribute information, and the memory element, when selected by the second circuit, It may have a function of generating third data based on second data corresponding to the first image data and the retained first data.

In the above aspect, the third data may be the product of the first data and the second data.

Further, in the above aspect, the memory element may have a first transistor, and the first transistor may have a metal oxide in a channel formation region.

Further, in the above aspect, the memory element includes a second transistor and a first capacitor, and one of the source and the drain of the first transistor corresponds to the gate of the second transistor and the first capacitor. It is electrically connected to one of the pair of electrodes of the capacitive element, the first data is input to the other of the source or the drain of the first transistor, and the first capacitive element corresponds to the first data It may have a function of retaining electric charge.

According to one aspect of the present invention, it is possible to provide a broadcasting system provided with an autoencoder having a small number of dimensionality of each hidden layer and a small number of hidden layers, and a method of operating the same. Alternatively, according to one aspect of the present invention, it is possible to provide a broadcasting system provided with an autoencoder with a simple circuit configuration and an operating method thereof. Another object of one aspect of the present invention is to provide a broadcasting system provided with an autoencoder requiring a small number of parameters for operation and an operation method thereof. Another object of one embodiment of the present invention is to provide a broadcasting system provided with an autoencoder that operates at high speed and an operation method thereof. Alternatively, according to one aspect of the present invention, it is possible to provide a broadcasting system provided with an autoencoder capable of highly accurate compression and decompression, and an operating method thereof. Alternatively, according to one aspect of the present invention, it is possible to provide a broadcasting system provided with an autoencoder with low power consumption and an operating method thereof. Alternatively, according to one embodiment of the present invention, it is possible to provide a broadcasting system provided with an arithmetic processing device with high calculation accuracy and an operating method thereof.

Alternatively, according to one embodiment of the present invention, a semiconductor device with a simple circuit configuration and an operation method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device requiring a small number of parameters for operation and an operation method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that operates at high speed and an operating method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device capable of performing highly accurate processing and an operation method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption and an operation method thereof can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high calculation accuracy and an operation method thereof can be provided.

Alternatively, one embodiment of the present invention can provide a novel broadcasting system, a novel semiconductor device, and an operating method thereof.

Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Still other effects are effects not mentioned in this section that will be described in the following description. Effects not mentioned in this item can be derived from the descriptions in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention has at least one of the effects listed above and other effects. Accordingly, one aspect of the present invention may not have the effects listed above depending on the case.

1 is a block diagram showing a configuration example of a broadcasting system; FIG. 1 is a block diagram showing a configuration example of a broadcasting system; FIG. 1 is a schematic diagram showing a configuration example of a broadcasting system; FIG. 4 is a flow chart showing an example of an autoencoder operation method. 4 is a flow chart showing an example of an autoencoder operation method. FIG. 2 is a block diagram showing a configuration example of an image recognition circuit; FIG. 2 is a block diagram showing a configuration example of an autoencoder; The figure which shows an example of the hierarchical artificial neural network. The figure which shows an example of the hierarchical artificial neural network. The figure which shows an example of the hierarchical artificial neural network. 4A and 4B are diagrams for explaining a configuration example of a circuit; FIG. 2 is a block diagram showing a configuration example of a circuit; 4A and 4B are a block diagram and a circuit diagram showing a configuration example of an arithmetic processing circuit; FIG. FIG. 2 is a block diagram explaining a programmable switch; FIG. 2 is a block diagram showing a configuration example of an autoencoder; FIG. 2 is a circuit diagram showing a configuration example of a product calculation circuit; FIG. 2 is a circuit diagram showing a configuration example of a product calculation circuit; 4 is a timing chart showing an example of the operation method of the product calculation circuit; 4 is a timing chart showing an example of the operation method of the product calculation circuit; FIG. 2 is a cross-sectional view showing a configuration example of a display device; FIG. 2 is a cross-sectional view showing a configuration example of a display device; FIG. 2 is a cross-sectional view showing a configuration example of a display device; FIG. 2 is a cross-sectional view showing a configuration example of a display device; 4A and 4B are cross-sectional views each illustrating a configuration example of a transistor; Schematic diagrams for explaining a laser irradiation method and a laser crystallization apparatus. The schematic diagram explaining the laser irradiation method. 1A and 1B are a top view and a cross-sectional view illustrating a configuration example of a transistor; 4A and 4B are cross-sectional views each illustrating a configuration example of a transistor; 4A and 4B are cross-sectional views each illustrating a configuration example of a transistor; The figure explaining the range of the atomic ratio of a metal oxide. 1A and 1B are a top view and a cross-sectional view illustrating a configuration example of a transistor; 4A and 4B are circuit diagrams and timing charts for explaining a configuration example of a pixel circuit; 1A and 1B are diagrams each illustrating an example of an electronic device;

In this specification and the like, an artificial neural network (ANN, hereinafter referred to as a neural network) refers to all models imitating the neural network of living organisms. In general, a neural network has a configuration in which units that simulate neurons are connected to each other via units that simulate synapses.

The strength (also called weighting factor) of synaptic connections (connections between neurons) can be varied by providing existing information to the neural network. In this way, the process of giving existing information to the neural network and determining the coupling strength is sometimes called "learning".

Also, by giving some information to the neural network that has "learned" (determined the coupling strength), it is possible to output new information based on the coupling strength. In this way, in a neural network, the process of outputting new information based on given information and coupling strength is sometimes called "inference" or "cognition".

Examples of neural network models include the Hopfield model and the hierarchical model. In particular, a multilayer neural network is called a "deep neural network" (DNN), and machine learning using a deep neural network is called "deep learning."

In this specification and the like, a metal oxide is a metal oxide in broad terms. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for an active layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. That is, when a metal oxide can constitute a channel-forming region of a transistor having at least one of an amplifying action, a rectifying action, and a switching action, the metal oxide is called a metal oxide semiconductor, abbreviated It can be called an OS. In addition, the description of an OS FET (or an OS transistor) can also be referred to as a transistor including a metal oxide or an oxide semiconductor.

An impurity of a semiconductor means, for example, a substance other than the main component that constitutes a semiconductor layer. For example, elements with a concentration of less than 0.1 atomic percent are impurities. When impurities are contained, for example, DOS (Density of States) is formed in the semiconductor, carrier mobility is lowered, crystallinity is lowered, and the like may occur. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, group 14 elements, group 15 elements, and elements other than the main component. There are transition metals and the like, especially for example hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed due to entry of impurities such as hydrogen. Further, when the semiconductor is a silicon layer, impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, group 15 elements excluding oxygen and hydrogen.

In this specification and the like, the ordinal numbers "first", "second", and "third" are added to avoid confusion of constituent elements. Therefore, the number of components is not limited. Also, the order of the components is not limited. Also, for example, the component referred to as "first" in one of the embodiments of this specification etc. is the component referred to as "second" in another embodiment or the scope of claims It is possible. Further, for example, the component referred to as "first" in one of the embodiments of this specification etc. may be omitted in other embodiments or the scope of claims.

Embodiments are described with reference to the drawings. Those skilled in the art will readily appreciate, however, that the embodiments can be embodied in many different forms and that various changes in form and detail can be made without departing from the spirit and scope thereof. be. Therefore, the present invention should not be construed as being limited to the description of the embodiments. In addition, in the configuration of the invention of the embodiment, the same reference numerals are used in common for the same parts or parts having similar functions in different drawings, and repeated description thereof will be omitted.

In this specification and the like, terms such as “above” and “below” are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. The positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, the words and phrases indicating the arrangement are not limited to the descriptions described in the specification, and can be appropriately rephrased according to the situation.

In addition, the terms "upper" and "lower" do not limit the positional relationship of the components to being directly above or directly below and in direct contact with each other. For example, the expression “electrode B on insulating layer A” does not require that electrode B be formed on insulating layer A in direct contact with another configuration between insulating layer A and electrode B. Do not exclude those containing elements.

Also, in the drawings, sizes, layer thicknesses, and regions are shown as arbitrary sizes for convenience of explanation. Therefore, it is not necessarily limited to that scale. Note that the drawings are shown schematically for clarity, and the shapes, values, and the like shown in the drawings are not limited. For example, variations in signal, voltage, or current due to noise or variations in signal, voltage, or current due to timing shift can be included.

Also, in drawings such as perspective views, description of some components may be omitted in order to ensure clarity of the drawings.

In addition, in the drawings, the same reference numerals may be given to the same elements, elements having similar functions, elements made of the same material, or elements formed at the same time, and repeated description thereof may be omitted. .

In this specification and the like, when describing the connection relationship of transistors, one of a source and a drain is referred to as “one of the source or the drain” (or the first electrode or the first terminal). is referred to as "the other of the source or the drain" (or the second electrode or the second terminal). This is because the source and drain of a transistor change depending on the structure or operating conditions of the transistor. Note that the names of the source and the drain of a transistor can be appropriately changed to a source (drain) terminal, a source (drain) electrode, or the like, depending on the situation. In addition, in this specification and the like, the two terminals other than the gate are sometimes called a first terminal and a second terminal, or sometimes called a third terminal and a fourth terminal. Further, when a transistor described in this specification and the like has two or more gates (this structure is sometimes referred to as a dual gate structure), these gates are sometimes referred to as a first gate and a second gate, or a front gate , is sometimes called a back gate. In particular, the term "front gate" is interchangeable with simply the term "gate." Also, the term "backgate" can be interchanged with the term simply "gate." Note that a bottom gate is a terminal formed before a channel formation region is formed when a transistor is manufactured, and a “top gate” is a terminal formed after a channel formation region is formed when a transistor is manufactured. It refers to a terminal that

A transistor has three terminals called gate, source, and drain. A gate is a terminal that functions as a control terminal that controls the conduction state of a transistor. One of the two input/output terminals functioning as a source or a drain functions as a source and the other as a drain depending on the type of transistor and the level of the potential applied to each terminal. Therefore, the terms "source" and "drain" can be used interchangeably in this specification and the like. In addition, in this specification and the like, the two terminals other than the gate are sometimes called a first terminal and a second terminal, or sometimes called a third terminal and a fourth terminal.

In addition, the terms “electrode” and “wiring” in this specification and the like do not functionally limit these constituent elements. For example, an "electrode" may be used as part of a "wiring" and vice versa. Furthermore, the terms "electrode" and "wiring" include the case where a plurality of "electrodes" and "wiring" are integrally formed.

In this specification and the like, voltage and potential can be interchanged as appropriate. A voltage is a potential difference from a reference potential. For example, if the reference potential is a ground potential, the voltage can be translated into a potential. Ground potential does not necessarily mean 0V. Note that the potential is relative, and the potential applied to the wiring or the like may be changed depending on the reference potential.

Note that in this specification and the like, terms such as “film” and “layer” can be interchanged depending on the case or situation. For example, it may be possible to change the term "conductive layer" to the term "conductive film." Or, for example, it may be possible to change the term "insulating film" to the term "insulating layer". Alternatively, depending on the case or situation, the terms "film", "layer", etc. can be omitted and replaced with other terms. For example, it may be possible to change the term "conductive layer" or "conductive film" to the term "conductor." Alternatively, for example, the terms “insulating layer” and “insulating film” may be changed to the term “insulator”.

Note that in this specification and the like, terms such as “wiring”, “signal line”, and “power line” can be interchanged depending on the case or situation. For example, it may be possible to change the term "wiring" to the term "signal line". Also, for example, it may be possible to change the term "wiring" to a term such as "power supply line". Also, vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring". A term such as “power line” may be changed to a term such as “signal line”. Also, vice versa, terms such as “signal line” may be changed to terms such as “power line”. In addition, the term "potential" applied to the wiring may be changed to the term "signal" or the like depending on the case or depending on the situation. Also, vice versa, terms such as "signal" may be changed to the term "potential".

The structure described in each embodiment can be combined with any structure described in another embodiment as appropriate to be one embodiment of the present invention. Moreover, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

It should be noted that the content (or part of the content) described in one embodiment may be combined with another content (or part of the content) described in that embodiment, or one or a plurality of other implementations. can be applied, combined, or replaced with at least one of the contents described in the form of (may be part of the contents).

The content described in the embodiments means the content described using various drawings or the content described using the sentences described in the specification in each embodiment.

It should be noted that the figure (may be part of) described in one embodiment refers to another part of that figure, another figure (may be part) described in that embodiment, and one or more other More drawings can be formed by combining at least one of the drawings (or part of them) described in the embodiments.

(Embodiment 1)
In this embodiment, a broadcasting system of one embodiment of the present invention and a semiconductor device or the like included in the broadcasting system will be described.

One embodiment of the present invention relates to a broadcasting system including an imaging device, a transmitting device, a receiving device, and a display device, and a semiconductor device included in the broadcasting system. Note that imaging devices, transmitting devices, receiving devices, display devices, and the like can be called semiconductor devices. In addition, a circuit or the like provided in an imaging device, a transmitting device, a receiving device, a display device, or the like can also be called a semiconductor device.

The imaging device has a function of generating image data and supplying it to the transmission device. The transmitting device has a function of transmitting image data to the receiving device. The receiving device has a function of receiving image data from the transmitting device. The display device has a function of displaying an image based on the image data received by the receiving device.

The transmitting device is provided with an image recognition circuit and an encoder, and the receiving device is provided with a decoder. A neural network is used for the image recognition circuit, encoder, and decoder, and the encoder and decoder constitute an autoencoder. Encoders and decoders are provided with memories that have the ability to hold weighting factors.

The image recognition circuit has a function of extracting features of image data, recognizing the image, and sorting the image data according to attributes. The image recognition circuitry can sort the image data according to objects contained in the image data, such as animals, plants, and man-made objects. In this case, animals, plants, and artifacts can be called attributes. Information indicating which attribute image data belongs to can be referred to as attribute information. The image recognition circuit has a function of generating attribute information of image data.

The encoder has a function of receiving attribute information from the image recognition circuit and compressing image data based on the attribute information. Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning. When the attribute information is received, arithmetic processing is performed using the weighting factor corresponding to the attribute information and the data corresponding to the image data. This allows the encoder to have a circuit configuration corresponding to the attribute of the image data and compress the image data. The compressed image data and the attribute information received from the image recognition circuit can be sent to the decoder.

The decoder has a function of decompressing the image data compressed by the encoder based on the attribute information. Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning. When the attribute information is received, arithmetic processing is performed using the weighting factor corresponding to the attribute information and the data corresponding to the compressed image data. Thus, the decoder can have a circuit configuration corresponding to the attributes of the image data, and the image data compressed by the encoder can be decompressed.

According to one aspect of the present invention, while simplifying the circuit configuration of the autoencoder, for example, while reducing the number of dimensions of each intermediate layer of the autoencoder, or reducing the number of intermediate layers included in the autoencoder, Accurate compression and decompression can be performed. As a result, the number of parameters required for the autoencoder to compress and decompress image data can be reduced, and high-precision compression and decompression can be performed. In addition, high-precision compression and decompression can be performed while operating the autoencoder at high speed. One aspect of the present invention is particularly effective when the display device has a function of displaying extremely high resolution such as 2K, 4K, or 8K.

Further, according to one embodiment of the present invention, it is possible to provide an encoder capable of highly accurate compression of image data with a simple circuit configuration, and a transmission device having the encoder. Accordingly, it is possible to provide an encoder capable of highly accurate compression with a small number of parameters, and a transmission device having the encoder. Also, it is possible to provide an encoder capable of highly accurate compression in a short learning time, and a transmission device having the encoder. Further, according to one embodiment of the present invention, it is possible to provide a decoder capable of decompressing image data with high accuracy with a simple circuit configuration, and a receiving device having the decoder. Accordingly, it is possible to provide a decoder capable of highly accurate decompression with a small number of parameters, and a receiver having the decoder. Also, it is possible to provide a decoder capable of highly accurate decompression in a short learning time, and a receiver having the decoder.

<Broadcast system>
FIG. 1 is a block diagram schematically showing a configuration example of a broadcasting system 10, which is a broadcasting system according to one aspect of the present invention. A broadcasting system 10 has an imaging device 11 , a transmitting device 12 , a receiving device 13 and a display device 14 .

The imaging device 11 has an image sensor IS and an image processing circuit PP1. The transmitter 12 has an image recognition circuit PR and an encoder AIE. The receiving device 13 has a decoder AID. The display device 14 has an image processing circuit PP2 and a display section PA. A neural network is used for the image recognition circuit PR, the encoder AIE, and the decoder AID, and the autoencoder 20 is configured by the encoder AIE and the decoder AID. Although the details will be described later, the encoder AIE and the decoder AID are provided with memories having a function of holding weighting coefficients.

When the imaging device 11 is capable of capturing an 8K video, the image sensor IS has the number of pixels capable of capturing an 8K color image. For example, if one pixel consists of one red (R) sub-pixel, one green (G) sub-pixel, and one blue (B) sub-pixel, then the image sensor IS has at least 7680×4320× pixels. 3 [R, G, B] sub-pixels are required, and in the case of a 4K imaging device, the number of sub-pixels of the image sensor IS is at least 3840×2160×3. If so, the number of sub-pixels is at least 1920×1080×3.

The image sensor IS has a function of acquiring imaging data. The image processing circuit PP1 has a function of performing image processing (noise removal, interpolation processing, gamma correction, dimming, toning, etc.) on the captured image data to generate image data 31 . The image data 31 can be output to the image recognition circuit PR and the encoder AIE which the transmission device 12 has.

The image recognition circuit PR has a function of extracting features of the image data 31, performing image recognition, and sorting the image data 31 according to attributes. The image recognition circuit PR can sort the image data 31 according to objects included in the image data 31, such as animals, plants, and man-made objects. Further, the image recognition circuit PR may sort animals into dogs, cats, horses, and the like, for example. Further, the image recognition circuit PR may further sort dogs according to their breed, for example. Information indicating which attribute the image data 31 belongs to can be called attribute information 32 . The image recognition circuit PR has a function of generating attribute information 32 . Although the details will be described later, the image recognition circuit PR can have a function of sorting the image data 31 by supervised learning, for example.

The encoder AIE has a function of receiving the attribute information 32 from the image recognition circuit PR and compressing the image data 31 based on the attribute information 32 . Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning, and the weighting factor is stored in a memory provided in the encoder AIE. When the attribute information 32 is received, the weighting factor corresponding to the attribute information 32 is read out from the memory, and arithmetic processing is performed using the weighting factor read out from the memory and the data corresponding to the image data 31 . This allows the encoder AIE to have a circuit configuration corresponding to the attributes of the image data 31 and compress the image data 31 to generate the compressed image data 33 . The compressed image data 33 and attribute information 32 can be transmitted to the decoder AID of the receiving device 13 .

The transmitting device 12 has a function of adding broadcast control data (for example, data for authentication) to the image data 31, encryption processing, scrambling processing (data rearrangement processing for spread spectrum), and the like. may have. The function can be provided, for example, by the encoder AIE of the transmitting device 12 . The transmitting device 12 may also have a function of IQ-modulating (quadrature amplitude modulation) the compressed image data 33 and outputting it to the receiving device 13 . For example, the transmitter 12 may be provided with a modulator, and the compressed image data 33 may be IQ-modulated by the modulator.

The decoder AID has a function of decompressing the compressed image data 33 based on the attribute information 32 and restoring the image data 31 . Specifically, for example, a weighting factor corresponding to each attribute is acquired in advance by learning, and the weighting factor is stored in a memory provided in the decoder AID. When the attribute information 32 is received, the weighting factor corresponding to the attribute information 32 is read out from the memory, and arithmetic processing is performed using the weighting factor read out from the memory and the data corresponding to the compressed image data 33 . As a result, the decoder AID has a circuit configuration corresponding to the attributes of the image data 31 , and the compressed image data 33 can be decompressed to restore the image data 31 .

Note that the decoder AID may receive the attribute information 32 from the image recognition circuit PR. In this case, the image recognition circuit PR may be provided in the receiving device 13 . Moreover, both the transmitting device 12 and the receiving device 13 may be provided with an image recognition circuit. In this case, for example, the image recognition circuit of the receiving device 13 may receive the attribute information from the image recognition circuit of the transmitting device 12 and transmit the attribute information to the decoder AID.

Further, the receiving device 13 may have a function of executing various processes on the compressed image data 33, for example. This processing includes frame separation, decoding of LDPC (Low Density Parity Check) code, separation of broadcast control data, descrambling processing, and the like. A decoder AID provided in the receiving device 13, for example, can have the function of performing such processing. Further, when the compressed image data 33 is IQ-modulated by a modulator or the like of the transmitting device 12, the receiving device 13 has a function of demodulating the IQ-modulated compressed image data 33. FIG. For example, a demodulator can be provided in the receiver 13 and demodulation can be performed by the demodulator.

The decoder AID can send the restored image data 31 to the image processing circuit PP2 of the display device 14 . The image processing circuit PP2 has a function of applying image processing (noise removal, interpolation processing, gamma correction, dimming, toning, etc.) to the image data 31 and transmitting the processed data to the display unit PA. Pixels are arranged in a matrix on the display portion PA, and the pixels receive the image data 31, whereby the display portion PA can display an image.

Note that a pixel provided in the display portion PA includes a display element. As the display element, for example, a transmissive liquid crystal element, a reflective liquid crystal element, an organic EL element, or the like can be used.

In one aspect of the present invention, the image recognition circuit PR sorts the image data 31 according to attributes, and the autoencoder 20 compresses and decompresses the image data 31 using the attribute information 32 resulting from the sorting. As a result, the circuit configuration of the autoencoder 20 can be made simpler than when compressing and decompressing the image data 31 without using the attribute information 32, and highly accurate compression and decompression can be performed. As a result, the autoencoder 20 can compress and decompress the image data 31 with high accuracy while reducing the number of parameters required for the compression and decompression. In addition, highly accurate compression and decompression can be performed while operating the autoencoder 20 at high speed. One aspect of the present invention is particularly effective when the display device 14 has a function of displaying extremely high resolution such as 2K, 4K, or 8K.

FIG. 2 is a modification of the broadcasting system 10 shown in FIG. 1, and differs from the configuration shown in FIG. 1 in that the autoencoder 20 has an external memory EM1 and an external memory EM2. The external memory EM1 is provided in the transmitting device 12 and the external memory EM2 is provided in the receiving device 13 . In this case, weighting coefficients are held in the external memory EM1 and the external memory EM2. The external memory EM1 has a function of receiving attribute information 32 from the image recognition circuit PR and transmitting weighting coefficients corresponding to the attribute information 32 to the encoder AIE. The external memory EM2 has a function of receiving attribute information 32 from the encoder AIE and transmitting weighting coefficients corresponding to the attribute information 32 to the decoder AID. By configuring the autoencoder 20 as shown in FIG. 2, the memory capacity of the encoder AIE and the memory capacity of the decoder AID can be reduced. This allows the encoder AIE and decoder AID to be miniaturized. As the external memory EM1 and the external memory EM2, storage devices using volatile storage elements such as DRAM (Dynamic Random Access Memory) and SRAM (Static RAM), flash memory, MRAM (Magnetoresistive RAM), PRAM (Phase change RAM), ReRAM (Resistive RAM), and FeRAM (Ferroelectric RAM) storage devices using non-volatile storage elements, or hard disk drives (HDD) and solid state drives (SSD) etc. can be used.

FIG. 3 schematically shows data transmission in a broadcasting system. FIG. 3 shows a route for radio waves (broadcast signals) including image data and the like transmitted from the broadcasting station 61 to reach the television receiver 60 (TV 60) in each home. The TV 60 has a receiver 13 and a display device 14 . Examples of the artificial satellite 62 include CS (communication satellite), BS (broadcasting satellite), and the like. Examples of the antenna 64 include a BS/110° CS antenna and a CS antenna. Examples of the antenna 65 include a UHF (Ultra High Frequency) antenna and the like.

Radio waves 66A and 66B are broadcast signals for satellite broadcasting. When the satellite 62 receives the radio wave 66A, it transmits the radio wave 66B toward the ground. At each home, the radio wave 66B is received by the antenna 64, and the satellite TV broadcast can be viewed on the TV 60. FIG. Alternatively, the radio wave 66B is received by an antenna of another broadcasting station and processed by a receiving device within the broadcasting station into a signal that can be transmitted over an optical cable. A broadcasting station uses an optical cable network to transmit a broadcasting signal to the TV 60 in each home. Radio waves 67A and 67B are broadcast signals for terrestrial broadcasting. The radio tower 63 amplifies the received radio wave 67A and transmits the radio wave 67B. At each home, the antenna 65 receives the radio wave 67B, so that the TV 60 can watch the terrestrial TV broadcast.

The transmitting device 12 can be provided at a broadcasting station 61, an artificial satellite 62, or a radio tower 63, for example. The receiving device 13 can be provided in the TV 60, for example, as described above. Moreover, you may provide the receiver 13 in the exterior of TV60.

Also, the broadcasting system of the present embodiment is not limited to a system for TV broadcasting. Image data to be distributed may be moving image data or still image data.

<Example of learning method>
Next, an example of a learning method in the image recognition circuit PR and the autoencoder 20 will be described with reference to FIG. FIG. 4 is a flow chart showing an example of a learning method in the image recognition circuit PR and the autoencoder 20. As shown in FIG.

First, image data is input to the image recognition circuit PR, and the image recognition circuit PR performs learning. This enables the image recognition circuit PR to output the attribute information 32 corresponding to the attribute of the image data (step S01). For example, the image recognition circuit PR can learn by supervised learning. Specifically, for example, when sorting image data into animals, plants, and man-made objects, image data to be recognized as animals is input to the image recognition circuit PR, and an answer of animals is prepared as teacher data. Subsequently, a weighting factor in the image recognition circuit PR is set so that the image data is recognized as an animal. Also, image data to be recognized as plants is inputted to the image recognition circuit PR, and the answer "plants" is prepared as teacher data. Subsequently, the weight coefficient in the image recognition circuit PR is updated so that the image data is recognized as a plant. Furthermore, next, image data to be recognized as an artifact is input to the image recognition circuit PR, and the answer "artifact" is prepared as teaching data. Subsequently, the weighting coefficient in the image recognition circuit PR is updated so that the image data is recognized as an artifact. As described above, the weight coefficients in the image recognition circuit PR can be set so that the image data can be appropriately sorted and the appropriate attribute information 32 can be output. Although the details will be described later, when supervised learning is performed, for example, learning by the error backpropagation method can be performed. In addition, in order to suppress learning with biased data, image data with attributes of the same type are not continuously input to the image recognition circuit PR, but the types of attributes are randomized and the image data is processed as an image. It is preferably input to the recognition circuit PR. For example, when sorting image data into animals, plants, and artifacts, it is preferable to randomly input animal image data, plant image data, and artifact image data to the image recognition circuit PR.

In this specification and the like, the image recognition circuit PR is assumed to have a function of sorting image data into n types of attributes (attribute [1] to attribute [n]) (where n is an integer equal to or greater than 2). For example, n=3 when the image recognition circuit PR sorts image data into animals, plants, and artifacts. In this case, for example, animals can be attribute [1], plants can be attribute [2], and artificial objects can be attribute [3].

Next, a variable i is prepared and set to 1, and the image recognition circuit PR and the encoder AIE receive the image data of the attribute [i] (steps S02 and S03). After that, the image recognition circuit PR transmits the attribute information 32 of attribute [i] to the encoder AIE and the decoder AID (step S04). In this specification and the like, the attribute information 32 of attribute [i] is represented as attribute information 32[i].

Next, based on the attribute [i] image data and the attribute information 32[i], the autoencoder 20, that is, the encoder AIE and the decoder AID perform learning to acquire learning data (step S05). Note that the learning data includes, for example, weighting coefficients. Also, the learning can be, for example, unsupervised learning. After that, the variable i is incremented by 1 (step S06).

Next, it is determined whether or not the variable i is greater than n (step S07). If the variable i is less than or equal to n, steps S03 to S07 are executed again. When the variable i is greater than n, it is assumed that the autoencoder 20 has completed learning, that is, it can appropriately compress and decompress any image data of attribute [1] to attribute [n], and the learning operation is performed. exit. The above is an example of the learning operation in the autoencoder 20 .

The learning operation shown in FIG. 4 can actually be performed by a server or the like provided outside the broadcasting system 10 . Specifically, the image processing circuit PR, the encoder AIE, and the decoder AID are modeled in the server or the like, and learning is performed using the model. After the learning is completed, the learning result, that is, the learning data such as the weighting coefficient is transmitted from the server or the like to the image recognition circuit PR, the encoder AIE, and the decoder AID. As described above, the image processing circuit PR, the encoder AIE, and the decoder AID can perform learning.

<Example of operation method of each device in the broadcasting system>
Next, an example of an operation method of each device constituting the broadcasting system 10 after the image recognition circuit PR and the autoencoder 20 have learned will be described with reference to FIG. FIG. 5 is a flow chart showing an example of an operation method of each device constituting the broadcasting system 10. As shown in FIG.

First, the imaging device 11 generates the image data 31 and transmits it to the image recognition circuit PR and the encoder AIE of the transmission device 12 . Specifically, the imaging data is acquired by the image sensor IS of the imaging device 11, and the image data 31 is generated by performing image processing and the like on the imaging data by the image processing circuit PP1 (step S11). .

Next, the image recognition circuit PR extracts features of the image data 31 to perform image recognition, and generates attribute information 32 corresponding to the attributes of the image data 31 . That is, when the image data 31 is image data with attribute [i], attribute information 32[i] is generated. The generated attribute information 32 is sent to the encoder AIE (step S12).

Next, the encoder AIE compresses the image data 31 based on the attribute information 32 to generate compressed image data 33 (step S13). For example, the encoder AIE generates compressed image data 33 by performing arithmetic processing using weighting coefficients corresponding to attribute information 32 and data corresponding to image data 31 . After that, the decoder AID receives the compressed image data 33 and the attribute information 32 from the encoder AIE (step S14).

After that, the decoder AID decompresses the compressed image data 33 based on the attribute information 32 and restores the image data 31 . For example, the decoder AI restores the image data 31 by performing arithmetic processing using weighting factors corresponding to the attribute information 32 and data corresponding to the compressed image data 33 . The restored image data 31 is transmitted to the display device 14 (step S15). Specifically, the restored image data 31 is transmitted to the image processing circuit PP2 included in the display device 14, and image processing and the like are performed. After that, an image corresponding to the image data 31 is displayed on the display part PA.

Then, the process returns to step S11. That is, the imaging device 11 generates the image data 31 and transmits it to the image recognition circuit PR and the encoder AIE of the transmission device 12 . An example of the operation method of each device constituting the broadcasting system 10 has been described above.

Even after the image recognition circuit PR and the autoencoder 20 have learned according to the procedure shown in FIG. 4 and have been operated according to the procedure shown in FIG. 5, the learning may be carried out again. For example, in order to increase the number of types of attribute information 32 that can be output by the image recognition circuit PR, the image recognition circuit PR may learn, and the autoencoder 20 may learn accordingly. This allows the autoencoder 20 to perform compression and decompression with higher precision.

<Configuration Example of Circuit Using Neural Network>
Next, configuration examples of the image recognition circuit PR and the autoencoder 20, which are circuits using a neural network, will be described with reference to the drawings. FIG. 6 is a configuration example of the image recognition circuit PR. Note that FIG. 6 also shows an image processing circuit PP1 and an encoder AIE in addition to the image recognition circuit PR.

The image recognition circuit PR has an input layer IL1, an intermediate layer ML1[1], an intermediate layer ML1[2], and an output layer OL1. That is, in the image recognition circuit PR, a hierarchical neural network is configured by the input layer IL1, the intermediate layer ML1[1], the intermediate layer ML1[2], and the output layer OL1.

Image data 31 sent from the image processing circuit PP1 is input to the input layer IL1 of the image recognition circuit PR. That is, the image data 31 is treated as input data for a hierarchical neural network. A hierarchical neural network will be described later.

The hierarchical neural network in the image recognition circuit PR is configured such that the number of neurons decreases as the hierarchy progresses. In other words, the number of neurons in the intermediate layer ML1[1] is smaller than the number of neurons in the input layer IL1, and the number of neurons in the intermediate layer ML1[2] is less than the number of neurons in the intermediate layer ML1[1]. less than the number of Furthermore, the number of neurons that the output layer OL1 has is smaller than the number of neurons that the intermediate layer ML1[2] has. In FIG. 6, the number of neurons is indicated by the number of arrows connecting layers. By configuring the image recognition circuit PR so that the number of neurons decreases as the hierarchy progresses, it is possible to perform feature extraction of the image data 31 and generate attribute information 32 corresponding to the attributes of the image data 31 . Also, although the configuration in which the number of neurons gradually decreases has been shown here, the configuration of the neural network is not limited to this. The number of neurons in the intermediate layer may increase, or the number of neurons may remain unchanged.

FIG. 7 is a configuration example of the autoencoder 20. As shown in FIG. In addition to the autoencoder 20, FIG. 7 also shows the image processing circuit PP1 and the image processing circuit PP2. Also in FIG. 7, similarly to FIG. 6, the number of neurons in each layer is indicated by the number of arrows connecting the respective layers.

The encoder AIE that the autoencoder 20 has has an input layer IL2, an intermediate layer ML2[1], and an intermediate layer ML2[2], and the decoder AID that the autoencoder 20 has has an intermediate layer ML2[3] and , an intermediate layer ML2[4] and an output layer OL2. In other words, in the autoencoder 20, the input layer IL2, the intermediate layers ML2[1] to ML2[4], and the output layer OL2 form a hierarchical neural network.

The image data 31 sent from the image processing circuit PP1 is input to the input layer IL2 of the encoder AIE that the autoencoder 20 has. That is, the image data 31 is treated as input data for a hierarchical neural network. A hierarchical neural network will be described later.

The hierarchical neural network in the encoder AIE is configured such that the number of neurons decreases as the hierarchy progresses. That is, the number of neurons in the intermediate layer ML2[1] is less than the number of neurons in the input layer IL2, and the number of neurons in the intermediate layer ML2[2] is equal to the number of neurons in the intermediate layer ML2[1]. less than the number of By configuring the encoder AIE as described above, the amount of data output from the intermediate layer ML2[2] can be reduced, ie, compressed, relative to the amount of input data.

The hierarchical neural network in the decoder AID is configured such that the number of neurons increases as the hierarchy progresses. That is, the number of neurons possessed by the intermediate layer ML2[4] is greater than the number of neurons possessed by the intermediate layer ML2[3], and the number of neurons possessed by the output layer OL2 is greater than the number of neurons possessed by the intermediate layer ML2[4]. more than the number of

The encoder AIE, as a circuit configuration corresponding to the attribute information 32, extracts features of the image data 31, compresses the image data 31 based on the attribute information 32, and generates compressed image data 33. FIG. The decoder AID restores the compressed image data 33, which is the feature-extracted image data, to the image data 31, and outputs the image data 31 from the output layer OL2.

Note that in the hierarchical neural network configured by the image recognition circuit PR and the hierarchical neural network configured by the autoencoder 20, each layer can be fully connected, or a convolution layer or pooling can be performed between each layer. It can be a layered configuration, or CNN.

Also, the number of intermediate layers in the image recognition circuit PR and the number of intermediate layers in the autoencoder 20 are not limited and can be provided as required. Furthermore, the numbers of neurons that the input layer, intermediate layer, and output layer in the image recognition circuit PR have are not limited to the numbers shown in FIG. 6, and may be provided as required. Also, the numbers of neurons that the input layer, intermediate layer, and output layer in the autoencoder 20 have are not limited to the numbers shown in FIG. 7, and any number can be provided as required.

As described above, according to one aspect of the present invention, the circuit configuration of the autoencoder 20 can be simplified while highly accurate compression and decompression can be performed. Here, simplifying the circuit configuration of the autoencoder 20 means, for example, reducing the number of intermediate layers that the autoencoder 20 has. Alternatively, it means reducing the number of neurons in each layer that the autoencoder 20 has, for example.

<Hierarchical neural network>
Next, a hierarchical neural network will be described as one type of neural network that can be used for the image recognition circuit PR and the autoencoder 20. FIG.

FIG. 8 is a diagram showing an example of a hierarchical neural network. The (k-1)-th layer (where k is an integer of 2 or more) has P neurons (where P is an integer of 1 or more), and the k-th layer has neurons (where Q is an integer of 1 or more), and the (k+1)-th layer has R neurons (here, R is an integer of 1 or more).

The product of the output signal z _p ^(k-1) of the p-th neuron in the (k-1) layer (where p is an integer of 1 or more and P or less) and the weighting factor w _qp ^(k) is Input to the q-th neuron of the k-th layer (where q is an integer of 1 or more and Q or less), and the output signal z _q ^(k) of the q-th neuron of the k-th layer and the weight coefficient w _rq The product of (k+1 ⁾ and is input to the r-th neuron of the (k+1)-th layer (where r is an integer of 1 or more and R or less), and the r-th neuron of the (k+1)-th layer Let the output signal be z _r ^(k+1) .

At this time, the total sum u _q ^(k) of signals input to the q-th neuron in the k-th layer is expressed by the following equation.

Also, the output signal z _q ^(k) from the q-th neuron in the k-th layer is defined by the following equation.

The function f(u _q ^(k) ) is an activation function, and can be a step function, linear ramp function, sigmoid function, or the like. Note that the sum-of-products operation of equation (1) can be realized by a sum-of-products operation circuit, which will be described later. Note that the calculation of expression (2) can be realized, for example, by a circuit 161 shown in FIG. 11(A).

Note that the activation function may be the same or different in all neurons. Additionally, the activation function may be the same or different from layer to layer.

Here, consider a hierarchical neural network composed of all L layers (where L is an integer of 3 or more) shown in FIG. That is, k here is an integer of 2 or more and (L-1) or less. The first layer is the input layer of the hierarchical neural network, the Lth layer is the output layer of the hierarchical neural network, and the second to (L-1)th layers are intermediate layers.

The first layer (input layer) has P neurons, the k-th layer (intermediate layer) has Q[k] neurons (Q[k] is an integer equal to or greater than 1), and the The L layer (output layer) has R neurons.

Let z _{s [1]} ⁽¹⁾ be the output signal of the s[1]-th neuron in the first layer (s[1] is an integer greater than or equal to P and less than or equal to P), and the s[k]-th neuron in the k-th layer (s[k] is an integer from 1 to Q[k]) is defined as z _s[k] ^(k) , and the s[L]-th neuron in the L-th layer (s[L] is 1 is an integer equal to or greater than R and equal to or less than R) is assumed to be z _s[L] ^(L) .

Also, the output signal z _{s[k-1 ]} ^(k−1) and the weighting factor w _s[k]s[k−1] ^(k) , u _s[k] ^(k) is input to the s[k]-th neuron of the k-th layer. Assume that the output signal z _{s[L- 1]} ^(L−1) and the weighting coefficient w _s[L]s[L−1] ^(L) , u _s[L] ^(L) is input to the s[L]-th neuron in the L-th layer. shall be

Next, supervised learning will be explained. Supervised learning is when the output result differs from the desired result (sometimes referred to as teacher data or teacher signal) in the function of the hierarchical neural network described above, the hierarchical neural network This refers to the operation of updating all weighting factors based on output results and desired results.

As a specific example of supervised learning, a learning method using backpropagation will be described. FIG. 10 is a diagram for explaining a learning method based on the error backpropagation method. The error backpropagation method is a method of changing weighting coefficients so as to reduce the error between the output of a hierarchical neural network and teacher data.

For example, assume that input data is input to the s[1]-th neuron in the first layer and output data z _s[L] ^(L) is output from the s[L]-th neuron in the L-th layer. Here, when the teacher signal for the output data zs _[L] ^(L) is _ts[L] ^(L) , the error energy E is the output data zs _[L] ^(L) and the teacher signal ts _{[ L]} can be represented by ^(L) .

For the error energy E, the update amount of the weight coefficient w _s[k]s[k−1] ^(k) of the s[k]-th neuron in the k-th layer is ∂E/∂w _{s[k]s[k −1]} ^(k) , the weighting factor can be newly changed. Here, if the error δ _s[k] ^(k) of the output value z _s[k] ^(k) of the s[k]-th neuron in the k-th layer is defined as ∂E/∂u _s[k] ^(k) , δ _s[k] ^(k) and ∂E/∂w _s[k]s[k−1] ^(k) can be expressed by the following equations, respectively.

f'(u _s[k] ^(k) ) is the derivative of the activation function. Note that the calculation of expression (3) can be realized, for example, by a circuit 163 shown in FIG. 11(B). Also, the calculation of equation (4) can be realized by, for example, a circuit 164 shown in FIG. 11(C). The derivative of the activation function can be realized, for example, by connecting an operational circuit corresponding to the desired derivative to the output terminal of the operational amplifier.

Further, for example, the calculation of the portion Σδ _s[k+1] ^(k+1) ·w _s[k+1]·s[k] ^(k+1) in Equation (3) can be realized by a sum-of-products operation circuit to be described later.

where δ _s[L] ^(L) and ∂E/∂w _{s[L]s[L −1]} ^(L) can be represented by the following equations.

The calculation of equation (5) can be implemented by circuit 165 shown in FIG. 11(D). Also, the calculation of equation (6) can be realized by a circuit 164 shown in FIG. 11(C).

In other words, the errors δ _s[k] ^(k) and δ _s[L] ^(L) of all neuron circuits can be obtained from equations (1) to (6). The update amount of the weighting coefficient is set based on the errors δ _s[k] ^(k) , δ _s[L] ^(L) , desired parameters, and the like.

As described above, by using the circuits shown in FIGS. 11A to 11D and a sum-of-products operation circuit to be described later, hierarchical neural network calculations to which supervised learning is applied can be performed.

<Example of circuit configuration of hierarchical neural network>
FIG. 12 is a block diagram showing a circuit configuration example of a hierarchical neural network.

An NN (neural network) circuit 100 has input terminals PDL[1] through input terminals PDL[l] (where l is an integer equal to or greater than 1), and output terminals PDR[1] through output terminals PDR[v]. (where v is an integer of 1 or more), programmable logic elements PLE[1] to PLE[m] (where m is an integer of 1 or more), wiring L[1] to wiring L[l], wiring P[1] to wiring P[m], wiring R[1] to wiring R[v], wiring Q[1] to wiring Q[m], a plurality of programmable switches PSW1, a plurality of of programmable switches PSW2 and a plurality of programmable switches PSW3.

Note that in the NN circuit 100 shown in FIG. 12, the input terminal PDL[1], the input terminal PDL[2], the input terminal PDL[l], the output terminal PDR[1], the output terminal PDR[2], the output terminal PDR[ v], programmable logic element PLE[1], programmable logic element PLE[2], programmable logic element PLE[m], wiring L[1], wiring L[2], wiring L[l], wiring P[1] , wiring P[2], wiring P[m], wiring R[1], wiring R[2], wiring R[v], wiring Q[1], wiring Q[2], wiring Q[m], programmable Only the switch PSW1, the programmable switch PSW2, the programmable switch PSW3, and a switch circuit SWC, which will be described later, are shown, and other circuits, elements, wiring, and symbols are omitted.

That is, one embodiment of the present invention is a multi-context programmable processing device using programmable logic elements PLE[1] to PLE[m] and programmable switches PSW1 to PSW3. As will be described in detail later, in the hierarchical neural network, the arithmetic processing unit associates the connection state of the network between the layers with each context, and by sequentially switching the context, the arithmetic processing of the neural network is performed. conduct.

The input terminal PDL[i] (where i is an integer greater than or equal to 1 and less than or equal to l) is electrically connected to the wiring L[i]. The output terminal PDR[k] (where k is an integer of 1 or more and v or less) is electrically connected to each of the wirings R[1] to R[v] via the programmable switch PSW3. It is A first terminal of the programmable logic element PLE[j] (here, j is an integer of 1 or more and m or less) is electrically connected to the wiring Q[j], and the wiring Q[j] is connected to the wiring. It is electrically connected to each of L[1] to wiring L[l] via a programmable switch PSW1. Further, the wiring Q[j] is electrically connected to each of the wirings P[1] to P[m] through the programmable switch PSW2. A second terminal of the programmable logic element PLE[j] is electrically connected to the wiring R[j]. The wirings P[1] to P[m] are electrically connected to the wirings R[1] to R[v], respectively.

The programmable switches PSW1 to PSW3 included in the NN circuit 100 are switches that can switch between a conducting state and a non-conducting state according to data stored in a memory MS, which will be described later. Each of the programmable switches PSW1 to PSW3 has a switch circuit SWC. Details of the programmable switches PSW1 to PSW3 will be described later.

The programmable logic element PLE has an arithmetic processing circuit. FIG. 13A is a circuit diagram showing a configuration example of the arithmetic processing circuit 150 included in the NN circuit 100 provided in the autoencoder 20. FIG. The arithmetic processing circuit 150 includes a controller CNT, product operation circuits MAC[1] to product operation circuits MAC[s] (s is an integer equal to or greater than 2), an addition circuit AD, an activation function circuit AFC, and a memory MF. , and a holding circuit KC. The product operation circuit MAC[h] (h is an integer from 1 to s) includes a multiplication circuit MLT[h], a memory MW[h](1) to a memory MW[h](t), and a multiplexer MUX1[h ] and Note that t can be an integer equal to or greater than n. That is, the product operation circuit MAC[h] has memories MW[h] equal to or greater than the number of types of attribute information 32 that can be output by the image recognition circuit PR. Here, memory MW[h](1) to memory MW[h](t) may be collectively referred to as memory MW[h].

Note that when the autoencoder 20 is configured as shown in FIG. 2, t can be an integer smaller than n. That is, the number of memories MW[h] that the product operation circuit MAC[h] has can be made smaller than the number of types of attribute information 32 that can be output by the aforementioned image recognition circuit PR.

In this specification and the like, the memories MW[h](1) to MW[h](t) may be collectively referred to as a group of memories. In this specification and the like, the memories MW[h](1) to MW[h](t) are sometimes referred to as memory elements. That is, it can be said that the product operation circuit MAC[h] has a group of memories composed of memories MW[h](1) to MW[h](t), which are memory elements.

Note that FIG. 13A only shows the function of the arithmetic processing circuit 150, and the circuits shown in FIG. 13A do not necessarily have to be provided as separate circuits. For example, the memory MW[h](1) to memory MW[h](t) included in the product operation circuit MAC[h] can have the function of the multiplication circuit MLT[h], although the details will be described later. That is, it is not necessary to provide a circuit separate from the memory MW[h](1) to the memory MW[h](t) as the multiplication circuit MLT[h]. Alternatively, for example, the multiplexers MUX1[1] through MUX1[s] may not be provided in the product operation circuits MAC[1] through MAC[s]. In this case, for example, the controller CNT can function as multiplexers MUX1[1] to MUX1[s]. It should be noted that in the circuit diagrams that follow, there are cases in which the illustrated circuits do not necessarily have to be provided as separate circuits.

Attribute information 32 is input to the controller CNT. The controller CNT is also electrically connected to the selection signal input terminals of the multiplexers MUX1[1] to MUX1[s]. The memory MW[h](1) to memory MW[h](t) are electrically connected to the input terminal of the multiplexer MUX1[h]. The output terminal of the multiplexer MUX1[h] is electrically connected to the first input terminal of the multiplication circuit MLT[h].

The input terminal In[h] is electrically connected to the second input terminal of the multiplier circuit MLT[h], and the output terminal of the multiplier circuit MLT[h] is electrically connected to the input terminal of the adder circuit AD. ing. An output terminal of the addition circuit AD is electrically connected to an input terminal of the activation function circuit AFC. The output terminal of activation function circuit AFC is electrically connected to terminal TA1 of holding circuit KC. A terminal TA2 of the holding circuit KC is electrically connected to the output terminal OUT.

Multiplication circuit MLT[h] uses one of the data (hereinafter sometimes referred to as weighting coefficients) held in memory MW[h](1) to memory MW[h](t) as a multiplier. , is a circuit that performs multiplication using the data input to the input terminal In[h] as the multiplicand. The data can be data corresponding to image data, for example. The multiplier in the multiplication circuit MLT[h], that is, the memory MW[h] holding the data output from the multiplexer MUX[h] is selected by the controller CNT based on the attribute information 32 . For example, if the image recognition circuit PR sorts the image data into attributes [1] to [t], the attribute information 32[i] (where i is an integer from 1 to t) is sent to the controller CNT. If so, the controller CNT can select memory MW[h](i).

The addition circuit AD is a circuit that calculates the sum of the multiplication results output from the multiplication circuits MLT[1] to MLT[s]. In other words, the sum-of-products operation circuit is composed of the multiplication circuits MLT[1] to MLT[s] and the addition circuit AD.

The activation function circuit AFC is a circuit that performs an operation according to a function system defined by the data held in the memory MF on the signal input to the input terminal, that is, the sum-of-products operation result. As the function system, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, and the like can be used.

The holding circuit KC has a function of acquiring the calculation result output from the activation function circuit AFC from the terminal TA1, temporarily holding the calculation result, and a function of outputting the temporarily held calculation result to the terminal TA2. have In addition, the holding circuit KC can switch between the above two functions according to the clock signal CLK input to the terminal CKT.

For example, when the pulse of the clock signal CLK is high level potential, the holding circuit KC can hold the potential input from the terminal TA1, and when the pulse of the clock signal CLK is low level potential, the holding circuit KC can hold the potential input from the terminal TA1. can output the potential from the terminal TA2 to the output terminal OUT.

If the arithmetic processing circuit 150 is a circuit that handles digital data, a flip-flop circuit, for example, can be applied to the holding circuit KC.

Further, when the arithmetic processing circuit 150 is a circuit that handles analog data, as an example, a holding circuit KC illustrated in FIG. 13B can be applied. A holding circuit KC illustrated in FIG. 13B is a sample-and-hold circuit and includes a transistor TrA, a transistor TrB, a capacitor CA, an amplifier AMP, and a NOT circuit NL.

One of the source and the drain of the transistor TrA is electrically connected to the terminal TA1, the other of the source and the drain of the transistor TrA is electrically connected to one of the pair of electrodes of the capacitor CA, and the gate of the transistor TrA is , and the terminal CKT. The input terminal of the amplifier AMP is electrically connected to the other of the source and drain of the transistor TrA, and the output terminal of the amplifier AMP is electrically connected to one of the source and drain of the transistor TrB. The other of the source and drain of the transistor TrB is electrically connected to the terminal TA2. The input terminal of the NOT circuit NL is electrically connected to the terminal CKT, and the output terminal of the NOT circuit NL is electrically connected to the gate of the transistor TrB. The other of the pair of electrodes of the capacitor CA is electrically connected to the wiring GNDL. Note that a node N is a node to which the other of the source or drain of the transistor TrA, the input terminal of the amplifier AMP, and one of the pair of electrodes of the capacitor are connected.

The amplifier AMP has a function of amplifying a signal input to an input terminal by 1 and outputting the amplified signal to an output terminal.

A wiring GNDL is a wiring for applying a reference potential.

When the pulse of the clock signal CLK input to the terminal CKT is at a high level potential, the transistor TrA becomes conductive and the transistor TrB becomes non-conductive. At this time, the signal input from the terminal TA1 is input to the amplifier AMP via the transistor TrA. Therefore, the amplifier AMP amplifies the signal and outputs the amplified signal from the output terminal of the amplifier AMP. Since the transistor TrB is in a non-conducting state, the amplified signal is not output from the terminal TA2.

Further, the potential of the node N is held by the capacitor CA. At this time, the potential of the node N becomes the potential of the signal input from the terminal TA1.

When the pulse of the clock signal CLK input to the terminal CKT is at the low level potential, the transistor TrA becomes non-conductive and the transistor TrB becomes conductive. The potential of the node N does not change because the transistor TrA is in a non-conducting state. The amplifier AMP outputs the potential of the node N to one of the source and drain of the transistor TrB. Since the transistor TrB is in a conducting state, the potential of the node N, ie, the potential of the signal input from the terminal TA1 when the pulse of the clock signal CLK is at a high level potential, is output from the terminal TA2.

The transistor TrA and/or the transistor TrB are preferably OS transistors. In particular, the OS transistor preferably uses a metal oxide containing at least one of indium, element M (element M is aluminum, gallium, yttrium, or tin), and zinc for the channel formation region. By applying such an OS transistor to the transistor TrA and/or the transistor TrB, the off-state current of the transistor can be significantly reduced. Therefore, the influence of charge leakage due to the off-state current of the transistor can be reduced.

Note that the holding circuit KC of the product-sum operation circuit 150 included in the semiconductor device of one embodiment of the present invention is not limited to the above structure. Depending on the case or situation, the configuration of the holding circuit KC can be changed as appropriate.

The memory MW[1] to memory MW[s] and the memory MF included in the arithmetic processing circuit 150 and the memory MS for setting the states of the programmable switches PSW1 to PSW3 to be described later are driven by different drive circuits. may be written. That is, without updating the data in the memory MS, the data in the memory MW[1] to memory MW[s] of the sum-of-products operation circuit 150 and the memory MF can be repeatedly updated. This enables efficient learning in the neural network.

In the above description, one programmable logic element has a single arithmetic processing circuit 150. However, a plurality of programmable logic elements and programmable switches connecting between the programmable logic elements can be used to form one sum-of-products arithmetic circuit. It is also possible to configure

13A, the controller CNT and the multiplexers MUX1[1] to MUX1[s] are omitted, and each product operation circuit MAC has one memory MW. Thus, it can be an arithmetic processing circuit included in the image recognition circuit PR. In this case, one memory MW is electrically connected to the first input terminal of one multiplier circuit MLT.

Next, configurations of the programmable switches PSW1 to PSW3 will be described. FIG. 14A shows a connection example of the wiring Q[j], the programmable switch PSW1, the programmable switch PSW2, and the programmable logic element PLE[j] in the NN circuit 100, and FIG. , and a configuration example of the switch circuit SWC.

Note that in FIG. 14A, the wiring Q[j] is composed of wirings q[1] to q[s]. Furthermore, in FIG. 14A, the first terminal of the programmable logic element PLE[j] serves as the input terminal In[1] to the input terminal In[s] of the arithmetic processing circuit 150 described in FIG. 13A. there is That is, in FIG. 14A, the wiring q[h] is electrically connected to the input terminal In[h].

Further, in FIG. 14A, the wiring q[1] to the wiring q[s] are electrically connected to the wiring "0" through the programmable switch PSW1. A wiring "0" is a wiring for supplying a signal with a value of 0 (the potential of the signal is the reference potential).

In the configuration example shown in FIG. 14A, the programmable switch PSW1 and the programmable switch PSW2 have switch circuits SWC. FIG. 14B shows a configuration example of the switch circuit SWC that the autoencoder 20 has. The switch circuit SWC has a switch SW, a controller CNT, memories MS(1) to MS(t), and a multiplexer MUX2. As noted above, t can be an integer greater than or equal to n. In other words, the switch circuit SW has memories MS that are equal to or greater than the number of types of attribute information 32 that can be output by the aforementioned image recognition circuit PR.

Note that when the autoencoder 20 is configured as shown in FIG. 2 as described above, t can be set to a smaller integer. That is, the number of memories MS included in one switch circuit SWC can be made smaller than the number of types of attribute information 32 that can be output by the image recognition circuit PR.

A first terminal of the switch SW is electrically connected to the wiring q[h], and a second terminal of the switch SW is electrically connected to the wiring X. Note that the wiring X is any one of the wiring “0”, the wirings L[1] to L[l], and the wirings P[1] to P[m].

As described above, the attribute information 32 is input to the controller CNT. The controller CNT is also electrically connected to the selection signal input terminal of the multiplexer MUX2. The memories MS(1) to MS(t) are electrically connected to the input terminals of the multiplexer MUX2. The switch SW determines a conducting state or a non-conducting state according to data held in one of the memories MS(1) to MS(t). Data to be output to the switch SW is selected by the controller CNT based on the attribute information 32 . That is, one of the memories MS( 1 ) to MS(t) is selected by the controller CNT based on the attribute information 32 . For example, if the image recognition circuit PR sorts the image data into attributes [1] to [t], the attribute information 32[i] (where i is an integer from 1 to t) is sent to the controller CNT. If so, the controller CNT can select memory MS(i).

Each of the programmable switch PSW1 and the programmable switch PSW2 shown in FIG. 14A becomes conductive or non-conductive depending on the data held in one of the memories MS(1) to MS(t). In other words, the data held in one of the memories MS(1) to MS(t) is used to select the wiring "0", the wiring L[1] to wiring L[l], the wiring P[1] to wiring P[m]. ] and each of the input terminals In[1] to In[s].

In particular, when signals are not input to some of the input terminals In[1] to In[s], the switch circuit SWC that connects some of the terminals and the wiring "0" is brought into conduction. . At this time, the power consumption of the multiplier circuits corresponding to the partial terminals can be reduced by power gating.

As the switch SW shown in FIG. 14B, for example, a switch using MEMS (micro-electro-mechanical system) technology such as a transistor, a diode, or a digital micromirror device (DMD) can be applied. can. Also, the switch SW may be a logic circuit in which transistors are combined. In the case where one transistor is used as the switch SW, it is preferable to use an OS transistor with extremely low off-state current.

In the switch circuit SWC having the configuration shown in FIG. 14B, the controller CNT and the multiplexer MUX2 are omitted, and one switch circuit SWC has one memory MS. can be a circuit.

FIG. 14C shows a connection example of the wiring R[k], the programmable switch PSW3, the programmable logic element PLE[j], and the output terminals PDR[1] to PDR[v] in the NN circuit 100. showing.

Note that in FIG. 14C, the wiring R[k] is composed of the wirings r[1] to r[c]. Further, in FIG. 14C, the second terminals of the programmable logic element PLE[j] are designated as terminals O[1] to O[e] (where e is an integer of 1 or more). showing. That is, in FIG. 14C, the wiring r[k] is electrically connected to the terminal O[k]. Note that although a plurality of second terminals are shown in FIG. 14C, one terminal may be provided.

In the configuration example shown in FIG. 14C, the programmable switch PSW3 has a switch circuit SWC. That is, similarly to the programmable switches PSW1 and PSW2, the data held in one of the memories MS(1) to MS(t) determines the conductive state or non-conductive state of the switch SW included in the switch circuit SWC. can do. Therefore, it is possible to control whether or not each of the terminals O[1] to O[e] is connected to each of the output terminals PDR[1] to PDR[v] according to the data in the memory MS. can.

By the way, SRAM, MRAM, etc. can be applied to the memory MS, the memory MW, and the memory MF described above, for example. Alternatively, for example, a memory device using an OS transistor (referred to as an OS memory in this specification and the like) can be applied. In particular, by applying an OS memory as the memory described above, a neural network with a small number of elements and low power consumption can be configured.

Here, consider a case where the NN circuit 100 is applied to each of the encoder AIE and the decoder AID of the autoencoder 20. FIG. The autoencoder 20 shown in FIG. 15 has a configuration example in which an NN circuit 100A is applied as the NN circuit 100 to the encoder AIE, and an NN circuit 100B is applied as the NN circuit 100 to the decoder AID. In FIG. 15, the NN circuit 100A and the NN circuit 100B are electrically connected. In addition to the autoencoder 20, FIG. 15 also shows the image processing circuit PP1 and the image processing circuit PP2.

By the way, the encoder AIE is such that the number of neurons possessed by the hidden layers ML2[2] and ML2[3] shown in FIG. It is configured to have fewer neurons than the layer OL2 has.

Therefore, the NN circuit 100A includes input terminals PDL[1] through input terminals PDL[L] (where L is an integer equal to or greater than 1) and output terminals PDR[1] through output terminals PDR[V] ( Here, V is an integer of 1 or more and less than L.), and the NN circuit 100B includes input terminals PDL[1] to input terminals PDL[V] and output terminals PDR[1] to output terminals and PDR[L]. Further, in FIG. 15, the plurality of programmable logic elements PLE included in each of the NN circuit 100A and the NN circuit 100B are indicated as a programmable logic element section PLES1 and a programmable logic element section PLES2.

As shown in FIG. 15, the autoencoder 20 can be configured by applying the NN circuit 100 to each of the encoder AIE and the decoder AID. As a result, the image data 31 sent from the image processing circuit PP1 can be converted into the compressed image data 33, which is the feature-extracted image data, by the NN circuit 100A. In addition, the compressed image data 33 can be restored to the original image data 31 by the NN circuit 100B, and the restored image data 31 can be transmitted to the image processing circuit PP2 of the display device .

In FIG. 15, the number of input terminals PDL of NN circuit 100A and the number of output terminals PDR of NN circuit 100B are the same. , and the number of input terminals PDL of the NN circuit 100A and the number of output terminals PDR of the NN circuit 100B may be different.

<Multiplication circuit>
Next, a specific configuration example of the product operation circuit shown in FIG. 13 will be described with reference to the drawings. FIG. 16 shows product operation circuit MAC[i] and controller CNT, and wiring electrically connected to product operation circuit MAC[i] and controller CNT.

The product operation circuit MAC[i] has memories MW[i](1) to MW[i](t). A configuration example of the memory MW[i](g) (g is an integer greater than or equal to 1 and less than or equal to t) will be described below.

The memory MW[i](g) has a transistor Tr1(g), a transistor Tr2(g), a transistor Tr3(g), and a capacitive element C1(g). One of the source and drain of the transistor Tr1(g) is electrically connected to the gate of the transistor Tr2(g) and one of the pair of electrodes of the capacitor C1(g). The other of the source and drain of the transistor Tr1(g) is electrically connected to the wiring WD. A gate of the transistor Tr1(g) is electrically connected to the wiring WW(g). One of the source and drain of the transistor Tr2(g) is electrically connected to one of the source and drain of the transistor Tr3(g). The other of the source and drain of the transistor Tr2(g) is electrically connected to the wiring VSSL. The other of the source and drain of the transistor Tr3(g) is electrically connected to the wiring RD. A gate of the transistor Tr3(g) is electrically connected to the wiring SE(t). The other of the pair of electrodes of the capacitor C1(g) is electrically connected to the wiring RW. As described above, the other of the sources and drains of the transistors Tr1(1) to Tr1(t) can be electrically connected by one wiring WD. In addition, the other of the sources and drains of the transistors Tr3(1) to Tr3(t) can be electrically connected by one wiring RD.

A node to which the other of the source or drain of the transistor Tr1(g), the gate of the transistor Tr2(g), and one of the pair of electrodes of the capacitive element C1(g) is connected is referred to as a node N1(g). Further, for example, a low potential can be applied to the wiring VSSL. The low potential can be ground potential, for example.

Data to be a weighting factor is supplied to the memory MW[i](1) to the memory MW[i](t) through the wiring WD. Further, the conduction state of the transistor Tr1(g) is controlled by the potential of the wiring WW(g). When data to be a weighting factor output from the wiring WD is written to the memory MW[i](g), the transistor Tr1(g) is turned on. On the other hand, when the data output from the wiring WD and serving as the weighting factor is not written to the memory MW[i](g), the transistor Tr1(g) is turned off. When the transistor Tr1(g) is rendered non-conductive, the memory MW[i](g) can hold data that becomes a weighting factor corresponding to the attribute information 32[g]. Specifically, data written to the memory MW[i](g) is held as charge in the node N1(g). As described above, MAC[i] performs learning, and the weighting coefficients obtained as a result of learning can be held in memory MW[i](1) to memory [i](t).

The transistors Tr1(1) to Tr1(t) and the transistors Tr2(1) to Tr2(t) are preferably OS transistors. Further, a channel formation region of each of the transistors Tr1(1) to Tr1(t) and the transistors Tr2(1) to Tr2(t) is a metal oxide containing at least one of indium, element M, and zinc. is more preferable.

By using OS transistors as the transistors Tr1(1) to Tr1(t) and the transistors Tr2(1) to Tr2(t), the transistors Tr1(1) to Tr1(t) and the transistors Tr2(1) are used. ) to transistor Tr2(t). Thus, leakage of charges held in the nodes N1(1) to N1(t) to the wiring WD when the transistors Tr1(1) to Tr1(t) are off can be greatly reduced. Therefore, it is possible to provide a sum-of-products arithmetic circuit with high calculation accuracy. In addition, since the frequency of refresh operations on the nodes N1(1) to N1(t) can be reduced, power consumption of the semiconductor device can be reduced.

Note that transistors containing silicon in a semiconductor layer (hereinafter referred to as Si transistors) may be used as the transistors Tr2(1) to Tr2(t). For example, hydrogenated amorphous silicon is preferably used as the silicon because it can be formed over a large substrate with high yield.

Alternatively, OS transistors may be used as the transistors Tr3(1) to Tr3(t). Accordingly, all the transistors provided in the product circuit MAC[i] can be OS transistors, and the manufacturing process of the semiconductor device can be shortened. That is, since the production time of semiconductor devices can be reduced, the number of products produced per fixed period of time can be increased. Note that the transistors Tr1(1) to Tr1(t), the transistors Tr2(1) to Tr2(t), and the transistors Tr3(1) to Tr3(t) may all be Si transistors.

Data such as image data is supplied to the memory MW[i](1) to the memory MW[i](t) through the wiring RW. When data is supplied from the wiring RW to the memories MW[i](1) to MW[i](t), the potential of the other of the pair of electrodes of the capacitors C1(1) to C1(t) changes. , depending on the supplied data. Therefore, the potentials of the nodes N1(1) to N1(t) change due to capacitive coupling caused by the capacitance of the capacitors C1(1) to C1(t) or the like. As described above, the potentials of the nodes N1(1) to N1(t) correspond to the data such as the image data and the data serving as the weighting coefficient. That is, the memory cells MW[i](1) to MW[i](t) hold data corresponding to data such as image data and data serving as weighting coefficients.

In this specification and the like, data supplied from the wiring WD to the memory MW[i](1) to the memory MW[i](t) is referred to as first data. That is, for example, data that becomes a weighting factor can be called first data. In this specification and the like, data supplied from the wiring RW to the memory MW[i](1) to the memory MW[i](t) is referred to as second data. That is, for example, data such as image data can be called second data. Further, in this specification and the like, data corresponding to the first data and the second data is referred to as third data. The third data can be, for example, data corresponding to the product of the first data and the second data. In this case, it can be said that the memory MW[i](1) to the memory MW[i](t) have the function of the multiplication circuit MLT[i].

The third data is output to the outside of the product operation circuit MAC[i] via the wiring RD. The controller CNT has a function of controlling the conduction state of the transistor Tr3(g) by controlling the potential of the wiring SE(g) based on the attribute information 32. FIG. For example, when the attribute information 32[g] is input to the controller CNT and the transistors Tr3(1) to Tr3(t) are n-channel transistors, a high potential is applied to the wiring SE(g). A low potential is applied to the wirings SE other than the wirings SE. As a result, the third data can be read from the memory MW[i](g) that holds the weighting factor corresponding to the attribute information 32[g].

FIG. 17 shows the product operation circuit MAC[i] and the controller CNT, and wiring electrically connected to the product operation circuit MAC[i] and the controller CNT, and shows a configuration different from that of FIG. . Note that FIG. 17 shows a case where product operation circuit MAC[i] has memory MW[i](1) and memory MW[i](2), but product operation circuit MAC[i] has memory MW You may have three or more [i].

The product operation circuit MAC[i] illustrated in FIG. 17 has a memory MW[i](1), a memory MW[i](2), a transistor Tr4, and a capacitive element C2. It can be said that the transistor Tr4 and the capacitive element C2 are shared by the memory MW[i](1) and the memory MW[i](2). Note that the product operation circuit MAC[i] may have three or more memories MW[i]. In this case, the transistor Tr4 and the capacitive element C2 can be shared by the three or more memories MW[i].

The memory MW[i](1) has a transistor Tr1(1), a transistor Tr2(1), and a capacitive element C1(1). The memory MW[i](2) has a transistor Tr1(2), a transistor Tr2(2), and a capacitive element C1(2).

One of the source and the drain of the transistor Tr1(1) is electrically connected to the gate of the transistor Tr2(1) and one of the pair of electrodes of the capacitor C1(1). One of the source and drain of the transistor Tr1(2) is electrically connected to the gate of the transistor Tr2(2) and one of the pair of electrodes of the capacitor C1(2). The other of the source and the drain of the transistor Tr1(1) and the other of the source and the drain of the transistor Tr1(2) are electrically connected to the wiring WD.

A gate of the transistor Tr1(1) is electrically connected to the wiring WW(1). A gate of the transistor Tr1(2) is electrically connected to the wiring WW(2).

One of the source and drain of the transistor Tr2(1) is electrically connected to one of the source and drain of the transistor Tr2(2), the gate of the transistor Tr4, and one of the pair of electrodes of the capacitor C2. The other of the source or the drain of the transistor Tr2(1) and the other of the source or the drain of the transistor Tr2(2) are electrically connected to the wiring VRSL. A high potential or a low potential can be applied to the wiring VRSL.

One of the source and drain of the transistor Tr4 is electrically connected to the wiring RD. The other of the source and drain of the transistor Tr4 is electrically connected to the wiring VSSL.

The other of the pair of electrodes of the capacitor C1(1) is electrically connected to the wiring SE(1). The other of the pair of electrodes of the capacitor C1(2) is electrically connected to the wiring SE(2). The other of the pair of electrodes of the capacitor C2 is electrically connected to the wiring RW.

A node to which one of the source or drain of the transistor Tr1(1), the gate of the transistor Tr2(1), and one of the pair of electrodes of the capacitor C1(1) is connected is referred to as a node N1(1). A node to which one of the source or drain of the transistor Tr1(2), the gate of the transistor Tr2(2), and one of the pair of electrodes of the capacitor C1(2) is connected is referred to as a node N1(2). Further, a node to which one of the source and drain of the transistor Tr2(1), one of the source and drain of the transistor Tr2(2), the gate of the transistor Tr4, and one of the pair of electrodes of the capacitive element C2 are connected is referred to as a node N2. and

The transistor Tr4 is preferably an OS transistor, like the transistors Tr1(1), Tr1(2), Tr2(1), and Tr2(2). As a result, when the transistor Tr4 is in a non-conducting state, it is possible to suppress leakage of the charge held at the node N2 from the gate of the transistor Tr4, so that a product-sum operation circuit with high calculation accuracy can be provided. can. In addition, since the frequency of the refresh operation to the node N2 can be reduced, the power consumption of the semiconductor device can be reduced.

The description of the functions of various wirings electrically connected to the product operation circuit MAC[i] shown in FIG. 17 is the same as in the case shown in FIG. 16, and therefore omitted.

<Example of Operation Method of Product Operation Circuit>
Next, an example of the operation method of the product operation circuit MAC[i] having the configuration shown in FIG. 17 will be described with reference to the drawings. Although the transistor Tr1(1), the transistor Tr1(2), the transistor Tr2(1), the transistor Tr2(2), and the transistor Tr4 are all n-channel transistors in the description, the magnitude relationship of the potentials is reversed as appropriate. For this reason, the following description can be applied even when some or all of the transistors are p-channel type.

FIG. 18 is a timing chart showing an example of an operation method when the semiconductor device having the product operation circuit MAC[i] configured as shown in FIG. 17 performs learning. Specifically, as a weighting factor, data of potential V11 is written to memory MW[i]( ₁ ) of product operation circuit MAC[i], and data of potential V12 is written to memory MW[i]( ₂ ). Indicates when to write.

FIG. 18 illustrates a wiring WD, a wiring WW(1), a wiring WW(2), a wiring RW, a wiring SE(1), a wiring SE(2), a wiring VRSL, a node N1(1), a node N1(2), and It shows the potential of node N2.

In this specification and the like, the potential VSS is a low potential and the potential VDD is a high potential. Further, the potential VH is set higher than the potential VDD.

Before time T00, the potentials of the wiring WD, the wiring WW(1), the wiring WW(2), the wiring RW, the wiring VRSL, the node N1(1), the node N1(2), and the node N2 are set low. Further, the potentials of the wiring SE(1) and the wiring SE(2) are set to a high potential.

Between time T00 and time T01, the potential of the wiring WD is set to the potential V11, which is the potential corresponding to the data held in the memory MW[i]( ₁ ). After the potential of the wiring WD is set to the potential V11, the potential of the wiring WW( ₁ ) is set to a high potential. As a result, the transistor Tr1(1) is turned on, and the potential of the node N1(1) becomes the potential V ₁₁ or a potential corresponding to the potential V ₁₁ . As a result, data to be a weighting factor is written in the memory MW[i](1). Note that the potential _V11 can be, for example, higher than or equal to the potential VSS and lower than or equal to the potential VDD. Also, FIG. 18 shows the case where the potential of the node N1( ₁ ) becomes V11.

The potential of the wiring WW(1) is set to a low potential from time T01 to time T02. As a result, the potential of the node N1(1) is held, and the data written to the memory MW[i](1) is held. After the potential of the wiring WW(1) is set to a low potential, the potential of the wiring WD is set to a low potential.

From time T02 to time T03, the potential of the wiring WD is set to the potential V12, which is the potential corresponding to the data held in the memory MW[i]( ₂ ). After the potential of the wiring WD is set to the potential V12, the potential of the wiring WW( ₂ ) is set to a high potential. As a result, the transistor Tr1(2) is turned on, and the potential of the node N1(2) becomes the potential V ₁₂ or a potential corresponding to the potential V ₁₂ . As a result, data to be a weighting factor is written in the memory MW[i](2). Note that the potential _V12 can be, for example, higher than or equal to the potential VSS and lower than or equal to the potential VDD. FIG. 18 shows the case where the potential of the node N1( ₂ ) is V12.

The potential of the wiring WW(2) is set to a low potential from time T03 to time T04. As a result, the potential of the node N1(2) is held, and the data written to the memory MW[i](2) is held. After the potential of the wiring WW(2) is set to a low potential, the potential of the wiring WD is set to a low potential.

After time T04, the potential of the wiring SE(1) and the potential of the wiring SE(2) are set low. Since the potential of the other of the pair of electrodes of the capacitor C1(1) is lowered, the potential of the node N1(1) is lowered. Further, since the potential of the other of the pair of electrodes of the capacitor C1(2) is lowered, the potential of the node N1(2) is lowered.

The amount of decrease in the potential of the node N1(1) is calculated by capacitive coupling caused by the capacitance of the capacitive element C1(1), the gate capacitance of the transistor Tr2(1), the parasitic capacitance, and the like. Also, the decrease in the potential of the node N1(2) is calculated by capacitive coupling caused by the capacitance of the capacitive element C1(2), the gate capacitance of the transistor Tr2(2), the parasitic capacitance, and the like. In the example of the operation method shown in FIG. 18, in order to avoid complication of the description, it is assumed that the amount of decrease in the potential of the wiring SE(1) is equal to the amount of decrease in the potential of the node N1(1). This corresponds to a capacitive coupling coefficient of 1 at node N1(1). Further, description will be made on the assumption that the amount of decrease in the potential of the wiring SE(2) and the amount of decrease in the potential of the node N1(2) are the same. This corresponds to a capacitive coupling coefficient of 1 at node N1(2).

The potential of the node N1(1) and the potential of the node N1(2) are lower than the potential VSS, for example. Specifically, when the potential of the wiring SE(1) is high and the potential of the node N1( ₁ ) is the potential V11, when the potential of the wiring SE(1) is low, the potential of the node N1(1) is low. becomes V ₁₁ +VSS−VDD. Further, when the potential of the node N1( ₂ ) is V12 when the potential of the wiring SE(2) is high, the potential of the node N1(2) is low when the potential of the wiring SE(2) is low. becomes V ₁₂ +VSS-VDD. As a result, the transistors Tr2(1) and Tr2(2) are rendered non-conductive.

The above is an example of the operation method when the product operation circuit MAC[i] having the configuration shown in FIG. 17 performs learning.

FIG. 19 shows an example of the operation method of the product operation circuit MAC[i] after the product operation circuit MAC[i] having the configuration shown in FIG. 17 performs learning by the method shown in FIG. 18 and acquires the first data. is a timing chart showing Specifically, it is a timing chart showing an example of an operation of inputting second data such as image data to the product operation circuit MAC[i] and outputting third data.

19, similarly to FIG. 18, a wiring WD, a wiring WW(1), a wiring WW(2), a wiring RW, a wiring SE(1), a wiring SE(2), a wiring VRSL, a node N1(1), a node N1(2) and the potential of node N2 are shown.

Before time T10, the potentials of the wiring WD, the wiring WW(1), the wiring WW(2), the wiring RW, the wiring SE(1), the wiring SE(2), and the node N2 are set low. Further, the potential of the wiring VRSL is set to a high potential. Note that the potential of the node N1(1) and the potential of the node N1(2) are set to the same potential as the potential after time T04 shown in FIG. 18, for example, the potential VSS or less.

Time T10 to time T13 show the case where the data held in the memory MW[i](1) is used as the first data, for example, the case where the attribute information 32[1] is input to the controller CNT. As second data, data of the potential _V21 is input to the product operation circuit MAC[i]. The potential _V21 is, for example, higher than the potential VSS and lower than the potential VDD.

Between time T10 and time T11, the potential of the wiring RW is set to the potential _V21 , which is the potential corresponding to the second data. Since the potential of the other of the pair of electrodes of the capacitive element C2 changes, the potential of the node N2 changes due to capacitive coupling caused by the electrostatic capacitance of the capacitive element C2 or the like. The potential of the node N2 is the potential _V21 or a potential corresponding to the potential _V21 . Note that FIG. ₁₉ shows the case where the potential of the node N2 is V21, that is, the case where the capacitive coupling coefficient of the node N2 is one.

The potential of the wiring SE(1) is set to a high potential from time T11 to time T12. Since the potential of the other of the pair of electrodes of the capacitor C1(1) rises, the potential of the node N1(1) rises due to capacitive coupling caused by the electrostatic capacitance of the capacitor C1(1). Specifically, the potential is the same as the potential after time T04 shown in FIG. 18, that is, the potential V ₁₁ or the potential corresponding to the potential V ₁₁ . Note that FIG. ₁₉ shows the case where the potential of the node N1(1) is V11.

As the potential of the node N1(1) increases, the potential of the node N2 changes to the potential _V31 . The potential _V31 becomes a potential corresponding to the potential _V11 and the potential _V21 . Accordingly, the third data is read from the wiring RD. A current I flowing through the wiring RD when the third data is read can be expressed by the following equation when the transistor Tr4 operates in the saturation region. Note that in equation (7), k is a constant determined by the channel length, channel width, mobility of the transistor Tr4, the capacitance of the gate insulating film, and the like. Also, the threshold voltage of the transistor Tr4 is assumed to be 0V.

Therefore, by performing offset correction on the current flowing through the wiring RD and canceling the components (V ₁₁₂ and V ²¹² ) that do not correspond to the product of the potential V ₁₁ and the potential V ₂₁ , the current I becomes ² _{kV 11} V ₂₁ becomes. As described above, the third data can be data corresponding to the product of the first data and the second data. Note that offset correction can be performed by a circuit not shown in FIG. Also, if the threshold voltage is not 0 V, the current value dependent on the threshold voltage can also be canceled by the offset correction.

From time T12 to time T13, the potential of the wiring SE(1) is set to the potential VH, that is, a potential higher than the potential VDD. As a result, the potential of the node N1(1) rises to, for example, the potential VDD or higher. Therefore, the transistor Tr2( ₁ ) becomes conductive regardless of the magnitude of the potential V11. Further, the potential of the wiring RW and the potential of the wiring VRSL are set low. As a result, the potential of the node N2 is reset to a low potential.

After time T13, specifically, the potential of the wiring SE(1) is set to a low potential until time T20, which will be described later. As a result, the potential of the node N1(1) becomes, for example, the potential from time T10 to time T11, for example, the potential VSS or lower. As a result, the transistor Tr2(1) becomes non-conductive. After that, the potential of the wiring VRSL is set to a high potential.

Time T20 to time T23 show the case where the data held in the memory MW[i](2) is used as the first data, for example, the case where the attribute information 32[2] is input to the controller CNT. As the second data, the data of the potential _V22 is input to the product operation circuit MAC[i]. The potential _V22 is, for example, higher than the potential VSS and lower than the potential VDD.

Between time T20 and time T21, the potential of the wiring RW is set to the potential _V22 , which is the potential corresponding to the second data. Since the potential of the other of the pair of electrodes of the capacitive element C2 changes, the potential of the node N2 changes due to capacitive coupling caused by the electrostatic capacitance of the capacitive element C2 or the like. The potential of the node N2 is the potential _V22 or a potential corresponding to the potential _V22 . Note that FIG. 19 shows the case where the potential of the node N2 is _V22 , that is, the case where the capacitive coupling coefficient of the node N2 is 1 as described above.

The potential of the wiring SE(2) is set to a high potential from time T21 to time T22. Since the potential of the other of the pair of electrodes of the capacitive element C1(2) rises, the potential of the node N1(2) rises due to capacitive coupling caused by the electrostatic capacitance of the capacitive element C1(2). Specifically, the potential is the same as the potential after time T04 shown in FIG. 18, that is, the potential V ₁₂ or the potential corresponding to the potential V ₁₂ . Note that FIG. 19 shows the case where the potential of the node N1( ₂ ) is V12.

As the potential of the node N1(2) increases, the potential of the node N2 changes to the potential _V32 . The potential _V32 becomes a potential corresponding to the potential _V12 and the potential _V22 . Accordingly, the third data is read from the wiring RD. As described above, by performing offset correction on the current flowing through the wiring RD, the third data can be data corresponding to the product of the first data and the second data.

Between time T22 and time T23, the potential of the wiring SE(2) is set to the potential VH, which is higher than the potential VDD. As a result, the potential of the node N1(2) rises to, for example, the potential VDD or higher. Therefore, the transistor Tr2( ₂ ) becomes conductive regardless of the magnitude of the potential V12. Further, the potential of the wiring RW and the potential of the wiring VRSL are set low. As a result, the potential of the node N2 is reset to a low potential.

After time T23, the potential of the wiring SE(2) is set to a low potential. As a result, the potential of the node N1(2) becomes, for example, the potential from time T10 to time T11, for example, the potential VSS or lower. As a result, the transistor Tr2(2) becomes non-conductive. After that, the potential of the wiring VRSL is set to a high potential.

The above is an example of the operation method of the product operation circuit MAC[i] having the configuration shown in FIG. 17 after the product operation circuit MAC[i] acquires the first data by performing learning by the method shown in FIG. .

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 2)
In this embodiment, a specific structural example of a display device using the semiconductor device described in the above embodiment will be described. Here, in particular, a display device using a liquid crystal element as a display element will be described.

<Configuration Example 1 of Display Device>
FIG. 20 shows an example of a cross-sectional structure of the display device 1400. As shown in FIG. Here, an example in which a transmissive liquid crystal element 1420 is applied as a display element is shown. In FIG. 20, the substrate 1412 side is the display surface side.

The display device 1400 has a structure in which a liquid crystal 1422 is sandwiched between substrates 1411 and 1412 . A liquid crystal element 1420 includes a conductive layer 1421 provided on the substrate 1411 side, a conductive layer 1423 provided on the substrate 1412 side, and a liquid crystal 1422 sandwiched therebetween. An alignment film 1424 a is provided between the liquid crystal 1422 and the conductive layer 1421 , and an alignment film 1424 b is provided between the liquid crystal 1422 and the conductive layer 1423 .

The conductive layer 1421 functions as a pixel electrode. In addition, the conductive layer 1423 functions as a common electrode or the like. Both the conductive layers 1421 and 1423 have a function of transmitting visible light. Therefore, the liquid crystal element 1420 is a transmissive liquid crystal element.

A colored layer 1441 and a light shielding layer 1442 are provided on the surface of the substrate 1412 on the substrate 1411 side. An insulating layer 1426 is provided to cover the coloring layer 1441 and the light-blocking layer 1442 , and a conductive layer 1423 is provided to cover the insulating layer 1426 . The colored layer 1441 is provided in a region overlapping with the conductive layer 1421 . A light-blocking layer 1442 is provided to cover the transistor 1430 and the connection portion 1438 .

A polarizing plate 1439 a is arranged outside the substrate 1411 , and a polarizing plate 1439 b is arranged outside the substrate 1412 . Furthermore, a backlight unit 1490 is provided outside the polarizing plate 1439a. In the display device 1400 shown in FIG. 20, the substrate 1412 side is the display surface side.

A transistor 1430 , a capacitor 1460 , and the like are provided over a substrate 1411 . Transistor 1430 functions as a pixel select transistor. Transistor 1430 is connected to liquid crystal element 1420 through connection 1438 .

A transistor 1430 shown in FIG. 20 is a so-called bottom-gate channel-etched transistor. The transistor 1430 includes a conductive layer 1431 functioning as a gate electrode, an insulating layer 1434 functioning as a gate insulating layer, a semiconductor layer 1432, and a pair of conductive layers 1433a and 1433b functioning as a source electrode and a drain electrode. have. A portion of the semiconductor layer 1432 overlapping with the conductive layer 1431 functions as a channel formation region. The semiconductor layer 1432 is connected to the conductive layers 1433a and 1433b.

The capacitor 1460 includes a conductive layer 1431a, an insulating layer 1434, and a conductive layer 1433b.

An insulating layer 1482 and an insulating layer 1481 are stacked to cover the transistor 1430 and the like. A conductive layer 1421 functioning as a pixel electrode is provided over the insulating layer 1481 . In the connection portion 1438, the conductive layer 1421 and the conductive layer 1433b are electrically connected through openings provided in the insulating layers 1481 and 1482. FIG. The insulating layer 1481 preferably functions as a planarization layer. Further, the insulating layer 1482 preferably has a function as a protective film that suppresses diffusion of impurities or the like to the transistor 1430 or the like. For example, an inorganic insulating material can be used for the insulating layer 1482 and an organic insulating material can be used for the insulating layer 1481 .

<Configuration Example 2 of Display Device>
FIG. 21 shows an example in which the colored layer 1441 is provided on the substrate 1411 side. Thereby, the configuration on the substrate 1412 side can be simplified.

Note that in the case where the colored layer 1441 is used as a planarization film, the insulating layer 1481 may not be provided.

<Configuration Example 3 of Display Device>
In the above description, as a liquid crystal element, an example of a vertical electric field type liquid crystal element in which a pair of electrodes sandwiching a liquid crystal is arranged vertically is shown; can be applied.

FIG. 22 shows a schematic cross-sectional view of a display device having a liquid crystal element to which FFS (Fringe Field Switching) mode is applied.

A liquid crystal element 1420 includes a conductive layer 1421 functioning as a pixel electrode and a conductive layer 1423 which overlaps with the conductive layer 1421 with an insulating layer 1483 provided therebetween. The conductive layer 1423 has a slit-shaped or comb-shaped top surface.

Further, in this structure, a capacitor is formed in a portion where the conductive layer 1421 and the conductive layer 1423 overlap, and this can be used as the capacitor 1460 . Therefore, since the area occupied by the pixels can be reduced, a high-definition display device can be realized. Also, the aperture ratio can be improved.

In FIG. 22, the conductive layer 1423 functioning as a common electrode is positioned on the liquid crystal 1422 side, but as shown in FIG. good. At this time, the conductive layer 1421 has a slit-like or comb-like top surface shape.

Here, when manufacturing a display device, manufacturing costs can be reduced as the number of photolithography steps in the manufacturing process is reduced, that is, as the number of photomasks is reduced.

For example, in the configuration shown in FIG. 20, among the processes on the substrate 1411 side, a process of forming the conductive layer 1431 and the like, a process of forming the semiconductor layer 1432, a process of forming the conductive layer 1433a and the like, a process of forming the opening serving as the connecting part 1438, and a step of forming the conductive layer 1421, a total of five photolithography steps. That is, a backplane substrate can be manufactured with five photomasks. On the other hand, on the substrate 1412 (counter substrate) side, it is preferable to use an inkjet method, a screen printing method, or the like as a method for forming the colored layer 1441 and the light-shielding layer 1442 because no photomask is required. For example, when the colored layers 1441 of three colors and the light shielding layer 1442 are provided, a total of four photomasks can be reduced as compared with the case of forming them by photolithography.

<Structure example of transistor>
Next, a specific structural example of the transistor 1430 is described. A semiconductor containing silicon can be used for the semiconductor layer 1432 of the transistor described below. As the semiconductor containing silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be used, for example. In particular, it is preferable to use hydrogenated amorphous silicon because it can be formed over a large substrate with high yield. The display device of one embodiment of the present invention can display favorable images even with a transistor including amorphous silicon with relatively low field-effect mobility.

A transistor illustrated in FIG. 24A has a pair of impurity semiconductor layers 1435 functioning as a source region and a drain region. The impurity semiconductor layers 1435 are provided between the semiconductor layer 1432 and the conductive layer 1433a and between the semiconductor layer 1432 and the conductive layer 1433b. The semiconductor layer 1432 and the impurity semiconductor layer 1435 are provided in contact, and the impurity semiconductor layer 1435 and the conductive layer 1433a or the conductive layer 1433b are provided in contact.

An impurity semiconductor film forming the impurity semiconductor layer 1435 is formed using a semiconductor to which an impurity element imparting one conductivity type is added. When the transistor is n-type, the semiconductor to which an impurity element imparting one conductivity type is added is, for example, silicon to which P or As is added. Alternatively, in the case of a p-type transistor, B, for example, can be added as an impurity element imparting one conductivity type, but the transistor is preferably an n-type. Note that the impurity semiconductor layer may be formed using an amorphous semiconductor or a crystalline semiconductor such as a microcrystalline semiconductor.

The transistor illustrated in FIG. 24B has a semiconductor layer 1437 between the semiconductor layer 1432 and the impurity semiconductor layer 1435 .

The semiconductor layer 1437 may be formed using a semiconductor film similar to the semiconductor layer 1432 . The semiconductor layer 1437 can function as an etching stopper for preventing the semiconductor layer 1432 from disappearing due to etching when the impurity semiconductor layer 1435 is etched. Note that although FIG. 24B shows an example in which the semiconductor layer 1437 is separated into left and right sides, part of the semiconductor layer 1437 may cover the channel formation region of the semiconductor layer 1432 .

Further, the semiconductor layer 1437 may contain impurities at a lower concentration than the impurity semiconductor layer 1435 . Accordingly, the semiconductor layer 1437 can function as an LDD (Lightly Doped Drain) region, and hot carrier deterioration when the transistor is driven can be suppressed.

In the transistor illustrated in FIG. 24C, an insulating layer 1484 is provided over the channel formation region of the semiconductor layer 1432 . The insulating layer 1484 functions as an etching stopper during etching of the impurity semiconductor layer 1435 .

The transistor illustrated in FIG. 24D includes a semiconductor layer 1432p instead of the semiconductor layer 1432. FIG. The semiconductor layer 1432p includes a highly crystalline semiconductor film. For example, the semiconductor layer 1432p includes a polycrystalline semiconductor or a single crystal semiconductor. Accordingly, the transistor can have high field-effect mobility.

The transistor illustrated in FIG. 24E has a semiconductor layer 1432p in the channel formation region of the semiconductor layer 1432. The transistor illustrated in FIG. For example, the transistor illustrated in FIG. 24E can be formed by irradiating a semiconductor film to be the semiconductor layer 1432 with laser light or the like so that the semiconductor film is locally crystallized. Accordingly, a transistor with high field effect mobility can be realized.

The transistor illustrated in FIG. 24F includes a crystalline semiconductor layer 1432p in the channel formation region of the semiconductor layer 1432 of the transistor illustrated in FIG. 24B.

The transistor illustrated in FIG. 24G includes a crystalline semiconductor layer 1432p in the channel formation region of the semiconductor layer 1432 of the transistor illustrated in FIG. 24C.

<Constituent element>
Below, each component shown above is demonstrated.

[substrate]
A material having a flat surface can be used for a substrate included in the display device. A material that transmits the light is used for the substrate for extracting the light from the display element. For example, materials such as glass, quartz, ceramics, sapphire, and organic resins can be used.

By using a thin substrate, the weight and thickness of the display panel can be reduced. Furthermore, a flexible display panel can be realized by using a substrate that is thick enough to be flexible. Alternatively, a thin glass or the like having flexibility can be used for the substrate. Alternatively, a composite material in which glass and a resin material are bonded together by an adhesive layer may be used.

[Transistor]
A transistor includes a conductive layer functioning as a gate electrode, a semiconductor layer, a conductive layer functioning as a source electrode, a conductive layer functioning as a drain electrode, and an insulating layer functioning as a gate insulating layer.

Note that there is no particular limitation on the structure of the transistor included in the display device of one embodiment of the present invention. For example, a planar transistor, a staggered transistor, or an inverted staggered transistor may be used. Further, the transistor structure may be either a top-gate type or a bottom-gate type. Alternatively, gate electrodes may be provided above and below the channel.

Crystallinity of a semiconductor material used for a transistor is not particularly limited, either an amorphous semiconductor or a semiconductor having crystallinity (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor partially including a crystal region). may be used. It is preferable to use a crystalline semiconductor because deterioration of transistor characteristics can be suppressed.

Silicon, for example, can be used as a semiconductor in which a channel of a transistor is formed. As silicon, it is particularly preferable to use amorphous silicon. By using amorphous silicon, a transistor can be formed on a large substrate with high yield, and mass productivity is excellent.

Alternatively, crystalline silicon such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon can be used. In particular, polycrystalline silicon can be formed at a lower temperature than monocrystalline silicon, and has higher field effect mobility and higher reliability than amorphous silicon.

The bottom-gate transistor described as an example in this embodiment is preferable because the number of manufacturing steps can be reduced. In addition, by using amorphous silicon at this time, since it can be formed at a lower temperature than polycrystalline silicon, it is possible to use a material with low heat resistance as a material for wiring and electrodes in a layer below the semiconductor layer and a material for the substrate. , the range of material selection can be expanded. For example, an extremely large-area glass substrate or the like can be suitably used. On the other hand, a top-gate transistor is preferable because an impurity region can be easily formed in a self-aligned manner and variations in characteristics can be reduced. At this time, it may be particularly suitable when polycrystalline silicon, single crystal silicon, or the like is used.

[Conductive layer]
In addition to the gate, source and drain of transistors, materials that can be used for conductive layers such as various wirings and electrodes constituting display devices include aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, A metal such as tantalum or tungsten, or an alloy containing this as a main component can be used. Also, a film containing these materials can be used as a single layer or as a laminated structure. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is stacked over a titanium film, a two-layer structure in which an aluminum film is stacked over a tungsten film, and a copper film over a copper-magnesium-aluminum alloy film. A two-layer structure, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film, and an aluminum film or a copper film overlaid thereon and further a titanium film or a titanium nitride film is formed thereon, a molybdenum film or a molybdenum nitride film is laminated thereon, an aluminum film or a copper film is laminated thereon, and a molybdenum film or a There is a three-layer structure that forms a molybdenum nitride film, and the like. Note that an oxide such as indium oxide, tin oxide, or zinc oxide may be used. Further, it is preferable to use copper containing manganese because the controllability of the shape by etching is increased.

In addition, indium oxide, indium tin oxide, indium tin oxide, indium tin oxide, indium tin oxide, indium tin oxide, indium tin oxide, indium tin oxide, indium tin oxide, etc. Conductive oxides such as indium zinc oxide, zinc oxide, gallium-doped zinc oxide, or graphene can be used. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium, or alloy materials containing such metal materials can be used. Alternatively, a nitride of the metal material (for example, titanium nitride) or the like may be used. Note that when a metal material or an alloy material (or a nitride thereof) is used, it may be thin enough to have translucency. Alternatively, a stacked film of any of the above materials can be used as the conductive layer. For example, it is preferable to use a laminated film of an alloy of silver and magnesium and indium tin oxide, or the like, because the conductivity can be increased. These can also be used for conductive layers such as various wirings and electrodes that constitute a display device, and conductive layers that display elements have (conductive layers functioning as pixel electrodes and common electrodes).

[Insulating layer]
Examples of insulating materials that can be used for each insulating layer include resins such as acrylic and epoxy, resins having a siloxane bond such as silicone, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide. inorganic insulating materials can also be used.

Examples of the insulating film with low water permeability include a film containing nitrogen and silicon such as a silicon nitride film and a silicon nitride oxide film, a film containing nitrogen and aluminum such as an aluminum nitride film, and the like. Alternatively, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or the like may be used.

[Liquid crystal element]
As the liquid crystal element, for example, a liquid crystal element to which a vertical alignment (VA) mode is applied can be used. As the vertical alignment mode, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, or the like can be used.

Liquid crystal elements to which various modes are applied can be used as the liquid crystal element. For example, in addition to VA mode, TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axially Symmetrically aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode , FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, ECB (Electrically Controlled Birefringence) mode, guest-host mode, or the like can be used.

Note that the liquid crystal element is an element that controls transmission or non-transmission of light by the optical modulation action of liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). The liquid crystal used in the liquid crystal element includes thermotropic liquid crystal, low-molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC), polymer network liquid crystal (PNLC), Ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc., depending on conditions.

As the liquid crystal material, either positive liquid crystal or negative liquid crystal may be used, and an optimum liquid crystal material may be used according to the mode and design to be applied.

In addition, an alignment film can be provided to control the alignment of liquid crystals. Note that when the horizontal electric field method is employed, liquid crystal exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the cholesteric phase transitions to the isotropic phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight % or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and optical isotropy. Further, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency. In addition, rubbing treatment is not required because an alignment film is not required, so that electrostatic damage caused by rubbing treatment can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .

Liquid crystal elements include a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, and the like.

In one embodiment of the present invention, a transmissive liquid crystal element can be particularly preferably used.

In the case of using a transmissive or transflective liquid crystal element, two polarizing plates are provided so as to sandwich a pair of substrates. A backlight is provided outside the polarizing plate. The backlight may be a direct type backlight or an edge light type backlight. It is preferable to use a direct type backlight equipped with LEDs (Light Emitting Diodes) because local dimming can be facilitated and contrast can be increased. Further, it is preferable to use an edge-light type backlight because the thickness of the module including the backlight can be reduced.

Note that see-through display can be performed by turning off the edge-light type backlight.

[Colored layer]
Materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like.

[Light shielding layer]
Examples of materials that can be used as the light shielding layer include carbon black, titanium black, metals, metal oxides, composite oxides containing a solid solution of multiple metal oxides, and the like. The light shielding layer may be a film containing a resin material, or may be a thin film of an inorganic material such as metal. Alternatively, a laminated film of films containing a material for the colored layer can be used as the light shielding layer. For example, a layered structure of a film containing a material used for a colored layer transmitting light of a certain color and a film containing a material used for a colored layer transmitting light of another color can be used. By using a common material for the colored layer and the light shielding layer, it is possible to use a common apparatus and to simplify the process, which is preferable.

Note that although a display device using a liquid crystal element as a display element is described in this embodiment mode, a light-emitting element can also be used as a display element.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 3)
In this embodiment mode, an example of a method for crystallizing polycrystalline silicon and a laser crystallization apparatus that can be used for a semiconductor layer of a transistor will be described.

In order to form a polycrystalline silicon layer with good crystallinity, it is preferable to provide an amorphous silicon layer over a substrate and crystallize the amorphous silicon layer by irradiating it with laser light. For example, by using a laser beam as a linear beam and moving the substrate while irradiating the amorphous silicon layer with the linear beam, the polycrystalline silicon layer can be formed in a desired region over the substrate.

A method using a linear beam has a relatively good throughput. On the other hand, since it is a method in which a laser beam is irradiated a plurality of times while moving relatively to a certain region, variations in crystallinity are likely to occur due to variations in the output of the laser beam and the resulting changes in the beam profile. For example, when a semiconductor layer crystallized by this method is used for a transistor included in a pixel of a display device, a random striped pattern due to variations in crystallinity may be seen when an image is displayed.

Also, the length of the linear beam is ideally equal to or longer than the length of one side of the substrate, but the length of the linear beam is limited by the output of the laser oscillator and the configuration of the optical system. Therefore, in the processing of a large substrate, it is realistic to irradiate the laser while folding back within the substrate surface. As a result, there are areas where the laser beams overlap and are irradiated. Since the crystallinity of the region is likely to be different from the crystallinity of other regions, display unevenness may occur in the region.

In order to suppress the above problems, an amorphous silicon layer formed over a substrate may be locally irradiated with a laser to be crystallized. Local laser irradiation facilitates formation of a polycrystalline silicon layer with little variation in crystallinity.

FIG. 25A is a diagram illustrating a method of locally irradiating an amorphous silicon layer formed over a substrate with laser light.

A laser beam 626 emitted from an optical system unit 621 is reflected by a mirror 622 and enters a microlens array 623 . Microlens array 623 converges laser light 626 to form multiple laser beams 627 .

A substrate 630 having an amorphous silicon layer 640 formed thereon is fixed to the stage 615 . By irradiating the amorphous silicon layer 640 with a plurality of laser beams 627, a plurality of polycrystalline silicon layers 641 can be formed at the same time.

The individual microlenses included in the microlens array 623 are preferably provided in accordance with the pixel pitch of the display device. Alternatively, they may be provided at an interval that is an integral multiple of the pixel pitch. In either case, by repeating laser irradiation and movement of the stage 615 in the X direction or the Y direction, polycrystalline silicon layers can be formed in regions corresponding to all pixels.

For example, when the microlens array 623 has microlenses of I rows and J columns (I and J are natural numbers) at a pixel pitch, laser light is first irradiated at a predetermined starting position to cover the polycrystalline silicon layer of I rows and J columns. can be formed. Then, the polycrystalline silicon layer 641 is formed with M rows and N columns by moving a distance of J columns in the row direction and irradiating the laser beam, thereby forming polycrystalline silicon layers 641 with I rows and 2J columns. be able to. By repeating this step, a plurality of polycrystalline silicon layers 641 can be formed in desired regions. In addition, when the laser irradiation process is performed by turning back, the laser irradiation is performed by moving a distance of J columns in the row direction, and then the movement of a distance of I rows in the column direction and the irradiation of the laser light are repeated.

By appropriately adjusting the oscillation frequency of the laser light and the movement speed of the stage 615, the polycrystalline silicon layer can be formed at the pixel pitch even by a method of performing laser irradiation while moving the stage 615 in one direction.

The size of the laser beam 627 can be, for example, an area that includes the entire semiconductor layer of one transistor. Alternatively, the area can be such that the entire channel region of one transistor is included. Alternatively, the area can be such that part of the channel region of one transistor is included. These may be used depending on the required electrical characteristics of the transistor.

Note that in the case of a display device including a plurality of transistors in one pixel, the area of the laser beam 627 can be such that the entire semiconductor layer of each transistor in one pixel is included. Alternatively, the area of the laser beam 627 may be such that the entire semiconductor layers of transistors included in a plurality of pixels are included.

Also, as shown in FIG. 26A, a mask 624 may be provided between the mirror 622 and the microlens array 623 . A mask 624 is provided with a plurality of openings corresponding to each microlens. The shape of the opening can be reflected in the shape of the laser beam 627, and when the mask 624 has a circular opening as shown in FIG. 26A, a circular laser beam 627 can be obtained. Also, if the mask 624 has a rectangular opening, a rectangular laser beam 627 can be obtained. The mask 624 is effective, for example, when it is desired to crystallize only the channel region of the transistor. Note that the mask 624 may be provided between the optical system unit 621 and the mirror 622 as shown in FIG. 26(B).

FIG. 25B is a perspective view illustrating the main configuration of a laser crystallization apparatus that can be used in the local laser irradiation process described above. The laser crystallization apparatus has a moving mechanism 612, a moving mechanism 613, and a stage 615, which are components of an XY stage. It also has a laser oscillator 620 for shaping a laser beam 627 , an optical system unit 621 , a mirror 622 and a microlens array 623 .

The moving mechanism 612 and the moving mechanism 613 have a function of reciprocating linear motion in the horizontal direction. As a mechanism for applying power to the moving mechanism 612 and the moving mechanism 613, for example, a ball screw mechanism 616 driven by a motor can be used. Since the respective moving directions of the moving mechanism 612 and the moving mechanism 613 intersect perpendicularly, the stage 615 fixed to the moving mechanism 613 can be freely moved in the X direction and the Y direction.

The stage 615 has a fixing mechanism such as a vacuum suction mechanism, and can fix the substrate 630 and the like. Moreover, the stage 615 may have a heating mechanism as necessary. Although not shown, the stage 615 has a pusher pin and its vertical mechanism, and can move the substrate 630 and the like up and down when the substrate 630 and the like is carried in and out.

The laser oscillator 620 may output light having a wavelength and intensity suitable for the purpose of processing, and is preferably a pulsed laser, but may be a CW laser. Typically, an excimer laser capable of irradiating ultraviolet light with a wavelength of 351-353 nm (XeF), 308 nm (XeCl), or the like can be used. Alternatively, double waves (515 nm, 532 nm, etc.) or triple waves (343 nm, 355 nm, etc.) of a solid-state laser (YAG laser, fiber laser, etc.) may be used. Also, a plurality of laser oscillators 620 may be provided.

The optical system unit 621 has, for example, a mirror, a beam expander, a beam homogenizer, and the like, and can expand the laser light 625 output from the laser oscillator 620 while making the in-plane energy distribution uniform.

For example, a dielectric multilayer mirror can be used as the mirror 622, and it is installed so that the incident angle of the laser light is approximately 45°. The microlens array 623 can have, for example, a shape in which a plurality of convex lenses are provided on the upper surface or the upper and lower surfaces of a quartz plate.

By using the laser crystallization apparatus described above, a polycrystalline silicon layer with little variation in crystallinity can be formed.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 4)
In this embodiment, details of the transistor 200 and the transistor 201 that can be applied to the transistors described in this specification and the like are described with reference to FIGS.

<Transistor 200>
First, details of the transistor 200 will be described.

FIG. 27A is a top view of a semiconductor device including the transistor 200. FIG. 27B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 27A, and is also a cross-sectional view of the transistor 200 in the channel length direction. 27C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 27A, and is also a cross-sectional view of the transistor 200 in the channel width direction. In the top view of FIG. 27A, some elements are omitted for clarity of illustration.

As shown in FIGS. 27A-27C, transistor 200 includes an insulator 224 overlying a substrate (not shown), a metal oxide 406a overlying insulator 224, A metal oxide 406b placed in contact with at least part of a top surface of the metal oxide 406a, an insulator 412 placed over the metal oxide 406b, and a conductor 404a placed over the insulator 412. , the conductor 404b arranged on the conductor 404a, the insulator 419 arranged on the conductor 404b, the insulator 412, the conductor 404a, the conductor 404b, and the insulator 419. and an insulator 225 that is in contact with the top surface of the metal oxide 406 b and in contact with the side surface of the insulator 418 . Here, as shown in FIG. 27B, it is preferable that the top surface of the insulator 418 substantially coincides with the top surface of the insulator 419 . Insulator 225 is preferably provided over insulator 419 , conductor 404 , insulator 418 , and metal oxide 406 .

Hereinafter, the metal oxide 406a and the metal oxide 406b may be collectively referred to as the metal oxide 406 in some cases. Note that although the structure in which the metal oxide 406a and the metal oxide 406b are stacked is shown in the transistor 200, the present invention is not limited to this. For example, only the metal oxide 406b may be provided. Also, the conductor 404a and the conductor 404b may be collectively referred to as a conductor 404 in some cases. Note that although the structure in which the conductors 404a and 404b are stacked is shown in the transistor 200, the present invention is not limited to this. For example, only the conductor 404b may be provided.

A conductor 440a is formed in contact with the inner wall of the opening of the insulator 384, and a conductor 440b is further formed inside. Here, the height of the top surfaces of the conductors 440a and 440b and the height of the top surface of the insulator 384 can be approximately the same. Note that although the structure in which the conductor 440a and the conductor 440b are stacked is shown in the transistor 200, the present invention is not limited to this. For example, only the conductor 440b may be provided.

The conductor 310 has a conductor 310a formed in contact with the inner walls of the openings of the insulators 214 and 216, and a conductor 310b formed inside. Therefore, it is preferable that the conductor 310a is in contact with the conductor 440b. Here, the height of the upper surfaces of the conductors 310a and 310b and the height of the upper surface of the insulator 216 can be made approximately the same. Note that although the structure in which the conductor 310a and the conductor 310b are stacked is shown in the transistor 200, the present invention is not limited to this. For example, only the conductor 310b may be provided.

Conductor 404 can function as a top gate and conductor 310 can function as a back gate. The potential of the back gate may be the same potential as that of the top gate, the ground potential, or any other potential. In addition, by changing the potential of the back gate independently of the potential of the top gate, the threshold voltage of the transistor can be changed.

The conductor 440 extends in the channel width direction similarly to the conductor 404, and functions as a wiring that applies a potential to the conductor 310, that is, the back gate. Here, insulation is provided between the conductor 440 and the conductor 404 by providing the conductor 310 embedded in the insulator 214 and the insulator 216 and stacked over the conductor 440 functioning as a wiring of the back gate. A body 214, an insulator 216, and the like are provided to reduce parasitic capacitance between the conductor 440 and the conductor 404 and increase withstand voltage. By reducing the parasitic capacitance between the conductor 440 and the conductor 404, the switching speed of the transistor can be improved and the transistor can have high frequency characteristics. Further, by increasing the withstand voltage between the conductor 440 and the conductor 404, the reliability of the transistor 200 can be improved. Therefore, it is preferable to increase the thickness of the insulators 214 and 216 . Note that the extending direction of the conductor 440 is not limited to this, and may be extended in the channel length direction of the transistor 200, for example.

Here, for the conductors 310a and 440a, it is preferable to use a conductive material that has a function of suppressing permeation of impurities such as water or hydrogen (hardly permeates). For example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like, and a single layer or stacked layers may be used. Thus, impurities such as hydrogen and water can be prevented from diffusing from the lower layer to the upper layer through the conductors 440 and 310 . Note that the conductor 310a and the conductor 440a are hydrogen atoms, hydrogen molecules, water molecules, oxygen atoms, oxygen molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ etc.), copper atoms and the like. or at least one of oxygen (for example, oxygen atoms, oxygen molecules, etc.). The same applies to the case where a conductive material having a function of suppressing permeation of impurities is described below. Since the conductor 310a and the conductor 440a have a function of suppressing permeation of oxygen, the conductor 310b and the conductor 440b can be prevented from being oxidized to reduce their conductivity.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 310b. Although not shown, the conductor 310b may have a layered structure, for example, a layered structure of titanium, titanium nitride, and any of the above conductive materials.

In addition, since the conductor 440b functions as a wiring, it is preferable to use a conductor having higher conductivity than the conductor 310b. For example, a conductive material containing copper or aluminum as its main component can be used. Although not shown, the conductor 440b may have a layered structure, for example, a layered structure of titanium, titanium nitride, and any of the above conductive materials.

The insulator 214 can function as a barrier insulating film that prevents impurities such as water or hydrogen from entering the transistor from below. The insulator 214 is preferably formed using an insulating material that has a function of suppressing permeation of impurities such as water or hydrogen. For example, silicon nitride or the like is preferably used as the insulator 214 . Accordingly, impurities such as hydrogen and water can be prevented from diffusing into layers above the insulator 214 . Note that the insulator 214 suppresses permeation of at least one impurity such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, NO, NO ₂ or the like), or a copper atom. It is preferable to have a function. In the following, the same applies to the case where an insulating material having a function of suppressing penetration of impurities is described.

For the insulator 214, an insulating material having a function of suppressing permeation of oxygen (eg, oxygen atoms, oxygen molecules, or the like) is preferably used. Accordingly, downward diffusion of oxygen contained in the insulator 224 and the like can be suppressed.

In addition, the insulator 214 can be provided between the conductors 440 and 310 by stacking the conductor 310 over the conductor 440 . Here, even if a metal that is easily diffused, such as copper, is used for the conductor 440b, the metal can be prevented from diffusing into a layer above the insulator 214 by providing silicon nitride or the like as the insulator 214. FIG.

For the insulator 222, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, such as aluminum oxide or hafnium oxide, is preferably used. Accordingly, diffusion of impurities such as hydrogen and water from a layer below the insulator 222 to a layer above the insulator 222 can be suppressed. Furthermore, downward diffusion of oxygen contained in the insulator 224 or the like can be suppressed.

Further, it is preferable that the concentration of impurities such as water, hydrogen, or nitrogen oxides in the insulator 224 is reduced. For example, the amount of hydrogen desorbed from the insulator 224 is equivalent to the amount of hydrogen molecules in a range of 50° C. to 500° C. in thermal desorption spectroscopy (TDS). It may be 2×10 ¹⁵ molecules/cm ² or less, preferably 1×10 ¹⁵ molecules/cm ² or less, more preferably 5×10 ¹⁴ molecules/cm ² or less in terms of the area of the body 224 . The insulator 224 is preferably formed using an insulator from which oxygen is released by heating.

Insulator 412 can function as a first gate insulator, and insulator 220, insulator 222, and insulator 224 can function as a second gate insulator. Note that although the transistor 200 shows the structure in which the insulators 220, 222, and 224 are stacked, the present invention is not limited to this. For example, a structure in which any two layers of the insulator 220, the insulator 222, and the insulator 224 are stacked may be employed, or a structure using any one layer may be employed.

A metal oxide that functions as an oxide semiconductor is preferably used as the metal oxide 406 . It is preferable to use a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide energy gap in this manner, off-state current of a transistor can be reduced.

Since a transistor using a metal oxide has extremely low leakage current in a non-conducting state, a semiconductor device with low power consumption can be provided. Further, since a metal oxide can be deposited by a sputtering method or the like, it can be used for a transistor included in a highly integrated semiconductor device.

Metal oxide 406 preferably contains at least indium or zinc. Indium and zinc are particularly preferred. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Consider now that the metal oxide 406 is an In--M--Zn oxide having indium, the element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above elements may be combined.

In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

Here, in the metal oxide used for the metal oxide 406a, the atomic number ratio of the element M among the constituent elements is greater than the atomic number ratio of the element M among the constituent elements in the metal oxide used for the metal oxide 406b. is preferred. Moreover, in the metal oxide used for the metal oxide 406a, the atomic ratio of the element M to In is preferably higher than the atomic ratio of the element M to In in the metal oxide used for the metal oxide 406b. In addition, the atomic ratio of In to the element M in the metal oxide used for the metal oxide 406b is preferably higher than the atomic ratio of In to the element M in the metal oxide used for the metal oxide 406a.

When the above metal oxide is used as the metal oxide 406a, the energy of the conduction band bottom of the metal oxide 406a is higher than the energy of the conduction band bottom of the metal oxide 406b in the region where the energy of the conduction band bottom is low. It is preferable to be In other words, the electron affinity of the metal oxide 406a is preferably smaller than the electron affinity of the metal oxide 406b in the lower energy region of the conduction band bottom.

Here, in the metal oxide 406a and the metal oxide 406b, the energy level at the bottom of the conduction band changes smoothly. In other words, it can be said that it changes continuously or joins continuously. In order to achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the metal oxides 406a and 406b.

Specifically, when the metal oxide 406a and the metal oxide 406b have a common element (main component) other than oxygen, a mixed layer with a low defect level density can be formed. For example, when the metal oxide 406b is an In--Ga--Zn oxide, the metal oxide 406a may be In--Ga--Zn oxide, Ga--Zn oxide, gallium oxide, or the like.

At this time, the main path of carriers becomes the narrow gap portion formed in the metal oxide 406b. Since the defect level density at the interface between the metal oxide 406a and the metal oxide 406b can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

Metal oxide 406 also has region 426a, region 426b, and region 426c. The region 426a is sandwiched between the regions 426b and 426c as shown in FIG. 27(B). Regions 426b and 426c are regions whose resistance is lowered by film formation of the insulator 225, and which have higher conductivity than the region 426a. The regions 426b and 426c are doped with an impurity element such as hydrogen or nitrogen contained in the film formation atmosphere of the insulator 225 . As a result, oxygen vacancies are formed by the added impurity element mainly in a region of the metal oxide 406b overlapping with the insulator 225, and the impurity element enters the oxygen vacancies, whereby the carrier density is increased and the resistance is low. become.

Therefore, the regions 426b and 426c preferably have a higher concentration of at least one of hydrogen and nitrogen than the region 426a. The concentration of hydrogen or nitrogen may be measured using secondary ion mass spectrometry (SIMS) or the like. Here, the concentration of hydrogen or nitrogen in the region 426a is defined as the vicinity of the center of the region where the metal oxide 406b overlaps with the insulator 412 (for example, the distance from both side surfaces of the metal oxide 406b in the channel length direction of the insulator 412 is The concentration of hydrogen or nitrogen in approximately equal parts) may be measured.

Note that the resistance of the regions 426b and 426c is reduced by adding an element that forms oxygen vacancies or an element that combines with oxygen vacancies. Such elements typically include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, chlorine, titanium, noble gases, and the like. Representative examples of rare gas elements include helium, neon, argon, krypton, and xenon. Therefore, the regions 426b and 426c may contain one or more of the above elements.

In the metal oxide 406a, the atomic ratio of In to the element M in the regions 426b and 426c is preferably approximately the same as the atomic ratio of In to the element M in the metal oxide 406b. In other words, the metal oxide 406a preferably has an atomic ratio of In to the element M in the regions 426b and 426c that is greater than the atomic ratio of In to the element M in the region 426a. Here, by increasing the indium content of the metal oxide 406, the carrier density can be increased and the resistance can be reduced. With such a structure, even when the thickness of the metal oxide 406b is reduced and the electrical resistance of the metal oxide 406b is increased in the manufacturing process of the transistor 200, metal oxidation is not performed in the regions 426b and 426c. Object 406a is sufficiently low resistive that regions 426b and 426c of metal oxide 406 can serve as source and drain regions.

An enlarged view of the vicinity of the region 426a shown in FIG. 27(B) is shown in FIG. 28(A). As shown in FIG. 28A, the regions 426b and 426c are formed in regions of the metal oxide 406 that overlap with at least the insulator 225 . Here, one of region 426b and region 426c of metal oxide 406b can function as a source region and the other can function as a drain region. Also, the region 426a of the metal oxide 406b can function as a channel formation region.

Note that although the regions 426a, 426b, and 426c are formed in the metal oxide 406b and the metal oxide 406a in FIGS. 27B and 28A, these regions are at least metal oxide 406b. 27B and the like, the boundary between the regions 426a and 426b and the boundary between the regions 426a and 426c are shown substantially perpendicular to the upper surface of the metal oxide 406; It is not limited to this. For example, the regions 426b and 426c may protrude toward the conductor 404 near the surface of the metal oxide 406b and recede toward the insulator 225 near the bottom surface of the metal oxide 406a.

In the transistor 200, as shown in FIG. 28A, the regions 426b and 426c overlap with the region of the metal oxide 406 which is in contact with the insulator 225 and the regions near both ends of the insulators 418 and 412. It is formed. At this time, portions of the regions 426b and 426c that overlap with the conductor 404 function as so-called overlap regions (also referred to as Lov regions). With the structure including the Lov region, a high-resistance region is not formed between the channel formation region of the metal oxide 406 and the source and drain regions, so that the on-state current and mobility of the transistor can be increased. .

However, the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 28B, a structure in which the regions 426b and 426c overlap with the insulator 225 and the insulator 418 of the metal oxide 406 may be employed. In other words, the structure shown in FIG. 28B is a structure in which the width of the conductor 404 in the channel length direction and the width of the region 426a are substantially the same. With the structure shown in FIG. 28B, a high-resistance region is not formed between the source region and the drain region, so that the on current of the transistor can be increased. Further, with the structure shown in FIG. 28B, the source and drain regions do not overlap with the gate in the channel length direction, so formation of unnecessary capacitance can be suppressed.

Thus, by appropriately selecting the ranges of the regions 426b and 426c, it is possible to easily provide a transistor having electrical characteristics meeting the requirements according to the circuit design.

Insulator 412 is preferably placed in contact with the top surface of metal oxide 406b. The insulator 412 is preferably formed using an insulator from which oxygen is released by heating. By providing such an insulator 412 in contact with the top surface of the metal oxide 406b, oxygen can be effectively supplied to the metal oxide 406b. Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 412 is preferably reduced. The thickness of the insulator 412 is preferably 1 nm or more and 20 nm or less, for example, about 1 nm.

The insulator 412 preferably contains oxygen. For example, in temperature-programmed desorption spectroscopy (TDS analysis), the amount of desorption of oxygen molecules per area of the insulator 412 is measured in a surface temperature range of 100° C. to 700° C. or 100° C. to 500° C. converted to 1×10 ¹⁴ molecules/cm ² or more, preferably 2×10 ¹⁴ molecules/cm ² or more, more preferably 4×10 ¹⁴ molecules/cm ² or more.

Insulator 412, conductor 404, and insulator 419 have regions that overlap metal oxide 406b. In addition, it is preferable that side surfaces of the insulator 412, the conductor 404a, the conductor 404b, and the insulator 419 substantially coincide with each other.

A conductive oxide is preferably used as the conductor 404a. For example, a metal oxide that can be used as metal oxide 406a or metal oxide 406b can be used. In particular, among In-Ga-Zn-based oxides, the atomic ratio of metals with high conductivity [In]:[Ga]:[Zn] = 4:2:3 to 4.1, and values in the vicinity thereof is preferably used. By providing such a conductor 404a, permeation of oxygen to the conductor 404b can be suppressed, and an increase in electrical resistance of the conductor 404b due to oxidation can be prevented.

By forming such a conductive oxide by a sputtering method, oxygen can be added to the insulator 412 and oxygen can be supplied to the metal oxide 406b. Thereby, oxygen vacancies in the region 426a of the metal oxide 406 can be reduced.

A metal such as tungsten can be used for the conductor 404b. As the conductor 404b, a conductor that can improve the conductivity of the conductor 404a by adding an impurity such as nitrogen to the conductor 404a may be used. For example, the conductor 404b is preferably made of titanium nitride or the like. Alternatively, the conductor 404b may have a structure in which a metal nitride such as titanium nitride and a metal such as tungsten are stacked thereon.

Here, a conductor 404 functioning as a gate electrode is provided with an insulator 412 interposed therebetween so as to cover the upper surface of the metal oxide 406b near the region 426a and side surfaces in the channel width direction. Therefore, the electric field of the conductor 404 functioning as a gate electrode can electrically surround the upper surface and side surfaces in the channel width direction near the region 426a of the metal oxide 406b. A transistor structure in which a channel formation region is electrically surrounded by an electric field of the conductor 404 is called a surrounded channel (s-channel) structure. Therefore, a channel can be formed on the upper surface and side surfaces of the metal oxide 406b near the region 426a in the channel width direction. You can make it bigger. In addition, since the upper surface and side surfaces in the channel width direction of the metal oxide 406b in the vicinity of the region 426a are surrounded by the electric field of the conductor 404, leakage current (off current) during non-conduction can be reduced.

An insulator 419 is preferably placed over the conductor 404b. Further, it is preferable that the insulator 419, the conductor 404a, the conductor 404b, and the insulator 412 have substantially the same side surface. The insulator 419 is preferably deposited using an atomic layer deposition (ALD) method. Accordingly, the insulator 419 can be formed with a thickness of about 1 nm to 20 nm, preferably about 5 nm to 10 nm. Here, similarly to the insulator 418, the insulator 419 is preferably formed using an insulating material that has a function of suppressing permeation of impurities such as water or hydrogen and oxygen. For example, aluminum oxide, hafnium oxide, or the like is used. It is preferable to use

By providing such an insulator 419, the top surface and side surfaces of the conductor 404 can be covered with the insulator 419 and the insulator 418 which have a function of suppressing permeation of impurities such as water or hydrogen and oxygen. Accordingly, impurities such as water or hydrogen can be prevented from entering the metal oxide 406 through the conductor 404 . Thus, the insulator 418 and the insulator 419 function as gate caps that protect the gate.

The insulator 418 is provided in contact with side surfaces of the insulator 412 , the conductor 404 , and the insulator 419 . In addition, it is preferable that the top surface of the insulator 418 substantially coincides with the top surface of the insulator 419 . The insulator 418 is preferably deposited using an ALD method. Accordingly, the thickness of the insulator 418 can be about 1 nm to 20 nm, preferably about 1 nm to 3 nm, for example, 1 nm.

As described above, the regions 426b and 426c of the metal oxide 406 are formed by the impurity element added when the insulator 225 is deposited. When a transistor is miniaturized and has a channel length of about 10 nm to 30 nm, an impurity element contained in a source region or a drain region may diffuse to electrically connect the source region and the drain region. In contrast, by forming the insulator 418 as shown in this embodiment mode, the distance between the regions of the metal oxide 406 which are in contact with the insulator 225 can be increased. It is possible to prevent the drain region from becoming electrically conductive. Furthermore, by forming the insulator 418 by ALD, the film thickness is made to be equal to or less than the length of the miniaturized channel, and the distance between the source region and the drain region is increased more than necessary, resulting in an increase in resistance. You can prevent it.

Here, for the insulator 418, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen, such as aluminum oxide or hafnium oxide, is preferably used. Thus, oxygen in the insulator 412 can be prevented from diffusing to the outside. In addition, entry of impurities such as hydrogen and water into the metal oxide 406 from the edge of the insulator 412 or the like can be suppressed.

The insulator 418 is formed by forming an insulating film by an ALD method and performing anisotropic etching to remove portions of the insulating film which are in contact with side surfaces of the insulator 412, the conductor 404, and the insulator 419. It is preferable to form by leaving This makes it possible to easily form an insulator having a small film thickness as described above. Further, at this time, by providing the insulator 419 on the conductor 404, even if the insulator 419 is partially removed by the anisotropic etching, the insulator 412 and the conductor 404 of the insulator 418 remain unchanged. It is possible to sufficiently leave the portion in contact with the

Insulator 225 is provided over insulator 419 , insulator 418 , metal oxide 406 , and insulator 224 . Here, the insulator 225 is provided in contact with the upper surfaces of the insulator 419 and the insulator 418 and in contact with the side surface of the insulator 418 . Insulator 225 adds impurities such as hydrogen or nitrogen to metal oxide 406 to form regions 426b and 426c, as described above. Therefore, the insulator 225 preferably contains at least one of hydrogen and nitrogen.

Further, the insulator 225 is preferably provided in contact with the side surfaces of the metal oxide 406b and the side surfaces of the metal oxide 406a in addition to the top surface of the metal oxide 406b. Thus, in the regions 426b and 426c, the side surfaces of the metal oxide 406b and the side surfaces of the metal oxide 406a can be reduced in resistance.

For the insulator 225, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum nitride, aluminum nitride oxide, or the like is preferably used as the insulator 225 . By forming the insulator 225 in such a manner, oxygen can penetrate through the insulator 225 and supply oxygen to oxygen vacancies in the regions 426b and 426c, which can prevent a decrease in carrier density. . In addition, it is possible to prevent impurities such as water or hydrogen from penetrating through the insulator 225 and excessive expansion of the regions 426b and 426c toward the region 426a.

An insulator 280 is preferably provided over the insulator 225 . As with the insulator 224 and the like, the insulator 280 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

The conductors 450a and 451a and the conductors 450b and 451b are arranged in openings formed in the insulators 280 and 225, respectively. It is preferable that the conductors 450a and 451a and the conductors 450b and 451b face each other with the conductor 404 interposed therebetween.

A conductor 450a is formed in contact with the inner walls of the openings of the insulator 280 and the insulator 225, and a conductor 451a is further formed inside. A region 426b of the metal oxide 406 is located in at least part of the bottom of the opening, and the conductor 450a is in contact with the region 426b. Similarly, a conductor 450b is formed in contact with the inner walls of the openings of insulator 280 and insulator 225, and a conductor 451b is formed inside. A region 426c of the metal oxide 406 is located in at least part of the bottom of the opening, and the conductor 450b is in contact with the region 426c.

Here, FIG. 29A shows a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 27A. Note that although FIG. 29A shows a cross-sectional view of the conductor 450b and the conductor 451b, the structures of the conductor 450a and the conductor 451a are the same.

As shown in FIGS. 27B and 29A, the conductor 450b is preferably in contact with at least the top surface of the metal oxide 406 and further in contact with the side surfaces of the metal oxide 406. FIG. In particular, as shown in FIG. 29A, the conductor 450b is preferably in contact with both or one of the A5 side and the A6 side of the metal oxide 406 in the channel width direction. Alternatively, as shown in FIG. 27B, the conductor 450b may be in contact with the side surface of the metal oxide 406 on the A2 side in the channel length direction. In this manner, the conductor 450b is in contact with the side surface of the metal oxide 406 in addition to the upper surface of the metal oxide 406, so that the upper surface area of the contact portion between the conductor 450b and the metal oxide 406 is not increased. , the contact area of the contact portion can be increased, and the contact resistance between the conductor 450b and the metal oxide 406 can be reduced. As a result, the on current can be increased while miniaturizing the source electrode and the drain electrode of the transistor. Note that the same applies to the conductors 450a and 451a.

Here, conductor 450a is in contact with region 426b that functions as one of the source and drain regions of transistor 200, and conductor 450b is in contact with region 426c that functions as the other of the source and drain regions of transistor 200. . Thus, the conductors 450a and 451a can function as one of the source and drain electrodes, and the conductors 450b and 451b can function as the other of the source and drain electrodes. Since the regions 426b and 426c have low resistance, the contact resistance between the conductor 450a and the region 426b and the contact resistance between the conductor 450b and the region 426c can be reduced, and the on current of the transistor 200 can be increased.

Here, for the conductors 450a and 450b, similarly to the conductor 310a and the like, it is preferable to use a conductive material having a function of suppressing permeation of impurities such as water or hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used, and a single layer or stacked layers may be used. Thus, impurities such as hydrogen and water can be prevented from entering the metal oxide 406 from a layer above the insulator 280 through the conductors 451a and 451b.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductors 451a and 451b. Although not shown, the conductors 451a and 451b may have a stacked structure, for example, a stacked layer of titanium or titanium nitride and any of the above conductive materials.

27B and 29A, the conductor 450a and the conductor 450b are in contact with both the metal oxide 406a and the metal oxide 406b; It may be configured to contact only the object 406b. Further, the heights of the top surfaces of the conductor 450a, the conductor 451a, the conductor 450b, and the conductor 451b can be made substantially the same. Further, although the transistor 200 has a structure in which the conductors 450a and 451a are stacked and the conductors 450b and 451b are stacked, the present invention is not limited to this. For example, only the conductor 451a and the conductor 451b may be provided.

27B and 29A, the insulator 224 is the bottom of the opening in which the conductor 450b (the conductor 450a) is provided; however, this embodiment is limited to this. is not. As shown in FIG. 29B, the insulator 222 may be the bottom of the opening in which the conductors 450a and 450b are provided. In the case shown in FIG. 29A, the conductor 450b (the conductor 450a) is in contact with the insulator 224, the metal oxide 406a, the metal oxide 406b, the insulator 225, and the insulator 280. In the case shown in FIG. 29B, the conductor 450b (the conductor 450a) is in contact with the insulator 222, the insulator 224, the metal oxide 406a, the metal oxide 406b, the insulator 225, and the insulator 280.

Next, constituent materials of the transistor 200 will be described.

<<Substrate>>
As a substrate for forming the transistor 200, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), resin substrates, and the like. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitive element, a resistance element, a switch element, a light emitting element, a memory element, and the like.

Also, a flexible substrate may be used as the substrate. Note that as a method for providing a transistor over a flexible substrate, there is also a method in which after manufacturing a transistor over a non-flexible substrate, the transistor is peeled off and transferred to a substrate that is a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. As the substrate, a sheet, film, foil, or the like in which fibers are woven may be used. Also, the substrate may have stretchability. The substrate may also have the property of returning to its original shape when bending or pulling is ceased. Alternatively, it may have the property of not returning to its original shape. The substrate has a region with a thickness of, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less, more preferably 15 μm or more and 300 μm or less. By thinning the substrate, the weight of a semiconductor device having a transistor can be reduced. Further, by making the substrate thin, even when glass or the like is used, it may have elasticity, or may have the property of returning to its original shape when bending or pulling is stopped. As a result, it is possible to mitigate the impact or the like applied to the semiconductor device on the substrate due to dropping or the like. That is, a durable semiconductor device can be provided.

As the flexible substrate, for example, metal, alloy, resin, glass, or fiber thereof can be used. The substrate, which is a flexible substrate, preferably has a lower coefficient of linear expansion because deformation due to the environment is suppressed. As the flexible substrate, for example, a material having a coefficient of linear expansion of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. . Examples of resins include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like. In particular, aramid has a low coefficient of linear expansion, so it is suitable as a flexible substrate.

<<insulator>>
As insulators, oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, metal oxynitrides, and the like having insulating properties are given.

By surrounding a transistor with an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized. For example, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used as the insulator 222 and the insulator 214 .

Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks.

Further, for example, the insulator 222 and the insulator 214 include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide; Silicon oxide, silicon nitride, or the like may be used. Note that the insulators 222 and 214 preferably contain aluminum oxide, hafnium oxide, or the like.

Insulator 384, insulator 216, insulator 220, insulator 224, and insulator 412 include, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, Insulators including yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks. For example, insulator 384, insulator 216, insulator 220, insulator 224, and insulator 412 preferably include silicon oxide, silicon oxynitride, or silicon nitride.

Insulator 220, insulator 222, insulator 224, and/or insulator 412 preferably have an insulator with a high dielectric constant. For example, insulator 220, insulator 222, insulator 224, and/or insulator 412 may be gallium oxide, hafnium oxide, zirconium oxide, oxides with aluminum and hafnium, oxynitrides with aluminum and hafnium, silicon and/or It is preferable to have an oxide containing hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, or the like. Alternatively, the insulator 220, the insulator 222, the insulator 224, and/or the insulator 412 preferably have a stacked-layer structure of silicon oxide or silicon oxynitride and an insulator with a high relative dielectric constant. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure with a thermally stable high dielectric constant can be obtained by combining them with an insulator with a high dielectric constant. For example, the insulator 224 and the insulator 412 have a structure in which aluminum oxide, gallium oxide, or hafnium oxide is in contact with the metal oxide 406 , so that silicon contained in silicon oxide or silicon oxynitride enters the metal oxide 406 . can be suppressed. Further, for example, in the insulator 224 and the insulator 412, silicon oxide or silicon oxynitride is in contact with the metal oxide 406, so that aluminum oxide, gallium oxide, or hafnium oxide, silicon oxide, or silicon oxynitride, A trap center may be formed at the interface of The trap center may be able to shift the threshold voltage of the transistor in the positive direction by trapping electrons.

Insulator 384, insulator 216, and insulator 280 preferably have an insulator with a low dielectric constant. For example, insulator 384, insulator 216, and insulator 280 may be silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped It is preferable to use silicon oxide, silicon oxide having pores, resin, or the like. Alternatively, insulator 384, insulator 216, and insulator 280 can be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped It preferably has a layered structure of silicon oxide or silicon oxide having holes and a resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, and the like.

As the insulator 418 and the insulator 419, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used. Examples of the insulators 418 and 419 include metal oxides such as aluminum oxide, hafnium oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, and silicon nitride oxide. Alternatively, silicon nitride or the like may be used.

<<Conductor>>
Conductors 404a, 404b, 310a, 310b, 450a, 450b, 451a and 451b include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, A material containing one or more metal elements selected from titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

A conductive material containing oxygen and a metal element contained in a metal oxide that can be applied to the metal oxide 406 is used for the conductors, particularly the conductors 404a, 310a, 450a, and 450b. may Alternatively, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide 406 can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed in from an outer insulator or the like.

Alternatively, a plurality of conductive layers formed using any of the above materials may be stacked and used. For example, a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used. Alternatively, a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined. Alternatively, a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.

Note that in the case where oxide is used for a channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the metal element described above and a conductive material containing oxygen are combined for the gate electrode. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

<<Metal Oxide Applicable to Metal Oxide 406>>
The metal oxide 406 according to the present invention will be described below. A metal oxide that functions as an oxide semiconductor is preferably used as the metal oxide 406 .

Metal oxide 406 preferably contains at least indium or zinc. Indium and zinc are particularly preferred. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Now consider the case where metal oxide 406 comprises indium, element M and zinc. Note that [In], [M], and [Zn] are the terms of the atomic ratios of indium, the element M, and zinc in the metal oxide 406, respectively.

A preferable range of the atomic number ratio of indium, element M, and zinc in the metal oxide 406 will be described below with reference to FIGS. 30A, 30B, and 30C. Note that the atomic ratio of oxygen is not shown in FIGS. 30A, 30B, and 30C. In addition, [In], [M], and [Zn] are the terms of the atomic ratios of indium, the element M, and zinc in the metal oxide 406, respectively.

In FIGS. 30(A), 30(B), and 30(C), the dashed lines indicate the atomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):1. (-1 ≤ α ≤ 1), a line [In]: [M]: [Zn] = (1 + α): (1-α): a line with an atomic ratio of 2, [In]: [M] : [Zn] = (1 + α): (1-α): A line with an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 atomic number A line that gives a ratio and a line that gives an atomic number ratio of [In]:[M]:[Zn]=(1+α):(1−α):5.

In addition, the dashed-dotted line is a line with an atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0), [In]:[M]:[Zn]=2: A line with an atomic ratio of 1:β, [In]:[M]:[Zn]=1:1: A line with an atomic ratio of β, [In]:[M]:[Zn]=1: A line with an atomic ratio of 2:β, a line with an atomic ratio of [In]:[M]:[Zn]=1:3:β, and [In]:[M]:[Zn]=1 : represents a line with an atomic number ratio of 4:β.

30(A), 30(B), and 30(C), the atomic number ratio of [In]:[M]:[Zn]=0:2:1 and its neighboring values Metal oxides tend to have a spinel crystal structure.

Moreover, a plurality of phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is close to [In]:[M]:[Zn]=0:2:1, two phases, a spinel crystal structure and a layered crystal structure, tend to coexist. Moreover, when the atomic number ratio is close to [In]:[M]:[Zn]=1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure tend to coexist. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

Region A shown in FIG. 30A shows an example of a preferred range of the atomic number ratio of indium, element M, and zinc in metal oxide 406 .

By increasing the indium content of the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide with a high indium content has higher carrier mobility than a metal oxide with a low indium content.

On the other hand, lower contents of indium and zinc in the metal oxide result in lower carrier mobility. Therefore, when the atomic number ratio is [In]:[M]:[Zn]=0:1:0 and its neighboring values (for example, region C shown in FIG. 30(C)), the insulating property is high. .

For example, the metal oxide used for the metal oxide 406b preferably has an atomic ratio shown in region A in FIG. 30A and has high carrier mobility. The metal oxide used for the metal oxide 406b may be, for example, In:Ga:Zn=4:2:3 to 4.1 and its approximate values. On the other hand, the metal oxide used for the metal oxide 406a preferably has relatively high insulating properties and has an atomic ratio shown in region C in FIG. The metal oxide used for the metal oxide 406a may have, for example, In:Ga:Zn=1:3:4.

In particular, in the region B shown in FIG. 30B, even in the region A, an excellent metal oxide with high carrier mobility and high reliability can be obtained.

Note that region B includes [In]:[M]:[Zn]=4:2:3 to 4.1 and their neighboring values. Neighborhood values include, for example, [In]:[M]:[Zn]=5:3:4. Also, region B has [In]:[M]:[Zn]=5:1:6 and its neighboring values, and [In]:[M]:[Zn]=5:1:7 and its Contains neighborhood values.

Further, when In--M--Zn oxide is used as the metal oxide 406, it is preferable to use a target containing polycrystalline In--M--Zn oxide as the sputtering target. The atomic ratio of the metal oxide to be deposited includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide 406 is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the metal oxide to be deposited is In:Ga:Zn. = 4:2:3 [atomic number ratio]. When the composition of the sputtering target used for the metal oxide 406 is In:Ga:Zn=5:1:7 [atomic ratio], the composition of the metal oxide to be deposited is In:Ga:Zn=5. : in the vicinity of 1:6 [atomic number ratio].

The properties of metal oxides are not uniquely determined by the atomic number ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when the metal oxide 406 is deposited using a sputtering apparatus, a film having an atomic ratio different from that of the target is formed. Also, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Thus, the illustrated regions are regions exhibiting atomic ratios where metal oxides tend to have particular properties, and the boundaries of regions A through C are not strict.

<<Structure of Metal Oxide>>
A configuration of a CAC (Cloud-Aligned Composite)-OS that can be used for an OS transistor is described below.

In this specification and the like, it may be referred to as CAAC (c-axis aligned crystal) and CAC (cloud-aligned composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. Note that when CAC-OS or CAC-metal oxide is used for an active layer of a transistor, the function of conductivity is to flow electrons (or holes) that serve as carriers, and the function of insulation is to flow electrons that serve as carriers. It is a function that does not flow A switching function (on/off function) can be imparted to the CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

CAC-OS or CAC-metal oxide also has a conductive region and an insulating region. The conductive regions have the above-described conductive function, and the insulating regions have the above-described insulating function. In some materials, the conductive region and the insulating region are separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected like a cloud with its periphery blurred.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. There is

Also, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from an insulating region and a component having a narrow gap resulting from a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having a narrow gap acts complementarily on the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for the channel region of a transistor, high current drivability, that is, large on-current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

<<Structure of Metal Oxide>>
Oxide semiconductors are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors include, for example, CAAC-OS (c-axis aligned crystalline oxide semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline oxide semiconductors), pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductor), amorphous oxide semiconductor, and the like.

CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. Also, the distortion may have a lattice arrangement of pentagons, heptagons, or the like. In CAAC-OS, a clear crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It is considered to be for

CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is substituted with indium, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is an oxide semiconductor with high crystallinity. On the other hand, since a clear grain boundary cannot be confirmed in CAAC-OS, it can be said that the decrease in electron mobility caused by the grain boundary is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor may deteriorate due to contamination with impurities, generation of defects, or the like, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor including CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Also, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

An a-like OS is an oxide semiconductor having a structure between an nc-OS and an amorphous oxide semiconductor. An a-like OS has void or low density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors have various structures and each has different characteristics. An oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

<<Transistor Including Metal Oxide>>
Next, the case where the above metal oxide is used for a transistor is described.

Note that by using the above metal oxide for a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

Also, for transistors, it is preferable that the carrier density in region 426a of metal oxide 406b is low. In the case of lowering the carrier density of the metal oxide, the impurity concentration in the metal oxide should be lowered to lower the defect level density. In this specification and the like, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the carrier density in region 426a of metal oxide 406b is less than 8×10 ¹¹ /cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ /cm ³ , and 1×10 ⁻⁹ /cm ³ or more.

In addition, since a highly pure intrinsic or substantially highly pure intrinsic metal oxide has a low defect level density, the trap level density may also be low.

In addition, the charge trapped in the trap level of the metal oxide takes a long time to disappear, and may behave like a fixed charge. Therefore, a transistor whose channel region is formed in an oxide semiconductor with a high trap level density might have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the region 426a of the metal oxide 406b. Moreover, in order to reduce the impurity concentration in the region 426a of the metal oxide 406b, it is preferable to also reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

<<Impurities>>
Here, the effect of each impurity in the metal oxide will be described.

If the metal oxide contains silicon or carbon, which is one of the Group 14 elements, a defect level is formed in the metal oxide. Therefore, the concentration of silicon or carbon (concentration obtained by SIMS) in the region 426a of the metal oxide 406b is set to 2×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁷ atoms/cm ³ or less.

Further, if the metal oxide contains an alkali metal or an alkaline earth metal, it may form a defect level and generate carriers. Therefore, transistors using metal oxides containing alkali metals or alkaline earth metals tend to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in region 426a of metal oxide 406b. Specifically, the concentration of alkali metal or alkaline earth metal in region 426a of metal oxide 406b obtained by SIMS is 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less. to

In addition, when nitrogen is contained in the metal oxide, electrons as carriers are generated, the carrier density increases, and the metal oxide tends to be n-type. As a result, a transistor in which nitrogen is contained in the region 426a of the metal oxide 406b tends to have normally-on characteristics. Therefore, nitrogen is preferably reduced as much as possible in the region 426a of the metal oxide 406b. For example, the nitrogen concentration in the region 426a of the metal oxide 406b is less than 5×10 ¹⁹ atoms/cm ³ in SIMS. , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and still more preferably 5×10 ¹⁷ atoms/cm ³ or less.

In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor in which a large amount of hydrogen is contained in the region 426a of the metal oxide 406b tends to have normally-on characteristics. Therefore, hydrogen in region 426a of metal oxide 406b is preferably reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm Less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By sufficiently reducing impurities in the region 426a of the metal oxide 406b, the transistor can have stable electrical characteristics.

<Transistor 201>
Next, as a structural example different from that of the transistor 200, details of the transistor 201 are described.

FIG. 31A is a top view of a semiconductor device having a transistor 201. FIG. 31B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 31A, and is also a cross-sectional view of the transistor 201 in the channel length direction. FIG. 31C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 31A, and is also a cross-sectional view of the transistor 201 in the channel width direction. In the top view of FIG. 31A, some elements are omitted for clarity of illustration. Further, among the constituent elements of the transistor 201, the constituent elements common to those of the transistor 200 are denoted by the same reference numerals.

As shown in FIGS. 31A-31C, transistor 201 includes an insulator 224 overlying a substrate (not shown), a metal oxide 406a overlying insulator 224, A metal oxide 406b arranged in contact with at least part of the top surface of the metal oxide 406a, a conductor 452a and a conductor 452b arranged in contact with at least part of the top surface of the metal oxide 406b, and a metal oxide a metal oxide 406c in contact with at least part of the top surface of 406b and disposed over conductors 452a and 452b; an insulator 413 disposed over metal oxide 406c; It has a conductor 405a arranged, a conductor 405b arranged over the conductor 405a, and an insulator 420 arranged over the conductor 405b.

Conductor 405 (conductor 405a and conductor 405b) can function as a top gate and conductor 310 can function as a back gate. The potential of the back gate may be the same potential as that of the top gate, the ground potential, or any other potential. In addition, by changing the potential of the back gate independently of the potential of the top gate, the threshold voltage of the transistor can be changed.

The conductor 405a can be provided using a material similar to that of the conductor 404a in FIG. The conductor 405b can be provided using a material similar to that of the conductor 404b in FIG.

The conductor 452a functions as one of the source and drain electrodes, and the conductor 452b functions as the other of the source and drain electrodes.

For the conductors 452a and 452b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing any of these as its main component can be used. In addition, although a single-layer structure is shown in the drawing, a laminated structure of two or more layers may be used. Alternatively, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

In transistor 201, the channel is preferably formed in metal oxide 406b. Therefore, it is preferable that the metal oxide 406c use a material with relatively higher insulating properties than the metal oxide 406b. A material similar to that of the metal oxide 406a may be used for the metal oxide 406c.

By providing the metal oxide 406c, the transistor 201 can be a buried channel transistor. In addition, oxidation of the end portions of the conductors 452a and 452b can be prevented. Further, leakage current between the conductor 405 and the conductor 452a (or the conductor 405 and the conductor 452b) can be prevented. Note that the metal oxide 406c may be omitted in some cases.

For the insulator 420, an insulating material having a function of suppressing permeation of impurities such as water or hydrogen and oxygen is preferably used. For example, the insulator 420 includes metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, silicon nitride, or the like. You can use it.

By providing the insulator 420 in the transistor 201, oxidation of the conductor 405 can be prevented. In addition, impurities such as water or hydrogen can be prevented from entering the metal oxide 406 .

Compared to the transistor 200, the transistor 201 can have a larger contact area between the metal oxide 406b and an electrode (source electrode or drain electrode). Further, the step of forming the regions 426b and 426c shown in FIG. 27 is not required. Therefore, the transistor 201 can have a higher on-state current than the transistor 200 . Moreover, the manufacturing process can be simplified.

For details of other components of the transistor 201, refer to the description of the transistor 200. FIG.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 5)
In this embodiment, the display element included in the display portion PA described in Embodiment 1 will be described.

FIG. 32A illustrates a pixel circuit using a liquid crystal element as a display element. The pixel circuit 306 has a display element 301, a transistor M1, and a capacitor element _CsLC . Note that the first terminal of the display element 301 corresponds to a pixel electrode, and the second terminal of the display element 301 corresponds to a common electrode. Further, FIG. 32A illustrates a signal line SL electrically connected to the pixel circuit 306 and a gate line GL.

One of the source and the drain of the transistor M1 is electrically connected to the first terminal of the display element 301, the other of the source and the drain of the transistor M1 is electrically connected to the signal line SL, and the gate of the transistor M1 is the gate. It is electrically connected with the line GL. Additionally, the first terminal of the capacitive element _CsLC is electrically connected to the first terminal of the transistor M1.

A second terminal of the display element 301 is electrically connected to a wiring for applying a common potential for driving the display element 301 . In addition, the second terminal of the capacitive element _CsLC is electrically connected to a wiring that provides a reference potential.

An OS transistor is preferably used as the transistor M1. Hereinafter, as a representative example of a transistor, a transistor including an oxide semiconductor (OS transistor), which is one of metal oxides, will be described. Since the OS transistor has extremely low leakage current (off current) when it is in a non-conducting state, electric charge can be held in the pixel electrode of the liquid crystal element when the OS transistor is in a non-conducting state.

Note that by utilizing the characteristics of the OS transistor that the off current in the non-conducting state is extremely low, the display device having the pixel circuit 306 can be operated at a higher frame frequency than a normal frame frequency (typically 60 Hz or more and 240 Hz or less). It can be driven at a low frame frequency. Below, a normal operation mode (Normal mode) operating at a normal frame frequency and an idling stop (IDS) drive mode operating at a low frame frequency will be exemplified and explained.

Note that the idling stop (IDS) driving mode is a driving method in which rewriting of image data is stopped after execution of image data writing processing. By extending the interval between writing the image data once and then writing the next image data, the power consumption required for writing the image data during that period can be reduced. The idling stop (IDS) driving mode can be, for example, about 1/100 to 1/10 the frame frequency of the normal operation mode.

FIGS. 32B and 32C are timing charts for explaining the normal drive mode and the idling stop (IDS) drive mode, respectively.

FIG. 32B is a timing chart showing waveforms of signals respectively applied to signal line SL and gate line GL in the normal drive mode. The normal drive mode operates at a normal frame frequency (eg, 60 Hz). FIG. _32B shows periods _T1 to T3. In each frame period, _a scanning signal is applied to the gate line GL, and data D1 is written from the signal line SL. This operation is the same when writing the same data _D1 or writing different data in periods _T1 to _T3 .

On the other hand, FIG. 32C is a timing chart showing waveforms of signals respectively applied to signal line SL and gate line GL in the idling stop (IDS) drive mode. The idle stop (IDS) drive operates at a low frame frequency (eg 1 Hz). _One frame period is represented by a period T1, a data write period is represented by a period T _W , and a data retention period is represented by a period T _RET . In the idling stop (IDS) drive mode, a scanning signal is applied to the gate line GL during the period _{TW, data D1 is written in the signal line SL, the gate line GL is fixed at a low level voltage during the period TRET , and} the transistor An operation of holding data D1 _once written by making M1 non-conductive is performed.

Compared to the normal drive mode, the idling stop (IDS) drive mode can reduce the number of times image data is written to the pixel circuit 306, so power consumption can be reduced.

FIG. 32D illustrates a pixel circuit using an organic EL element as a display element. A pixel circuit 307 includes a display element 302, a transistor M2, a transistor M3, and a capacitor Cs _EL . In addition, FIG. 32D illustrates a signal line DL electrically connected to the pixel circuit 307, a gate line GL2, and a current supply line AL.

An OS transistor is preferably used as the transistor M2, similarly to the transistor M1. Since the OS transistor has extremely low leakage current (off current) when it is in a non-conducting state, the charge stored in the capacitor Cs _EL can be held by making the OS transistor non-conducting. In other words, the gate-drain voltage of the transistor M3 can be kept constant, and the emission intensity of the display element 302 can be kept constant.

Therefore, similarly to the case where the display element 301 is driven by idling stop (IDS), the idling stop (IDS) driving of the display element 302 is performed by applying a scanning signal to the gate line GL2 and writing data from the signal line DL. Later, by fixing the gate line GL2 to a low-level voltage, the transistor M2 is turned off, and the once written data is held.

By applying an OS transistor to the transistor M2, the pixel circuit 307 can also operate in an idling stop (IDS) driving mode in the same manner as the pixel circuit 306. FIG. Therefore, compared to the normal drive mode, the number of times image data is written to the pixel circuit 307 can be reduced, so that power consumption can be reduced.

Note that the transistor M3 is preferably made of the same material as the transistor M2. By using the same material for the transistor M3 and the transistor M2, the manufacturing process of the pixel circuit 307 can be shortened.

Materials that can be applied to the semiconductor layers of the transistor M1, the transistor M2, and the transistor M3 preferably include amorphous semiconductors, particularly hydrogenated amorphous silicon (a-Si:H), other than metal oxides. Since a transistor using an amorphous semiconductor can be easily applied to a large-sized substrate, for example, when manufacturing a large-screen display device compatible with 2K, 4K, 8K broadcasting, etc., the manufacturing process can be simplified.

This embodiment can be appropriately combined with the description of other embodiments.

(Embodiment 6)
In this embodiment, product examples to which the electronic devices described in the above embodiments are applied will be described.

FIG. 33A is a perspective view showing a television device. The television apparatus includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, sensors 9007 (force, displacement, position, speed, acceleration, angular velocity, rotation (Including the ability to measure numbers, distances, light, liquids, magnetism, temperature, chemicals, sounds, time, hardness, electric fields, currents, voltages, power, radiation, flow rates, humidity, gradients, vibrations, odors, or infrared rays) etc. A television apparatus may incorporate a display 9001 with a large screen, eg, 50 inches or more, or 100 inches or more. By applying the semiconductor device of one embodiment of the present invention to the television device illustrated in FIG. 33A, the circuit configuration of the television device can be simplified.

FIG. 33B shows an example of an electronic signboard (digital signage) that can be attached to a wall. FIG. 33B shows how the electronic signboard 6200 is attached to the wall 6201 . By applying the semiconductor device of one embodiment of the present invention to the electronic signboard illustrated in FIG. 33B, the circuit configuration of the electronic signboard can be simplified.

FIG. 33C illustrates a tablet information terminal including a housing 5221 , a display portion 5222 , operation buttons 5223 , and speakers 5224 . A display device having a function as a position input device may be used as the display unit 5222 . A function as a position input device can be added by providing a touch panel to the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element, also called a photosensor, in a pixel portion of the display device. Further, the operation button 5223 can include any of a power switch for starting the information terminal, a button for operating an application of the information terminal, a volume adjustment button, a switch for turning on/off the display portion 5222, and the like. Although the information terminal shown in FIG. 33C has four operation buttons 5223, the number and arrangement of the operation buttons of the information terminal are not limited to four. Further, although not shown, the information terminal shown in FIG. 33C may be configured to have a camera. Although not shown, the information terminal shown in FIG. 33C may have a structure including a flashlight or a light-emitting device for illumination. Although not shown, the information terminal shown in FIG. , temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell, infrared rays, etc.) . In particular, by providing a detection device having a sensor for detecting inclination such as a gyro or an acceleration sensor, the orientation of the information terminal shown in FIG. It is possible to automatically switch the screen display of the display unit 5222 according to the orientation of the information terminal. By applying the semiconductor device of one embodiment of the present invention to the information terminal illustrated in FIG. 33C, the circuit configuration of the information terminal can be simplified.

For example, in this specification and the like, a display device, a display device that is a device having a display device, a light-emitting device, and a light-emitting device that is a device that has a light-emitting device may use various forms or include various elements. can be done. Display elements, display devices, light-emitting elements or light-emitting devices are, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips, green LED chip, blue LED chip, etc.), transistor (transistor that emits light according to current), plasma display panel (PDP), electron emission device, display device using carbon nanotube, liquid crystal device, electronic ink, electrowetting device , electrophoresis element, display element using MEMS (micro-electro-mechanical system) (e.g., grating light valve (GLV), digital micromirror device (DMD), DMS (digital micro-shutter), MIRASOL (registered trademark), an IMOD (interferometric modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, a piezoelectric ceramic display, etc.), or a quantum dot. In addition to these, the display element, the display device, the light-emitting element, or the light-emitting device may have a display medium whose contrast, luminance, reflectance, transmittance, and the like are changed by electrical or magnetic action. An example of a display device using an EL element is an EL display. Examples of display devices using electron-emitting devices include a field emission display (FED) or an SED flat panel display (SED: Surface-conduction Electron-emitter Display). Examples of display devices using liquid crystal elements include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, and projection liquid crystal displays). An example of a display device using electronic ink, electronic liquid powder (registered trademark), or an electrophoretic element is electronic paper. An example of a display device using quantum dots for each pixel is a quantum dot display. Note that the quantum dots may be provided not as display elements but as part of the backlight. By using quantum dots, display with high color purity can be performed. In order to realize a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may function as reflective electrodes. For example, some or all of the pixel electrodes may contain aluminum, silver, or the like. Furthermore, in that case, it is also possible to provide a memory circuit such as an SRAM under the reflective electrode. Thereby, power consumption can be further reduced. When an LED chip is used, graphene or graphite may be placed under the electrode of the LED chip or the nitride semiconductor. A plurality of layers of graphene or graphite may be stacked to form a multilayer film. By providing graphene or graphite in this way, a nitride semiconductor, for example, an n-type GaN semiconductor layer having crystals can be easily formed thereon. Further, a p-type GaN semiconductor layer having crystals or the like can be provided thereon to form an LED chip. An AlN layer may be provided between the graphene or graphite and the n-type GaN semiconductor layer having crystals. Note that the GaN semiconductor layer of the LED chip may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED chip can also be formed by a sputtering method. Further, in a display element using MEMS (micro-electro-mechanical system), a space in which the display element is sealed (for example, an element substrate in which the display element is arranged and a A desiccant may be placed between the substrate and the opposing substrate. By arranging the desiccant, it is possible to prevent the MEMS and the like from becoming difficult to move due to moisture and from being easily deteriorated.

This embodiment can be appropriately combined with the description of other embodiments.

10 broadcasting system 11 imaging device 12 transmitting device 13 receiving device 14 display device 20 autoencoder 31 image data 32 attribute information 33 compressed image data 60 TV
61 broadcasting station 62 artificial satellite 63 radio tower 64 antenna 65 antenna 66A radio wave 66B radio wave 67A radio wave 67B radio wave 100 NN circuit 100A NN circuit 100B NN circuit 150 arithmetic processing circuit 161 circuit 163 circuit 164 circuit 165 circuit 200 transistor 201 transistor 214 insulator 216 Insulator 220 Insulator 222 Insulator 224 Insulator 225 Insulator 280 Insulator 301 Display element 302 Display element 306 Pixel circuit 307 Pixel circuit 310 Conductor 310a Conductor 310b Conductor 384 Insulator 404 Conductor 404a Conductor 404b Conductor 405 Conductor 405a Conductor 405b Conductor 406 Metal oxide 406a Metal oxide 406b Metal oxide 406c Metal oxide 412 Insulator 413 Insulator 418 Insulator 419 Insulator 420 Insulator 426a Region 426b Region 426c Region 440 Conductor 440a Conductor 440b Conductor 450a Conductor 450b Conductor 451a Conductor 451b Conductor 452a Conductor 452b Conductor 612 Moving mechanism 613 Moving mechanism 615 Stage 616 Ball screw mechanism 620 Laser oscillator 621 Optical system unit 622 Mirror 623 Microlens array 624 Mask 625 Laser beam 626 Laser beam 627 Laser beam 630 Substrate 640 Amorphous silicon layer 641 Polycrystalline silicon layer 1400 Display device 1411 Substrate 1412 Substrate 1420 Liquid crystal element 1421 Conductive layer 1422 Liquid crystal 1423 Conductive layer 1424a Alignment film 1424b Alignment film 1426 Insulating layer 1430 Transistor 1431 conductive layer 1431a conductive layer 1432 semiconductor layer 1432p semiconductor layer 1433a conductive layer 1433b conductive layer 1434 insulating layer 1435 impurity semiconductor layer 1437 semiconductor layer 1438 connection portion 1439a polarizing plate 1439b polarizing plate 1441 colored layer 1442 light shielding layer 1460 capacitive element 1481 insulating layer 1482 Insulating layer 1483 Insulating layer 1484 Insulating layer 1490 Backlight unit 5221 Housing 5222 Display unit 5223 Operation button 5224 Speaker 6200 Electronic signboard 6201 Wall 9000 Housing 9001 Display unit 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor

Claims (1)

having a transmitting device and a receiving device,
The transmitting device has a first circuit and an encoder,
The receiving device has a decoder,
An autoencoder is configured by the encoder and the decoder,
the first circuit and the encoder are operable to receive first image data;
the first circuit has a function of extracting features of the first image data and generating attribute information representing attributes of the first image data;
The encoder has a function of generating second image data by compressing the first image data by extracting features of the first image data based on the attribute information,
The decoder is a broadcasting system having a function of decompressing the second image data and restoring the first image data based on the attribute information,
The first circuit has a sum-of-products operation circuit,
The sum-of-products operation circuit includes a first transistor , a second transistor, a third transistor, a fourth transistor, a fifth transistor , a first capacitive element , a second capacitive element, and a third capacitive element. has
one of the source and the drain of the first transistor is electrically connected to the first wiring, and the other of the source and the drain is electrically connected to the gate of the second transistor;
the second transistor has one of its source and drain electrically connected to the gate of the fifth transistor and the other of its source and drain electrically connected to a second wiring;
the first capacitive element has one electrode electrically connected to the gate of the second transistor and the other electrode electrically connected to a third wiring;
the third transistor has one of its source and drain electrically connected to the first wiring and the other of its source and drain electrically connected to the gate of the fourth transistor;
one of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor and the other of the source and the drain is electrically connected to the second wiring;
the second capacitive element has one electrode electrically connected to the gate of the fourth transistor and the other electrode electrically connected to a fifth wiring;
the fifth transistor has one of its source and drain electrically connected to a sixth wiring and the other of its source and drain electrically connected to a seventh wiring;
the third capacitive element has one electrode electrically connected to the gate of the fifth transistor and the other electrode electrically connected to an eighth wiring ;
data that is a weighting factor input from the first wiring is held at the gate of the second transistor or the gate of the fourth transistor;
broadcasting system.

Images