JP7204353B2 - Transistors and semiconductor devices - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one aspect of the present invention relates to semiconductor wafers, modules, and electronic devices.

Note that a semiconductor device in this specification and the like refers to all devices that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are examples of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optic devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices, and the like can be said to have semiconductor devices in some cases. .

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition of matter.

Silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials. As oxide semiconductors, for example, not only single-component metal oxides such as indium oxide and zinc oxide, but also multi-component metal oxides are known. In--Ga--Zn oxides (hereinafter also referred to as IGZO) have been extensively studied among multicomponent metal oxides.

Research on IGZO has found a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure, which are neither single crystal nor amorphous, in oxide semiconductors (see Non-Patent Documents 1 to 3). .). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, Non-Patent Document 4 and Non-Patent Document 5 show that even an oxide semiconductor having a crystallinity lower than that of the CAAC structure and the nc structure has minute crystals.

Furthermore, a transistor using IGZO as an active layer has an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic have been reported (see Non-Patent Document 7 and Non-Patent Document 8). .).

S. Yamazaki et al. , "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , "The Proceedings of AM-FPD'13 Digest of Technical Papers", 2013, p. 151-154 S. Yamazaki et al. , "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, "ECS Transactions", 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , "Japanese Journal of Applied Physics", 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , "2015 Symposium on VLSI Technology Digest of Technical Papers", 2015, p. T216-T217 S. Amano et al. , "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p. 626-629

A transistor including an oxide semiconductor in a channel formation region, the transistor including a gate, a source, and a drain; a first insulator is formed below the oxide semiconductor; A second insulator is formed between the oxide semiconductor, and one or both of the first insulator and the second insulator include a layer containing silicon and a layer containing gallium. A transistor comprising: a layer;

An object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics. Another object of one embodiment of the present invention is to provide a highly productive semiconductor device.

An object of one embodiment of the present invention is to provide a semiconductor device capable of holding data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. An object of one embodiment of the present invention is to provide a semiconductor device that can consume less power. An object of one embodiment of the present invention is to provide a novel semiconductor device.

The description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Problems other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the descriptions of the specification, drawings, claims, etc. is.

One embodiment of the present invention is a transistor including an oxide semiconductor in a channel formation region, the transistor includes a gate, a source, and a drain, and a first insulator is formed below the oxide semiconductor. , a second insulator is formed between the gate and the oxide semiconductor, and one or both of the first insulator and the second insulator include a layer containing silicon and gallium. a layer comprising;

One embodiment of the present invention is a transistor including an oxide semiconductor in a channel formation region, the transistor including a first gate, a second gate, a source, and a drain; A first insulator is formed between the semiconductor, a second insulator is formed between the first gate and the oxide semiconductor, and the first insulator and the second insulator are formed between the first gate and the oxide semiconductor. Either or both of the insulators have a layer containing silicon and a layer containing gallium.

In the above, in any one of claim 1 and claim 2, the oxide semiconductor contains indium, zinc, and gallium.

In the above, the oxide semiconductor and the layer containing gallium have a crystal structure.

In the above semiconductor device including the capacitor, the capacitor includes a layer containing silicon and a layer containing gallium which are included in the transistor.

In the above, the capacitor is formed above the transistor.

In the above, the capacitor is formed below the transistor.

The transistor is a semiconductor device including a third insulator and a fourth insulator, the third insulator including aluminum and oxygen, and the fourth insulator comprising: It contains silicon and nitrogen, and one or more of a top surface, a bottom surface, and side surfaces of the transistor are covered with a third insulator and a fourth insulator.

In the above, the third insulator is located inside the fourth insulator.

According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

Alternatively, a semiconductor device capable of holding data for a long time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with a high degree of freedom in design can be provided. Alternatively, a semiconductor device with low power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Effects other than these are self-evident from the descriptions of the specification, drawings, claims, etc., and it is possible to extract effects other than these from the descriptions of the specification, drawings, claims, etc. is.

1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention; 4A and 4B are cross-sectional views illustrating a film formation method according to one embodiment of the present invention; 1A and 1B are cross-sectional views of a metal oxide according to one embodiment of the present invention; 4A and 4B are cross-sectional views illustrating a film formation method according to one embodiment of the present invention; 1A and 1B are a top view and a cross-sectional view illustrating a film formation apparatus according to one embodiment of the present invention; 1A and 1B are cross-sectional views illustrating a film formation apparatus according to one embodiment of the present invention; 4A and 4B illustrate a film formation method according to one embodiment of the present invention; 4A and 4B illustrate ranges of atomic ratios of metal oxides according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1A and 1B are cross-sectional views each illustrating a structure of a memory device according to one embodiment of the present invention; 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention; FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention; FIG. 1A and 1B are schematic diagrams of a semiconductor device according to one embodiment of the present invention; 1A and 1B are schematic diagrams of a memory device according to one embodiment of the present invention; 1A and 1B illustrate electronic devices according to one embodiment of the present invention;

Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily appreciate that the embodiments can be embodied in many different forms and that various changes in form and detail can be made without departing from the spirit and scope thereof. be. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

Also, in the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. The drawings schematically show ideal examples, and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but are sometimes omitted for ease of understanding. In addition, in the drawings, the same reference numerals may be used in common for the same parts or parts having similar functions, and repeated description thereof may be omitted. Moreover, when referring to similar functions, the hatch patterns may be the same and no particular reference numerals may be attached.

In particular, in top views (also referred to as “plan views”) and perspective views, description of some components may be omitted in order to facilitate understanding of the invention. Also, description of some hidden lines may be omitted.

In this specification and the like, the ordinal numbers such as first and second are used for convenience and do not indicate the order of steps or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third". Also, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

In this specification and the like, terms such as “above” and “below” are used for convenience in order to describe the positional relationship between configurations with reference to the drawings. In addition, the positional relationship between the configurations changes appropriately according to the direction in which each configuration is drawn. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately rephrased according to the situation.

For example, in this specification and the like, when X and Y are directly connected and when it is explicitly stated that X and Y are connected, X and Y are electrically The present specification and the like disclose the case where X and Y are functionally connected and the case where X and Y are functionally connected. Therefore, it is assumed that the connection relationships other than the connection relationships shown in the drawings or the text are not limited to the predetermined connection relationships, for example, the connection relationships shown in the drawings or the text.

Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

Also, the functions of the source and the drain may be interchanged when using transistors of different polarities or when the direction of current changes in circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" can be used interchangeably in some cases.

Note that in this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") and the channel width shown in a top view of the transistor. (hereinafter also referred to as “apparent channel width”). For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and its influence cannot be ignored. For example, in a fine transistor in which a gate electrode covers the side surface of a semiconductor, the proportion of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width if the shape of the semiconductor is not accurately known.

In this specification, simply describing the channel width may refer to the apparent channel width. Alternatively, in this specification, simply referring to the channel width may refer to the effective channel width. The values of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

Note that impurities in a semiconductor refer to, for example, substances other than the main components that constitute the semiconductor. For example, an element whose concentration is less than 0.1 atomic percent can be said to be an impurity. When impurities are contained, for example, the DOS (Density of States) of the semiconductor may increase, the crystallinity may decrease, and the like. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main component of , such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water may also function as an impurity. In the case of an oxide semiconductor, for example, oxygen vacancies may be formed due to contamination by impurities. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Note that in this specification and the like, silicon oxynitride contains more oxygen than nitrogen as its composition. Silicon nitride oxide contains more nitrogen than oxygen in its composition.

In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Also, the term “conductor” can be replaced with a conductive film or a conductive layer. Also, the term "semiconductor" can be interchanged with a semiconductor film or a semiconductor layer.

In this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. In addition, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

Note that in this specification, a barrier film is a film that has a function of suppressing permeation of impurities such as water and hydrogen, and oxygen. I may call

In this specification and the like, a metal oxide is a metal oxide in broad terms. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OSs), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, an OS FET or an OS transistor can also be referred to as a transistor including an oxide or an oxide semiconductor.

In this specification and the like, the term “normally off” means that a current per 1 μm of channel width flowing through a transistor when no potential is applied to the gate or when a ground potential is applied to the gate is 1×10 ⁻²⁰ at room temperature. A or less, 1×10 ⁻¹⁸ A or less at 85° C., or 1×10 ⁻¹⁶ A or less at 125° C.

(Embodiment 1)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

<Transistor Structure 1>
An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention is described below. 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 200 and its periphery according to one embodiment of the present invention. 1A is a top view, FIG. 1B is a cross-sectional view corresponding to the dashed-dotted line A1-A2 shown in FIG. 1A, and FIG. . Note that in the top view of FIG. 1A, some elements are omitted for clarity.

A semiconductor device of one embodiment of the present invention includes the transistor 200 and the insulators 212, 214, 216, 280, 282, 284, and 284 serving as interlayer films. have.

[Transistor 200]
As shown in FIG. 1, transistor 200 includes conductor 205 disposed over a substrate (not shown) and embedded in insulator 216 , and a conductor 205 disposed over insulator 216 and conductor 205 . Overlying insulator 222, insulator 224 overlying insulator 222, and oxide 230 overlying insulator 224 (oxide 230a, oxide 230b, and oxide 230c) , an insulator 250 overlying an oxide 230, an insulator 252 overlying the insulator 250, and a conductor 260 overlying the insulator 252 (a conductor 260a and a conductor 260b). and the conductor 240a and the conductor 240b in contact with part of the top surface of the oxide 230b, part of the top surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, the side surface of the conductor 240a, and the conductor 240a, a side surface of the conductor 240b, and an insulator 274 disposed in contact with the top surface of the conductor 240b.

In the transistor 200, the oxide 230 is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor). A transistor including an oxide semiconductor for a channel formation region has extremely low leakage current (off-state current) in a non-conducting state; therefore, a semiconductor device with low power consumption can be provided. In addition, since an oxide semiconductor can be deposited by a sputtering method, an atomic layer deposition (ALD) method, or the like, it can be used for the transistor 200 included in a highly integrated semiconductor device.

For example, as an oxide semiconductor that can be used for the oxide 230, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.). In particular, the element M is preferably aluminum, gallium, yttrium, or tin. As an oxide semiconductor that can be used for the oxide 230, an In--M oxide, an In--Zn oxide, or an M--Zn oxide may be used.

On the other hand, in a transistor using an oxide semiconductor, electrical characteristics are likely to vary due to oxygen vacancies and impurities such as hydrogen, nitrogen, and a metal element in the oxide semiconductor, and reliability may be degraded.

For example, hydrogen contained in an oxide semiconductor reacts with oxygen that bonds to a metal atom to form water, which may cause oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Therefore, a transistor including an oxide semiconductor containing oxygen vacancies is likely to have normally-on characteristics. Therefore, oxygen vacancies in the oxide semiconductor are preferably reduced as much as possible.

Further, oxygen vacancies in the oxide semiconductor may occur, for example, when a metal is used for a structure provided close to the oxide semiconductor, oxygen atoms of the oxide semiconductor are absorbed by the metal. be. Also, the metal that has absorbed the oxygen atoms may be oxidized and have a high resistance. In addition, hydrogen in a structure provided close to an oxide semiconductor may diffuse into the oxide semiconductor to cause oxygen vacancies.

In order to reduce oxygen vacancies in the oxide semiconductor, an oxide containing more oxygen than the stoichiometric composition is preferably placed near the oxide semiconductor. For example, the insulators 250 and 280 preferably have regions in which oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as excess oxygen regions). The excess oxygen diffuses into the oxide semiconductor, so that oxygen vacancies can be compensated.

For example, in the transistor 200 illustrated in FIG. 1, the oxide 230b is in contact with the conductor 240 functioning as the source and drain electrodes. For example, when the conductive material used for the conductor 240 has the property of absorbing oxygen of the oxide 230 or has the property of supplying impurities such as hydrogen, nitrogen, and metal elements to the oxide 230, the oxide A region of 230 in contact with the conductor 240 or the vicinity of the region is partially reduced in resistance due to lack of oxygen or diffusion of impurities. Therefore, the contact resistance between oxide 230 and conductor 240 can be reduced.

On the other hand, in the transistor 200 illustrated in FIG. 1, the conductor 260 functioning as a gate electrode overlaps with the oxide 230 with the insulators 250 and 252 functioning as gate insulators interposed therebetween. For example, if the conductor 260 has the property of absorbing oxygen from the oxide 230 or has the property of supplying impurities such as hydrogen, nitrogen, or metal elements to the oxide 230, oxidation may occur through the gate insulator. There is a high probability that the substance 230 will be deprived of oxygen or impurities will be diffused.

A region of the oxide 230 that overlaps with the conductor 260 has a region where a channel is formed; This may result in poor electrical characteristics of the transistor, such as a shift in In particular, when the transistor 200 is miniaturized, the probability of short-circuiting between the source and the drain increases.

That is, in a transistor including an oxide semiconductor, when impurities and oxygen vacancies are present in a region where a channel is formed in the oxide semiconductor, electrical characteristics are likely to vary, and reliability may be degraded. In addition, when oxygen vacancies are included in a region where a channel is formed in the oxide semiconductor, the transistor tends to have normally-on characteristics. Therefore, it is preferable that impurities and oxygen vacancies in the region where the channel of oxide 230 is formed are reduced as much as possible.

Therefore, the gate insulator preferably contains a film having barrier properties against oxygen, hydrogen, or impurities. Specifically, the transistor 200 illustrated in FIG. 1 has insulators 250 and 252 that serve at least as gate insulators. Here, for the insulator 252 in contact with the conductor 260, a film having a barrier property against oxygen, hydrogen, or impurities is preferably used.

Note that in this specification, a film having a function of suppressing impurity diffusion is referred to as a film through which impurities are difficult to permeate, a film with low impurity permeability, a film having a barrier property against impurities, a barrier film against impurities, or the like. may be called. Similarly, the film having the function of suppressing the diffusion of hydrogen or oxygen is selected from a film impermeable to hydrogen or oxygen, a film having low permeability to hydrogen or oxygen, a film having barrier properties against hydrogen or oxygen, It is sometimes called a barrier film against oxygen.

In particular, when an In--Ga--Zn oxide is used as the oxide 230, gallium oxide is used as the insulator 252, the gallium content is higher than that of the oxide 230b, or an oxide among the In--Ga--Zn oxides. It is preferable to use a material having a higher insulating property than 230b. Since the element forming the insulator 252 and the element forming the oxide 230 are common, for example, even if the element forming the insulator 252 diffuses into the oxide 230, the resistance of the oxide 230 is lowered. does not cause

Specifically, when an In—Ga—Zn oxide having an atomic ratio of In:Ga:Zn=4:2:3 is used as the oxide 230b, the insulator 252 is composed of In:Ga:Zn= An In--Ga--Zn oxide in the vicinity of 1:3:4 [atomic ratio] or In:Ga:Zn=1:3:4 [atomic ratio] can be used. In—Ga—Zn oxide near the above In:Ga:Zn=1:3:4 [atomic number ratio], for example, In:Ga:Zn=1:2.97:2.61 [atomic number ratio], and the like.

In particular, gallium oxide is a high dielectric constant insulating material having a dielectric constant higher than that of silicon nitride, and is a so-called high-k material. As transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulator while maintaining the physical thickness. Therefore, it is possible to reduce the gate potential during transistor operation.

Note that the insulator 252 is formed over the region of the oxide 230 where the channel is formed. As will be described later, the channel formation region preferably has crystallinity. Therefore, in forming the insulator 252, it is preferable to use a film formation method in which film formation damage to the oxide 230 is unlikely to occur. For example, the ALD method is a film formation method that does not easily damage the film formation surface. Therefore, by forming the insulator 252 by the ALD method, film formation damage to the oxide 230 which is a film formation surface can be reduced, and the crystallinity of the oxide 230 can be maintained.

Also, the insulator 252 is formed on the bottom and sides of the opening formed in the insulator 280 or the like. Further, the thickness of the insulator 252 functioning as a gate insulator is preferably uniform at the bottom of the opening. The ALD method is a film forming method that is excellent in covering a structure having steps and unevenness. Therefore, by forming the insulator 252 by the ALD method, the thickness of the insulator 252 can be uniform at the bottom of the opening.

Note that an insulator 250 may be provided between the oxide 230 and the insulator 252 . The insulator 250 adjacent to the oxide 230 preferably contains oxygen released by heating (also referred to as excess oxygen). Alternatively, the insulator 250 preferably has a region where the hydrogen concentration is low and oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). Excess oxygen in the insulator 250 diffuses into the oxide 230 by heat treatment or treatment involving heating in a production process, thereby reducing oxygen vacancies in the oxide 230 and suppressing normally-on of the transistor. can be done.

For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used as the insulator having a low hydrogen concentration and an excess oxygen region. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. Specifically, an insulator having a low hydrogen concentration and an excess oxygen region or excess oxygen has a hydrogen concentration of less than 5×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ²⁰ atoms/cm ³ by SIMS. , more preferably less than 5×10 ¹⁹ atoms/cm ³ . Further, according to TDS (Thermal Desorption Spectroscopy) analysis, the amount of oxygen desorption in terms of oxygen molecules is 2.0×10 ¹⁴ molecules/cm ² or more, preferably 1.0×10 ¹⁵ molecules/cm ² or more. is. The surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C. or in the range of 100° C. to 500° C.

The gate potential during transistor operation can be reduced while maintaining the physical film thickness by making the insulator that functions as a gate insulator into a laminated structure of a high-k material and a thermally stable material. becomes. Moreover, it is possible to obtain a laminated structure that is thermally stable and has a high dielectric constant.

Similar to the structure above, the insulator functioning as the gate insulator, placed between the oxide 230 and the conductor 205 functioning as the gate electrode, has barrier properties against oxygen, hydrogen, or impurities. It preferably includes a membrane. Specifically, the transistor 200 illustrated in FIG. 1 has insulators 222 and 224 that serve at least as gate insulators.

Therefore, for the insulator 222 in contact with the conductor 205, a film having a barrier property against oxygen, hydrogen, or impurities is preferably used. On the other hand, the insulator 224 in contact with the oxide 230 preferably contains oxygen released by heating (also referred to as excess oxygen). Alternatively, the insulator 250 preferably has a region where the hydrogen concentration is low and oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). Also, it is preferable to use a thermally stable material.

The gate potential during transistor operation can be reduced while maintaining the physical film thickness by making the insulator that functions as a gate insulator into a laminated structure of a high-k material and a thermally stable material. becomes. Moreover, it is possible to obtain a laminated structure that is thermally stable and has a high dielectric constant.

As described above, a semiconductor device having stable electrical characteristics can be provided. Further, a highly reliable semiconductor device can be provided. Further, a semiconductor device with low power consumption can be provided.

A detailed structure of the semiconductor device including the transistor 200 according to one embodiment of the present invention is described below.

First, oxide 230 having a region functioning as a channel formation region preferably includes oxide 230a, oxide 230b, and oxide 230c. Specifically, an oxide 230 a is placed between the oxide 230 b and the insulator 224 . In addition, an oxide 230c is provided between the oxide 230b and the insulator 250. FIG.

By providing the oxide 230a under the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, by having the oxide 230c over the oxide 230b, diffusion of impurities from a structure formed above the oxide 230c to the oxide 230b can be suppressed.

A metal oxide that functions as an oxide semiconductor is preferably used for the oxide 230 . For example, it is preferable to use a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, as the metal oxide in the region where the channel is formed. By using a metal oxide with a large bandgap in this manner, off-state current of a transistor can be reduced.

Note that the oxide 230a, the oxide 230b, and the oxide 230c are shown as single layers in the drawing, but the present invention is not limited to this. For example, a structure in which the oxide 230a, the oxide 230b, and the oxide 230c are provided as a stacked structure of two or more layers may be employed. In particular, oxide 230 c preferably has a first layer in contact with oxide 230 b and a second layer in contact with insulator 250 .

For example, an oxide having the same composition as the oxide 230b is used for the first layer of the oxide 230c. On the other hand, for the second layer of the oxide 230c, it is preferable to use an oxide having a composition having a higher barrier property against impurities than the first layer. By using an oxide having the same composition as the oxide 230b for the first layer of the oxide 230, defects generated on the surface of the oxide 230b due to the production process can be compensated. Further, by using a film having a barrier property against impurities for the second layer, diffusion of impurities into the oxide 230b can be suppressed.

Further, when the oxide 230c has the above-described stacked structure, oxygen in the excess oxygen region of the insulator 280 forms a channel of the oxide 230 through the first layer of the oxide 230c, although the details will be described later. Oxygen vacancies generated in the region to be treated can be reduced. On the other hand, diffusion of oxygen in the excess oxygen region of the insulator 280 to the conductor 260 can be suppressed by the second layer of the oxide 230c.

Note that in the transistor 200, the oxide 230 has a three-layer structure of the oxide 230a, the oxide 230b, and the oxide 230c in the channel formation region and its vicinity; is not limited to For example, the oxide 230 may have a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers. good.

Conductor 260 may then function as a first gate (also referred to as top gate) electrode. In some cases, the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode.

Further, the potential applied to the conductor 205 may be changed independently of the potential applied to the conductor 260 without being interlocked with the potential applied to the conductor 260 . Specifically, the threshold voltage of the transistor 200 can be controlled by the potential applied to the conductor 205 . In particular, by applying a negative potential to the conductor 205, the threshold voltage of the transistor 200 can be made higher than 0 V, and the off current can be reduced. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0 V than when no potential is applied.

Further, for example, as illustrated in FIGS. 1A and 1C, the conductor 205 and the conductor 260 are provided so as to overlap each other, so that a potential is applied to the conductor 260 and the conductor 205. In that case, the electric field generated from the conductor 260 and the electric field generated from the conductor 205 are connected to each other, so that the channel formation region formed in the oxide 230 can be covered.

That is, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region. In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

Note that FIG. 1 shows a structure in which the first conductor of the conductor 205 and the second conductor of the conductor 205 are stacked, but the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned in order of formation for distinction.

As an example, in FIG. 1, the conductor 205 functioning as the second gate has the first conductor formed in contact with the inner walls of the openings of the insulators 214 and 216, and the second conductor further inside. is formed. Here, it is preferable that the height of the top surface of the first conductor and the second conductor and the height of the top surface of the insulator 216 be approximately the same.

For the first conductor of the conductor 205, a conductive material having a function of suppressing diffusion of impurities such as water, oxygen, or metal elements is preferably used. Alternatively, it is preferable to use a conductive material having a function of suppressing at least one diffusion of oxygen.

Since the first conductor of the conductor 205 has a function of suppressing the diffusion of oxygen, the second conductor of the conductor 205 can be prevented from being oxidized to reduce its conductivity.

In the case where the conductor 205 also functions as a wiring, the second conductor of the conductor 205 is preferably a highly conductive material containing tungsten, copper, or aluminum as its main component. Note that although the second conductor of the conductor 205 is shown as a single layer, it may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and any of the above conductive materials.

In addition, the conductor 260 functioning as the first gate electrode has a conductor 260a and a conductor 260b over the conductor 260a. The conductor 260a, like the first conductor of the conductor 205, contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N ₂ O, NO, NO ₂ , etc.), copper atoms. It is preferable to use a conductive material having a function of suppressing the diffusion of impurities such as . Alternatively, it is preferable to use a conductive material that has a function of suppressing at least one diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.).

Since the conductor 260a has a function of suppressing diffusion of oxygen, diffusion of excess oxygen from the oxide 230 and the insulator 250 to the conductor 260b is suppressed. Therefore, oxidation of the conductor 260b due to excess oxygen in the insulator 250 is suppressed, and a decrease in conductivity can be prevented. Moreover, reduction in the amount of excess oxygen supplied to the oxide 230 can be suppressed.

As the conductive material having a function of suppressing diffusion of oxygen, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used, for example. Further, an oxide semiconductor that can be used as the oxide 230 can be used as the conductor 260a. In that case, by forming the conductor 260b by a sputtering method, the electric resistance value of the conductor 260a can be lowered and the conductor 260a can be a conductor. This can be called an OC (Oxide Conductor) electrode.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor 260b. Further, since the conductor 260 functions as a wiring, a conductor with high conductivity is preferably used. For example, a conductive material whose main component is tungsten, copper, or aluminum can be used. Also, the conductor 260b may have a layered structure, for example, a layered structure of titanium, titanium nitride, and any of the above conductive materials.

Insulator 250 and insulator 252 then serve as the first gate insulator. Insulators 222 and 224 function as second gate insulators. For details, reference can be made to the above description.

Next, one of the conductors 240 (the conductor 240a and the conductor 240b) functions as a source electrode and the other functions as a drain electrode in some cases.

The conductors 240a and 240b can be metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or alloys containing these as main components. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

In addition, although a single-layer structure is shown in the drawing, a laminated structure of two or more layers may be used. For example, a tantalum nitride film and a tungsten film are preferably stacked. Alternatively, a titanium film and an aluminum film may be stacked. A two-layer structure in which an aluminum film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked over a titanium film, a two-layer structure in which a copper film is stacked over a titanium film, A two-layer structure in which copper films are stacked may be used.

In addition, a three-layer structure in which a titanium film or a titanium nitride film is laminated, an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is formed thereon, a molybdenum film or a There is a three-layer structure including a molybdenum nitride film, an aluminum film or a copper film laminated on the molybdenum film or the molybdenum nitride film, and a molybdenum film or a molybdenum nitride film formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

Further, an insulator 274 having a barrier property may be provided over the conductor 240 . A substance having a barrier property against oxygen or hydrogen is preferably used for the insulator 274 . With this structure, although details will be described later, oxygen in the excess oxygen region of the insulator 280 can be prevented from reacting with the conductor 240 and being oxidized.

Silicon nitride or metal oxide can be used for the insulator 274, for example. In particular, it is preferable to use an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide, hafnium oxide, and gallium oxide. Alternatively, silicon nitride formed by a CVD method may be used.

By including the insulator 274, the selection of materials for the conductor 240 can be expanded. For example, the conductor 240 can be made of a material having low oxidation resistance but high conductivity, such as tungsten or aluminum. Alternatively, for example, a conductor that can be easily formed into a film or processed can be used.

In addition, oxidation of the conductor 240 can be suppressed, and oxygen released from the insulators 224 and 280 can be efficiently supplied to the oxide 230 . By using a conductor with high conductivity for the conductor 240, the transistor 200 with low power consumption can be provided.

Subsequently, the insulator 212, the insulator 214, the insulator 216, the insulator 280, the insulator 282, the insulator 283, and the insulator 284 function as interlayer films.

The interlayer film may be silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ) or (Ba, Sr). Insulators such as TiO ₃ (BST) can be used in single layers or stacks. Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

For example, the insulator 216 preferably uses a so-called Low-k material with a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

Further, the insulators 280 and 284 are preferably made of a so-called Low-k material with a low dielectric constant, like the insulator 216 . By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between wirings can be reduced.

In particular, for the insulator 280, an oxide containing more oxygen than the stoichiometric composition is preferably used. Since the insulator 280 is in contact with the oxide 230c of the transistor 200, oxygen vacancies generated in a region where a channel is formed in the oxide 230 can be reduced through the oxide 230c. In other words, by providing an insulator having an excess oxygen region in an interlayer film near the transistor 200, oxygen vacancies in the oxide 230 included in the transistor 200 can be reduced, whereby reliability can be improved.

The insulator 282 preferably has barrier properties against oxygen, hydrogen, and water. Since the insulator 282 has a barrier property against oxygen, oxygen in the excess oxygen region can be efficiently supplied to the oxide 230 without diffusing to the insulator 284 side.

The insulator 212, the insulator 214, the insulator 282, and the insulator 283 are formed using an insulating material which has a function of suppressing diffusion of impurities such as water or hydrogen, and oxygen. It has a structure that seals (surrounds) the insulator 280 having

For example, it is shown in FIG. 10(A) and FIG. 10(B). FIG. 10A is a top view of the transistor 200 provided over the substrate 10 and the periphery of the transistor 200 according to one embodiment of the present invention. FIG. 10B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 10A. In addition, in FIG. 10, some elements are omitted for clarity of illustration.

The semiconductor device shown in FIGS. 10A and 10B includes a transistor 200 provided over a substrate 10, an insulator 12 having a structure surrounding the transistor 200, and an insulator 14 outside the insulator 12. have

The electric characteristics of the oxide 230 included in the transistor 200 are likely to change due to impurities such as hydrogen, water, or metal oxide; therefore, it is preferable to block entry of impurities from the outside. Therefore, it is preferable to seal the transistor 200 with a stacked-layer structure represented by the insulators 12 and 14 using an insulator having a barrier property.

As the insulator 12 and the insulator 14, for example, aluminum oxide, hafnium oxide, or the like can be used. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can also be used.

Note that the insulators 12 and 14 are preferably made of different film types. By laminating different types of films, it is possible to suppress the diffusion of more types of impurities with respect to impurities that enter from the outside. Specifically, aluminum oxide is preferably used for the insulator 12 and silicon nitride is preferably used for the insulator 14 .

Further, the insulator 12 and the insulator 14 may be formed using the same film type and different film formation methods. For example, the insulator 12 may be deposited by sputtering and the insulator 14 may be deposited by ALD. With this structure, the insulator 12, which is thicker than the insulator 14, is coated with the insulator 14, which is a dense film, so that sealing can be performed with a high yield.

Alternatively, as shown in FIGS. 10C and 10D, a plurality of transistors 200 may be surrounded together. Alternatively, each region having a different density of the transistors 200 may be surrounded.

Specifically, the semiconductor device shown in FIGS. 10C and 10D has a region 20 with a high density of transistors 200 and a region 30 with a low density of transistors 200 over the substrate 10 . Insulator 22 and insulator 24 surround the plurality of transistors 200 on all sides in region 20 of high transistor density. Insulator 32 and insulator 34 surround transistor 200 on all four sides in region 30 where transistor density is low. Here, the number of transistors 200 surrounded by insulators 22 and 24 is greater than the number of transistors 200 surrounded by insulators 32 and 34 .

Therefore, by sealing regions having different transistor densities on the substrate 10 with an insulator having a barrier property, diffusion of impurities into the transistor 200 can be suppressed. In addition, variation in the amount of excess oxygen that diffuses into the transistor 200 can be reduced. Therefore, variations in electrical characteristics can be reduced among the plurality of transistors 200 .

Here, as insulators corresponding to the insulators 12, 14, 22, 24, 32, and 34 shown in FIG. and insulator 283 can be used.

For example, the insulator 212 and the insulator 283 can be arranged as the insulator 12 , the insulator 22 , and the insulator 32 . Moreover, the insulator 214 and the insulator 282 can be arranged as the insulator 14 , the insulator 24 , and the insulator 34 . In addition, the layered structure of the insulators 214 and 216 has a region in contact with the layered structure band of the insulators 282 and 283 on the substrate.

Therefore, the insulator 212, the insulator 214, the insulator 282, and the insulator 283 function as barrier films that prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Specifically, the insulator 212, the insulator 214, the insulator 282, and the insulator 283 contain hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ₂ O, NO, NO ₂ etc.), it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (the impurities are less likely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing at least one diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate). Alternatively, aluminum oxide, silicon nitride, or the like may be used for the insulators 212, 214, 282, and 283, for example. With this structure, impurities such as hydrogen and water can be prevented from diffusing from the substrate, the substrate edge, or the insulator 284 toward the transistor 200 side.

In addition, the insulator 280 covering the transistor 200 may function as a planarization film covering the uneven shape therebelow. By adopting this structure, the coating property of the film arranged above the insulator 280 is improved. Therefore, the insulator 282 can seal the transistor 200 and the insulator 280 without film breakage.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

<Transistor structure 2>
FIG. 2 illustrates an example of a semiconductor device including a transistor 200. FIG. FIG. 2A shows the top surface of the semiconductor device. Note that part of the film is omitted in FIG. 2A for clarity of illustration. 2B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 2A, and FIG. 2C is a cross-sectional view corresponding to A3-A4.

In the semiconductor device shown in FIG. 2, structures having the same functions as those constituting the semiconductor device shown in FIG. 1 are denoted by the same reference numerals.

The transistor 200 illustrated in FIG. 2 has a structure in which an insulator 254 is provided between a conductor 260 and an insulator 252 . Also, the insulator 250 does not necessarily have to be provided. Similarly, it has a structure in which an insulator 220 is provided between a conductor 205 and an insulator 224 . Moreover, the insulator 250 and the insulator 222 do not necessarily have to be provided.

The insulator 254 is preferably, for example, an insulator that has a low hydrogen concentration and is resistant to heat. As the insulator 254, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat. Specifically, an insulator having a low hydrogen concentration and an excess oxygen region or excess oxygen has a hydrogen concentration of less than 5×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ²⁰ atoms/cm ³ by SIMS. , more preferably less than 5×10 ¹⁹ atoms/cm ³ .

The gate potential during transistor operation can be reduced while maintaining the physical film thickness by making the insulator that functions as a gate insulator into a laminated structure of a high-k material and a thermally stable material. becomes. Moreover, it is possible to obtain a laminated structure that is thermally stable and has a high dielectric constant.

In the case where an In--Ga--Zn oxide is used as the oxide 230 and an insulating material containing more gallium than the oxide 230, such as gallium oxide, is used as the insulator 252, the oxide 230 and the insulator 252 are formed. , the density of defect states at the interface between the oxide 230 and the insulator 252 can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-current and high frequency characteristics.

Alternatively, an insulator 275 may be placed over the insulator 274 . The insulator 275 preferably has barrier properties. When the insulator 275 is provided, the insulator 274 is preferably formed using a different film type. By laminating different types of films, it is possible to suppress the diffusion of more types of impurities with respect to impurities that enter from the outside.

Alternatively, the insulator 275 and the insulator 274 may be formed using the same film type and a different film formation method. For example, the insulator 274 may be deposited by a sputtering method, and the insulator 275 may be deposited by an ALD method. With this structure, the insulator 274, which is thicker than the insulator 275, is coated with the insulator 275, which is a dense film, so that sealing can be performed with high yield.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

<Transistor Structure 3>
FIG. 3 illustrates an example of a semiconductor device including a transistor 200. FIG. FIG. 3A shows the top surface of the semiconductor device. Note that part of the film is omitted in FIG. 3A for clarity of illustration. 3B is a cross-sectional view corresponding to the dashed line A1-A2 shown in FIG. 3A, and FIG. 3C is a cross-sectional view corresponding to A3-A4.

In the semiconductor device shown in FIG. 3, structures having the same functions as those constituting the semiconductor device shown in FIG. 1 or 2 are denoted by the same reference numerals.

The transistor 200 shown in FIG. 3 differs in the stacked structure of the first gate insulator and the second gate insulator. In particular, when different potentials are applied to the conductor 260 functioning as the first gate electrode and the conductor 205 functioning as the second gate electrode, the structure of the first gate insulator and the second gate insulator The structure of the body may be appropriately selected for each potential.

For example, as shown in FIG. 3, the first gate insulator can use a laminate structure of insulator 250, insulator 252, and insulator 254. FIG. On the other hand, a stacked-layer structure of insulators 221, 223, and 225 can be used for the second gate insulator.

For example, the insulators 221 and 225 preferably use films having barrier properties against oxygen, hydrogen, or impurities.

In particular, when In—Ga—Zn oxide is used as the oxide 230 , it is preferable to use an insulating material containing more gallium than the oxide 230 , such as gallium oxide, as the insulators 221 and 225 . Since an element forming the insulators 221 and 225 and an element forming the oxide 230 are common, for example, the elements forming the insulators 221 and 225 are diffused into the oxide 230. Even so, it does not cause the oxide 230 to have a low resistance.

Gallium oxide is a high dielectric constant insulating material having a higher dielectric constant than silicon nitride, and is a so-called high-k material. As transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the equivalent oxide thickness (EOT) of the gate insulator while maintaining the physical thickness. Therefore, it is possible to reduce the gate potential during transistor operation.

On the other hand, so-called high-k materials such as gallium oxide tend to crystallize easily. Also, the higher the crystallinity of the gate insulator, the higher the probability of leakage current. Therefore, it is preferable to arrange an amorphous insulator 223 between the insulator 221 and the insulator 225 . By including the insulator 223, generation of leakage current can be suppressed even when the insulators 221 and 225 have high crystallinity.

With the above structure, a semiconductor device including a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, it is possible to provide a semiconductor device in which variation in electrical characteristics is suppressed, stable electrical characteristics are obtained, and reliability is improved.

<Semiconductor Device Constituent Materials>
Constituent materials that can be used for the semiconductor device are described below.

<<Substrate>>
As a substrate for forming the transistor 200, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of insulator substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (yttria stabilized zirconia substrates, etc.), and resin substrates. Examples of semiconductor substrates include semiconductor substrates such as silicon and germanium, and compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are a substrate having a metal nitride, a substrate having a metal oxide, and the like. Furthermore, there are substrates in which an insulator substrate is provided with a conductor or a semiconductor, a substrate in which a semiconductor substrate is provided with a conductor or an insulator, a substrate in which a conductor substrate is provided with a semiconductor or an insulator, and the like. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include a capacitor element, a resistance element, a switch element, a light emitting element, a memory element, and the like.

<<insulator>>
As insulators, there are insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like.

For example, as transistors are miniaturized and highly integrated, thinning of gate insulators may cause problems such as leakage current. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material should be selected according to the function of the insulator.

Insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. oxynitrides with silicon, or nitrides with silicon and hafnium.

Insulators with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and an empty silicon oxide. There are silicon oxide with pores, resin, and the like.

A transistor including an oxide semiconductor is surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 82, and the insulator 283) which has a function of suppressing permeation of impurities such as hydrogen and oxygen. , the electrical characteristics of the transistor can be stabilized. Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or in stacks. Specifically, as insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Metal oxides such as tantalum oxide, and metal nitrides such as aluminum nitride, titanium aluminum nitride, titanium nitride, silicon nitride oxide, and silicon nitride can be used.

An insulator that functions as a gate insulator preferably has a region containing oxygen that is released by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

<<Conductor>>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from among the above, an alloy containing the above-described metal elements as a component, or an alloy or the like in which the above-described metal elements are combined. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, and the like are used. is preferred. Also, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even after absorbing oxygen. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Alternatively, a plurality of conductive layers formed using any of the above materials may be stacked and used. For example, a laminated structure in which the material containing the metal element described above and the conductive material containing oxygen are combined may be used. Alternatively, a laminated structure may be employed in which the material containing the metal element described above and the conductive material containing nitrogen are combined. Alternatively, a laminated structure may be employed in which the material containing the metal element described above, the conductive material containing oxygen, and the conductive material containing nitrogen are combined.

Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked-layer structure in which the above-described material containing the metal element and a conductive material containing oxygen are combined is used for a conductor functioning as a gate electrode. is preferred. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the metal element and nitrogen described above may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be captured in some cases. Alternatively, it may be possible to capture hydrogen mixed from an outer insulator or the like.

<Method for manufacturing a semiconductor device>
Next, a method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention, which is illustrated in FIG. 1, will be described with reference to FIGS.

4 to 9, (A) in each figure shows a top view. (B) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 shown in (A), and is also a cross-sectional view of the transistor 200 in the channel length direction. (C) of each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. In addition, in the top view of (A) of each figure, some elements are omitted for clarity of illustration.

First, a substrate (not shown) is prepared, and insulators 212 and 214 are formed over the substrate. The insulators 212 and 214 are deposited by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method. ) method, ALD method, or the like.

The CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD (Photo CVD) method using light, and the like. . Further, the method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method depending on the raw material gas used.

The plasma CVD method can obtain high quality films at relatively low temperatures. Moreover, since the thermal CVD method does not use plasma, it is a film formation method capable of reducing plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, and the like included in the semiconductor device. On the other hand, a thermal CVD method that does not use plasma does not cause such plasma damage, so that the yield of semiconductor devices can be increased. Moreover, since the thermal CVD method does not cause plasma damage during film formation, a film with few defects can be obtained.

The CVD method is a film forming method in which a film is formed by a reaction on the surface of the object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage.

In the CVD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gases. For example, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of source gases. Further, for example, in the CVD method, by changing the flow rate ratio of the source gases while forming the film, it is possible to form a film whose composition is continuously changed. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation is reduced compared to film formation using multiple film formation chambers, as the time required for transportation and pressure adjustment is not required. can do. Therefore, productivity of semiconductor devices can be improved in some cases.

In this embodiment, the insulator 212 is formed using silicon nitride by a sputtering method or a CVD method. For the insulator 214, aluminum oxide is deposited by a sputtering method or a CVD method. Alternatively, for example, the insulator 212 may be formed of aluminum oxide by a sputtering method, and the insulator 214 may be formed of aluminum oxide by an ALD method. Alternatively, a structure in which aluminum oxide is deposited as the insulator 212 by an ALD method and aluminum oxide is deposited as the insulator 214 by a sputtering method may be employed.

Next, an insulator 216 is formed over the insulator 214 . The insulator 216 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, the insulating film to be the insulator 216 is formed using silicon oxide by a CVD method.

Next, an opening is formed in insulator 216 to reach insulator 214 . The opening includes, for example, grooves and slits. Also, an area in which an opening is formed may be referred to as an opening. Wet etching may be used to form the openings, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form a groove. For example, when a silicon oxide film is used as the insulator 216 forming the trench, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as the insulator 214 .

As a dry etching device, a capacitively coupled plasma (CCP) etching device having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency voltage to one electrode of the parallel plate electrodes. Alternatively, a plurality of different high-frequency voltages may be applied to one of the parallel plate electrodes. Alternatively, a high-frequency voltage having the same frequency may be applied to each of the parallel plate electrodes. Alternatively, high-frequency voltages having different frequencies may be applied to parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. For example, an inductively coupled plasma (ICP) etching apparatus can be used as a dry etching apparatus having a high-density plasma source.

After the opening is formed, a conductive film to be the first conductor of the conductor 205 is formed. The conductive film preferably contains a conductor having a function of suppressing permeation of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, a stacked film of a conductor having a function of suppressing permeation of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. A conductive film to be the first conductor of the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment mode, as the conductive film to be the first conductor of the conductor 205, a tantalum nitride film or a film in which titanium nitride is stacked over tantalum nitride is formed by a sputtering method. By using a metal nitride as the first conductor of the conductor 205, even if a metal such as copper which is easily diffused is used as a second conductor of the conductor 205, which will be described later, the metal can be used as the second conductor of the conductor 205. Diffusion to the outside from one conductor can be prevented.

Next, a conductive film to be the second conductor of the conductor 205 is formed over the conductive film to be the first conductor of the conductor 205 . The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, tungsten is deposited as the conductive film that serves as the second conductor of the conductor 205 .

Next, CMP (Chemical Mechanical Polishing) treatment is performed to remove part of the conductive film that serves as the first conductor of the conductor 205 and part of the conductive film that serves as the second conductor of the conductor 205. Insulator 216 is exposed. As a result, the conductive film to be the first conductor of the conductor 205 and the conductive film to be the second conductor of the conductor 205 remain only in the opening. Thus, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 having a flat top surface can be formed (see FIG. 4). Note that part of the insulator 216 is removed by the CMP treatment in some cases.

Note that after the conductor 205 is formed, part of the second conductor of the conductor 205 is removed, a conductive film is formed over the conductor 205 and the insulator 216, and CMP treatment is performed. good too. By the CMP treatment, part of the conductive film is removed and the insulator 216 is exposed. Note that part of the second conductor of the conductor 205 is preferably removed by a dry etching method or the like. Further, a material similar to that of the first conductor of the conductor 205 or the second conductor of the conductor 205 is preferably used for the conductive film.

Through the above steps, the conductor 205 having a flat top surface and including the above conductive film can be formed. By improving the planarity of the top surfaces of the insulator 216 and the conductor 205, crystallinity of the CAAC-OS forming the oxides 230b and 230c can be improved.

From here, a method of forming the conductor 205 different from the above will be described below.

A conductive film to be the conductor 205 is formed over the insulator 214 . The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Also, the conductive film can be a multilayer film. In this embodiment mode, tungsten is deposited as the conductive film.

Next, the conductive film is processed by lithography to form a conductor 205 .

In the lithography method, first, the resist is exposed through a mask. The exposed regions are then removed or left behind using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching treatment through the resist mask. For example, a resist mask may be formed by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Also, an electron beam or an ion beam may be used instead of the light described above. A mask is not necessary when using an electron beam or an ion beam. Note that the resist mask can be removed by dry etching treatment such as ashing, wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

A hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film serving as the conductor 205, a resist mask is formed thereover, and the hard mask material is etched to obtain a desired shape. A hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after removing the resist mask or may be performed with the resist mask left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after the conductive film to be the conductor 205 is etched. On the other hand, if the hard mask material does not affect the post-process, or if it can be used in the post-process, it is not always necessary to remove the hard mask.

Next, an insulating film to be the insulator 216 is formed over the insulator 214 and the conductor 205 . The insulating film is formed so as to be in contact with the top surface and side surfaces of the conductor 205 . The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Here, the thickness of the insulating film to be the insulator 216 is preferably greater than or equal to the thickness of the conductor 205 . For example, if the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less.

Next, the insulating film to be the insulator 216 is subjected to CMP treatment to remove part of the insulating film to be the insulator 216 and expose the surface of the conductor 205 . Accordingly, the conductor 205 with a flat top surface and the insulator 216 in contact with the side surface of the conductor 205 can be formed. The above is a different formation method of the conductor 205 .

Next, an insulator 222 is formed over the insulator 216 and the conductor 205 . The insulator 222 has barrier properties against hydrogen and water. Since the insulator 222 has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in structures provided around the transistor 200 into the transistor 200 through the insulator 222 is suppressed. Thus, generation of oxygen vacancies in the oxide 230 can be suppressed.

Further, as the insulator 222, an insulator containing an oxide having a common metal element with the element contained in the oxide 230 is preferably deposited.

In particular, when an In—Ga—Zn oxide is used as the oxide 230 , an insulating material containing more gallium than the oxide 230 , such as gallium oxide, is preferably used as the insulator 222 . Since the element forming the insulator 222 and the element forming the oxide 230 are common, for example, even if the element forming the insulator 222 diffuses into the oxide 230, the resistance of the oxide 230 is lowered. does not cause

The insulator 222 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Note that the insulator 222 is preferably formed by an ALD method, which will be described later.

For example, when a gallium oxide film is formed as the insulator 222 by the ALD method, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium, gallium (III) acetylacetonate, Gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and the like can be used.

In addition to the metal element, some precursors contain one or both of carbon and chlorine. An oxide film formed using a carbon-containing precursor may contain carbon. Also, an oxide film formed using a chlorine-containing precursor may contain chlorine.

Subsequently, heat treatment may be performed. The heat treatment may be performed at 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Moreover, you may perform heat processing in a pressure-reduced state. Alternatively, heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, and then heat treatment is performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for desorbed oxygen. may

In this embodiment, heat treatment is performed in a nitrogen atmosphere at 400° C. for 1 hour after the insulator 222 is formed, and then in an oxygen atmosphere at 400° C. for 1 hour. process. Impurities such as water and hydrogen contained in the insulator 222 can be removed by the heat treatment. Further, the heat treatment can be performed at a timing such as after the insulator 224 is formed.

Next, an insulator 224 is formed over the insulator 222 . The insulator 224 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment mode, silicon oxide is deposited as the insulator 224 by a CVD method.

Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For plasma treatment containing oxygen, it is preferable to use an apparatus having a power supply that generates high-density plasma using microwaves, for example. Alternatively, the board may have a power supply for applying RF (Radio Frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by the high-density plasma can be efficiently guided into the insulator 224. can. Alternatively, plasma treatment containing an inert gas may be performed using this apparatus, and then plasma treatment containing oxygen may be performed to compensate for desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting conditions for the plasma treatment. In that case, heat treatment may not be performed.

Here, an aluminum oxide film may be formed over the insulator 224 by a sputtering method, for example, and CMP treatment may be performed until the aluminum oxide reaches the insulator 224 . By performing the CMP treatment, the surface of the insulator 224 can be planarized and smoothed. By performing the CMP treatment with the aluminum oxide over the insulator 224, the end point of the CMP treatment can be easily detected. Further, part of the insulator 224 is polished by the CMP treatment and the thickness of the insulator 224 is reduced in some cases. By planarizing and smoothing the surface of the insulator 224, it is possible to prevent the deterioration of the coverage of an oxide to be formed later and the decrease in the yield of the semiconductor device in some cases. Further, by forming an aluminum oxide film over the insulator 224 by a sputtering method, oxygen can be added to the insulator 224, which is preferable.

Next, an oxide film 230A and an oxide film 230B are formed in order on the insulator 224 (see FIG. 4). The oxide films 230A and 230B are preferably formed continuously without being exposed to the atmospheric environment. By forming the films without exposure to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide films 230A and 230B. can be kept clean.

The oxide film 230A and the oxide film 230B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that when the oxide film 230A and the oxide film 230B are formed by the ALD method, the contents described in the previous embodiments can be taken into consideration.

For example, when In—Ga—Zn oxide films are formed by ALD as the oxide films 230A and 230B, trimethylindium, tris(2,2,6,6-tetramethyl- 3,5-heptanedioic acid) indium, cyclopentadienyl indium, and the like are used. Further, gallium precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptane dioic acid) Gallium, dimethylchlorogallium, diethylchlorogallium, etc. are used. Dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionate)zinc and the like are used as zinc precursors. Depending on the properties required for the oxides 230a and 230b, the types and amounts of precursors used for forming the In--Ga--Zn oxide film may be appropriately combined.

In addition to the metal element, some precursors contain one or both of carbon and chlorine. An oxide film formed using a carbon-containing precursor may contain carbon. Also, an oxide film formed using a chlorine-containing precursor may contain chlorine.

Further, for example, when the oxide film 230A and the oxide film 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the formed oxide film can be increased. Further, when the above oxide film is formed by a sputtering method, the above In--M--Zn oxide target or the like can be used. An alternating current (AC) power supply such as a direct current (DC) power supply or a radio frequency (RF) power supply is connected to the target, and required power can be applied according to the electrical conductivity of the target.

In particular, part of oxygen contained in the sputtering gas may be supplied to the insulator 224 when forming the oxide film 230A. Therefore, the percentage of oxygen contained in the sputtering gas should be 70% or more, preferably 80% or more, and more preferably 100%.

Further, when the oxide film 230B is formed by a sputtering method, if the percentage of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, oxygen-excess oxidation occurs. A material semiconductor is formed. A transistor in which an oxygen-excess oxide semiconductor is used for a channel formation region has relatively high reliability. However, one embodiment of the present invention is not limited to this. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed by setting the oxygen content in the sputtering gas to 1% to 30%, preferably 5% to 20%. be. A transistor in which an oxygen-deficient oxide semiconductor is used for a channel formation region has relatively high field-effect mobility. In addition, the crystallinity of the oxide film can be improved by forming the film while heating the substrate.

In this embodiment, the oxide film 230A is formed by a sputtering method using an In--Ga--Zn oxide target of In:Ga:Zn=1:3:4 [atomic ratio]. Further, the oxide film 230B is formed by a sputtering method using an In--Ga--Zn oxide target of In:Ga:Zn=4:2:4.1 [atomic ratio]. It should be noted that each oxide film may be formed in accordance with the characteristics required for the oxide 230 by appropriately selecting the film formation conditions and the atomic ratio.

Here, the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are preferably formed without exposure to the air. For example, a multi-chamber film deposition apparatus may be used.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Impurities such as water and hydrogen in the oxide films 230A and 230B can be removed by the heat treatment. In this embodiment mode, treatment is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and then treatment is continuously performed at a temperature of 400° C. in an oxygen atmosphere for 1 hour.

Next, a conductive film 240A is formed on the oxide film 230B. The conductive film 240A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 4). Note that heat treatment may be performed before the conductive film 240A is formed. The heat treatment may be performed under reduced pressure to continuously form the conductive film 240A without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed to the surface of oxide film 230B can be removed, and the moisture concentration and hydrogen concentration in oxide film 230A and oxide film 230B can be reduced. . The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.

Next, the oxide film 230A, the oxide film 230B, and the conductive film 240A are processed into an island shape to form the oxide 230a, the oxide 230b, and the conductive layer 240B (see FIG. 5). Note that in this step, the thickness of a region of the insulator 224 which does not overlap with the oxide 230a may be thin.

Here, the oxides 230 a , 230 b , and the conductive layer 240 B are formed so that at least part of them overlaps with the conductor 205 . Also, the side surfaces of the oxide 230a, the oxide 230b, and the conductive layer 240B are preferably substantially perpendicular to the top surface of the insulator 224. FIG. The side surfaces of the oxides 230a, 230b, and the conductive layer 240B are substantially perpendicular to the top surface of the insulator 224; Become. Alternatively, the angle between the side surfaces of the oxides 230a, 230b, and the conductive layer 240B and the top surface of the insulator 224 may be small. In that case, the angle between the side surfaces of the oxides 230a, 230b, and the conductive layer 240B and the top surface of the insulator 224 is preferably 60° or more and less than 70°. With such a shape, the coverage with the insulator 274 or the like is improved in subsequent steps, and defects such as voids can be reduced.

A curved surface is preferably provided between the side surface of the conductive layer 240B and the upper surface of the conductive layer 240B. That is, it is preferable that the end of the side surface and the end of the upper surface are curved. For example, the curved surface has a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less, at the end of the conductive layer 240B. Since the edges do not have corners, the coverage of the film in the subsequent film forming process is improved.

Note that the oxide film 230A, the oxide film 230B, and the conductive film 240A may be processed using a lithography method. A dry etching method or a wet etching method can be used for the processing. Processing by the dry etching method is suitable for fine processing. Also, the oxide film 230A, the oxide film 230B, and the conductive film 240A may be processed under different conditions.

Next, an insulating film 274A to be the insulator 274 is formed over the insulator 224, the oxides 230a and 230b, and the conductive layer 240B (see FIG. 6).

The insulating film 274A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 274A is preferably an insulating film having a function of suppressing permeation of oxygen. For example, a film of silicon nitride, silicon oxide, or aluminum oxide is formed by a sputtering method. As the insulator 274, a material that can be used for the oxides 230a and 230c can be used. For example, the insulator 274 may be a metal oxide of In:Ga:Zn=1:3:4 [atomic ratio].

Also, the insulating film 274A may have a two-layer laminated structure. The lower layer of the insulating film 274A and the upper layer of the insulating film 274A can be formed using the above method, and the lower layer of the insulating film 274A and the upper layer of the insulating film 274A can be formed using the same method. Alternatively, different methods may be used. In addition, the above materials can be used for the lower layer of the insulating film 274A and the upper layer of the insulating film 274A. The lower layer of the insulating film 274A and the upper layer of the insulating film 274A may be made of the same material, or may be made of different materials. . For example, an aluminum oxide film may be formed by sputtering as a lower layer of the insulating film 274A, and an aluminum oxide film may be formed by an ALD method as an upper layer of the insulating film 274A. Alternatively, an aluminum oxide film may be formed by a sputtering method as a lower layer of the insulating film 274A, and a silicon nitride film may be formed by an ALD method as an upper layer of the insulating film 274A.

Next, an insulating film 280A is formed on the insulating film 274A. The insulating film 280A may be provided with the same type of layer by a different film formation method. Specifically, the first film of the insulating film 280A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment mode, a silicon oxide film is formed by a sputtering method as the first film of the insulating film 280A, and a silicon oxide film is formed by a CVD method as the second film of the insulating film 280A. Note that heat treatment may be performed before the insulating film 280A is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed to the surface of the insulating film 274A and the like are removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b and the insulating film 274A are reduced. be able to. The heat treatment conditions described above can be used.

Next, the insulating film 280A is subjected to CMP processing to planarize the upper surface of the insulating film 280A (see FIG. 6).

A portion of the insulating film 280A, a portion of the insulating film 274A, and a portion of the conductive layer 240B are then processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap with the conductor 205 . A conductor 240a, a conductor 240b, an insulator 274, and an insulator 280 are formed through the opening (see FIG. 7).

In addition, processing of a portion of the insulating film 280A, a portion of the insulating film 274A, and a portion of the conductive layer 240B may be performed under different conditions. For example, part of the insulator 280 may be processed by a dry etching method, part of the insulating film 274A may be processed by a wet etching method, and part of the conductive layer 240B may be processed by a dry etching method.

Here, it is preferable to remove impurities adhering to the surfaces of the oxides 230a, 230b, and the like or diffused inside. The impurities include components contained in the insulator 280, the insulating film 274A, and the conductive layer 240B, components contained in members used in an apparatus used for forming the opening, and gas or liquid used for etching. caused by the ingredients contained in Such impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

A cleaning process is performed to remove the above impurities. As a cleaning method, there are wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be performed in combination as appropriate.

As wet cleaning, cleaning treatment may be performed using an aqueous solution obtained by diluting ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these washings may be appropriately combined. For ultrasonic cleaning, it is preferable to use a frequency of 200 kHz or higher, preferably 900 kHz or higher. By using the frequency, damage to the oxide 230b and the like can be reduced.

As the cleaning treatment, in the present embodiment, wet cleaning is performed using diluted hydrofluoric acid or diluted ammonia water, followed by wet cleaning using pure water or carbonated water. By performing the cleaning treatment, impurities attached to the surfaces of the oxides 230a and 230b or diffused inside can be removed. Alternatively, the crystallinity of the oxide 230c over the oxide 230b can be improved.

Heat treatment may then be performed. The heat treatment may be performed under reduced pressure, and the first oxide film 230C and the second oxide film 230C may be successively formed without exposure to the atmosphere. By this step, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment mode, the temperature of the heat treatment is set to 200.degree.

The first film of the oxide film 230C and the second film of the oxide film 230C can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The first film of the oxide film 230C and the second film of the oxide film 230C may be formed by using the same film forming method as that for the oxide film 230A or the oxide film 230B, or by using a different film forming method. may be used. Note that when the first film of the oxide film 230C and the first film of the oxide film 230C are formed by the ALD method, the contents described in the previous embodiment can be taken into consideration. In this embodiment, as the first film of the oxide film 230C, an In—Ga—Zn oxide film having an atomic ratio of In:Ga:Zn=4:2:3 is formed by the ALD method, and then oxidized. As a second film of the film 230C, an In--Ga--Zn oxide film of In:Ga:Zn=1:3:4 [atomic ratio] is formed by ALD.

By forming the first film of the oxide film 230C and the second film of the oxide film 230C using the ALD method, it is possible to form oxide films having substantially the same film thickness on the bottom and side surfaces of the opening. For example, the ratio of the thickness of the oxide film 230C on the side surface of the opening to the thickness of the oxide film 230C on the bottom of the opening is 0.5 or more and 1 or less, preferably 0.5. It can be 7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, the ratio of the second film thickness of the oxide film 230C on the side surface of the opening to the second film thickness of the oxide film 230C on the bottom of the opening is 0.5 or more and 1 or less, preferably 0.5. It can be 7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, the ratio of the first film thickness of the oxide film 230C on the side surface of the oxide 230b to the first film thickness of the oxide film 230C on the upper surface of the oxide 230b is 0.5 or more and 1 or less, preferably It can be 0.7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, the ratio of the thickness of the second film of the oxide film 230C on the side surface of the oxide 230b to the thickness of the second film of the oxide film 230C on the top surface of the oxide 230b is 0.5 or more and 1 or less, preferably It can be 0.7 or more and 1 or less, more preferably 0.9 or more and 1 or less. Further, when the oxide film formed by the ALD method has a crystal structure, its c-axis can be substantially parallel to the normal direction of the film formation surface.

When the first film of the oxide film 230C and the second film of the oxide film 230C are formed by a sputtering method, the sputtering gas is In some cases, part of the oxygen contained in is supplied to the oxides 230a and 230b. Therefore, the ratio of oxygen contained in the sputtering gas for the first oxide film 230C and the second oxide film 230C should be 70% or more, preferably 80% or more, and more preferably 100%.

Heat treatment may then be performed. The heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. By performing such treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C are removed, and the moisture concentration and hydrogen concentration in the oxide film 230a, the oxide 230b, and the oxide film 230C are reduced. can be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxynitride is deposited by a CVD method as the insulating film 250A. The film formation temperature for forming the insulating film 250A is preferably 350.degree. C. or more and less than 450.degree. By forming the insulating film 250A at 400° C., an insulating film containing few impurities can be formed.

Next, an insulating film 252A is formed over the insulating film 250A. The insulating film 252A has barrier properties against hydrogen and water. Since the insulating film 252A has barrier properties against hydrogen and water, diffusion of hydrogen and water contained in structures provided around the transistor 200 into the transistor 200 through the insulating film 252A is suppressed. Thus, generation of oxygen vacancies in the oxide 230 can be suppressed.

As the insulating film 252A, an insulator containing an oxide having a common metal element with the element contained in the oxide 230 is preferably formed. In particular, when an In--Ga--Zn oxide is used as the oxide 230, an insulating material containing more gallium than the oxide 230, such as gallium oxide, is preferably used as the insulating film 252A. Since the element forming the insulating film 252A and the element forming the oxide 230 are common, for example, even if the element forming the insulating film 252A diffuses into the oxide 230, the resistance of the oxide 230 is reduced. does not cause

The insulating film 252A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that the insulating film 252A is preferably formed by the ALD method similarly to the insulator 222 .

For example, when a gallium oxide film is formed as the insulating film 252A by the ALD method, trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium, gallium(III) acetylacetonate, Gallium tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and the like can be used.

In addition to the metal element, some precursors contain one or both of carbon and chlorine. An oxide film formed using a carbon-containing precursor may contain carbon. Also, an oxide film formed using a chlorine-containing precursor may contain chlorine.

Next, a conductive film 260A and a conductive film 260B are formed in order. The conductive films 260A and 260B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use the CVD method. In this embodiment mode, the conductive film 260A is formed using an ALD method, and the conductive film 260B is formed using a CVD method (see FIG. 8).

Next, by CMP processing, the first film of the oxide film 230C, the second film of the oxide film 230C, the insulating film 250A, the insulating film 252A, the conductive film 260A, and the conductive film 260B are polished until the insulator 280 is exposed. By doing so, an oxide 230c, an insulator 250, an insulator 252, and conductors 260 (conductors 260a and 260b) are formed (see FIG. 9). Thereby, the oxide 230c is arranged to cover the inner walls (side walls and bottom) of the opening reaching the oxide 230b. Insulators 250 and 252 are arranged to cover the inner wall of the opening with oxide 230c interposed therebetween. In addition, the conductor 260 is arranged to fill the opening with the oxide 230c, the insulator 250, and the insulator 252 interposed therebetween.

Next, heat treatment may be performed. In this embodiment mode, the treatment is performed at a temperature of 400° C. for one hour in a nitrogen atmosphere. By the heat treatment, the concentrations of moisture and hydrogen in the insulators 250, 252, and 280 can be reduced.

Next, insulators 282 and 283 are formed over the oxide 230 c , the insulator 250 , the insulator 252 , the conductor 260 , and the insulator 280 . The insulators 282 and 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, similarly to the insulators 212 and 214 . As the insulators 282 and 283, for example, an aluminum oxide film or a silicon nitride film is preferably formed by a sputtering method. By forming an aluminum oxide film or a silicon nitride film by a sputtering method, hydrogen contained in the insulators 282 and 283 can be suppressed from diffusing into the oxide 230 . Forming the insulator 282 so as to be in contact with the conductor 260 is preferable because oxidation of the conductor 260 can be suppressed.

In addition, oxygen can be supplied to the insulator 280 by forming an aluminum oxide film as the insulator 282 by a sputtering method. Oxygen supplied to the insulator 280 may be supplied to a channel formation region of the oxide 230b through the oxide 230c. Further, by supplying oxygen to the insulator 280, oxygen contained in the insulator 280 before the insulator 282 is formed is supplied to the channel formation region of the oxide 230b through the oxide 230c. may occur.

Alternatively, as the insulator 282, an aluminum oxide film may be formed by a sputtering method, and as the insulator 283, a silicon nitride film may be formed over the aluminum oxide film by a sputtering method.

Next, heat treatment may be performed. For the heat treatment, the heat treatment conditions described above can be used. By the heat treatment, the moisture concentration and the hydrogen concentration of the insulator 280 can be reduced. Further, oxygen contained in the insulator 282 can be injected into the insulator 280 .

Note that as a method for forming the insulator 282 and the insulator 283, first, an aluminum oxide film is formed over the oxide 230c, the insulator 250, the insulator 252, the conductor 260, and the insulator 280 by a sputtering method. Next, heat treatment is performed using the above heat treatment conditions, the aluminum oxide film is removed by CMP treatment, and then an insulator 282 and an insulator 283 are formed. good too. By this method, more excess oxygen regions can be formed in the insulator 280 . Note that part of the insulator 280, part of the conductor 260, part of the insulator 250, part of the insulator 252, and part of the oxide 230c are removed in the step of removing the aluminum oxide film. may occur.

Further, an insulator may be provided between the insulator 280 and the insulator 282 . As the insulator, silicon oxide deposited by a sputtering method may be used, for example. By providing the insulator, an excess oxygen region can be formed in the insulator 280 .

Next, an insulator 284 may be formed over the insulator 282 . The insulator 284 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 1).

According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

The structures, methods, and the like described in this embodiment can be combined as appropriate with the structures, methods, and the like described in other embodiments.

(Embodiment 2)
One embodiment of the present invention relates to a manufacturing method and a manufacturing apparatus that can be used for the manufacturing method of the semiconductor device described in the above embodiment.

<Metal Oxide Applicable to Oxide Semiconductors and Gate Insulators>
The metal oxide according to the present invention will be described below.

The oxide semiconductor preferably contains at least indium or zinc. Indium and zinc are particularly preferred. In addition to these, aluminum, gallium, yttrium, tin, or the like is preferably contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained.

Here, consider the case where the oxide semiconductor is InMZnO having indium, the element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above elements may be combined.

On the other hand, the gate insulator is preferably an oxide containing at least the element I. Element I may include one or more selected from gallium, aluminum, hafnium, boron, titanium, silicon, germanium, zirconium, yttrium, cerium, magnesium, and the like. Note that when the oxide semiconductor is InMZnO, the element I is preferably of the same kind as the element M.

In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Metal oxides containing nitrogen may also be referred to as metal oxynitrides.

Now consider the case where the metal oxide comprises indium, the element M and zinc. The terms of the atomic ratios of indium, the element M, and zinc contained in the metal oxide are represented by [In], [M], and [Zn], respectively.

17A, 17B, and 17C, indium, element M, and zinc included in metal oxides that can be used for the oxides of one embodiment of the present invention are described below. A preferable range of the atomic number ratio of is explained. Note that the atomic number ratio of oxygen is not shown in FIGS. 17A, 17B, and 17C. Further, the terms of the atomic ratios of indium, the element M, and zinc contained in the metal oxide are represented by [In], [M], and [Zn], respectively.

In FIGS. 17(A), 17(B), and 17(C), the dashed lines indicate the atomic ratio of [In]:[M]:[Zn]=(1+α):(1−α):1. (-1 ≤ α ≤ 1), a line [In]: [M]: [Zn] = (1 + α): (1-α): a line with an atomic ratio of 2, [In]: [M] : [Zn] = (1 + α): (1-α): A line with an atomic number ratio of 3, [In]: [M]: [Zn] = (1 + α): (1-α): 4 atomic number A line that gives a ratio and a line that gives an atomic number ratio of [In]:[M]:[Zn]=(1+α):(1−α):5.

In addition, the dashed-dotted line is a line with an atomic ratio of [In]:[M]:[Zn]=5:1:β (β≧0), [In]:[M]:[Zn]=2: A line with an atomic ratio of 1:β, [In]:[M]:[Zn]=1:1: A line with an atomic ratio of β, [In]:[M]:[Zn]=1: A line with an atomic ratio of 2:β, a line with an atomic ratio of [In]:[M]:[Zn]=1:3:β, and [In]:[M]:[Zn]=1 : represents a line with an atomic number ratio of 4:β.

17(A), 17(B), and 17(C), the atomic number ratio of [In]:[M]:[Zn]=0:2:1 and its neighboring values Metal oxides tend to have a spinel crystal structure.

In addition, multiple phases may coexist in the metal oxide (two-phase coexistence, three-phase coexistence, etc.). For example, when the atomic number ratio is close to [In]:[M]:[Zn]=0:2:1, two phases, a spinel crystal structure and a layered crystal structure, tend to coexist. Moreover, when the atomic number ratio is close to [In]:[M]:[Zn]=1:0:0, two phases of a bixbyite crystal structure and a layered crystal structure tend to coexist. When multiple phases coexist in a metal oxide, grain boundaries may be formed between different crystal structures.

A region A shown in FIG. 17A shows an example of a preferred range of the atomic ratio of indium, element M, and zinc in the metal oxide.

By increasing the indium content of the metal oxide, the carrier mobility (electron mobility) of the metal oxide can be increased. Therefore, a metal oxide with a high indium content has higher carrier mobility than a metal oxide with a low indium content.

On the other hand, lower contents of indium and zinc in the metal oxide result in lower carrier mobility. Therefore, when the atomic number ratio is [In]:[M]:[Zn]=0:1:0 and its neighboring values (for example, region C shown in FIG. 17C), the insulating property is high. .

For example, the metal oxide used for the channel formation region and the low-resistance region preferably has an atomic ratio shown in region A in FIG. 17A, which has high carrier mobility. The metal oxide used for the channel forming region and the low-resistance region may have a ratio of, for example, In:Ga:Zn=4:2:3 to 4.1 or a value in the vicinity thereof. On the other hand, when a metal oxide is provided so as to surround the channel formation region and the low-resistance region, it preferably has an atomic ratio shown in region C in FIG. 17C, which has relatively high insulating properties. The metal oxide surrounding the channel forming region and the low resistance region is, for example, about In:Ga:Zn=1:3:4 or about In:Ga:Zn=1:3:2. do it. Alternatively, the metal oxide provided to surround the channel formation region and the low-resistance region may be a metal oxide that is equivalent to the metal oxide used for the channel formation region and the low-resistance region.

In particular, in the region B shown in FIG. 17B, even in the region A, an excellent metal oxide with high carrier mobility and high reliability can be obtained.

Note that region B includes [In]:[M]:[Zn]=4:2:3 to 4.1 and their neighboring values. Neighborhood values include, for example, [In]:[M]:[Zn]=5:3:4. Also, region B has [In]:[M]:[Zn]=5:1:6 and its neighboring values, and [In]:[M]:[Zn]=5:1:7 and its Contains neighborhood values.

In addition, the atomic ratio of the metal oxide also affects the easiness of diffusion or permeation of oxygen in the metal oxide.

In the region A with a high indium content, particularly in the metal oxide of the region B (referred to as the first metal oxide), oxygen easily diffuses, and the oxygen contained in the material adjacent to the first metal oxide is absorbed and , the release of oxygen to the material adjacent to the first metal oxide is facilitated. That is, when a first metal oxide is provided between a first material containing oxygen and a second material containing less oxygen than the first material, oxygen contained in the first material may pass through the first metal oxide and be supplied to the second material. On the other hand, in the metal oxide of region C (referred to as a second metal oxide), diffusion of oxygen is difficult to occur, so the second metal oxide suppresses permeation of oxygen and functions as a blocking layer against oxygen. Sometimes. That is, by providing the second metal oxide between the third material containing oxygen and the fourth material containing less oxygen than the third material, the oxygen contained in the third material is may be suppressed in diffusion by the second metal oxide and may be suppressed in supply to the fourth material.

As described above, the atomic ratio in the metal oxide is important from the viewpoint of electrical conductivity and oxygen diffusion properties, and should be controlled according to the properties required of the metal oxide.

When the metal oxide is formed by sputtering, the atomic ratio of the sputtering target depends on the atomic ratio of the film. When In--M--Zn oxide is used as the metal oxide, it is preferable to use a target containing polycrystalline In--M--Zn oxide as the sputtering target. The atomic ratio of the metal oxide to be deposited includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target. For example, when the composition of the sputtering target used for the metal oxide is In:Ga:Zn=4:2:4.1 [atomic ratio], the composition of the metal oxide to be deposited is In:Ga:Zn= It may be close to 4:2:3 [atomic ratio]. Further, when the composition of the sputtering target used for the metal oxide is In:Ga:Zn=5:1:7 [atomic ratio], the composition of the metal oxide to be deposited is In:Ga:Zn=5: It may be close to 1:6 [atomic number ratio].

The properties of metal oxides are not uniquely determined by the atomic number ratio. Even if the atomic ratio is the same, the properties of the metal oxide may differ depending on the formation conditions. For example, when a metal oxide is deposited using a sputtering apparatus, a film having an atomic ratio deviating from the atomic ratio of the target is formed. Also, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target. Thus, the illustrated regions are regions exhibiting atomic ratios where metal oxides tend to have particular properties, and the boundaries of regions A through C are not strict.

Here, when stacking a plurality of metal oxides having different atomic ratios, a plurality of sputtering targets corresponding to the respective atomic ratios and a plurality of chambers in which these targets are installed are required.

In addition, in film formation using a sputtering method, particles during the film formation are incident on the film formation surface, so if a separate film is formed on the film formation surface, the film may be damaged. There is Here, film formation damage includes the formation of a mixed layer due to the incidence of particles into the film during film formation, and the decrease in the crystallinity of the film when the film has crystals.

In view of the above problems in film formation using the sputtering method, it is preferable that the atomic ratio of the metal oxide can be adjusted by the film formation conditions of the metal oxide. In addition, it is preferable to use a film formation method with reduced film formation damage for forming the metal oxide.

ALD can be used as a method for forming a metal oxide to solve the above problem.

The ALD method utilizes the self-regulating properties of precursor molecules or atoms contained in precursors, and can deposit atoms layer by layer, making it possible to form ultra-thin films and to form structures with high aspect ratios. film formation with few defects such as pinholes; film formation with excellent coverage; and film formation at low temperatures. The ALD method also includes a plasma enhanced ALD (PEALD) method, which is a film forming method using plasma. By using plasma, film formation can be performed at a lower temperature, which is preferable in some cases. Some precursors used in the ALD method contain elements such as carbon and chlorine. Therefore, a film formed by the ALD method may contain more elements such as carbon and chlorine than films formed by other film formation methods. Quantification of these elements can be performed using X-ray photoelectron spectroscopy (XPS).

The ALD method is a film formation method in which a film is formed by a reaction on the surface of the object to be processed, unlike a film formation method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method which is not easily affected by the shape of the object to be processed and which has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with another film formation method, such as the CVD method, which has a high film formation rate.

In the ALD method, the composition of the resulting film can be controlled by the amount of source gas introduced. For example, in the ALD method, a film having an arbitrary composition can be formed by adjusting the introduction amount and the number of introductions (also referred to as the number of pulses) of the source gas. Further, for example, in the ALD method, a film whose composition is continuously changed can be formed by changing the material gas while forming the film. When film formation is performed while changing the source gas, the time required for film formation can be shortened as much as the time required for transportation and pressure adjustment is not required compared to the case where film formation is performed using a plurality of film formation chambers. can. Therefore, productivity of semiconductor devices can be improved in some cases.

<Deposition method using ALD apparatus and ALD method>
Here, an ALD apparatus that can be used for forming the metal oxide of one embodiment of the present invention and a film formation method using the ALD method are described.

A film forming apparatus using the ALD method alternately supplies a first source gas (precursor, precursor, or metal precursor) and a second source gas (reactant, reactant, or non-metal precursor) for reaction. A film is formed by repeating the introduction of these source gases into the chamber. Note that the introduction of the source gas can be switched, for example, by switching each switching valve (also referred to as a high-speed valve). Further, when introducing the raw material gas, an inert gas such as nitrogen (N ₂ ) or argon (Ar) may be introduced into the chamber together with the raw material gas as a carrier gas. By using a carrier gas, even if the volatility of the raw material gas is low or the vapor pressure is low, the raw material gas can be introduced into the chamber by suppressing the adsorption of the raw material gas inside the pipes and valves. Become. Moreover, the uniformity of the formed film is also improved, which is preferable.

An example of a film formation method using the ALD method will be described with reference to FIG. First, a first source gas is introduced into the chamber (see FIG. 11A), and the precursor 601 is adsorbed on the substrate surface (first step). Here, when the precursor 601 is adsorbed on the substrate surface, a self-terminating mechanism of the surface chemical reaction acts, and the precursor is not further adsorbed on the precursor layer on the substrate (see FIG. 11B). . The proper range of substrate temperature in which the self-stopping mechanism of the surface chemical reaction acts is also called the ALD window. The ALD window is determined by the temperature characteristics, vapor pressure, decomposition temperature, etc. of the precursor, and should be 100° C. or higher and 500° C. or lower, preferably 200° C. or higher and 400° C. or lower. Next, the chamber is evacuated to exhaust excess precursors, reaction products, and the like (second step). Alternatively, instead of evacuating, an inert gas (argon, nitrogen, or the like) may be introduced into the chamber to discharge excess precursors, reaction products, and the like from the chamber. This step is also called a purge. Next, a reactant 602 (eg, an oxidizing agent (ozone (O ₃ ), oxygen (O ₂ ), water (H ₂ O), and plasma, radicals, ions thereof, etc.) is introduced into the chamber as a second source gas. (see FIG. 11(C)), reacting with the precursor 601 adsorbed on the substrate surface, and part of the component contained in the precursor 601 is released while the constituent molecules of the film are adsorbed on the substrate (third step) (see FIG. 11(D)). Next, excess reactant 602 and reaction products are discharged from the chamber by evacuation or introduction of inert gas (fourth step).

In the following description of this specification, unless otherwise specified, when ozone, oxygen, or water is used as a reactant or an oxidizing agent, these are not limited to gas or molecular states, but plasma states and radical states. , and ionic states. When forming a film using an oxidizing agent in a plasma state, a radical state, or an ion state, a radical ALD apparatus or a plasma ALD apparatus, which will be described later, may be used.

As the oxidizing agent, water is preferably used to remove the carbon contained in the precursor. Hydrogen contained in water can react with carbon contained in the precursor to efficiently desorb the carbon from the precursor. On the other hand, when it is desired to reduce hydrogen contained in the formed film as much as possible, it is preferable to use ozone or oxygen that does not contain hydrogen as the oxidizing agent. In addition, water is introduced into the chamber as the first oxidant to remove carbon contained in the precursor, and then the chamber is evacuated, and ozone or oxygen containing no hydrogen is introduced into the chamber as the second oxidant. may be used to remove hydrogen and evacuate. After that, the first to fourth steps are repeated until a desired film thickness is obtained.

In addition, although the above description shows an example in which the first source gas is introduced into the chamber and then the second source gas is introduced into the chamber, the present invention is not limited to this. The second source gas may be introduced into the chamber before the first source gas is introduced into the chamber. That is, first, after the third step and the fourth step, the first step, the second step, the third step, and the fourth step are performed, and thereafter the first step to the fourth step are repeatedly performed to form a film. may be performed. Further, after repeating the third step and the fourth step a plurality of times, the film formation may be performed by repeating the first step to the fourth step.

Performing the third step and the fourth step once or a plurality of times before the first step in this way is preferable because the film formation atmosphere in the chamber can be controlled. For example, as a third step, an oxygen atmosphere can be created in the chamber by introducing an oxidizing agent. Starting the film formation in an oxygen atmosphere is preferable because the oxygen concentration in the formed film can be increased. Furthermore, oxygen can be supplied to an insulator or an oxide that serves as a base of the film. A semiconductor device formed using such a method has good characteristics and can obtain high reliability.

Further, after the first step and the second step, the introduction of the second raw material gas in the third step and the evacuation or the introduction of the inert gas in the fourth step may be repeated multiple times. That is, after repeating the first step, the second step, the third step, the fourth step, the third step, the fourth step, and the third step and the fourth step, the first step and the second step are performed. may

For example, O ₃ and O ₂ may be introduced as oxidizing agents in the third step, evacuation may be performed in the fourth step, and this process may be repeated multiple times.

Further, when repeating the third step and the fourth step, it is not always necessary to repeat introduction of the same kind of raw material gas. For example, H ₂ O may be used as the oxidizing agent in the first third step, and O ₃ may be used as the oxidizing agent in the second and subsequent third steps.

In this way, the introduction of the oxidizing agent and the evacuation (or the introduction of the inert gas) are repeated several times in a short period of time, so that excess hydrogen atoms, carbon atoms, and chlorine atoms are removed from the precursors adsorbed on the substrate surface. Atoms and the like can be more reliably removed and eliminated from the chamber. Moreover, by increasing the number of types of oxidizing agents to two, it is possible to remove more excess hydrogen atoms and the like from the precursor adsorbed on the substrate surface. Thus, by preventing hydrogen atoms from being taken into the film during film formation, water, hydrogen, and the like contained in the formed film can be reduced.

By using such a method, the amount of desorption of water molecules is 1.0×10 ¹³ molecules/cm ² in the surface temperature range of 100° C. to 700° C. or 100° C. to 500° C. in TDS analysis. A film having a concentration of 1.0×10 ¹⁶ molecule/cm ² or more, more preferably 1.0×10 ¹³ molecule/cm ² or more and 3.0×10 ¹⁵ molecule/cm ² or less can be formed.

In this manner, a first monolayer can be deposited on the substrate surface, and steps 1 to 4 are repeated to deposit a second monolayer on top of the first monolayer. be able to. By repeating the first to fourth steps a plurality of times while controlling gas introduction until the film reaches a desired thickness, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of repetitions, the film thickness can be precisely adjusted, which is suitable for manufacturing fine transistors.

Also, the film formed by the above method may have a layered structure. Furthermore, when the film formed by the above method has a crystalline structure, the c-axis of the film is oriented in a direction substantially parallel to the normal direction of the film formation surface. That is, the c-axis of the film is oriented perpendicularly to the film formation surface. Although the details will be described later, in this specification, such a crystal structure is sometimes referred to as a CAAC structure, and an oxide semiconductor (metal oxide) having the CAAC structure is sometimes referred to as a CAAC-OS. By using the ALD method, it is possible to form a metal oxide having a CAAC structure.

The ALD method is a film forming method in which thermal energy is used to react a precursor and a reactant. The temperature required for the reaction of the precursor and reactant is determined by their temperature characteristics, vapor pressure, decomposition temperature, etc., and is 100° C. or higher and 500° C. or lower, preferably 200° C. or higher and 400° C. or lower. Furthermore, an ALD method in which processing is performed by introducing a plasma-excited reactant as a third source gas into the chamber in addition to the reaction of the precursor and the reactant is sometimes called a plasma ALD method. In this case, a plasma generator is provided at the inlet for the third source gas. Inductively Coupled Plasma (ICP) can be used to generate plasma. On the other hand, the ALD method in which the precursor and the reactant react with thermal energy is sometimes called the thermal ALD method.

In the plasma ALD method, a film is formed by introducing a plasma-excited reactant in the third step. Alternatively, film formation is performed by introducing a plasma-excited reactant (second reactant) while repeating the first to fourth steps. In this case, the reactant introduced in the third step is called the first reactant. In the plasma ALD method, the same material as the oxidizing agent can be used for the second reactant used for the third source gas. That is, plasma-excited ozone, oxygen, and water can be used as the second reactant. Also, as the second reactant, a nitriding agent may be used in addition to the oxidizing agent. Nitrogen (N ₂ ) or ammonia (NH ₃ ) can be used as the nitriding agent. Also, a mixed gas of nitrogen (N ₂ ) and hydrogen (H ₂ ) can be used as a nitriding agent. For example, a mixed gas of 5% nitrogen (N ₂ ) and 95% hydrogen (H ₂ ) can be used as the nitriding agent. A nitride film such as a metal nitride film can be formed by performing film formation while introducing plasma-excited nitrogen or ammonia.

Also, argon (Ar) or nitrogen (N ₂ ) may be used as the carrier gas for the second reactant. The use of a carrier gas such as argon or nitrogen facilitates plasma discharge and facilitates generation of the plasma-excited second reactant, which is preferable. Note that when an oxide film such as a metal oxide film is formed by plasma ALD, if nitrogen is used as a carrier gas, nitrogen may enter the film and desired film quality may not be obtained. In this case, argon is preferably used as the carrier gas.

The ALD method can form an extremely thin film with a uniform film thickness. Moreover, the surface coverage is high even for a surface having unevenness.

In addition, film formation by the plasma ALD method enables film formation at a lower temperature than the thermal ALD method. The plasma ALD method can form a film at a temperature of, for example, 100° C. or less without lowering the film forming speed. In plasma ALD, not only oxidizing agents but also many reactants such as nitriding agents can be used. Therefore, it is possible to form not only oxides but also many kinds of films such as nitrides, fluorides and metals. can be done.

Also, when plasma ALD is performed, plasma can be generated away from the substrate, such as ICP (Inductively Coupled Plasma). Plasma damage can be suppressed by generating plasma in this manner.

By the above method, a film, an oxide film, or a nitride film containing atoms contained in the first source gas as one component can be formed.

On the other hand, when forming a film containing a plurality of metals as a metal oxide, a plurality of precursors may be prepared for each metal and sequentially introduced into the chamber.

When forming an In--M--Zn oxide as the metal oxide, a raw material gas containing a first precursor containing indium is introduced into the chamber, and excess raw material gas is exhausted (purged). Next, as a reactant, an oxidizing agent is introduced into the chamber and excess reactant is exhausted. Next, a raw material gas containing a second precursor containing the element M is introduced into the chamber, and excess raw material gas is exhausted (purged). Next, as a reactant, an oxidizing agent is introduced into the chamber and excess reactant is exhausted. Next, a raw material gas containing a third precursor containing zinc is introduced into the chamber, and excess raw material gas is exhausted (purged). Next, as a reactant, an oxidizing agent is introduced into the chamber and excess reactant is exhausted. By repeating the above steps, a metal oxide including a single layer containing indium, a single layer containing the element M, and a single layer containing zinc can be formed. Note that the order of introduction of the raw material gases is not limited to the above. After introducing the raw material gas containing the first precursor, the raw material gas containing the third precursor may be introduced, and then the raw material gas containing the second precursor may be introduced. can be determined as appropriate. Further, after each raw material gas is introduced, the excess raw material gas can be exhausted, the reactant can be introduced, and the exhaust can be appropriately performed. Note that metal oxides are not limited to In--M--Zn oxides. As mentioned above, the metal oxide preferably contains at least indium or zinc, particularly preferably indium and zinc. Also, the number of metals contained in the metal oxide may be two, or four or more.

Also, the atomic ratio of the metal contained in the metal oxide can be controlled by adjusting the number of introduction times of the raw material gas containing the precursor containing the desired metal into the chamber and the film formation temperature. For example, when it is desired to increase the atomic ratio of the element M with respect to indium or zinc, a raw material gas containing a second precursor containing the element M is introduced into the chamber, excess raw material gas is exhausted, and the reactant is After introducing an oxidizing agent into the chamber and evacuating excess reactant, a source gas containing a second precursor containing the element M is again introduced into the chamber, excess source gas is evacuated, and an oxidizing agent is introduced into the chamber as a reactant. and exhaust the excess reactant.

Also, a plurality of precursors may be introduced into the chamber, for example, a source gas containing a first precursor is introduced into the chamber, excess source gas is exhausted, a reactant is introduced into the chamber, and excess reactant is exhausted. Then, a raw material gas containing the second precursor and the third precursor is introduced into the chamber, excess raw material gas is exhausted, a reactant is introduced into the chamber, and the excess reactant is exhausted to obtain In-M- Metal oxides, including Zn oxides, may be formed. The combination of precursors introduced into the chamber is not limited to the above. A raw material gas containing the first precursor and the second precursor may be introduced into the chamber, a raw material gas containing the first precursor and the third precursor may be introduced into the chamber, and the first precursor may be introduced into the chamber. , a second precursor, and a third precursor may be introduced into the chamber. It can be appropriately determined by the practitioner according to the required properties of the film.

Also, raw material gases containing different precursors may be successively introduced into the chamber. For example, a source gas containing a first precursor is introduced into the chamber, excess source gas is evacuated, a reactant is introduced into the chamber, excess reactant is evacuated, and a source gas containing a second precursor is introduced into the chamber. Then, after the excess source gas is exhausted, the reactant is not introduced into the chamber, the source gas containing the third precursor is subsequently introduced into the chamber, the excess source gas is exhausted, and the reactant is introduced into the chamber. , the excess reactant may be evacuated to form metal oxides, including In--M--Zn oxides. The order and combination of precursors introduced into the chamber in succession are not limited to the above. After introducing the raw material gas containing the third precursor into the chamber, the raw material gas containing the second precursor may be introduced into the chamber, or after introducing the raw material gas containing the first precursor into the chamber, The source gas containing the second precursor may be introduced into the chamber without introduction. It can be appropriately determined by the practitioner according to the required properties of the film.

Alternatively, a precursor containing multiple metals may be used to form a metal oxide. For example, a precursor containing indium and element M in one molecule, a precursor containing indium and zinc in one molecule, a precursor containing element M and zinc in one molecule, or the like may be used to form a metal oxide.

<Structure of Metal Oxide>
A structure of a CAC (Cloud-Aligned Composite)-OS that can be used for the transistor disclosed in one embodiment of the present invention is described below.

In this specification and the like, it may be referred to as CAAC (c-axis aligned crystal) and CAC (cloud-aligned composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or material configuration.

CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. Note that when CAC-OS or CAC-metal oxide is used for an active layer of a transistor, the function of conductivity is to flow electrons (or holes) that serve as carriers, and the function of insulation is to flow electrons that serve as carriers. It is a function that does not flow A switching function (on/off function) can be imparted to the CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. By separating each function in CAC-OS or CAC-metal oxide, both functions can be maximized.

Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive regions have the above-described conductive function, and the insulating regions have the above-described insulating function. In some materials, the conductive region and the insulating region are separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed to be connected like a cloud with its periphery blurred.

In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are each dispersed in the material with a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less. There is

Also, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap resulting from an insulating region and a component having a narrow gap resulting from a conductive region. In the case of this configuration, when the carriers flow, the carriers mainly flow in the component having the narrow gap. In addition, the component having a narrow gap acts complementarily on the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, high current drivability, that is, high on-current and high field-effect mobility can be obtained in the on-state of the transistor.

That is, CAC-OS or CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

[Structure of Metal Oxide]
Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nc-OS, pseudo-amorphous oxide semiconductors (a-like OS: amorphous-like oxide semiconductors), and amorphous oxide semiconductors. semiconductors, etc.

CAAC-OS has a c-axis orientation and a distorted crystal structure in which a plurality of nanocrystals are connected in the ab plane direction. The strain refers to a portion where the orientation of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagons and may have non-regular hexagons. Also, the distortion may have a lattice arrangement of pentagons, heptagons, and the like. In CAAC-OS, it is difficult to confirm clear crystal grain boundaries (also called grain boundaries) even in the vicinity of strain. That is, it can be seen that the distortion of the lattice arrangement suppresses the formation of grain boundaries. This is because the CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the ab plane direction and the bond distance between atoms changes due to the substitution of metal elements. It's for.

CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be substituted with each other, and when the element M in the (M, Zn) layer is substituted with indium, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced with the element M, it can also be expressed as an (In, M) layer.

CAAC-OS is a highly crystalline metal oxide. On the other hand, in CAAC-OS, since it is difficult to confirm a clear crystal grain boundary, it can be said that the decrease in electron mobility due to the crystal grain boundary is unlikely to occur. In addition, since the crystallinity of metal oxides may be degraded by the contamination of impurities and the generation of defects, CAAC-OS is made of a metal with few impurities and defects (such as oxygen vacancy (V _O )). It can also be called an oxide. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, a metal oxide containing CAAC-OS is heat resistant and highly reliable.

The nc-OS has periodic atomic arrangement in a minute region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). Also, nc-OS shows no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, an nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor depending on the analysis method.

Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a type of metal oxide containing indium, gallium, and zinc, may have a stable structure when formed into the above-described nanocrystals. be. In particular, since IGZO tends to be difficult to crystallize in the atmosphere, it is better to use smaller crystals (for example, the above-mentioned nanocrystals) than large crystals (here, crystals of several mm or crystals of several cm). can be structurally stable.

An a-like OS is a metal oxide having a structure between an nc-OS and an amorphous oxide semiconductor. An a-like OS has void or low density regions. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

Oxide semiconductors (metal oxides) have various structures, each of which has different characteristics. An oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

Note that although there is no particular limitation on the structure of the oxide semiconductor (metal oxide) in the semiconductor device of one embodiment of the present invention, it preferably has crystallinity. For example, oxide 230 can have a CAAC-OS structure and oxide 243 can have a hexagonal crystal structure. When the oxides 230 and 243 have the above crystal structures, the semiconductor device can have high reliability.

[impurities]
Here, the effect of each impurity in the metal oxide will be described.

Further, if the metal oxide contains an alkali metal or an alkaline earth metal, it may form a defect level and generate carriers. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region tends to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by SIMS (concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry)) is 1×10 ¹⁸ atoms. /cm ³ or less, preferably 2×10 ¹⁶ atoms/cm ³ or less.

In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to the metal atom to become water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, electrons, which are carriers, are generated in some cases. In addition, part of hydrogen may bond with oxygen that bonds with a metal atom to generate an electron, which is a carrier. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1×10 ²⁰ atoms/cm ³ , preferably less than 1×10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm Less than ³ , more preferably less than 1×10 ¹⁸ atoms/cm ³ . By using a metal oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted.

A highly crystalline thin film is preferably used as a metal oxide used for a semiconductor of a transistor. By using the thin film, the stability or reliability of the transistor can be improved. The thin film includes, for example, a single-crystal metal oxide thin film or a polycrystalline metal oxide thin film. However, forming a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate requires a high temperature or laser heating process. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

Non-Patent Document 1 and Non-Patent Document 2 report that an In--Ga--Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, does not clearly identify grain boundaries, and can be formed on a substrate at low temperatures. Furthermore, it has been reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

In 2013, an In--Ga--Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity in crystal orientation is observed between different regions. there is

Non-Patent Document 4 and Non-Patent Document 5 show changes in the average crystal size due to electron beam irradiation of each of the thin films of CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity. In thin films of IGZO with low crystallinity, crystalline IGZO of about 1 nm has been observed even before electron beam irradiation. Therefore, it is reported here that the presence of a completely amorphous structure could not be confirmed in IGZO. Furthermore, it has been shown that CAAC-IGZO thin films and nc-IGZO thin films have higher stability against electron beam irradiation than IGZO thin films with low crystallinity. Therefore, a thin film of CAAC-IGZO or a thin film of nc-IGZO is preferably used as a semiconductor of a transistor.

A transistor using a metal oxide has an extremely small leakage current in a non-conducting state. Specifically, an off current per 1 μm channel width of the transistor is on the order of yA/μm (10 ⁻²⁴ A/μm). is shown in Non-Patent Document 6. For example, a low-power-consumption CPU that utilizes the low leakage current characteristic of a transistor using a metal oxide has been disclosed (see Non-Patent Document 7).

In addition, application of a transistor using a metal oxide to a display device has been reported, taking advantage of the low leakage current characteristic of the transistor (see Non-Patent Document 8). In a display device, displayed images are switched several tens of times per second. The number of image switching times per second is called a refresh rate. Also, the refresh rate is sometimes called a drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is considered to be the cause of eye fatigue. Therefore, it has been proposed to reduce the number of times the image is rewritten by lowering the refresh rate of the display device. In addition, power consumption of the display device can be reduced by driving with a reduced refresh rate. Such a driving method is called idling stop (IDS) driving.

The discovery of CAAC and nc structures has contributed to improved electrical properties and reliability of transistors using metal oxides with CAAC or nc structures, as well as reduced cost and increased throughput of the manufacturing process. In addition, application research of the transistor to display devices and LSIs is underway, taking advantage of the characteristic of the transistor having a low leakage current.

As described above, the ALD method can form a film on a structure with a high aspect ratio, and can form a film with excellent coverage even on the side surfaces of the structure. By using the ALD method, a metal oxide having a CAAC structure can be easily formed regardless of the orientation of the film formation surface. For example, even if the structure has a convex shape or a concave shape, the metal oxide can be formed with good coverage over the top surface, bottom surface, side surfaces, and inclined surfaces of the structure. That is, a metal oxide having a substantially uniform film thickness in the normal direction can be formed on each film-forming surface. In the metal oxide formed on each of the top surface, bottom surface, side surfaces, and inclined surface of the structure, the ratio of the minimum thickness to the maximum thickness is 0.5 to 1, preferably 0.7 to 1, More preferably, it can be 0.9 or more and 1 or less. At this time, when the metal oxide has a crystal structure, its c-axis is oriented in a direction substantially parallel to the normal direction of each film-forming surface. That is, the c-axis is oriented perpendicular to each film formation surface.

FIG. 12 shows metal oxide 51 with In--M--Zn oxide formed on structure 50. In FIG. Here, the structural body refers to an element constituting a semiconductor device such as a transistor. The structure 50 includes conductors such as substrates, gate electrodes, source electrodes, and drain electrodes, insulators such as gate insulating films, interlayer insulating films, and underlying insulating films, and semiconductors such as metal oxides and silicon. . FIG. 12A shows the case where the film formation surface of the structure 50 is arranged parallel to the substrate (or base, not shown). FIG. 12B is an enlarged view of a region 53 that is part of the metal oxide 51 in FIG. 12A. FIG. 12B shows a state in which a layer containing indium and a layer containing the element M and zinc are stacked on the top surface or the bottom surface of the structure 50 . The layer containing In is arranged parallel to the film formation surface of the structure 50 , and the layer containing the element M and zinc is arranged parallel to the film formation surface of the structure 50 . That is, the ab plane of the metal oxide 51 is substantially parallel to the deposition surface of the structure 50, and the c-axis of the metal oxide 51 is the normal direction of the deposition surface of the structure 50. and are roughly parallel to each other.

FIG. 12C shows the case where the film formation surface of the structure 50 is arranged perpendicular to the substrate (or base, not shown). FIG. 12(D) is an enlarged view of a region 54 that is part of the metal oxide 51 in FIG. 12(C). FIG. 12D shows a state in which a layer containing indium and a layer containing the element M and zinc are stacked on the side surface of the structure 50 . The layer containing In is arranged parallel to the film formation surface of the structure 50 , and the layer containing the element M and zinc is arranged parallel to the film formation surface of the structure 50 . That is, the ab plane of the metal oxide 51 is substantially parallel to the deposition surface of the structure 50, and the c-axis of the metal oxide 51 is the normal direction of the deposition surface of the structure 50. and are roughly parallel to each other.

Details of the method for forming the metal oxide 51 having the In--M--Zn oxide will now be described with reference to FIG. Note that FIG. 13 shows an example in which an InO layer is formed as a layer containing indium and a (M, Zn)O layer is formed thereover as a layer containing the element M and zinc; Not exclusively. First, a (M, Zn)O layer may be formed, and an InO layer may be formed thereon. Alternatively, one of the layer containing the element M and the layer containing zinc may be formed over the InO layer, and the other of the layer containing the element M and the layer containing zinc may be formed thereover.

First, a raw material gas containing a precursor containing indium is introduced into the chamber, and the precursor is adsorbed on the surface of the structure 50 (see FIG. 13A). Here, the raw material gas includes a carrier gas such as argon or nitrogen in addition to the precursor. Precursors containing indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, and cyclopentadienylindium. Next, the inside of the chamber is purged to discharge excess precursors, reaction products, and the like from the chamber. Next, as a reactant, an oxidizing agent is introduced into the chamber and reacted with the adsorbed precursor to release components other than indium while indium is adsorbed on the substrate, thereby forming an InO layer in which indium and oxygen are bonded. (See FIG. 13(B).). Ozone, oxygen, water, or the like can be used as the oxidizing agent. Next, the inside of the chamber is purged to discharge excess reactants, reaction products, and the like from the chamber.

Next, a source gas containing a precursor containing the element M and a precursor containing zinc is introduced into the chamber to adsorb the precursor onto the InO layer (see FIG. 13C). Source gases include carrier gases such as argon and nitrogen in addition to precursors. When gallium is used as element M, gallium-containing precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium, gallium (III) acetylacetonate, tris(2,2,6,6-tetra Gallium methyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and the like can be used. As precursors containing zinc, dimethyl zinc, diethyl zinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionate) zinc, and the like can be used. Next, the inside of the chamber is purged to discharge excess precursors, reaction products, and the like from the chamber. Next, as a reactant, an oxidizing agent is introduced into the chamber and reacted with the adsorbed precursor to release components other than the element M and zinc while the element M and zinc are adsorbed on the substrate, thereby removing the element M and oxygen. and a layer in which zinc and oxygen are combined (M, Zn)O layers. Next, the inside of the chamber is purged to discharge excess reactants, reaction products, and the like from the chamber. By repeating the formation of the (M,Zn)O layer multiple times, the (M,Zn)O layer having a desired number of atoms, layers, and thickness may be formed (see FIG. 13D). ).

Next, an InO layer is formed again on the (M, Zn)O layer by the method described above (see FIG. 13E). By repeating the above method, the metal oxide 51 can be formed on the substrate or the structure.

In addition to the metal element, some precursors contain one or both of carbon and chlorine. A film formed using a carbon-containing precursor may contain carbon. Also, a film formed using a chlorine-containing precursor may contain chlorine.

As described above, by forming the metal oxide 51 using the ALD method, it is possible to form a metal oxide having a CAAC structure in which the c-axis is oriented substantially parallel to the normal direction of the film formation surface.

Here, as an example of an apparatus capable of forming a film by an ALD method, a structure of a film forming apparatus 4000 will be described with reference to FIGS. 14A and 14B. FIG. 14A is a schematic diagram of a multi-chamber film formation apparatus 4000, and FIG. 14B is a cross-sectional view of an ALD apparatus that can be used for the film formation apparatus 4000. FIG.

<Configuration example of deposition apparatus>
The film formation apparatus 4000 includes a loading/unloading chamber 4002 , a loading/unloading chamber 4004 , a transfer chamber 4006 , a film formation chamber 4008 , a film formation chamber 4009 , a film formation chamber 4010 , and a transfer arm 4014 . Here, the loading/unloading chamber 4002, the loading/unloading chamber 4004, and the film formation chambers 4008 to 4010 are connected to the transfer chamber 4006 independently. Accordingly, continuous film formation can be performed in the film formation chambers 4008 to 4010 without exposure to the atmosphere, and impurities can be prevented from entering the film. Also, contamination at the interface between the substrate and the film and at the interface between each film is reduced, and a clean interface can be obtained.

Note that the loading/unloading chamber 4002, the loading/unloading chamber 4004, the transfer chamber 4006, and the film formation chambers 4008 to 4010 are filled with an inert gas (such as nitrogen gas) whose dew point is controlled in order to prevent adhesion of moisture. It is preferable to maintain the reduced pressure.

In addition, an ALD apparatus can be used for the film formation chambers 4008 to 4010 . Further, any one of the film forming chambers 4008 to 4010 may be configured to use a film forming apparatus other than the ALD apparatus. Examples of film forming apparatuses that can be used in the film forming chambers 4008 to 4010 include a sputtering apparatus, a plasma enhanced CVD (PECVD) apparatus, a thermal CVD (TCVD) apparatus, and a photo CVD (Photo CVD) apparatus. , a metal CVD (MCVD: Metal CVD) device, an organic metal CVD (MOCVD: Metal Organic CVD) device, and the like. Further, one or more of the film formation chambers 4008 to 4010 may be provided with an apparatus having a function other than the film formation apparatus. Examples of the device include a heating device (typically a vacuum heating device), a plasma generator (typically a microwave plasma generator), and the like.

For example, when the deposition chamber 4008 is an ALD device, the deposition chamber 4009 is a PECVD device, and the deposition chamber 4010 is a metal CVD device, the metal oxide is used in the deposition chamber 4008, and the gate insulating film is used in the deposition chamber 4009. An insulating film that functions and a conductive film that functions as a gate electrode can be formed in the deposition chamber 4010 . At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be formed continuously without being exposed to the atmosphere.

In addition, although the deposition apparatus 4000 has a loading/unloading chamber 4002, a loading/unloading chamber 4004, and deposition chambers 4008 to 4010, the present invention is not limited to this. The film forming apparatus 4000 may be configured to have four or more film forming chambers. Further, the film forming apparatus 4000 may be of a single-wafer type, or may be of a batch type in which films are formed on a plurality of substrates at once.

<ALD device>
Next, the structure of an ALD apparatus that can be used for the film formation apparatus 4000 is described with reference to FIG. 14B. The ALD apparatus includes a film forming chamber (chamber 4020), a raw material supply unit 4021 (raw material supply units 4021a and 4021b), a raw material supply unit 4031, high-speed valves 4022a and 4022b as introduction amount controllers, and a raw material introduction port 4023. (raw material introduction ports 4023 a and 4023 b ), a raw material introduction port 4033 , a raw material discharge port 4024 and an exhaust device 4025 . Raw material introduction ports 4023a, 4023b, and 4033 installed in the chamber 4020 are connected to the raw material supply units 4021a, 4021b, and 4031 via supply pipes and valves, respectively, and a raw material discharge port 4024 is connected to a discharge pipe and valves. It is connected to an exhaust device 4025 via a pressure regulator.

Further, by connecting a plasma generator 4028 to the chamber 4020 as shown in FIG. 14B, film formation can be performed by a plasma ALD method in addition to the thermal ALD method. The plasma generator 4028 is preferably an ICP type plasma generator using a coil 4029 connected to a high frequency power supply. The high-frequency power source can output power having a frequency of 10 kHz or more and 100 MHz or less, preferably 1 MHz or more and 60 MHz or less, more preferably 10 MHz or more and 60 MHz or less. For example, power with frequencies of 13.56 MHz and 60 MHz can be output. In the plasma ALD method, a film can be formed without lowering the film forming rate even at a low temperature. Therefore, it is preferable to use a single wafer type film forming apparatus having a low film forming efficiency.

Inside the chamber is a substrate holder 4026 on which a substrate 4030 is placed. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, substrate holder 4026 may be floating or grounded. A heater 4027 is provided on the outer wall of the chamber, and the temperature of the inside of the chamber 4020, the substrate holder 4026, the surface of the substrate 4030, and the like can be controlled. The heater 4027 can control the surface temperature of the substrate 4030 to 100° C. to 500° C., preferably 200° C. to 400° C., and the temperature of the heater 4027 itself can preferably be set to 100° C. to 500° C.

In the raw material supply units 4021a, 4021b, and 4031, a raw material gas is formed from a solid raw material or a liquid raw material by vaporizers, heating means, or the like. Alternatively, the raw material supply units 4021a, 4021b, and 4031 may be configured to supply gaseous raw material gases.

In addition, FIG. 14B shows an example in which two source material supply units 4021 and one source material supply unit 4031 are provided; however, this embodiment is not limited to this. One or three or more raw material supply units 4021 may be provided. Also, two or more raw material supply units 4031 may be provided. Further, the high-speed valves 4022a and 4022b can be precisely controlled by time, and are configured to control the supply of the raw material gas supplied from the raw material supply unit 4021a and the raw material gas supplied from the raw material supply unit 4021b.

In the film forming apparatus shown in FIG. 14B, the substrate 4030 is loaded onto the substrate holder 4026, and the chamber 4020 is sealed. , preferably 200° C. or higher and 400° C. or lower). A thin film is formed on the substrate surface by repeating the evacuation by Further, in the formation of the thin film, the raw material gas supplied from the raw material supply unit 4021b and the evacuation by the exhaust device 4025 may be further performed. The temperature of the heater 4027 may be appropriately determined according to the type of film to be formed, source gas, desired film quality, and heat resistance of the substrate, films provided thereon, and elements. For example, the temperature of the heater 4027 may be set to 200° C. to 300° C. or 300° C. to 500° C. for deposition.

By forming a film while heating the substrate 4030 with the use of the heater 4027, heat treatment of the substrate 4030 required in a later process can be omitted. That is, by using the chamber 4020 provided with the heater 4027 or the deposition apparatus 4000, formation of a film over the substrate 4030 and heat treatment of the substrate 4030 can be performed simultaneously.

In the deposition apparatus shown in FIG. 14B, a metal oxide can be formed by appropriately selecting materials (such as a volatile organometallic compound) used in the material supply portion 4021 and the material supply portion 4031 . In the case of forming an In--Ga--Zn oxide containing indium, gallium, and zinc as the metal oxide, a deposition apparatus provided with at least three source supply units 4021 and at least one source supply unit 4031 is used. is preferred. A precursor containing indium may be supplied from the first raw material supply unit 4021 , a precursor containing gallium may be supplied from the second raw material supply unit 4021 , and a precursor containing zinc may be supplied from the third raw material supply unit 4021 . preferable. When a precursor containing gallium and zinc is used to form the metal oxide, at least two raw material supply units 4021 may be provided. As the indium-containing precursor, the gallium-containing precursor, and the zinc-containing precursor, the precursors described above can be used.

A reactant is supplied from the raw material supply unit 4031 . An oxidant containing at least one of ozone, oxygen, and water can be used as a reactant.

By appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, oxides containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, and the like ( It is possible to form an insulating layer containing a complex oxide). Specifically, an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, an insulating layer containing aluminum silicate, or the like can be deposited. In addition, by appropriately selecting the raw materials (such as volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, metal layers such as a tungsten layer and a titanium layer, and nitride layers such as a titanium nitride layer can be formed. Thin films can also be deposited.

For example, when a hafnium oxide layer is formed by an ALD apparatus, a first raw material gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamide hafnium (TDMAHf)) is used. and a second raw material gas of ozone (O ₃ ) and oxygen (O ₂ ) as oxidants. In this case, the first raw material gas supplied from the raw material supply unit 4021a is TDMAHf, and the second raw material gas supplied from the raw material supply unit 4031 is ozone and oxygen. The chemical formula of tetrakisdimethylamide hafnium is Hf[N(CH ₃ ) ₂ ] ₄ . Other material liquids include tetrakis(ethylmethylamido)hafnium. Moreover, water can be used as the second raw material gas.

When forming an aluminum oxide layer by an ALD apparatus, a first raw material gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (TMA: trimethylaluminum, etc.), and ozone (O ₃ ) and oxygen as oxidants. A second source gas containing (O ₂ ) is used. In this case, the first raw material gas supplied from the raw material supply unit 4021a is TMA, and the second raw material gas supplied from the raw material supply unit 4031 is ozone and oxygen. The chemical formula of trimethylaluminum is Al(CH ₃ ) ₃ . Other material liquids include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). Moreover, water can be used as the second raw material gas.

FIG. 15 describes different configurations of an ALD apparatus that can be used in the deposition apparatus 4000. FIG. A detailed description of the same configuration and functions as those of the ALD apparatus shown in FIG. 14B may be omitted.

FIG. 15A is a schematic diagram showing one mode of a plasma ALD apparatus. A plasma ALD apparatus 4100 is provided with a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120 . Reaction chamber 4120 can be referred to as a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively called a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124 , and the plasma generation chamber 4111 has a raw material inlet 4133 . In addition, plasma 4131 can be generated in the plasma generation chamber 4111 by applying high frequency such as RF or microwave to the gas introduced into the plasma generation chamber 4111 by the plasma generation device 4128 . When plasma 4131 is generated using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Plasma generated using such microwaves is sometimes called ECR (Electron Cyclotron Resonance) plasma. The reaction chamber 4120 also has a substrate holder 4126 on which a substrate 4130 is placed. A source gas introduced from source inlet 4123 is decomposed by heat from a heater provided in reaction chamber 4120 and deposited on substrate 4130 . Also, the raw material gas introduced from the raw material introduction port 4133 is brought into a plasma state by the plasma generator 4128 . The plasma-state source gas recombines with electrons and other molecules before reaching the surface of the substrate 4130 , becomes a radical state, and reaches the substrate 4130 . Such an ALD apparatus that forms a film using radicals is sometimes called a radical ALD (Radical-Enhanced ALD) apparatus. Further, the plasma ALD apparatus 4100 shows a configuration in which the plasma generation chamber 4111 is provided above the reaction chamber 4120, but this embodiment is not limited to this. A plasma generation chamber 4111 may be provided adjacent to the side of the reaction chamber 4120 .

FIG. 15B is a schematic diagram showing one mode of a plasma ALD apparatus. A plasma ALD apparatus 4200 has a chamber 4220 . The chamber 4220 has an electrode 4213, a material outlet 4224, a substrate holder 4226, and a substrate 4230 is placed thereon. The electrode 4213 has a raw material inlet 4223 and a shower head 4214 for supplying the introduced raw material gas into the chamber 4220 . A power source 4215 capable of applying a high frequency is connected to the electrode 4213 via a capacitor 4217 . The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, substrate holder 4226 may be floating or grounded. Electrode 4213 and substrate holder 4226 function as upper and lower electrodes for generating plasma 4231, respectively. A source gas introduced from source inlet 4223 is decomposed by heat from a heater provided in chamber 4220 and deposited on substrate 4230 . Alternatively, the raw material gas introduced from the raw material introduction port 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226 . A source gas in a plasma state is incident on the substrate 4230 due to a potential difference (also referred to as an ion sheath) generated between the plasma 4231 and the substrate 4230 .

FIG. 15(C) is a schematic diagram showing one mode of a plasma ALD apparatus different from that in FIG. 15(B). A plasma ALD apparatus 4300 has a chamber 4320 . The chamber 4320 has an electrode 4313, a material outlet 4324, a substrate holder 4326, and a substrate 4330 is placed thereon. The electrode 4313 has a raw material introduction port 4323 and a shower head 4314 for supplying the introduced raw material gas into the chamber 4320 . A power supply 4315 capable of applying a high frequency is connected to the electrode 4313 via a capacitor 4317 . The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, substrate holder 4326 may be floating or grounded. Electrode 4313 and substrate holder 4326 function as upper and lower electrodes for generating plasma 4331, respectively. The plasma ALD apparatus 4300 differs from the plasma ALD apparatus 4200 in that it has a mesh 4319 connected between the electrode 4313 and the substrate holder 4326 via a capacitor 4322 to a power source 4321 capable of applying high frequency. Plasma 4231 can be separated from substrate 4130 by providing mesh 4319 . A source gas introduced from source inlet 4323 is decomposed by heat from a heater provided in chamber 4320 and deposited on substrate 4330 . Alternatively, the raw material gas introduced from the raw material introduction port 4323 becomes a plasma state between the electrode 4313 and the substrate holder 4326 . The raw material gas in the plasma state has its charges removed by the mesh 4319 and reaches the substrate 4130 in an electrically neutral state such as radicals. Therefore, film formation can be performed in which damage due to ion incidence and plasma is suppressed.

<Deposition sequence>
FIG. 16A shows a film forming sequence using the ALD apparatus shown in FIG. 14B. First, the substrate 4030 is set on the substrate holder 4026 inside the chamber 4020 (S101). Next, the temperature of the heater 4027 is adjusted (S102). Next, the substrate 4030 is held on the substrate holder 4026 so that the temperature of the substrate 4030 becomes uniform within the substrate surface (S103). Next, film formation is performed by the first to fourth steps described above. That is, the first source gas and the second source gas are alternately introduced into the chamber 4020 to form a film on the substrate 4030 (S104). Further, between S103 and S104, a process of making the inside of the chamber 4020 into an oxygen atmosphere may be performed. By setting the inside of the chamber 4020 to an oxygen atmosphere after the substrate 4030 is set and held, oxygen can be added to the substrate 4030 and a film provided over the substrate 4030 in some cases. In some cases, hydrogen can be released from the substrate 4030 before deposition and from the film provided over the substrate 4030 . In some cases, hydrogen in the substrate 4030 or the film reacts with oxygen added in the substrate 4030 or the film to become water (H ₂ O) and leave the substrate 4030 or the film.

FIG. 16B shows a specific example of the film formation sequence. According to S101 to S103 described above, the substrate 4030 is set on the substrate holder 4026, the temperature of the heater 4027 is adjusted, and the substrate 4030 is held.

Next, the first source gas and the second source gas are alternately introduced to form a film on the substrate 4030 (S104). The first source gas and the second source gas are each introduced in a pulsed manner. In FIG. 16B, ON indicates introduction of the first source gas and second source gas, and OFF indicates a period in which the source gas is not introduced. The inside of the chamber 4020 is evacuated during the period in which neither the first source gas nor the second source gas is introduced. The pulse time for introducing the first source gas into the chamber 4020 is preferably 0.1 seconds or more and 1 second or less, preferably 0.1 seconds or more and 0.5 seconds or less. The period during which the first source gas is not introduced, that is, the period during which the chamber 4020 is evacuated is 1 second or more and 15 seconds or less, preferably 1 second or more and 5 seconds or less. The pulse time for introducing the second source gas into the chamber 4020 is preferably 0.1 seconds or more and 30 seconds or less, preferably 0.3 seconds or more and 15 seconds or less. The period during which the second source gas is not introduced, that is, the period during which the chamber 4020 is evacuated is 1 second or more and 15 seconds or less, preferably 1 second or more and 5 seconds or less.

The film formation includes introduction of the first raw material gas (the first step above), exhaustion of the first raw material gas (the second step above), introduction of the second raw material gas (the third step above), and introduction of the second raw material. A film having a desired film thickness is formed by repeating gas exhaustion (the fourth step described above) as one cycle.

Further, in the case where the process of making the inside of the chamber 4020 into an oxygen atmosphere is performed between S103 and S104, the second source gas may be introduced into the chamber 4020. FIG. As the second raw material gas, one or more selected from ozone (O ₃ ), oxygen (O ₂ ) and water (H ₂ O), which function as an oxidizing agent, is preferably introduced. In this embodiment, ozone (O ₃ ) and oxygen (O ₂ ) are used as the second source gas. At this time, the second source gas is preferably introduced in a pulsed manner as in the method shown in S104, but the present invention is not limited to this. The second source gas may be introduced continuously. The inside of the chamber 4020 is evacuated during the period in which the second source gas is not introduced. The pulse time for introducing the second source gas into the chamber 4020 is preferably 0.1 seconds or more and 30 seconds or less, preferably 0.3 seconds or more and 15 seconds or less. The period during which the second source gas is not introduced, that is, the period during which the chamber 4020 is evacuated is 1 second or more and 15 seconds or less, preferably 1 second or more and 5 seconds or less. By introducing the second source gas such as the oxidant into the chamber 4020, the substrate 4030 or the film provided over the substrate 4030 is exposed to the second source gas such as the oxidant.

Note that if the temperature control of the heater 4027 is unnecessary after setting the substrate 4030 (S101), it may be omitted. Further, if there is no need to change the inside of the chamber 4020 to an oxygen atmosphere after holding the substrate 4030 (S103), it may be omitted.

FIG. 16C shows an example of a sequence for film formation using a plurality of kinds of source gases containing precursors. In FIG. 16C, the precursor-containing source gas is the first source gas, the third source gas, and the fourth source gas, and the oxidant-containing source gas is the second source gas. According to S101 to S103 described above, the substrate 4030 is set on the substrate holder 4026, the temperature of the heater 4027 is adjusted, and the substrate 4030 is held.

Next, a first source gas, a second source gas, a third source gas, a second source gas, a fourth source gas, and a second source gas are sequentially introduced to form a film on the substrate 4030 . A film is formed (S104). The introduction of the first source gas to the fourth source gas is performed in a pulsed manner. In FIG. 16C, the introduction of the first source gas to the fourth source gas is indicated by ON, and the period in which the source gas is not introduced is indicated by OFF. The inside of the chamber 4020 is exhausted during a period in which none of the first to fourth source gases is introduced. The pulse time for introducing the first source gas, the third source gas, and the fourth source gas into the chamber 4020 is 0.1 seconds or more and 1 second or less, preferably 0.1 seconds or more and 0.5 seconds or less. is preferable. In addition, the period during which the first source gas, the third source gas, and the fourth source gas are not introduced, that is, the time during which the chamber 4020 is evacuated is 1 second or more and 15 seconds or less, preferably 1 second or more. 5 seconds or less. The pulse time for introducing the second source gas into the chamber 4020 is preferably 0.1 seconds or more and 30 seconds or less, preferably 0.3 seconds or more and 15 seconds or less. The period during which the second source gas is not introduced, that is, the period during which the chamber 4020 is evacuated is 1 second or more and 15 seconds or less, preferably 1 second or more and 5 seconds or less.

Film formation is carried out by introducing a first raw material gas, discharging a first raw material gas, introducing a second raw material gas, discharging a second raw material gas, introducing a third raw material gas, and discharging a third raw material gas. exhaust, introduction of the second source gas, exhaust of the second source gas, introduction of the fourth source gas, exhaust of the fourth source gas, introduction of the second source gas, and exhaust of the second source gas A film having a desired film thickness is formed by repeating one cycle.

For example, when the first source gas contains a precursor containing indium, the third source gas contains a precursor containing gallium, and the fourth source gas contains a precursor containing zinc, the sequence shown in FIG. can form an In--Ga--Zn oxide.

Note that in the sequence shown in FIG. 16C, the order of introduction of the first source gas, the third source gas, and the fourth source gas is not limited to this. Moreover, the number of introductions of the first source gas, the third source gas, and the fourth source gas during one cycle is not limited to one. By introducing a source gas multiple times in one cycle, a film having a high concentration of metal elements contained in the source gas can be formed. That is, by changing the number of times each gas is introduced, the atomic ratio of the formed film can be controlled. Also, the first source gas, the third source gas, and the fourth source gas, or two types of source gases selected from these source gases may be introduced into the chamber 4020 at the same time.

This embodiment can be implemented in appropriate combination with structures described in other embodiments, examples, and the like.

(Embodiment 3)
In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[Storage device 1]
FIG. 18 illustrates an example of a semiconductor device (memory device) using a capacitor that is one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistor 200 . At least part of the capacitor 100 or the transistor 300 preferably overlaps with the transistor 200 . As a result, the area occupied by the capacitive element 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated. The semiconductor device according to the present embodiment is, for example, a logic circuit represented by a CPU (Central Processing Unit) or GPU (Graphics Processing Unit), or a DRAM (Dynamic Random Access Memory) or NVM (Non-Volatile Memory). can be applied to a memory circuit represented by

Note that the transistor 200 described in the above embodiment can be used as the transistor 200 . Therefore, the description in the above embodiment can be referred to for the transistor 200 and the layer including the transistor 200 .

The transistor 200 is a transistor whose channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a low off-state current, when it is used for a memory device, stored data can be retained for a long time. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced. In addition, the transistor 200 has better electrical characteristics at high temperatures than a transistor using silicon for a semiconductor layer. For example, the transistor 200 exhibits good electrical characteristics even in the temperature range of 125.degree. C. to 150.degree. Also, in the temperature range of 125° C. to 150° C., the transistor 200 has a transistor on/off ratio of ten orders of magnitude or more. In other words, the transistor 200 has better characteristics such as on current and frequency characteristics, which are examples of transistor characteristics, as the temperature rises, compared to a transistor using silicon for a semiconductor layer.

In the semiconductor device shown in FIG. 18, a wiring 1001 is electrically connected to the source of the transistor 300, a wiring 1002 is electrically connected to the drain of the transistor 300, and a wiring 1007 is electrically connected to the gate of the transistor 300. there is A wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 1004 is electrically connected to the first gate of the transistor 200, and a wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. The other of the source and drain of the transistor 200 is electrically connected to one of the electrodes of the capacitor 100 , and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100 .

The semiconductor device illustrated in FIG. 18 has a characteristic that electric charge charged in one electrode of the capacitor 100 can be held by switching of the transistor 200, so that information can be written, held, and read. Further, the transistor 200 is an element provided with a second gate in addition to a source, a first gate, and a drain. That is, since it is a 4-terminal element, it is represented by MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistive Random Access Memory), Phase-change memory, etc. using MTJ (Magnetic Tunnel Junction) characteristics. It has a feature that independent control of input and output can be easily performed as compared with the terminal element. In addition, MRAM, ReRAM, and phase change memory may undergo structural changes at the atomic level when information is rewritten. On the other hand, the semiconductor device shown in FIG. 18 operates by charging or discharging electrons using a transistor and a capacitive element when rewriting information, and thus has excellent resistance to repetitive rewriting and little structural change.

Further, the semiconductor devices illustrated in FIG. 18 can form a memory cell array by being arranged in a matrix. In this case, the transistor 300 can be used as a reading circuit, a driver circuit, or the like connected to the memory cell array. Also, the semiconductor device shown in FIG. 18 forms a memory cell array as described above. When the semiconductor device shown in FIG. 18 is used as a memory element, for example, an operating frequency of 200 MHz or higher can be achieved at a drive voltage of 2.5 V and an evaluation environmental temperature in the range of -40.degree. C. to 85.degree.

<Transistor 300>
The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate electrode, an insulator 315 functioning as a gate insulator, a semiconductor region 313 consisting of part of the substrate 311, and functioning as a source or drain region. It has a low resistance region 314a and a low resistance region 314b.

Here, an insulator 315 is placed over the semiconductor region 313 and a conductor 316 is placed over the insulator 315 . In addition, the transistors 300 formed in the same layer are electrically isolated by an insulator 312 functioning as an element isolation insulating layer. As the insulator 312, an insulator similar to the insulator 326 described later or the like can be used. Transistor 300 can be either p-channel or n-channel.

The substrate 311 contains a semiconductor such as a silicon-based semiconductor in the region where the channel of the semiconductor region 313 is formed, the region in the vicinity thereof, the low-resistance regions 314a and 314b serving as the source region or the drain region, and the like. is preferred, and preferably contains single crystal silicon. Alternatively, a material including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

The low-resistance region 314a and the low-resistance region 314b are made of an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron in addition to the semiconductor material applied to the semiconductor region 313. contains elements that

The conductor 316 functioning as a gate electrode is a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron, a metal material, or an alloy. material, or a conductive material such as a metal oxide material can be used.

Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and it is particularly preferable to use tungsten from the viewpoint of heat resistance.

Here, in the transistor 300 shown in FIG. 18, the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. Such a transistor 300 is also called a FIN transistor because it utilizes the projections of the semiconductor substrate. Note that an insulator that functions as a mask for forming the protrusion may be provided in contact with the upper portion of the protrusion. Further, here, the case where a part of the semiconductor substrate is processed to form a convex portion is shown, but a semiconductor film having a convex shape may be formed by processing an SOI substrate.

Note that the transistor 300 illustrated in FIG. 18 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

In addition, as shown in FIG. 18, the semiconductor device has a stacked transistor 300 and a transistor 200 . For example, the transistor 300 can be formed using a silicon-based semiconductor material, and the transistor 200 can be formed using an oxide semiconductor. In this manner, the semiconductor device shown in FIG. 18 can be formed by combining a silicon-based semiconductor material and an oxide semiconductor in different layers. Further, the semiconductor device shown in FIG. 18 can be manufactured by the same process as the manufacturing equipment used for silicon-based semiconductor materials, and can be highly integrated.

<Capacitor>
Capacitive element 100 includes insulator 114 on insulator 160, insulator 140 on insulator 114, conductor 110 disposed in an opening formed in insulator 114 and insulator 140, conductor Insulator 130 over 110 and insulator 140 , conductor 120 over insulator 130 , and insulator 150 over conductor 120 and insulator 130 . Here, at least a portion of conductor 110 , insulator 130 , and conductor 120 are placed in openings formed in insulator 114 and insulator 140 .

The conductor 110 functions as the lower electrode of the capacitor 100 , the conductor 120 functions as the upper electrode of the capacitor 100 , and the insulator 130 functions as the dielectric of the capacitor 100 . The capacitive element 100 has a configuration in which the upper electrode and the lower electrode face each other with a dielectric interposed not only on the bottom surface but also on the side surfaces in the openings of the insulator 114 and the insulator 140. Capacity can be increased. Therefore, the capacitance of the capacitive element 100 can be increased as the depth of the opening is increased. By increasing the capacitance per unit area of the capacitive element 100 in this manner, miniaturization or high integration of the semiconductor device can be promoted.

An insulator that can be used for the insulator 280 may be used as the insulator 114 and the insulator 150 . In addition, the insulator 140 preferably functions as an etching stopper when the opening of the insulator 114 is formed, and an insulator that can be used for the insulator 212 may be used.

The shape of the openings formed in the insulators 114 and 140 when viewed from above may be a quadrangle, a polygonal shape other than a quadrangle, or a polygonal shape with curved corners. , or a circular shape including an ellipse. Here, it is preferable that the opening and the transistor 200 overlap with each other in a large area when viewed from above. With such a structure, the area occupied by the semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

Conductor 110 is placed in contact with insulator 140 and openings formed in insulator 114 . Preferably, the top surface of the conductor 110 substantially coincides with the top surface of the insulator 140 . A conductor 152 provided on the insulator 160 is in contact with the lower surface of the conductor 110 . The conductor 110 is preferably formed by an ALD method, a CVD method, or the like. For example, a conductor that can be used for the conductor 205 may be used.

Insulator 130 is arranged to cover conductor 110 and insulator 140 . For example, the insulator 130 is preferably formed using an ALD method, a CVD method, or the like. The insulator 130 is made of, for example, silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, nitridation. Hafnium or the like may be used, and a stacked layer or a single layer can be provided. For example, as the insulator 130, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used.

For the insulator 130, a material with high dielectric strength such as silicon oxynitride or a high dielectric constant (high-k) material is preferably used. Alternatively, a laminated structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

Note that insulators of high dielectric constant (high-k) materials (high dielectric constant materials) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, and oxynitrides containing aluminum and hafnium. , oxides with silicon and hafnium, oxynitrides with silicon and hafnium, nitrides with silicon and hafnium, and the like. By using such a high-k material, the capacitance of the capacitor 100 can be sufficiently secured even if the insulator 130 is thick. By increasing the thickness of the insulator 130, leakage current generated between the conductors 110 and 120 can be suppressed.

On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and vacancies. silicon oxide, resin, etc. For example, in order of silicon nitride (SiN _x ) deposited using the ALD method, silicon oxide (SiO _x ) deposited using the plasma ALD method, and silicon nitride (SiN _x ) deposited using the ALD method. A laminated insulating film can be used. By using such an insulator with high dielectric strength, dielectric strength is improved, and electrostatic breakdown of the capacitor 100 can be suppressed.

Alternatively, the insulator 130 may have a structure similar to that of the first gate insulator or the second gate insulator described in the above embodiment.

Specifically, in the case where an In--Ga--Zn oxide is used as the oxide 230, the insulator 130 is gallium oxide or an In--Ga--Zn oxide that has a higher insulating property than the oxide 230b. preferably included. Since the element forming the insulator 130 and the element forming the oxide 230 are common, even if the element forming the insulator 130 diffuses into the oxide 230, the resistance of the oxide 230 is lowered. does not cause

In particular, gallium oxide is a high dielectric constant insulating material having a dielectric constant higher than that of silicon nitride, and is a so-called high-k material. As semiconductor devices become finer and more highly integrated, problems such as leakage current may occur due to thinner dielectrics. By using a high-k material for an insulator that functions as a dielectric, it is possible to reduce the equivalent oxide thickness (EOT) of the dielectric while maintaining the physical thickness.

Also, the insulator 130 is formed on the bottom and sides of the opening formed in the insulator 114 or the like. In addition, it is preferable that the thickness of the insulator 130 functioning as a dielectric is uniform on the bottom of the opening and on the side surfaces. The ALD method is a film forming method that is excellent in covering a structure having steps and unevenness. Therefore, by forming the insulator 130 by the ALD method, the thickness of the insulator 130 can be uniform at the bottom and side surfaces of the opening.

Conductor 120 is arranged to fill the openings formed in insulator 140 and insulator 114 . In addition, the conductor 120 is electrically connected to the wiring 1005 through the conductors 112 and 153 . The conductor 120 is preferably formed by an ALD method, a CVD method, or the like. For example, a conductor that can be used for the conductor 205 may be used.

Further, since the transistor 200 includes an oxide semiconductor, compatibility with the capacitor 100 is excellent. Specifically, since the transistor 200 including an oxide semiconductor has low off-state current, it is possible to retain stored data for a long time by using the transistor 200 in combination with the capacitor 100 .

<Wiring layer>
A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Also, the wiring layer can be provided in a plurality of layers depending on the design. Here, for conductors functioning as plugs or wiring, a plurality of structures may be grouped together and given the same reference numerals. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as a wiring and a part of the conductor functions as a plug.

For example, an insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order over the transistor 300 as interlayer films. In the insulators 320, 322, 324, and 326, conductors 328, 330, and the like, which are electrically connected to the conductor 153 functioning as terminals, are embedded. Note that the conductors 328 and 330 function as plugs or wirings.

Moreover, the insulator functioning as an interlayer film may function as a planarization film covering the uneven shape thereunder. For example, the top surface of the insulator 322 may be planarized by a chemical mechanical polishing (CMP) method or the like to improve planarity.

A wiring layer may be provided over the insulator 326 and the conductor 330 . For example, in FIG. 18, an insulator 350, an insulator 352, and an insulator 354 are stacked in order. A conductor 356 is formed over the insulators 350 , 352 , and 354 . Conductor 356 functions as a plug or wiring.

An insulator 360 , an insulator 362 , an insulator 212 , and an insulator 216 are stacked in this order over the insulator 354 and the conductor 356 . In addition, the insulator 360 , the insulator 362 , the insulator 212 , and the insulator 216 are embedded with a conductor 366 , a conductor forming the transistor 200 (the conductor 205 ), and the like. Note that the conductor 366 functions as a plug electrically connected to the transistor 300 or a wiring.

In addition, the insulator 114, the insulator 140, the insulator 130, the insulator 150, and the insulator 154 are embedded with the conductor 112, the conductors forming the capacitor 100 (the conductor 120 and the conductor 110), and the like. is Note that the conductor 112 functions as a plug or a wiring that electrically connects the capacitor 100, the transistor 200, or the transistor 300 and the conductor 153 functioning as a terminal.

A conductor 153 is provided over the insulator 154 and is covered with an insulator 156 . Here, the conductor 153 is in contact with the top surface of the conductor 112 and functions as a terminal of the capacitor 100 , the transistor 200 , or the transistor 300 .

Note that insulators that can be used as an interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, and the like. For example, by using a material with a low dielectric constant for an insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, the material should be selected according to the function of the insulator.

For example, the insulator 320, the insulator 322, the insulator 326, the insulator 352, the insulator 354, the insulator 362, the insulator 114, the insulator 150, the insulator 156, and the like have an insulator with a low dielectric constant. is preferred. For example, the insulator includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, and silicon oxide with vacancies. , resin and the like. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having vacancies. and resin. Since silicon oxide and silicon oxynitride are thermally stable, by combining them with a resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. Examples of resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

In addition, the resistivity of the insulator provided over or under the conductor 152 or the conductor 153 is 1.0×10 ¹² Ωcm to 1.0×10 ¹⁵ Ωcm, preferably 5.0×10 ¹² Ωcm to 1.0×10 15 Ωcm. 0×10 ¹⁴ Ωcm or less, more preferably 1.0×10 ¹³ Ωcm or more and 5.0×10 ¹³ Ωcm or less. By setting the resistivity of the insulator provided above or below the conductor 152 or the conductor 153 to be in the above range, the insulator can maintain its insulating property and the transistor 200, the transistor 300, the capacitor 100, and the electric charge accumulated between wirings such as the conductor 152 can be dispersed, and characteristic defects and electrostatic breakdown of the transistor and the semiconductor device including the transistor due to the electric charge can be suppressed. Silicon nitride or silicon nitride oxide can be used as such an insulator. For example, the resistivity of insulator 160 or insulator 154 may be set within the above range.

In addition, when a transistor including an oxide semiconductor is surrounded by an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, electrical characteristics of the transistor can be stabilized. Therefore, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used for the insulators 324, 350, 360, and the like.

Examples of insulators having a function of suppressing permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. Insulators including lanthanum, neodymium, hafnium, or tantalum may be used in single layers or stacks. Specifically, as an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. , ruthenium and the like can be used. Alternatively, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

For example, the conductor 328, the conductor 330, the conductor 356, the conductor 366, the conductor 112, the conductor 152, the conductor 153, and the like are metal materials, alloy materials, and metal nitride materials formed of the above materials. , or a conductive material such as a metal oxide material can be used in single or stacked layers. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably made of a low-resistance conductive material such as aluminum or copper. Wiring resistance can be reduced by using a low-resistance conductive material.

<Wiring or Plug in Layer Provided with Oxide Semiconductor>
Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region is provided near the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided near the insulator having the excess oxygen region.

For example, in FIG. 18, an insulator 278 may be provided between the insulator 280 (insulator 280 a and insulator 280 b ) containing excess oxygen and the conductor 246 . Further, the insulator 278 and the insulator 274 are preferably provided in contact with each other. A structure in which the conductor 246 and the transistor 200 are sealed with insulators 278 and 274 having barrier properties can be employed.

In other words, the provision of the insulator 278 can prevent excess oxygen in the insulator 280 from being absorbed by the conductor 246 . In addition, with the insulator 278 , hydrogen, which is an impurity, can be prevented from diffusing into the transistor 200 through the conductor 246 .

Here, the conductor 246 functions as a plug electrically connected to the transistor 200 or the transistor 300 or as a wiring.

The above is the description of the configuration example. With this structure, a semiconductor device including a transistor including an oxide semiconductor can be miniaturized or highly integrated. Alternatively, in a semiconductor device including a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

Note that FIG. 18 shows an example in which the capacitor 100 is provided over the transistor 200; however, the semiconductor device described in this embodiment is not limited thereto. For example, as shown in FIG. 19, in adjacent memory cells, the capacitor 100a may be arranged above the transistor 200a and the capacitor 100b may be arranged below the transistor 200b.

In the memory device shown in FIG. 19 , a wiring 1001 is electrically connected to the source of the transistor 300 and a wiring 1002 is electrically connected to the drain of the transistor 300 . A wiring 1003a is electrically connected to one of the source and the drain of the transistor 200a. The other of the source and the drain of the transistor 200a is electrically connected to one of the electrodes of the capacitor 100a, and the wiring 1005a is electrically connected to the other of the electrodes of the capacitor 100a. The wiring 1003b is electrically connected to one of the source and drain of the transistor 200b. The other of the source and drain of the transistor 200b is electrically connected to one of the electrodes of the capacitor 100b, and the wiring 1005b is electrically connected to the other of the electrodes of the capacitor 100b.

FIG. 19 shows a transistor 200a and a capacitor 100a and a transistor 200b and a capacitor 100b which are included in adjacent memory cells. Transistors 200a and 200b have the same structure as transistor 200. FIG. Note that the transistor 200 b is different from the transistor 200 in that the conductor 240 c is in contact with at least part of the top surface of the conductor 247 through the opening 248 . Differences from the transistor 200 will be described below.

Transistor 200 b has conductor 240 d , opening 248 , and conductor 240 c located within opening 248 . Also, the conductor 240c is in contact with at least part of the upper surface of the conductor 247 through the opening 248 . By connecting the conductor 240c and the conductor 247, electrical resistance between the other of the source and the drain of the transistor 200b and the conductor 247 can be reduced.

Conductors 247 are disposed in openings formed in insulator 150 , insulator 362 , insulator 212 , insulator 214 and insulator 216 . At least part of the top surface of the conductor 247 is exposed from the insulator 216, and preferably the top surface of the conductor 247 and the top surface of the insulator 216 substantially coincide.

Here, the conductor 247 functions as a plug for electrical connection with one electrode of the capacitor 100b provided below the insulator 362 . Note that the conductor 247 may be electrically connected to a gate of a transistor provided below the insulator 362 or may be electrically connected to a wiring provided below the insulator 362. may Note that the conductor 247 may be extended to function as a wiring.

An opening 248 that exposes at least part of the conductor 247 is formed in the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b.

In addition, although the conductor 247 is provided under the conductor 240c in FIG. 19, the semiconductor device described in this embodiment is not limited to this. For example, the conductor 247 may be provided under the conductor 240d, or the conductor 247 may be provided under both the conductor 240c and the conductor 240d.

Capacitive elements 100 a and 100 b have the same structure as the capacitive element 100 . That is, the capacitor 100a has a conductor 110a, an insulator 130a, and a conductor 120a, and the capacitor 100b has a conductor 110b, an insulator 130b, and a conductor 120b. Conductors 110 a and 110 b have the same structure as conductor 110 . Insulator 130 a and insulator 130 b have the same configuration as insulator 130 . Conductors 120 a and 120 b have the same configuration as conductor 120 .

Here, the capacitor 100a preferably overlaps with the transistors 200a and 200b. For example, the capacitor 100a preferably overlaps with the channel formation regions of the transistors 200a and 200b. The capacitor 100b preferably overlaps with the transistors 200a and 200b. For example, the capacitor 100b preferably overlaps with a channel formation region of the transistor 200a and a channel formation region of the transistor 200b.

By arranging the capacitor 100a and the capacitor 100b in this manner, the capacitor 100a and the capacitor 100b can be formed without increasing the area occupied by the capacitor 100a, the capacitor 100b, the transistor 200a, and the transistor 200b in a top view. can increase the capacitance of Therefore, the semiconductor device according to this embodiment can be miniaturized or highly integrated.

Further, as shown in FIG. 20, a plurality of openings for providing the capacitive elements 100a and 100b may be provided. Here, the conductor 110a may be provided separately at each opening. Similarly, conductors 110b may be provided separately for each opening. Thereby, the capacitive element 100a and the capacitive element 100b can be formed on the side surface of each opening. Therefore, the capacitive element 100a and the capacitive element 100b shown in FIG. 20 can increase the capacitance while occupying the same area as the capacitive element 100a and the capacitative element 100b shown in FIG.

Note that FIGS. 19 and 20 show examples in which the capacitor 100a and the capacitor 100b are provided above and below the transistor 200a and the transistor 200b, respectively; however, the semiconductor device described in this embodiment is not limited to this. . For example, a structure in which the capacitor 100b and the transistor 200b are provided without providing the capacitor 100a and the transistor 200a may be employed. Note that at least part of the capacitor 100b or the transistor 300 preferably overlaps with the transistor 200b. As a result, the area occupied by the capacitive element 100b, the transistor 200b, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

Note that heat treatment at a high temperature exceeding 700° C. may be required in the manufacturing process of the capacitor 100b. If such high-temperature heat treatment is performed after the transistor 200b is formed, the oxide 230 may be affected by diffusion of impurities such as hydrogen or water, or oxygen, and electrical characteristics of the transistor 200b may be degraded.

However, by forming the transistor 200b over the capacitor 100b as shown in this modification, the thermal history in the manufacturing process of the capacitor 100b does not affect the transistor 200b. Accordingly, deterioration of the electrical characteristics of the transistor 200b can be prevented, and a semiconductor device having stable electrical characteristics can be provided.

[Storage device 2]
An example of a semiconductor device (storage device) using the semiconductor device of one embodiment of the present invention is shown in FIG. The semiconductor device shown in FIG. 21 has a transistor 200, a transistor 300, and a capacitor 100, similarly to the semiconductor device shown in FIG. However, the semiconductor device shown in FIG. 21 differs from the semiconductor device shown in FIG. 18 in that capacitor element 100 is of a planar type and transistors 200 and 300 are electrically connected.

In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300 and the capacitor 100 is provided above the transistors 300 and 200 . At least part of the capacitor 100 or the transistor 300 preferably overlaps with the transistor 200 . As a result, the area occupied by the capacitive element 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

Note that the above transistors 200 and 300 can be used as the transistors 200 and 300 . Therefore, the above description of the transistor 200, the transistor 300, and the layer including these can be referred to.

In the semiconductor device shown in FIG. 21, a wiring 2001 is electrically connected to the source of the transistor 300 and a wiring 2002 is electrically connected to the drain of the transistor 300 . A wiring 2003 is electrically connected to one of the source and the drain of the transistor 200, a wiring 2004 is electrically connected to the first gate of the transistor 200, and a wiring 2006 is electrically connected to the second gate of the transistor 200. It is connected to the. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and the wiring 2005 is electrically connected to the other electrode of the capacitor 100. . Note that hereinafter, a node to which the gate of the transistor 300, the other of the source and the drain of the transistor 200, and one of the electrodes of the capacitor 100 are connected is sometimes referred to as a node FG.

The semiconductor device illustrated in FIG. 21 has a characteristic that the potential of the gate (node FG) of the transistor 300 can be held by switching the transistor 200, so that data can be written, held, and read.

Further, the semiconductor devices illustrated in FIG. 21 can form a memory cell array by being arranged in a matrix.

Since a layer including the transistor 300 has a structure similar to that of the semiconductor device illustrated in FIG. 18, the above description can be referred to for the structure below the insulator 354 .

Over insulator 354 are insulators 360 , 362 , 212 , 214 and 216 . Here, as the insulator 360, an insulator having a function of suppressing permeation of impurities such as hydrogen and oxygen may be used in a manner similar to that of the insulator 350 and the like.

A conductor 366 is embedded in insulator 360 , insulator 362 , insulator 212 , insulator 214 and insulator 216 . The conductor 366 functions as a plug or wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. FIG. For example, conductor 366 is electrically connected to conductor 316 which functions as the gate electrode of transistor 300 .

In addition, the conductor 246 functions as a plug or wiring electrically connected to the transistor 200 or the transistor 300 . For example, the conductor 246 electrically connects the conductor 246 b functioning as the other of the source and drain of the transistor 200 and the conductor 110 functioning as one of the electrodes of the capacitor 100 through the conductor 246 . there is

Further, the planar capacitor 100 is provided above the transistor 200 . The capacitor 100 has a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric. Note that the conductor 110, the conductor 120, and the insulator 130 can be the same as those described for the memory device 1 described above.

Conductor 153 and conductor 110 are provided in contact with the upper surface of conductor 246 . The conductor 153 is in contact with the top surface of the conductor 246 and functions as a terminal of the transistor 200 or the transistor 300 .

The conductor 153 and the conductor 110 are covered with the insulator 130, and the conductor 120 is arranged so as to overlap with the conductor 110 with the insulator 130 interposed therebetween. Furthermore, the insulator 114 is placed over the conductor 120 and the insulator 130 .

In addition, FIG. 21 shows an example in which a planar capacitor is used as the capacitor 100, but the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIG. 22, a cylindrical capacitive element 100 as shown in FIG. 18 may be used as the capacitive element 100. In FIG.

Here, the description of FIG. 18 can be referred to for details of the capacitor 100 . However, as shown in FIG. 22, a configuration in which the conductor 152 is arranged on the conductor 246 and the conductor 112 is arranged on the conductor 152 is preferable. With such a structure, electrical connection between the conductor 246 and the conductor 112 can be made more reliable.

Also, an insulator 154 is preferably placed over the insulator 150 . An insulator that can be used for the insulator 160 may be used as the insulator 154 . A conductor 153 is provided in contact with the upper surface of the conductor 112 . The conductor 153 is in contact with the top surface of the conductor 112 and functions as a terminal of the capacitor 100 , the transistor 200 or the transistor 300 . Further, an insulator 156 is provided over the conductor 153 and the insulator 154 .

FIG. 22 shows an example in which the gate of the transistor 300 is electrically connected to the other of the source and the drain of the transistor 200 through one of the electrodes of the capacitor 100; The illustrated semiconductor device is not limited to this. For example, as shown in FIG. 23, the gate of transistor 300 may be electrically connected to one electrode of capacitor 100 through the other of the source and drain of transistor 200 . As a result, the area occupied by the capacitive element 100, the transistor 200, and the transistor 300 in a top view can be reduced, so that the semiconductor device according to this embodiment can be miniaturized or highly integrated.

This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

(Embodiment 4)
In this embodiment, a transistor using an oxide as a semiconductor (hereinafter also referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied with reference to FIGS. A storage device (hereinafter sometimes referred to as an OS memory device) will be described. An OS memory device is a memory device that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

<Configuration example of storage device>
FIG. 24A shows an example of the configuration of the OS memory device. A memory device 1400 has a peripheral circuit 1411 and a memory cell array 1470 . Peripheral circuitry 1411 includes row circuitry 1420 , column circuitry 1430 , output circuitry 1440 and control logic circuitry 1460 .

The column circuit 1430 has, for example, column decoders, precharge circuits, sense amplifiers, write circuits, and the like. The precharge circuit has a function of precharging the wiring. A sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wirings are wirings connected to memory cells included in the memory cell array 1470, and will be described later in detail. The amplified data signal is output to the outside of memory device 1400 via output circuit 1440 as data signal RDATA. Also, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select a row to be accessed.

The storage device 1400 is externally supplied with a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 as power supply voltages. Control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. Address signal ADDR is input to the row and column decoders, and WDATA is input to the write circuit.

The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and other control signals may be input as needed.

Memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in rows and columns. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. The number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.

Note that FIG. 24A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited to this. For example, as shown in FIG. 24B, a memory cell array 1470 may be provided over part of the peripheral circuit 1411 . For example, a structure in which a sense amplifier is provided under the memory cell array 1470 may be employed.

A configuration example of a memory cell that can be applied to the memory cell MC described above will be described with reference to FIG.

[DOSRAM]
25A to 25C show circuit configuration examples of memory cells of a DRAM. In this specification and the like, a DRAM using a 1-OS-transistor-1-capacitor-type memory cell is sometimes referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 1471 illustrated in FIG. 25A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes referred to as a top gate) and a back gate.

The transistor M1 has a first terminal connected to the first terminal of the capacitor CA, a second terminal connected to the wiring BIL, a gate connected to the wiring WOL, and a back gate of the transistor M1. are connected to the wiring BGL. A second terminal of the capacitive element CA is connected to the wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. A low-level potential is preferably applied to the wiring CAL when data is written and read. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Here, a memory cell 1471 illustrated in FIG. 25A corresponds to the memory device illustrated in FIG. That is, the transistor M1 corresponds to the transistor 200, the capacitor CA to the capacitor 100, the wiring BIL to the wiring 1003, the wiring WOL to the wiring 1004, the wiring BGL to the wiring 1006, and the wiring CAL to the wiring 1005. Note that the transistor 300 illustrated in FIG. 18 corresponds to the transistor provided in the peripheral circuit 1411 of the memory device 1400 illustrated in FIG. 24B.

Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, like the memory cell 1472 illustrated in FIG. 25B. Further, for example, the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M1 having no back gate, like a memory cell 1473 shown in FIG. 25C.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, leakage current of the transistor M1 can be significantly reduced. In other words, since written data can be held for a long time by the transistor M1, the frequency of refreshing the memory cell can be reduced. Also, the refresh operation of the memory cells can be made unnecessary. In addition, since leakage current is very low, multilevel data or analog data can be held in the memory cells 1471, 1472, and 1473. FIG.

Further, in the DOSRAM, if the sense amplifier is provided under the memory cell array 1470 as described above, the bit line can be shortened. As a result, the bit line capacity is reduced, and the storage capacity of the memory cell can be reduced.

[NOSRAM]
25D to 25G show a circuit configuration example of a gain cell type memory cell with two transistors and one capacitor. A memory cell 1474 illustrated in FIG. 25D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and the like, a memory device including a gain cell memory cell using an OS transistor as the transistor M2 is sometimes called a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

The transistor M2 has a first terminal connected to the first terminal of the capacitor CB, a second terminal connected to the wiring WBL, a gate connected to the wiring WOL, and a back gate of the transistor M2. are connected to the wiring BGL. A second terminal of the capacitive element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitor CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. A low-level potential is preferably applied to the wiring CAL when data is written, during data retention, and when data is read. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

Here, a memory cell 1474 illustrated in FIG. 25D corresponds to the memory device illustrated in FIG. That is, the transistor M2 is connected to the transistor 200, the capacitor CB is connected to the capacitor 100, the transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 2003, the wiring WOL is connected to the wiring 2004, the wiring BGL is connected to the wiring 2006, and the wiring CAL is connected to the wiring. 2005 , the wiring RBL corresponds to the wiring 2002 , and the wiring SL corresponds to the wiring 2001 .

Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, like the memory cell 1475 illustrated in FIG. Further, for example, the memory cell MC may be a memory cell including a single-gate transistor, that is, a transistor M2 having no back gate, like the memory cell 1476 shown in FIG. Further, for example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL, like the memory cell 1477 illustrated in FIG.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be very low. Accordingly, written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Also, the refresh operation of the memory cells can be made unnecessary. In addition, since the leakage current is very low, the memory cell 1474 can hold multilevel data or analog data. The same applies to memory cells 1475 to 1477 .

Note that the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter also referred to as a Si transistor). The conductivity type of the Si transistor may be n-channel type or p-channel type. A Si transistor may have higher field effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor. Further, by using a Si transistor for the transistor M3, the transistor M2 can be stacked on the transistor M3, so that the area occupied by the memory cell can be reduced and the integration of the memory device can be increased.

Alternatively, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the circuit of the memory cell array 1470 can be formed using only n-channel transistors.

FIG. 25H shows an example of a gain cell type memory cell with three transistors and one capacitor. A memory cell 1478 illustrated in FIG. 25H includes transistors M4 to M6 and a capacitor CC. Capacitive element CC is provided as appropriate. A memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL. A wiring GNDL is a wiring for applying a low-level potential. Note that the memory cell 1478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. Note that the back gate and gate of the transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a backgate.

Note that the transistor M5 and the transistor M6 may each be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-channel transistors.

When the semiconductor device described in any of the above embodiments is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very low.

Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like described in this embodiment are not limited to those described above. Arrangements or functions of these circuits and wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.

The structure described in this embodiment can be used in combination with any of the structures described in other embodiments or the like as appropriate.

(Embodiment 5)
In this embodiment mode, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is shown with reference to FIG. A plurality of circuits (systems) are mounted on the chip 1200 . Such a technique of integrating a plurality of circuits (systems) on one chip is sometimes called System on Chip (SoC).

As shown in FIG. 26A, a chip 1200 includes a CPU 1211, a GPU 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like. have

The chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. 26(B). A plurality of bumps 1202 are provided on the back side of the first surface of the PCB 1201 and connected to the motherboard 1203 .

The mother board 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222 . For example, the DOSRAM shown in the previous embodiment can be used for the DRAM 1221 . Further, for example, the NOSRAM described in the above embodiment can be used for the flash memory 1222 .

The CPU 1211 preferably has multiple CPU cores. Also, the GPU 1212 preferably has multiple GPU cores. Also, the CPU 1211 and GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200 . The above-mentioned NOSRAM or DOSRAM can be used for the memory. Also, the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and sum-of-products operations. By providing the image processing circuit using the oxide semiconductor of the present invention and the product-sum operation circuit in the GPU 1212, image processing and product-sum operation can be performed with low power consumption.

In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened. And, after the calculation by the GPU 1212, transfer of the calculation result from the GPU 1212 to the CPU 1211 can be performed at high speed.

The analog computation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. Further, the analog calculation unit 1213 may be provided with the sum-of-products calculation circuit.

Memory controller 1214 has a circuit that functions as a controller for DRAM 1221 and a circuit that functions as an interface for flash memory 1222 .

The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used as such an interface.

The network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have circuitry for network security.

The circuit (system) can be formed in the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing processes, and the chip 1200 can be manufactured at low cost.

A PCB 1201 provided with a chip 1200 having a GPU 1212 , a motherboard 1203 provided with a DRAM 1221 and a flash memory 1222 can be referred to as a GPU module 1204 .

Since the GPU module 1204 has the chip 1200 using SoC technology, its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. In addition, a product-sum operation circuit using the GPU 1212 enables a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), a deep belief network ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

The structure described in this embodiment can be used in combination with any of the structures described in other embodiments or the like as appropriate.

(Embodiment 6)
In this embodiment, an application example of a memory device using the semiconductor device described in any of the above embodiments will be described. The semiconductor devices described in the above embodiments are, for example, storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/reproducing devices, navigation systems, etc.). can be applied to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor devices described in the above embodiments are applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). FIG. 27 schematically shows some configuration examples of the removable storage device. For example, the semiconductor devices described in the previous embodiments are processed into packaged memory chips and used for various storage devices and removable memories.

FIG. 27A is a schematic diagram of a USB memory. USB memory 1100 has housing 1101 , cap 1102 , USB connector 1103 and substrate 1104 . A substrate 1104 is housed in a housing 1101 . For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104 . The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1105 of the substrate 1104 or the like.

FIG. 27B is a schematic diagram of the appearance of the SD card, and FIG. 27C is a schematic diagram of the internal structure of the SD card. SD card 1110 has housing 1111 , connector 1112 and substrate 1113 . A substrate 1113 is housed in a housing 1111 . For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113 . By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip having a wireless communication function may be provided on the substrate 1113 . As a result, data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110 . The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1114 of the substrate 1113 or the like.

FIG. 27D is a schematic diagram of the appearance of the SSD, and FIG. 27E is a schematic diagram of the internal structure of the SSD. SSD 1150 has housing 1151 , connector 1152 and substrate 1153 . A substrate 1153 is housed in a housing 1151 . For example, substrate 1153 has memory chip 1154 , memory chip 1155 and controller chip 1156 attached thereto. A memory chip 1155 is a work memory for the controller chip 1156, and may be a DOSRAM chip, for example. By providing a memory chip 1154 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in any of the above embodiments can be incorporated in the memory chip 1154 of the substrate 1153 or the like.

This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

(Embodiment 7)
A semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. FIG. 28 shows a specific example of an electronic device including a processor such as a CPU or GPU or a chip according to one embodiment of the present invention.

<Electronic Devices/Systems>
A GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include relatively large screens such as televisions, monitors for desktop or notebook information terminals, digital signage (digital signage), large game machines such as pachinko machines, etc. , digital cameras, digital video cameras, digital photo frames, electronic book readers, mobile phones, portable game machines, personal digital assistants, sound reproducing devices, and the like. Further, by providing an electronic device with a GPU or a chip according to one embodiment of the present invention, the electronic device can be equipped with artificial intelligence.

An electronic device of one embodiment of the present invention may have an antenna. An image, information, or the like can be displayed on the display portion by receiving a signal with the antenna. Moreover, when an electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared).

An electronic device of one embodiment of the present invention can have various functions. For example, functions to display various information (still images, moving images, text images, etc.) on the display, touch panel functions, functions to display calendars, dates or times, functions to execute various software (programs), wireless communication function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 28 shows an example of an electronic device.

[Information terminal]
FIG. 28A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As an input interface, the display unit 5102 is provided with a touch panel, and the housing 5101 is provided with buttons.

By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute an application using artificial intelligence. Applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5102. An application displayed on the display portion 5102, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.

FIG. 28(B) shows a notebook information terminal 5200 . The notebook information terminal 5200 has an information terminal main body 5201 , a display section 5202 , and a keyboard 5203 .

As with the information terminal 5100 described above, the notebook information terminal 5200 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Also, by using the notebook information terminal 5200, it is possible to develop new artificial intelligence.

In the above description, a smartphone and a notebook information terminal are shown as examples of electronic devices in FIGS. 28A and 28B, respectively. be able to. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[game machine]
FIG. 28C shows a portable game machine 5300 as an example of a game machine. A portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. Housing 5302 and housing 5303 can be removed from housing 5301 . By attaching the connection portion 5305 provided in the housing 5301 to another housing (not shown), the video output to the display portion 5304 can be output to another video device (not shown). can. At this time, the housing 5302 and the housing 5303 can each function as an operation unit. This allows multiple players to play the game at the same time. The chips described in the above embodiments can be incorporated into the chips or the like provided in the substrates of the housings 5301, 5302, and 5303. FIG.

FIG. 28D shows a stationary game machine 5400 as an example of the game machine. A controller 5402 is wirelessly or wiredly connected to the stationary game machine 5400 .

By applying the GPU or chip of one embodiment of the present invention to a game machine such as the portable game machine 5300 or the stationary game machine 5400, a low power consumption game machine can be realized. In addition, the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.

Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game machine 5300, the portable game machine 5300 having artificial intelligence can be realized.

Originally, the progress of the game, the speech and behavior of creatures appearing in the game, and the expressions that occur in the game are determined by the program of the game. , which enables expressions not limited to game programs. For example, it is possible to express changes in the content of questions asked by the player, the progress of the game, the time, and the speech and behavior of characters appearing in the game.

In addition, when a game requiring a plurality of players is played on the portable game machine 5300, the game players can be anthropomorphically configured by artificial intelligence. can play games.

FIGS. 28C and 28D illustrate a portable game machine and a stationary game machine as examples of game machines, and these are game machines to which the GPU or chip of one embodiment of the present invention is applied. is not limited to Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in amusement facilities (game arcades, amusement parks, etc.), pitching machines for batting practice installed in sports facilities, and the like. is mentioned.

[Large computer]
A GPU or chip of one aspect of the present invention can be applied to large-scale computers.

FIG. 28E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 28F is a diagram showing a rack-mounted computer 5502 that the supercomputer 5500 has.

A supercomputer 5500 has a rack 5501 and a plurality of rack-mount computers 5502 . A plurality of computers 5502 are stored in the rack 5501 . Further, the computer 5502 is provided with a plurality of substrates 5504, and the GPUs or chips described in the above embodiments can be mounted over the substrates.

The supercomputer 5500 is a large computer mainly used for scientific and technical calculations. Scientific and technical calculations require high-speed processing of enormous amounts of computation, resulting in high power consumption and high chip heat generation. By applying the GPU or chip of one embodiment of the present invention to the supercomputer 5500, a low power consumption supercomputer can be realized. In addition, the low power consumption can reduce the heat generated from the circuit, thereby reducing the influence of the heat on the circuit itself, the peripheral circuits, and the module.

Although FIGS. 28E and 28F illustrate a supercomputer as an example of a large computer, the large computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Large computers to which the GPU or chip of one aspect of the present invention is applied include, for example, computers that provide services (servers), large general-purpose computers (mainframes), and the like.

[Moving body]
A GPU or chip of one embodiment of the present invention can be applied to automobiles, which are mobile objects, and to the vicinity of the driver's seat of automobiles.

FIG. 28G is a diagram showing the vicinity of the windshield in the interior of an automobile, which is an example of a moving object. FIG. 28G illustrates a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, and a display panel 5704 attached to a pillar.

Display panels 5701 through 5703 can provide a variety of other information such as speedometer, tachometer, mileage, fuel level, gear status, air conditioner settings, and the like. In addition, the display items and layout displayed on the display panel can be appropriately changed according to the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

The display panel 5704 can complement the field of view (blind spot) blocked by the pillars by displaying an image from an imaging device (not shown) provided in the automobile. That is, by displaying an image from an imaging device provided outside the automobile, blind spots can be compensated for and safety can be enhanced. In addition, by projecting an image that supplements the invisible part, safety confirmation can be performed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

Since the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, the chip can be used in an automatic driving system for automobiles, for example. In addition, the chip can be used in a system for road guidance, danger prediction, and the like. The display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.

In addition, in the above description, an automobile is described as an example of a mobile object, but the mobile object is not limited to an automobile. For example, moving objects include trains, monorails, ships, flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, rockets), and the like, and the chip of one embodiment of the present invention can be applied to these moving objects. It is possible to give a system using artificial intelligence.

[electric appliances]
FIG. 28H shows an electric refrigerator-freezer 5800, which is an example of an electrical appliance. The electric freezer-refrigerator 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, and the like.

By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric freezer-refrigerator 5800 has a function of automatically generating a menu based on the ingredients stored in the electric freezer-refrigerator 5800 and the expiration date of the ingredients, etc. It can have a function of automatically adjusting the temperature according to the ingredients.

Electric refrigerators and freezers have been described as an example of electrical appliances, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners. Examples include washing machines, dryers, and audiovisual equipment.

The electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, the effects thereof, and the like described in this embodiment can be appropriately combined with the description of other electronic devices.

This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

10 Substrate 12 Insulator 14 Insulator 20 Region 22 Insulator 24 Insulator 30 Region 32 Insulator 34 Insulator 200 Transistor 205 Conductor 212 Insulator 214 Insulator 216 Insulation body, 220 insulator, 221 insulator, 222 insulator, 223 insulator, 224 insulator, 225 insulator, 230 oxide, 230a oxide, 230A oxide film, 230b oxide, 230B oxide film, 230c oxide, 230C Oxide film 240 Conductor 240a Conductor 240A Conductive film 240b Conductor 240B Conductive layer 250 Insulator 250A Insulating film 252 Insulator 252A Insulating film 260 Conductor 260a Conductor 260A Conductive Film 260b Conductor 260B Conductive film 274 Insulator 274A Insulating film 275 Insulator 280 Insulator 280A Insulating film 282 Insulator 283 Insulator 284 Insulator

Claims (5)

a first conductive layer;
a first insulator on the first conductive layer;
an oxide semiconductor layer on the first insulator;
a second insulator on the oxide semiconductor layer;
a second conductive layer on the second insulator;
a third insulator on the second conductive layer;
The oxide semiconductor layer has a channel formation region of a transistor,
the first conductive layer has a region functioning as a first gate electrode of the transistor;
the second conductive layer has a region functioning as a second gate electrode of the transistor;
the first insulator has a first layer, a second layer and a third layer;
the first layer has a region in contact with the top surface of the first conductive layer;
the third layer has a region in contact with the bottom surface of the oxide semiconductor layer,
the second insulator has a fourth layer, a fifth layer, and a sixth layer;
the sixth layer has a region in contact with the bottom surface of the second conductive layer and a region in contact with the side surface of the second conductive layer;
The fifth layer has a region in contact with the bottom surface of the sixth layer,
The fourth layer has a region in contact with the bottom surface of the fifth layer,
The third insulator has a region in contact with the upper surface of the second conductive layer, a region in contact with the fourth layer, a region in contact with the fifth layer, and a region in contact with the sixth layer. , and
the first layer comprises silicon;
the second layer comprises gallium;
the third layer comprises silicon;
the fourth layer comprises silicon;
the fifth layer comprises gallium;
The semiconductor device, wherein the sixth layer contains silicon. a first insulator;
an oxide semiconductor layer on the first insulator;
a second insulator on the oxide semiconductor layer;
a second conductive layer on the second insulator;
a third insulator on the second conductive layer;
The oxide semiconductor layer has a channel formation region of a transistor,
the second conductive layer has a region functioning as a second gate electrode of the transistor;
the second insulator has a fourth layer, a fifth layer, and a sixth layer;
the sixth layer has a region in contact with the bottom surface of the second conductive layer and a region in contact with the side surface of the second conductive layer;
The fifth layer has a region in contact with the bottom surface of the sixth layer,
The fourth layer has a region in contact with the bottom surface of the fifth layer,
The third insulator has a region in contact with the upper surface of the second conductive layer, a region in contact with the fourth layer, a region in contact with the fifth layer, and a region in contact with the sixth layer. , and
the fourth layer comprises silicon;
the fifth layer comprises gallium;
The semiconductor device, wherein the sixth layer contains silicon. In claim 2,
the first insulator has a first layer, a second layer and a third layer;
the first layer comprises silicon;
the second layer comprises gallium;
The semiconductor device, wherein the third layer contains silicon. In any one of claims 1 to 3,
having a capacitive element,
The semiconductor device, wherein the capacitive element is formed above the third insulator. In claim 1,
having a capacitive element,
the capacitive element is formed below the first conductive layer;
semiconductor equipment.

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