JP7372388B2 - Semiconductor device and its manufacturing method - Google Patents

Description

One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and storage devices are examples of semiconductor devices. Display devices (liquid crystal display devices, light emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic equipment, etc. may be said to have semiconductor devices. .

Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the present invention relates to a process, machine, manufacture, or composition of matter.

Although silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials. As oxide semiconductors, not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals are known. Among multi-element metal oxides, research on In--Ga--Zn oxide (hereinafter also referred to as IGZO) has been actively conducted.

Research on IGZO has revealed that C is neither single crystal nor amorphous in oxide semiconductors.
AAC (c-axis aligned crystalline) structure and nc (n
anocrystalline) structure was found (see Non-Patent Documents 1 to 3). Non-Patent Document 1 and Non-Patent Document 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Furthermore, Non-Patent Document 4 and Non-Patent Document 5 show that even oxide semiconductors with lower crystallinity than the CAAC structure and the nc structure have minute crystals.

Furthermore, transistors using IGZO as an active layer have an extremely low off-state current (see Non-Patent Document 6), and LSIs and displays that utilize this property have been reported (
See Non-Patent Document 7 and Non-Patent Document 8. ).

S. Yamazaki et al. , “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , “The Proceedings of AM-FPD’13 Digest of Technical Papers”, 2013, p. 151-154 S. Yamazaki et al. , “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217 S. Amano et al. , “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p. 626-629

An object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current.
Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with good reliability. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

An object of one embodiment of the present invention is to provide a semiconductor device that can retain data for a long period of time. An object of one embodiment of the present invention is to provide a semiconductor device that can write information at a high speed. An object of one embodiment of the present invention is to provide a semiconductor device with a high degree of freedom in design. An object of one embodiment of the present invention is to provide a semiconductor device that can suppress power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

Note that the description of these issues does not preclude the existence of other issues. Note that one embodiment of the present invention does not need to solve all of these problems. In addition, problems other than these will become obvious from the description, drawings, claims, etc.
It is possible to extract problems other than these from the drawings, claims, etc.

One embodiment of the present invention includes a first oxide, a second oxide on the first oxide, a first oxide,
and a third oxide that covers the second oxide; a first insulator that covers the third oxide; and a first to third oxide that is disposed on the first insulator; The conductor, the second insulator in contact with the top surface of the first insulator and the side surface of the conductor, and the third insulator in contact with the top surface of the second insulator and the side surface of the conductor, which overlap with each other. , the upper surface of the conductor, and the fourth insulator that is in contact with the upper surface of the third insulator.
an insulator, and the second oxide has a first region, a second region, a third region located between the first region and the second region, and a third region located between the first region and the third region. a fourth region located between the regions;
has a fifth region located between the region and the third region, the resistance of the first region and the second region is lower than the resistance of the third region, The resistance of the region No. 5 is lower than the resistance of the third region and higher than the resistance of the first region and the second region.
The semiconductor device is provided above the third region, the fourth region, and the fifth region so as to overlap with the region, the fourth region, and the fifth region.

In the above, the conductor overlaps at least a portion of the first region and the second region,
It is preferable. Further, in the above, a fifth insulator is further provided between the first insulator and the second insulator.
The fifth insulator is preferably in contact with the side surface of the conductor.

In the above, it is preferable that the first region, the second region, the fourth region, and the fifth region contain one of phosphorus and boron. In addition, in the above, the first region and the second region
Preferably, the region contains more phosphorus or boron than the fourth region and the fifth region. Further, it is preferable that the first region, the second region, the fourth region, and the fifth region have more oxygen vacancies than the third region. Further, it is preferable that the first region, the second region, the fourth region, and the fifth region contain more hydrogen than the third region.

Further, in another embodiment of the present invention, a first oxide and a second oxide are formed on the first oxide, and a second oxide is formed to cover the first oxide and the second oxide. A first insulating film is formed covering the third oxide, and a second oxide is superimposed on the first insulating film to form a first dummy gate. a first dopant is added to the second oxide using the first dummy gate as a mask, a portion of the first dummy gate is removed to form a second dummy gate, and a second dummy gate is formed. A part of the oxide is exposed from the second dummy gate, a second dopant is added to the second oxide using the second dummy gate as a mask, and the first insulating film and the second dopant are added to the second oxide. forming a second insulating film to cover the dummy gate; forming a third insulating film on the second insulating film;
removing part of the second insulating film and the third insulating film until the upper part of the second dummy gate is exposed; removing part of the second dummy gate and the second insulating film; This is a method for manufacturing a semiconductor device in which an opening is formed, a conductive film is deposited to fill the opening, and a portion of the conductive film is removed until the top of a third insulating film is exposed.

Further, in the above, it is preferable to use phosphorus or boron as the first dopant and the second dopant. Furthermore, in the above, the amount of the first dopant added is:
The amount of the second dopant added is preferably larger than that of the second dopant. In addition, in the above, the first
It is preferable that an ion implantation method or an ion doping method be used for the addition of the dopant and the addition of the second dopant. Further, in the above, the first dummy gate preferably contains carbon. Further, in the above, the formation of the second dummy gate is preferably performed by an ashing process using oxygen radicals.

According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided.
Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

Alternatively, a semiconductor device that can retain data for a long period of time can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with a high degree of freedom in design can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. Alternatively, a new semiconductor device can be provided.

Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become obvious from the description, drawings, claims, etc., and effects other than these can be extracted from the description, drawings, claims, etc. It is.

1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 1 is a cross-sectional view showing the configuration of a storage device according to one embodiment of the present invention. FIG. 1 is a cross-sectional view showing the configuration of a storage device according to one embodiment of the present invention. FIG. 1 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 1 is a circuit diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 1 is a schematic diagram of a semiconductor device according to one embodiment of the present invention. FIG. 1 is a schematic diagram of a storage device according to one embodiment of the present invention. 1 is a diagram illustrating an electronic device according to one embodiment of the present invention.

Hereinafter, embodiments will be described with reference to the drawings. However, those skilled in the art will readily understand that the embodiments can be implemented in many different ways and that the form and details thereof can be changed in various ways without departing from the spirit and scope thereof. Ru. Therefore, the present invention should not be construed as being limited to the contents described in the following embodiments.

Additionally, in the drawings, the size, layer thickness, or region may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. for example,
In actual manufacturing processes, layers, resist masks, etc. may be unintentionally reduced due to treatments such as etching, but they are sometimes omitted for ease of understanding. Also,
In the drawings, the same reference numerals are used for the same parts or parts having similar functions in different drawings, and repeated description thereof may be omitted. Furthermore, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

Further, in order to facilitate understanding of the invention, particularly in top views (also referred to as "plan views") and perspective views, descriptions of some components may be omitted. In addition, some hidden lines may be omitted.

Further, in this specification and the like, ordinal numbers such as 1st, 2nd, etc. are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, "first" can be replaced with "second".
It can be explained by replacing it with "no" or "third" as appropriate. Furthermore, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one aspect of the present invention.

Furthermore, in this specification and the like, words indicating placement such as "above" and "below" are used for convenience in order to explain the positional relationship between structures with reference to the drawings. Further, the positional relationship between the structures changes as appropriate depending on the direction in which each structure is depicted. Therefore, the words and phrases are not limited to those explained in the specification, and can be appropriately rephrased depending on the situation.

For example, in this specification, etc., when X and Y are directly connected, and when it is explicitly stated that X and Y are connected, A case where X and Y are functionally connected and a case where X and Y are functionally connected are disclosed in this specification and the like. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in the diagrams or text, and connection relationships other than those shown in the diagrams or text are also described in the diagrams or text.

Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films,
layer, etc.).

Furthermore, the functions of the source and drain may be interchanged when transistors with different polarities are used, or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain may be used interchangeably.

Note that in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as "effective channel width") and the channel width shown in the top view of the transistor (Hereinafter, also referred to as "apparent channel width."
) and may be different. For example, when a gate electrode covers the side surface of a semiconductor, the effective channel width becomes larger than the apparent channel width, and the effect thereof may become impossible to ignore. For example, in a transistor whose gate electrode is minute and covers the side surface of the semiconductor, a large proportion of the channel formation region is formed on the side surface of the semiconductor. In that case, the effective channel width becomes larger than the apparent channel width.

In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, in order to estimate the effective channel width from design values, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

In this specification, when simply described as channel width, it may refer to the apparent channel width. Alternatively, in this specification, when simply described as channel width, it may refer to effective channel width. Note that the values of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

Note that the term "impurity of a semiconductor" refers to, for example, something other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic % can be considered an impurity. For example, due to the inclusion of impurities,
In some cases, the DOS (Density of States) of the semiconductor increases or the crystallinity decreases. When the semiconductor is an oxide semiconductor, examples of impurities that change the properties of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxide semiconductors. There are transition metals other than the main components, for example,
These include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of oxide semiconductors, water may also function as an impurity. Further, in the case of an oxide semiconductor, oxygen vacancies may be formed due to, for example, mixing of impurities. Further, when the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include oxygen, group 1 elements other than hydrogen, group 2 elements, group 13 elements, group 15 elements, and the like.

Note that in this specification and the like, silicon oxynitride has a composition that contains more oxygen than nitrogen. Furthermore, silicon nitride oxide has a composition containing more nitrogen than oxygen.

Further, in this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer. Further, the term "conductor" can be translated as a conductive film or a conductive layer. Further, the term "semiconductor" can be translated as a semiconductor film or a semiconductor layer.

Furthermore, in this specification and the like, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, cases where the temperature is -5 degrees or more and 5 degrees or less are also included. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Moreover, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is greater than or equal to 85 degrees and less than or equal to 95 degrees are also included. Moreover, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

Note that in this specification, a barrier film is a film that has the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, and when the barrier film has conductivity, it is referred to as a conductive barrier film. I may call you.

In this specification and the like, metal oxide refers to a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes called an oxide semiconductor. In other words, OS FET or OS
When described as a transistor, it can be referred to as a transistor including an oxide or an oxide semiconductor.

In addition, in this specification, etc., normally-off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the current per 1 μm of channel width flowing through the transistor is 1×10 ^-20 at room temperature. Below A means below 1×10 ⁻¹⁸ A at 85°C, or below 1×10 ⁻¹⁶ A at 125°C.

(Embodiment 1)
An example of a specific structure of a semiconductor device including a transistor 200 according to one embodiment of the present invention will be described below with reference to FIGS. 1 to 19.

<Example of configuration of semiconductor device>
1(A), FIG. 1(B), FIG. 1(C), and FIG. 1(D) are a top view and a cross-sectional view of a transistor 200 and the vicinity of the transistor 200 according to one embodiment of the present invention.

FIG. 1A is a top view of a semiconductor device including a transistor 200. In addition, Figure 1 (
B) and FIG. 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Further, FIG. 1(D) is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 1(A). Note that in the top view of FIG. 1A, some elements are omitted for clarity of illustration. Further, FIG. 2 is an enlarged view of the oxide 230b and its vicinity in FIG. 1(B).

[Transistor 200]
As shown in FIG. 1, the transistor 200 includes an oxide 230a disposed on a substrate (not shown), an oxide 230b disposed on the oxide 230a, an oxide 230a,
and an oxide 230c covering the oxide 230b, and an insulator 250 covering the oxide 230c.
, a layer 253a formed at a distance from each other in the oxide 230b and the oxide 230c, and a layer 252 formed at a distance from each other between the layer 253a and the layer 253b.
a, and a layer 252b, which is disposed on the insulator 250 and includes oxides 230a to 230.
The layer 253a overlaps with the conductor 260, the insulator 266 in contact with the top surface of the insulator 250, and the side surface of the conductor 260, and the layer 253a in contact with the top surface of the insulator 266 and the side surface of the conductor 260.
and an insulator 280 in which an opening 263 is formed in an overlapping manner between the layer 253b and the layer 253b. Here, as shown in FIGS. 1B and 1C, the upper surface of the conductor 260 preferably substantially coincides with the upper surface of the insulator 280.

Note that in the following, the oxide 230a, the oxide 230b, and the oxide 230c may be collectively referred to as the oxide 230. In addition, the layer 252a and the layer 252b may be combined into a layer 2.
52 in some cases. Further, the layer 253a and the layer 253b may be collectively referred to as a layer 253.

Note that in the transistor 200, the oxide 230a, the oxide 230b, and the oxide 2 are formed in a region where a channel is formed (hereinafter also referred to as a channel formation region) and in the vicinity thereof.
Although a configuration in which three layers of 30c are laminated is shown, the present invention is not limited to this. For example, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be used. In addition, the oxide 230a, the oxide 230b, and the oxide 230
Each of c may have a laminated structure of two or more layers. Further, in the transistor 200, the conductor 260 is shown as having a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single layer structure or a laminated structure of three or more layers.

For example, when the oxide 230c has a stacked structure consisting of a first oxide and a second oxide on the first oxide, the first oxide has the same composition as the oxide 230b. , the second oxide preferably has the same composition as the oxide 230a.

Here, the conductor 260 functions as a gate electrode of the transistor, and the layer 252a and the layer 253a, and the layer 252b and the layer 253b each function as a source region or a drain region. As described above, the conductor 260 is formed to be embedded in the insulator 280, the opening 263 of the insulator 266, and the region sandwiched between the layers 253a and 253b. Here, the arrangement of conductor 260, layer 252a, layer 252b, layer 253a, and layer 253b is selected in a self-aligned manner with respect to opening 263. That is, in the transistor 200, the gate electrode can be disposed between the source electrode and the drain electrode in a self-aligned manner. Therefore, since the conductor 260 can be formed without providing a margin for alignment, the area occupied by the transistor 200 can be reduced. This results in
It is possible to achieve miniaturization and high integration of semiconductor devices.

Further, as shown in FIG. 1, the conductor 260 is a conductor 26 provided inside the opening 263.
It is preferable to have a conductor 0a and a conductor 260b embedded inside the conductor 260a.

The transistor 200 also includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, and a conductor disposed so as to be embedded in the insulator 216. 205, an insulator 222 disposed on the insulator 216 and the conductor 205, and an insulator 224 disposed on the insulator 222. Insulator 22
Preferably, an oxide 230a is disposed on top of 4.

Further, it is preferable that an insulator 274 and an insulator 281 functioning as an interlayer film be provided over the transistor 200. Here, the insulator 274 is preferably disposed in contact with the upper surfaces of the conductor 260 and the insulator 280.

The insulator 222, the insulator 266, and the insulator 274 preferably have a function of suppressing diffusion of hydrogen (eg, hydrogen atoms, hydrogen molecules, etc.). For example, insulator 222, insulator 266, and insulator 274 preferably have lower hydrogen permeability than insulator 224, insulator 250, and insulator 280. Further, the insulator 222, the insulator 266, and the insulator 274 preferably have a function of suppressing diffusion of oxygen (eg, oxygen atoms, oxygen molecules, etc.). For example, insulator 222, insulator 266, and insulator 274 are
4. It is preferable that the oxygen permeability is lower than that of the insulator 250 and the insulator 280.

Here, insulator 224, oxide 230a, oxide 230b, and insulator 250 are changed from insulator 280 and insulator 281 to insulator 266, oxide 230c, and insulator 27.
separated by 4. Therefore, impurities such as hydrogen contained in the insulator 280 and the insulator 281 and excessive oxygen can be suppressed from entering the insulator 224, the oxide 230a, the oxide 230b, and the insulator 250. .

Further, as shown in FIGS. 1B and 1D, a conductor 240 (a conductor 240a and a conductor 240b) that is electrically connected to the transistor 200 and functions as a plug is preferably provided. Note that an insulator 241 (
An insulator 241a and an insulator 241b) are provided. That is, the insulator 241 is provided in contact with the inner walls of the openings of the insulator 266, the insulator 280, the insulator 274, and the insulator 281. Alternatively, a first conductor of the conductor 240 may be provided in contact with the side surface of the insulator 241, and a second conductor of the conductor 240 may be further provided inside. Here, conductor 2
The height of the top surface of the insulator 40 and the height of the top surface of the insulator 281 can be made to be approximately the same. Note that although the transistor 200 shows a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 24
0 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned to the order of formation to distinguish them.

The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region.
, the oxide 230b, and the oxide 230c), a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used. For example, the metal oxide that becomes the channel forming region of the oxide 230 has a band gap of 2 eV or more, preferably 2 eV or more.
．． It is preferable to use a voltage of 5 eV or more. In this way, by using a metal oxide with a large band gap, leakage current (off current) in a non-conducting state of a transistor can be extremely reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

For example, as the oxide 230, In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , neodymium, hafnium, tantalum, tungsten, or one or more selected from magnesium, etc.). In particular, the element M is preferably aluminum, gallium, yttrium, or tin. Further, as the oxide 230, indium oxide, zinc oxide, In--Ga oxide, In--Zn oxide, Ga--Zn oxide, or gallium oxide may be used.

Here, by adding an element that forms oxygen vacancies or an element that combines with oxygen vacancies to the oxide 230, the carrier density may increase and the resistance may be lowered. Typical examples of such elements include boron and phosphorus. Further, in addition to boron and phosphorus, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, etc. can be used. Further, typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. In addition, the oxide 230 includes aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, and strontium. One or more metal elements selected from metal elements such as , lanthanum, etc. may be added. Among the above-mentioned elements, boron and phosphorus are preferable as the elements to be added. Equipment on an amorphous silicon or low-temperature polysilicon production line can be used to add boron and phosphorus, so capital investment can be suppressed. The concentration of the above elements can be measured using secondary ion mass spectrometry (SIMS).
The measurement may be performed using, for example, spectrometry.

In particular, as the element added to the oxide 230, it is preferable to use an element that easily forms an oxide. Such elements typically include boron, phosphorus, aluminum, magnesium, and the like. The element added to the oxide 230 can take away oxygen from the oxide 230 to form an oxide. As a result, many oxygen vacancies occur in the oxide 230. The combination of the oxygen vacancies and hydrogen in the oxide 230 generates carriers, resulting in an extremely low resistance region. Furthermore, the element added to the oxide 230 is in a stable oxide state.
Since it exists in the oxide 230, it is difficult to desorb from the oxide 230 even if a process requiring high temperature is performed in a subsequent process. That is, by using an element that easily forms an oxide as an element added to the oxide 230, a region that is difficult to increase the resistance even through a high-temperature process can be formed in the oxide 230.

The layer 252 is a layer formed by adding the above elements to the oxide 230. Figure 1(B)
As shown in FIG. 2, the layer 252a and the layer 252b are formed to face each other with the conductor 260 in between, and preferably have their upper surfaces in contact with the insulator 250. In top view, layer 2
Preferably, at least a portion of layer 52a and layer 252b overlap conductor 260. Here, it is preferable that the concentration of the above element in the layer 252 is higher than that in a portion of the oxide 230 where the layer 252 and the layer 253 are not formed. Further, the amount of oxygen vacancies contained in the layer 252 is preferably higher than the amount of oxygen vacancies in the portion of the oxide 230 where the layer 252 and the layer 253 are not formed. As a result, the layer 252 has a higher carrier density and lower resistance than a portion of the oxide 230 where the layers 252 and 253 are not formed.

The layer 253 is a layer formed by adding the above elements to the oxide 230, and is formed by adding more of the above elements than the layer 252. As shown in FIG. 1(B) and FIG.
Layer 253a and layer 253b are formed to face each other with conductor 260 and layer 252 in between, and preferably have upper surfaces in contact with insulator 250. In a top view, the side surfaces of the layers 253a and 253b on the conductor 260 side coincide with the side surfaces of the conductor 260, or
53a and a portion of layer 253b preferably overlap with conductor 260. Here, the concentration of the above element in the layer 253 is preferably equal to or higher than the concentration of the above element in the layer 252. Further, the amount of oxygen vacancies contained in the layer 253 is preferably higher than the amount of oxygen vacancies in the portion of the oxide 230 where the layer 252 and the layer 253 are not formed. As a result, the layer 253 has a higher carrier density and lower resistance than a portion of the oxide 230 where the layers 252 and 253 are not formed.

As shown in FIG. 2, in the oxide 230, a region that overlaps with the conductor 260 and is sandwiched between the layers 252a and 252b is defined as a region 234, and a region that overlaps with the layer 253 is defined as a region 231 (region 231a and region 231b). The area that overlaps with the layer 252 is defined as the area 232 (area 2
32a, and region 232b). As shown in FIG. 2, the area 234 is the area 231a
and region 231b, region 232a is located between region 231a and region 234,
Region 232b is located between region 231b and region 234. Here, the region 231 has a higher carrier density and lower resistance than the region 234. Furthermore, the region 232 has a higher carrier density and lower resistance than the region 234, and has a lower carrier density and higher resistance than the region 231. Alternatively, region 232 may have a carrier density similar to that of region 231 and may have a similar resistance. Therefore, the region 234 functions as a channel formation region of the transistor 200, the region 231 functions as a source or drain region, and the region 232 functions as a junction region.

With the above configuration, the layer 252 that overlaps the conductor 260 functions as a so-called overlap region (also referred to as a LOV region). Therefore, it is possible to prevent an offset region from being formed between the channel formation region of the oxide 230 and the source or drain region, and to suppress the effective channel length from becoming larger than the width of the conductor 260. can. Thereby, the on-state current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved.

By forming the region 231 that functions as a source region or a drain region in the oxide 230, it is possible to connect the conductor 240 that functions as a plug to the region 231 without providing a source electrode and a drain electrode formed of metal. can. If a source electrode and a drain electrode made of metal are provided in contact with the oxide 230, if high-temperature heat treatment is performed in the manufacturing process or post-process of the transistor 200, the source electrode and drain electrode made of metal will be oxidized. However, the on-state current, S value, and frequency characteristics of the transistor 200 may deteriorate. However, in the semiconductor device shown in this embodiment, there is no need to provide a source electrode and a drain electrode made of metal. Therefore, even if high-temperature heat treatment is performed in the manufacturing process or post-process of the transistor 200, a semiconductor device that exhibits good on-current, S value, and frequency characteristics can be provided. For example, in the semiconductor device described in this embodiment, after the transistor 200 is manufactured, the temperature is higher than or equal to 450° C. and lower than or equal to 800° C.
A process that requires high temperatures of 0° C. or more and 750° C. or less can be performed.

Further, as described above, by adding an element that forms oxygen vacancies to the layers 252 and 253,
By performing heat treatment, hydrogen contained in the region 234 functioning as a channel formation region can be captured by oxygen vacancies contained in the layer 253 in some cases. Here, the concentration of hydrogen contained in the layer 253 or the layer 252 is preferably higher than the concentration of hydrogen in a portion of the oxide 230 where the layer 252 and the layer 253 are not formed. Accordingly, stable electrical characteristics can be provided to the transistor 200, and reliability can be improved.

Further, although the details will be described later, the transistor 200 is manufactured using the manufacturing method described in this embodiment.
By forming the conductor 260, the conductor 260 can be disposed between the layer 253a and the layer 253b in a self-aligned manner, and can be overlapped with the layer 252a and the layer 252b. Therefore, semiconductor devices having good electrical characteristics can be manufactured with high yield. Also, the channel length (area 2
34 in the A1-A2 direction, or the distance between the layers 252a and 252b. ) can also be made below the resolution limit of the exposure device. For example, the channel length should be set to 1 nm or more6.
The thickness can also be set to 0 nm or less, more preferably 15 nm or more and 40 nm or less. By shortening the channel length in this manner, the on-current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved.

Further, although details of a method for manufacturing a semiconductor device will be described later, the layers 252 and 253 are preferably formed by adding the above element as a dopant to the oxide 230 via the insulator 250. At this time, the dopant is applied not only to the oxide 230 but also to the insulator 25.
0 may also be added.

The dopant added to regions 231 and 232 of oxide 230
Oxygen vacancies are generated in the oxide 230 in the regions 231 and 232 because of the combination with oxygen therein. Here, hydrogen contained in the region 234 of the oxide 230 diffuses into the regions 231 and 232 and is captured by the oxygen vacancies, so the oxide 230 in the region 234 is
It is thought that the resistance becomes higher compared to the resistance value after film formation. On the other hand, the oxide 230 in the region 231
It is thought that the oxygen vacancies capture the hydrogen, thereby lowering the resistance compared to the resistance value after film formation.

Further, when the insulator 250 overlapping with the region 231 contains oxygen (or excess oxygen as described below), when the oxygen diffuses into the oxide 230, the resistance of the oxide 230 becomes high in the region 231, and the source region and drain region There are concerns that it will not function adequately. but,
By adding the dopant to the insulator 250, oxygen contained in the insulator 250 is captured and fixed by the dopant. Therefore, the release of oxygen from the insulator 250 is suppressed,
In the region 231, the resistance value of the oxide 230 can be maintained lower than the resistance value after film formation.

Due to the above mechanism, in the oxide 230, the region 234 maintains a high resistance value and functions as a channel forming region, and the region 231 maintains a low resistance value and functions as a source region or a drain region. It seems possible. In addition, the dopant added to the oxide 230 does not cause diffusion or the like and is stable even after the heat treatment in the subsequent process, so the regions 234, 232, and 231 are stable even after the heat treatment is performed. , it does not expand or contract and is stable. That is, in the transistor according to the present invention, the risk of causing defects in electrical characteristics and reliability such as increase or decrease in channel length and connection between source and drain regions due to heat treatment is reduced.

Note that in FIG. 2, the layer 252 and the layer 253 are formed near the interface between the oxide 230b and the oxide 230c and the insulator 250 in the thickness direction of the oxide 230b and the oxide 230c. Not limited. For example, layers 252 and 253 are made of oxide 23
It may have approximately the same thickness as the film thickness of 0b, or may be formed on the oxide 230a as well.

Further, in the oxide 230, it may be difficult to clearly detect the boundaries of each region. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected within each region are not limited to gradual changes from region to region, but also vary continuously (also called gradation) within each region. It's okay. In other words, the closer the region is to the channel formation region, the lower the concentration of metal elements and impurity elements such as hydrogen and nitrogen may be.

Note that although FIG. 2 shows a configuration in which the conductor 260 overlaps the region 234 and the region 232 (layer 252), the present embodiment is not limited to this. For example, as shown in FIG.
1 (layer 253). With this configuration, in addition to the layer 252 overlapping with the conductor 260, a part of the layer 253 also functions as an overlapping region. Therefore, formation of an offset region between the channel forming region of the oxide 230 and the source or drain region can be more reliably prevented, and the effective channel length can be adjusted to the length of the conductor 260.
It is possible to prevent the width from becoming larger than the width of the . Thereby, the on-state current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved.

As described above, a semiconductor device including a transistor with a large on-state current can be provided. Alternatively, a semiconductor device including a transistor with high frequency characteristics can be provided. Alternatively, it is possible to provide a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability. Alternatively, a semiconductor device including a transistor with low off-state current can be provided.

A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

The conductor 205 is arranged to overlap the oxide 230 and the conductor 260. Further, it is preferable that the conductor 205 is embedded in the insulator 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, the average surface roughness (Ra) of the upper surface of the conductor 205 may be set to 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Thereby, the flatness of the insulator 224 formed on the conductor 205 can be improved, and the crystallinity of the oxides 230a, 230b, and 230c can be improved.

Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Further, the conductor 205 may function as a second gate (also referred to as a bottom gate) electrode. In that case, Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without interlocking with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be made larger than 0 V, and the off-state current can be reduced. Therefore, it is better to apply a negative potential to the conductor 205 than to apply it to the conductor 260.
The drain current when the potential applied to is 0V can be reduced.

Further, the conductor 205 is preferably provided larger than the channel formation region in the oxide 230. In particular, as shown in FIG. 1C, the conductor 205 preferably extends also in a region outside the end of the oxide 230 that intersects with the channel width direction. That is, on the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap with each other with an insulator interposed therebetween.

With the above structure, the oxide 230 is
can electrically surround the channel forming region of.

Furthermore, as shown in FIG. 1C, the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this, and a configuration may be adopted in which a conductor that functions as a wiring is provided below the conductor 205. Furthermore, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by a plurality of transistors.

Further, the conductor 205 has a first conductor formed in contact with the inner wall of the opening of the insulator 216,
Further inside, a second conductor is formed. Here, the heights of the first conductor and the second conductor of the conductor 205 and the height of the upper surface of the insulator 216 can be made to be approximately the same. Note that although the transistor 200 shows a structure in which the first conductor and the second conductor of the conductor 205 are stacked, the present invention is not limited to this. For example, the conductor 205 may be provided as a single layer or a laminated structure of three or more layers. When the structure has a laminated structure, an ordinal number may be assigned to the order of formation to distinguish them.

Further, as the first conductor of the conductor 205, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom,
A conductor having a function of suppressing the diffusion of impurities such as nitrogen molecules, nitrogen oxide molecules ( _N2O , NO, _NO2, etc.), and copper atoms (the impurities are difficult to pass through) may be used. Or, it has the function of suppressing at least one diffusion of oxygen (e.g., oxygen atoms, oxygen molecules, etc.)
The above oxygen is difficult to permeate. ) It is preferable to use a conductor. In addition, in this specification,
The function of suppressing the diffusion of impurities or oxygen is a function of suppressing the diffusion of any one or all of the impurities or oxygen.

By using a conductor having a function of suppressing oxygen diffusion as the first conductor of the conductor 205, it is possible to prevent the conductor 205 from being oxidized and the conductivity from decreasing.
Examples of conductors that have the function of suppressing oxygen diffusion include tantalum, tantalum nitride,
It is preferable to use ruthenium or ruthenium oxide. Therefore, the conductor 20
The first conductor of No. 5 may be a single layer or a laminated layer of the above-mentioned conductive material.

Further, as the second conductor of the conductor 205, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component.

The insulator 214 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side. Therefore, the insulator 21
4 is hydrogen atom, hydrogen molecule, water molecule, nitrogen atom, nitrogen molecule, nitrogen oxide molecule (N ₂ O, NO
It is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as copper atoms (e.g., NO ₂ ), copper atoms, etc. (the impurities are difficult to pass through). Alternatively, it has a function of suppressing the diffusion of at least one of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (the above-mentioned oxygen is difficult to permeate).
) It is preferable to use an insulating material.

For example, it is preferable to use aluminum oxide, silicon nitride, or the like as the insulator 214. Thereby, impurities such as water or hydrogen can be suppressed from diffusing from the substrate side to the transistor 200 side with respect to the insulator 214. Alternatively, oxygen contained in the insulator 224 and the like can be suppressed from diffusing closer to the substrate than the insulator 214.

Further, it is preferable that the insulator 216, the insulator 280, and the insulator 281 that function as interlayer films have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, insulator 216, insulator 28
0, and as the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide,
Silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like may be used as appropriate.

Further, the insulator 216 may have a laminated structure. For example, an insulator similar to the insulator 214 may be provided in at least a portion of the insulator 216 that is in contact with the side surface of the conductor 205. With such a configuration, oxidation of the conductor 205 due to oxygen contained in the insulator 216 can be suppressed. Alternatively, the conductor 205 may cause the insulator 2
It is possible to suppress absorption of oxygen contained in 16.

The insulator 222 and the insulator 224 function as gate insulators.

Here, it is preferable that the insulator 224 in contact with the oxide 230 desorb oxygen by heating. In this specification, oxygen released by heating may be referred to as excess oxygen. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and reliability of the transistor 200 can be improved.

Specifically, as the insulator 224, it is preferable to use an oxide material from which some oxygen is released by heating. The oxide that desorbs oxygen by heating is TDS (Thermal D
(esorption spectroscopy) analysis, the amount of oxygen desorbed in terms of oxygen atoms is 1.0 x 10 ¹⁸ atoms/cm ³ or more, preferably 1.0 x 10 ¹⁹ at.
oms/cm ³ or more, more preferably 2.0×10 ¹⁹ atoms/cm ³ or 3
．． The oxide film has an oxide density of 0×10 ²⁰ atoms/cm ³ or more. The surface temperature of the film during the above TDS analysis is 100°C or more and 700°C or less, or 100°C or more and 400°C.
The following ranges are preferred.

Further, as shown in FIG. 1C, the thickness of the insulator 224 in a region that does not overlap with the oxide 230b is preferably thinner than the thickness of the other region. Further, the insulator 224 may have an island shape that overlaps the oxide 230b. With such a configuration, the conductor 26
Since the lower end of the oxide 230 can be located further down, the electric field of the conductor 260 functioning as the first gate electrode can be easily applied to the side surface of the oxide 230. Therefore, the on-state current of the transistor 200 can be increased and the frequency characteristics can be improved. Alternatively, the insulator 224 may be provided in an island shape by overlapping the oxide 230b and the oxide 230a.

Like the insulator 214 and the like, the insulator 222 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, insulator 222 preferably has lower hydrogen permeability than insulator 224. Insulator 222, insulator 266, and insulator 274 allow insulator 224, oxide 230,
By surrounding the insulator 250 and the like, impurities such as water or hydrogen can be prevented from entering the transistor 200 from the outside.

Further, it is preferable that the insulator 222 has a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate). For example, insulator 222 preferably has a lower oxygen permeability than insulator 224. It is preferable for the insulator 222 to have a function of suppressing the diffusion of oxygen and impurities, since this can reduce the diffusion of oxygen included in the oxide 230 toward the substrate side. Further, the conductor 205 may be an insulator 224 or
Reaction with oxygen contained in the oxide 230 can be suppressed.

The insulator 222 is preferably an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. When the insulator 222 is formed using such a material, the insulator 222 suppresses the release of oxygen from the oxide 230 and the incorporation of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200. Acts as a layer.

Alternatively, these insulators may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide,
Zirconium oxide may also be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulator.

Further, the insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide,
Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT)
An insulator containing a so-called high-k material such as iO ₃ ) or (Ba,Sr)TiO ₃ (BST) may be used in a single layer or in a stack. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinning of gate insulators. By using a high-k material for the insulator that functions as a gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In that case, the structure is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222.

The oxide 230 includes an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 2
and oxide 230c on top of 30b. By having the oxide 230a below the oxide 230b, diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b can be suppressed. Furthermore, by providing the oxide 230c over the oxide 230b, diffusion of impurities from a structure formed above the oxide 230c to the oxide 230b can be suppressed.

Note that it is preferable that the oxide 230 has a layered structure made of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M among the constituent elements is larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 230b. It is preferable. Further, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. Also,
For the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

It is preferable that the oxide 230a, the oxide 230b, and the oxide 230c have crystallinity, and it is particularly preferable to use CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (oxygen vacancies, etc.), and have a highly crystalline and dense structure. By including such an oxide 230, the transistor 200 becomes stable against high temperatures (so-called thermal budget) during the manufacturing process.

Further, the energy at the lower end of the conduction band of the oxide 230a and the oxide 230c is
It is preferable that the energy be higher than the energy at the lower end of the conduction band of 0b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than that of the oxide 230b. In this case, it is preferable to use a metal oxide that can be used for the oxide 230a as the oxide 230c. Specifically, in the metal oxide used for the oxide 230c, the atomic ratio of the element M among the constituent elements is larger than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 230b. It is preferable. Further, in the metal oxide used for the oxide 230c, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Also,
In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230c.

Here, at the junction of oxide 230a, oxide 230b, and oxide 230c,
The energy level at the bottom of the conduction band changes smoothly. In other words, it can be said that the energy level at the lower end of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c changes continuously or forms a continuous junction. In order to do this, it is preferable to lower the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c.

Specifically, the oxide 230a and the oxide 230b, the oxide 230b and the oxide 230c,
By having a common element other than oxygen (making it the main component), a mixed layer with low defect level density can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a and the oxide 230c are In-Ga-Zn oxide, Ga-Zn oxide,
Gallium oxide or the like may also be used. Further, the oxide 230c may have a layered structure. For example, a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide, or a stacked structure of an In-Ga-Zn oxide and a Ga-Zn oxide on the In-Ga-Zn oxide. A laminated structure with gallium oxide can be used. In other words, In-Ga-Zn oxide and In
A stacked structure with an oxide not containing may be used as the oxide 230c.

Specifically, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio] or 1:1:0.5 [atomic ratio] may be used as the oxide 230a. Further, as the oxide 230b, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or 3:1:2 [atomic ratio] may be used. In addition, as the oxide 230c, In:Ga:Zn=1:3:4
[atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio] Metal oxides may be used. Further, as a specific example when the oxide 230c has a layered structure, In:Ga:Zn=4:2:3[
Laminated structure of [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], In:Ga:Z
Laminated structure of n=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], In:
Laminated structure of Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio] , a laminated structure with gallium oxide, etc.

At this time, the main path of carriers is through the oxide 230b and the vicinity of its interface. By making the oxide 230a and the oxide 230c have the above-described structure, the oxide 230a and the oxide 230
The density of defect levels at the interface between the oxide 230b and the oxide 230c and between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain high on-current and high frequency characteristics. Note that when the oxide 230c has a layered structure, in addition to the effect of lowering the defect level density at the interface between the oxide 230b and the oxide 230c, the constituent elements of the oxide 230c are It is expected that the spread of the virus will be suppressed. More specifically, oxide 230c
has a laminated structure, and in order to position an oxide not containing In above the laminated structure, the insulator 25
In can be suppressed from diffusing to the 0 side. Since the insulator 250 functions as a gate insulator, if In is diffused, the characteristics of the transistor will be poor. Therefore, by forming the oxide 230c into a layered structure, it is possible to provide a highly reliable semiconductor device.

Insulator 250 functions as a gate insulator. It is preferable that the insulator 250 be disposed in contact with the upper surface of the oxide 230c and covering the oxide 230c. The insulator 250 is made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with holes. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

Like the insulator 224, the insulator 250 preferably has a reduced concentration of impurities such as water or hydrogen. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

Further, as will be described later, the insulator 250 may have a function as a protective film when forming the layer 252 and the layer 253. When using ion implantation or ion doping to form the layers 252 and 253, providing the insulator 250 as a protective film prevents the surface of the oxide 230 from being directly exposed to ions or plasma. This is preferable because damage to the oxide 230 during formation of the layer 253 can be suppressed. Here, oxide 23
0 damage means the formation of excessive oxygen vacancies in the oxide 230 or the formation of excessive oxygen vacancies in the oxide 230.
30, a decrease in crystallinity, etc. On top of the insulator 250 that functions as such a protective film,
Furthermore, the above-mentioned barrier insulating films may be stacked.

Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses oxygen diffusion from the insulator 250 to the conductor 260. Thereby, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed. For example, a metal oxide that can be used as the oxide 230c described above may be used.

Further, the metal oxide may function as part of a gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high dielectric constant. When the gate insulator has a stacked structure of the insulator 250 and the metal oxide, it can have a stacked structure that is stable against heat and has a high dielectric constant. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator.
Further, it is possible to reduce the equivalent oxide thickness (EOT) of an insulator that functions as a gate insulator.

Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. can. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing oxides of one or both of aluminum and hafnium.

Although the conductor 260 is shown as having a two-layer structure in FIG. 1, it may have a single-layer structure or a laminated structure of three or more layers.

The conductor 260a has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules ( _N2O , NO, _NO2, etc.), and copper atoms, as described above. It is preferable to use a conductor having the following characteristics. or oxygen (e.g., oxygen atom, oxygen molecule, etc.)
It is preferable to use a conductive material that has the function of suppressing the diffusion of at least one of the following.

Further, since the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to prevent the conductor 260b from being oxidized by the oxygen contained in the insulator 250 and resulting in a decrease in conductivity. As the conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

Further, it is preferable that the conductor 260b is made of a conductive material containing tungsten, copper, or aluminum as a main component. Further, since the conductor 260 also functions as a wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. Further, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

Furthermore, a metal oxide that can be used as the oxide 230 may be provided between the insulator 250 and the conductor 260a. At this time, the metal oxide functions as a gate electrode similarly to the conductor 260. By providing the metal oxide, the insulator 250 and the oxide 230
Oxygen can be supplied to at least one of the two, which is preferable. Moreover, as the metal oxide,
By using a metal oxide that has a function of suppressing oxygen permeation, oxidation of the conductor 260 due to oxygen contained in the insulator 250 or the insulator 280 can be suppressed. Alternatively, oxygen contained in the insulator 250 can be suppressed from being absorbed by the conductor 260.

Further, as shown in FIGS. 1A and 1C, in a region of the oxide 230b that does not overlap with the layer 252 and the layer 253, in other words, in a channel formation region of the oxide 230, the oxide 230b
The conductor 260 covers the side surface of the conductor 260 . This makes it easier to cause the electric field of the conductor 260 functioning as the first gate electrode to act on the side surface of the oxide 230. Therefore, the on-state current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved.

Similar to the insulator 214, the insulator 266 is impurities such as water or hydrogen.
It is preferable that it functions as a barrier insulating film that suppresses infiltration into the transistor 200 from the 80 side. For example, insulator 266 preferably has a lower hydrogen permeability than insulator 224. Further, as shown in FIGS. 1B and 1C, it is preferable that the insulator 266 be in contact with a part of the side surface of the conductor 260 and the top surface of the insulator 250. By configuring like this,
Hydrogen contained in the insulator 280 can be prevented from penetrating into the oxide 230 and the insulator 224.

Furthermore, it is preferable that the insulator 266 has a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate). For example, insulator 266 preferably has a lower oxygen permeability than insulator 280 or insulator 224.

Further, the insulator 266 may be formed using a sputtering method. By forming the insulator 266 using a sputtering method in an atmosphere containing oxygen, the insulator 25
Oxygen can be added near the region in contact with the zero insulator 266. Thereby, oxygen can be supplied into the oxide 230 from the region through the insulator 250. here,
Since the insulator 266 has a function of suppressing upward diffusion of oxygen, oxygen is absorbed into the oxide 23.
0 to the insulator 280 can be prevented. Further, since the insulator 222 has a function of suppressing downward diffusion of oxygen, oxygen can be prevented from diffusing from the oxide 230 toward the substrate side. In this way, oxygen is supplied to the channel forming region of oxide 230. Thereby, oxygen vacancies in the oxide 230 can be reduced, and normally-on state of the transistor can be suppressed.

As the insulator 266, for example, an insulator containing oxides of one or both of aluminum and hafnium may be formed. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like.

Further, the insulator 266 may have a laminated structure. When the insulator 266 has a laminated structure,
The second insulator may be formed using the ALD method on the first insulator formed using the sputtering method. At this time, the first insulator and the second insulator may be made of the same material selected from the materials mentioned above, or may be made of different materials. For example, aluminum oxide formed by sputtering is used as the first insulator, and A
Aluminum oxide formed by the LD method may also be used. A film formed by the ALD method has high coverage, and can form a film with high uniformity even on stepped portions formed by structures such as the oxide 230. Further, it is possible to compensate for defects in film formation in the first insulating film formed by sputtering, which is preferable.

Further, as the insulator 266, for example, an insulator containing aluminum nitride may be used. As the insulator 266, it is preferable to use a nitride insulator whose compositional formula satisfies AlNx (x is a real number greater than 0 and less than or equal to 2, preferably x is a real number greater than 0.5 and less than or equal to 1.5). As a result, a film with excellent insulating properties and excellent thermal conductivity can be obtained, so that heat dissipation of heat generated when the transistor 200 is driven can be improved. Furthermore, aluminum titanium nitride, titanium nitride, or the like can also be used as the insulator 266. In this case, it is preferable to form a film using a sputtering method because the film can be formed without using a strongly oxidizing gas such as oxygen or ozone as a film forming gas. Furthermore, silicon nitride, silicon nitride oxide, or the like can also be used.

In this way, by covering the insulator 250 and the oxide 230 with the insulator 266 having barrier properties against hydrogen, the insulator 280 is separated from the insulator 250 and the oxide 230. This can suppress impurities such as hydrogen from entering the transistor 200 from outside, so that the transistor 200 can have good electrical characteristics and reliability.

Further, as the insulator 266, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. In this case, the insulator 266 is preferably formed using an ALD method. ALD
Since this method is a film forming method with good coverage, it is possible to prevent the formation of step breakage etc. due to the unevenness of the surface to be formed.

Insulator 280 is provided over insulator 224, oxide 230, and insulator 250 via insulator 266. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with holes, etc. It is preferable to have. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

Preferably, the concentration of impurities such as water or hydrogen in the insulator 280 is reduced. Further, the upper surface of the insulator 280 may be flattened.

Like the insulator 214 and the like, the insulator 274 preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the insulator 280 from above. For example, insulator 274 preferably has lower hydrogen permeability than insulator 280.

Furthermore, it is preferable that the insulator 274 has a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate). For example, insulator 274 preferably has a lower oxygen permeability than insulator 280. Since the insulator 274 has a function of suppressing oxygen diffusion, outward diffusion of oxygen contained in the insulator 280 can be suppressed.

As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 222, etc. may be used. Alternatively, a structure may be adopted in which a barrier insulating film against impurities such as water or hydrogen and an insulating film having a function of suppressing oxygen diffusion are stacked.

Further, it is preferable to provide an insulator 281 functioning as an interlayer film on the insulator 274. Like the insulator 224 and the like, the insulator 281 preferably has a reduced concentration of impurities such as water or hydrogen in the film.

Further, the conductor 240a and the conductor 240b are arranged in openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 266. The conductor 240a and the conductor 240b are provided facing each other with the conductor 260 interposed therebetween. Note that the heights of the upper surfaces of the conductor 240a and the conductor 240b may be on the same plane as the upper surface of the insulator 281.

Note that an insulator 241a is provided in contact with the inner walls of the openings of the insulators 281, 274, 280, and 266, and a first conductor of the conductor 240a is formed in contact with the side surface of the insulator 241a. ing. A layer 253a is located at least in part at the bottom of the opening, and the conductor 240a is in contact with the layer 253a. Here, as shown in FIG. 1(D), the conductor 240a
The first conductor is preferably in contact with the top surface and side surfaces of the layer 253a (which may also be referred to as the top surface and side surfaces of the oxide 230b). By providing the conductor 240a in this manner, the contact area between the conductor 240a and the layer 253a increases, so that the on-state current and mobility of the transistor 200 can be improved, and the S value can be reduced. Similarly, the insulator 241b is in contact with the inner wall of the opening of the insulator 281, the insulator 274, the insulator 280, and the insulator 266.
is provided, and a first conductor of the conductor 240b is formed in contact with the side surface thereof. A layer 253b is located at least in part at the bottom of the opening, and the conductor 240b is located on the layer 253b.
come into contact with Although not shown, like the conductor 240a, the first conductor of the conductor 240b is the upper surface and side surfaces of the layer 253b (which may also be referred to as the upper surface and side surfaces of the oxide 230b).
It is preferable that it be in contact with. By providing the conductor 240b in this manner, the contact area between the conductor 240b and the layer 253b increases, so that the on-state current and mobility of the transistor 200 can be improved, and the S value can be reduced.

Note that although FIGS. 1B, 1D, and the like show a structure in which the conductor 240 is in contact with the layer 253 formed on the oxide 230c, this embodiment is not limited to this. For example, conductor 240 passes through oxide 230c and layer 25 formed on oxide 230b.
3 may be adopted.

The conductor 240a and the conductor 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. In addition, the conductor 240a and the conductor 24
0b may have a laminated structure.

In addition, when the conductor 240 has a laminated structure, the conductor in contact with the oxide 230a, the oxide 230b, the insulator 266, the insulator 280, the insulator 274, and the insulator 281 may contain water, hydrogen, or the like described above. It is preferable to use a conductor that has a function of suppressing diffusion of impurities. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Further, the conductive material having the function of suppressing the diffusion of impurities such as water or hydrogen may be used in a single layer or in a stacked layer. By using the conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b. Furthermore, it is possible to suppress impurities such as water or hydrogen from entering the oxide 230 from a layer above the insulator 281 through the conductor 240a and the conductor 240b.

As the insulator 241a and the insulator 241b, an insulator that can be used for the insulator 214 or the like, such as aluminum oxide or silicon nitride, may be used. Insulator 24
1a and the insulator 241b are provided in contact with the insulator 266, so it is possible to prevent impurities such as water or hydrogen from the insulator 280 from entering the oxide 230 through the conductor 240a and the conductor 240b. can. Further, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

An ALD method or a CVD method can be used to form the insulator 241a and the insulator 241b.

Further, although not shown, a conductor functioning as a wiring may be placed in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. As the conductor functioning as the wiring, it is preferable to use a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor may have a laminated structure, for example, a laminated layer of titanium, titanium nitride, and the above-mentioned conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator.

Although not shown, the resistivity is 1.0×10 ¹³ Ωcm or more and 1.0×10 ¹⁵ Ωcm or less, preferably 5.0×10 ¹³ Ωcm or more and 5.0×10 ¹⁴ so as to cover the conductor.
It is preferable to provide an insulator with a resistance of Ωcm or less. By providing an insulator having the above-mentioned resistivity over the conductor, the insulator can maintain insulating properties and disperse the charge accumulated between the transistor 200, the conductor, and other wiring. This is preferable since it is possible to suppress characteristic defects and electrostatic damage of the transistor and electronic equipment including the transistor due to the charge.

FIG. 4 shows a transistor 200 in which laminated insulating films are used as the oxide 230c and the insulator 274, and an insulator 256a and an insulator 256b (hereinafter sometimes referred to collectively as an insulator 256) are provided. Shown below. Similar to FIG. 1, FIGS. 4(A)(B)
(C) and (D) are a top view and a cross-sectional view of the transistor 200 and the vicinity of the transistor 200. FIG. 4A is a top view of a semiconductor device including the transistor 200. Further, FIG. 4(B) and FIG. 4(C) are cross-sectional views of the semiconductor device. Here, Figure 4 (
B) is a cross-sectional view of the portion indicated by the dashed-dotted line on A1-A2 in FIG.
00 is also a sectional view in the channel length direction. In addition, FIG. 4(C) shows A3-A4 in FIG. 4(A).
2 is a cross-sectional view of a portion indicated by a dashed-dotted line, and is also a cross-sectional view of the transistor 200 in the channel width direction. Further, FIG. 4(D) is a cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG. 4(A). Note that in the top view of FIG. 4A, some elements are omitted for clarity of illustration.

In the transistor 200 shown in FIG. 4, an oxide 230c1 and an oxide 230c2 stacked thereon are used as the oxide 230c, and an insulator 274a and an insulator 274b stacked thereon are used as the insulator 274. There is.

Here, a metal oxide that can be used as the oxide 230b may be used as the oxide 230c1, and a metal oxide that can be used as the oxide 230a may be used as the oxide 230c2. For example, as the oxide 230c1, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] is used, and as the oxide 230c2, a metal oxide with In:Ga:Zn=1:3:4 is used.
[Atomic ratio] may be used.

Further, as the insulator 274a, an insulator having a function of suppressing oxygen diffusion is used as the insulator 274a.
As 74b, an insulator that functions as a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen may be used. For example, aluminum oxide or the like formed by sputtering can be used as the insulator 274a. Furthermore, silicon nitride, silicon nitride oxide, aluminum nitride, or the like can be used as the insulator 274b.

Furthermore, as shown in FIG. 4, it is preferable to provide an insulator 256 between the insulator 250 and the insulator 266. As shown in FIG. 4, the insulator 256 has a laminated structure of an insulator 256a and an insulator 256b thereon.

The insulator 256a may function as a protective film when forming the layer 252 and the layer 253. When using ion implantation or ion doping to form the layers 252 and 253, providing the insulator 256a as a protective film prevents the surface of the oxide 230 from being directly exposed to ions or plasma. This is preferable because damage to the oxide 230 during formation of the layer 253 can be suppressed. Here, damage to the oxide 230 refers to excessive formation of oxygen vacancies in the oxide 230, excessive reduction in crystallinity of the oxide 230, and the like.

Like the insulator 214 and the like, the insulator 256b preferably functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the insulator 280 side. For example, insulator 256b preferably has lower hydrogen permeability than insulator 250. Further, as shown in FIGS. 4B and 4C, the insulator 256b is preferably disposed so as to be in contact with the top surface of the insulator 250 and the side surface of the conductor 260. With such a configuration, hydrogen contained in the insulator 280 can be prevented from penetrating into the oxide 230 and the insulator 250.

In this way, by covering the insulator 224, the insulator 250, and the oxide 230 with the insulator 266 and the insulator 256b having barrier properties against hydrogen, the insulator 280 can be
An insulator 224, an oxide 230, and an insulator 250 are spaced apart from each other. This can suppress impurities such as hydrogen from entering the transistor 200 from outside, so that the transistor 200 can have good electrical characteristics and reliability.

Furthermore, it is preferable that the insulator 256b has a function of suppressing the diffusion of at least one of oxygen (eg, oxygen atoms, oxygen molecules, etc.) (the oxygen is difficult to permeate). for example,
Insulator 256b preferably has lower oxygen permeability than insulator 224. Insulator 256b
However, by having the function of suppressing oxygen diffusion, the oxide 230 can be suppressed from reacting with excess oxygen included in the insulator 280.

As the insulator 256b, for example, a barrier insulating film that can be used for the insulator 266 may be used. However, if the insulator 266 has sufficient barrier properties against hydrogen, the insulator 256b does not necessarily need to be a barrier insulating film.

For example, the insulator 256a may be an insulator that functions as a protective film when forming the oxide 230 and the insulator 250, and the insulator 256b may be a barrier insulating film that suppresses the incorporation of impurities such as water or hydrogen. An insulator that functions as an insulator may be used. For example, silicon oxynitride or silicon oxide can be used as the insulator 256a. Further, as the insulator 256b, silicon nitride, silicon nitride oxide, aluminum nitride, aluminum oxide, or the like can be used.

In FIG. 4, the insulator 256 has a laminated structure of an insulator 256a and an insulator 256b, but the present embodiment is not limited to this. The insulator 256 may be a single layer or may have a laminated structure of three or more layers.

<Constituent materials of semiconductor devices>
Below, constituent materials that can be used in the semiconductor device will be explained.

<<Substrate>>
As a substrate for forming the transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, a semiconductor substrate having an insulator region inside the semiconductor substrate described above, for example, an SOI (Silicon On
Insulator) board, etc. Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, there are substrates containing metal nitrides, substrates containing metal oxides, and the like. Furthermore, a substrate in which a conductor or a semiconductor is provided on an insulator substrate,
There are substrates in which a semiconductor substrate is provided with a conductor or an insulator, and substrates in which a conductor substrate is provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Elements provided on the substrate include capacitive elements, resistive elements, switch elements, light emitting elements, and memory elements.

<<Insulator>>
Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.

For example, as transistors become smaller and more highly integrated, problems such as leakage current may occur due to thinning of gate insulators. An insulator that acts as a gate insulator,
By using a high-k material, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant as the insulator that functions as an interlayer film, parasitic capacitance occurring between wirings can be reduced. Therefore, the material should be selected depending on the function of the insulator.

Insulators with high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, and silicon and hafnium. There are oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

Insulators with low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon,
Examples include silicon oxide to which carbon and nitrogen are added, silicon oxide with pores, and resin.

In addition, a transistor using an oxide semiconductor can be surrounded by an insulator (such as the insulator 214, the insulator 222, the insulator 256, and the insulator 274) that has the function of suppressing the permeation of impurities such as hydrogen and oxygen. , the electrical characteristics of the transistor can be stabilized.
Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or in a laminated manner.
Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen,
Metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide or Metal nitrides such as silicon nitride can be used.

Further, the insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

<<Conductor>>
Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. It is preferable to use a metal element selected from the following, an alloy containing the above-mentioned metal elements as a component, an alloy containing a combination of the above-mentioned metal elements, or the like. For example, use of tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. It is preferable. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are difficult to oxidize. It is preferable because it is a conductive material or a material that maintains conductivity even if it absorbs oxygen. Further, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

Further, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a layered structure may be used in which a material containing the metal element described above and a conductive material containing oxygen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element and a conductive material containing nitrogen are combined. Alternatively, a laminated structure may be used in which a material containing the aforementioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined.

Note that when an oxide is used in the channel formation region of a transistor, the conductor that functions as the gate electrode should have a stacked structure that is a combination of a material containing the aforementioned metal element and a conductive material containing oxygen. is preferred. In this case, it is preferable to provide a conductive material containing oxygen on the channel forming region side. By providing a conductive material containing oxygen on the side of the channel formation region, oxygen released from the conductive material is easily supplied to the channel formation region.

In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as the conductor functioning as the gate electrode. Further, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may also be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Alternatively, it may be possible to capture hydrogen mixed in from an external insulator or the like.

<<Metal oxide>>
As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor). Below, metal oxides applicable to the oxide 230 according to the present invention will be explained.

The oxide semiconductor preferably contains at least indium or zinc. In particular, it is preferable to include indium and zinc. Moreover, in addition to these, it is preferable that aluminum, gallium, yttrium, tin, or the like is contained. Further, one or more selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be included.

Here, a case will be considered in which the oxide semiconductor is an In--M--Zn oxide containing indium, the element M, and zinc. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium,
These include neodymium, hafnium, tantalum, tungsten, and magnesium. However, as the element M, there are cases where a plurality of the above-mentioned elements may be combined.

Note that in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide (metal oxide).
ide). In addition, metal oxides containing nitrogen can be replaced with metal oxynitrides (me
tal oxynitride).

Oxide semiconductors are divided into single crystal oxide semiconductors and non-single crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, polycrystalline oxide semiconductors, amorphous oxide semiconductors, and the like are known.

It is preferable to use a thin film with high crystallinity as an oxide semiconductor used for a semiconductor of a transistor. By using the thin film, stability or reliability of a transistor can be improved. Examples of the thin film include a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film. However, forming a single crystal oxide semiconductor thin film or a polycrystalline oxide semiconductor thin film on a substrate requires a high temperature or laser heating process. Therefore, the cost of the manufacturing process increases and the throughput also decreases.

In 2009, it is reported in Non-Patent Document 1 and Non-Patent Document 2 that In--Ga--Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered. It is reported here that CAAC-IGZO has c-axis orientation, grain boundaries are not clearly observed, and can be formed on a substrate at low temperatures. Furthermore, it has been reported that transistors using CAAC-IGZO have excellent electrical characteristics and reliability.

Furthermore, in 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it has been reported that nc-IGZO has periodicity in its atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and that no regularity is observed in the crystal orientation between different regions. There is.

In Non-Patent Document 4 and Non-Patent Document 5, the above CAAC-IGZO, nc-IGZO,
The changes in average crystal size due to electron beam irradiation for each thin film of IGZO and IGZO with low crystallinity are shown. In a thin film of IGZO with low crystallinity, crystalline IGZO of about 1 nm is observed even before electron beam irradiation. Therefore, here, IGZO has a completely amorphous structure.
It is reported that the existence of ure) could not be confirmed. Furthermore, IGZO with low crystallinity
It has been shown that the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability against electron beam irradiation than the nc-IGZO thin film. Therefore, CAA can be used as a transistor semiconductor.
It is preferable to use a thin film of C-IGZO or a thin film of nc-IGZO.

A transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state. Specifically, the off-state current per 1 μm of transistor channel width is yA/μm (10 ^−
24 A/μm) order, as shown in Non-Patent Document 6. For example, a CPU with low power consumption that takes advantage of the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Non-Patent Document 7).

In addition, taking advantage of the low leakage current characteristics of transistors using oxide semiconductors,
Application of the transistor to a display device has been reported (see Non-Patent Document 8). In a display device, the displayed image changes several dozen times per second. The number of times images are switched per second is called the refresh rate. The refresh rate is also sometimes called the drive frequency. Such high-speed screen switching, which is difficult for the human eye to perceive, is thought to be a cause of eye fatigue. Therefore, it has been proposed to lower the refresh rate of the display device to reduce the number of times images are rewritten. Further, by driving at a lower refresh rate, it is possible to reduce power consumption of the display device. Such a driving method is called idling stop (IDS) driving.

The discovery of the CAAC structure and nc structure has contributed to improving the electrical characteristics and reliability of transistors using oxide semiconductors having a CAAC structure or nc structure, as well as reducing costs and improving throughput of manufacturing processes. In addition, research is underway to apply the transistor to display devices and LSIs, taking advantage of the transistor's low leakage current characteristics.

[Composition of metal oxide]
Below, CAC (C
The configuration of the loud-Aligned Composite)-OS will be explained.

In addition, in this specification etc., CAAC (c-axis aligned crystal
1), and CAC (Cloud-Aligned Composite). Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a material configuration.

CAC-OS or CAC-metal oxide has a part of the material having a conductive function, a part of the material having an insulating function, and the entire material having a semiconductor function. Note that when CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is to allow electrons (or holes) to flow as carriers, and the insulating function is to flow electrons (or holes) as carriers. This is a function that prevents the flow of Switching function (On/O
ff function) can be added to CAC-OS or CAC-metal oxide. By separating the functions of CAC-OS or CAC-metal oxide, the functions of both can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in a material, a conductive region and an insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. Further, the conductive regions may be observed to be connected in a cloud-like manner with the periphery blurred.

In addition, in CAC-OS or CAC-metal oxide, a conductive region and
The insulating regions each have a thickness of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or more.
It may be dispersed in the material with a size of less than m.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal ox
ide is composed of a component having a wide gap caused by the insulating region and a component having a narrow gap caused by the conductive region. In the case of this configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. Furthermore, the component having a narrow gap acts complementary to the component having a wide gap, and carriers also flow into the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the above-mentioned CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current, and high field effect mobility can be obtained in the on state of the transistor.

That is, CAC-OS or CAC-metal oxide is a matrix composite or a metal matrix composite.
It can also be called a matrix composite.

[Structure of metal oxide]
Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single crystal oxide semiconductors include CAAC-OS (c-axis
igned crystalline oxide semiconductor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline oxide SEM)
iconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorph
ous-like oxide semiconductors) and amorphous oxide semiconductors.

CAAC-OS has c-axis orientation and a plurality of nanocrystals connected in the a-b plane direction, resulting in a distorted crystal structure. Note that distortion refers to a location where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and another region where the lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.

Although nanocrystals are basically hexagonal, they are not limited to regular hexagonal shapes and may have irregular hexagonal shapes. In addition, the distortion may have a pentagonal or heptagonal lattice arrangement. Note that in CAAC-OS, clear grain boundaries (also referred to as grain boundaries) cannot be confirmed even in the vicinity of strain. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, and the bond distance between atoms changes due to substitution of metal elements. It is thought that this is because of this.

In addition, CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter referred to as an "In layer") and a layer containing element M, zinc, and oxygen (hereinafter referred to as a (M,Zn) layer) are laminated. They tend to have a structure (also called a layered structure). Note that indium and element M can be substituted with each other, and when element M of the (M, Zn) layer is substituted with indium, (In, M, Zn
) layer. Furthermore, when indium in the In layer is replaced with element M, (In,
M) It can also be expressed as a layer.

CAAC-OS is a highly crystalline oxide semiconductor. On the other hand, in CAAC-OS, since clear grain boundaries cannot be confirmed, it can be said that reduction in electron mobility due to grain boundaries is less likely to occur. Further, since the crystallinity of an oxide semiconductor may be reduced due to the incorporation of impurities or the formation of defects, CAAC-OS can also be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, an oxide semiconductor having CAAC-OS has stable physical properties. Therefore, an oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, in nc-OS, no regularity is observed in crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be indistinguishable from a-like OS or amorphous oxide semiconductor.

The a-like OS is an oxide semiconductor having a structure between that of an nc-OS and an amorphous oxide semiconductor. A-like OS has holes or low density areas. That is, a-lik
e OS has lower crystallinity compared to nc-OS and CAAC-OS.

Oxide semiconductors have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention includes an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an n
It may have two or more types of c-OS and CAAC-OS.

[Transistor with oxide semiconductor]
Next, a case where the above oxide semiconductor is used in a transistor will be described.

Note that by using the above oxide semiconductor for a transistor, a transistor with high field-effect mobility can be realized. Further, a highly reliable transistor can be realized.

Further, it is preferable to use an oxide semiconductor with low carrier density for the transistor.
In order to lower the carrier density of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be lowered to lower the defect level density. In this specification etc., the impurity concentration is low,
Low defect level density is referred to as high-purity intrinsic or substantially high-purity intrinsic. For example, the oxide semiconductor has a carrier density of less than 8×10 ¹¹ /cm ³ , preferably 1×10 ¹¹ /cm ³
It is less than 1×10 ¹⁰ /cm ³ , more preferably less than 1×10 −9 /cm 3 , and may be 1×10 ⁻⁹ /cm ³ or more.

Further, since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect level density, the trap level density may also be low.

In addition, charges captured in trap levels of an oxide semiconductor may take a long time to disappear, and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap level density may have unstable electrical characteristics.

Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In addition, in order to reduce the impurity concentration in the oxide semiconductor,
Preferably, the impurity concentration in adjacent films is also reduced. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[impurities]
Here, the influence of each impurity in the oxide semiconductor will be described.

When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon and carbon in the oxide semiconductor and the concentration of silicon and carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are ×10 ¹⁸ atoms/cm ³ or less, preferably 2 × 10 ¹⁷ a
toms/cm ³ or less.

Further, when an alkali metal or an alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have normally-on characteristics.
Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is set to 1×10 ¹⁸ atoms/cm ³ or less, preferably 2×10
¹⁶ atoms/ ^cm3 or less.

Furthermore, when an oxide semiconductor contains nitrogen, electrons as carriers are generated, the carrier density increases, and the semiconductor becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Therefore, in the oxide semiconductor, nitrogen is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 atoms/cm 3 in SIMS.
¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, even more preferably 5×10 ¹⁷ atoms/cm ³ or less.

Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to become water, which may result in the formation of oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons, which are carriers, may be generated. Further, a portion of hydrogen may combine with oxygen that is bonded to a metal atom to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. Therefore, it is preferable that hydrogen in the oxide semiconductor be reduced as much as possible. Specifically, in oxide semiconductors, SI
The hydrogen concentration obtained by MS is lower than 1×10 ²⁰ atoms/cm ³ , preferably 1×
It is less than 10 ¹⁹ atoms/cm ³ , more preferably less than 5×10 ¹⁸ atoms/cm ³ , even more preferably less than 1×10 ¹⁸ atoms/cm ³ .

By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be provided.

[Effects of vacuum baking]
Here, a weak Zn--O bond contained in a metal oxide will be explained, and an example of a method for reducing the oxygen atoms and zinc atoms constituting the bond will be shown.

In a transistor using a metal oxide, oxygen vacancies are an example of defects that lead to poor electrical characteristics of the transistor. For example, a transistor using a metal oxide containing oxygen vacancies in its film tends to have a threshold voltage that fluctuates in the negative direction and tends to have normally-on characteristics. This is because donors are generated due to oxygen vacancies contained in the metal oxide, and the carrier concentration increases. When a transistor has normally-on characteristics, various problems arise, such as malfunctions being more likely to occur during operation or increased power consumption when not operating.

In addition, due to thermal history (thermal budget) in the process of forming connection wiring for manufacturing modules, the electrical characteristics of transistors may deteriorate, such as fluctuations in threshold voltage and increases in parasitic resistance, and electrical There are problems such as increased variation in characteristics. These problems are directly linked to a decrease in manufacturing yield, so it is important to consider countermeasures. In addition, deterioration of electrical characteristics occurs even in stress tests that can quickly evaluate changes in transistor characteristics (changes over time) caused by long-term use. It is presumed that the deterioration of the electrical properties is caused by the loss of oxygen in the metal oxide due to the high temperature treatment performed during the thermal history process or the electrical stress applied during the stress test.

Metal oxides contain oxygen atoms that have weak bonds with metal atoms and tend to become oxygen vacancies. In particular, when the metal oxide is an In-Ga-Zn oxide, zinc atoms and oxygen atoms tend to form weak bonds (also referred to as weak Zn-O bonds). Here, a weak Zn-O bond is a bond between a zinc atom and an oxygen atom that is strong enough to be broken by high-temperature treatment performed during thermal history or by electrical stress applied during a stress test. It is a combination that occurs in When weak Zn--O bonds exist in a metal oxide, the bonds are broken by thermal history or current stress, and oxygen vacancies are formed. The formation of oxygen vacancies reduces the stability of the transistor, such as resistance to thermal history and resistance to stress tests.

The bond that occurs between the zinc atom and the oxygen atom, which is often bonded to the zinc atom, is a weak Zn
-O bond may be present. Compared to gallium atoms, zinc atoms have weaker bonds with oxygen atoms. Therefore, oxygen atoms that are bonded to many zinc atoms are likely to be deleted. That is, it is presumed that the bond formed between the zinc atom and the oxygen atom is weaker than the bond with other metals.

Furthermore, it is assumed that when impurities are present in the metal oxide, weak Zn--O bonds are likely to be formed. Examples of impurities in metal oxides include water molecules and hydrogen. Due to the presence of water molecules and hydrogen in the metal oxide, the hydrogen atoms may bond with the oxygen atoms constituting the metal oxide (also referred to as OH bond). The oxygen atoms constituting the metal oxide are In-Ga-
When the Zn oxide is a single crystal, it is bonded to four metal atoms constituting the metal oxide. However, an oxygen atom bonded to a hydrogen atom may be bonded to two or three metal atoms. As the number of metal atoms bonded to an oxygen atom decreases, the oxygen atom becomes more likely to be deficient. In addition, when a zinc atom is bonded to an oxygen atom forming an OH bond,
It is presumed that the bond between the oxygen atom and the zinc atom is weak.

In addition, weak Zn--O bonds may be formed in a strain that exists in a region where a plurality of nanocrystals are connected. Nanocrystals are basically hexagonal, but in this distortion, they have lattice arrangements such as pentagonal and heptagonal. In this strain, the bond distance between atoms is not uniform, so the weak Zn
It is presumed that an -O bond is formed.

Furthermore, it is assumed that weak Zn--O bonds are likely to be formed when the metal oxide has low crystallinity. When the metal oxide has high crystallinity, the zinc atoms constituting the metal oxide are bonded to four or five oxygen atoms. However, as the crystallinity of the metal oxide decreases, the number of oxygen atoms bonded to zinc atoms tends to decrease. When the number of oxygen atoms bonded to a zinc atom decreases, the zinc atom becomes more likely to become defective. That is, it is presumed that the bond formed between the zinc atom and the oxygen atom is weaker than the bond formed in a single crystal.

By reducing the oxygen atoms and zinc atoms that constitute the above-mentioned weak Zn--O bonds, it is possible to suppress the formation of oxygen vacancies due to thermal history or current stress, and improve the stability of the transistor. Note that only the oxygen atoms constituting the weak Zn-O bond are reduced, and the weak Zn-O
If the zinc atoms constituting the bond are not reduced, the weak Zn--O bond may be re-formed when oxygen atoms are supplied near the zinc atom. Therefore, it is preferable to reduce the number of zinc atoms and oxygen atoms that constitute weak Zn--O bonds.

One method for reducing oxygen atoms and zinc atoms that constitute weak Zn--O bonds is to perform vacuum baking after forming a metal oxide film. Vacuum baking is a heat treatment performed in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuation using a turbo molecular pump or the like. Note that the pressure in the processing chamber is 1×10 ⁻² Pa or less, preferably 1×10
^-3 Pa or less is sufficient. Further, the temperature of the substrate during the heat treatment may be 300° C. or higher, preferably 400° C. or higher.

By performing vacuum baking, oxygen atoms and zinc atoms that constitute weak Zn--O bonds can be reduced. In addition, since heat is applied to the metal oxide by vacuum baking, the oxygen atoms and zinc atoms that make up the weak Zn-O bond are reduced, and the atoms that make up the metal oxide rearrange, resulting in the formation of four metals. The number of oxygen atoms bonded to atoms increases. Therefore, the oxygen atoms and zinc atoms that constitute the weak Zn-O bond are reduced, and the weak Zn-
Re-formation of O bonds can be suppressed.

Further, when impurities are present in the metal oxide, vacuum baking can release water molecules or hydrogen in the metal oxide and reduce OH bonds. O in metal oxides
By reducing the H-bonds, the proportion of oxygen atoms bonded to the four metal atoms increases. Also, when water molecules or hydrogen are released, the atoms constituting the metal oxide rearrange, resulting in 4
The number of oxygen atoms bonded to one metal atom increases. Therefore, reformation of weak Zn--O bonds can be suppressed.

As described above, by performing vacuum baking after forming a metal oxide film, weak Zn-O
Oxygen atoms and zinc atoms that constitute bonds can be reduced. Therefore, this step can improve the stability of the transistor. Furthermore, by improving the stability of the transistor, the degree of freedom in selecting materials and formation methods increases.

<Method for manufacturing semiconductor device>
Next, a method for manufacturing a semiconductor device including the transistor 200 according to one embodiment of the present invention shown in FIG. 1 will be described with reference to FIGS. 5 to 14. Furthermore, in FIGS. 5 to 14, (A) in each figure shows a top view. Further, (B) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line A1-A2 shown in (A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, (C) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in (A), and is also a cross-sectional view in the channel width direction of the transistor 200. Also, (D) in each figure
is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in (A). In addition, in each figure (
In the top view of A), some elements are omitted for clarity.

First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 is formed by sputtering or chemical vapor deposition (CVD).
or Deposition) method, molecular beam epitaxy (MBE:Molecular
Beam Epitaxy) method, Pulsed Laser Deposition (PLD)
method, or ALD (Atomic Layer Deposition) method, or ALD (Atomic Layer Deposition) method.
This can be done using a method such as tion).

Note that the CVD method is plasma CVD (PECVD) that uses plasma.
Enhanced CVD) method, Thermal CVD (TCVD: Thermal C
It can be classified into the photo CVD method, which uses light, and the photo CVD method, which uses light. Furthermore, depending on the raw material gas used, metal CVD (MCVD) method, organometallic CVD method, etc.
(MOCVD: Metal Organic CVD) method.

The plasma CVD method can obtain a high quality film at a relatively low temperature. Further, since the thermal CVD method does not use plasma, it is a film forming method that can reduce plasma damage to the object to be processed. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the accumulated charges may destroy wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, since plasma damage does not occur during film formation, a film with fewer defects can be obtained.

In addition, the ALD method uses the self-control property of atoms to deposit atoms one layer at a time, making it possible to form extremely thin films and structures with high aspect ratios. It has the following effects: it is possible to form a film with few defects such as holes, it is possible to form a film with excellent coverage, and it is possible to form a film at a low temperature. In addition, the ALD method includes PEALD (a film forming method using plasma).
Also included is the Plasma Enhanced ALD method. By using plasma,
It may be possible to form a film at a lower temperature, which may be preferable. Note that some precursors used in the ALD method contain impurities such as carbon. Therefore, a film formed by the ALD method may contain more impurities such as carbon than a film formed by other film forming methods. The impurities can be quantified using X-ray photoelectron spectroscopy (XPS).
n Spectroscopy).

The CVD method and the ALD method are film-forming methods in which a film is formed by a reaction on the surface of an object, unlike film-forming methods in which particles emitted from a target or the like are deposited. Therefore, this is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is therefore suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed by changing the flow rate ratio of source gases. Further, for example, in the CVD method and the ALD method, by changing the flow rate ratio of the raw material gas while forming the film, it is possible to form a film in which the composition changes continuously. When forming a film while changing the flow rate ratio of raw material gases, compared to forming a film using multiple film formation chambers, the time required for film formation is reduced because it does not require time for transportation or pressure adjustment. can do. Therefore, it may be possible to improve the productivity of semiconductor devices.

In this embodiment, aluminum oxide is formed as the insulator 214 by a sputtering method. Further, the insulator 214 may have a multilayer structure. For example, a structure may be adopted in which aluminum oxide is formed into a film by a sputtering method, and then aluminum oxide is formed into a film by an ALD method on the aluminum oxide. Alternatively, a structure may be used in which aluminum oxide is formed into a film by an ALD method, and then aluminum oxide is formed into a film by a sputtering method on the aluminum oxide.

Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
In this embodiment, silicon oxide is formed as the insulator 216 by a CVD method.

Next, an opening reaching the insulator 214 is formed in the insulator 216 using a lithography method. The opening includes, for example, a groove or a slit. Further, an area in which an opening is formed may be referred to as an opening. Although a wet etching method may be used to form the opening, it is preferable to use a dry etching method for fine processing. Furthermore, it is preferable to select an insulator for the insulator 214 that functions as an etching stopper when etching the insulator 216 to form an opening. For example, when silicon oxide is used for the insulator 216 that forms the opening, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator 214 as an insulator that functions as an etching stopper.

Note that in the lithography method, the resist is first exposed to light through a mask. Next, a resist mask is formed by removing or leaving the exposed area using a developer. next,
By performing an etching process through the resist mask, a conductor, semiconductor, insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing a resist to light using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, a mask is not required. Note that the resist mask can be removed by performing a dry etching process such as ashing, by performing a wet etching process, by performing a wet etching process after a dry etching process, or by performing a dry etching process after a wet etching process.

Furthermore, a hard mask made of an insulator or a conductor may be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on the insulating film that will serve as the insulator 216, a resist mask is formed on top of the insulating film, and the hard mask material is etched to form the desired shape. A hard mask can be formed. Etching of the insulating film that will become the insulator 216 may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the insulating film that will become the insulator 216. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

As a dry etching device, a capacitively coupled plasma (CCP) with parallel plate electrodes is used.
:Capacitively Coupled Plasma) etching apparatus can be used. A capacitively coupled plasma etching apparatus having parallel plate type electrodes may have a configuration in which a high frequency power source is applied to one electrode of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which a plurality of different high frequency power sources are applied to one electrode of a parallel plate type electrode. Alternatively, a configuration may be adopted in which a high frequency power source having the same frequency is applied to each of the parallel plate type electrodes. Alternatively, a configuration may be adopted in which high frequency power sources having different frequencies are applied to each of the parallel plate type electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source is, for example, an inductively coupled plasma (ICP).
A plasma etching device or the like can be used.

After forming the opening, a conductive film that becomes the first conductor of the conductor 205 is formed. As the conductive film, it is preferable to use a conductive barrier film having a function of suppressing permeation of impurities and oxygen.
For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used. Alternatively, it can be a laminated film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and molybdenum-tungsten alloy. The conductive film that becomes the first conductor of the conductor 205 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, tantalum nitride, tantalum nitride,
Alternatively, a film in which titanium nitride is laminated on tantalum nitride is formed. By using such a metal nitride as the first conductor of the conductor 205, even if a metal that easily diffuses, such as copper, is used as the second conductor of the conductor 205, the metal nitride can be used as the first conductor of the conductor 205. Diffusion from one conductor to the outside can be suppressed.

Next, a conductive film that will become the second conductor of the conductor 205 is formed over the conductive film that will become the first conductor of the conductor 205 . The conductive film can be formed by sputtering method, CVD method, MBE method,
This can be performed using a PLD method, an ALD method, or the like. In this embodiment, the conductor 2
A low resistance conductive material such as tungsten, copper, or aluminum is formed as a conductive film to become the second conductor of No. 05.

Next, by performing a CMP (Chemical Mechanical Polishing) process, part of the conductive film that will become the first conductor of the conductor 205 and the conductive film that will become the second conductor of the conductor 205 are removed by polishing. Then, the insulator 216 is exposed. As a result, the conductive film that becomes the first conductor of the conductor 205 and the conductive film that becomes the second conductor of the conductor 205 remain only in the opening. As a result, the conductor 205 including the first conductor of the conductor 205 and the second conductor of the conductor 205 with a flat upper surface can be formed (see FIG.
reference. ). Note that part of the insulator 216 may be removed by the CMP process.

Note that the method for manufacturing the insulator 216 and the conductor 205 is not limited to the above method. For example, the conductor 205 is formed by forming a conductive film to become the conductor 205 over the insulator 214 and processing the conductive film using a lithography method. Next, an insulating film that will become the insulator 216 is provided so as to cover the conductor 205, and a part of the insulating film is removed from the conductor 205 by CMP processing.
The conductor 205 and the insulator 216 may be formed by removing until a portion of the conductor 205 and the insulator 216 are exposed.

By forming the conductor 205 and the insulator 216 using CMP processing as described above, the flatness of the upper surfaces of the conductor 205 and the insulator 216 can be improved, and in a later process, the oxide 230a, The crystallinity of CAAC-OS forming the oxide 230b and the oxide 230c can be improved.

Next, an insulator 222 is formed over the insulator 216 and the conductor 205. Insulator 222
It is preferable to form a film of an insulator containing oxides of one or both of aluminum and hafnium. Note that as the insulator containing an oxide of one or both of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in the structure provided around the transistor 200 are suppressed from diffusing into the inside of the transistor 200 through the insulator 222. , the generation of oxygen vacancies in the oxide 230 can be suppressed.

The film of the insulator 222 can be formed by sputtering method, CVD method, MBE method, PLD method, or A
This can be done using the LD method or the like.

Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Subsequently, it is preferable to perform heat treatment. The heat treatment may be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas. Further, the heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of oxidizing gas to compensate for the desorbed oxygen after heat treatment in a nitrogen or inert gas atmosphere. good.

In this embodiment, heat treatment is performed at 400° C. in a nitrogen atmosphere after the insulator 224 is formed.
Treatment is carried out at a temperature of 1 hour. Through the heat treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. Further, the heat treatment can also be performed at a timing such as after the insulator 222 is formed.

Here, in order to form an excess oxygen region in the insulator 224, plasma treatment containing oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power source that generates high-density plasma using microwaves, for example. Or, RF (
It may also have a power supply that applies radio frequency). By using high-density plasma, high-density oxygen radicals can be generated, and by applying RF to the substrate side, the oxygen radicals generated by high-density plasma can be efficiently guided into the insulator 224. can. Or, after performing plasma treatment containing inert gas using this equipment,
Plasma treatment containing oxygen may be performed to compensate for the desorbed oxygen. Note that impurities such as water and hydrogen contained in the insulator 224 can be removed by appropriately selecting the conditions for the plasma treatment. In that case, heat treatment may not be performed.

Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulator 224 (see FIG. 5). Note that the oxide film is preferably formed continuously without being exposed to the atmospheric environment. By forming the film without exposing it to the atmosphere, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230A and the oxide film 230B.
The vicinity of the interface with 0B can be kept clean.

The oxide film 230A and the oxide film 230B are formed by sputtering, CVD, or MBE.
This can be carried out using a method such as a method, a PLD method, or an ALD method.

For example, when forming the oxide films 230A and 230B by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. Furthermore, when the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target or the like can be used. Further, a direct current (DC) power source or an alternating current (AC) power source such as a radio frequency (RF) power source is connected to the target, and necessary power can be applied depending on the electrical conductivity of the target.

Particularly, when forming the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

Furthermore, when the oxide film 230B is formed by a sputtering method, if the proportion of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. It is formed. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can achieve relatively high field-effect mobility. Furthermore, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved. However, one embodiment of the present invention is not limited thereto. When forming the oxide film that will become the oxide 230b by sputtering, the proportion of oxygen contained in the sputtering gas is increased to more than 30% to 100%.
% or less, preferably 70% or more and 100% or less, an oxygen-excess type oxide semiconductor is formed. A transistor using an oxygen-rich oxide semiconductor in a channel formation region has relatively high reliability.

In this embodiment, the oxide film 230A is formed using In:Ga:
Zn=1:1:0.5 [atomic ratio] (2:2:1 [atomic ratio]) or 1:3:4 [
A film is formed using a target with the following atomic ratio. Further, the oxide film 230B is formed by sputtering using a target with In:Ga:Zn=4:2:4.1 [atomic ratio]. Note that each oxide film can be formed by appropriately selecting the film formation conditions and the atomic ratio.
It is preferable to form it in accordance with the characteristics required for 30.

Here, it is preferable that the insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B be formed without being exposed to the atmosphere. For example, a multi-chamber type film forming apparatus may be used.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. The heat treatment can remove impurities such as water and hydrogen in the oxide films 230A and 230B. In this embodiment, the process is performed at a temperature of 400° C. for 1 hour in a nitrogen atmosphere, and then the process is continuously performed at a temperature of 400° C. for 1 hour in an oxygen atmosphere.

Next, the oxide films 230A and 230B are processed into island shapes to form oxides 230a and 230b (see FIG. 6). Note that in this step, the insulator 224
The film thickness may be thinner in a region that does not overlap with the oxide 230a. Further, in this step, the insulator 224 may be processed into an island shape that overlaps with the oxide 230a, so that a part of the insulator 222 is exposed.

Here, the oxide 230a and the oxide 230b are formed so that at least a portion thereof overlaps with the conductor 205. In addition, the side surfaces of the oxide 230a and the oxide 230b and the insulator 2
22 may be configured so that the angle formed by the upper surface thereof is a small angle. In that case, the angle between the side surfaces of oxide 230a and oxide 230b and the top surface of insulator 222 is preferably 60° or more and less than 70°. With such a shape, the covering properties of the insulator 266 and the like can be improved in subsequent steps, and defects such as holes can be reduced. Or, the side surface of the oxide 230b is
It may be approximately perpendicular to the upper surface of the insulator 222. Oxide 230a and oxide 23
Since the side surface of 0b is approximately perpendicular to the upper surface of the insulator 222, it is possible to reduce the area and increase the density when providing a plurality of transistors 200.

Further, a curved surface is provided between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, it is preferable that the end of the side surface and the end of the top surface be curved (hereinafter also referred to as round shape). For example, the curved surface has a radius of curvature of 3 nm or more at the end of the oxide 230b layer.
The thickness is 0 nm or less, preferably 5 nm or more and 6 nm or less. By not having corners at the ends, the coverage of the film in the subsequent film forming process is improved.

Note that the oxide film 230A and the oxide film 230B may be processed using a lithography method. Moreover, the processing can use a dry etching method or a wet etching method. Processing by dry etching is suitable for microfabrication.

Further, by performing a process such as dry etching, impurities caused by etching gas or the like may adhere to or diffuse into the surfaces or insides of the oxides 230a, 230b, and the like. Examples of impurities include fluorine and chlorine.

Cleaning is performed to remove the above impurities. Cleaning methods include wet cleaning using cleaning liquid, plasma treatment using plasma, and cleaning by heat treatment.
The above washing may be performed in combination as appropriate.

The wet cleaning may be performed using an aqueous solution of oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed. In this embodiment, ultrasonic cleaning is performed using pure water or carbonated water.

Next, it is preferable to perform heat treatment before forming an oxide film that will become the oxide 230c. The heat treatment may be performed at a temperature of 100°C or more and 400°C or less, for example, 200°C. Alternatively, it is preferable to perform the process at the same temperature as the film formation temperature of the oxide film that will become the oxide 230c. Here, the film-forming temperature is not limited to the substrate temperature during film-forming, but also includes the set temperature of the film-forming apparatus. For example, when forming an oxide film to become the oxide 230c at 300°C, the heat treatment is preferably performed at 300°C. The heat treatment is preferably performed under reduced pressure, and may be performed, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuation using a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber may be 1×10 ⁻² Pa or less, preferably 1×10 ⁻³ Pa or less.

Next, an oxide film to become the oxide 230c is formed to cover the oxide 230a and the oxide 230b (see FIG. 6). Further, after the heat treatment, it is preferable to continuously form an oxide film to become the oxide 230c without exposing it to the atmosphere. For example, it is preferable to perform the heat treatment and the film formation process consecutively in different chambers using a multi-chamber type film formation apparatus, which will be described later. By performing such treatment, impurities such as moisture, hydrogen, and carbon adsorbed on the surfaces of the oxides 230a and 230b are removed, and the water concentration in the oxides 230a and 230b is further reduced. and hydrogen concentration can be reduced. The impurities removed by the heat treatment include impurities having a bond between hydrogen and carbon, impurities having a bond between hydrogen and oxygen, and the like. Further, by continuously performing heat treatment and film formation without exposing to the outside air, it is possible to prevent impurities such as hydrogen from entering the oxide 230 again.

The oxide film that becomes oxide 230c can be formed by sputtering, CVD, MBE, or PLD.
This can be carried out using a method such as a method, an ALD method, or the like. Using the same film formation method as the oxide film 230A or the oxide film 230B, depending on the characteristics required for the oxide film that becomes the oxide 230c,
An oxide film that becomes the oxide 230c may be formed. As the oxide film that becomes the oxide 230c, an In--Ga--Zn oxide or an oxide that does not contain In can be used. I
As the oxide that does not contain n, Ga--Zn oxide, gallium oxide, or the like can be used. Further, as the oxide film serving as the oxide 230c, a laminated structure of an In--Ga--Zn oxide and an oxide not containing In may be used. As the oxide film to become the oxide 230c, In:Ga:Zn=1:3:4 [atomic ratio], 4:2:4.1 [atomic ratio], Ga:Zn=2:1 by sputtering method. A film is formed using a target with [atomic ratio] or Ga:Zn=2:5 [atomic ratio]. In this embodiment, the oxide film serving as the oxide 230c is formed by a sputtering method using a target with an atomic ratio of 1:3:4.

Further, the oxide film that becomes the oxide 230c may have a laminated structure consisting of a first oxide film and a second oxide film on the first oxide film, and the oxide film used to form the oxide film 230B may have a stacked structure. The first oxide film may be formed using a target similar to the target, and the second oxide film may be formed using a target similar to the target used to form the oxide film 230A.

It is preferable to form an oxide film to become the oxide 230c while heating the substrate. At this time, by setting the substrate temperature to 300° C. or higher, oxygen vacancies in the oxide films that become the oxides 230a, 230b, and 230c can be reduced. Further, for example, the film may be formed at the same temperature as the film forming temperature of the insulator 250, which will be described later. Further, by forming the film while heating the substrate in this manner, it is possible to improve the crystallinity of the oxide films that become the oxide 230a, the oxide 230b, and the oxide 230c.

In particular, when forming an oxide film to become the oxide 230c, some of the oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Therefore, the proportion of oxygen contained in the sputtering gas for the oxide film forming the oxide 230c may be 70% or more, preferably 80% or more, and more preferably 100%. Furthermore, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

Next, the oxide film that will become the oxide 230c is processed into an island shape to form the oxide 230c (see FIG. 6). As shown in FIG. 6, oxide 230c is different from oxide 230a and oxide 230.
Process to cover b. Note that the oxide 230c may be formed using a lithography method. Moreover, the processing can use a dry etching method or a wet etching method. Processing by dry etching is suitable for microfabrication. For details on the formation of the oxide 230c, refer to the method for forming the oxide 230a and the oxide 230b.

Next, it is preferable to perform heat treatment before forming the insulator 250. Heat treatment is 100℃
The above temperature may be 400°C or lower, for example, 200°C. Alternatively, the insulator 250
It is preferable to perform the process at the same temperature as the film forming temperature. Here, the film-forming temperature is not limited to the substrate temperature during film-forming, but also includes the set temperature of the film-forming apparatus. For example, when forming the insulator 250 at 350° C., the heat treatment is preferably performed at 350° C. The heat treatment is preferably performed under reduced pressure, and may be performed, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuation using a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber is 1×10 ⁻² Pa
Below, it is preferably 1×10 ⁻³ Pa or less.

Next, an insulator 250 is formed to cover the oxide 230c (see FIG. 6). Insulator 25
0 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulator 250, it is preferable to form a film of silicon oxide, hafnium oxide, gallium oxide, or the like using an ALD method. For example, insulator 250
For this purpose, a laminated film of silicon oxide and gallium oxide on silicon oxide may be used. Note that the film forming temperature when forming the insulator 250 is 300° C. or higher and lower than 450° C., preferably 30° C. or higher and lower than 450° C.
The temperature is preferably 0°C or higher and lower than 400°C, particularly around 350°C. For example, insulator 250
By forming a film at 350° C., an insulator containing few impurities can be formed.

Note that oxygen can be introduced into the insulator 250 by exciting oxygen with microwaves to generate high-density oxygen plasma, and by exposing the insulator 250 to the oxygen plasma.

Further, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and hydrogen concentration of the insulator 250 can be reduced.

Next, a dummy gate film that will become the dummy gate 262A is formed on the insulator 250.

The dummy gate film that becomes the dummy gate 262A is processed and used as a dummy gate. A dummy gate is a temporary gate electrode. That is, a temporary gate electrode is formed by processing a dummy gate film that will become the dummy gate 262A, and in a later step, the dummy gate is removed and a gate electrode made of a conductive film or the like is formed instead. Therefore, it is preferable to use a film that can be easily microfabricated and easily removed as the dummy gate film serving as the dummy gate 262A.

The dummy gate film that becomes the dummy gate 262A is formed by sputtering method, CVD method,
This can be performed using an MBE method, a PLD method, an ALD method, or the like. For example, an insulator, a semiconductor, or a conductor can be used. Specifically, silicon such as polysilicon, microcrystalline silicon, amorphous silicon, or a metal film such as aluminum, titanium, or tungsten may be used. Alternatively, using a coating method, a film containing carbon, SOG (Spin
On Glass), a resin film, etc. may be formed. Examples include photoresist, polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate or acrylic. By forming SOG and resin film by coating method,
The surface of the dummy gate film can be made flat. By flattening the surface of the dummy gate film in this manner, microfabrication is facilitated and removal is also facilitated.

The dummy gate needs to protect the oxide 230 from the dopant when the dopant is added, which will be described later. For this reason, it is preferable that the dummy gate film serving as the dummy gate 262A has sufficient hardness. As such a dummy gate film, for example, a film containing carbon is suitable.

Further, the dummy gate film serving as the dummy gate 262A can be made into a multilayer film using different film types. For example, the dummy gate film serving as the dummy gate 262A can have a two-layer structure including a conductive film and a resin film formed on the conductive film. When the dummy gate film has such a structure, the conductive film may function as a stopper film for the CMP process, for example, in a later CMP process. Alternatively, it may be possible to detect the end point of CMP processing,
It may be possible to reduce processing variations.

Next, the dummy gate film that will become the dummy gate 262A is etched by a lithography method to form the dummy gate 262A (see FIG. 7). The dummy gate 262A is
It is formed so that at least a portion thereof overlaps with the conductor 205 and the oxide 230.

Further, after forming the dummy gate 262A, heat treatment may be performed to harden the dummy gate 262A. In particular, when the dummy gate 262A is shaped to have a high aspect ratio, deformation of the dummy gate 262A can be prevented by hardening the dummy gate 262A.

Next, using the dummy gate 262A as a mask, a dopant 257 is added to the oxide 230b and the oxide 230c (see FIG. 7). As a result, the layer 253a and the layer 25 containing the dopant 257 are formed in a region of the oxide 230b that does not overlap with the dummy gate 262A.
3b is formed. In this way, the distance between the layer 253a and the layer 253b, that is, the channel length, can be controlled by the length of the dummy gate 262A in the channel length direction.

As a method for adding the dopant 257, an ion implantation method in which ionized raw material gas is added after mass separation, an ion doping method in which ionized raw material gas is added without mass separation, a plasma immersion ion implantation method, etc. are used. be able to. When performing mass separation, the ion species to be added and their concentrations can be strictly controlled. On the other hand, when mass separation is not performed, ions can be added at a high concentration in a short time. Alternatively, an ion doping method may be used in which clusters of atoms or molecules are generated and ionized.
Note that the dopant may also be referred to as an ion, donor, acceptor, impurity, element, or the like.

As the dopant 257, an element that forms the above-mentioned oxygen vacancies, an element that combines with oxygen vacancies, or the like may be used. Such an element typically includes boron or phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gas, etc. may be used. Further, typical examples of rare gas elements include helium, neon, argon, krypton, and xenon. Also, metals such as aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum. One or more metal elements selected from among the elements may be added. Among those mentioned above, boron and phosphorus are preferable as the dopant 257. When boron or phosphorus is used as the dopant 257, equipment for amorphous silicon or low-temperature polysilicon production lines can be used, so capital investment can be suppressed.

In particular, it is preferable to use an element that easily forms an oxide as the dopant 257.
Such elements typically include boron, phosphorus, aluminum, magnesium, and the like.

As the raw material gas used when adding the dopant 257, a gas containing the above impurity element can be used. When boron is supplied, typically B ₂ H ₆ gas, BF ₃ gas, or the like can be used. Further, when supplying phosphorus, PH ₃ gas can typically be used. Alternatively, a mixed gas obtained by diluting these source gases with a rare gas may be used.

Other raw material gases include CH ₄ , N ₂ , NH ₃ , AlH ₃ , AlCl ₃ , SiH ₄ ,
_Si2H6 , _F2 , HF, _{H2 ,} rare gas, etc. can be used. Further, the ion source is not limited to gas, and may be a vaporized liquid or solid.

Addition of the dopant 257 can be controlled by setting conditions such as accelerating voltage and dose amount in consideration of the composition, density, thickness, etc. of the insulator 250 and the oxide 230b. In particular, it is preferable to apply sufficient energy so that the dopant 257 can penetrate through the portion of the insulator 250 that is not in contact with the dummy gate 262A.

It is preferable that the amount of dopant 257 added is greater than the amount of dopant 258 added, which will be described later. Thereby, a layer 253 into which elements are implanted at a higher concentration than the layer 252 can be formed. Further, the dopant 257 may be added at a higher acceleration voltage than the dopant 258. Thereby, the layer 253 in which the elements are distributed deeper than the layer 252 can be formed.

Furthermore, in FIG. 7, the dopant 257 is added approximately perpendicularly to the upper surface of the insulator 214;
The present invention is not limited to this, and the dopant 257 may be added at an angle with respect to the upper surface of the insulator 214. By adding the dopant at an angle with respect to the upper surface of the insulator 214,
It becomes easy to form the layer 253a and the layer 253b in a part of the region overlapping with the dummy gate 262A.

Further, in the manufacturing method of this embodiment, the dopant 257 is added to the oxide 230 via the insulator 250. By using this manufacturing method, the dopant 257 is also applied to the insulator 250.
is added. That is, both the oxide 230 and the insulator 250 have the element included in the dopant 257. Also, if the insulator 250 has excess oxygen, the dopant 257
In some cases, the diffusion of excess oxygen to the outside can be suppressed. Further, the oxide 230a and the insulator 224 provided below the oxide 230b, the oxide 230c, and the insulator 250
A dopant 257 may also be added to the insulator 222. Therefore, oxide 23
0a, the insulator 224 and the insulator 222 may have an element included in the dopant 257.

Next, a portion of the dummy gate 262A is removed (hereinafter sometimes referred to as slimming processing) to form a dummy gate 262B (see FIG. 8). Dummy gate 262B
The shape is like a scaled-down dummy gate 262B. Therefore, as shown in FIG. 8B, part of the region where the oxide 230b and oxide 230c layers 253 are not formed can be exposed from the dummy gate 262B. A part of the region where the layer 253 of the oxide 230b is not formed becomes a layer 252 by adding a dopant 258 in a later step.
In other words, the region of the oxide 230b overlapping with the dummy gate 262B becomes the region 234 that functions as a channel formation region.

As the slimming process, for example, an ashing process using oxygen in a radical state (oxygen radicals) can be applied. However, the slimming process is performed using the dummy gate 262A.
It is not necessary to limit the process to the above-mentioned ashing process as long as the process can process the process into a finer pattern. For example, plasma treatment or heat treatment in an atmosphere containing oxygen, treatment in which ultraviolet light is irradiated under an ozone atmosphere, dry etching treatment, wet etching treatment, etc. can be used. Note that since the channel length of the transistor 200 is determined by the dummy gate 262B, it is desirable to apply a process with good controllability as the slimming process.

By slimming processing, the length of the dummy gate 262A in the A1-A2 direction is reduced to a line width that is below the resolution limit of the exposure device, for example, 1/2 or less of the resolution limit, preferably 1/3 or less. is possible. As a result, for example, the channel length of the transistor 200 can be set to 1
The thickness can be 15 nm or more and 40 nm or less, more preferably 15 nm or more and 40 nm or less.
By shortening the channel length in this manner, the on-current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved.

Next, a dopant 258 is added to the oxide 230b and the oxide 230c using the dummy gate 262B as a mask (see FIG. 9). As a result, layers 252a and 252b containing the dopant 258 are formed in regions of the oxide 230b and the oxide 230c that do not overlap with the dummy gate 262B and where the layer 253 is not formed. In this way, the distance between the layer 252a and the layer 252b, that is, the channel length of the transistor 200, can be controlled by the width of the dummy gate 262B in the A1-A2 direction.

The method for adding the dopant 258 can be the same as the method for adding the dopant 257 described above. At this time, the dopant 258 is applied to the dummy gate 262 of the insulator 250.
It is preferable to apply sufficient energy so that the portion that is not in contact with B can be penetrated.
Further, as the dopant 258, similarly to the dopant 257, an element that forms the above-mentioned oxygen vacancies or an element that combines with the oxygen vacancies may be used. However, dopant 258
It is preferable that the amount of dopant 257 added is smaller than the amount of dopant 257 added.

Furthermore, in FIG. 9, the dopant 258 is added approximately perpendicularly to the upper surface of the insulator 214;
The present invention is not limited to this, and the dopant 258 may be added at an angle with respect to the upper surface of the insulator 214. By adding the dopant at an angle with respect to the upper surface of the insulator 214,
The layer 252a and the layer 252b may also be formed in a part of the region overlapping with the dummy gate 262B.

Further, in the manufacturing method of this embodiment, the dopant 258 is added to the oxide 230 via the insulator 250. By using this manufacturing method, the dopant 258 is also applied to the insulator 250.
is added. That is, both the oxide 230b and the insulator 250 are doped with the dopant 258.
It has elements contained in. Additionally, if the insulator 250 has excess oxygen, the dopant 25
8, it may be possible to suppress the diffusion of excess oxygen to the outside. In addition, dopant 258
is also added to layer 253, so layer 253 may have elements included in dopant 258. Further, the dopant 258 may also be added to the oxide 230a, the insulator 224, and the insulator 222 provided below the oxide 230b, the oxide 230c, and the insulator 250. Therefore, the oxide 230a, the insulator 224, and the insulator 222 may have elements included in the dopant 258.

As described above, by forming the layer 252 and the layer 253 using the dummy gates 262A and 262B as masks, the conductor 260 to be formed in a later step can be
It can be self-aligned between layer 53a and layer 253b and self-aligned over layer 252a and layer 252b.

Note that heat treatment may be performed after adding the dopant 257 or after adding the dopant 258. Through the heat treatment, hydrogen contained in the region 234 functioning as a channel formation region may be captured by oxygen vacancies contained in the layer 253. As a result, transistor 2
It is possible to provide stable electrical characteristics to 00 and improve reliability. In addition, the heat treatment is
It may be performed in subsequent steps.

Next, an insulating film 266A is formed to cover the insulator 250 and the dummy gate 262B (see FIG. 10). The insulating film 266A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

As the insulating film 266A, it is preferable to use an insulating film that has a function of suppressing diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to form an aluminum oxide film by a sputtering method. Oxygen can be injected into the insulator 250 by forming an aluminum oxide film using a gas containing oxygen by a sputtering method. That is, insulator 250 can have excess oxygen.

Further, as the insulating film 266A, aluminum oxide may be formed while heating the substrate at a high temperature. The substrate heating temperature when forming the insulating film 266A is 200°C or higher, preferably 250°C.
℃ or higher, more preferably 350℃ or higher. At this time, by forming aluminum oxide using the ALD method before forming the insulating film 266A, the dummy gate 262B will not be deformed when the insulating film 266A is formed at the above temperature. can be prevented.

In a later step, the dummy gate 262B and the portion of the insulating film 266A that is in contact with the dummy gate 262B are removed to form an opening 263. In other words, the size of the opening 263 can be controlled by the thickness of the insulating film 266A. Here, the layer 252 and the layer 253 are formed in self-alignment with respect to the arrangement of the dummy gate 262B. The size of the opening 263 can be controlled centering on the position of the dummy gate 262B. Therefore, by enlarging the opening 263, the conductor 260 can be overlapped with the layer 252. Furthermore, by enlarging the opening 263, the conductor 260 can be overlapped with the layer 253. In this way, between the channel forming region of the oxide 230 and the source or drain region,
Formation of an offset region can be prevented, and the effective channel length can be prevented from becoming larger than the width of the conductor 260. Thereby, the on-state current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved. Note that the size of the opening 263, that is, the size of the overlapping region of the transistor 200, can be appropriately set according to the electrical characteristics required of the transistor 200.

Next, the insulating film 28 is placed on the insulator 250, the insulating film 266A, and the dummy gate 262B.
A film of 0A is formed (see FIG. 10). The insulating film 280A is formed by sputtering method or CVD.
This can be carried out using a method such as a method, an MBE method, a PLD method, or an ALD method.

Next, parts of the insulating film 280A, the insulating film 266A, and the dummy gate 262B are removed until part of the dummy gate 262B is exposed, forming the insulator 280, the insulator 266B, and the dummy gate 262 (see FIG. (See 11). It is preferable to use CMP processing to form the insulator 280, the insulator 266B, and the dummy gate 262.

Further, as described above, by making the dummy gate 262B a film with a two-layer structure in which a conductive film and a resin film are formed on the conductive film, the conductive film can be used as a stopper film for the CMP process in the CMP process. It may work. Alternatively, the conductive film may make it possible to detect the end point of CMP processing, and it may become possible to reduce variations in the height of the dummy gate 262. As shown in FIG. 11(B), the top surface of the dummy gate 262, the insulator 266B, and the insulator 2
The upper surfaces of 80 substantially match.

Next, the dummy gate 262 and the portion of the insulating film 266A exposed from the insulator 280 are removed to form an opening 263 (see FIG. 12). Dummy gate 262 and insulating film 266
Removal of A can be performed using wet etching, dry etching, ashing, or the like using the insulator 280 as a mask. Alternatively, a plurality of the above processes may be combined as appropriate. For example, wet etching treatment may be performed after ashing treatment. At this time, it is preferable that the insulator 250 functions as an etching stopper. An insulator 266 is formed by removing a portion of the insulating film 266A. By removing a portion of the dummy gate 262 and the insulating film 266A, the insulator 25 is removed from the opening 263.
Part of the surface of 0 is exposed.

Note that the insulator 250 does not necessarily have to function as an etching stopper. For example, the exposed portion of the insulator 250 from the insulator 280 may be removed by the etching process, and then an insulator functioning as a gate insulating film may be formed so as to fill the opening 263.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. By heat treatment, impurities such as water and hydrogen in the insulator 250, the oxide 230a, and the oxide 230b can be removed through the opening 263. For example, heat treatment may be performed at a temperature of 600° C. in a nitrogen atmosphere.

Furthermore, before forming the conductive film 260Aa and the conductive film 260Ab, one or more methods selected from ion implantation, ion doping, plasma treatment, and plasma immersion ion implantation are used to form an oxide. Oxygen may be added to 230b, oxide 230c, and insulator 280. At this time, oxygen can be added to the oxide 230b, the oxide 230c, and the insulator 280 with good control by using an ion implantation method in which the ionized source gas is added after mass separation, which is preferable.

Next, a conductive film 260Aa and a conductive film 260Ab are formed so as to fill the opening 263 (see FIG. 13). The conductive film 260Aa and the conductive film 260Ab can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.
For example, it is preferable to use the CVD method. In this embodiment, a conductive film 260Aa is formed using an ALD method, and a conductive film 260Ab is formed using a CVD method.

Next, the conductive film 260Aa and the conductive film 260Ab are removed from the insulator 280 by CMP processing.
By polishing until the conductor 260 (conductor 260a and conductor 26
0b) (see FIG. 14).

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and hydrogen concentration of the insulator 280 can be reduced. Alternatively, it is preferable to perform heat treatment before forming an insulating film that will become the insulator 274. The heat treatment may be performed at a temperature of 100°C or more and 400°C or less, for example, 200°C. Alternatively, it is preferable to perform the step at the same temperature as the film forming temperature of the insulating film. Here, the film-forming temperature is not limited to the substrate temperature during film-forming, but also includes the set temperature of the film-forming apparatus. For example, the insulating film is
When forming a film at .degree. C., the heat treatment is preferably performed at 250.degree. The heat treatment is preferably performed under reduced pressure, and may be performed, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by evacuation using a turbo molecular pump or the like. In a vacuum atmosphere, the pressure in the processing chamber is 1×1
It may be 0 ⁻² Pa or less, preferably 1×10 ⁻³ Pa or less.

Next, an insulating film that will become the insulator 274 is formed on the insulator 280 (see FIG. 14). The insulating film that becomes the insulator 274 can be formed by sputtering method, CVD method, MBE method, PLD method,
Alternatively, it can be performed using an ALD method or the like. As the insulating film serving as the insulator 274, it is preferable to form an aluminum oxide film by, for example, a sputtering method. By forming an aluminum oxide film by a sputtering method, hydrogen included in the insulator 280 can be suppressed from diffusing into the oxide 230 in some cases.

Next, heat treatment may be performed. The heat treatment conditions described above can be used for the heat treatment. Through the heat treatment, the moisture concentration and hydrogen concentration of the insulator 280 can be reduced.

Next, an insulator that will become the insulator 281 may be formed over the insulator 274. The insulating film that becomes the insulator 281 can be formed by sputtering, CVD, MBE, PLD, or ALD.
This can be done using a method or the like (see FIG. 14).

Next, layer 253a is applied to insulator 266, insulator 280, insulator 274, and insulator 281.
and forming an opening reaching layer 253b. The opening may be formed using a lithography method.

Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The conductive film can be formed by sputtering method, CVD method, MBE method, PL
This can be performed using the D method, the ALD method, or the like. As the insulating film serving as the insulator 241, it is preferable to use an insulating film that has a function of suppressing permeation of oxygen. For example, ALD
It is preferable to form the aluminum oxide film by a method. Alternatively, a silicon nitride film may be formed using an ALD method or a CVD method. When forming a silicon nitride film using the ALD method, a precursor containing silicon and halogen or an aminosilane precursor can be used. As a precursor containing silicon and halogen, SiCl ₄ , Si
_H2Cl2 , _Si2Cl6 , _{Si3Cl8 , etc.} can be used _. Moreover, monovalent, divalent, or trivalent aminosilanes can be used as precursors of aminosilanes. Furthermore, ammonia or hydrazine can be used as the nitriding gas. Further, the anisotropic etching may be performed by, for example, a dry etching method. By configuring the side wall portion of the opening in this manner, it is possible to suppress permeation of oxygen from the outside and prevent oxidation of the conductor 240a and the conductor 240b to be formed next. In addition, the conductor 240a and the conductor 24
0b can prevent impurities such as water and hydrogen from diffusing to the outside.

Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. Conductor 240a
The conductive film serving as the conductor 240b preferably has a stacked structure including a conductor having a function of suppressing diffusion of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. Conductor 24
The conductive film that becomes 0 can be formed by sputtering method, CVD method, MBE method, PLD method or AL.
This can be done using the D method or the like.

Next, by performing a CMP process, part of the conductive film that will become the conductor 240a and the conductor 240b is removed, and the insulator 281 is exposed. As a result, since the conductive film remains only in the opening, the conductor 240a and the conductor 240b with flat upper surfaces can be formed (
See Figure 1. ). Note that part of the insulator 281 may be removed by the CMP process.

Through the above steps, a semiconductor device including the transistor 200 shown in FIG. 1 can be manufactured. As shown in FIGS. 5 to 14, a transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.

According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided.
Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a highly productive semiconductor device can be provided.

<Modified example of semiconductor device>
15 to 19, a semiconductor device including a transistor 200 according to one embodiment of the present invention and a method for manufacturing the semiconductor device, which is different from that shown in <Structure example of semiconductor device> above, will be described below. An example will be explained.

In addition, in FIGS. 15 to 19, (A) in each figure shows a top view. Also, (B) in each figure
1 is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line along line A1-A2 shown in FIG. In addition, (C) in each figure is (A) in each figure.
) is a cross-sectional view corresponding to the portion indicated by the dashed-dotted line along A3-A4, and is also a cross-sectional view in the channel width direction of the transistor 200. Further, (D) in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in (A) of each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of (A) in each figure, some elements are omitted for clarity of illustration.

Note that in the semiconductor devices shown in FIGS. 15 to 19, structures having the same functions as the structures configuring the semiconductor device (see FIG. 1) shown in <Configuration Example of Semiconductor Device> are given the same reference numerals. Note that in this item, as the constituent material of the transistor 200, the material described in detail in <Structure Example of Semiconductor Device> can be used.

The transistor 200 illustrated in FIG. 15 differs from the transistor 200 illustrated in FIG. 1 in that it does not include an insulator 266 and an insulator 280 and an insulator 250 are in contact with each other.

The semiconductor device shown in FIG. 15 is manufactured using the same method as the semiconductor device shown in FIG. 1 until the dummy gate 262B is formed and the dopant 258 is added. Therefore, the method for manufacturing a semiconductor device according to FIGS. 5 to 9 can be considered.

Next, a film that will become the dummy film 267A is formed to cover the insulator 250 and the dummy gate 262B. The film that will become the dummy film 267A can be formed by sputtering method, CVD method, MB
The film can be formed using the E method, PLD method, ALD method, or the like. Here, dummy film 2
Since the film that becomes 67A will be removed eventually, it is preferable to use a film that is easy to microfabricate and also easy to remove. For example, an insulator that can be used for the insulator 266 may be used. However, it is preferable to use a material that can provide a sufficiently large etching rate for the insulator 280 and the insulator 250 when removed in a later step.

Next, the film that will become the dummy film 267A is subjected to anisotropic etching to form the dummy film 267A, leaving only the portion in contact with the side wall of the dummy gate 262B. (See Figure 16.) The anisotropic etching may be performed using, for example, a dry etching method.

In a later process, the dummy gate 262B and the dummy film 267A are removed to form the opening 263.
form. In other words, the size of the opening 263 can be controlled by the thickness of the dummy film 267A. Here, the layer 252 and the layer 253 are formed in self-alignment with respect to the arrangement of the dummy gate 262B. The size of the opening 263 can be controlled centering on the position of the dummy gate 262B. Therefore, by enlarging the opening 263, the conductor 2
60 can be overlapped with layer 252. Furthermore, by enlarging the opening 263, the conductor 260 can be overlapped with the layer 253. In this way, an offset region is prevented from being formed between the channel forming region of the oxide 230 and the source or drain region, and the effective channel length is prevented from becoming larger than the width of the conductor 260. be able to. Thereby, the on-state current of the transistor 200 can be increased, the S value can be improved, and the frequency characteristics can be improved. Note that the size of the opening 263, that is, the size of the overlapping region of the transistor 200, can be appropriately set according to the electrical characteristics required of the transistor 200.

Next, a process similar to that shown in FIG. 10 is performed to form an insulating film 280A over the insulator 250, dummy film 267A, and dummy gate 262B.

Next, a process similar to that in FIG. 11 is performed to remove parts of the insulating film 280A, dummy film 267A, and dummy gate 262B until part of the dummy gate 262B is exposed, and A film 267 and a dummy gate 262 are formed (see FIG. 17).
). It is preferable to use CMP processing to form the insulator 280, dummy film 267, and dummy gate 262.

Next, the dummy gate 262 and the dummy film 267 are removed to form an opening 263 (see FIG. 18). The dummy gate 262 and the dummy film 267 can be removed using wet etching, dry etching, ashing, or the like using the insulator 280 as a mask. Alternatively, a plurality of the above processes may be combined as appropriate. For example, wet etching treatment may be performed after ashing treatment. By removing dummy gate 262 and dummy film 267, insulator 250 is exposed from opening 263.

Here, it is preferable to remove the dummy gate 262 and the dummy film 267 using the insulator 280 and the insulator 250 as etching stoppers. In this process, the dummy gate 26
By removing 2 and the dummy film 267, the opening 263 can be formed without excessively etching the sidewall of the opening 263.

The subsequent steps in the method for manufacturing the semiconductor device shown in FIG. 15 are the same as the method for manufacturing the semiconductor device shown in FIG. Therefore, the method for manufacturing a semiconductor device according to FIGS. 13 and 14 can be referred to.

The transistor 200 shown in FIG. 19 differs from the transistor 200 shown in FIG.
different from.

In the description of the method for manufacturing the semiconductor device shown in FIG. 7, the side surface of the dummy gate 262A was approximately perpendicular to the top surface of the oxide 230b. On the other hand, dummy gate 262A
The angle between the side surface of the oxide 230b and the top surface of the oxide 230b is less than 90°, in other words, the dummy gate 262
When the cross-sectional shape of A has a forward tapered shape, the cross-sectional shapes of the insulator 266 and the insulator 280 have a reverse tapered shape as shown in FIG. Further, the cross-sectional shape of the conductor 260 becomes a forward tapered shape.

As described above, the structure, method, etc. shown in this embodiment can be used in appropriate combination with the structure, method, etc. shown in other embodiments.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device will be described with reference to FIGS. 20 and 21.

[Storage device 1]
FIG. 20 shows an example of a semiconductor device (memory device) using a capacitor that is one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that as the transistor 200, the transistor 200 described in the previous embodiment or the like can be used.

The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a small off-state current, it is possible to retain stored contents for a long period of time by using the transistor 200 in a memory device. In other words, since a refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

In the semiconductor device shown in FIG. 20, a wiring 1001 is electrically connected to the source of the transistor 300, and a wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1004 is electrically connected to the first gate of the transistor 200.
006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. .

Furthermore, the memory device shown in FIG. 20 can be arranged in a matrix to form a memory cell array.

<Transistor 300>
The transistor 300 is provided on a substrate 311 and includes a conductor 3 that functions as a gate electrode.
16, it has an insulator 315 that functions as a gate insulator, a semiconductor region 313 made of a part of the substrate 311, a low resistance region 314a that functions as a source region or a drain region, and a low resistance region 314b. The transistor 300 may be either a p-channel type or an n-channel type.

Here, the transistor 300 shown in FIG. 20 has a semiconductor region 313 (where a channel is formed) (
(a part of the substrate 311) has a convex shape. Furthermore, a conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 in between. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it utilizes a convex portion of a semiconductor substrate. Note that an insulator may be provided in contact with the upper portion of the convex portion to function as a mask for forming the convex portion. Furthermore, although a case is shown in which a portion of the semiconductor substrate is processed to form a convex portion, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

Note that the transistor 300 illustrated in FIG. 20 is an example, and the structure thereof is not limited, and an appropriate transistor may be used depending on the circuit configuration and driving method.

<Capacitive element 100>
Capacitive element 100 is provided above transistor 200. The capacitive element 100 has a first
The conductor 110 functions as an electrode, the conductor 120 functions as a second electrode, and the insulator 130 functions as a dielectric.

Further, for example, the conductor 112 provided over the conductor 240 and the conductor 110 can be formed at the same time. Note that the conductor 112 functions as a plug or wiring that is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

Although the conductor 112 and the conductor 110 have a single-layer structure in FIG. 20, they are not limited to this structure, and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesiveness to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

The insulator 130 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. etc., and can be provided as a laminate or a single layer.

For example, the insulator 130 preferably has a stacked structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material. With this configuration, the capacitor 100 can secure sufficient capacitance by having an insulator with a high dielectric constant (high-k), and can improve dielectric strength and increase capacitance by having an insulator with a high dielectric strength. Electrostatic damage to the element 100 can be suppressed.

Insulators of high dielectric constant (high-k) materials (materials with high relative permittivity) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, and oxynitrides containing aluminum and hafnium. , an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, carbon and nitrogen. Examples include added silicon oxide, silicon oxide with pores, and resin.

<Wiring layer>
A wiring layer including an interlayer film, wiring, plug, etc. may be provided between each structure. Further, a plurality of wiring layers can be provided depending on the design. Here, for a conductor having a function as a plug or a wiring, a plurality of structures may be given the same reference numeral. Further, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked and provided as interlayer films over the transistor 300. In addition, the insulator 320,
A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 322, the insulator 324, and the insulator 326. Note that the conductor 328 and the conductor 330 function as a plug or wiring.

Furthermore, the insulator that functions as an interlayer film may function as a flattening film that covers the uneven shape below it. For example, the top surface of the insulator 322 may be chemically mechanically polished (
The surface may be flattened by a flattening process using a CMP method or the like.

A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 20, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order.
Further, a conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring.

Similarly, a conductor 218, a conductor (conductor 205) forming the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 has a function as a plug or wiring that is electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided on the conductor 120 and the insulator 130.

Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

For example, by using a material with a low dielectric constant as the insulator that functions as an interlayer film, parasitic capacitance occurring between wirings can be reduced. Therefore, the material should be selected depending on the function of the insulator.

For example, it is preferable that the insulator 150, the insulator 212, the insulator 352, the insulator 354, etc. have an insulator with a low dielectric constant. For example, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with vacancies. Alternatively, it is preferable to have a resin or the like. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with holes. It is preferable to have a laminated structure of and a resin. Silicon oxide and silicon oxynitride are thermally stable, so by combining them with resin, a laminated structure that is thermally stable and has a low dielectric constant can be obtained. As the resin, for example, polyester,
Examples include polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic.

In addition, one or both of the conductor 112, the insulator 130 provided on the conductor 120, and the insulator 150 has a resistivity of 1.0×10 ¹² Ωcm or more and 1.0×10 ¹⁵ Ωc.
m or less, preferably from 5.0×10 ¹² Ωcm to 1.0×10 ¹⁴ Ωcm, more preferably from 1.0×10 ¹³ Ωcm to 5.0×10 ¹³ Ωcm. By using one or both of the insulator 130 and the insulator 150 as an insulator having the above-mentioned resistivity, the insulator maintains its insulating properties and can be used for the transistor 200,
Dispersing charges accumulated between the transistor 300, the capacitor 100, and wiring such as the conductor 112 and the conductor 120, and suppressing characteristic defects and electrostatic discharge damage of the transistor and the memory device including the transistor due to the charge. is possible and preferred. As such an insulator, silicon nitride or silicon nitride oxide can be used.

Furthermore, as an insulator having the resistivity as described above, an insulator 140 may be provided below the conductor 112. In this case, the insulator 140 is formed on the insulator 281, openings are formed in the insulator 140, the insulator 281, the insulator 274, the insulator 280, the insulator 244, the insulator 254, etc. The insulator 241 and the conductor 240 electrically connected to the transistor 200, the conductor 218, and the like may be formed. The insulator 140 is the insulator 130,
Alternatively, the same material as the insulator 150 can be used.

Further, the electrical characteristics of a transistor including an oxide semiconductor can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, as the insulator 210, the insulator 350, and the like, an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used.

Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include:
Insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, either in a single layer or in layers. Just use it.
Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen,
Metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.

Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver,
A material containing one or more metal elements selected from gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. In addition, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus,
Silicides such as nickel silicide may also be used.

For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1
As the material 12, a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material formed of the above-mentioned materials can be used in a single layer or in a stacked manner. It is preferable to use high melting point materials such as tungsten and molybdenum, which have both heat resistance and conductivity.
Preferably, tungsten is used. Alternatively, it is preferable to use a low resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low resistance conductive material.

<<Wiring or plug in layer provided with oxide semiconductor>>
Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region is provided near the oxide semiconductor in some cases. In that case, it is preferable to provide an insulator having barrier properties between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region.

For example, in FIG. 20, an insulator 241 may be provided between an insulator 224 and a conductor 240. In particular, insulator 241 includes insulator 222 sandwiching insulator 224 having an excess oxygen region.
and the insulator 266 are preferably provided. Insulator 241 and insulator 222
, and the insulator 266 are provided in contact with each other, so that the insulator 224 can be sealed with an insulator having barrier properties. Furthermore, the insulator 241 is the insulator 28
0 and a part of the insulator 281. The insulator 241 is the insulator 28
0 and the insulator 281, diffusion of oxygen and impurities can be further suppressed.

In other words, by providing the insulator 241, excess oxygen contained in the insulator 224 is transferred to the conductor 241.
0 absorption can be suppressed. Further, by providing the insulator 241, hydrogen, which is an impurity, can be suppressed from diffusing into the transistor 200 via the conductor 240.

Note that as the insulator 241, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen. For example, it is preferable to use aluminum oxide or hafnium oxide. In addition, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can also be used.

The above is a description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[Storage device 2]
FIG. 21 shows an example of a memory device using a semiconductor device that is one embodiment of the present invention. Figure 21
The memory device shown in FIG. 2 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in FIG.

Transistor 400 can control the second gate voltage of transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 and the second gate of the transistor 200 are connected. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and source and the voltage between the second gate and source of the transistor 400 become 0V. In the transistor 400, the drain current when the second gate voltage and the first gate voltage are 0V is very small. Negative potential can be maintained for a long time. As a result, the transistor 200 and the transistor 400
A storage device having this can retain stored contents for a long period of time.

Therefore, in FIG. 21, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Also,
The wiring 1003 is electrically connected to one of the source and drain of the transistor 200,
The wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other electrode of the capacitor 100. . The wiring 1007 is electrically connected to the source of the transistor 400, the wiring 1008 is electrically connected to the gate of the transistor 400, the wiring 1009 is electrically connected to the back gate of the transistor 400, and the wiring 1010 is electrically connected to the drain of the transistor 400. electrically connected to. Here, wiring 1006, wiring 1007, wiring 1008,
and wiring 1009 are electrically connected.

Further, the memory device shown in FIG. 21 can be arranged in a matrix to form a memory cell array, similarly to the memory device shown in FIG. 20. Note that one transistor 40
0 can control the second gate voltage of the plurality of transistors 200. Therefore, it is preferable to provide fewer transistors 400 than transistors 200.

<Transistor 400>
The transistor 400 is formed in the same layer as the transistor 200, and can be manufactured in parallel. The transistor 400 includes a conductor 460 (conductor 460a and conductor 460b) that functions as a first gate electrode, and a conductor 405 (conductor 405a and conductor 405b) that functions as a second gate electrode. An insulator 222, an insulator 224, and an insulator 450 that function as gate insulating layers, an oxide 430c having a region where a channel is formed, a layer 453a that functions as either a source or a drain, an oxide 431a, and an oxide A conductor 440 (conductor 440a and conductor 440b) is included.

In the transistor 400, the conductor 405 and the conductor 205 are in the same layer. The oxide 431a, the oxide 432a, and the oxide 230a are the same layer, and the oxide 431
b, the oxide 432b, and the oxide 230b are the same layer. Layer 453a and layer 4
53b is a layer formed in the same process as layer 253a and layer 253b. oxide 430
In c, the oxide 230c is the same layer. Insulator 450 is the same layer as insulator 250. The conductor 460 is the same layer as the conductor 260.

Note that structures formed in the same layer can be formed at the same time. For example, oxide 4
The oxide 30c can be formed by processing an oxide film that becomes the oxide 230c.

The oxide 430c functioning as the active layer of the transistor 400 has reduced oxygen vacancies and impurities such as hydrogen or water, like the oxide 230 and the like. This results in
The threshold voltage of the transistor 400 can be made larger than 0 V, the off-state current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be made very small.

<<Dicing line>>
Below, we will explain the dicing line (sometimes called a scribe line, dividing line, or cutting line) that is provided when taking out multiple semiconductor devices in chip form by dividing a large-area substrate into semiconductor elements. . As a dividing method, for example, a groove (dicing line) for dividing the semiconductor element is first formed in the substrate, and then the substrate is cut along the dicing line to divide (divide) into a plurality of semiconductor devices.

Here, for example, as shown in FIG. 21, it is preferable to design a region where the insulator 254 and the insulator 222 are in contact to form a dicing line. In other words, openings are provided in the insulator 224 in the vicinity of the memory cell having a plurality of transistors 200 and a region that will be a dicing line provided at the outer edge of the transistor 400. Further, an insulator 254 and an insulator 244 are provided to cover the side surfaces of the insulator 224.

In other words, the insulator 222 and the insulator 254 are in contact with each other at the opening provided in the insulator 224 . For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 using the same material and using the same method, adhesion can be improved. For example, it is preferable to use aluminum oxide.

With this structure, the insulator 222 and the insulator 254 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have a function of suppressing the diffusion of oxygen, hydrogen, and water, the substrate is divided into each circuit region in which the semiconductor element described in this embodiment is formed. As a result, even if the semiconductor substrate is processed into a plurality of chips, impurities such as hydrogen or water can be prevented from entering from the side surface of the divided substrate and diffusing into the transistors 200 and 400.

Moreover, with this structure, excess oxygen in the insulator 224 is transferred to the insulator 254 and the insulator 222.
can be prevented from spreading outside. Therefore, excess oxygen in insulator 224 is efficiently supplied to transistor 200 or the oxide in which the channel in transistor 400 is formed. The oxygen can reduce oxygen vacancies in the oxide in which the channel of the transistor 200 or the transistor 400 is formed. As a result, the oxide in which the channel of the transistor 200 or the transistor 400 is formed can be an oxide semiconductor with stable characteristics and low density of defect levels. In other words, variations in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and reliability can be improved.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 3)
In this embodiment, a transistor using an oxide semiconductor (hereinafter sometimes referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are applied, with reference to FIGS. 22 and 23. A storage device (hereinafter sometimes referred to as an OS memory device) will be explained. An OS memory device is a storage device that includes at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small,
OS memory devices have excellent retention characteristics and can function as non-volatile memory.

<Example of storage device configuration>
FIG. 22A shows an example of the configuration of an OS memory device. The storage device 1400 includes the peripheral circuit 1
411 and a memory cell array 1470. The peripheral circuit 1411 is a row circuit 142
0, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

Column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying data signals read from memory cells. In addition,
The above-mentioned wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. Further, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select a row to be accessed.

The storage device 1400 is supplied with a low power supply voltage (VSS) and a peripheral circuit 14 as an external power supply voltage.
A high power supply voltage (VDD) for the memory cell array 11 and a high power supply voltage (VIL) for the memory cell array 1470 are supplied. Furthermore, control signals (CE, WE, RE), address signal ADDR, and data signal WDATA are input to the storage device 1400 from the outside. Address signal ADDR is input to the row decoder and column decoder, and WDATA is input to the write circuit.

The control logic circuit 1460 processes external input signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

The memory cell array 1470 has a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wires connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. Further, the number of wires connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, and the like.

Note that although FIG. 22A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in FIG. 22B, a memory cell array 14 is placed on a part of the peripheral circuit 1411.
70 may be provided so as to overlap. For example, a sense amplifier may be provided so as to overlap below the memory cell array 1470.

A configuration example of a memory cell applicable to the above-described memory cell MC will be described with reference to FIG. 23.

[DOSRAM]
FIGS. 23A to 23C show examples of circuit configurations of DRAM memory cells. In this specification, etc., a DRAM using one OS transistor and one capacitor type memory cell is referred to as a DOSRA.
M (Dynamic Oxide Semiconductor Random Acc
ess Memory). A memory cell 1471 illustrated in FIG. 23A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes called a front gate) and a back gate.

The first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, and the first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA.
The second terminal of the transistor M1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL, and the back gate of the transistor M1 is connected to the wiring BGL. Capacitive element C
The second terminal of A is connected to the wiring CAL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA.
It is preferable to apply a low level potential to the wiring CAL when writing and reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 23(B). Further, for example, the memory cell MC is the memory cell 14 shown in FIG. 23(C).
73, the memory cell may be configured of a transistor with a single gate structure, that is, a transistor M1 having no back gate.

When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very low. In other words, the written data can be held for a long time by the transistor M1, so the frequency of refreshing the memory cells can be reduced. Furthermore, refresh operations for memory cells can be made unnecessary. In addition, since the leakage current is very low, memory cells 1471, 1472,
Multi-level data or analog data can be held in the memory cell 1473.

Further, in a DOSRAM, if the sense amplifier is provided so as to overlap with the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and reduces the storage capacitance of the memory cell.

[NOSRAM]
FIGS. 23D to 23H show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitive element. The memory cell 1474 shown in FIG. 23(D) includes a transistor M2,
It has a transistor M3 and a capacitive element CB. Note that the transistor M2 has a front gate (sometimes simply called a gate) and a back gate. In this specification, etc., a memory device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as NOSRAM (Nonvolatile Oxide Semiconductor).
controller RAM).

The first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB, and the first terminal of the transistor M2 is connected to the first terminal of the capacitive element CB.
The second terminal of the transistor M2 is connected to the wiring WBL, the gate of the transistor M2 is connected to the wiring WOL, and the back gate of the transistor M2 is connected to the wiring BGL. Capacitive element C
The second terminal of B is connected to the wiring CAL. The first terminal of the transistor M3 is connected to the wiring R
The second terminal of the transistor M3 is connected to the wiring SL, and the second terminal of the transistor M3 is connected to the wiring SL.
The gate of No. 3 is connected to the first terminal of the capacitive element CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL is the second wiring of the capacitive element CB.
It functions as a wiring for applying a predetermined potential to the terminal. It is preferable to apply a low-level potential to the wiring CAL when writing data, during data retention, and when reading data. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

Furthermore, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a configuration in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 23(E). Further, for example, the memory cell MC may be a memory cell including a transistor with a single gate structure, that is, a transistor M2 having no back gate, like a memory cell 1476 shown in FIG. 23(F). Also, for example, memory cell MC
The wiring WBL and the wiring RBL may be combined into one wiring BIL, as in a memory cell 1477 shown in FIG. 23(G).

When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as transistor M2, the leakage current of transistor M2 can be made very low. Thereby, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cells can be reduced. Furthermore, refresh operations for memory cells can be made unnecessary. Furthermore, since the leakage current is very low, multi-value data or analog data can be held in the memory cell 1474. The same applies to memory cells 1475 to 1477.

Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of Si transistor is
It may be an n-channel type or a p-channel type. Si transistors may have higher field effect mobility than OS transistors. Therefore, a Si transistor may be used as the transistor M3 that functions as a read transistor. Further, by using a Si transistor as the transistor M3, the transistor M2 can be stacked on top of the transistor M3, so the area occupied by the memory cell can be reduced and the memory device can be highly integrated.

Furthermore, the transistor M3 may be an OS transistor. Transistors M2, M3
When OS transistors are used in the memory cell array 1470, a circuit can be configured using only n-type transistors.

Further, FIG. 23(H) shows an example of a gain cell type memory cell having three transistors and one capacitive element. A memory cell 1478 shown in FIG. 23(H) includes transistors M4 to M6 and a capacitor CC. The capacitive element CC is provided as appropriate. The memory cell 1478 is connected to the wiring BI
It is electrically connected to L, RWL, WWL, BGL, and GNDL. Wiring GNDL
is a wiring that provides a low level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and gate of the transistor M4 may be electrically connected to each other. Alternatively, transistor M4 may not have a back gate.

Note that the transistors M5 and M6 may each be an n-channel type Si transistor or a p-channel type Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured using only n-type transistors.

When the semiconductor device described in the above embodiment mode is used for the memory cell 1478, the transistor M
A transistor 200 is used as transistor M4, and a transistor 300 is used as transistor M5 and M6.
The capacitive element 100 can be used as the capacitive element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very low.

Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to the above. The arrangement or functions of these circuits and the wiring, circuit elements, etc. connected to the circuits may be changed, deleted, or added as necessary.

The structure shown in this embodiment can be used in appropriate combination with the structures shown in other embodiments.

(Embodiment 4)
In this embodiment, a chip 1200 on which a semiconductor device of the present invention is mounted will be described using FIG.
An example is shown below. A plurality of circuits (systems) are mounted on the chip 1200. In this way, system-on-chip (system-on-chip) technology is used to integrate multiple circuits (systems) onto a single chip.
It is sometimes called a System on Chip (SoC).

As shown in FIG. 24(A), the chip 1200 includes a CPU (Central Process
ssing Unit) 1211, GPU (Graphics Processing
unit) 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

The chip 1200 is provided with bumps (not shown), and as shown in FIG. 24(B),
The first part of the printed circuit board (PCB) 1201
Connect with the surface. Further, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201 and are connected to a motherboard 1203.

The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 has the DOSR shown in the previous embodiment.
AM can be used. Further, for example, the NOSRAM described in the previous embodiment can be used as the flash memory 1222.

Preferably, the CPU 1211 has multiple CPU cores. Also, GPU1212
preferably has multiple GPU cores. In addition, CPU1211 and GPU1
212 may each have a memory for temporarily storing data. Or, C.P.
A memory common to U1211 and GPU 1212 may be provided in chip 1200. The above-mentioned NOSRAM or DOSRAM can be used as the memory.
Furthermore, the GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and product-sum calculations. By providing the GPU 1212 with an image processing circuit using the oxide semiconductor of the present invention and a product-sum calculation circuit, image processing and product-sum calculation can be performed with low power consumption.

In addition, since the CPU 1211 and GPU 1212 are provided on the same chip,
The wiring between the CPU 1211 and the GPU 1212 can be shortened, and after data transfer from the CPU 1211 to the GPU 1212, data transfer between the memory of the CPU 1211 and the GPU 1212, and calculations in the GPU 1212, the wiring from the GPU 1212 to the CPU 12
11 can be transferred at high speed.

The analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit. In addition, the analog calculation unit 1213
The above-mentioned product-sum calculation circuit may be provided.

The memory controller 1214 includes a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, game controllers, and the like. Examples of such interfaces include USB (Universal Serial Bus) and HDMI (registered trademark) (H
(i.e. Definition Multimedia Interface), etc. can be used.

The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

The above circuit (system) can be formed on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

PCB 1201 provided with chip 1200 having GPU 1212, DRAM 122
1 and a motherboard 1203 provided with flash memory 1222 can be called a GPU module 1204.

Since the GPU module 1204 has a chip 1200 using SoC technology,
Its size can be reduced. Furthermore, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. In addition, a product-sum calculation circuit using the GPU 1212 can be used to create deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks ( DBN), the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module.

The structure shown in this embodiment can be used in combination with the structures shown in other embodiments as appropriate.

(Embodiment 5)
In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device described in the above embodiments can be used, for example, as a storage device of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording/playback devices, navigation systems, etc.). Applicable to In addition,
Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the previous embodiment may be used as a memory card (for example, an S
It is applied to various removable storage devices such as D card), USB memory, and SSD (solid state drive). FIG. 25 schematically shows several configuration examples of removable storage devices. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

FIG. 25(A) is a schematic diagram of a USB memory. The USB memory 1100 is housed in a housing 1101
, a cap 1102, a USB connector 1103, and a board 1104. Substrate 110
4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110.
5. Controller chip 1106 is attached. Memory chip 1 on board 1104
The semiconductor device described in the previous embodiment can be incorporated into 105 or the like.

FIG. 25(B) is a schematic diagram of the external appearance of the SD card, and FIG. 25(C) is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The board 1113 is housed in the housing 1111. For example, the substrate 11
13, a memory chip 1114 and a controller chip 1115 are attached.
By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided on the substrate 1113. Thereby, data can be read from and written to the memory chip 1114 through wireless communication between the host device and the SD card 1110. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1114 of the substrate 1113 or the like.

FIG. 25(D) is a schematic diagram of the external appearance of the SSD, and FIG. 25(E) is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. The board 1153 is housed in a housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156,
For example, a DOSRAM chip may be used. There is also a memory chip 11 on the back side of the substrate 1153.
By providing 54, the capacity of the SSD 1150 can be increased. The semiconductor device described in the previous embodiment can be incorporated into the memory chip 1154 of the substrate 1153 or the like.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

(Embodiment 6)
A semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. FIG. 26 shows a specific example of an electronic device including a processor, such as a CPU or GPU, or a chip according to one embodiment of the present invention.

<Electronic equipment/systems>
A GPU or a chip according to one embodiment of the present invention can be installed in various electronic devices.
Examples of electronic devices include television devices, desktop or notebook personal chips, chip monitors, and digital signage.
In addition to electronic devices with relatively large screens such as large game machines such as pachinko machines (GNAGE), large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio equipment. Examples include playback devices. Furthermore, by providing an integrated circuit or a chip according to one embodiment of the present invention in an electronic device, artificial intelligence can be installed in the electronic device.

An electronic device according to one embodiment of the present invention may include an antenna. By receiving signals with the antenna, images, information, etc. can be displayed on the display unit. Furthermore, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

An electronic device according to one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (including the ability to measure voltage, power, radiation, flow rate, humidity, tilt, vibration, odor, or infrared radiation).

An electronic device according to one embodiment of the present invention can have various functions. For example, functions that display various information (still images, videos, text images, etc.) on the display, touch panel functions, calendars, functions that display date or time, etc., functions that execute various software (programs), wireless communication. It can have a function, a function of reading a program or data recorded on a recording medium, etc. FIG. 26 shows an example of an electronic device.

[mobile phone]

FIG. 26A shows a mobile phone (smartphone) that is a type of information terminal. The information terminal 5500 has a casing 5510 and a display section 5511. The display section 5511 is equipped with a touch panel as an input interface, and buttons are provided on the casing 551.
0 is provided.

The information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. Applications using artificial intelligence include, for example, an application that recognizes a conversation and displays the content of the conversation on the display unit 5511, an application that recognizes characters, figures, etc. input by the user on a touch panel included in the display unit 5511, Examples include an application displayed on the display unit 5511 and an application that performs biometric authentication such as a fingerprint or voiceprint.

[Information terminal 1]
A desktop information terminal 5300 is illustrated in FIG. 26(B). The desktop information terminal 5300 includes an information terminal main body 5301, a display 5302, and a keyboard 5303.

Similar to the information terminal 5500 described above, the desktop information terminal 5300 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. Examples of applications that utilize artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, by using the desktop information terminal 5300, new artificial intelligence can be developed.

Note that in the above description, a smartphone and a desktop information terminal are shown as examples of electronic devices in FIGS. can. Examples of information terminals other than smartphones and desktop information terminals include PDA (Personal Digital
1 Assistant), notebook information terminals, workstations, etc.

[electric appliances]
FIG. 26C shows an electric refrigerator-freezer 5800 that is an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By using artificial intelligence, the electric refrigerator-freezer 5800 has a function that automatically generates a menu based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, etc. It can have functions such as automatically adjusting the temperature to suit the food.

In this example, an electric refrigerator-freezer was explained as an electric appliance, but other electric appliances include vacuum cleaners, microwave ovens, microwave ovens, rice cookers, water heaters, IH cookers, water servers, and air conditioners including air conditioners. Examples include appliances, washing machines, dryers, and audio-visual equipment.

[game machine]

FIG. 26(D) shows a portable game machine 5200 that is an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

By applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200,
A portable game machine 5200 with low power consumption can be realized. In addition, due to low power consumption,
Since the heat generated from the circuit can be reduced, the influence of the heat generated on the circuit itself, peripheral circuits, and modules can be reduced.

Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 having artificial intelligence can be realized.

Originally, the expressions such as the progress of the game, the words and actions of creatures appearing in the game, and the phenomena that occur in the game are determined by the program of the game, but the portable game machine 520
By applying artificial intelligence to 0, it becomes possible to express things that are not limited to game programs. For example, it is possible to express changes in the content of questions asked by the player, the progress of the game, the time of day, and the words and actions of people appearing in the game.

Furthermore, when playing a game that requires multiple players on the portable game machine 5200, the game players can be configured anthropomorphically using artificial intelligence. You can play games.

Although FIG. 26D illustrates a portable game machine as an example of a game machine, the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. G of one embodiment of the present invention
Examples of game machines to which PU or chips are applied include home-use stationary game machines, arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), and batting practice pitching machines installed in sports facilities. Examples include machines.

[Mobile object]
A GPU or a chip according to one embodiment of the present invention can be applied to an automobile, which is a moving body, and around the driver's seat of the automobile.

FIG. 26 (E1) shows an automobile 5700 that is an example of a moving object, and FIG. 26 (E2) is a diagram showing the area around the windshield inside the automobile. FIG. 26 (E1) shows a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, as well as a display panel 5704 attached to a pillar.

The display panels 5701 to 5703 can provide various information such as speedometer, tachometer, mileage, amount of fuel, gear status, air conditioner settings, and so on. Furthermore, the display items and layout displayed on the display panel can be changed as appropriate to suit the user's preferences, making it possible to improve the design. Display panel 570
1 to display panel 5703 can also be used as a lighting device.

By displaying an image from an imaging device (not shown) provided in the automobile 5700 on the display panel 5704, it is possible to supplement the field of view (blind spot) blocked by the pillar. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated for and safety can be improved. In addition, by displaying images that complement the invisible parts, safety confirmation can be performed more naturally and without any discomfort. Display panel 57
04 can also be used as a lighting device.

Since the GPU or chip of one embodiment of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in the automatic driving system of the automobile 5700. Furthermore, the chip can be used in systems that perform road guidance, danger prediction, etc. Display panel 57
The display panels 01 to 5704 may be configured to display information such as road guidance and danger prediction.

Note that although a car is described above as an example of a moving body, the moving body is not limited to a car. For example, examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets), and the chip of one embodiment of the present invention can be applied to these moving objects. It is possible to provide a system using artificial intelligence.

[Broadcast system]
A GPU or a chip according to one embodiment of the present invention can be applied to a broadcast system.

FIG. 26(F) schematically shows data transmission in the broadcasting system. Specifically, FIG. 26(F) shows a route through which radio waves (broadcast signals) transmitted from a broadcast station 5680 reach a television receiving device (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.

In FIG. 26(F), the antenna 5650 is a UHF (Ultra High Frequency) antenna.
The antenna 5650 is BS/110°CS.
Antenna, CS antenna, etc. can also be applied.

The radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio waves 5675A and transmits the radio waves 5675B. In each home, by receiving radio waves 5675B with an antenna 5650, terrestrial TV broadcasts can be viewed on a TV 5600. Note that the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 26(F), but may also be satellite broadcasting using an artificial satellite, data broadcasting using an optical line, or the like.

The above-described broadcasting system may be a broadcasting system using artificial intelligence by applying the chip of one embodiment of the present invention. When transmitting broadcast data from the broadcast station 5680 to the TV 5600 in each home, the encoder compresses the broadcast data, and when the antenna 5650 receives the broadcast data, the decoder of the receiving device included in the TV 5600 compresses the broadcast data. Restoration takes place. By using artificial intelligence, for example, display patterns included in a display image can be recognized in motion compensated prediction, which is one of the compression methods of an encoder. It is also possible to perform intra-frame prediction using artificial intelligence. Further, for example, when receiving low-resolution broadcast data and displaying the broadcast data on a high-resolution TV 5600, image interpolation processing such as up-conversion can be performed when restoring the broadcast data by the decoder.

The above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcast data increases.

Further, as an application of artificial intelligence on the TV 5600 side, for example, a recording device having artificial intelligence may be provided in the TV 5600. With such a configuration, by having the recording device learn the user's preferences using artificial intelligence, it is possible to automatically record a program that matches the user's preferences.

The electronic device, the functions of the electronic device, the application examples of artificial intelligence, the effects thereof, etc. described in this embodiment can be combined as appropriate with the descriptions of other electronic devices.

This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes.

200 Transistor 205 Conductor 210 Insulator 212 Insulator 214 Insulator 216 Insulator 218 Conductor 222 Insulator 224 Insulator 230 Oxide 230a Oxide 230A Oxide film 230b Oxide 230B Oxide film 230c Oxide 230c1 Oxide 230c2 Oxide 231 Region 231a Region 231b Region 232 Region 232a Region 232b Region 234 Region 240 Conductor 240a Conductor 240b Conductor 241 Insulator 241a Insulator 241b Insulator 244 Insulator 250 Insulator 252 Layer 252a Layer 252b Layer 253 Layer 253a layer 253b layer 254 Insulator 256 Insulator 256a Insulator 256b Insulator 257 Dopant 258 Dopant 260 Conductor 260a Conductor 260Aa Conductive film 260Ab Conductive film 260b Conductor 262 Dummy gate 262A Dummy gate 262B Dummy gate 263 Opening 266 Insulator 266A Insulating film 26 6B insulation Body 267 Dummy film 267A Dummy film 274 Insulator 274a Insulator 274b Insulator 280 Insulator 280A Insulator 281 Insulator

Claims (12)

a first oxide;
a second oxide on the first oxide;
a first insulator on the second oxide;
a conductor disposed on the first insulator and having a region overlapping with the first oxide and the second oxide;
a second insulator having a region in contact with the top surface of the first insulator and a region in contact with the side surface of the conductor;
a third insulator having a region in contact with an upper surface of the second insulator and a region in contact with a side surface of the conductor;
a fourth insulator having a region in contact with the top surface of the conductor and a region in contact with the top surface of the third insulator;
The second oxide includes a first region, a second region, a third region located between the first region and the second region, and a third region located between the first region and the second region. a fourth region located between the third region and a fifth region located between the second region and the third region,
The resistance of the first region and the resistance of the second region are lower than the resistance of the third region,
The resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region,
The conductor is configured to overlap at least a portion of the first region, at least a portion of the second region, the third region, the fourth region, and the fifth region. A semiconductor device provided above a third region, above the fourth region, and above the fifth region. a first oxide;
a second oxide on the first oxide;
a first insulator on the second oxide;
a conductor disposed on the first insulator and having a region overlapping with the first oxide and the second oxide;
a second insulator having a region in contact with the top surface of the first insulator and a region in contact with the side surface of the conductor;
a third insulator having a region in contact with an upper surface of the second insulator and a region in contact with a side surface of the conductor;
a fourth insulator having a region in contact with the top surface of the conductor and a region in contact with the top surface of the third insulator;
The second oxide includes a first region, a second region, a third region located between the first region and the second region, and a third region located between the first region and the second region. a fourth region located between the third region and a fifth region located between the second region and the third region,
The resistance of the first region and the resistance of the second region are lower than the resistance of the third region,
The resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region,
A semiconductor device, wherein the conductor overlaps at least a portion of the first region, at least a portion of the second region, the third region, the fourth region, and the fifth region. In claim 1 or 2 ,
The semiconductor device, wherein the first region, the second region, the fourth region, and the fifth region contain phosphorus or boron. In claim 3 ,
The semiconductor device, wherein the first region and the second region contain more phosphorus or boron than the fourth region and the fifth region. In any one of claims 1 to 4 ,
The first region, the second region, the fourth region, and the fifth region have more oxygen vacancies than the third region. In any one of claims 1 to 5 ,
The first region, the second region, the fourth region, and the fifth region contain more hydrogen than the third region. forming a first oxide and a second oxide on the first oxide;
forming a first insulating film on the second oxide;
forming a first dummy gate on the first insulating film, having a region overlapping with the second oxide;
adding a first dopant to the second oxide using the first dummy gate as a mask;
removing a portion of the first dummy gate to form a second dummy gate, exposing a portion of the second oxide from the second dummy gate;
adding a second dopant to the second oxide using the second dummy gate as a mask;
forming a second insulating film covering the first insulating film and the second dummy gate;
forming a third insulating film on the second insulating film;
removing a portion of the second insulating film and the third insulating film until an upper part of the second dummy gate is exposed;
removing a portion of the second dummy gate and the second insulating film to form an opening;
forming a conductive film so as to be embedded in the opening;
A method for manufacturing a semiconductor device, wherein a part of the conductive film is removed until an upper part of the third insulating film is exposed. In claim 7 ,
A method for manufacturing a semiconductor device, using phosphorus or boron as the first dopant and the second dopant. In claim 7 or 8 ,
The method for manufacturing a semiconductor device, wherein the amount of the first dopant added is greater than the amount of the second dopant added. In any one of claims 7 to 9 ,
In the method for manufacturing a semiconductor device, an ion implantation method or an ion doping method is used for adding the first dopant and adding the second dopant. In any one of claims 7 to 10 ,
The method for manufacturing a semiconductor device, wherein the first dummy gate contains carbon. In any one of claims 7 to 11 ,
In the method for manufacturing a semiconductor device, the second dummy gate is formed by an ashing process using oxygen radicals.

Images