JP7195928B2 - Charge emission circuit, display substrate, display device and charge emission method thereof - Google Patents

Description

CROSS-REFERENCE TO RELATED APPLICATIONS The present invention claims priority to a Chinese patent application with filing date Jan. 3, 2017 and application number 201720002380.1, and disclosed in said Chinese patent application The full text of the content is incorporated as an illustrative part of this disclosure.

Exemplary embodiments of the present disclosure relate to charge emission circuits, display substrates, display devices, and charge emission methods thereof.

A liquid crystal display panel includes a color film substrate and an array substrate facing each other, and a liquid crystal positioned between the color film substrate and the array substrate.

For example, a common electrode is formed on the base substrate of the color film substrate, a plurality of horizontally arranged gate lines and a plurality of vertically arranged data lines are formed on the base substrate of the array substrate, A plurality of pixel regions are formed by intersecting gate lines and data lines, and one thin film transistor and one pixel electrode are formed in each pixel region. For example, a thin film transistor includes a gate connected to a gate line, a source connected to a data line, and a drain connected to a pixel electrode. When the display panel is controlled to display an image, a voltage is applied to the gate through the gate line to turn on the thin film transistor, a pixel voltage is applied to the pixel electrode through the data line, the source and the drain, and By applying a common voltage to the common electrode, the liquid crystal is deflected under the action of the pixel voltage and the common voltage, so that the display panel displays an image. When there is no need to control the display panel to display an image, the application of voltage to the pixel electrode and the common electrode is stopped so that the liquid crystal is undeflected and the display panel is in a blank screen state.

Exemplary embodiments of the present disclosure provide charge emission circuits, display substrates, display devices, and charge emission methods thereof.

At least one example of the present disclosure includes a controller, a charge emission subcircuit, and a first conductor, the charge emission subcircuit being positioned within the active display area of the controller, the first conductor, and the array substrate. and a second conductor, and the charge discharge subcircuit conducts the first conductor and the second conductor under the control of the controller to discharge the charge on the second conductor to the second conductor. A charge discharge circuit is provided which is arranged to move toward the one conductor.

According to a charge emission circuit provided by an example of the present disclosure, the second conductor includes at least one gate line, the controller includes a first control line, and the charge emission subcircuit includes a first one charge emission unit, wherein the first charge emission unit is connected to the at least one gate line, the first control line and the first conductor; is arranged to conduct a control signal on the first control line between the first conductor and the at least one gate line.

According to a charge emission circuit provided by an example of the present disclosure, the second conductor includes a plurality of gate lines, the first charge emission unit includes a plurality of first transistors, and the first is perpendicular to the gate line, the plurality of first transistors correspond to the plurality of gate lines one-to-one, and the gates of each of the first transistors are all connected to the first transistor. one control line, a first pole of each of the first transistors is connected to one gate line of the plurality of gate lines, and a second pole of each of the first transistors is connected to one gate line of the plurality of gate lines; are both connected to the first conductor.

According to a charge emission circuit provided by an example of the present disclosure, the second conductor includes at least one data line, the controller includes a second control line, and the charge emission subcircuit includes a second two charge-emission units, wherein the second charge-emission unit is respectively connected to the at least one data line, the second control line and the first conductor, and the second charge-emission unit The unit is arranged to conduct between said first conductor and said at least one data line by a control signal on said second control line.

According to a charge emission circuit provided by an example of the present disclosure, the second conductor includes a plurality of data lines, the second charge emission unit includes a plurality of second transistors, and the second are perpendicular to the data lines, the plurality of second transistors correspond one-to-one to the plurality of data lines, and the gates of each of the second transistors are all connected to the second transistors. 2 control lines, a first pole of each of the second transistors is connected to one data line of the plurality of data lines, and a second pole of each of the second transistors is connected to one of the plurality of data lines. are both connected to the first conductor.

According to a charge emission circuit provided by an example of the present disclosure, the second conductor further includes at least one pixel electrode, the controller further includes a third control line, and the charge emission subcircuit comprises: , further comprising a third charge emission unit, the third charge emission unit being connected to the gate line and the third control line on the array substrate, respectively, the third charge emission unit being connected to the third By writing the control signal on the control line to the gate line, each pixel electrode and the data line connected to the pixel electrode are arranged to be electrically connected.

According to a charge emission circuit provided by an example of the present disclosure, the third charge emission unit includes a plurality of third transistors, and the plurality of third transistors comprises a plurality of gate lines on the array substrate. , wherein the second conductor includes a plurality of pixel electrodes connected to each of the gate lines, the third control line is perpendicular to the gate lines, and each of the third The gates and first poles of the three transistors are both connected to the third control line, and the second poles of each of the third transistors are both gates of one of the plurality of gate lines. connected to the line.

According to the charge emission circuit provided by one example of the present disclosure, the volume of the first conductor is larger than the volume of the second conductor.

According to the charge discharge circuit provided by one example of the present disclosure, the first conductor is a common electrode line or a storage electrode line.

At least one example of the present disclosure provides a display substrate comprising any one of the charge emission circuits.

At least one example of the present disclosure further provides a display device comprising a display panel including any one of the display substrates.

At least one example of the present disclosure applies a control signal to the controller when the display panel becomes a blank screen, and conducts the first conductor and the second conductor under the control of the controller to cause the Further provided is a method of discharging charge in any one of the foregoing display devices, comprising the step of moving charge on a second conductor toward said first conductor.

According to the method provided by one example of the present disclosure, the first conductor is a common electrode line or a storage electrode line, and the second conductor is at least one of a gate line, a data line, or a pixel electrode. including one.

According to the method provided by one example of the present disclosure, the volume of the first conductor is greater than the volume of the second conductor.

In order to more clearly describe the technical solutions in the examples of the present disclosure, the drawings required for the description of the examples will be briefly described below, and the drawings depicted below are merely examples of the examples of the present disclosure. It is obvious that there is no other drawing, and those skilled in the art can follow these drawings to obtain other drawings without creative effort.

1 is a structural schematic diagram of a charge discharge circuit provided by an example of the present disclosure; FIG. It is a structural schematic diagram of an array substrate. FIG. 4 is a structural schematic diagram of another array substrate; FIG. 4 is a structural schematic diagram of another charge discharge circuit provided by an example of the present disclosure; FIG. 4 is a structural schematic diagram of another charge discharge circuit provided by an example of the present disclosure; FIG. 4 is a structural schematic diagram of yet another charge discharge circuit provided by an example of the present disclosure; FIG. 2 is a structural schematic diagram of a charge discharge circuit provided by another example of the present disclosure; FIG. 4 is a structural schematic diagram of another charge discharge circuit provided by another example of the present disclosure;

In order to make the purpose, technical solution and advantages of the examples of the present disclosure clearer, the following will describe the example technical solutions of the present disclosure more clearly and completely in conjunction with the example drawings of the present disclosure. It is evident that the examples described are part, but not all, of the disclosure. Based on the described examples of the present disclosure, all other examples obtained by persons skilled in the art without creative efforts shall fall within the protection scope of the present invention.

Unless defined otherwise, technical or scientific terms used herein have the common meaning understood by one of ordinary skill in the art to which this invention belongs. The terms "first", "second" and similar terms used in this disclosure do not imply order, number or importance, but are only used to distinguish different components. Similarly, similar terms such as "a", "one" or "this" are not intended to be limiting in number, but to indicate the presence of at least one. Similar terms such as “comprising” or “including” are intended to include the elements or components listed after the term and their equivalents, as well as the elements or components listed after the term. means not excluding elements or parts of Similar terms such as "connected" or "continuous" are not limited to physical or mechanical connections, but may include direct or indirect electrical connections. "Top", "bottom", "left", "right", etc. are used only to indicate relative positional relationships and may be used to indicate relative position if the absolute position of the object being described changes. positional relationship also changes.

If it is not necessary to control the display panel to display an image, the charge remaining when voltage was applied to some conductors (e.g. gate lines and data lines) within the effective display area of the array substrate the previous time. Due to the presence of , some liquid crystals are still deflected, causing the display panel in the blank screen state to display bright spots.

The transistors employed in all examples of this disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics, and according to their role in the circuit, the transistors employed in the examples of this disclosure are mainly Second, it is a switching transistor. Since the source and drain of the switching transistor employed here are symmetrical, the source and drain are interchangeable. In the illustrations of this disclosure, the source therein is referred to as the first pole and the drain as the second pole to distinguish between the two poles of the transistor, excluding the gate. According to the configuration in the drawings, the intermediate end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Also, the switching transistors employed in the examples of the present disclosure include at least one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is conductive when the gate is at a low level; It is cut off when the gate is high level, and the N-type switching transistor is conductive when the gate is high level and cut off when the gate is low level.

FIG. 1 is a structural schematic diagram of a charge emission circuit 0 provided by an example of the present disclosure.As shown in FIG. 1, this charge emission circuit 0 includes a controller 01, a charge emission subcircuit 02, A charge emission subcircuit 02 is connected to the controller 01, the first conductor 03 and a second conductor A within the active display area of the array substrate, respectively. Controller 01 may be a control module and charge emission subcircuit 02 may be a charge emission module.

The charge discharge subcircuit 02 conducts the first conductor 03 and the second conductor A under the control of the controller 01 so that the charge on the second conductor A moves toward the first conductor 03. placed. For example, the first conductor 03 can be grounded.

For example, in the charge emission circuit provided by the illustrative examples of this disclosure, the charge emission sub-circuit 02 is connected to the controller 01 and the first conductor 03, and the charge emission sub-circuit 02 is connected to the first conductor 03 under the action of the controller 01. Conducting the conductor 03 and the second conductor A in the effective display area of the array substrate, the charge on the second conductor A can be transferred to the first conductor 03, so that the effective display area of the array substrate to reduce the charge on the second conductor A in the display panel, reduce the probability of liquid crystal deflection when the display panel is in blank screen state, and reduce the number of bright spots on the display panel in blank screen state.

FIG. 2A is a structural schematic diagram of the array substrate 1. As shown in FIG. 2A, the array substrate 1 may include a base substrate 100, and within the effective display area Y of the base substrate 100, a plurality of A gate line A1 and a plurality of data lines A2 are formed. The plurality of gate lines A1 and the plurality of data lines A2 are insulated from each other and cross to form a plurality of pixel regions. A transistor A4 and one pixel electrode A3 are formed, the gate of the transistor A4 is connected to the gate line A1 surrounding this pixel area, and the source of the transistor A4 is connected to the data line A2 surrounding this pixel area. , the drain of the transistor A4 is connected to the pixel electrode A3 in this pixel region. For example, a first common electrode line 031 and a second common electrode line 032 are formed in the non-effective display area (that is, edge area) of the base substrate 100 . For example, the first common electrode line 031 is perpendicular to the gate line A1 and the second common electrode line 032 is perpendicular to the data line A2. For example, the first common electrode line 031 is insulated from the gate line A1, and the second common electrode line 032 is insulated from the data line A2. For example, the data lines are arranged to input data signals such as gradation voltages to the pixels. For example, gate lines are arranged to input gate signals, such as gate voltages, to the transistors.

As shown in FIG. 2B, a plurality of storage electrode lines A0 may be further formed in the effective display area Y of the base substrate 100, and each storage electrode line A0 passes through one row of pixel areas. are installed in parallel with the gate line A1.

For example, as shown in FIGS. 2A and 2B, transistors A4 are arranged in an array, each gate line is connected to one row of transistors A4, each data line is connected to one column of transistors A4, and each pixel The electrodes are connected to one transistor A4. The pixel electrode corresponding to each gate line is the pixel electrode connected to this gate line via transistor A4. The data line corresponding to each pixel electrode is the data line connected to this pixel electrode via transistor A4.

For example, the volume of the first conductor 03 may be greater than the volume of the second conductor A. At this time, since the volume of the first conductor 03 is large, the amount of charge that can be received by the first conductor 03 is also large. can do. For example, the line width of the first conductor 03 may be larger than the line width of the second conductor A, thus increasing the amount of charge that the first conductor 03 can receive. Exemplarily, the array substrate includes a base substrate, on which various conductive lines are formed, where common electrode lines and storage electrode lines are wide, but other conductive lines (eg, gate lines, data line, etc.) is narrow. The first conductor 03 may be a common electrode line or a storage electrode line on the array substrate, and the second conductor A is any one conductor within the effective display area of the array substrate, such as the second conductor A. 2 conductors A may be gate lines, data lines or pixel electrodes.

The following provides an illustration of the present disclosure, taking as an example the case where the first conductor is the common electrode line on the array substrate and the second conductors are respectively the gate line, the data line and the pixel electrode on the array substrate. A charge discharge circuit is interpreted and described.

In a first aspect, the second conductor includes at least one gate line, the controller includes a first control line, the charge emission subcircuit includes a first charge emission unit, and the first charge emission subcircuit includes a first charge emission unit. The emission unit is connected to the at least one gate line, the first control line and the first conductor respectively, and the first charge emission unit is connected to the first conductor and at least one by a control signal on the first control line. are arranged to conduct one gate line.

FIG. 3 is a structural schematic diagram of the charge emission circuit 0 provided by the example of the present disclosure, as shown in FIG. 3, the second conductor includes a plurality of gate lines A1, the first charge emission The unit 021 includes a plurality of first transistors 0211, and the plurality of first transistors 0211 correspond to the plurality of gate lines A1 on a one-to-one basis. The gate G of each first transistor 0211 is connected to the first control line 011, the first pole J1 of each first transistor 0211 is connected to the corresponding gate line A1, The second pole J2 of one transistor 0211 is connected to a first common electrode line 031 which are both perpendicular to the gate line A1, where the first control line 011 is connected to the gate line A1. vertical. For example, the first control line 011 is insulated from each gate line A1.

When it is necessary to control the display panel to enter a blank screen state, each first transistor 0211 of the plurality of first transistors 0211 is in a conductive state (that is, A control signal is input to the first control line 011 so that the first pole J1 and the second pole J2 are in communication, whereby each first transistor 0211 is connected to the gate line A1 and the first common electrode line 031 are electrically connected, and if charges remain in the gate line A1 at this time, the remaining charges can flow toward the first common electrode line 031, Therefore, the charge on the gate line A1 is reduced, and the first conductor for sharing the charge on the second conductor is the first common electrode line 031 at this time. After the display panel enters the blank screen state, the charge on the gate line is less, so that the liquid crystal is prevented from being deflected under the action of voltage, preventing the display panel from displaying bright spots, and the blank screen It can solve the problem that the display panel in the state displays bright spots.

In a second aspect, the second conductor includes at least one data line, the controller includes a second control line, the charge emission subcircuit includes a second charge emission unit, and the second charge emission subcircuit includes a second charge emission unit. The emission unit can be connected to at least one data line, the second control line and the first conductor respectively, the second charge emission unit being activated by the control signal on the second control line to the first The conductor is arranged to communicate with the at least one data line.

FIG. 4 is a structural schematic diagram of another charge discharge circuit 0 provided by the example of the present disclosure, as shown in FIG. The second charge discharge unit 022 includes a line A2, and includes a plurality of second transistors 0221, the plurality of second transistors 0221 corresponding to the plurality of data lines A2 one-to-one, and each second transistor 0221 are all connected to the second control line 012, the first poles J1 of each second transistor 0221 are all connected to the corresponding data line A2, and the The second pole J2 is connected to a second common electrode line 032 which is both perpendicular to the data line A2. For example, the second control line 012 may be perpendicular to the data line A2.

When it is necessary to control the display panel to enter a blank screen state, a control signal is input to the second control line 012 so that each second transistor 0221 becomes conductive, thus each second transistor 0221 is turned on. 2 transistor 0221 conducts the connected data line A2 and the second common electrode line 032. At this time, if charges remain on the data line A2, the charges remaining on the data line A2 are transferred to the second common electrode line 032. can flow toward the common electrode line 032 of the second common electrode line 032, thus reducing the charge on the data line A2, at this time the first conductor for sharing the charge on the second conductor becomes the second common electrode line. line 032; After the display panel is in a blank screen state, the charge on the data line is small, so that the liquid crystal is prevented from being deflected under the action of the voltage, and the display panel is prevented from displaying a bright spot.

In a third aspect, in addition to the second aspect, the second conductor further includes at least one pixel electrode, the controller further includes a third control line, and the charge emission subcircuit comprises a third further comprising a charge emission unit, wherein the third charge emission unit is respectively connected to the gate line and the third control line on the array substrate, the third charge emission unit outputs the control signal on the third control line to the gate line; , the pixel electrode and the data line corresponding to the pixel electrode are electrically connected.

FIG. 5 is a structural schematic diagram of yet another charge emission circuit 0 provided by the example of the present disclosure. As shown in FIG. 5, in addition to FIG. Further includes a charge emission unit 023, the third charge emission unit 023 includes a plurality of third transistors 0231, and the plurality of third transistors 0231 correspond one-to-one with the plurality of gate lines A1 on the array substrate. , at least one pixel electrode on the second conductor includes a plurality of pixel electrodes A3 corresponding to each gate line A1, and the gate G and first pole J1 of each third transistor 0231 are both connected to the third The second pole J2 of each third transistor 0231 is connected to the gate line A1 corresponding to this third transistor 0231, and the third control line 013 is connected to the gate line A1. can be perpendicular to

If the display panel needs to be controlled to enter a blank screen state, a control signal can also be input to the third control line 013 so that each third transistor 0231 is all conductive, thus Along the first and second poles of the third transistor 0231, the control signal on the third control line 013 is input to the gate line A1 corresponding to this third transistor 0231, and this gate line A1 By turning on the transistor in the pixel region connected to the gate line A1, the pixel electrode A3 corresponding to the gate line A1 and the data line A2 corresponding to the pixel electrode A3 are turned on. For example, a control signal can be input to the second control line 012 so that each second transistor 0221 is all conductive, so that each second transistor 0221 is connected to the data line. A2 and the second common electrode line 032 are electrically connected. At this time, if a charge remains on the pixel electrode A3, the remaining charge flows toward the data line A2 and further flows into the second common electrode line 032, thereby generating data. The first conductor for reducing the charge on the line A2 and the pixel electrode A3 and sharing the charge on the second conductor at this time is the second common electrode line 032 . After the display panel is in a blank screen state, the charge on the data line and the pixel electrode is small, preventing the liquid crystal from being deflected under the action of voltage and preventing the display panel from displaying a bright spot. do.

In a fourth aspect, FIG. 6 is a structural schematic diagram of a charge discharge circuit 0 provided by another example of the present disclosure, as shown in FIG. , the charge discharge circuit 0 includes a plurality of first transistors 0211, a plurality of second transistors 0221, a first control line 011, and a second control line A1 and a plurality of data lines A2. A line 012, a first common electrode line 031, and a second common electrode line 032 may be included.

For example, the first common electrode line 031 is perpendicular to the gate line A1 and parallel to the data line A2, and the first control line 011 is parallel to the first common electrode line 031. are parallel to each other. The second common electrode line 032 is perpendicular to the data line A2 and parallel to the gate line A1, and the second control line 012 is parallel to the second common electrode line 032. is. The plurality of first transistors 0211 correspond to the plurality of gate lines A1 one-to-one, and the plurality of second transistors 0221 correspond to the plurality of data lines A2 one-to-one. The gate of each first transistor 0211 is connected to the first control line 011, and the first pole of each first transistor 0211 is connected to the gate line A1 corresponding to this first transistor. , and the second poles of the respective first transistors 0211 are all connected to the first common electrode line 031 . The gate of each second transistor 0221 is connected to the second control line 012, and the first pole of each second transistor 0221 is connected to the data line A2 corresponding to this second transistor. , and the second poles of the respective second transistors 0221 are all connected to the second common electrode line 032 .

When it is necessary to control the display panel to enter a blank screen state, a control signal can be input to the first control line 011 such that each first transistor 0211 is all conductive, thus , each of the first transistors 0211 conducts the connected gate line A1 and the first common electrode line 031. At this time, if a charge remains in the gate line A1, the remaining charge is transferred to the first gate line A1. 1 can flow toward the common electrode line 031, thus reducing the charge on the gate line A1. Also, a control signal can be input to the second control line 012 so that each second transistor 0221 is in a conductive state, and thus each second transistor 0221 is connected to the data line A2. and the second common electrode line 032, and at this time, if a charge remains in the data line A2, this remaining charge can flow toward the second common electrode line 032, so that , the charge on the data line A2 decreases. At this time, the first conductors for sharing the charge on the second conductors are the first common electrode line 031 and the second common electrode line 032 . After the display panel enters the blank screen state, the charge on the data lines decreases.

In a fifth aspect, FIG. 7 is a structural schematic diagram of another charge discharge circuit 0 provided by another example of the present disclosure, as shown in FIG. The charge discharge circuit 0 includes a plurality of gate lines A1, a plurality of data lines A2 and a plurality of pixel electrodes A3 on the substrate, and the charge discharge circuit 0 includes a plurality of first transistors 0211, a plurality of second transistors 0221 and a plurality of including a third transistor 0231, a first control line 011, a second control line 012, a third control line 013, a first common electrode line 031, and a second common electrode line 032 It's okay.

For example, the first common electrode line 031 is perpendicular to the gate line A1 and parallel to the data line A2. Both the first control line 011 and the third control line 013 are perpendicular to the first common electrode line 031 and are installed near the first common electrode line 031. One control line 011 is installed on one side of the first common electrode line 031 near the effective display area, and a third control line 013 is installed on one side of the first common electrode line 031 away from the effective display area. Installed. A second common electrode line 032 is perpendicular to the data line A2 and parallel to the gate line A1. The second control line 012 is parallel to the second common electrode line 032 and placed near the second common electrode line 032, for example, the effective display area of the second common electrode line 032. is installed on one side close to the

The plurality of first transistors 0211 correspond one-to-one to the plurality of gate lines A1, the plurality of second transistors 0221 correspond to the plurality of data lines A2 one-to-one, and the plurality of third transistors 0231 correspond to , correspond to a plurality of gate lines A1 one-to-one. The gate of each first transistor 0211 is connected to the first control line 011, and the first pole of each first transistor 0211 is connected to the gate line A1 corresponding to this first transistor. , and the second poles of the respective first transistors 0211 are all connected to the first common electrode line 031 . The gate of each second transistor 0221 is connected to the second control line 012, and the first pole of each second transistor 0221 is connected to the data line A2 corresponding to this second transistor. , and the second poles of the respective second transistors 0221 are all connected to the second common electrode line 032 . The gate and first pole of each third transistor 0231 are both connected to the third control line 013, and the second pole of each third transistor 0231 corresponds to this third transistor. It is connected to the gate line A1.

When it is necessary to control the display panel to enter a blank screen state, a control signal can be input to the first control line 011 such that each first transistor 0211 is all conductive, thus , each first transistor 0211 conducts the connected gate line A1 and the first common electrode line 031. At this time, if a charge remains in the gate line A1, this remaining charge is transferred to the first gate line A1. 1 common electrode line 031, the charge on the gate line A1 is reduced.

For example, a control signal can be input to the second control line 012 so that each second transistor 0221 is all conductive, so that each second transistor 0221 is connected to the data line. A2 and the second common electrode line 032 are electrically connected, and at this time, if charges remain in the data line A2, the remaining charges can flow to the second common electrode line 032 and divert. , the charge on the data line A2 decreases. After the display panel enters the blank screen state, the charge on the data lines decreases.

Furthermore, a control signal can be input to the third control line 013 so that all the third transistors 0231 are in a conducting state, so that the control signal on the third control line 013 is set to the third transistor 0231. input from the first and second poles of the transistor 0231 to the gate line A1 corresponding to this third transistor 0231, the pixel electrode A3 corresponding to this gate line A1, and the data corresponding to this pixel electrode A3. Conduct line A2. At this time, if a charge remains in the pixel electrode A3, the remaining charge can flow to the data line A2 and then to the second common electrode line 032, so that the data line A2 and the pixel electrode The charge on A3 is reduced.

At this time, the first conductors for sharing the charges on the second conductors are the first common electrode line 031 and the second common electrode line 032 . After the display panel enters the blank screen state, the charge on the conductors (such as gate lines, data lines and pixel electrodes) in the effective display area of the array substrate becomes less and the liquid crystal is deflected under the action of voltage. to prevent a bright spot from being displayed on the display panel.

For example, members extending in the same direction may be formed in the same layer in an example of the present disclosure. For example, at least two of the data line A2, the first common electrode line 031, the first control line 011 and the third control line 013 may be formed in the same layer, for example, in the first layer. do. At least two of the gate line A1, the second control line 012 and the common electrode line 032 may be formed in the same layer, for example, in the second layer. For example, an insulating layer can be placed between the first layer and the second layer so that the intersections of the two lines are not electrically connected.

For example, in an example of the present disclosure, two members can be connected through a transistor. For example, black dots in each figure can represent electrical connections. For example, in each figure, two intersecting lines are insulated from each other at the intersection.

In summary, examples of the present disclosure provide a charge emission circuit in which the charge emission subcircuit is connected to the controller and the first conductor, respectively, and the charge emission subcircuit is connected to the first conductor and the first conductor under the action of the controller. By conducting the second conductors of the array substrate effective display area, the charge on the second conductors can be transferred to the first conductors, so that the charges on the second conductors within the array substrate effective display area are transferred to the first conductors. reduces the probability that the liquid crystal will be deflected when the display panel is in the blank screen state, and reduces the number of bright spots on the display panel in the blank screen state.

Exemplary embodiments of the present disclosure further provide display substrates including the charge emission circuit shown in any one of FIGS. 1, 3, 4, 5, 6 or 7. FIG.

Further, the exemplification of the present disclosure further provides a display panel including a display substrate on which the charge emission circuit shown in any one of FIGS. 1, 3, 4, 5, 6 or 7 is mounted. . For example, this display substrate may be an array substrate. For example, the display panel may further include a counter substrate facing the array substrate. For example, the counter substrate may be a color film substrate, but is not limited to this. During implementation, this display substrate may be the opposing substrate, although the examples of this disclosure are not limited thereto.

Further, the exemplification of the present disclosure further provides a display device comprising a display panel, wherein the display substrate in the display panel is any one of FIGS. including the charge discharge circuit shown. This display device includes a liquid crystal panel, electronic paper, an organic light-emitting diode (OLED) panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet PC, and a television. , televisions, notebook computers, digital frames, navigators, and any other products or components with a display function.

At least one example of the present disclosure further provides a charge discharging method for a display device including discharging charges using any one of the charge discharging circuits described above. In this method, when the display panel becomes a blank screen, a control signal is applied to the controller to conduct the first conductor and the second conductor under the control of the controller so that the charge on the second conductor is to the first conductor.

For example, when the display panel is in a blank screen state, the display device is in a standby state.

The above descriptions are only specific embodiments of the present invention, and the protection scope of the present invention is not limited thereto. Those skilled in the art can make modifications or replacements within the technical scope disclosed in the present invention. Any modification or replacement thereof should be easily conceived and should also fall within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (12)

including a controller, a charge discharge subcircuit, and a first conductor;
said charge emission sub-circuits are respectively connected to said controller, said first conductors and second conductors within an active display area of an array substrate;
The charge discharge subcircuit is controlled by the controller to conduct the first conductor and the second conductor to move the charge on the second conductor toward the first conductor. placed and
the second conductor includes at least one data line, the controller includes a second control line,
the charge emission subcircuit includes a second charge emission unit;
said second charge discharging unit is connected to said at least one data line, said second control line and said first conductor respectively;
the second charge discharging unit is arranged to conduct between the first conductor and the at least one data line by a control signal on the second control line;
the second conductor further includes a gate line and at least one pixel electrode;
The controller further includes a third control line,
the charge emission subcircuit further includes a third charge emission unit;
the third charge emission unit is respectively connected to the gate line and the third control line on the array substrate;
The third charge emission unit is arranged to electrically connect each pixel electrode and a data line connected to the pixel electrode by writing a control signal on the third control line to the gate line. ,
The second conductor includes a plurality of data lines, the second charge discharge unit includes a plurality of second transistors, each gate of the plurality of second transistors is connected to the second control lines, a first pole of each of said plurality of second transistors being connected to one data line of said plurality of data lines, and a second pole of each of said plurality of second transistors being connected to a data line of said plurality of data lines; a pole connected to the first conductor;
The second conductor includes a plurality of gate lines, the third charge discharge unit includes a plurality of third transistors, and both a gate and a first pole of each of the plurality of third transistors. is connected to the third control line, a second pole of each of the plurality of third transistors is connected to one gate line of the plurality of gate lines,
The plurality of gate lines and the plurality of data lines are arranged in the effective display area, are insulated from each other, and cross each other to form a plurality of pixel areas, and transistors and pixel electrodes are arranged in the plurality of pixel areas. , the gate of the transistor is connected to one gate line, the source of the transistor is connected to the data line, and the drain of the transistor is connected to the pixel electrode in the pixel region. ,
The charge discharge circuit, wherein the second control line is insulated from the third control line. the controller includes a first control line;
the charge emission sub-circuit includes a first charge emission unit;
the first charge discharging unit is connected to at least one gate line of the plurality of gate lines, the first control line and the first conductor;
2. The charge emission circuit of claim 1, wherein the first charge emission unit is arranged to conduct the first conductor and the at least one gate line by a control signal on the first control line. the first charge emission unit includes a plurality of first transistors;
the first control line is perpendicular to the gate line;
the plurality of first transistors correspond to the plurality of gate lines on a one-to-one basis;
A gate of each of the plurality of first transistors is connected to the first control line, and a first pole of each of the plurality of first transistors is one of the gate lines. 3. The charge emission circuit according to claim 2, wherein a second pole of each of said plurality of first transistors is connected to said first conductor. the second control line is perpendicular to the data line;
4. The charge discharge circuit according to claim 3, wherein the plurality of second transistors correspond to the plurality of data lines one-to-one. the plurality of third transistors correspond one-to-one to the plurality of gate lines on the array substrate;
the second conductor includes a plurality of pixel electrodes connected to each of the gate lines;
5. A charge emission circuit according to any one of claims 1 to 4, wherein said third control line is perpendicular to said gate line. 6. The charge emission circuit according to any one of claims 1 to 5, wherein the line width of the first conductor is greater than the line width of the second conductor. 7. The charge emission circuit according to any one of claims 1 to 6, wherein said first conductor is a common electrode line or a storage electrode line. A display substrate comprising the charge emission circuit according to any one of claims 1 to 7. A display device comprising a display panel including the display substrate according to claim 8 . A charge emission method in the display device according to claim 9,
applying a control signal to the controller when the display panel becomes a blank screen;
Conducting the first conductor and the second conductor under the control of the controller;
moving charge on the second conductor toward the first conductor;
Conducting the first conductor and the second conductor under the control of the controller,
inputting a control signal to the second control line to move the charge on the data line to the first conductor;
and inputting a control signal to the third control line to move the charge on the pixel electrode to the first conductor. the first conductor is a common electrode line or a storage electrode line;
11. The method of Claim 10, wherein said second conductor comprises at least one of a gate line, a data line or a pixel electrode. 12. A method according to claim 10 or 11, wherein the line width of said first conductor is greater than the line width of said second conductor.

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