JP7194918B2 - Solid-state image sensor - Google Patents

Description

The present disclosure relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a charge storage section in each unit pixel.

In recent years, as one of photodetectors for detecting weak light, photon counting photodetectors using an avalanche photodiode (APD) have been developed. An APD is a photodiode that multiplies photocurrent by applying a predetermined reverse voltage. When the APD is in the Geiger multiplication mode, when one photon causes photoelectric conversion, avalanche breakdown occurs and the output current increases sharply. For this reason, a charge storage unit is required to store the signal charge multiplied by the avalanche breakdown.

However, in order to ensure a sufficiently large capacitance value in the charge storage section, it is necessary to increase the area occupied by the charge storage section, resulting in the problem of a reduced area of the photodiode.

Therefore, as shown in Japanese Unexamined Patent Application Publication No. 2002-100000, the charge storage portion is arranged in a waveguide for guiding light to the photoelectric conversion portion so that the charge storage portion can be provided in the unit pixel without reducing the planar area of the photodiode. A technique for setting the

Japanese Patent Application Laid-Open No. 2013-207321 (Fig. 30)

However, in the conventional solid-state imaging device, the lower electrode, capacitive film, and upper electrode, which constitute the charge storage section, are formed even on the surface of the interlayer insulating film. As a result, the portion of the charge storage section formed on the interlayer insulating film protrudes upward from the open end of the waveguide, and the charge storage section is raised by this protruding portion. As a result, the height of the waveguide for guiding light to the photoelectric conversion section is also increased, that is, the depth of the waveguide is increased.

The present disclosure solves the above-described conventional problem, and reduces the height of the upper end of the charge storage portion provided in the unit pixel, that is, the height thereof, thereby improving the light collection efficiency in the photoelectric conversion portion. for the purpose.

In order to achieve the above object, the present disclosure provides a structure in which a capacitor film and an upper electrode are provided on an interlayer insulating film in a charge storage portion provided in a unit pixel.

Specifically, the present disclosure is directed to a solid-state imaging device, and has taken the following solutions.

That is, one aspect of the present disclosure is a semiconductor substrate, a photoelectric conversion unit provided on the semiconductor substrate, an interlayer insulating film provided over the semiconductor substrate, and provided on the photoelectric conversion unit in the interlayer insulating film, A waveguide for introducing received light into a photoelectric conversion portion, a charge storage portion having a lower electrode, a capacitive film, and an upper electrode which are sequentially laminated on at least sidewalls of the waveguide, and a plurality of charge storage portions provided inside the interlayer insulating film. and a wiring layer. The lower electrode is electrically connected to at least one wiring layer of the plurality of wiring layers on the side wall of the waveguide, and the capacitive film and the upper electrode extend to the upper edge of the waveguide in the interlayer insulating film. ing.

According to the present disclosure, the height of the upper end of the charge storage section provided in the unit pixel is reduced to improve the light collecting efficiency in the photoelectric conversion section.

FIG. 1 is a cross-sectional view showing a unit pixel of a solid-state imaging device according to the first embodiment of the present disclosure. FIG. 2 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 3 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 4 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 5 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 6 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 7 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 8 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 9 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 10 is a cross-sectional view showing one step of the method for manufacturing the solid-state imaging device according to the first embodiment of the present disclosure. FIG. 11 is a cross-sectional view showing a unit pixel of a solid-state imaging device according to a modified example of the first embodiment of the present disclosure; FIG. 12 is a plan view showing a unit pixel of a solid-state imaging device according to the second embodiment of the present disclosure; 13 is a cross-sectional view taken along line XIII--XIII of FIG. 12. FIG.

An imaging device according to the first embodiment includes a semiconductor substrate, a photoelectric conversion section provided on the semiconductor substrate, an interlayer insulating film provided on the semiconductor substrate, and a photoelectric conversion section provided on the interlayer insulating film. a waveguide for introducing received light into the photoelectric conversion portion; a charge storage portion having a lower electrode, a capacitive film, and an upper electrode sequentially laminated on at least a side wall of the waveguide; wiring layers. The lower electrode is electrically connected to at least one wiring layer of the plurality of wiring layers on the side wall of the waveguide, and the capacitive film and the upper electrode extend to the upper edge of the waveguide in the interlayer insulating film. there is

According to this, a charge storage section having a lower electrode, a capacitive film and an upper electrode which are sequentially laminated on the side wall is provided at least on the side wall of the waveguide, and the capacitive film and the upper electrode are formed in the interlayer insulating film. It extends to the upper edge of the waveguide. On the other hand, the lower electrode is electrically connected to at least one wiring layer among the plurality of wiring layers on the side wall of the waveguide. For this reason, the charge storage portion has the thickness of only the capacitor film and the upper electrode at the upper edge of the waveguide in the interlayer insulating film, so that the height of the wiring layer at the upper end of the charge storage portion can be reduced. That is, since the height can be reduced, the light collecting efficiency in the photoelectric conversion section can be improved. Also, by providing the charge storage section in the waveguide, it becomes possible to miniaturize the layout.

In the first embodiment, the lower electrode is connected to the lower wiring layer among the plurality of wiring layers, and the upper electrode has its upper end portion connected to the uppermost wiring layer among the plurality of wiring layers on the upper surface of the interlayer insulating film. It may be connected with a layer.

According to this, since the lower electrode is connected to the lower wiring layer among the plurality of wiring layers, conduction is possible even if the upper end is not provided on the upper surface of the interlayer insulating film. In addition, since the upper electrode extends to the upper edge of the interlayer insulating film together with the capacitor film and the upper end of the upper electrode is connected to the uppermost wiring layer of the wiring layers on the upper surface of the interlayer insulating film, the charge storage section is not required. capacity can be secured.

In this case, the thickness of the upper electrode on the uppermost wiring layer may be greater than the thickness of the other portions.

According to this, since the upper electrode is the only component having a height in the connection portion of the upper electrode wiring in the charge storage portion, even if the thickness is made larger than that of other portions, the reduction in height is impaired. never Moreover, in the case of a configuration in which a floating diffusion portion is provided below this connection portion, it functions as a light shielding film for the floating diffusion portion.

In the first embodiment, the thickness of the bottom electrode may be greater than the thickness of the top electrode on the sidewalls of the waveguide.

According to this, since the lower electrode does not extend to the upper edge of the interlayer insulating film, it is possible to reduce the height even if the side wall upper portion is thicker than the upper electrode. Therefore, it is possible to improve the light collection efficiency without increasing the height of the charge storage section on the interlayer insulating film.

In the first embodiment, the waveguide is embedded with a buried insulating film, and the buried insulating film may be a high refractive index insulating film.

According to this, the efficiency of condensing light to the waveguide can be further improved.

In this case, the high refractive index insulating film may be a silicon nitride film.

According to this, even if the silicon nitride film has high internal stress and tends to peel off, film peeling does not easily occur due to the reduction in height.

In the first embodiment, the charge storage portion may have an opening exposing the semiconductor substrate at the bottom of the waveguide.

According to this, the photoelectric conversion section is positioned below the opening provided in the charge storage section, and when metal is used for the electrode film, incident light is reflected at the bottom of the charge storage section Therefore, the efficiency of collecting light can be increased.

In this case, the end surface of the charge storage portion on the side of the opening may form a stepped portion between the upper electrode and the capacitor film and/or between the capacitor film and the lower electrode.

According to this, the upper electrode and the lower electrode are not flush with each other at the end face of the charge storage section on the side of the opening, and a certain insulating distance is ensured. can be prevented from leaking.

In the first embodiment, the charge storage portion may have the capacitive film and the upper electrode removed, leaving the lower electrode at the bottom of the waveguide.

In this case, the lower electrode may be a transparent electrode.

According to this, even if the lower electrode is left, the light collection efficiency does not decrease.

In the first embodiment, the semiconductor substrate further includes a floating diffusion portion that accumulates charges converted by the photoelectric conversion portion. may be placed on the side.

According to this, by arranging the floating diffusion part in the region below the part of the upper electrode provided on the side wall of the waveguide in the charge accumulation part or on the interlayer insulating film, the part extending to the upper edge of the waveguide , the upper electrode functions as a shield. As a result, the floating diffusion portion is less likely to be affected by the received light, so that it is possible to secure the transistor characteristics of an amplifying transistor or the like.

In this case, the floating diffusion portion is provided so as to overlap the portion of the upper electrode extending to the upper edge portion of the waveguide in plan view.

As described above, according to the solid-state imaging device according to the present disclosure, since the charge storage section can be provided in the waveguide, it is possible to increase the capacity and save space.

Hereinafter, embodiments of the present disclosure will be described in detail based on the drawings. The following description of preferred embodiments is merely exemplary in nature and is not intended to limit the disclosure, its applicability, or its uses. Moreover, in each drawing, the same code|symbol is attached|subjected to the substantially same structure, and the description is abbreviate|omitted. Also, the dimensional ratios of the constituent members are for convenience only and do not represent actual dimensional ratios.

(First embodiment)
A first embodiment of the present disclosure will be described with reference to the drawings.

FIG. 1 shows an example of a solid-state imaging device according to the first embodiment. Here, a unit pixel in the solid-state imaging device 100 is shown.

As shown in FIG. 1, a solid-state imaging device 100 according to the present embodiment has pixels formed inside a semiconductor substrate 101 made of silicon (Si), for example, and on the main surface of the semiconductor substrate 101. . The conductivity type of semiconductor substrate 101 may be either p-type or n-type. Further, the main surface of the semiconductor substrate 101 means the surface on which light is incident, that is, the light receiving surface.

Above the semiconductor substrate 101, a photoelectric conversion unit 102 consisting of a photodiode and a floating diffusion (FD) unit 103 for temporarily storing one of charges (electrons and holes) generated by the photoelectric conversion unit perform photoelectric conversion. It is formed spaced apart from the portion 102 .

A plurality of interlayer insulating films 201 , 202 and 203 and a plurality of wiring layers 104 , 105 and 106 formed therebetween are formed on the main surface of the semiconductor substrate 101 . Silicon oxide (SiO _x ), for example, can be used for the interlayer insulating films 201 , 202 , and 203 . A liner layer 202 a is formed between the interlayer insulating films 201 and 202 , and a liner layer 203 a is formed between the interlayer insulating films 202 and 203 . Silicon oxynitride (SiON) or silicon carbonitride (SiCN), for example, can be used for the liner layers 202a and 203a.

The wiring layer 104 and the wiring layer 105 thereon are electrically connected by a connection hole (hereinafter referred to as via) 105a according to specifications. Similarly, the wiring layer 105 and the wiring layer 106 thereon are electrically connected by vias 106a. Copper (Cu), for example, can be used for each wiring layer including vias.

A waveguide 107 exposing the main surface of the semiconductor substrate 101 is formed on the semiconductor substrate 101 above the photoelectric conversion portion 102 . A charge accumulation portion 108 that accumulates charges converted by the photoelectric conversion portion 102 is formed at least on the side wall of the waveguide 107 .

The charge storage section 108 has a lower electrode 109 , a capacitive film 110 and an upper electrode 111 which are sequentially laminated on the side wall of the waveguide 107 . Titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tantalum (Ta), or the like can be used for the lower electrode 109 and the upper electrode 111, for example.

A high dielectric film (High-k) such as silicon nitride (SiN), hafnium oxide (HfO), or zirconium oxide (ZrO) can be used for the capacitor film 110 .

A feature of this embodiment is that the lower electrode 109 is connected to a lower layer wiring among a plurality of wiring layers, for example, the wiring layer 104 . On the other hand, the upper electrode 111 has its upper end connected to the uppermost wiring among the plurality of wiring layers, for example, the wiring layer 106 , on the upper surface of the interlayer insulating film 204 . Note that the lower electrode 109 may be connected to, for example, the middle wiring layer 105 instead of the lowermost wiring layer 104 .

The interlayer insulating film 204, the waveguide 107 and the charge storage section 108 are covered with a high refractive index insulating film 112 as a buried insulating film. Here, for example, silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN) can be used for the high refractive index insulating film 112 . Among them, silicon nitride (SiN) having a high refractive index is preferable.

As described above, the lower electrode 109 according to this embodiment is not connected to the uppermost wiring layer 106 , that is, is not extended to the upper surface of the uppermost interlayer insulating film 204 . As a result, the height of the charge storage section 108 above the interlayer insulating film 204 can be reduced, and the height of the charge storage section 108 can be reduced.

In addition, since the lower electrode 109 is not connected to the uppermost wiring layer 106, conventionally at least a four-layer wiring layer was required, but in this embodiment, a three-layer wiring layer 104, Configurations at 105 and 106 are possible. Thereby, the height of the wiring layers 104, 105 and 106 having a three-layer structure can be reduced. For this reason, conventionally, since the height of a plurality of wiring layers is high, tetraethyl orthosilicate, which has a relatively large coefficient of thermal expansion, is used in the buried insulating film that embeds the deep waveguides 107 provided in the plurality of wiring layers. (Tetraethoxyl Orthosilicate: TEOS) film had to be used. If silicon nitride (SiN), which is a high refractive index insulating film, is used as the buried insulating film when the height of the wiring layer is high, the film thickness of SiN required to embed the waveguide 107 increases. Therefore, film peeling occurs due to the high stress of the SiN film in the outer peripheral portion of the semiconductor wafer. On the other hand, although the TEOS film is less prone to film peeling, it has a low refractive index and low light collection efficiency, and is extremely poor in properties as a waveguide for guiding light.

In this embodiment, since the wiring layer itself can be reduced in height, the SiN film for embedding the waveguide 107 can be reduced to a thickness equal to or less than the thickness at which film peeling occurs. Accordingly, in this embodiment, it is possible to apply the SiN film as the buried insulating film of the waveguide 107 . That is, silicon nitride having a small thermal expansion coefficient can be used as the high refractive index insulating film 112 that embeds the waveguide 107 . Therefore, the light collection efficiency can be increased by the waveguide 107 that uses silicon nitride as the buried insulating film, which has a high refractive index and does not easily peel off.

Further, as shown in FIG. 1, the charge storage section 108 according to the present embodiment is provided with an opening 108a that exposes the semiconductor substrate 101 at the bottom of the waveguide 107 . When metal is used for the electrodes 109 and 111, this opening 108a eliminates the reflection of incident light on the upper portion of the bottom of the waveguide 107 in the charge storage section 108, so that the light collection efficiency can be further enhanced. .

Further, a step portion 111a is formed between the upper electrode 111 and the capacitor film 110 at the end face of the charge storage portion 108 on the side of the opening portion 108a. Due to this stepped portion 111a, the lower electrode 109 and the upper electrode 111 of the charge storage portion 108 are not flush with each other at the end face on the side of the opening 108a. Therefore, since a certain amount of insulation distance (creeping distance) is secured between the end face of the lower electrode 109 and the end face of the upper electrode 111, the occurrence of leakage current between the lower electrode 109 and the upper electrode 111 can be suppressed. A stepped portion may also be formed between the capacitor film 110 and the lower electrode 109 . In other words, the end surface of the capacitor film 110 should be configured to protrude more than at least one of the end surfaces of the lower electrode 109 and the upper electrode 111 to increase the insulation distance.

An example of the dimensions of each component of the semiconductor device 100 is listed below.

First, the height from the main surface of the semiconductor substrate 101 to the upper surface of the uppermost interlayer insulating film 204 is approximately 0.78 μm. The opening width of the upper end of the waveguide 107, that is, the opening width of the upper end of the interlayer insulating film 204 is about 4.9 μm. The opening length of the upper end of the waveguide 107 may also be about 4.9 μm, and in this case the opening shape (planar shape) of the upper end of the waveguide 107 is substantially square.

The thickness of the lower electrode 109 and the upper electrode 111 forming the charge storage section 108 can be about 10 nm when titanium nitride (TiN) is used as the electrode material.

Note that the thickness of the lower electrode 109 may be 40 nm or more in order to increase the light collection efficiency in the charge storage section 108 . This is because, when titanium nitride (TiN) is used for the upper electrode 111, the thickness of titanium nitride through which light can pass is 40 nm. Thereby, the light collection efficiency in the waveguide 107 can be improved.

Moreover, the thickness of the upper electrode 111 is preferably 30 nm or less in the region excluding the connection portion with the wiring layer 106 connected on the interlayer insulating film 204, that is, on the sidewall of the waveguide 107 and on the capacitive film 110. FIG. Therefore, the thickness of the upper electrode 111 on the sidewall of the waveguide 107 may be less than the thickness of the lower electrode 109 on the sidewall of the waveguide 107 . Thereby, the height of the charge storage unit 108 can be reduced. On the other hand, the thickness of the connection portion of the upper electrode 111 with the wiring layer 106 may be larger than the thickness of the sidewall of the waveguide 107 and the upper portion of the capacitor film 110, and is preferably about 40 nm or more and 60 nm or less. This provides a low profile and a light shielding function for the FD section 103 .

Silicon nitride (SiN) having a thickness of about 25 nm, for example, can be used for the capacitor film 110 . The film thickness of the capacitor film 110 can be freely set according to the required unit capacity.

Further, when silicon nitride is used, the high refractive index insulating film 112 embedding the waveguide 107 preferably has a thickness of 2.0 μm or less on the uppermost interlayer insulating film 204 . Thereby, peeling of the high refractive index insulating film 112 can be suppressed.

(Manufacturing method of solid-state imaging device)
A method for manufacturing the solid-state imaging device according to the first embodiment will be described below with reference to FIGS.

First, as shown in FIG. 2, each pixel on the main surface side of a semiconductor substrate 101 made of silicon is ion-implanted. A photoelectric conversion portion 102 and a floating diffusion (FD) portion 103 are selectively formed.

Subsequently, a Cu multilayer wiring structure is formed by a dual damascene method on the main surface of the semiconductor substrate 101 on which the photoelectric conversion section 102 and the FD section 103 are formed. In the dual damascene method, a lower wiring layer 104 is formed, and then a liner layer 202a and an upper interlayer insulating film 202 are deposited by chemical vapor deposition (CVD). Subsequently, wiring trenches and vias are patterned by lithography. After that, trenches and vias are formed inside the interlayer insulating film 202 by dry etching. Subsequently, by Physical Vapor Deposition (PVD) method, a barrier film that suppresses Cu diffusion and a Cu seed layer for current flow during electroplating are deposited on the inner wall surfaces of the trenches and vias. do. After that, a Cu film is embedded in the trenches and vias by a Cu electroplating method. Further, the excessive Cu film and the barrier film on the surface of the wiring layer are removed by chemical mechanical polishing (CMP) to form the wiring layer 105a. By repeating this process, a Cu multi-layer wiring structure having a desired number of wirings is obtained by the dual damascene method.

Next, in FIG. 3, a resist (not shown) for forming a waveguide is deposited on the interlayer insulating film 203 by lithography, and dry etching is performed using the deposited resist film as a mask. As a result, waveguides 107 are formed in the interlayer insulating films 201 , 202 and 203 , exposing the side surfaces of the underlying wiring layer 104 . As an etching gas in this case, for example, a carbon fluoride (CF)-based gas may be used. Thereafter, ashing is performed to remove the resist film.

Next, as shown in FIG. 4, the PVD method is used to deposit a lower electrode forming film 109A of the charge storage section 108 so as to cover the side wall and bottom surface of the waveguide 107. Next, as shown in FIG. Here, titanium nitride (TiN) is used as the material for forming the lower electrode formation film 109A. As a result, the lower electrode formation film 109A is connected to the underlying wiring layer 104 at at least two locations. A CVD method may be used to form the lower electrode formation film 109A.

Next, in FIG. 5, a resist (not shown) is deposited on the side wall of the waveguide 107 by lithography, and dry etching is performed using the deposited resist film as a mask. As a result, the upper surface of the interlayer insulating film 203 and the lower electrode forming film 109A on the bottom of the waveguide 107 are removed, and the lower electrode 109 is formed on the sidewall of the waveguide 107 and the peripheral portion of the bottom. . As an etching gas at this time, for example, a chlorine (Cl ₂ )-based gas may be used. Thereafter, ashing is performed to remove the resist film.

Next, as shown in FIG. 6, a capacitive film forming film 110A forming the charge storage portion 108 is deposited by the CVD method so as to cover at least the sidewalls and bottom surface of the waveguide 107. Next, as shown in FIG. Here, silicon nitride (SiN) is used for the capacitance film forming film 110A.

Next, in FIG. 7, a resist (FIG. 7) is applied to the interlayer insulating film 203 over the upper edge of the waveguide 107, the side wall of the waveguide 107, and the peripheral edge of the bottom of the waveguide 107 by lithography. not shown). Thereafter, dry etching is performed using the deposited resist film as a mask to remove the capacitance film forming film 110A from the upper edge of the waveguide 107 on the interlayer insulating film 203, the side walls of the waveguide 107, and the waveguide 107. Remove to leave it on the bottom rim. That is, inside the waveguide 107, the capacitive film 110 is formed by leaving the capacitive film forming film 110A so as to face the lower electrode 109. FIG. As an etching gas at this time, for example, a carbon fluoride (CF)-based gas may be used. Thereafter, ashing is performed to remove the resist film.

Next, as shown in FIG. 8, the PVD method is used to deposit an upper electrode forming film 111A so as to cover the upper surface of the interlayer insulating film 203 including the side walls and bottom surface of the waveguide 105. Next, as shown in FIG. Titanium nitride (TiN) is used for the upper electrode formation film 111A, similarly to the lower electrode formation film 109A. A CVD method may be used to form the upper electrode formation film 111A.

Next, in FIG. 9, the interlayer insulating film 203 is formed on the upper edge of the waveguide 107, the side wall of the waveguide 107, and the peripheral edge of the bottom of the waveguide 107 by the lithography method in the same manner as in FIG. A resist (not shown) is deposited as follows. In this step, the upper portion of the interlayer insulating film 203 of the deposited resist film is patterned so as to be connected to the upper wiring layer 106 at at least two locations. After that, dry etching is performed using the deposited resist film as a mask to remove the upper electrode forming film 111A from the upper edge of the waveguide 107 on the interlayer insulating film 203, the side walls of the waveguide 107, and the waveguide 107. Remove to leave it on the bottom rim. As a result, the upper electrode 111 of the charge storage section 108 is formed from the upper electrode formation film 111A. At this time, a stepped portion 111a is formed between the upper electrode 111 and the capacitor film 110 on the end surface of the charge storage portion 108 on the opening 108a side. As an etching gas at this time, for example, a chlorine (Cl ₂ )-based gas may be used. Thereafter, ashing is performed to remove the resist film.

Here, the upper electrode 111 is connected to the uppermost wiring layer 106 to form the charge storage section 108 inside the waveguide 107 , that is, on the side wall of the waveguide 107 . An opening 108 a exposing the semiconductor substrate 101 is formed at the bottom of the waveguide 107 of the charge storage section 108 . As a result, the waveguide 107 and the charge storage section 108 can be formed in the same region within the pixel, so that the pixel layout can be made finer. In addition, since the light incident on the waveguide 107 is reflected by the electrodes 109 and 111 of the charge storage section 108, the light collection efficiency of the photoelectric conversion section 102 is improved. As a result, it is possible to suppress optical noise components such as color mixture and stray light.

Next, as shown in FIG. 10, a high refractive index insulating film 112 is deposited on the interlayer insulating film 203 by CVD so that the waveguide 107 is embedded. After that, the surface of the deposited high refractive index insulating film 112 is flattened by the CMP method to form the waveguide 107 in which the high refractive index insulating film 112 is embedded.

As described above, the solid-state imaging device 100 according to the present embodiment can be manufactured. According to such a manufacturing method, the charge storage section 108 having the lower electrode 109 , the capacitive film 110 and the upper electrode 111 is provided with the lower electrode 109 only on the side wall of the waveguide 107 . On the other hand, a capacitive film 110 and an upper electrode 111 are provided from the sidewall of the waveguide 107 to the upper surface of the interlayer insulating film 203 having the uppermost wiring layer 106 . As a result, the height of the charge storage section 108 can be reduced by the film thickness of the lower electrode 109 of the charge storage section 108 .

In addition, the bottom of the waveguide 107 has an opening 108a from which the charge storage section 108 is removed. As a result, the light inside the waveguide 107 can be guided without being reflected at its bottom.

The reduction in the height of the charge storage section 108, the high refractive index insulating film (SiN film) 112 in the waveguide 107, and the opening 108a provided at the bottom of the waveguide 107 significantly improve the light collection efficiency. can be done.

Although copper (Cu) is used for the lower wiring layer 104 in this embodiment, the material is not limited to this, and a metal such as tungsten (W) can be used.

(One modification of the first embodiment)
A modified example of the first embodiment will be described below with reference to FIG.

FIG. 11 shows an example of the solid-state imaging device according to the first embodiment, and here shows a unit pixel in the solid-state imaging device 100A.

As shown in FIG. 11, in the solid-state imaging device 100A according to this modification, a transparent electrode is used for the lower electrode 109B that constitutes the charge storage section . Therefore, it is not necessary to provide the opening 108a at the bottom of the waveguide 107, and the bottom 109b is exposed above the bottom of the waveguide 107 in the lower electrode 109B.

Here, for the lower electrode 109B, indium tin oxide (ITO), In--Ga--ZnO ₄ (so-called IGZO), which is an amorphous oxide semiconductor, or the like can be used. The thickness of the lower electrode 109B may be, for example, about 10 nm.

Further, the thickness of the upper electrode 111 is, for example, 40 nm or more and 60 nm on the region excluding the connection portion with the wiring layer 106 connected on the interlayer insulating film 204, that is, on the side wall of the waveguide 107 and on the capacitor film 110. The following degree is preferable. Thus, in this modification, since a transparent electrode is used for the lower electrode 109B, when titanium nitride (TiN) is used for the upper electrode 111, the thickness through which light can pass is 40 nm. If the thickness is thicker than 40 nm, the height of the charge storage section 108 can be reduced without lowering the light collection efficiency.

On the other hand, the thickness of the upper portion of the wiring layer 106 in the upper electrode 111 is also preferably about 40 nm or more and 60 nm or less, for example. As a result, it is possible to obtain a low profile and a light shielding effect for the FD portion 103 .

Also in this modification, a stepped portion 111a may be formed between the end surfaces of the capacitive film 110 and the upper electrode 111 of the charge storage portion 108 on the bottom side. Thereby, current leakage between the lower electrode 109 and the upper electrode 111 can be suppressed.

As another modification, even when titanium nitride (TiN) is used for the lower electrode 109, if the thickness of the lower electrode 109 is set to be less than 40 nm, light can be transmitted even with the titanium nitride film. A configuration can be obtained that leaves only 109 at the bottom of waveguide 107 .

(Second embodiment)
A second embodiment of the present disclosure will be described below with reference to the drawings. 12 and 13 show an example of a solid-state imaging device according to the second embodiment. Here, a unit pixel in the solid-state imaging device 100B is shown.

In the second embodiment, when the FD portion 103 provided on the semiconductor substrate 101 is arranged below the connection portion of the upper electrode 111B with the upper wiring layer 106 so as to overlap each other in plan view, the upper portion Optimize the thickness of electrode 111B.

That is, the thickness of the connection portion of the upper electrode 111B with the wiring layer 106 is preferably, for example, about 40 nm or more and 60 nm or less. This is because, when titanium nitride (TiN) is used for the upper electrode 111B, the light-transmissible thickness of titanium nitride is 40 nm as described above. On the other hand, the thickness of the upper electrode 111B on the sidewall of the waveguide 107 and the upper portion of the capacitive film 110 is preferably 30 nm or less in order to reduce the height.

Moreover, the thickness of the portion of the lower electrode 109 on the side wall of the waveguide 107 is preferably 30 nm or less. Thereby, the height of the charge storage unit 108 can be reduced.

Also in the second embodiment, a modification can be applied in which a transparent electrode is used for the lower electrode 109 of the charge storage section 108 and the upper portion of the bottom portion of the waveguide 107 is left in the transparent electrode.

INDUSTRIAL APPLICABILITY The present disclosure can be used as a solid-state imaging device having a charge storage portion in a unit pixel, and can be used particularly as a method for improving light sensitivity.

100, 100A, 100B solid-state imaging device 101 semiconductor substrate 102 photoelectric conversion layer 103 floating diffusion (FD) section 104 wiring layer (lower layer)
106 wiring layer (upper layer)
107 Waveguide 108 Charge storage portion 108a Openings 109, 109B Lower electrode 109A Lower electrode formation film 110 Capacitance film 110A Capacitance film formation films 111, 111B Upper electrode 111A Upper electrode formation film 111a Step 112 High refractive index insulation film (buried insulation film)
203 Interlayer insulating film (upper layer)

Claims (10)

a semiconductor substrate;
a photoelectric conversion unit provided on the semiconductor substrate;
an interlayer insulating film provided on the semiconductor substrate;
a waveguide provided on the photoelectric conversion section in the interlayer insulating film and introducing received light to the photoelectric conversion section;
a charge storage section having a lower electrode, a capacitive film and an upper electrode, which are sequentially stacked on at least the side wall of the waveguide;
a plurality of wiring layers provided inside the interlayer insulating film,
the lower electrode is electrically connected to a lower wiring layer among the plurality of wiring layers on a side wall of the waveguide and does not extend to the upper surface of the interlayer insulating film ;
the capacitive film and the upper electrode extend to the upper surface of the interlayer insulating film ;
The upper electrode has an upper end connected to the uppermost wiring layer among the plurality of wiring layers on the upper surface of the interlayer insulating film,
Solid-state image sensor. In the solid-state imaging device according to claim 1,
The solid-state imaging device, wherein the thickness of the upper electrode on the wiring layer of the uppermost layer is larger than the thickness of other portions. In the solid-state imaging device according to claim 1 or 2,
A solid-state imaging device, wherein the thickness of the lower electrode is greater than the thickness of the upper electrode on the side wall of the waveguide. In the solid-state imaging device according to any one of claims 1 to 3,
The waveguide is embedded with an embedded insulating film,
The solid-state imaging device, wherein the embedded insulating film is a silicon nitride film. In the solid-state imaging device according to any one of claims 1 to 4,
The solid-state imaging device, wherein the charge storage section has an opening that exposes the semiconductor substrate at the bottom of the waveguide. In the solid-state imaging device according to claim 5,
A solid-state imaging device, wherein the end surface of the charge storage section on the side of the opening forms a stepped section at least one between the upper electrode and the capacitive film and between the capacitive film and the lower electrode. . In the solid-state imaging device according to any one of claims 1 to 4,
The solid-state imaging device, wherein the charge storage section is formed by removing the capacitive film and the upper electrode while leaving the lower electrode at the bottom of the waveguide. In the solid-state imaging device according to claim 7,
The solid-state imaging device, wherein the lower electrode is a transparent electrode. In the solid-state imaging device according to claim 1,
further comprising a floating diffusion portion provided on the semiconductor substrate for accumulating charges converted by the photoelectric conversion portion;
The solid-state imaging device, wherein the floating diffusion portion is arranged below a portion of the upper electrode that extends to the upper surface of the interlayer insulating film . In the solid-state imaging device according to claim 9,
The solid-state imaging device, wherein the floating diffusion portion overlaps a portion of the upper electrode extending to the upper surface of the interlayer insulating film in plan view.

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