JP7181843B2 - Wiring board and method for manufacturing wiring board - Google Patents

Description

The present invention relates to wiring boards.

Conventionally, there has been proposed a wiring board having a plurality of conductive layers formed of different materials on a base material (see, for example, Patent Document 1).

JP 2017-216315 A

In the wiring board as described above, it is desired to further improve the adhesiveness of the plurality of conductive layers.

The present invention has been made to solve the problems described above, and an object of the present invention is to provide a technique for improving adhesion between a plurality of conductive layers.

The present invention has been made to solve the above problems, and can be implemented as the following modes.

(1) According to one aspect of the present invention, a wiring board is provided. The wiring board includes a base material, a first conductive layer made of a first conductive material, the first conductive layer formed on the base material, and a second conductive material different from the first conductive material. a barrier layer of a conductive material formed on a portion of said first conductive layer; and a third conductive material different from said first conductive material and said second conductive material. a second conductive layer formed on the barrier layer; and an alloy layer made of an alloy containing the first conductive material and the second conductive material, and an alloy layer formed between one conductive layer and the barrier layer, wherein the first conductive layer has an upper surface of at least a portion of a portion where the barrier layer and the second conductive layer are not formed. exposed to the outside.

According to this configuration, since the alloy layer containing the first conductive material and the second conductive material is formed between the first conductive layer and the barrier layer, adhesion between the first conductive layer and the barrier layer is reduced. can improve sexuality. In addition, since the upper surface of at least a portion of the first conductive layer where the barrier layer and the second conductive layer are not formed is exposed to the outside, when forming a bump made of the first conductive material, By forming the bump on the exposed portion of the first conductive layer, the bonding strength of the bump can be ensured.

(2) In the wiring board of the above aspect, the first conductive layer has a thickness of a first portion where the alloy layer is not formed is thinner than a thickness of a second portion where the alloy layer is formed. good too. In this way, when the device is configured by mounting the elements on the wiring board, the size of the device can be reduced.

(3) In the wiring board of the above aspect, the first conductive layer may be exposed to the outside on the entire upper surface of the portion where the barrier layer and the second conductive layer are not formed. By doing so, it is possible to widen the range in which the bonding strength of the bumps can be ensured.

(4) According to another aspect of the invention, there is provided a method for manufacturing a wiring board. This method of manufacturing a wiring board includes a preparation step of preparing a base material with a first conductive layer, in which a first conductive layer made of a first conductive material and having a first wiring pattern formed thereon is laminated on the base material. forming a barrier layer of a second conductive material different from the first conductive material on the first conductive layer, the barrier layer being formed of an alloy containing the first conductive material and the second conductive material; a first layer forming step of forming an alloy layer between the first conductive layer and the barrier layer; and a third conductive material made of a third conductive material different from the first conductive material and the second conductive material. a second layer forming step of forming two conductive layers on the upper surface of the barrier layer; forming a protective film for forming a second wiring pattern on the second conductive layer; and a wiring pattern forming step of etching a part of the barrier layer to form the second wiring pattern; and an etching step of etching the alloy layer and the surface of the first conductive layer. Prepare. According to this manufacturing method, the above wiring board can be manufactured easily.

It should be noted that the present invention can be implemented in various forms, for example, in the form of a product including a wiring board, a method of manufacturing a product including a wiring board, and the like.

1 is an explanatory diagram schematically showing a planar configuration of a wiring board according to a first embodiment of the present invention; FIG. FIG. 2 is an explanatory view schematically showing a cross-sectional configuration (a section taken along line AA) of a wiring substrate; It is process drawing which shows the manufacturing method of a wiring board.

<Embodiment>
- Configuration of the wiring board 10:
FIG. 1 is an explanatory view schematically showing a planar configuration of a wiring board 10 according to a first embodiment of the invention. As shown, the wiring board 10 comprises two first conductive layers 2 and two second conductive layers 6, each second conductive layer 6 being a part of the first conductive layer 2. formed on top. In FIG. 1, the portion of the first conductive layer 2 where the second conductive layer 6 is formed is indicated by a broken line. In the following description, a portion of the first conductive layer 2 where the second conductive layer 6 is not formed, in other words, an exposed portion (indicated by a solid line in FIG. 1) will be referred to as a "first portion 2P1". A portion of the layer 2 where the second conductive layer 6 is formed (indicated by a dashed line in FIG. 1) is called a "second portion 2P2".

FIG. 2 is an explanatory view schematically showing a cross-sectional configuration (AA cross section) of the wiring board 10. As shown in FIG. FIG. 2 shows the AA section in FIG. However, FIG. 2 is a partially omitted and simplified explanatory diagram, and the dimensional ratio is not accurate. The wiring board 10 includes a base material 1 , a first conductive layer 2 , a barrier layer 4 , a second conductive layer 6 and an alloy layer 8 . The first conductive layer 2 is formed on the substrate 1 with the first bonding layer 3 and the second bonding layer 5 interposed therebetween. The barrier layer 4 is formed on part of the first conductive layer 2 with the alloy layer 8 interposed therebetween. A second conductive layer 6 is formed on the barrier layer 4 .

The base material 1 is an insulating flat plate. In this embodiment, it is made of aluminum nitride (AlN) ceramics. Since aluminum nitride has high heat dissipation and high strength, it can be suitably used for parts that generate a large amount of heat, such as power semiconductor modules. Materials forming the substrate 1 are not limited to those of the present embodiment, and examples thereof include alumina (Al ₂ O ₃ ), alumina zirconia (Al ₂ O ₃ /ZrO ₂ ), silicon nitride (Si ₃ N ₄ ), and silicon carbide. Ceramics such as (SiC) may be used, resins such as glass, glass epoxy, thermoplastic resin and thermosetting resin, paper phenol, paper epoxy, glass composite, low temperature co-fired ceramics (LTCC), insulation of these The member may be formed by a metal member or the like formed on the surface.

In this embodiment, the first conductive material forming the first conductive layer 2 contains gold (Au) as a main component. Gold (Au) and gold alloys can be used as the first conductive layer material. Since the first conductive layer 2 is mainly composed of gold, it is soft and has a smooth surface. Here, the main component is a component containing 99% or more.

The second conductive material forming barrier layer 4 contains titanium (Ti) as a main component. Since titanium has a high melting point, it functions as a so-called barrier metal. As the second conductive material, for example, titanium (Ti), titanium nitride (TiN), titanium alloys (including, for example, zirconium (Zr), hafnium (Hf), etc.), etc. can be used.

A third conductive material forming the second conductive layer 6 contains aluminum (Al) as a main component. As the third conductive material, aluminum (Al) or an aluminum alloy (eg, Al--Si--Cu, Al--Cu, etc.) can be used.

The alloy layer 8 is an alloy layer made of an alloy containing the first conductive material and the second conductive material. Since the alloy layer 8 is formed between the first conductive layer 2 and the barrier layer 4, the adhesion between the first conductive layer 2 and the barrier layer 4, which are formed of a material containing a high-melting-point metal as a main component, is improved. can be improved.

As described above, the first conductive layer 2 is formed on the substrate 1 with the first bonding layer 3 and the second bonding layer 5 interposed therebetween. The first bonding layer 3, like the barrier layer 4, is made of a second conductive material. The fourth conductive material forming the second bonding layer 5 contains palladium (Pd) as a main component. Since titanium is easily oxidized, the second bonding layer 5 containing palladium as a main component is formed on the first bonding layer 3 in the manufacturing process.

As shown in FIGS. 1 and 2, in the wiring board 10 of the present embodiment, the first conductive layer 2 has the entire upper surface of the portion where the barrier layer 4 and the second conductive layer 6 are not formed is exposed to the outside. there is As described above, the main component of the first conductive material forming the first conductive layer 2 is gold (Au), so the first conductive layer 2 is soft and has a smooth surface. Therefore, when bumps containing gold (Au) as a main component are formed on the first conductive layer 2, the bonding strength of the bumps can be ensured, and deterioration in bondability and reliability can be suppressed.

As shown in FIG. 2, in the wiring board 10 of the present embodiment, the first conductive layer 2 has the thickness T1 of the first portion 2P1 where the second conductive layer 6 is not formed, and the thickness T1 of the first portion 2P1 where the second conductive layer 6 is formed. thinner than the thickness T2 of the second portion 2P2. In the present embodiment, since the outer circumference of the second conductive layer 6 and the outer circumference of the alloy layer 8 match, in other words, the first conductive layer 2 has the thickness T1 of the first portion 2P1 where the alloy layer 8 is not formed. is thinner than the thickness T2 of the second portion 2P2 on which the alloy layer 8 is formed. Therefore, when an element such as a light-emitting diode is mounted on the wiring board 10 of the present embodiment to configure a device, the size of the device can be reduced. The thickness of the first conductive layer 2 can be measured, for example, by fluorescent X-ray film thickness measurement.

- Manufacturing method of wiring board 10:
3A to 3D are process diagrams showing a method of manufacturing the wiring board 10. FIG. FIG. 3 schematically illustrates a cross section of a portion of the wiring board 10 (a cross section taken along line AA in FIG. 1).

In step P102, the base material 12 with the first conductive layer, which includes the base material 1, the first bonding layer 3, the second bonding layer 5, and the first conductive layer 2, is prepared. A predetermined first wiring pattern is formed on the first conductive layer 2 . In step P102, the substrate 12 with the first conductive layer formed in advance may be prepared, or the first bonding layer 3, the second bonding layer 5, and the first conductive layer 2 are formed on the substrate 1. You may form by a well-known method. For example, the first bonding layer 3 and the second bonding layer 5 may be formed by sputtering, vapor deposition, or the like, and the first conductive layer 2 may be formed by plating or the like. The step P102 in this embodiment is also called a "preparation step".

In step P104, the barrier layer 4 is formed on the base material 12 with the first conductive layer and the alloy layer 8 is formed between the first conductive layer 2 and the barrier layer 4 by sputtering. The first conductive material forming the first conductive layer 2 and the barrier layer 4 are formed by forming the barrier layer 4 on the substrate 12 with the first conductive layer by a method such as sputtering that imparts high energy. An alloy layer 8 made of an alloy containing a second conductive material is formed. The alloy layer 8 may be formed together with the barrier layer 4 by another method of applying high energy such as high thermal vapor deposition. Process P104 is also called a "first layer forming process".

In step P106, a second conductive layer 6 is formed on the barrier layer 4 by sputtering. The second conductive layer 6 may be formed by other known methods such as vapor deposition. The step P104 is also called a "second layer forming step".

In step P108, a resist 20 (protective film) for forming a second wiring pattern different from the first wiring pattern is formed on the second conductive layer 6 by a known method such as photolithography or printing. After the second conductive layer 6 is etched, the barrier layer 4 is etched. Thereby, the second wiring pattern is formed. In step P108, the alloy layer 8 and the first conductive layer 2 remain because they are difficult to etch. Process P108 is also called a "wiring pattern forming process".

In step P110, the alloy layer 8 and the surface of the first conductive layer 2 are etched with the resist 20 still attached. The process P110 is also called an "etching process".

In step P112, the resist 20 is removed, and the wiring board 10 is completed.

According to this manufacturing method, in step P104, the alloy layer 8 is formed by forming the barrier layer 4 by applying high energy. Therefore, the adhesion between the first conductive layer 2 and the barrier layer 4 can be improved, and the occurrence of peeling of the first conductive layer 2 and the barrier layer 4 can be reduced.

Further, according to this manufacturing method, since the surfaces of the alloy layer 8 and the first conductive layer 2 are etched in the step P110, the first conductive layer 2 can be exposed to the outside. Furthermore, since the surface of the first conductive layer 2 is etched, the alloy layer 8 remaining on the surface of the first conductive layer 2 is removed, and the cleanliness of the surface of the first conductive layer 2 can be improved. Therefore, by using the wiring substrate 10 manufactured by this manufacturing method, it is possible to improve the bonding strength during bonding. The absence of the alloy layer 8 on the surface of the first conductive layer 2 can be determined by cross-sectional TEM-EDX (energy dispersive X-ray spectroscopy) mapping. Specifically, when the composition of the second conductive material forming the barrier layer 4 is below the detection limit in cross-sectional TEM-EDX mapping, it can be determined that "the alloy layer 8 is absent."

As described above, according to the wiring board 10 of the present embodiment, the alloy layer 8 containing the first conductive material and the second conductive material is formed between the first conductive layer 2 and the barrier layer 4. Therefore, the adhesion between the first conductive layer 2 and the barrier layer 4 can be improved, and the occurrence of peeling between the first conductive layer 2 and the barrier layer 4 can be reduced.

In addition, since the entire upper surface of the portion of the first conductive layer 2 where the barrier layer 4 and the second conductive layer 6 are not formed is exposed to the outside, when forming a bump made of the first conductive material Moreover, by forming the bumps on the exposed portions of the first conductive layer 2, the bonding strength of the bumps can be ensured.

In the first conductive layer 2, the thickness T1 of the first portion 2P1 where the alloy layer 8 is not formed is thinner than the thickness T2 of the second portion 2P2 where the alloy layer 8 is formed. When the device is configured by mounting the above, the size of the device can be reduced.

According to the manufacturing method of this embodiment, the wiring board 10 can be manufactured easily. Moreover, since the alloy layer 8 remaining on the surface of the first conductive layer 2 is removed by etching, the cleanliness of the surface of the first conductive layer 2 can be improved.

<Modification of this embodiment>
The present invention is not limited to the above-described embodiments, and can be implemented in various aspects without departing from the scope of the invention. For example, the following modifications are possible.

- The main component of the 1st conductive material which forms the 1st conductive layer 2, and the main component of the 3rd conductive material which forms the 2nd conductive layer 6 are not limited to the said embodiment. For example, it can be formed of a single layer or laminated structure of metals such as Al, Au, Pt, Ti, Cu, Pd, Rh, Ni, W, Mo, Cr, Ag, or alloys thereof. Alternatively, a conductive material such as ITO (Indium Tin Oxide) may be used.

In the above-described embodiment, the first conductive layer 2 of the wiring board 10 shows an example in which the entire upper surface of the portion where the barrier layer 4 and the second conductive layer 6 are not formed is exposed to the outside. At least part of the upper surface of the portion where the layer 4 and the second conductive layer 6 are not formed should be exposed to the outside. Even in this case, by forming the bumps on the portions where the first conductive layer 2 is exposed, the bonding strength of the bumps can be ensured.

- In the wiring board 10 of the above embodiment, the thickness T1 of the first portion 2P1 of the first conductive layer 2 does not have to be thinner than the thickness T2 of the second portion 2P2.

- Although the outer periphery of the second conductive layer 6 and the outer periphery of the alloy layer 8 match each other in the above embodiment, they do not have to match. For example, etching may cause the outer periphery of the second conductive layer 6 to be inside the outer periphery of the alloy layer 8 . Even in such a case, if the thickness T1 of the first portion 2P1 of the first conductive layer 2 where the alloy layer 8 is not formed is thinner than the thickness T2 of the second portion 2P2 where the alloy layer 8 is formed, When devices are mounted on the wiring board 10 to configure the device, the size of the device can be reduced.

- In the above-described embodiment, an example in which two first conductive layers 2 and two second conductive layers 6 are formed on one base material 1 is shown. The number of two conductive layers 6 is not limited to the above embodiment. For example, one first conductive layer 2 and one second conductive layer 6 may be formed on one base material 1, or three or more layers may be formed. Also, the number of the first conductive layers 2 and the number of the second conductive layers 6 may be different.

- In the above-described embodiment, an example in which the first bonding layer 3 is formed from the second conductive material is shown, but it may be formed from a conductive material containing other metals as a main component, such as palladium. .

- In the above embodiment, the first conductive layer 2 is formed on the base material 1 via the first bonding layer 3 and the second bonding layer 5, but the first conductive layer 2 is the bonding layer. It may be configured such that it is formed directly on the substrate 1 without intervening. Also, a configuration including three or more bonding layers may be employed.

- A third conductive layer made of another conductive material may be provided on the second conductive layer 6 . For example, the second conductive layer 6 may be made of a conductive material containing palladium as a main component, and a third conductive layer made of a conductive material containing aluminum as a main component may be provided on the second conductive layer 6. good.

- The manufacturing method of the wiring board 10 is not limited to the manufacturing method of the above embodiment. In the above-described embodiment, an example of forming the second wiring pattern of the second conductive layer 6 by the subtractive method was shown. It may be formed directly. Also, the step P110 may not be provided. However, including the step P110 is preferable because the cleanliness of the surface of the first conductive layer 2 can be improved.

The present aspect has been described above based on the embodiments and modifications, but the above-described embodiments are intended to facilitate understanding of the present aspect, and do not limit the present aspect. This aspect may be modified and modified without departing from the spirit and scope of the claims, and this aspect includes equivalents thereof. Also, if the technical features are not described as essential in this specification, they can be deleted as appropriate.

REFERENCE SIGNS LIST 1 Base material 2 First conductive layer 2P1 First part 2P2 Second part 3 Second barrier layer 4 First barrier layer 5 Third conductive layer 6 Second conductive layer 8 Alloy layer 10 Wiring substrate 12 Base material with first conductive layer 20 Resist

Claims (2)

A wiring board,
a substrate;
a first conductive layer of a first conductive material, the first conductive layer formed on the substrate;
a barrier layer of a second conductive material different from the first conductive material, the barrier layer formed on a portion of the first conductive layer;
a second conductive layer of a third conductive material different from the first conductive material and the second conductive material, the second conductive layer formed on the barrier layer;
an alloy layer made of an alloy containing the first conductive material and the second conductive material, the alloy layer formed at least between the first conductive layer and the barrier layer;
with
The first conductive layer is
The upper surface of at least a part of the portion where the barrier layer and the second conductive layer are not formed is exposed to the outside, and the thickness of the first portion where the alloy layer is not formed is equal to the thickness of the alloy layer. characterized by being thinner than the thickness of the second part ,
wiring board. A method for manufacturing a wiring board,
A preparation step of preparing a substrate with a first conductive layer, in which a first conductive layer made of a first conductive material and having a first wiring pattern is laminated on the substrate;
forming a barrier layer of a second conductive material different from the first conductive material on the first conductive layer, and an alloy of an alloy containing the first conductive material and the second conductive material; a first layer forming step of forming a layer between the first conductive layer and the barrier layer;
a second layer forming step of forming a second conductive layer made of a third conductive material different from the first conductive material and the second conductive material on the upper surface of the barrier layer;
forming a protective film for forming a second wiring pattern on the second conductive layer, and etching a part of the second conductive layer and the barrier layer to form the second wiring pattern; a wiring pattern forming step;
an etching step of etching the alloy layer and the surface of the first conductive layer;
characterized by comprising
A method for manufacturing a wiring board.

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