JP7180623B2 - semiconductor equipment - Google Patents

Description

The present invention relates to semiconductor devices.

A capacitor with increased capacitance is formed by forming a fine groove (also referred to as a trench) on the surface of a semiconductor substrate to increase the surface area and forming MIM (Metal Insulator Metal) on the surface to form a capacitor. It is known (Patent Document 1).

In addition, a capacitor is formed in one layer on a substrate, poly-Si is deposited on the surface of the capacitor, and a trench is formed to fabricate a capacitor. Reference 2) has also been proposed. This method requires an advanced process such as densely depositing Si on the surface of the trench capacitor once formed on the substrate, resulting in high device cost.
For this reason, a semiconductor device has been proposed in which a plurality (or two or more) of substrates on which trench capacitors are formed are integrated by bonding them together to increase the capacity density per device to achieve a large capacity (Patent Reference 3).

U.S. Patent Application Publication No. 2018/0350790 U.S. Patent Application Publication No. 2018/0308638 WO2018/174191

However, in a semiconductor device having a structure in which substrates are bonded to each other as shown in Patent Document 3, stress concentrates on the terminal portion, which is a contact point between the substrates, depending on the environment during mounting or use of the semiconductor element. Therefore, there is a possibility that cracks may occur.
In particular, since substrates made of the same material are bonded together, stress tends to concentrate on the terminals, which are the points of contact between the substrates.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a semiconductor device having a structure in which substrates are bonded together, and which has a structure in which cracks are less likely to occur at the contact points between the substrates when a semiconductor element is mounted or used. aim.

A semiconductor device of the present invention comprises: a first substrate provided with a first electrode layer, a first dielectric layer and a second electrode layer provided in a trench formed on a first Si substrate; 2. A semiconductor device including a structure in which a second substrate provided with a second capacitor section including a third electrode layer provided in a trench section formed on a 2Si substrate, a second dielectric layer, and a fourth electrode layer are laminated. The electrode forming the first capacitor section of the first substrate and the electrode forming the second capacitor section of the second substrate are electrically connected by at least two conductive pillars having a predetermined height. and a strength holding member is arranged in a space surrounded by the at least two conductive pillars, the first substrate, and the second substrate.

According to the present invention, it is possible to provide a semiconductor device having a structure in which substrates are bonded together, and which has a structure in which cracks are less likely to occur at the contact points between the substrates when a semiconductor element is mounted or used. can.

FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device according to a first embodiment of the invention. FIG. 2 is a cross-sectional view schematically showing an example of a semiconductor device having a strength retaining member made of metal. FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along the line AA. FIG. 4 is a cross-sectional view schematically showing an example of the semiconductor device according to the second embodiment of the invention. FIG. 5 is a cross-sectional view schematically showing an example of the semiconductor device according to the third embodiment of the invention. FIG. 6 is a cross-sectional view schematically showing an example of a semiconductor device according to the fourth embodiment of the invention. FIG. 7 is a cross-sectional view schematically showing an example of a semiconductor device according to the fourth embodiment of the invention. FIG. 8 is a process diagram schematically showing how the first substrate and the second substrate are laminated and bonded together so that the directions of the trench portions face each other. FIG. 9 is a process diagram schematically showing how the first substrate and the second substrate are stacked and bonded together so that the directions of the trench portions are the same.

A semiconductor device according to the present invention will be described below.
However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. A combination of two or more desirable configurations of the embodiments of the present invention described below is also the present invention.

A semiconductor device of the present invention comprises: a first substrate provided with a first electrode layer, a first dielectric layer and a second electrode layer provided in a trench formed on a first Si substrate; 2. A semiconductor device including a structure in which a second substrate provided with a second capacitor section including a third electrode layer provided in a trench section formed on a 2Si substrate, a second dielectric layer, and a fourth electrode layer are laminated. The electrode forming the first capacitor section of the first substrate and the electrode forming the second capacitor section of the second substrate are electrically connected by at least two conductive pillars having a predetermined height. and a strength holding member is arranged in a space surrounded by the at least two conductive pillars, the first substrate, and the second substrate.

[Semiconductor Device of First Embodiment]
FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device according to a first embodiment of the invention.
The semiconductor device 1 shown in FIG. 1 includes a structure in which a first substrate 10 and a second substrate 20 are stacked.
The first substrate 10 and the second substrate 20 are electrically connected by at least two conductive pillars 30 (conductive pillars 31a and 32a and conductive pillars 31b and 32b) having a predetermined height.
A strength holding member 40 is arranged in a space surrounded by at least two conductive pillars 30 , the first substrate 10 and the second substrate 20 .
The conductive pillar 31a and the conductive pillar 32a and the conductive pillar 31b and the conductive pillar 32b are bonded with the conductive adhesive 35a and the conductive adhesive 35b, respectively.

The first substrate 10 includes a first Si substrate 11 having a first main surface 11a and a second main surface 11b facing the first main surface 11a. has a trench portion 50 of .
In the trench portion 50 , the first electrode layer 12 , the first dielectric layer 13 and the second dielectric layer 12 are arranged in the thickness direction from the second main surface 11 b of the first Si substrate 11 toward the first main surface 11 a (upward direction in the drawing). A first capacitor section 15 is provided which is formed by laminating the electrode layers 14 in this order.
By providing the first dielectric layer 13 between the first electrode layer 12 and the second electrode layer 14, the first capacitance section 15 functions as a capacitor.
The second electrode layer 14 is formed extending from the trench portion 50 to the first main surface 11 a of the first Si substrate 11 . A protective layer 16 is provided on the surface of the second electrode layer 14 . The conductive pillar 31a and the conductive pillar 31b pass through the protective layer 16 in the thickness direction and are electrically connected to the second electrode layer 14, which is an electrode forming the first capacitor section 15 of the first substrate 10. FIG.
Note that the protective layer is a layer made of an insulating material.

The second substrate 20 includes a second Si substrate 21 having a third main surface 21a and a fourth main surface 21b facing the third main surface 21a. has a trench portion 60 of .
In the trench portion 60, the third electrode layer 22, the second dielectric layer 23, and the fourth electrode layer 22, the second dielectric layer 23, and the fourth electrode layer 22 are formed in the thickness direction (downward direction in the drawing) from the fourth main surface 21b of the second Si substrate 21 toward the third main surface 21a. A second capacitor section 25 is provided in which the electrode layers 24 are stacked in order.
By providing the second dielectric layer 23 between the third electrode layer 22 and the fourth electrode layer 24, the second capacitor section 25 functions as a capacitor.
The fourth electrode layer 24 is formed extending from the trench portion 60 to the third main surface 21 a of the second Si substrate 21 . A protective layer 26 is provided on the surface of the fourth electrode layer 24 . The conductive pillars 32a and 32b pass through the protective layer 26 in the thickness direction and are electrically connected to the fourth electrode layer 24, which is an electrode forming the second capacitor section 25 of the second substrate 20. FIG.

Two trench portions 50 and two trench portions 60 are provided on each of the first substrate 10 and the second substrate 20 on the step surface shown in FIG. 1, but the number thereof is not limited.
Moreover, when the semiconductor device is viewed from the top, the trench portions may be arranged side by side in the vertical direction and the horizontal direction. The trench portions may be arranged in a grid pattern or in a zigzag pattern.
As for the cross-sectional shape of the trench portion, the width from the opening to the tip may be the same shape as shown in FIG. Also, the cross-sectional shape of the trench portion may be a V-shape in which the width narrows from the opening of the trench toward the tip. When the cross-sectional shape of the trench portion is V-shaped, the overall shape of the trench portion may be conical, pyramidal, or wedge-shaped.

The first substrate 10 and the second substrate 20 are stacked with the first main surface 11a of the first Si substrate 11 and the third main surface 21a of the second Si substrate 21 facing each other, thereby forming trench portions 50 and 60. are laminated so that the directions of
If the layers are stacked so that the directions of the trench portions face each other, there is no trench structure on the surface on which wire bonding is performed when the semiconductor device is mounted by wire bonding. There is no damage to the trench structure due to pressure, and it is possible to suppress deterioration of electrical characteristics and reliability of the semiconductor device.

The first substrate 10 has a back electrode 17 on the second main surface 11b opposite to the first main surface 11a of the first Si substrate 11 provided with the trench portion 50 . In addition, the second substrate 20 has a back surface electrode 27 on the fourth main surface 21b opposite to the third main surface 21a on which the trench portion 60 of the second Si substrate 21 is provided.
Using the back electrode 17 and the back electrode 27, the semiconductor device 1 can be mounted on another substrate or the like.

Components of the first Si substrate, the second Si substrate, the back electrode, the first capacitor, the second capacitor, and the protective layer, which constitute the first substrate and the second substrate, will be described below.
The first Si substrate and the second Si substrate are made of a Si (silicon)-based material. For example, the first Si substrate and the second Si substrate are preferably made of conductive n-type Si or p-type Si. When the first Si substrate and the second Si substrate are conductive, the first Si substrate and the second Si substrate can also function as back electrodes. For example, the thickness of the first Si substrate and the second Si substrate is approximately 680 μm. The resistivity of the first Si substrate and the second Si substrate may be 0.001 Ωcm or more and 90 Ωcm or less.
Since the first Si substrate and the second Si substrate have the above properties, the back electrode is electrically connected to the first electrode layer through the conductive first Si substrate or the second Si substrate.

The back electrode is formed of metal materials such as Mo (molybdenum), Al (aluminum), Au (gold), W (tungsten), Pt (platinum), and Ti (titanium). The back electrode made of these metal materials is formed by a sputtering method, a vacuum deposition method, or the like. The material of the back electrode is not limited to a metal material as long as it is a conductive material, and may be a conductive resin or the like.

A first capacitive section composed of a first electrode layer, a first dielectric layer, and a second electrode layer is provided in the trench section of the first substrate.
As the first electrode layer, a method of using the conductive first Si substrate or the second Si substrate as it is may be used, or a metal film for an electrode provided on the first Si substrate or the second Si substrate may be used. Examples of materials for using a metal film as the first electrode layer include metals such as Cu, Ag, Au, Al, Ni, Cr, and Ti, and conductors containing these metals.
Also, the first electrode layer may have two or more conductor layers made of the above materials.

Although the thickness of the first electrode layer is not particularly limited, it is preferably 0.3 μm or more and 10 μm or less, more preferably 0.5 μm or more and 3 μm or less.

Materials constituting the dielectric layer include oxides such as SiO, Al ₂ O ₃ , HfO ₂ , Ta ₂ O ₅ and ZrO ₂ and nitrides such as Si ₃ N ₄ having dielectric or insulating properties. materials having

Although the thickness of the dielectric layer is not particularly limited, it is preferably 0.02 μm or more and 2 μm or less.

As the material forming the second electrode layer, the same material as the material forming the first electrode layer can be preferably used.
Although the thickness of the second electrode layer is not particularly limited, it is preferably 0.3 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 5 μm or less.

Although the trench portion of the second substrate is provided with the second capacitance portion composed of the third electrode layer, the second dielectric layer and the fourth electrode layer, the third electrode layer, the second dielectric layer and the fourth electrode layer are provided. The four electrode layers have configurations corresponding to the first electrode layer, the first dielectric layer, and the second electrode layer, respectively, which constitute the first capacitance section of the first substrate. A detailed description of is omitted.

The protective layer is a layer that covers the second electrode layer or the fourth electrode layer. The protective layer is preferably formed using, for example, polyimide, and preferably has a thickness of about 30 μm.

Next, the conductive pillar that electrically connects the first substrate and the second substrate will be described.
The conductive pillar is a columnar electrode formed outside the trench. The conductive pillar is preferably a metal material, preferably a metal such as Cu, Ag, Au, Al, Ni, Cr, Ti or a conductor containing these metals.

The shape of the conductive pillar is preferably cylindrical or prismatic.
The conductive pillar has a predetermined height.
The height of the conductive pillars is preferably 10 μm or more and 40 μm or less.
The height of the conductive pillars defined here is the total height of the conductive pillars that electrically connect the first substrate and the second substrate. When the conductive pillar 30 electrically connecting the first substrate 10 and the second substrate 20 is composed of a plurality of conductive pillars (conductive pillars 31a and 32a and conductive pillars 31b and 32b) as in the semiconductor device 1 shown in FIG. The height of conductive pillar 30 is the sum of the heights of conductive pillars 31a and 32a or conductive pillars 31b and 32b.
The height of the conductive pillars provided on the first substrate or the second substrate (the height of one conductive pillar) is preferably 5 μm or more and 20 μm or less.
Further, when the conductive pillars are cylindrical, the diameter is preferably 30 μm or more and 100 μm or less. Further, when the conductive pillar has a prism shape, the cross-sectional area is preferably 700 μm ² or more and 8000 μm ² or less.

Also, two conductive pillars are provided on each of the first substrate and the second substrate on the step surface shown in FIG. 1, but the number is not limited.
In addition, when the semiconductor device is viewed from above, the conductive pillars may be arranged side by side in the vertical direction and the horizontal direction so as to surround the trench portion.

In addition, apart from the conductive pillar for electrically connecting the first substrate and the second substrate, there is no physical connection between the first substrate and the second substrate without electrically connecting the first substrate and the second substrate. A separate pillar may be provided that connects only to the . As the number of pillars that physically connect the first substrate and the second substrate increases, the stability of bonding between the first substrate and the second substrate can be improved.

FIG. 1 shows a mode in which the conductive pillars 31a and 32a and the conductive pillars 31b and 32b are bonded with the conductive adhesive 35a and the conductive adhesive 35b, respectively.
As a method for joining the conductive pillars, in addition to joining using a conductive adhesive, methods such as joining using a brazing material and joining by thermocompression bonding of metals can be used.
When joining the conductive pillars by thermocompression bonding of metal, it is preferable to use thermocompression bonding of Cu/Ni/Au terminals.

In the semiconductor device of the present invention, the strength holding member is arranged in a space surrounded by at least two conductive pillars, the first substrate and the second substrate.
In the semiconductor device of the present invention, a strength retaining member is provided in the gap formed by bonding the first substrate and the second substrate, and the substrates are supported by the conductive pillars. By providing the strength retaining material, it is possible to prevent stress from concentrating on the conductive pillar, which is the connecting portion of the first substrate and the second substrate, and to avoid breakage of the conductive pillar caused by stress applied during mounting or use of the semiconductor device. can.

The linear thermal expansion coefficient of the strength retaining material is preferably 0.1% or more and 300% or less of the linear thermal expansion coefficient of Si. Further, the linear thermal expansion coefficient of the strength retaining material is more preferably 30% or more and 300% or less of the linear thermal expansion coefficient of Si.
By using a material whose linear thermal expansion coefficient is close to that of the first Si substrate and the second Si substrate as the strength retaining material, the thermal stress applied between the strength retaining material and the first Si substrate and the second Si substrate is minimized. , the occurrence of cracks in the semiconductor device can be prevented.

The strength retaining material is preferably made of a resin composition containing resin and SiO ₂ filler.
Epoxy resin or the like can be used as the resin. When the strength retaining material is a resin composition containing SiO ₂ filler, the linear thermal expansion coefficient of the resin composition is compared with the linear thermal expansion coefficient (3.9 ppm/° C.) of Si, which is the substrate on which the trench portion is formed. get closer.
Therefore, by disposing a strength retaining material made of a resin composition containing a resin and a SiO ₂ filler between the first substrate and the second substrate, the strength of the first Si substrate and the second Si substrate can be maintained when the semiconductor device is mounted or used. The difference in the linear thermal expansion coefficient of the material reduces the applied strain. In addition, the thermal stress applied to the conductive pillars can be minimized to prevent cracks from occurring in the semiconductor device.

Moreover, the resin composition constituting the strength retaining material may contain other fillers in addition to the SiO ₂ filler. Also, the resin composition may contain other fillers instead of the _SiO2 filler.
Other fillers that the resin composition may contain include Al ₂ O ₃ fillers, ZrO ₂ fillers, TiO ₂ fillers, and the like.

It is also preferable that the strength retaining material is made of metal. The metal is preferably Cu, Ag, an alloy containing them, or the like, and preferably has the same composition as the conductive pillar. If the composition is the same as that of the conductive pillars, the strength retaining member can be formed simultaneously with the conductive pillars.
By using a metal having a high thermal conductivity such as Cu, it is possible to reduce distortion due to a difference in coefficient of linear thermal expansion during mounting and use. In addition, if the same kind of metal as the conductive pillar is used, the linear thermal expansion coefficient of the conductive pillar and the strength retaining material will be uniform, so the thermal stress applied to the conductive pillar will be minimized and the occurrence of cracks in the semiconductor device will be prevented. be able to.
Further, when the strength retaining material is metal, the strength retaining material is preferably a dummy electrode that does not electrically act on the circuit of the semiconductor device.
When the strength holding member is made of metal, the strength holding member and two conductive pillars for electrically connecting the electrode forming the first capacitive section of the first substrate and the electrode forming the second capacitive section of the second substrate. contact with the semiconductor device affects the electrical characteristics of the semiconductor device. Therefore, it is necessary to insulate between the strength retaining member and the conductive pillar, so that the strength retaining member and the two conductive pillars should not come into contact with each other.

FIG. 2 is a cross-sectional view schematically showing an example of a semiconductor device having a strength retaining member made of metal.
The semiconductor device 2 shown in FIG. 2 has two strength holding members made of metal. One of the strength retaining members made of metal is a metal pillar 33a and a metal pillar 34a bonded with a conductive adhesive 36a, and the other is a metal pillar 33b and a metal pillar 34b bonded with a conductive adhesive 36b. It is glued.
The strength retaining material made of these metals is a dummy electrode that does not electrically act on the circuits of the first capacitor section 15 and the second capacitor section 16 of the semiconductor device 2. It is insulated from the capacitor section 16 .
Further, the strength retaining member made of metal is not in contact with each conductive pillar 30 .
By providing a gap between the metal strength retention member and each conductive pillar, or providing a protective layer between the metal strength retention member and each conductive pillar, the strength retention member made of metal and each conductive pillar are separated. It is preferable to avoid contact with the

FIG. 3 is a cross-sectional view of the semiconductor device shown in FIG. 2 taken along the line AA. It can also be said that FIG. 3 is a top view of the semiconductor device 2 in a cross section taken along line AA.
A region surrounded by a dotted line indicated by reference numeral 19 in FIG. 3 is a portion where the first capacitor portion 15 is not formed on the first main surface 11a of the first Si substrate. It shows that metal pillars 33a and 33b) are provided.
It also shows that the metal strength retaining members (metal pillars 33a and 33b) are not in contact with the conductive pillars 31a and 31b when viewed from the top of the semiconductor device.

It is also preferred that the strength retaining material includes a resin composition portion containing resin and SiO ₂ filler, and a metal portion.
By arranging the metal portion of the strength retaining member at a position close to the conductive pillar, the difference in linear thermal expansion coefficient between the conductive pillar and the strength retaining member can be reduced, and the thermal stress applied to the conductive pillar can be suppressed.
In addition, if the other portion is a resin composition portion containing a resin and SiO ₂ filler, the linear thermal expansion coefficient of this portion is the linear thermal expansion coefficient of Si, which is the substrate on which the trench portion is formed (3.9 ppm / ° C. ) is relatively close. Therefore, the strain applied due to the difference in the linear thermal expansion coefficient between the first Si substrate and the second Si substrate and the strength holding member during mounting or use of the semiconductor device is reduced.
As a result of these actions, it is possible to minimize the thermal stress applied to the conductive pillars and prevent cracks from occurring in the semiconductor device.
In this case as well, it is necessary to insulate the strength retaining member and the conductive pillar, so that the metal portion of the strength retaining member and the conductive pillar do not come into contact with each other.

Also, the strength retaining material may be a conductive resin, but in this case as well, it is necessary to insulate the strength retaining material and the conductive pillars, so that the strength retaining material and the conductive pillars are prevented from coming into contact with each other.

The strength retaining material is preferably a poly-Si film.
The poly-Si film is preferably a film formed by CVD.
When the strength retaining material is a poly-Si film, the linear thermal expansion coefficient of the strength retaining material is close to the linear thermal expansion coefficient of Si, which is the substrate in which the trench portion is formed.
Therefore, the strain applied due to the difference in the linear thermal expansion coefficient between the first Si substrate and the second Si substrate and the strength holding member during mounting or use of the semiconductor device is reduced. In addition, the thermal stress applied to the conductive pillars can be minimized to prevent cracks from occurring in the semiconductor device.
If the strength retainer is a poly-Si film, the physical bonding of the first substrate and the second substrate may be made by at least two conductive pillars.

[Semiconductor Device of Second Embodiment]
The semiconductor device of the present invention may be stacked such that the directions of the trench portions are the same.
FIG. 4 is a cross-sectional view schematically showing an example of the semiconductor device according to the second embodiment of the invention.
A semiconductor device 3 shown in FIG. 4 includes a structure in which a first substrate 10 and a second substrate 20 are stacked.
In the semiconductor device 3, the first substrate 10 and the second substrate 20 are stacked so that the first main surface 11a of the first Si substrate 11 and the fourth main surface 21b of the second Si substrate 21 are opposed to each other, so that the trench portion 50 is formed between the first substrate 10 and the second substrate 20. and the trench portions 60 are stacked in the same direction.
Since the configurations of the first substrate 10 and the second substrate 20 can be the same as those of the first substrate 10 and the second substrate 20 shown in FIG. 1, detailed description thereof will be omitted.

A conductive pillar 31a and a conductive pillar 31b are provided on the upper surface of the first substrate 10 . The conductive pillars 31 a and 31 b are connected to the back electrode 27 of the second substrate 20 .
The conductive pillars 31a and 31b and the back surface electrode 27 of the second substrate 20 are joined by metal thermocompression bonding.
A strength holding member 40 is arranged in a space surrounded by the conductive pillar 31a, the conductive pillar 31b, the first substrate 10 (protective layer 16 of the first substrate 10), and the second substrate 20 (back electrode 27 of the second substrate). there is

Also in the semiconductor device of the second embodiment, a strength holding material is provided in the gap formed by bonding the first substrate and the second substrate, and the substrates are supported by the conductive pillars. By providing the strength retaining material, it is possible to prevent stress from concentrating on the conductive pillar, which is the connecting portion of the first substrate and the second substrate, and to avoid breakage of the conductive pillar caused by stress applied during mounting or use of the semiconductor device. can.

[Semiconductor Device of Third Embodiment]
In the semiconductor device of the present invention, the first substrate may be a substrate having trench portions on its upper and lower surfaces. A lower second substrate may be provided facing the trench portion. In this case, three substrates, ie, the lower second substrate, the first substrate, and the upper second substrate are laminated.
The lower second substrate and the first substrate are electrically connected by at least two conductive pillars, and a strength holding member is arranged in a space surrounded by the at least two conductive pillars, the lower second substrate and the first substrate. It is
The first substrate and the upper second substrate are also electrically connected by at least two conductive pillars, and the strength holding member is arranged in a space surrounded by the at least two conductive pillars, the first substrate and the upper second substrate. there is

FIG. 5 is a cross-sectional view schematically showing an example of the semiconductor device according to the third embodiment of the invention.
The semiconductor device 4 shown in FIG. 5 includes a structure in which a lower second substrate 120b, a first substrate 110, and an upper second substrate 120a are laminated.

The lower second substrate 120b and the first substrate 110 are electrically connected by at least two conductive pillars 30 having a predetermined height (conductive pillars 31a and 32a and conductive pillars 31b and 32b). .
A strength holding member 40b is arranged in a space surrounded by at least two conductive pillars 30, the first substrate 110 and the lower second substrate 120b.

The first substrate 110 and the upper second substrate 120a are electrically connected by at least two conductive pillars 30 (conductive pillar 31a and conductive pillar 32a and conductive pillar 31b and conductive pillar 32b) having a predetermined height. .
A strength holding member 40a is arranged in a space surrounded by at least two conductive pillars 30, the first substrate 110 and the upper second substrate 120a.

The first substrate 110 includes a first Si substrate 11 having a first main surface 11a and a second main surface 11b facing the first main surface 11a. Each has a trench portion 50 on the main surface 11b.
The trench portions 50 formed on the first main surface 11a and the second main surface 11b of the first Si substrate 11 are provided with the first capacitor portions 15, respectively. A back electrode is not provided on the first Si substrate 11 .
The structures of the first electrode layer 12, the dielectric layer 13, and the second electrode layer 14 that constitute the first capacitor section 15 on the first substrate 110 can be the same as those of the first substrate 10 shown in FIG.
The configuration of the upper second substrate 120a and the lower second substrate 120b can be the same as the configuration of the second substrate 20 shown in FIG.
The upper second substrate 120a and the lower second substrate 120b each include a second Si substrate 21 having a third principal surface 21a and a fourth principal surface 21b facing the third principal surface 21a. A plurality of trench portions 60 are provided on the third main surface 21a.
A second capacitance section 25 is provided in each trench section 60 formed on the third main surface 21a of the second Si substrate 21 constituting the second upper substrate 120a and the second lower substrate 120b.
Therefore, detailed descriptions of the first substrate 110, the upper second substrate 120a, and the lower second substrate 120b are omitted.

In the semiconductor device of the third embodiment as well, the gap formed by laminating the lower second substrate and the first substrate and the gap formed by laminating the first substrate and the upper second substrate each have strength. A retainer is provided to support the substrates against each other by the conductive pillars. By providing the strength retaining material, it is possible to prevent stress from concentrating on the conductive pillar, which is a connection portion between the substrates, and to avoid breakage of the conductive pillar caused by stress applied during mounting or use of the semiconductor device.

[Semiconductor Device of Fourth Embodiment]
In the semiconductor device of the present invention, the coordinates of the center point of the bottom of the trench of the first substrate and the coordinates of the center of the bottom of the trench of the second substrate do not overlap each other when viewed in the thickness direction of the substrate. may be in the form .
6 and 7 are cross-sectional views schematically showing an example of the semiconductor device according to the fourth embodiment of the present invention.
In the semiconductor device 5 shown in FIG. 6 and the semiconductor device 6 shown in FIG. 7, when viewed in the thickness direction of the substrate, the coordinates of the center point of the bottom of the trench portion 50 of the first substrate 10 and the coordinates of the trench of the second substrate 20 are The center point coordinates of the bottoms of the parts 60 do not overlap.
Whether or not the coordinates of the center points overlap when viewed in the thickness direction of the substrate is determined by the overlap of the positions where the center points of the respective trench portions are pulled out to the uppermost surface of the semiconductor substrate along the thickness direction of the semiconductor substrate.
6 and 7, the center point _C50a of the bottom of the trench portion 50 is pulled out to the uppermost surface of the semiconductor substrate 4 or 5 along the thickness direction of the semiconductor substrate 4 or 5 (line indicated by symbol _C50 ). The point is indicated by center point coordinates C _50b . Also, the center point coordinates of a point drawn from the center point C _60a of the bottom of the trench portion 60 to the uppermost surface of the semiconductor substrate 4 or 5 along the thickness direction of the semiconductor substrate 4 or 5 (the line indicated by symbol C ₆₀ ) are Denoted by C _60b .
When the center point coordinates C _50b and the center point coordinates C _60b drawn to the uppermost surface of the semiconductor substrate do not overlap, the center point coordinates of the bottom of the trench portion of the first substrate and the center of the bottom of the trench portion of the second substrate. It is determined that the point coordinates do not overlap.
In FIGS. 6 and 7, a line C ₅₀ indicates a line extending from the center point C _50a of the bottom of the trench portion 50 of the first substrate 10 to the uppermost surface along the thickness direction of the semiconductor substrate 4 or 5. A line C ₆₀ indicates a line extending the center point C _{60 a} of the bottom of the trench portion 60 of the second substrate 20 to the uppermost surface along the thickness direction of the semiconductor substrate 4 or 5 .

In the semiconductor device 5 shown in FIG. 6, the first substrate 10 and the second substrate 20 are laminated such that the directions of the trench portions 50 and 60 face each other.
That is, in the semiconductor device 1 shown in FIG. 1, the semiconductor device 5 shown in FIG. 20 is modified so that the coordinates of the central point of the trench portion 60 do not overlap.

On the other hand, in the semiconductor device 6 shown in FIG. 7, the first substrate 10 and the second substrate 20 are laminated so that the trench portions 50 and 60 are oriented in the same direction.
That is, in the semiconductor device 3 shown in FIG. 4, the semiconductor device 6 shown in FIG. 20 is modified so that the coordinates of the central point of the trench portion 60 do not overlap.

A trench portion formed in a semiconductor device tends to bend when heat is applied, and stress tends to concentrate on the trench portion. When viewed in the thickness direction of the substrate, if the coordinates of the center points of the bottoms of the trenches of the first substrate and the second substrate are overlapped, the portion where the stress concentrates is the thickness of the semiconductor substrate of the first substrate and the second substrate. Since they overlap when viewed in the lateral direction, it easily leads to brittle fracture of the semiconductor device.
As in the semiconductor device of the fourth embodiment, when viewed in the thickness direction of the substrate, the coordinates of the central point of the bottom of the trench of the first substrate and the coordinates of the central point of the bottom of the trench of the second substrate overlap. Otherwise, the stress concentration location in the first substrate and the stress concentration location in the second substrate are not aligned, so that the stress is dispersed in the semiconductor device as a whole, resulting in brittle fracture of the semiconductor device. become difficult.

[Method for manufacturing a semiconductor device]
An example of the method for manufacturing the semiconductor device of the present invention will be described below.
First, a first substrate is produced.
A Si substrate serving as a first Si substrate is prepared, a trench portion is formed on the Si substrate by photolithography and dry etching, and a first electrode layer, a first dielectric layer, and a second electrode layer are formed in the trench portion. A first volume is provided. A back surface electrode is provided on the surface opposite to the surface on which the trench portion is provided.
At least two conductive pillars are provided on the surface of the second electrode layer, and a protective layer is provided by coating or the like. Furthermore, the surfaces of the conductive pillars are exposed from the protective layer by a process such as polishing the surface of the protective layer.

Furthermore, a resin composition layer serving as a strength retaining material is provided on the protective layer. The resin composition layer preferably contains a strength retaining resin and SiO ₂ filler.
After providing the resin composition layer, it is preferable that the top surface of the conductive pillar is flush with the surface of the resin composition layer, or the top surface of the conductive pillar is slightly exposed from the surface of the resin composition layer.
Thus, the first substrate can be produced.
A second substrate is produced by the same procedure.

FIG. 8 is a process diagram schematically showing how the first substrate and the second substrate are laminated and bonded together so that the directions of the trench portions face each other.
The first substrate 10 and the second substrate 20 shown in FIG. 8 have a resin composition layer 140 on their outermost surfaces, and the first substrate 10 and the second substrate 20 are arranged so that the resin composition layers 140 face each other. overlap.
When the first substrate 10 and the second substrate 20 are superimposed and thermally compressed by applying heat and pressure from above and below, the resin composition layer 140 of the first substrate 10 and the resin composition layer 140 of the second substrate 20 are integrated to form a second substrate. A strength holding member 40 is formed between the first substrate 10 and the second substrate 20 .

A conductive adhesive 135 is applied to the upper surfaces of the conductive pillars 31a and 31b of the first substrate 10, and the conductive adhesive 135 is also applied to the upper surfaces of the conductive pillars 32a and 32b of the second substrate 20. Keep
Then, when the first substrate 10 and the second substrate 20 are superimposed and thermally compressed by applying heat and pressure from above and below, the conductive pillars 31a and 32a and between the conductive pillars 31b and 32b become conductive. They are joined with a conductive adhesive 35a and a conductive adhesive 35b.

By the above procedure, the first substrate and the second substrate are electrically connected by at least two conductive pillars, and the strength holding member is arranged in the space surrounded by the at least two conductive pillars, the first substrate, and the second substrate. , the semiconductor device of the first embodiment of the present invention can be obtained.

FIG. 9 is a process diagram schematically showing how the first substrate and the second substrate are stacked and bonded together so that the directions of the trench portions are the same.
The first substrate 10 shown in FIG. 9 has a resin composition layer 140 on its outermost surface.
The first substrate 10 and the second substrate 20 are stacked so that the resin composition layer 140 of the first substrate 10 and the back electrode 27 of the second substrate 20 face each other.
When the first substrate 10 and the second substrate 20 are superimposed and thermally compressed by applying heat and pressure from above and below, the resin composition layer 140 of the first substrate 10 is adhered to the back electrode 27 of the second substrate 20, thereby A strength retaining member 40 is formed between the substrate 10 and the second substrate 20 .

The upper surfaces of the conductive pillars 31a and 31b of the first substrate 10 are formed as metal terminals (for example, Cu/Ni/Au terminals) that can be thermocompression bonded.
Then, when the first substrate 10 and the second substrate 20 are superimposed and thermally compressed by applying heat and pressure from above and below, the conductive pillars 31a and 31b are joined to the back electrode 27 of the second substrate 20 by thermal compression.

By the above procedure, the first substrate and the second substrate are electrically connected by at least two conductive pillars, and the strength holding member is arranged in the space surrounded by the at least two conductive pillars, the first substrate, and the second substrate. , the semiconductor device of the second embodiment of the present invention can be obtained.

Regarding the bonding method between the conductive pillars of the first substrate and the conductive pillars of the second substrate, a method using a conductive adhesive was described in FIG. 8, and a method using metal thermocompression bonding was described in FIG. A brazing material may be applied to the tip of each member, and the joining may be performed using the brazing material. Moreover, you may join by another joining method.

1, 2, 3, 4, 5, 6 semiconductor device 10, 110 first substrate 11 first Si substrate 11a first main surface 11b second main surface 12 first electrode layer 13 first dielectric layer 14 second electrode layer 15 First capacitive sections 16, 26 Protective layers 17, 27 Rear electrode 19 Region 20 where the first capacitive section is not formed on the first main surface of the first Si substrate 20 Second substrate 21 Second Si substrate 21a Third main surface 21b 4 main surface 22 third electrode layer 23 second dielectric layer 24 fourth electrode layer 25 second capacitor section 30, 31a, 31b, 32a, 32b conductive pillars 33a, 33b, 34a, 34b metal pillars 35a, 35b, 36a, 36b, 135 conductive adhesives 40, 40a, 40b strength retaining members 50, 60 trench portion 120a second upper substrate 120b second lower substrate 140 resin composition layer

Claims (9)

a first substrate provided with a first capacitor portion including a first electrode layer, a first dielectric layer, and a second electrode layer provided in a trench portion formed on a first Si substrate;
and a second substrate provided with a second capacitor portion composed of a third electrode layer, a second dielectric layer, and a fourth electrode layer provided in a trench portion formed on a second Si substrate. a device,
The electrode forming the first capacitor section of the first substrate and the electrode forming the second capacitor section of the second substrate are electrically connected by at least two conductive pillars having a predetermined height, and A semiconductor device, comprising: a strength holding member disposed in a space surrounded by at least two conductive pillars, the first substrate, and the second substrate. 2. The semiconductor device according to claim 1, wherein the linear thermal expansion coefficient of said strength retaining material is 0.1% or more and 300% or less of the linear thermal expansion coefficient of Si. 3. The semiconductor device according to claim 1, wherein said strength retaining material comprises a resin composition containing resin and _SiO2 filler. 3. The semiconductor device according to claim 1, wherein said strength retaining member is made of metal, and said strength retaining member and said two conductive pillars are not in contact with each other. 3. The semiconductor device according to claim 1, wherein said strength retaining material comprises a resin composition portion containing resin and _SiO2 filler, and a metal portion. 3. The semiconductor device according to claim 1, wherein said strength retaining material is a poly-Si film. 7. The center point coordinates of the bottom portion of the trench portion of the first substrate and the center point coordinates of the bottom portion of the trench portion of the second substrate do not overlap each other when viewed in the thickness direction of the substrate. 1. The semiconductor device according to claim 1. 8. The semiconductor device according to claim 1, wherein said first substrate and said second substrate are laminated so that said trench portions face each other. 8. The semiconductor device according to claim 1, wherein said first substrate and said second substrate are laminated so that said trench portions are oriented in the same direction.

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