JP7167086B2 - circuit, chip, imaging device, imaging system, moving body - Google Patents

Description

The present invention relates to circuits, chips, imaging devices, imaging systems, and moving objects.

Japanese Unexamined Patent Application Publication No. 2002-100001 describes an imaging apparatus in which AD converters for AD-converting signals from photoelectric converters are arranged over a plurality of rows and columns.

In the imaging device described in Patent Document 1, one column of AD converters is connected to one vertical bus. This vertical bus is connected to a signal holding section provided corresponding to each column. A digital signal is sequentially transmitted from the signal holding unit of each column to the output unit.

JP 2014-165733 A

In the imaging apparatus of Patent Document 1, no consideration is given to a connection form between bit memories each holding different bits among a plurality of bit digital signals and transmission lines for transmitting digital signals.

This embodiment provides a technique for speeding up the transmission of digital signals of a plurality of bits while suppressing an increase in the number of transmission lines.

The present invention has been made in view of the above problems. One aspect of the present invention is to provide a plurality of arrays each having a plurality of AD converters for converting analog signals into digital signals; a counter for outputting a count signal to the plurality of AD converters arranged in each of the arrays; and a ramp signal generator for generating a ramp signal to be supplied to the plurality of AD converters arranged in each of the plurality of arrays. a circuit , wherein the counter is arranged in a region between a first array and a second array among the plurality of arrays in plan view, and the ramp signal generation circuit is separate from the region and is arranged in a region between one array of the plurality of arrays and another array .

According to the present invention, it is possible to provide a technique for speeding up the transmission of digital signals of a plurality of bits while suppressing an increase in the number of transmission lines.

Schematic diagram of configuration of imaging device and cross-sectional view Diagram showing pixel configuration A diagram showing the configuration of the second chip A diagram showing the configuration of a part of the second chip, and a diagram showing the configuration of the AD converter. A diagram showing the configuration of the first memory and the buffer memory. Diagram showing configuration of buffer memory A diagram showing the operation of the imaging device A diagram showing the configuration of the first memory and the buffer memory. Schematic diagram of the configuration of the imaging device A diagram showing the configuration of the second chip and a diagram showing the configuration of the AD conversion unit A diagram showing the configuration of an imaging device Overall view of imaging system General view of moving body Diagram showing the signal processing flow of the imaging system

Each embodiment will be described below with reference to the drawings.

(Example 1)
FIG. 1(a) is a diagram showing a first chip 1 and a second chip 5 included in the imaging device of this embodiment. Photoelectric conversion units 13 are arranged over a plurality of rows and a plurality of columns in the first chip 1 . In the second chip 5, an AD converter (hereinafter referred to as ADC) 21 is arranged over multiple rows and multiple columns. The ADC 21 AD-converts a signal based on the signal generated by the photoelectric conversion unit 13 into a digital signal of a plurality of bits. Although only the photoelectric conversion unit 13 and the ADC 21 are illustrated here, a control line for controlling the photoelectric conversion unit 13 and a signal line for transmitting a signal based on the charge accumulated by the photoelectric conversion unit 13 are provided as appropriate. 1 chip 1 and second chip 5 are arranged. Driving circuits such as a vertical scanning circuit and a timing generator are arranged in the first chip 1 or the second chip 5 as appropriate.

FIG. 1B is a cross-sectional view of the first chip 1 and the second chip 5. FIG. The first chip 1 and the second chip 5 are connected via the bonding surface 2 . At this bonding surface 2, the uppermost wiring and insulating layer of the first chip 1 and the uppermost wiring and insulating layer of the second chip 5 are connected. Cu is typically used as the wiring. Al can also be used as another example. The uppermost wiring of each of the first chip 1 and the second chip 5 is connected through the connecting portion 3 .

FIG. 2 is an equivalent circuit diagram of the pixel 11 of this embodiment. The pixel 11 has a photodiode as the photoelectric conversion unit 13 . The photodiode 13 of the pixel 11 receives light that has passed through one microlens (not shown) and a color filter.

The photodiode 13 is connected to a floating diffusion section (hereinafter referred to as FD section) 605 via a transfer transistor 603 . Also, the gate of the transfer transistor 603 is connected to a vertical scanning circuit (not shown) through a control line 650 . Control line 650 transmits signal Tx.

The FD section 605 is connected to gates of the reset transistor 606 and the amplification transistor 607 .

A power supply voltage Vdd is supplied to the reset transistor 606 and the amplification transistor 607 . A gate of the reset transistor 606 is connected to a vertical scanning circuit (not shown) via a control line 660 . Control line 660 carries signal Rx.

The amplification transistor 607 is connected to the selection transistor 608 . A gate of the selection transistor 608 is connected to a vertical scanning circuit (not shown) via a control line 665 . Control line 665 carries signal PSELx.

The select transistor 608 is connected to the signal line 201 .

FIG. 3 is a block diagram showing the configuration of the second chip 5 of the imaging device of this embodiment.

The second chip 5 has a plurality of AD conversion areas (denoted as ADC Array in the drawing) 22 in which ADCs 21 are arranged over a plurality of rows and a plurality of columns. That is, the AD conversion area 22 is also arranged over multiple rows and multiple columns. A buffer memory (denoted as buffer memory in the figure) 25 is provided corresponding to each AD conversion area 22 . The ADC 21 in the AD conversion area 22 and the buffer memory 25 are connected by a transmission line (not shown in FIG. 3).

The second chip 5 also has a vertical scanning circuit (denoted as VSCAN in the drawing) 24 that sequentially scans the pixels 11 arranged on the first chip 1 row by row.

The second chip 5 has a digital signal processing circuit (denoted as DFE in the drawing, hereinafter referred to as DFE) 28 . The DFE 28 performs various processing (noise subtraction processing, various corrections such as gain correction, offset correction, etc.) on the digital signal output from the buffer memory 25 . The second chip 5 has two DFEs 28 . One DFE 28 processes digital signals output from a plurality of buffer memories 25 .

The ADC 21 of this embodiment performs ramp signal comparison type AD conversion that compares a ramp signal with a signal based on a signal generated by a photoelectric conversion unit. The second chip 5 has a ramp signal generator 35 (denoted as Ramp Gen. in the drawing) that generates this ramp signal.

The second chip 5 includes a timing generator (denoted as TG in the drawing, hereinafter referred to as TG) 30 that generates various control signals, and a counter that generates a Gray code count signal used in ramp signal comparison type AD conversion. (denoted as Counter in the figure) 31.

The second chip 5 has a data interface section (denoted as data I/F in the figure, hereinafter referred to as an IF section) 35 that outputs the signal processed by the DFE 28 to the outside of the imaging device.

FIG. 4A is a block diagram showing the details of the configuration related to one AD conversion area 22 and one buffer memory 25. FIG.

The AD conversion area 22 has m rows and n columns of ADCs 21 as ADCs 21 of multiple rows and multiple columns.

The AD conversion area 22 has a plurality of transmission lines 43 extending from the AD conversion area 22 to a buffer memory 25 provided outside the AD conversion area 22 . One transmission line 43 is connected to the ADCs 21 arranged in one column and multiple rows. That is, the plurality of transmission lines 43 are arranged in the AD conversion area 22 so that each of the plurality of transmission lines 43 is connected to the ADCs 21 arranged in one column and multiple rows.

The second chip 5 also has an ADC scanning circuit (denoted as ADC SCAN in the drawing) 41 that scans the ADCs 21 arranged in multiple rows and multiple columns row by row. As will be described later, the ADC 21 has a memory that holds a digital signal obtained by AD-converting a signal corresponding to the signal from the photoelectric conversion unit 13 . This memory is connected to the transmission line 43 . Then, the ADC scanning circuit 41 selects each memory of the ADC 21 row by row. A digital signal held in the memory is output to the transmission line 43 from the memory selected by the ADC scanning circuit 41 .

The signal output to the transmission line 43 is transmitted to the buffer memory 25 via the transmission line 43 . The buffer memory 25, which will be described later, has memories (hereafter referred to as bit memories) that hold respective bit signals (hereafter referred to as bit signals) of a plurality of bit digital signals arranged over a plurality of rows and a plurality of columns. It is The second chip 5 includes a memory vertical scanning circuit (denoted as MEM VSCAN in the drawing) 45 for vertically scanning the buffer memory 25 and a memory horizontal scanning circuit (denoted as MEM HSCAN in the drawing) 48 for horizontally scanning the buffer memory 25. and

A bit signal is transmitted from the bit memory selected by the memory vertical scanning circuit 45 and the memory horizontal scanning circuit 48 to the DFE 28 via the transmission line 49 .

FIG. 4(b) is a block diagram showing the configuration of the ADC 21. As shown in FIG. The ADC 21 is connected to the signal line 201 shown in FIG. 2 via the connecting portion 3 connecting the second chip 5 and the first chip 1 shown in FIG. 1(b). The current source 50 is provided in the second chip 5 and supplies a current to the signal line 201 shown in FIG. 2 via the connection portion 3 shown in FIG. 1(b). As a result, the amplification transistor 607 of the pixel 11 performs source follower operation. In other words, current source 50 and amplifying transistor 607 form a source follower circuit.

ADC 21 has comparator 51 and first memory 55 . A ramp signal VRMP is output to the comparator 51 from the ramp signal generator 35 shown in FIG. The comparator 51 outputs to the first memory 55 a comparison result signal indicating the result of comparing the ramp signal VRMP and the signal of the pixel 11 output from the signal line 201 . A count signal Count is output to the first memory 55 from the counter 31 shown in FIG. The count signal Count is a signal obtained by counting the clock signal with Gray code. The first memory 55 holds the current count signal Count based on the timing at which the signal level of the comparison result signal changes. Each bit signal of the count signal Cout held by each of the bit memories 550a to 550d is each bit signal of a digital signal corresponding to the signal based on the signal generated by the photoelectric conversion section 13. FIG.

In this embodiment, the first memory 55 is included in the ADC 21 . Therefore, the memory area having the first memories 55 arranged over multiple rows and multiple columns is the AD conversion area 22 in this embodiment.

A scanning signal is output to the first memory 55 from the ADC scanning circuit 41 shown in FIG. The first memory 55 to which the active level scanning signal is input outputs the held digital signal to the transmission line 43 .

FIG. 5 is a block diagram showing the configuration of ADC 21 and buffer memory 25 shown in FIG. Here, one ADC 21 among the ADCs 21 arranged in multiple rows and multiple columns will be described. The other ADC 21 also has the same configuration as the ADC 21 described below.

The first memory 55 has first bit memories 550a-d. Each of the first bit memories 550a to 550d is a memory that holds a signal of each bit of the count signal Count. A comparison result signal from the comparator 51 is output to the first bit memories 55a to 55d.

Further, scanning signals S1 to S4 are input from the ADC scanning circuit 41 to the first bit memories 550a to 550d. The ADC scanning circuit 41 is a first scanning circuit that scans the plurality of first bit memories 550a to 550d in a first direction (row advancing direction). One transmission line 43 is connected to the first bit memories 550a to 550d. That is, the transmission line 43 is a first transmission line to which a plurality of first bit memories are connected. The ADC scanning circuit 41 sequentially sets the scanning signals S1 to S4 to an active level. As a result, bit signals are sequentially output to the transmission line 43 from the first bit memory 550a. That is, the transmission line 43 serially transmits each bit signal of the digital signal output by one AD converter 21 .

After that, the ADC scanning circuit 41 brings the scanning signals S5 to S8 to the active level in order. As a result, each bit signal of the digital signals of the AD converters 21 in multiple rows is serially transferred to one transmission line 43 .

The buffer memory 25 has a bit memory section 250 in which second bit memories are arranged in an array. The buffer memory 25 also has a first selection circuit 60 and a second selection circuit 65 . A control signal SEL1 is input to the first selection circuit 60 from the TG 30 shown in FIG. Also, the control signal SEL2 is input to the second selection circuit 65 from the TG 30 shown in FIG.

The bit memory unit 250 has a plurality of columns of second bit memories for one column of ADC 21 . A certain column of second bit memories among the plurality of columns of second bit memories can be said to be one memory group. Also, the second bit memory in another column can be said to be another memory group. That is, it can be said that the bit memory 250 has a plurality of memory groups for one column of ADCs 21 . When the signal SEL1 is at the active level, the first selection circuit 60 transmits each bit signal transmitted from the transmission line 43 to one column of the second bit memories provided in a plurality of columns. The first selection circuit 60 transmits each bit signal transmitted from the transmission line 43 to the other column of the second bit memories provided in a plurality of columns when the signal SEL1 is at the non-active level.

The memory vertical scanning circuit 45 outputs a scanning signal Sxy (x is a value of 1 to 8, y is a value of 1 to 2) to the corresponding second bit memory. The memory vertical scanning circuit 45 is a second scanning circuit that scans the plurality of second bit memories 250a to 250h in the first direction (row advancing direction).

The buffer memory 25 has a transmission line group 520 . Although the details of the transmission line group 520 will be described later, it includes a plurality of transmission lines.

The bit signal output from the first selection circuit 60 is held in the second bit memory to which the active level scanning signal Sxy is input.

When the signal SEL2 output from the TG 30 is at the active level, the second selection circuit 65 connects the transmission line group 520 through which bit signals are transmitted from one column of the second bit memory to the switch SW2. On the other hand, when the signal SEL2 is at the non-active level, the transmission line group 520 through which bit signals are transmitted from the other column of the second bit memory is connected to the switch SW2.

The memory horizontal scanning circuit 48 outputs a scanning signal Hw (w is a number from 1 to n) to the corresponding switch SWw (w is a number from 1 to n). The memory horizontal scanning circuit 48 sets the scanning signal Hw to the active level in order from the scanning signal H1. As a result, bit signals are output to the transmission line group 49 in order from the switch SW1. Memory horizontal scanning circuit 48 is a third scanning circuit that scans each of the plurality of sets of second and third transmission lines.

FIG. 6 is a diagram showing details of the buffer memory 25 shown in FIG. Transmission line group 520 comprises transmission lines 520a-h. The bit memory unit 250 also includes second bit memories 250a to 250h. The second bit memory 250a is connected to the transmission line 520a. Similarly, each of the second bit memories 250b-h is connected to a corresponding transmission line 520z (where z is any of b-h) among the transmission lines 520b-h. For example, transmission line 520a is a second transmission line to which second bit memory 250a, which is a portion of the plurality of second bit memories 250a-h, is connected. Also, the transmission line 520b is a third transmission line to which the second bit memory 250b, which is another part of the plurality of second bit memories 250a to 250h, is connected.

The second selection circuit 65 has selection circuits 65a-h arranged corresponding to the transmission lines 520a-h, respectively. Transmission line group 49 includes transmission lines 490a-h. Each of the selection circuits 65a-h is connected to a corresponding one of the transmission lines 490a-h via a corresponding switch SW. The transmission line 490a is a fourth transmission line selectively connected to the second transmission line of one memory group of the plurality of memory groups and the second transmission line of the other memory group of the plurality of memory groups. . Further, the transmission line 490b is a fifth transmission line to which the third transmission line of one memory group of the plurality of memory groups and the third transmission line of the other memory group of the plurality of memory groups are selectively connected. be.

FIG. 7 is a timing chart showing the operation of the imaging device of this embodiment.

The signals shown in FIG. 7 correspond to the signals referenced in FIGS. VLINE shown in FIG. 7 is the potential of the signal line 201 .

During the period P1, the vertical scanning circuit 24 sets the signal RX to be output to the pixel row from which the signal is to be output to the active level. This activates the reset transistor 606 and resets the potential of the FD section 605 . A signal (noise signal) corresponding to the potential of the FD unit 605 whose reset has been released is output from the amplification transistor 607 to the signal line 201 via the selection transistor 608 .

In the period P2, the ramp signal generator 35 starts monotonically changing the potential of the ramp signal VRMP. Monotonic change here means that the direction of potential change is maintained in the same direction from the start to the end of the change. Even when the potential change rate per unit time of the ramp signal changes from the start to the end of the change, this is within the range of monotonic change of the potential.

In the period P2, each of the first bit memories 550a to 550d of the first memory 55 holds the count signal Count when the signal level of the comparison result signal changes. This count signal Count is a digital signal based on a noise signal. This is denoted as N data.

In the period P4, the signal SEL1 output from the TG 30 to the first selection circuit 60 is set to the active level. As a result, the bit signals output from the first bit memories 550a to 550d are transferred to the transmission lines connected to the first selection circuit 60 and the second bit memories 250a to 250h in one column of the second bit memory section 250. output to

During the period P4, the ADC scanning circuit 41 sequentially sets the scanning signals S1 to S8 to the active level. In accordance with this, the memory vertical scanning circuit 45 sequentially sets the scanning signals S11, S21, S31, S41, S51, S61, S71, and S81 to the active level.

For example, when scanning signal S1 is at active level, scanning signal S11 is at active level. As a result, the bit signal output from the first bit memory 550a is held in the second bit memory 250a in one column of the second bit memory unit 250. FIG. Similarly, the N data bit signals held by the first memory 55 of one ADC 21 are held in the second bit memories 250a to 250d. Then, the N data bit signals held by the first memory 55 of the ADC 21 in another row in the same column are held in the second bit memories 250e to 250h.

In addition, the vertical scanning circuit 24 sets the signal Tx to the active level during the period P3, which is a period included in part of the period P4. Thereby, the charges generated by the photoelectric conversion unit 13 are transferred to the FD unit 605 . As a result, the FD portion 605 has a potential corresponding to the charge generated by the photoelectric conversion portion 13 . Therefore, a signal (optical signal) corresponding to the potential of the FD unit 605 corresponding to the charge generated by the photoelectric conversion unit 13 is output from the amplification transistor 607 to the signal line 201 via the selection transistor 608 .

As described above, the period P3 is a period included in part of the period P4. That is, the operation of transmitting bit signals from the first bit memories 550a to 550d to the second bit memories 250a to 250h and the operation of transferring charges from the photoelectric conversion unit 13 to the FD unit 605 are performed in parallel.

In the period P5, the ramp signal generator 35 starts monotonically changing the potential of the ramp signal VRMP.

In the period P5, each of the first bit memories 550a to 550d of the first memory 55 holds the count signal Count when the signal level of the comparison result signal changes. This count signal Count is a digital signal based on an optical signal. This is denoted as S data.

Also, in the period P5, the memory horizontal scanning circuit 48 sequentially sets the scanning signal Hw (w is 1 to n) to the active level. As a result, the N data held by the second bit memories 250a to 250h in one column of the second bit memory section 250 are output to the transmission line group 49. FIG.

In the period P7, the signal SEL2 output from the TG 30 to the first selection circuit 60 is set to the active level. As a result, the bit signals output from the first bit memories 550a to 550d are transferred to the transmission lines connected to the first selection circuit 60 and the second bit memories 250a to 250h in the other column of the second bit memory section 250. output to

During the period P7, the ADC scanning circuit 41 sequentially sets the scanning signals S1 to S8 to the active level. In accordance with this, the memory vertical scanning circuit 45 sequentially sets the scanning signals S12, S22, S32, S42, S52, S62, S72, and S82 to the active level.

For example, when scanning signal S1 is at active level, scanning signal S12 is at active level. As a result, the bit signal output from the first bit memory 550a is held in the second bit memory 250a in the other column of the second bit memory section 250. FIG. Similarly, the S data bit signals held by the first memory 55 of one ADC 21 are held in the second bit memories 250a to 250d. Then, the bit signals of the S data held by the first memory 55 of the ADC 21 in another row in the same column are held in the second bit memories 250e to 250h.

In addition, during period P6, which is a period included in part of this period P7, the vertical scanning circuit 24 sets the signal Rx to be supplied to the next pixel row to the active level. As a result, the reset transistor 606 in the next row becomes active, and the potential of the FD section 605 is reset. A noise signal is output to the signal line 201 from the pixels 11 in the next row.

During periods P8 and P9, the memory horizontal scanning circuit 48 sequentially sets the scanning signal Hw (w is 1 to n) to the active level. As a result, the S data held by the second bit memories 250a to 250h in the other column of the second bit memory unit 250 are output to the transmission line group 49. FIG.

Further, during a period P10 that partially overlaps with the period P9, the N data bit signals held by the first memory 55 of one ADC 21 are held in the second bit memories 250a to 250d as in the previous period P4. be. Then, the N data bit signals held by the first memory 55 of the ADC 21 in another row in the same column are held in the second bit memories 250e to 250h.

That is, the operation of outputting the S data held by the second bit memories 250a to 250h in the other column of the second bit memory section 250 to the transmission line group 49, and h can be performed in parallel. This is due to the fact that the second bit memories 250a-250h have a plurality of columns for the one column of the first bit memories 550a-550d. In other words, a plurality of second bit memories 250a are provided for the first bit memory 550a, and bit signals can be selectively output from the plurality of second bit memories 250a. This reduces the waiting time for transfer from the first bit memories 550a-d to the second bit memories 250a-h.

Also, in this embodiment, the first bit memories 550a-d are serially transmitted through the transmission line 43. FIG. On the other hand, the second bit memories 250a-h are transmitted in parallel by transmission lines 520a-h and transmission lines 490a-h. As a result, the wiring area of the transmission lines in the AD conversion area 22 can be reduced by serially transmitting the signals from the first bit memories 550a to 550d. The AD conversion area 22 comprises a circuit having many elements for AD conversion. Therefore, when a sufficient area for the AD conversion region 22 cannot be secured, the number of AD conversion units may be reduced. In this case, the period required to finish the AD conversion of the pixels 11 of multiple rows becomes long. Therefore, by reducing the wiring area of the transmission lines, which causes pressure on the area of the AD converters, it is possible to secure a sufficient number of AD converters.

On the other hand, serial transmission takes more time than parallel transmission to transmit a digital signal of a plurality of bits. Therefore, the digital signal from the buffer memory 25 provided outside the AD conversion area is transmitted in parallel. This makes it possible to speed up reading of digital signals corresponding to the pixels 11 in multiple rows and multiple columns from the imaging device.

Further, high-speed reading of digital signals by parallel transmission causes noise due to signal fluctuations in scanning signals and signal fluctuations in transmission lines. When this noise propagates to the AD converter, it causes a decrease in AD conversion accuracy. Specifically, when noise is superimposed on the power line of the comparator 51, the transmission line of the ramp signal VRMP, and the transmission line between the signal line 201 and the comparator 51, the timing at which the signal level of the comparison result signal changes is The timing is different from the original timing. Therefore, a digital signal different from the value of the originally obtained digital signal is obtained. On the other hand, the imaging apparatus of this embodiment has a buffer memory for noise parallel transmission provided outside the AD conversion area 22 . As a result, it is possible to suppress deterioration in accuracy of AD conversion.

Further, when the digital signal is transmitted from the AD conversion area 22 to the DFE 28 without the buffer memory 25, there is the following problem. In this case, it is assumed that an XY address is specified and a digital signal is read out from among the AD converters 21 of multiple rows and multiple columns. The AD conversion area 22 is provided with many elements for performing AD conversion including the comparator 51 . Therefore, when a digital signal is transmitted from the AD conversion area 22 to the DFE 28, the difference between the shortest AD converter 21 and the longest AD converter 21 in the transmission path between the AD converter 21 and the DFE 28 becomes large. . Therefore, if the transmission time from the AD conversion section 21 to the DFE 28 is determined based on the AD conversion section 21 having the longest transmission distance, the transmission time of the digital signal from the AD conversion region 22 to the DFE 28 becomes long. On the other hand, if the transmission time from the AD conversion unit 21 to the DFE 28 is determined based on the AD conversion unit 21 having the shortest transmission distance, a digital signal transmission failure from the AD conversion region 22 to the DFE 28 occurs.

On the other hand, in this embodiment, a digital signal is transmitted to the buffer memory 25 by vertical scanning from the multi-row multi-column AD converters 21 . A digital signal is transmitted to the DFE 28 by vertical scanning and horizontal scanning of the buffer memory 25 . Thereby, the difference in the transmission distance of the digital signal from each AD converter 21 to the DFE 28 can be reduced. As a result, high-speed digital signal transmission can be performed while ensuring a sufficient length of time for digital signal transmission.

In this embodiment, an example in which one transmission line 43 is provided for one column and multiple rows of AD converters 21 has been described, but the present invention is not limited to this example. For example, as shown in FIG. 8, among the AD converters 21 arranged in one column and multiple rows, some of the AD converters 21 are connected to the transmission line 43-1, and some of the AD converters 21 are connected to the transmission line 43-1. 43-2 may be used. In this case, bit signals can be transmitted to the buffer memory 25 in parallel from the AD converters 21 in multiple rows.

In this embodiment, one of the transmission lines 520a to 520h is provided corresponding to one of the bit memories 250a to 250h, but the present invention is not limited to this example. That is, a transmission line 520a (second transmission line) is connected to a plurality of second bit memories that are part of the second bit memories 250a to 250h, and another transmission line 520b (third transmission line) is connected to the second bit memory 250a. 1 through h may be connected to a plurality of second bit memories. In this case, bit signals are transmitted in parallel from part of the second bit memory and part of the other bit memory. Therefore, the effect of increasing the speed of signal transmission from the buffer memory 25 to the DFE 28 is obtained.

Also, in this embodiment, as an example of the reference signal input to the comparator 51, the ramp signal is used. The present embodiment is not limited to this example, and another example of the reference signal may be a reference signal used for successive approximation AD conversion.

(Example 2)
The description will focus on the differences from the imaging apparatus of the first embodiment. The imaging device of Example 1 was an imaging device in which the first chip 1 and the second chip 5 were stacked. The image pickup device of this embodiment is an image pickup device in which three chips are stacked as a first chip, a second chip, and a third chip.

FIG. 9 is a schematic diagram of the imaging device of this embodiment. A first chip 101, a second chip 102 and a third chip 103 are stacked. In the first chip 101, the photoelectric conversion units 13 are arranged over a plurality of rows and a plurality of columns.

In the second chip 102, the AD converters 21 are arranged over a plurality of rows and a plurality of columns.

In the third chip 103, regions including the buffer memory 25 and the DFE 28 are arranged in multiple rows and multiple columns.

FIG. 10(a) is a block diagram showing the configuration of the imaging apparatus of this embodiment. In FIG. 10(a), blocks having the same functions as the blocks shown in FIG. 3 are given the same reference numerals as those shown in FIG. The imaging apparatus of this embodiment is provided with a first memory 55 outside the AD converter 21 . The first memory 55 is arranged on the third chip 103 . In this embodiment, a memory area in which a plurality of rows and columns of first memories 55 are arranged is arranged in an area different from the AD conversion area 22 .

FIG. 10B is a block diagram showing a configuration related to the AD converter 21 of this embodiment. The configuration can be the same as that of FIG. 4B except that the first memory 55 is provided outside the AD converter 21 .

Also in this embodiment, the signal transmission between the first memory 55 and the buffer memory 25 and the signal transmission between the buffer memory 25 and the DFE 28 can be the same as in the first embodiment.

As described above, the image pickup apparatus of the present embodiment is similar to that of the first embodiment even when the AD conversion section having the comparator 51 and the first memory 55 for receiving the output of the AD conversion section are provided in separate chips. You can get the same effect.

(Example 3)
The image pickup apparatus of this embodiment will be described with a focus on the differences from the first embodiment.

In the imaging apparatus of this embodiment, the transistors (amplifying transistors 607 in the first embodiment) whose input nodes are connected to the FD section 605 operate as input transistors of a differential pair included in the comparator.

FIG. 11 is a circuit diagram showing the circuit of the imaging device of this embodiment.

A pixel 912 having a photoelectric conversion unit (photodiode) 913 , a transfer transistor 914 , a reset transistor 915 , and an FD unit 920 is arranged in the first chip 1 . The pixels 912 are arranged in multiple rows and multiple columns as in FIG.

The pixel 912 also has input transistors 917 - 1 and 917 - 2 and a current source 919 .

The second chip 5 includes a transistor group 918, a memory section 921, and a ramp signal generation section 911 that form a current mirror circuit.

A common node of the transistor group 918 is supplied with the power supply voltage VDD. One main node of current source 919 is connected to input transistors 917-1 and 917-2. The other main node of current source 919 is supplied with power supply voltage GND (ground potential).

A differential pair 925 is composed of input transistors 917-1 and 917-2, a transistor group 918 forming a current mirror circuit, and a current source 919. FIG. Input transistors 917 - 1 and 917 - 2 are provided as a plurality of input nodes of the differential pair 925 . The input transistor 917 - 1 of the differential pair 925 has its gate, which is a control node, connected to the FD section 920 . Since the input transistor 917-1 is connected to the photoelectric conversion unit 913 via the transfer transistor 914, the input transistor 917-1 can be said to be an input node of the differential pair 925 connected to the photoelectric conversion unit 913. .

Further, since the gate, which is the control node of the input transistor 917-2, is connected to the ramp signal generator 911 via the transmission line 916, the ramp signal generator 911 is connected to the input transistor 917-2. It can also be said that it is an input node of the differential pair 925 .

The input transistors 917-1 and 917-2 and the current source 919, which are part of the differential pair 925, are arranged on the first chip 1 where the photoelectric conversion section 913 is arranged. On the other hand, a transistor group 918 that is a current mirror circuit that is another part of the differential pair 925 is arranged on the second chip 5 . In this embodiment, the ramp signal generation unit 911 is the input transistors 917-1 and 917-2 that are part of the differential pair 925, and the current source 919 is the first chip 1 in which the photoelectric conversion unit 913 is arranged. It is arranged on a second chip 5 which is a chip different from that.

The differential pair 925 is a comparator that outputs a comparison result signal COUT indicating the result of comparing the potential of the control node of the input transistor 917-1 and the potential of the control node of the input transistor 917-2. That is, the comparator including the differential pair 925 and the memory section 921 are an AD conversion section that converts an analog signal based on the charge accumulated by the photoelectric conversion section 913 into a digital signal.

The memory unit 921 of this embodiment can be the first memory 55 described in the first embodiment. Then, the buffer memory 25 is provided after the first memory 55 as in the first embodiment. A DFE 28 is provided in the subsequent stage of the buffer memory 25 .

Signal transmission between the first memory 55 and the buffer memory 25 and signal transmission between the buffer memory 25 and the DFE 28 can be the same as in the first embodiment.

As described above, even when the input transistors having the input node to which the FD section (floating diffusion section) is connected are the input transistors of the differential pair as in the present embodiment, the imaging device of the first embodiment is the same. effect can be obtained.

In the embodiments described so far, the rolling shutter operation in which the start and end of the charge accumulation period of the pixels are different for each row has been described. The embodiments described so far can be performed even when the start and end of the charge accumulation period of the pixels are the same global shutter operation for a plurality of rows and a plurality of columns.

(Example 4)
FIG. 12 is a block diagram showing the configuration of an imaging system 500 according to this embodiment. An imaging system 500 of this embodiment includes an imaging device 200 to which any configuration of the imaging devices described in the above embodiments is applied. Specific examples of the imaging system 500 include a digital still camera, a digital camcorder, a surveillance camera, and the like. FIG. 12 shows a configuration example of a digital still camera to which one of the imaging apparatuses of the above-described embodiments is applied as an imaging apparatus 200. As shown in FIG.

An imaging system 500 illustrated in FIG. 12 includes an imaging device 200, a lens 5020 for forming an optical image of a subject on the imaging device 200, an aperture 504 for varying the amount of light passing through the lens 5020, and a lens for protecting the lens 5020. has a barrier 506 of A lens 5020 and a diaphragm 504 are an optical system that condenses light on the imaging device 200 .

The imaging system 500 also has a signal processing section 5080 that processes an output signal output from the imaging device 200 . The signal processing unit 5080 performs a signal processing operation of performing various corrections and compressions on an input signal and outputting the signal as necessary. The signal processing unit 5080 may have a function of performing AD conversion processing on the output signal output from the imaging device 200 . In this case, the imaging device 200 does not necessarily have an AD conversion circuit inside.

The imaging system 500 further includes a buffer memory section 510 for temporarily storing image data, and an external interface section (external I/F section) 512 for communicating with an external computer or the like. Further, the imaging system 500 includes a recording medium 514 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface section (recording medium control I/F section) 516 for recording or reading the recording medium 514. have Note that the recording medium 514 may be built in the imaging system 500 or may be detachable.

The imaging system 500 further includes an overall control/calculation unit 518 that performs various calculations and controls the entire digital still camera, and a timing generation unit 520 that outputs various timing signals to the imaging device 200 and the signal processing unit 5080 . Here, the timing signal and the like may be input from the outside, and the imaging system 500 only needs to have at least the imaging device 200 and the signal processing section 5080 that processes the output signal output from the imaging device 200 . The overall control/calculation unit 518 and the timing generation unit 520 may be configured to implement some or all of the control functions of the imaging device 200 .

The imaging device 200 outputs the image signal to the signal processing section 5080 . The signal processing unit 5080 performs predetermined signal processing on the image signal output from the imaging device 200 and outputs image data. Also, the signal processing unit 5080 generates an image using the image signal.

By configuring an imaging system using the imaging apparatus according to each of the embodiments described above, it is possible to realize an imaging system capable of acquiring a higher-quality image.

(Example 5)
An imaging system and a moving object according to this embodiment will be described with reference to FIGS. 13 and 14. FIG.

FIG. 13 is a schematic diagram showing a configuration example of an imaging system and a moving object according to this embodiment. FIG. 14 is a flowchart showing the operation of the imaging system according to this embodiment.

In this embodiment, an example of an imaging system for an in-vehicle camera is shown. FIG. 13 shows an example of a vehicle system and an imaging system mounted thereon. The imaging system 701 includes an imaging device 702 , an image preprocessor 715 , an integrated circuit 703 and an optical system 714 . An optical system 714 forms an optical image of a subject on the imaging device 702 . The imaging device 702 converts the optical image of the object formed by the optical system 714 into an electrical signal. The imaging device 702 is one of the imaging devices of the embodiments described above. An image preprocessing unit 715 performs predetermined signal processing on the signal output from the imaging device 702 . The functionality of the image preprocessor 715 may be incorporated within the imaging device 702 . The imaging system 701 is provided with at least two sets of an optical system 714 , an imaging device 702 , and an image preprocessing unit 715 . It's becoming

The integrated circuit 703 is an integrated circuit for use in an imaging system, and includes an image processing unit 704 including a memory 705 , an optical distance measurement unit 706 , a parallax calculation unit 707 , an object recognition unit 708 and an abnormality detection unit 709 . An image processing unit 704 performs image processing such as development processing and defect correction on the output signal of the image preprocessing unit 715 . A memory 705 temporarily stores captured images and stores defect positions of captured pixels. An optical distance measurement unit 706 performs focusing and distance measurement on a subject. A parallax calculation unit 707 calculates parallax (phase difference of parallax images) from a plurality of image data acquired by a plurality of imaging devices 702 . An object recognition unit 708 recognizes subjects such as cars, roads, signs, and people. The abnormality detection unit 709 notifies the main control unit 713 of the abnormality when detecting the abnormality of the imaging device 702 .

The integrated circuit 703 may be implemented by specially designed hardware, software modules, or a combination thereof. Moreover, it may be implemented by FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or the like, or by a combination thereof.

A main control unit 713 integrates and controls the operations of the imaging system 701, the vehicle sensor 710, the control unit 720, and the like. A method in which the imaging system 701, the vehicle sensor 710, and the control unit 720 have separate communication interfaces without having the main control unit 713, and each of them transmits and receives control signals via a communication network (for example, CAN standard). can also take

The integrated circuit 703 has a function of receiving a control signal from the main control unit 713 or transmitting a control signal and setting values to the imaging device 702 by its own control unit. For example, the integrated circuit 703 transmits settings for pulse-driving the voltage switch 13 in the imaging device 702, settings for switching the voltage switch 13 for each frame, and the like.

The imaging system 701 is connected to a vehicle sensor 710, and can detect the running state of the own vehicle such as vehicle speed, yaw rate, and steering angle, the environment outside the own vehicle, and the states of other vehicles and obstacles. The vehicle sensor 710 also serves as distance information acquisition means for acquiring distance information from the parallax image to the object. The imaging system 701 is also connected to a driving support control unit 711 that performs various driving support functions such as automatic steering, automatic cruise, and anti-collision functions. In particular, regarding the collision determination function, based on the detection results of the imaging system 701 and the vehicle sensor 710, it is possible to estimate a collision with another vehicle/obstacle and determine whether or not there is a collision. As a result, avoidance control when a collision is presumed and safety device activation at the time of collision are performed.

The imaging system 701 is also connected to an alarm device 712 that issues an alarm to the driver based on the determination result of the collision determination unit. For example, if the collision determination unit determines that there is a high probability of collision, the main control unit 713 controls the vehicle to avoid collisions and reduce damage by applying the brakes, releasing the accelerator, or suppressing engine output. conduct. The alarm device 712 warns the user by sounding an alarm such as sound, displaying alarm information on a display unit screen of a car navigation system or a meter panel, or vibrating a seat belt or steering wheel.

In this embodiment, the image pickup system 701 photographs the surroundings of the vehicle, for example, the front or rear. FIG. 13B shows an arrangement example of the image pickup system 701 when the image pickup system 701 picks up an image in front of the vehicle.

Two imaging devices 702 are arranged in front of the vehicle 700 . Specifically, if the center line of the vehicle 700 with respect to the forward/retreat direction or the outer shape (for example, the width of the vehicle) is regarded as the axis of symmetry, and the two imaging devices 702 are arranged symmetrically with respect to the axis of symmetry, the vehicle 700 and the subject are arranged. This is preferable for obtaining information on the distance to the photographed object and determining the possibility of collision. In addition, the imaging device 702 is preferably arranged so as not to obstruct the driver's field of view when the driver visually recognizes the situation outside the vehicle 700 from the driver's seat. It is preferable that the warning device 712 be arranged so as to be easily visible to the driver.

Next, failure detection operation of the imaging device 702 in the imaging system 701 will be described with reference to FIG. The failure detection operation of the imaging device 702 is performed according to steps S810 to S880 shown in FIG.

Step S<b>810 is a step of performing settings for startup of the imaging device 702 . That is, the setting for the operation of the imaging device 702 is transmitted from the outside of the imaging system 701 (for example, the main control unit 713) or the inside of the imaging system 701, and the imaging operation and failure detection operation of the imaging device 702 are started.

Next, in step S820, pixel signals are obtained from effective pixels. Also, in step S830, an output value is obtained from a failure detection pixel provided for failure detection. This failure detection pixel has a photoelectric conversion section like the effective pixel. A predetermined voltage is written in the photoelectric conversion unit. The failure detection pixel outputs a signal corresponding to the voltage written to the photoelectric conversion section. Note that steps S820 and S830 may be reversed.

Next, in step S840, whether or not the expected output value of the failure-detected pixel corresponds to the actual output value from the failure-detected pixel is determined.

As a result of the pertinence determination in step S840, if the expected output value and the actual output value match, the process proceeds to step S850, it is determined that the imaging operation is performed normally, and the processing step proceeds to step S860. and migrate. In step S860, the pixel signals of the scanning line are transmitted to the memory 705 for temporary storage. After that, the process returns to step S820 to continue the failure detection operation.

On the other hand, if the result of the pertinence determination in step S840 is that the expected output value and the actual output value do not match, the process proceeds to step S870. In step S870, it is determined that there is an abnormality in the imaging operation, and an alarm is issued to the main control unit 713 or the alarm device 712. FIG. The alarm device 712 causes the display unit to display that an abnormality has been detected. After that, in step S880, the imaging device 702 is stopped, and the operation of the imaging system 701 ends.

In this embodiment, the flowchart is looped for each line, but the flowchart may be looped for a plurality of lines, or the failure detection operation may be performed for each frame.

Note that the issuing of the warning in step S870 may be notified to the outside of the vehicle via a wireless network.

In addition, in this embodiment, control for avoiding collision with other vehicles has been described, but it is also applicable to control for automatically driving following another vehicle or control for automatically driving so as not to stray from the lane. . Furthermore, the imaging system 701 can be applied not only to vehicles such as the own vehicle, but also to moving objects (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to mobile objects but also to devices that widely use object recognition, such as intelligent transportation systems (ITS).

[Modified embodiment]
The present invention is not limited to the above embodiments, and various modifications are possible.

For example, an example in which a part of the configuration of one of the embodiments is added to another embodiment or an example in which a part of the configuration of another embodiment is replaced is also an embodiment of the present invention.

In addition, the above-described embodiments are merely examples of specific implementations of the present invention, and the technical scope of the present invention should not be construed to be limited by these exemplifications. That is, the present invention can be embodied in various forms without departing from its technical concept or main features.

1 first chip 5 second chip 21 AD converter (ADC)
22 AD conversion area (ADC Array)
25 buffer memory 28 digital signal processing circuit (DFE)
30 timing generator (TG)
31 counter 35 ramp signal generator

Claims (23)

a plurality of arrays each having a plurality of AD converters for converting analog signals into digital signals;
a counter that outputs a count signal to the plurality of AD converters arranged in each of the plurality of arrays ;
a ramp signal generation circuit for generating a ramp signal to be supplied to the plurality of AD converters arranged in each of the plurality of arrays ;
The counter is arranged in a region between a first array and a second array among the plurality of arrays in plan view,
The ramp signal generation circuit is arranged in a region different from the above region and between one array of the plurality of arrays and another one of the arrays. circuit. 2. The circuit of claim 1, wherein the area between said one array and said another array is free of said other counters . including a plurality of circuit regions including a first circuit region and a second circuit region ;
each of the plurality of circuit regions,
an array including a plurality of AD converters for converting analog signals to digital signals;
a memory array including a plurality of memories holding the digital signals output from the array ;
the first circuit region has a first array as the array;
the second circuit region has a second array as the array;
a counter that outputs a count signal to each of the plurality of AD converters in each of the plurality of circuit regions ;
a ramp signal generation circuit for generating a ramp signal to be supplied to the plurality of AD converters arranged in each of the plurality of circuit regions ;
the counter is arranged in a region between a first circuit region and a second circuit region among the plurality of circuit regions ;
wherein the ramp signal generation circuit is disposed in a region different from the region and between one circuit region and another circuit region among the plurality of circuit regions; A circuit characterized by: 4. The circuit according to claim 3, wherein no other said counters are arranged in a region between said one circuit region and said another one circuit region . The plurality of AD conversion units are arranged over a plurality of rows and columns,
a first line that transmits the count signal to a plurality of AD converters arranged in a plurality of columns in one row among the plurality of rows;
a second line for transmitting the count signal to a plurality of AD converters arranged in a plurality of columns of another row among the plurality of rows;
A circuit as claimed in any preceding claim, comprising a third line for supplying said count signal to said first line and said second line . a scanning circuit that scans the plurality of AD converters of the first array and sequentially reads out the digital signals from the AD converters;
the plurality of AD converters to which the first line is connected are connected to the scanning circuit by the first scanning line;
6. The circuit according to claim 5 , wherein the plurality of AD converters to which the second lines are connected are connected to the scanning circuit by the second scanning lines. Having a first digital signal processing circuit that processes the digital signal,
7. A circuit as claimed in any preceding claim, wherein the first array is arranged in an area between the counter and the first digital signal processing circuit. A first interface unit that outputs a signal to the outside of the circuit,
8. The circuit of claim 7 , wherein the first digital signal processing circuit is arranged between the first interface section and the first array. A first memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns each holding the digital signal is arranged between the first array and the first digital signal processing circuit. 9. A circuit according to claim 7 or 8 , characterized in that: Having a second digital signal processing circuit that processes the digital signal,
9. A circuit according to any one of claims 7 to 8 , characterized in that said second array is arranged in an area between said counter and said second digital signal processing circuit. A second interface unit that outputs a signal to the outside of the circuit,
11. The circuit of claim 10 , wherein the second digital signal processing circuit is arranged between the second interface section and the second array. A second memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns each holding the digital signal is arranged between the second array and the second digital signal processing circuit. 12. A circuit according to claim 10 or 11 , characterized in that: 13. The method according to any one of claims 10 to 12, wherein a fourth array among the plurality of arrays is arranged between the ramp signal generation circuit and the second digital signal processing circuit. Circuit as described. The circuit includes a second scanning circuit that scans a plurality of analog output circuits that output the analog signal,
14. The circuit of claim 13 , wherein a third of said plurality of arrays is provided between said second scanning circuit and said first array. 15. The circuit of claim 14 , wherein said fourth array is provided between said second scanning circuit and said second array. A third memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns each holding the digital signal is arranged between the third array and the first digital signal processing circuit. 16. A circuit according to claim 14 or 15 , characterized in that: The circuit further has a third array and a fourth array in which a plurality of AD converters are arranged over a plurality of rows and a plurality of columns,
a third memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns each holding the digital signal, arranged between the third array and the first digital signal processing circuit;
The circuit includes a second scanning circuit that scans a plurality of analog output circuits that output the analog signal,
10. The circuit of claim 9 , wherein said third memory array is disposed between said second scanning circuit and said first memory array. Having a second digital signal processing circuit that processes the digital signal,
the second array is arranged in an area between the counter and the second digital signal processing circuit;
between the second array and the second digital signal processing circuit, a second memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns each holding the digital signal;
a fourth memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns each holding the digital signal, arranged between the fourth array and the second digital signal processing circuit;
18. The circuit of claim 17 , wherein said fourth memory array is interposed between said second scanning circuit and said second memory array. a plurality of arrays each having a plurality of AD converters for converting analog signals into digital signals;
a counter that outputs a count signal to the plurality of AD converters arranged in each of the plurality of arrays ;
a ramp signal generation circuit for generating a ramp signal to be supplied to the plurality of AD converters arranged in each of the plurality of arrays ;
The counter is arranged in a region between a first array and a second array among the plurality of arrays in plan view,
The ramp signal generation circuit is arranged in a region different from the above region and between one array of the plurality of arrays and another one of the arrays. chips. including a plurality of circuit regions including a first circuit region and a second circuit region ;
each of the plurality of circuit regions,
an array including a plurality of AD converters for converting analog signals to digital signals;
a memory array including a plurality of memories holding the digital signals output from the array ;
the first circuit region has a first array as the array;
the second circuit region has a second array as the array;
a counter that outputs a count signal to each of the plurality of AD converters in each of the plurality of circuit regions ;
a ramp signal generation circuit for generating a ramp signal to be supplied to the plurality of AD converters arranged in each of the plurality of circuit regions ;
the counter is arranged in a region between a first circuit region and a second circuit region among the plurality of circuit regions ;
wherein the ramp signal generation circuit is disposed in a region different from the region and between one circuit region and another circuit region among the plurality of circuit regions; Characteristic chip. A chip on which the circuit according to any one of claims 1 to 18 is arranged;
An imaging device in which another chip having a photoelectric conversion unit that outputs the analog signal to the chip is stacked. 22. An image pickup system comprising: the image pickup apparatus according to claim 21 ; and a signal processing section that processes a signal output from the image pickup apparatus. A moving body having the imaging device according to claim 21 ,
A moving object, further comprising a control unit for controlling movement of the moving object.

Images