JP2020115698A5 - Circuits, chips, imaging devices, imaging systems, mobiles - Google Patents
Circuits, chips, imaging devices, imaging systems, mobiles Download PDFInfo
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- 238000003384 imaging method Methods 0.000 title claims description 8
- 238000006243 chemical reaction Methods 0.000 claims description 16
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 4
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Description
本発明は、回路、チップ、撮像装置、撮像システム、移動体に関する。 The present invention relates to circuits, chips, imaging devices, imaging systems, and mobile objects.
本発明は上記の課題を鑑みて為されたものであり、一の態様は、アナログ信号をデジタル信号に変換する複数のＡＤ変換部が、それぞれにおいて複数行および複数列に渡って配された第１アレイおよび第２アレイと、前記第１アレイに配された前記複数のＡＤ変換部と、前記第２アレイに配された前記複数のＡＤ変換部の両方にカウント信号を出力するカウンタとを備え、前記カウンタが、平面視において、前記第１アレイと前記第２アレイの間の領域に配されていることを特徴とする回路である。 The present invention has been made in view of the above problems, and one aspect is that a plurality of AD conversion units for converting an analog signal into a digital signal are arranged in a plurality of rows and a plurality of columns, respectively. The first array and the second array, the plurality of AD conversion units arranged in the first array, and a counter that outputs a count signal to both the plurality of AD conversion units arranged in the second array are provided. , The counter is a circuit characterized in that it is arranged in a region between the first array and the second array in a plan view .
Claims (24)
前記第１アレイに配された前記複数のＡＤ変換部と、前記第２アレイに配された前記複数のＡＤ変換部の両方にカウント信号を出力するカウンタとを備え、
前記カウンタが、平面視において、前記第１アレイと前記第２アレイの間の領域に配されていることを特徴とする回路。 A first array and a second array in which a plurality of AD converters for converting an analog signal into a digital signal are arranged over a plurality of rows and columns, respectively.
A counter for outputting a count signal to both the plurality of AD conversion units arranged in the first array and the plurality of AD conversion units arranged in the second array is provided.
A circuit characterized in that the counter is arranged in a region between the first array and the second array in a plan view.
前記第１回路領域は、
アナログ信号をデジタル信号に変換する複数のＡＤ変換部を含む第１アレイと、
前記第１アレイから出力される前記デジタル信号を保持する複数のメモリを含む第１メモリアレイとを含み、
前記第２回路領域は、
アナログ信号をデジタル信号に変換する複数のＡＤ変換部を含む第２アレイと、
前記第２アレイから出力される前記デジタル信号を保持する複数のメモリを含む第２メモリアレイとを含み、
前記第１アレイの前記複数のＡＤ変換回路と、前記第２アレイの前記複数のＡＤ変換回路の両方にカウント信号を出力するカウンタを備え、
前記カウンタが、前記第１回路領域と前記第２回路領域の間の領域に配されていることを特徴とする回路。 Including the first circuit area and the second circuit area,
The first circuit area is
A first array containing a plurality of AD converters that convert analog signals to digital signals, and
A first memory array including a plurality of memories for holding the digital signal output from the first array, and the like.
The second circuit area is
A second array containing a plurality of AD converters that convert analog signals to digital signals, and
A second memory array including a plurality of memories for holding the digital signal output from the second array, and the like.
A counter for outputting a count signal to both the plurality of AD conversion circuits of the first array and the plurality of AD conversion circuits of the second array is provided.
A circuit characterized in that the counter is arranged in a region between the first circuit region and the second circuit region .
前記第１線と前記第２線はそれぞれ、前記第１アレイのうちの互いに異なる複数のＡＤ変換部に接続され、
前記第３線は、前記第１線と前記第２線とに接続されていることを特徴とする請求項１または２に記載の回路。 Each has a first line, a second line, and a third line that transmit the count signal.
The first line and the second line are each connected to a plurality of different AD converters in the first array.
The circuit according to claim 1 or 2 , wherein the third wire is connected to the first wire and the second wire.
前記第１線が接続された複数のＡＤ変換部は前記走査回路と第１走査線で接続され、
前記第２線が接続された複数のＡＤ変換部は前記走査回路と第２走査線で接続されることを特徴とする請求項３に記載の回路。 It has a scanning circuit that scans the plurality of AD conversion units of the first array and sequentially reads out the digital signal from the AD conversion unit.
The plurality of AD conversion units to which the first line is connected are connected to the scanning circuit by the first scanning line.
The circuit according to claim 3 , wherein the plurality of AD conversion units to which the second line is connected are connected to the scanning circuit by the second scanning line.
前記第１アレイは、前記カウンタと、前記第１デジタル信号処理回路との間の領域に配されていることを特徴とする請求項１～４のいずれか１項に記載の回路。 It has a first digital signal processing circuit that processes the digital signal.
The circuit according to any one of claims 1 to 4 , wherein the first array is arranged in a region between the counter and the first digital signal processing circuit.
前記第１インターフェース部と前記第１アレイとの間に、前記第１デジタル信号処理回路が配されていることを特徴とする請求項５に記載の回路。 A first interface unit that outputs a signal is provided outside the circuit.
The circuit according to claim 5 , wherein the first digital signal processing circuit is arranged between the first interface unit and the first array.
前記第２アレイは、前記カウンタと、前記第２デジタル信号処理回路との間の領域に配されていることを特徴とする請求項５～７のいずれか１項に記載の回路。 It has a second digital signal processing circuit that processes the digital signal.
The circuit according to any one of claims 5 to 7 , wherein the second array is arranged in a region between the counter and the second digital signal processing circuit.
前記第２インターフェース部と前記第２アレイとの間に、前記第２デジタル信号処理回路が配されていることを特徴とする請求項８に記載の回路。 A second interface unit that outputs a signal is provided outside the circuit.
The circuit according to claim 8 , wherein the second digital signal processing circuit is arranged between the second interface unit and the second array.
前記第３アレイと前記第４アレイの間に、ランプ信号を生成するランプ信号生成回路が配されていることを特徴とする請求項５～７のいずれか１項に記載の回路。 The circuit further comprises a third array and a fourth array in which the plurality of AD converters are arranged over a plurality of rows and columns, respectively.
The circuit according to any one of claims 5 to 7 , wherein a lamp signal generation circuit for generating a lamp signal is arranged between the third array and the fourth array.
前記第３アレイと前記第４アレイの間に、ランプ信号を生成するランプ信号生成回路が配されていることを特徴とする請求項８～１０のいずれか１項に記載の回路。 The circuit further comprises a third array and a fourth array in which the plurality of AD converters are arranged over a plurality of rows and columns, respectively.
The circuit according to any one of claims 8 to 10 , wherein a lamp signal generation circuit for generating a lamp signal is arranged between the third array and the fourth array.
前記第２走査回路と、前記第１アレイの間に前記第３アレイが設けられていることを特徴とする請求項１１～１４のいずれか１項に記載の回路。 The circuit includes a second scanning circuit that scans a plurality of analog output circuits that output the analog signal.
The circuit according to any one of claims 1 to 14 , wherein the third array is provided between the second scanning circuit and the first array.
前記第３アレイと前記第１デジタル信号処理回路の間に、各々が前記デジタル信号を保持する複数行および複数列に渡って配された複数のメモリを有する第３メモリアレイが配され、
前記回路は、前記アナログ信号を出力する複数のアナログ出力回路を走査する第２走査回路を備え、
前記第２走査回路と前記第１メモリアレイとの間に、前記第３メモリアレイが配されている請求項７に記載の回路。 The circuit further comprises a third array and a fourth array in which the plurality of AD converters are arranged over a plurality of rows and columns, respectively.
Between the third array and the first digital signal processing circuit, a third memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns, each of which holds the digital signal, is arranged.
The circuit includes a second scanning circuit that scans a plurality of analog output circuits that output the analog signal.
The circuit according to claim 7 , wherein the third memory array is arranged between the second scanning circuit and the first memory array.
前記第２アレイは、前記カウンタと、前記第２デジタル信号処理回路との間の領域に配され、
前記第２アレイと前記第２デジタル信号処理回路の間に、各々が前記デジタル信号を保持する複数行および複数列に渡って配された複数のメモリを有する第２メモリアレイを有し、
前記第４アレイと前記第２デジタル信号処理回路の間に、各々が前記デジタル信号を保持する複数行および複数列に渡って配された複数のメモリを有する第４メモリアレイが配され、
前記第２走査回路と前記第２メモリアレイとの間に、前記第４メモリアレイが配されている請求項１８に記載の回路。 It has a second digital signal processing circuit that processes the digital signal.
The second array is arranged in the area between the counter and the second digital signal processing circuit.
Between the second array and the second digital signal processing circuit, there is a second memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns, each of which holds the digital signal.
Between the fourth array and the second digital signal processing circuit, a fourth memory array having a plurality of memories arranged over a plurality of rows and a plurality of columns, each of which holds the digital signal, is arranged.
The circuit according to claim 18 , wherein the fourth memory array is arranged between the second scanning circuit and the second memory array.
前記第１アレイに配された前記複数のＡＤ変換部と、前記第２アレイに配された前記複数のＡＤ変換部の両方にカウント信号を出力するカウンタとを備え、
前記カウンタが、平面視において、前記第１アレイと前記第２アレイの間の領域に配されていることを特徴とするチップ。 A first array and a second array in which a plurality of AD converters for converting an analog signal into a digital signal are arranged over a plurality of rows and columns, respectively.
A counter for outputting a count signal to both the plurality of AD conversion units arranged in the first array and the plurality of AD conversion units arranged in the second array is provided.
A chip characterized in that the counter is arranged in a region between the first array and the second array in a plan view.
前記第１回路領域は、
アナログ信号をデジタル信号に変換する複数のＡＤ変換部を含む第１グループと、
前記第１グループから出力される前記デジタル信号を保持する複数のメモリを含む第１メモリグループとを含み、
前記第２回路領域は、
アナログ信号をデジタル信号に変換する複数のＡＤ変換部を含む第２グループと、
前記第２グループから出力される前記デジタル信号を保持する複数のメモリを含む第２メモリグループとを含み、
前記第１グループの前記複数のＡＤ変換回路と、前記第２グループの前記複数のＡＤ変換回路の両方にカウント信号を出力するカウンタを備え、
前記カウンタが、前記第１回路領域と前記第２回路領域の間の領域に配されていることを特徴とするチップ。 Including the first circuit area and the second circuit area,
The first circuit area is
The first group, which includes a plurality of AD converters that convert analog signals to digital signals,
A first memory group including a plurality of memories for holding the digital signal output from the first group is included.
The second circuit area is
A second group containing multiple AD converters that convert analog signals to digital signals,
A second memory group including a plurality of memories for holding the digital signal output from the second group is included.
A counter for outputting a count signal to both the plurality of AD conversion circuits of the first group and the plurality of AD conversion circuits of the second group is provided.
A chip characterized in that the counter is arranged in a region between the first circuit region and the second circuit region .
前記アナログ信号を前記チップに出力する、光電変換部を備える別のチップとが積層された撮像装置。 The chip to which the circuit according to any one of claims 1 to 19 is arranged, and
An image pickup device in which another chip including a photoelectric conversion unit that outputs the analog signal to the chip is laminated.
前記移動体の移動を制御する制御部をさらに有することを特徴とする移動体。 A mobile body having the image pickup apparatus according to claim 22 .
A moving body having a control unit for controlling the movement of the moving body.
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| JP2020083333A JP7167086B2 (en) | 2020-05-11 | 2020-05-11 | circuit, chip, imaging device, imaging system, moving body |
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| JP2020083333A JP7167086B2 (en) | 2020-05-11 | 2020-05-11 | circuit, chip, imaging device, imaging system, moving body |
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| JP2018022403A Division JP6704944B2 (en) | 2018-02-09 | 2018-02-09 | Imaging device, imaging system, moving body |
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| JP2020115698A5 true JP2020115698A5 (en) | 2022-02-07 |
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| JPWO2016151837A1 (en) | 2015-03-26 | 2018-01-18 | オリンパス株式会社 | Solid-state imaging device |
| CN117012796A (en) | 2016-03-31 | 2023-11-07 | 株式会社尼康 | Image pickup element and image pickup device |
| JP2017192056A (en) | 2016-04-14 | 2017-10-19 | ソニー株式会社 | Solid state image sensor, imaging apparatus, and electronic apparatus |
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