JP7165612B2 - Semiconductor capacitor device and semiconductor capacitor device module - Google Patents

Description

The present invention relates to a semiconductor capacitor device and a semiconductor capacitor device module.

Conventionally, an invention for reducing heat generation during operation of a capacitor is known (Patent Document 1). In the invention described in Patent Document 1, an uneven structure is formed in a dielectric layer of a capacitor, and the direction of the uneven structure is perpendicular to the direction from the upper electrode to the lower electrode, thereby reducing the equivalent series resistance.

JP 2016-195161 A

However, since the upper electrode and the lower electrode described in Patent Document 1 are positioned at both ends of the capacitor, the inductance of the current path increases when these electrodes are connected to external terminals. This may increase the surge voltage generated by the current during capacitor operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor capacitor device and a semiconductor capacitor device module capable of achieving both a reduction in equivalent series resistance and a reduction in inductance.

A semiconductor capacitor device according to an aspect of the present invention includes a semiconductor substrate, a dielectric layer formed inside the semiconductor substrate, a first electrode sandwiching the dielectric layer, and a second electrode having a polarity different from that of the first electrode. wherein a portion of at least one first electrode is arranged on the main surface of the semiconductor substrate, and portions of at least two second electrodes are arranged on the main surface so as to sandwich the first electrodes arranged on the main surface A semiconductor capacitor arranged, a first metal terminal joined to the first electrode, and a second metal terminal joined to each of the second electrodes.

According to the present invention, it is possible to achieve both a reduction in equivalent series resistance and a reduction in inductance.

1 is a plan view of a semiconductor capacitor device according to a first embodiment of the present invention; FIG. FIG. 2 is a side view of the semiconductor capacitor device according to the first embodiment of the invention. FIG. 3 is a plan view of the semiconductor capacitor device according to the first embodiment of the invention. FIG. 4 is a side view of the semiconductor capacitor device according to the first embodiment of the invention. FIG. 5 is a side view of the semiconductor capacitor device according to the first embodiment of the invention. FIG. 6 is a plan view of a semiconductor capacitor device according to a second embodiment of the invention. FIG. 7 is a side view of a semiconductor capacitor device according to a second embodiment of the invention. FIG. 8 is a side view of a semiconductor capacitor device according to a second embodiment of the invention. FIG. 9 is a plan view of a semiconductor capacitor device according to a third embodiment of the invention. 10 is a cross-sectional view of a semiconductor capacitor device according to a third embodiment of the present invention, taken along line AA of FIG. 9. FIG. FIG. 11 is a plan view of a semiconductor capacitor device according to a third embodiment of the invention. 12 is a cross-sectional view of a semiconductor capacitor device according to a third embodiment of the present invention, taken along line AA of FIG. 11. FIG. FIG. 13 is a cross-sectional view of a semiconductor capacitor device according to a fourth embodiment of the invention. FIG. 14 is a cross-sectional view of a semiconductor capacitor device according to a fifth embodiment of the invention. FIG. 15 is a cross-sectional view of a semiconductor capacitor device module according to a fifth embodiment of the invention. FIG. 16 is a side view of a semiconductor capacitor device module according to a fifth embodiment of the invention. FIG. 17 is a plan view of a semiconductor capacitor device module according to a sixth embodiment of the invention. 18 is a cross-sectional view of a semiconductor capacitor device module according to a sixth embodiment of the present invention, taken along line AA of FIG. 17. FIG. FIG. 19 is a plan view of a semiconductor capacitor device according to another embodiment of the invention. FIG. 20 is a side view of a semiconductor capacitor device according to another embodiment of the invention. FIG. 21 is a plan view of a semiconductor capacitor device according to another embodiment of the invention. FIG. 22 is a side view of a semiconductor capacitor device according to another embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the description of the drawings, the same parts are denoted by the same reference numerals, and the description thereof is omitted.

(First embodiment)
(Configuration example of a semiconductor capacitor device)
A semiconductor capacitor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. A semiconductor capacitor comprises a semiconductor substrate 1 . In this embodiment, the semiconductor substrate 1 is made of silicon (Si), but is not limited to this. The semiconductor substrate 1 may be made of silicon carbide (SiC), gallium nitride (GaN), or the like. In this embodiment, the semiconductor capacitor device will be described using an xyz orthogonal coordinate system. The width direction of the semiconductor capacitor device is defined as the x-axis direction. Further, the front-rear direction of the semiconductor capacitor device which is perpendicular to the x-axis direction is the z-axis direction, the x-axis direction and the z-axis direction are perpendicular to each other, and the height direction of the semiconductor capacitor device is the y-axis direction.

The semiconductor substrate 1 has a main surface 2 and a back surface (not shown in FIG. 1) facing the main surface 2, and the shape of the semiconductor substrate 1 is a flat plate. In this embodiment, the shape of the main surface 2 and the back surface is rectangular, but is not limited to this. The shape of the main surface 2 and the back surface may be circular.

Although not shown in FIG. 1, a groove is formed in the semiconductor substrate 1, and a dielectric layer made of a dielectric material is formed in the groove. Although the dielectric is not particularly limited, it is composed of, for example, a silicon nitride film _{( Si3N4} ), a silicon oxide film ( _SiO2 ), or the like. The dielectric layer is joined to a high potential electrode 3 and a low potential electrode 4 . Furthermore, although not shown in FIG. 1, the dielectric layer in the groove is sandwiched between a pair of conductors, and the pair of conductors are electrically insulated by the dielectric layer. A capacitor is composed of a dielectric layer and a pair of conductors sandwiching the dielectric layer. A pair of conductors are part of a high potential electrode 3 and a low potential electrode 4, which will be described later.

As shown in FIGS. 1 and 2, two high potential electrodes 3 and one low potential electrode 4 are arranged on the main surface 2 of the semiconductor substrate 1 . The high potential electrodes 3 are arranged so as to sandwich the low potential electrodes 4 . Also, the high potential electrode 3, the low potential electrode 4, and the high potential electrode 3 are arranged in this order along the x-axis direction. Although the shape of the high potential electrode 3 and the low potential electrode 4 arranged on the main surface 2 is not particularly limited, it is rectangular, for example. The high potential electrode 3 and the low potential electrode 4 are made of Al, Cu, Ti, Ni, Ag, or the like. A portion of the high potential electrode 3 and a portion of the low potential electrode 4 are arranged on the main surface 2 . The rest of the high potential electrode 3 and the rest of the low potential electrode 4 are formed inside the semiconductor substrate 1 .

Next, metal terminals for connecting the semiconductor capacitor according to the present embodiment to the outside will be described with reference to FIGS. 3 to 5. FIG.

As shown in FIGS. 3 to 5, a high potential metal terminal 5 (first metal terminal) is joined to the surface of the high potential electrode 3 . The surface of the high-potential electrode 3 is the surface opposite to the surface in contact with the main surface 2 . Similarly, a low potential metal terminal 6 (second metal terminal) is joined to the surface of the low potential electrode 4 . In the example shown in FIGS. 3-5, two high potential metal terminals 5 and one low potential metal terminal 6 are joined. That is, a high potential metal terminal 5 is joined to each of the high potential electrodes 3 . A well-known joining method (metal joining, pressure contact) is used for joining the high-potential metal terminal 5 and the low-potential metal terminal 6 .

Also, as shown in FIGS. 3 and 4, the high potential metal terminal 5 and the low potential metal terminal 6 are extended along the z-axis direction. Note that the two high-potential metal terminals 5 may be coupled at their ends.

(Effect)
According to the first embodiment, two high potential electrodes 3 arranged on the principal surface 2 sandwich one low potential electrode 4 arranged on the principal surface 2 . As a result, the current path from the high potential electrode 3 to the dielectric layer inside the semiconductor substrate 1 and the current path from the dielectric layer to the low potential electrode 4 are shortened, so that the equivalent series resistance can be reduced. can be done.

Further, according to the first embodiment, the high potential metal terminal 5 and the low potential metal terminal 6 are extended along the same direction (z direction). As a result, as shown in FIG. 3, a current 20 flowing from the high-potential metal terminal 5 to the semiconductor capacitor and a current 21 flowing from the semiconductor capacitor to the low-potential metal terminal 6 face each other. Therefore, due to the mutual inductance effect, the inductance from the high potential metal terminal 5 to the low potential metal terminal 6 via the semiconductor capacitor can be reduced. Similarly, the current 30 flowing from the high-potential metal terminal 5 to the semiconductor capacitor and the current 31 flowing from the semiconductor capacitor to the low-potential metal terminal 6 also oppose each other. This improves the effect of reducing the inductance. Note that the direction of the current 20 and the direction of the current 21 are opposite. Similarly, the direction of the current 30 and the direction of the current 31 are also opposite.

(Second embodiment)
(Configuration example of a semiconductor capacitor device)
Next, a semiconductor capacitor device according to a second embodiment of the present invention will be described with reference to FIGS. 6 to 8. FIG.

In the second embodiment, the high-potential metal terminal 5 and the low-potential metal terminal 6 are extended along the y-axis direction (the direction perpendicular to the main surface 2).

(Effect)
Also in the second embodiment, the same effect as in the first embodiment can be obtained. That is, the high-potential metal terminal 5 and the low-potential metal terminal 6 need only be extended along the same direction, and the extending direction may be the z-axis direction or the y-axis direction.

(Third Embodiment)
(Configuration example of a semiconductor capacitor device)
Next, a semiconductor capacitor device according to a third embodiment of the present invention will be described with reference to FIGS. 9 to 12. FIG.

In the third embodiment, as shown in FIGS. 9 to 10, a rectangular high-potential electrode 3 is arranged in the center of the main surface 2 of the semiconductor substrate 1. FIG. A hollow square low potential electrode 4 is arranged on the main surface 2 so as to surround the square high potential electrode 3 . A hollow square high-potential electrode 3 is arranged on the main surface 2 so as to surround the hollow square low-potential electrode 4 . That is, in the third embodiment, the low potential electrodes 4 are arranged so as to be surrounded by the high potential electrode 3 arranged in the center and the high potential electrodes 3 arranged outside.

In addition, in the third embodiment, metal terminals having the same shape as the high potential electrode 3 and the low potential electrode 4 shown in FIGS. Specifically, as shown in FIGS. 11 and 12, a square high-potential metal terminal 5, a hollow square low-potential metal terminal 6, and a hollow square high-potential metal terminal 5 are each formed into a square shape. high potential electrode 3 , hollow square low potential electrode 4 , and hollow square high potential electrode 3 . Moreover, the high-potential metal terminal 5 and the low-potential metal terminal 6 are extended along the y-axis direction (the direction perpendicular to the main surface 2).

(Effect)
According to the third embodiment, two high potential electrodes 3 are arranged to surround one low potential electrode 4 . As a result, compared with the first embodiment, the current path from the high potential electrode 3 to the dielectric layer inside the semiconductor substrate 1 and the current path from the dielectric layer to the low potential electrode 4 are further shortened. can be further reduced.

Further, according to the third embodiment, the area where the current flowing from the high-potential metal terminal 5 to the semiconductor capacitor faces the current flowing from the semiconductor capacitor to the low-potential metal terminal 6 is larger than in the first embodiment. Become. Therefore, the inductance from the high-potential metal terminal 5 to the low-potential metal terminal 6 via the semiconductor capacitor can be further reduced.

(Fourth embodiment)
(Configuration example of a semiconductor capacitor device)
Next, a semiconductor capacitor device according to a fourth embodiment of the present invention will be described with reference to FIG.

In the fourth embodiment, a dielectric layer 7 is formed inside the semiconductor substrate 1 in the y-axis direction (direction perpendicular to the main surface 2). Dielectric layer 7 is joined to high potential electrode 3 and low potential electrode 4 so as to be sandwiched between high potential electrode 3 and low potential electrode 4 in the x-axis direction. The high potential electrode 3 formed inside the semiconductor substrate 1 and the high potential electrode 3 arranged on the main surface 2 are integrally formed. Similarly, the low potential electrode 4 formed inside the semiconductor substrate 1 and the low potential electrode 4 arranged on the main surface 2 are integrally formed.

(Effect)
According to the fourth embodiment, since the dielectric layer 7 is formed in the direction perpendicular to the main surface 2 , the dielectric layer 7 extends from a portion of the high potential electrode 3 arranged on the main surface 2 to the dielectric layer 7 . A current path flowing from the dielectric layer 7 to a portion of the low potential electrode 4 disposed on the main surface 2 opposes each other to reduce the inductance of the semiconductor capacitor due to the mutual inductance effect. As a result, the inductance from the high-potential metal terminal 5 to the low-potential metal terminal 6 via the semiconductor capacitor can be further reduced as compared with the first embodiment.

(Fifth embodiment)
(Configuration example of a semiconductor capacitor device)
Next, a semiconductor capacitor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 14 to 16. FIG.

In the fifth embodiment, as shown in FIG. 14, two high-potential electrodes 3 and one low-potential electrode 4 are arranged on the rear surface 8 facing the principal surface 2 . The number and shape of the high potential electrodes 3 and the low potential electrodes 4 arranged on the main surface 2 are the same as the number and shape of the high potential electrodes 3 and the low potential electrodes 4 arranged on the back surface 8 . In the example shown in FIG. 14, two high potential electrodes 3 are arranged on the main surface 2 and two high potential electrodes 3 are arranged on the back surface 8 as well. One low potential electrode 4 is arranged on the main surface 2 and one low potential electrode 4 is arranged on the back surface 8 as well. The shape of the high potential electrode 3 arranged on the main surface 2 is rectangular, and the shape of the high potential electrode 3 arranged on the back surface 8 is also rectangular. The shape of the low potential electrode 4 arranged on the main surface 2 is rectangular, and the shape of the low potential electrode 4 arranged on the back surface 8 is also rectangular. The high-potential electrode 3 formed inside the semiconductor substrate 1, the high-potential electrode 3 arranged on the main surface 2, and the high-potential electrode 3 arranged on the back surface 8 are integrally formed. Similarly, the low potential electrode 4 formed inside the semiconductor substrate 1, the low potential electrode 4 arranged on the main surface 2, and the low potential electrode 4 arranged on the back surface 8 are integrally formed.

In the fifth embodiment, the semiconductor capacitor devices shown in FIG. 14 are stacked in the y-axis direction to form a semiconductor capacitor device module. A semiconductor capacitor device module is shown in FIG. A well-known method (metal bonding, pressure welding) is used as a method of stacking the semiconductor capacitor device.

(Effect)
According to the fifth embodiment, the same number and shape of the high potential electrodes 3 and the low potential electrodes 4 are arranged on the main surface 2 and the back surface 8, respectively. Then, such semiconductor capacitor devices are stacked to form a semiconductor capacitor device module. As a result, the capacitance value of the semiconductor capacitor device can be increased while reducing the inductance from the high-potential metal terminal 5 to the low-potential metal terminal 6 via the semiconductor capacitor.

(Sixth embodiment)
(Configuration example of a semiconductor capacitor device)
Next, a semiconductor capacitor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 17 and 18. FIG.

In the sixth embodiment, as shown in FIGS. 17 and 18, two semiconductor capacitor devices are arranged in the direction in which the high potential metal terminal 5 (high potential metal terminal 9) and the low potential metal terminal 6 extend (z-axis direction). are arranged side by side in a direction perpendicular to (x-axis direction) to form a semiconductor capacitor device module. Here, the high-potential metal terminal 9 will be explained. A high-potential metal terminal 9 is used to connect two semiconductor capacitor devices and is joined to each of the high-potential electrodes 3 of the two semiconductor capacitor devices.

(Effect)
In general, metal terminals are softer than semiconductor capacitor devices. Soldering or the like is used to join metal terminals and electrodes. When the temperature drops after soldering, a shear stress is generated in the x-axis direction due to the difference in coefficient of linear expansion between the metal terminals and the semiconductor capacitor device. Occur. According to the sixth embodiment, since a plurality of semiconductor capacitor devices are arranged side by side in the direction perpendicular to the direction in which the high potential metal terminals 5 and the low potential metal terminals 6 extend, the high potential metal terminals are arranged in the x-axis direction. A gap is formed between 5 (high potential metal terminal 9 ) and low potential metal terminal 6 . The gap formed in this manner can reduce the shear stress generated in the x-axis direction.

(Other embodiments)
While embodiments of the present invention have been described above, the discussion and drawings forming part of this disclosure should not be construed as limiting the invention. Various alternative embodiments, implementations and operational techniques will become apparent to those skilled in the art from this disclosure.

In FIG. 1, two high-potential electrodes 3 are arranged on the main surface 2 so as to sandwich one low-potential electrode 4, but the present invention is not limited to this. For example, as shown in FIGS. 19 to 20, two low potential electrodes 4 may be arranged on main surface 2 so as to sandwich one high potential electrode 3 therebetween. Even with such a configuration, the same effects as in the first embodiment can be obtained. In the present embodiment, at least one portion of the first electrode arranged on the main surface 2 may be sandwiched between at least two portions of the second electrode. The second electrode has a different polarity than the first electrode.

In FIG. 1, the number of high-potential electrodes 3 and the number of low-potential electrodes 4 arranged on the main surface 2 are two, but the present invention is not limited to this. For example, as shown in FIGS. 21 and 22, the number of high-potential electrodes 3 and the number of low-potential electrodes 4 arranged on the main surface 2 may be two. The number of high potential electrodes 3 and low potential electrodes 4 is not limited as long as the high potential electrodes 3 are arranged so as to sandwich the low potential electrodes 4 therebetween. The number of high potential electrodes 3 may be three or more. As the number of high potential electrodes 3 and low potential electrodes 4 increases, the number of high potential metal terminals 5 and low potential metal terminals 6 joined to the high potential electrodes 3 and low potential electrodes 4 also increases. Although it has been described above that the two high-potential metal terminals 5 may be connected at the ends, the metal terminals to be connected at the ends are not limited to the high-potential metal terminals 5 . When two or more low potential metal terminals 6 are joined, the two or more low potential metal terminals 6 may be joined at the ends.

Further, as shown in FIG. 6, even when the high potential metal terminals 5 and the low potential metal terminals 6 are extended along the direction orthogonal to the main surface 2, the number of the high potential electrodes 3 and the low potential electrodes 4 is is not restricted.

In FIG. 9, the number of high-potential electrodes 3 and the number of low-potential electrodes 4 arranged on the main surface 2 are two, but the present invention is not limited to this. As in the example shown in FIGS. 21 and 22, the number of high-potential electrodes 3 and the number of low-potential electrodes 4 arranged on the main surface 2 may be two. Even with such a configuration, the same effects as in the third embodiment can be obtained.

Also, in FIG. 15, two semiconductor capacitor devices are stacked, but the present invention is not limited to this. Three or more semiconductor capacitor devices may be stacked. As the number of stacked semiconductor capacitor devices increases, the capacitance value of the semiconductor capacitor devices can be increased.

In FIG. 17, the number of semiconductor capacitor devices arranged in the direction perpendicular to the direction in which the high-potential metal terminal 5 and the low-potential metal terminal 6 extend is two, but the present invention is not limited to this. The number of semiconductor capacitor devices arranged in the direction perpendicular to the direction in which the high-potential metal terminals 5 and the low-potential metal terminals 6 extend may be three or more. Even with such a configuration, the same effects as in the sixth embodiment can be obtained.

1 semiconductor substrate 2 main surface 3 high potential electrode 4 low potential electrodes 5, 9 high potential metal terminal 6 low potential metal terminal 7 dielectric layer 8 rear surface

Claims (5)

a semiconductor substrate; a dielectric layer formed inside the semiconductor substrate; first electrodes sandwiching the dielectric layer; and second electrodes having a polarity different from that of the first electrodes. A part of the electrode is arranged on the main surface of the semiconductor substrate, and at least two parts of the second electrode are arranged on the main surface so as to sandwich the first electrode arranged on the main surface. a semiconductor capacitor;
a first metal terminal joined to the first electrode arranged on the main surface;
a second metal terminal joined to each of the second electrodes arranged on the main surface;
A semiconductor capacitor device, wherein the first metal terminal and the second metal terminal extend in the same direction. 2. The semiconductor capacitor device according to claim 1, wherein a part of said two second electrodes is arranged on said main surface so as to surround said first electrode arranged on said main surface. 3. The semiconductor capacitor device according to claim 1, wherein said dielectric layer is formed in a direction perpendicular to said main surface. 4. The semiconductor capacitor device according to claim 1, wherein electrodes having the same number and shape as the first electrodes and the second electrodes are arranged on the surface facing the main surface,
A semiconductor capacitor device module, wherein two or more of the semiconductor capacitor devices are laminated. Having two or more semiconductor capacitor devices according to any one of claims 1 to 3,
A semiconductor capacitor device module, wherein the semiconductor capacitor devices are arranged side by side in a direction orthogonal to a direction in which the first metal terminal and the second metal terminal extend.

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