JP7157542B2 - プリフェッチコントローラ - Google Patents

プリフェッチコントローラ Download PDF

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Publication number
JP7157542B2
JP7157542B2 JP2018068436A JP2018068436A JP7157542B2 JP 7157542 B2 JP7157542 B2 JP 7157542B2 JP 2018068436 A JP2018068436 A JP 2018068436A JP 2018068436 A JP2018068436 A JP 2018068436A JP 7157542 B2 JP7157542 B2 JP 7157542B2
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Japan
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prefetch
amount
thread
priority
threads
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JP2018068436A
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Japanese (ja)
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JP2019179419A (ja
Inventor
雅史 九里
英樹 杉本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
NSI Texe Inc
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Denso Corp
NSI Texe Inc
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Priority to JP2018068436A priority Critical patent/JP7157542B2/ja
Priority to PCT/JP2019/009634 priority patent/WO2019188182A1/fr
Publication of JP2019179419A publication Critical patent/JP2019179419A/ja
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Publication of JP7157542B2 publication Critical patent/JP7157542B2/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2018068436A 2018-03-30 2018-03-30 プリフェッチコントローラ Active JP7157542B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2018068436A JP7157542B2 (ja) 2018-03-30 2018-03-30 プリフェッチコントローラ
PCT/JP2019/009634 WO2019188182A1 (fr) 2018-03-30 2019-03-11 Dispositif de commande de pré-extraction

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2018068436A JP7157542B2 (ja) 2018-03-30 2018-03-30 プリフェッチコントローラ

Publications (2)

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JP2019179419A JP2019179419A (ja) 2019-10-17
JP7157542B2 true JP7157542B2 (ja) 2022-10-20

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JP2018068436A Active JP7157542B2 (ja) 2018-03-30 2018-03-30 プリフェッチコントローラ

Country Status (2)

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JP (1) JP7157542B2 (fr)
WO (1) WO2019188182A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030004683A1 (en) 2001-06-29 2003-01-02 International Business Machines Corp. Instruction pre-fetching mechanism for a multithreaded program execution
JP2006343872A (ja) 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法
US9921839B1 (en) 2016-09-23 2018-03-20 Intel Corporation Coordinated thread criticality-aware memory scheduling

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6931641B1 (en) * 2000-04-04 2005-08-16 International Business Machines Corporation Controller for multiple instruction thread processors

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030004683A1 (en) 2001-06-29 2003-01-02 International Business Machines Corp. Instruction pre-fetching mechanism for a multithreaded program execution
JP2006343872A (ja) 2005-06-07 2006-12-21 Keio Gijuku マルチスレッド中央演算装置および同時マルチスレッディング制御方法
US9921839B1 (en) 2016-09-23 2018-03-20 Intel Corporation Coordinated thread criticality-aware memory scheduling

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Publication number Publication date
WO2019188182A1 (fr) 2019-10-03
JP2019179419A (ja) 2019-10-17

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