JP2019179419A - プリフェッチコントローラ - Google Patents
プリフェッチコントローラ Download PDFInfo
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- JP2019179419A JP2019179419A JP2018068436A JP2018068436A JP2019179419A JP 2019179419 A JP2019179419 A JP 2019179419A JP 2018068436 A JP2018068436 A JP 2018068436A JP 2018068436 A JP2018068436 A JP 2018068436A JP 2019179419 A JP2019179419 A JP 2019179419A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
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Abstract
Description
602:優先順位変更部
Claims (1)
- プロセッサに設けられるプリフェッチコントローラであって、
複数のスレッド毎に予め設定されている平均命令消費量と、現時点でのプリフェッチ量とを比較するプリフェッチ量比較部(601)と、
前記プリフェッチ量比較部の比較結果に基づいて、プリフェッチ量が相対的に不足しているスレッドのプリフェッチ優先順位を上昇させる優先順位変更部(602)と、を備えるプリフェッチコントローラ。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018068436A JP7157542B2 (ja) | 2018-03-30 | 2018-03-30 | プリフェッチコントローラ |
PCT/JP2019/009634 WO2019188182A1 (ja) | 2018-03-30 | 2019-03-11 | プリフェッチコントローラ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2018068436A JP7157542B2 (ja) | 2018-03-30 | 2018-03-30 | プリフェッチコントローラ |
Publications (2)
Publication Number | Publication Date |
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JP2019179419A true JP2019179419A (ja) | 2019-10-17 |
JP7157542B2 JP7157542B2 (ja) | 2022-10-20 |
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JP2018068436A Active JP7157542B2 (ja) | 2018-03-30 | 2018-03-30 | プリフェッチコントローラ |
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JP (1) | JP7157542B2 (ja) |
WO (1) | WO2019188182A1 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001350638A (ja) * | 2000-04-04 | 2001-12-21 | Internatl Business Mach Corp <Ibm> | 多重スレッド使用方法、多重スレッド処理システム、スレッド実行コントローラおよびバッファ使用方法 |
JP2006343872A (ja) * | 2005-06-07 | 2006-12-21 | Keio Gijuku | マルチスレッド中央演算装置および同時マルチスレッディング制御方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US6965982B2 (en) | 2001-06-29 | 2005-11-15 | International Business Machines Corporation | Multithreaded processor efficiency by pre-fetching instructions for a scheduled thread |
US9921839B1 (en) | 2016-09-23 | 2018-03-20 | Intel Corporation | Coordinated thread criticality-aware memory scheduling |
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2018
- 2018-03-30 JP JP2018068436A patent/JP7157542B2/ja active Active
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- 2019-03-11 WO PCT/JP2019/009634 patent/WO2019188182A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001350638A (ja) * | 2000-04-04 | 2001-12-21 | Internatl Business Mach Corp <Ibm> | 多重スレッド使用方法、多重スレッド処理システム、スレッド実行コントローラおよびバッファ使用方法 |
JP2006343872A (ja) * | 2005-06-07 | 2006-12-21 | Keio Gijuku | マルチスレッド中央演算装置および同時マルチスレッディング制御方法 |
Also Published As
Publication number | Publication date |
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WO2019188182A1 (ja) | 2019-10-03 |
JP7157542B2 (ja) | 2022-10-20 |
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