JP7151278B2 - Power semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a power semiconductor device having a heat absorbing element and a manufacturing method thereof.

A configuration is known in which a heat generating portion of a power semiconductor element and a cooling Peltier element are arranged adjacent to each other so as to absorb heat generated from the power semiconductor element.

Patent Document 1 listed below describes a semiconductor device in which intrinsic silicon carbide (i-SiC), which is an insulator and a heat conductor, is continuously formed on a heat generating portion made of silicon carbide of a semiconductor element. It is With this configuration, the thermal resistance at the contact portion between the heat generating portion of the semiconductor element and the Peltier element is reduced, and the heat flow rate (W/m ² ) of exhaust heat to the outside is improved.

Japanese Patent Application Laid-Open No. 2017-028118

However, even with the configuration disclosed in Document 1, cooling (heat absorption and heat dissipation) by the Peltier device cannot keep up with the instantaneous heat generation from the power semiconductor device mounted on the automobile, and as a result, There is a problem that the output of the semiconductor element must be limited.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional problems described above and to absorb and dissipate heat generated from a power semiconductor element without suppressing the output of the power semiconductor element.

In order to achieve the above object, the present invention is configured to increase the volume of each component constituting the Peltier element to increase its heat capacity.

Specifically, the present invention is directed to a power semiconductor device and a method of manufacturing the same, and has taken the following solutions.

That is, a first invention is a power semiconductor device comprising a power semiconductor element and a Peltier element joined to the upper surface of the power semiconductor element, the Peltier element comprising a plurality of p-type semiconductor blocks and a plurality of n-type semiconductor blocks. Each p-type semiconductor block and each n-type semiconductor block extends upward from the joint surface with the power semiconductor element, and is formed as a cubic column whose height is greater than the diameter of the bottom portion to increase the heat capacity. Intermediate portions adjacent to each other in the height direction of each p-type semiconductor block and each n-type semiconductor block are electrically connected by metal electrodes .

According to this, each semiconductor block is formed as a solid column whose height is greater than the diameter of its bottom portion, thereby forming a heat capacity body. Therefore, each semiconductor block can temporarily store heat generated from the power semiconductor element when a large load is momentarily applied to the power semiconductor element. Further, when the load is light after that, the heat stored in each semiconductor block can be exhausted .

Further , according to this, if each semiconductor block constituting the Peltier element is configured as a heat capacitor having a sufficient capacity, the heat generated by the internal resistance becomes large, so that an electrical current is generated at the intermediate portion in the height direction of each semiconductor block. By connecting, it is possible to achieve both an increase in heat capacity and suppression of heat generation due to internal resistance.

In a second invention according to the first invention, the p-type semiconductor block and the n-type semiconductor block may be made of semiconductor silicon.

According to this, the Peltier element can be formed from a semiconductor material that is inexpensive and readily available.

According to a third invention, in the first or second invention, a cooling part may be further provided in thermal contact with the p-type semiconductor block and the n-type semiconductor block.

According to this, the heat absorbed by each semiconductor block can be quickly dissipated through the cooling portion.

A fourth aspect of the invention is a method of manufacturing a power semiconductor device comprising a power semiconductor element and a Peltier element bonded to the upper surface of the power semiconductor element, wherein an insulating film is interposed on the power semiconductor element. and forming a patterned lower electrode; alternately arranging a plurality of p-type semiconductor blocks and n-type semiconductor blocks respectively on the lower electrode; each p-type semiconductor block and each n-type semiconductor block extending upward from the joint surface with the power semiconductor element and having a height greater than the diameter of the bottom portion; Prior to the step of forming a heat capacitor formed as a vertical column and arranging each p-type semiconductor block and each n-type semiconductor block, upper electrodes are formed on the side surfaces of each p-type semiconductor block and each n-type semiconductor block. The upper electrodes are electrically connected to each other at intermediate portions in the height direction of the adjacent semiconductor blocks .

According to this, in the manufacturing process of the power semiconductor element, the Peltier element can be formed by bonding to the upper surface of the power semiconductor element. In addition, since the Peltier element is formed as a cubic column in which the height of each semiconductor block is larger than the diameter of the bottom portion to form a heat capacitor, each semiconductor block momentarily causes a large load on the power semiconductor element. In this case, heat generated from the power semiconductor element can be temporarily stored. Further, when the load is light after that, the heat stored in each semiconductor block can be exhausted .

In addition, according to this, each semiconductor block constituting the Peltier element is configured as a heat capacitor having a sufficient capacity, and heat generation due to internal resistance increases. With such a connection, it is possible to achieve both an increase in heat capacity and suppression of heat generation due to internal resistance.

In a fifth aspect based on the fourth aspect, the p-type semiconductor block and the n-type semiconductor block may be made of semiconductor silicon.

According to this, the Peltier element can be formed from a semiconductor material that is inexpensive and readily available.

A sixth aspect of the invention is based on the fourth or fifth aspect, wherein the step of arranging each p-type semiconductor block and each n-type semiconductor block includes openings at positions where each p-type semiconductor block or each n-type semiconductor block is arranged. may be performed using a mask having

According to this, it is possible to efficiently arrange a minute semiconductor block at a predetermined position of the lower electrode.

According to the present invention, heat generated from a power semiconductor element can be absorbed and released without suppressing the output of the power semiconductor element.

FIG. 1 is a schematic cross-sectional view showing a power semiconductor device according to one embodiment. FIG. 2 is a graph showing the time dependency of the heat generation temperature of the power semiconductor element and the required torque of the vehicle motor according to the embodiment. FIG. 3 is a cross-sectional view showing a step of forming a power semiconductor element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 4 is a cross-sectional view showing a process of forming a lower electrode of a Peltier element on the upper surface of a power semiconductor element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 5 is a cross-sectional view showing a step of forming part of an upper electrode of a Peltier element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 6 is a cross-sectional view showing a step of forming part of the upper electrode of the Peltier element in the method of manufacturing a power semiconductor device according to one embodiment. FIG. 7 is a cross-sectional view showing a step of forming an insulating film for insulating an n-type silicon layer and a p-type silicon layer of a Peltier element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 8 is a method of manufacturing a power semiconductor device according to one embodiment, and is a cross-sectional view showing a part of the upper electrode of the Peltier element and an insulating film that insulates the n-type silicon layer and the p-type silicon layer. FIG. 9 is a front view and a plan view schematically showing a process of dicing a single-crystal silicon ingot for a Peltier element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 10 is a cross-sectional view and a plan view schematically showing a process of forming a high-concentration doping layer on the surface of silicon for a Peltier device in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 11 is a cross-sectional view and a plan view showing a step of placing a mask for arranging an n-type silicon layer of a Peltier element on a lower electrode in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 12 is a cross-sectional view and a plan view showing a method of manufacturing a power semiconductor device according to one embodiment, in which a solder material is applied onto a lower electrode through a mask and an n-type silicon layer is arranged. . FIG. 13 is a cross-sectional view and a plan view showing a step of placing a mask for arranging a p-type silicon layer on a lower electrode in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 14 is a cross-sectional view and a plan view showing a method of manufacturing a power semiconductor device according to one embodiment, in which a solder material is applied onto a lower electrode through a mask and a p-type silicon layer is arranged. . FIG. 15 shows a method of manufacturing a power semiconductor device according to one embodiment, in which an n-type silicon layer and a p-type silicon layer are arranged on a lower electrode on a power semiconductor element so that the upper electrode is in contact with the lower electrode. It is a sectional view. FIG. 16 is a cross-sectional view showing a step of sintering the power semiconductor device in the state of FIG. FIG. 17 is a plan view showing a process of arranging a plurality of power semiconductor elements in a housing in a method of manufacturing a power semiconductor device according to one embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail based on the drawings. The following description of preferred embodiments is merely exemplary in nature and is not intended to limit the invention, its applications or its uses. Also, the dimensional ratios of the constituent members in each drawing are for convenience only and do not necessarily represent the dimensional ratios of the actual constituent members.

(one embodiment)
An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic cross-sectional configuration of a power semiconductor device according to one embodiment. As shown in FIG. 1, the power semiconductor device 1 includes a power semiconductor element 10 and a Peltier element 20 mounted and fixed on the power semiconductor element 10 .

The power semiconductor element 10 may be a known power device such as SiC-DMOSFET or Si-IGBT. A SiC-DMOSFET is a double diffusion MOSFET (metal oxide semiconductor field effect transistor) made of silicon carbide (SiC), and a Si-IGBT is an insulated gate bipolar transistor made of silicon (Si). Here, the power semiconductor element 10 is fixed, for example, via a power element electrode 11 and a highly thermally conductive adhesive 12 on a base 40 made of metal that also serves as a cooling portion. Base 40 may be the bottom of the housing.

The Peltier element 20 includes an n-type silicon layer 20n and a p-type silicon layer 20p, which are structures arranged alternately in a plurality of dots (islands) on the power semiconductor element 10, and these silicon layers 20n and 20p. The silicon layers 20n and 20p are composed of a lower electrode 21 arranged thereunder and an upper electrode 22 arranged in the middle portion in the height direction of the silicon layers 20n and 20p so that currents flow alternately. Here, each silicon layer 20n, 20p is an example of a semiconductor block. Nickel (Ni), for example, can be used for the lower electrode 21 and the upper electrode 25 . Titanium (Ti), aluminum (Al), tin (Sn), molybdenum (Mo), copper (Cu), or gold (Au) can be used for these electrodes 21 and 22 in addition to nickel (Ni). can.

The Peltier element 20 is joined to the upper surface of the power semiconductor element 10 with the semiconductor element 10 . Specifically, the Peltier element 20 has its plurality of lower electrodes 21 thermally connected via an insulating layer (not shown) formed on the upper surface of the power semiconductor element 10 . That is, the Peltier element 20 and the power semiconductor element 10 are thermally connected to each other via the lower electrode 21 . Both ends of the lower electrode 21 are connected to a DC power supply 53 .

As shown in FIG. 1, the Peltier element 20 according to the present embodiment has an n-type silicon layer 20n and a p-type silicon layer 20p that are arranged upward from the junction surface with the power semiconductor element 10 positioned below. It is formed as a solid column that extends and whose height is greater than the diameter of the bottom. The upper part of these cubic columns constitutes the heat capacity part 30 of the Peltier element 20 .

Here, when silicon (Si) itself in the silicon layers 20n and 20p constituting the Peltier element 20 is used as the heat capacity section 30, the weight and volume required for the silicon will be roughly calculated.

First, it is assumed that the power semiconductor device 1 according to this embodiment has six power semiconductor elements 10 mounted thereon. Assuming that the heat loss for these six elements is 300 W and the plane area of each semiconductor element 10 is 1 cm ² , the amount of heat dissipation per second per element is 50 W/s. If the temperature difference due to the amount of heat absorbed by the Peltier element 20 is 50° C., and 50 W for one element is absorbed in one second, the specific heat of silicon is about 0.713 J/g·K. The weight of silicon required for 20 is about 1.4 g. Also, since the density of silicon is about 2.3 g/cm ³ , the volume of silicon required for one Peltier element 20 is about 0.6 cm ³ .

Here, if the plane area of one power semiconductor element 10 is 1 cm ³ , the plane area of the Peltier element 20 is also approximately 1 cm ³ , and 32 blocks each of the silicon layers 20n and 20p, and 64 blocks in total are arranged in series, do. At this time, if one side of the semiconductor block is a square of about 1.2 mm, the height is about 6.3 mm. The inventors of the present application considered physical properties such as the Seebeck coefficient of silicon, electrical resistance and thermal conductance, and the temperature difference between the front and back surfaces of the Peltier element 20. In the case of driving with a DC voltage of 12 V, 64 blocks It has been found that a tandem arrangement of is suitable.

In addition, as described above, the plurality of upper electrodes 22 in the Peltier element 20 are electrically connected at intermediate portions in the height direction of the adjacent silicon layers 20n and 20p. In this way, when the upper electrode 22 is provided not at the upper end of each silicon layer 20n, 20p but at the middle portion, each silicon layer 20n, 20p constituting the Peltier element 20 is configured as a heat capacity section 30 having a sufficient capacity. In this case, the heat generated by the internal resistance of each silicon layer 20n, 20p may increase. Therefore, if the silicon layers 20n and 20p are connected to each other by the upper electrode 22 at the middle portion, it is possible to both increase the heat capacity of the Peltier element 20 and suppress the heat generation due to the internal resistance.

Also, the plurality of power semiconductor elements 10 to which the Peltier elements 20 are respectively joined may be sealed inside the housing. As shown in FIG. 1 , the lid 50 of the housing may come into contact with the upper surface of the heat capacity section 30 . If a metal such as aluminum having a relatively high thermal conductivity is used for the lid 50 , heat from the inside of the housing and the heat capacity section 30 can be radiated to the outside through the lid 50 .

-effect-
As described above, according to the power semiconductor device 1 according to the present embodiment, the Peltier element 20, which is joined and thermally connected to the power semiconductor element 10, has the n-type silicon layer 20n and the p-type silicon layer 20n, which are the components thereof. The upper portion of 20p is thermally connected to the heat capacity portion 30 configured by extending upward. As a result, the heat capacity portion 30 can temporarily store the amount of heat having a peak momentarily exceeding the heat flux of the heat radiation from the power semiconductor element 10 . Furthermore, within several seconds after the peak of the amount of heat has passed in the case of a vehicle, the polarity of the DC power supply 53 in the Peltier element 20 is reversed, so that the heat stored in the heat capacity section 30 is transferred to the power semiconductor element 10 side. heat can be dissipated from Therefore, it is possible to sufficiently draw out the output (ability) of the power semiconductor device 10 .

FIG. 2 shows the relationship between the required specification value of motor torque and the heat generation temperature of the power semiconductor elements 10 when, for example, a power module using a plurality of power semiconductor elements 10 made of IGBTs is mounted on a vehicle. Here, the dashed line graph is the required specification value of the motor torque (right vertical axis), and the solid line graph is the temperature of the power semiconductor device 10 (left vertical axis). As shown in FIG. 2, the temperature of the power semiconductor element 10 rises from about 60.degree. C. to about 90.degree. The temperature rise rate at this time is about 40° C./s. Depending on the configuration of the inverter system, the temperature may rise to about 110°C. (see arrow T1 in Figure ₁ ). In a steady state where the temperature of the power semiconductor element 10 is about 60° C., the heat accumulated in the heat capacity portion 30 is radiated through the lid 50 on the upper surface, and the heat is absorbed from the upper electrode 22 of the Peltier element 20, Heat is radiated to the base 40, which is a cooling part, through the lower electrode 21, the power semiconductor element 10, the power element electrode 11, the adhesive 12, and the like (see arrow T2 in _FIG . 1).

(Production method)
The manufacturing method according to this embodiment will be described below with reference to the drawings.

In the manufacturing method, a DMOSFET is used as the power semiconductor element 10, and the Peltier element 20 is formed on the power semiconductor element 10 by bonding.

FIG. 3 shows an example of a cross-sectional configuration of a main part of the power semiconductor device 10 according to this embodiment. As shown in FIG. 3, the power semiconductor device 10 includes a bulk layer (contact layer) 320 made of n ⁺ -type SiC, and a drift layer 330 made of n-type SiC epitaxially grown on the bulk layer 320 to regulate the breakdown voltage. and an insulating thermally conductive layer 370 made of i-type SiC epitaxially grown on the drift layer 330 . Here, the impurity concentration of n ⁺ -type SiC may be, for example, approximately 1.0×10 ¹⁸ cm ⁻³ , and n-type SiC may be approximately 1.0×10 ¹⁶ cm ⁻³ . Also, the thickness of the drift layer 330 may be about 10 μm.

A gate electrode 390 is selectively formed on the surface of the drift layer 330 and on a region (electrode formation region) partially exposed from the heat conduction layer 370 with a gate insulating film 380a interposed therebetween. The gate electrode 390 and gate insulating film 380a are covered with an insulating film 380b. Gate electrode 390 may be polycrystalline silicon (Poly-Si), polycrystalline silicon carbide (Poly-SiC), aluminum (Al), or copper (Cu). Also, the gate insulating film 380a may be silicon oxide (SiO ₂ ), aluminum oxide (Al ₂ O ₃ ), aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), boron nitride (BN) or diamond (C ).

Furthermore, a source electrode 400 made of nickel (Ni), for example, is formed on the drift layer 330 and in the electrode formation region between the heat conduction layers 370 so as to cover the insulating film 380b.

A p-type body layer 340 is formed on the drift layer 330 between each thermally conductive layer 370 and the edge of the gate insulating film 380a facing thereto. On the upper portion of each body layer 340, an n ⁺ -type source layer 350 is formed on the side of the gate insulating film 380a, and adjacent to the source layer 350, on the side of the thermal conduction layer 370 is a p ⁺ region for improving breakdown voltage. 360 are formed respectively. Each source layer 350 makes ohmic contact with the source electrode 400 formed thereon. A drain electrode 310 made of nickel (Ni), for example, is formed on the rear surface of the bulk layer 320 . These body layer 340, source layer 350, and p ⁺ region 360 can be formed by known lithographic methods, ion implantation methods, and the like. Here, the p-type impurity concentration of the body layer 340 may be, for example, approximately 1.0×10 ¹⁶ cm ⁻³ , and the n-type impurity concentration of the source layer 350 may be, for example, 1.0×10 cm −3 . It may be about ²⁰ cm ⁻³ .

In the DMOSFET, a predetermined voltage is applied to the gate electrode 390 to form an n-type channel region 340a as an inversion layer at the boundary between the p-type body layer 340 and the gate insulating film 380a. As a result, the operating current flows through the drain electrode 310, bulk layer 320, drift layer 330, channel region 340a, source layer 350 and source electrode 400 in this order. In this current path, the channel resistance in channel region 340a and the drift resistance in drift layer 330 are large. Therefore, the Joule heat due to the channel resistance and the drift resistance accounts for a large proportion of the total amount of heat generated by the power semiconductor device 10 .

Next, as shown in FIG. 4, a lower electrode 21 is formed on the power semiconductor element 10 which is in a wafer state and has an insulating film 170 made of, for example, silicon oxide (SiO ₂ ) formed on the outermost surface thereof. Predetermined patterning is performed.

First, a copper film having a thickness of about 70 μm is formed on the lower electrode 21 by using, for example, a sputtering method using copper (Cu) as a target material.

Subsequently, a resist is applied on the formed copper film to form a first resist film 101, and a predetermined lower electrode pattern is formed on the first resist film 101 by lithography. Thereafter, using the patterned first resist film 101 as a mask, etching is performed using a ferric chloride (iron (III) chloride: FeCl ₃ ) solution or an acid solution to form a predetermined pattern shown in FIG. A lower electrode 21 is obtained.

Next, as shown in FIG. 5, the first resist film 101 is removed, and then, a chemical vapor deposition (MOCVD) method is used, for example, on the power semiconductor element 10 on which the lower electrode 21 is formed. An insulating film 23A made of silicon oxide (SiO ₂ ) or silicon nitride (SiN) is formed. The thickness of the insulating film 23A determines the position of the lower end of the upper electrode 22. As shown in FIG. Here, the film thickness of the insulating film 23A may be about 13 μm.

Subsequently, an upper electrode forming film 22A made of copper and having a thickness of about 100 μm is formed on the formed insulating film 23A using a copper sputtering method.

Subsequently, a resist is applied on the upper electrode forming film 22A to form a second resist film 102, and a predetermined upper electrode pattern is formed on the second resist film 102 by lithography.

Next, as shown in FIG. 6, using the second resist film 102 as a mask, the upper electrode forming film 22A is etched to form the first upper electrode 22a. Here, dry etching is used to etch the upper electrode forming film 22A made of copper. This dry etching may be low-pressure plasma etching using an etching gas containing chlorine (Cl ₂ ), carbon tetrachloride (CCl ₄ ), or the like.

Next, as shown in FIG. 7, a third resist film 103 is formed on the insulating film 23A in the region between the first upper electrodes 22a. The width of the third resist film 103 regulates the insulating width for insulating the lower regions of the silicon layers 20n and 20p sharing the patterned lower electrode 21 with respect to the insulating film 23A.

Subsequently, using the second resist film 102 and the third resist film 103 as masks, dry etching is performed on the insulating film 23A. When the insulating film 23A is silicon oxide, for example, a plasma etching method using carbon fluoride ₍ CF ₄ ) as an etching gas is used. Etching is performed by a plasma etching method using a mixed gas with oxygen (O ₂ ), sulfur fluoride (SF ₆ ), or the like as an etching gas. After that, the resist films 102 and 103 are removed to obtain the insulating supporting portion 23a and the lower insulating film 23b shown in FIG.

On the other hand, as shown in FIG. 9, an ingot 20A made of single crystal silicon having a diameter of about 8 cm and a thickness of about 6.2 mm is diced into a three-dimensional column having a maximum base of about 0.98 mm. A plurality of n-type silicon layers 20n are cut out. Here, the ingot 20A is made n-type with a predetermined impurity concentration in advance. Although not shown, a plurality of p-type silicon layers 20p are similarly cut out from an ingot (not shown) made of p-type single crystal silicon.

Next, as shown in FIG. 10, at least side surfaces and bottom surfaces of the silicon layers 20n and 20p are subjected to ion implantation, for example, to form high-concentration doping layers 20h for contact with the lower electrode 21 and the upper electrode 22. Form. Phosphorus (P), for example, can be used as a dopant for the n-type silicon layer 20n, and boron (B), for example, can be used as a dopant for the p-type silicon layer 20p.

Subsequently, a second upper electrode 22b made of copper is formed by sputtering in a region facing the first upper electrode 22a (see FIG. 8) on one side surface of the p-type silicon layer 20p. Further, the second upper electrode 22b of the n -type silicon layer 20n is connected to the second upper electrode 22b of the p-type silicon layer 20p so as to face the second upper electrode 22b of the p-type silicon layer 20p. 10 on the left side). A plating method (electroplating or electroless plating) can be used for the second upper electrode 22b.

Next, an n-type silicon layer 20n and a p-type silicon layer 20p are arranged at predetermined positions on the plurality of lower electrodes 21, respectively.

Here, as shown in FIGS. 11 to 14, for example, a mask having a plurality of openings 60a corresponding to the arrangement positions of the n-type silicon layer 20n or the p-type silicon layer 20p arranged on the lower electrode 21 respectively. 60 is used. The number of opening patterns in the mask 60 may be one. In this case, for example, when arranging the p-type silicon layer 20p, it may be used by shifting the arrangement position of the n-type silicon layer 20n by one row leftward or rightward in plan view. Also, a metal film may be used as a constituent material of the mask 60 . In this case, the plurality of openings 60a may be formed by etching.

First, as shown in FIG. 11, the mask 60 is held above the lower electrode 21 so that the openings 60a of the mask 60 are aligned with the arrangement positions of the n-type silicon layer 20n in the lower electrode 21. Then, as shown in FIG. Subsequently, a necessary amount of solder material 24 having fluidity (viscosity) such as cream solder is applied or dropped onto the lower electrode 21 through each opening 60 a of the mask 60 .

Next, as shown in FIG. 12, the n-type silicon layer 20n is applied to the solder material 24 on the lower electrode 21 through each opening 60a of the mask 60 held so as to match the arrangement position of the n-type silicon layer 20n. be placed on top of the

Next, as shown in FIG. 13, the mask 60 is held above the insulating substrate 23 so that each opening 60a of the mask 60 is aligned with each arrangement position of the p-type silicon layer 20p in the lower electrode 21. Next, as shown in FIG. Here, the holding position of the mask 60 is shifted leftward by one column compared to the case of the n-type silicon layer 20n. Subsequently, the solder material 24 is applied or dropped onto the lower electrode 21 through each opening 60 a of the mask 60 .

Next, as shown in FIG. 14, the p-type silicon layer 20p is applied to the solder material 24 on the lower electrode 21 through each opening 60a of the mask 60 held so as to match the arrangement position of the p-type silicon layer 20p. be placed on top of the

Thereafter, the mask 60 is removed, and the solder material 24 is cured by heating to a predetermined temperature while pressing the silicon layers 20n and 20p from above. Thereby, each silicon layer 20n, 20p is fixed to the lower electrode 21. Next, as shown in FIG. Thereby, a plurality of semiconductor blocks of the Peltier element 20 in the state shown in FIG. 15 are obtained.

As shown in FIGS. 14 and 15, the second silicon layers 20n and 20p adjacent to each other in the row direction (the x direction in the drawings) are provided on side surfaces opposite to the lower insulating films 23b and face each other. A configuration is adopted in which the upper electrodes 22b are electrically connected to each other with the first upper electrode 22a interposed therebetween. Therefore, in each placement step using the mask 60 for the n-type silicon layer 20n shown in FIG. 12 and the p-type silicon layer 20p shown in FIG. There is

In FIG. 14, for example, in the n-type silicon layer 20n located on the right end of the first row from the bottom and the p-type silicon layer 20p located on the right end of the second row from the bottom, the column direction (y A first upper electrode 22a and a second upper electrode 22b are provided on the side faces facing each other in the direction ) so that they can be connected in series. The same applies to the n-type silicon layer 20n located at the left end of the second row from the bottom and the p-type silicon layer 20p located at the left end of the third row from the bottom, and all eight rows are connected in series.

Next, as shown in FIG. 16, the silicon layers 20n and 20p, the lower electrode 21, the first upper electrode 22a and the second upper electrode 22b are sintered at a temperature of about 220° C. for about 180 seconds. conduct. As a result, the upper electrode 22 in which the first upper electrode 22a and the second upper electrode 22b are joined is obtained.

Next, as shown in FIG. 17, the power semiconductor device 1 according to the present embodiment is, as an example, a module on which two sets of 3-armed inverter devices are mounted. That is, an inverter device including six power semiconductor elements 10 each having a Peltier element 20 joined thereto is arranged in a housing 51 having external terminals 52 . In addition, in FIG. 17, illustration of wiring is omitted.

- Effect (manufacturing method) -
As described above, according to the method of manufacturing the power semiconductor device 1 according to the present embodiment, in the manufacturing process of the power semiconductor element 10, the silicon layers 20n and 20p forming the heat capacitor 30 are formed on the upper surface of the power semiconductor element 10. The Peltier element 20 having such a structure can be formed by bonding. In addition, since the Peltier element 20 is formed as a solid column in which the height of each of the silicon layers 20n and 20p is greater than the diameter of the bottom portion to constitute the heat capacitor 30, each of the silicon layers 20n and 20p is formed in the power semiconductor element 10. On the other hand, heat generated from the power semiconductor element 10 can be temporarily stored when a large load occurs momentarily. Further, when the load is light after that, the heat stored in each semiconductor block can be exhausted.

INDUSTRIAL APPLICABILITY The present invention can absorb and dissipate heat generated from a power semiconductor element without suppressing the output of the power semiconductor element, and is particularly useful as a power semiconductor device for vehicles.

1 power semiconductor device 10 power semiconductor element 11 power element electrode 13 Peltier element connection source electrode 20 Peltier element 20h high-concentration doping layer 20n n-type silicon layer (cubic column/semiconductor block)
20p p-type silicon layer (cylinder/semiconductor block)
21 Lower electrode 22 Upper electrode 22a First upper electrode 22b Second upper electrode 23A Insulating film 23a Insulating support 23b Insulating wall 24 Solder material 30 Heat capacity (heat capacity)
40 base (cooling part)
50 Lid 51 Housing 60 Mask 60a Opening

Claims (6)

A power semiconductor device comprising a power semiconductor element and a Peltier element bonded to the upper surface of the power semiconductor element,
The Peltier element is composed of a plurality of p-type semiconductor blocks and a plurality of n-type semiconductor blocks,
Each of the p-type semiconductor blocks and each of the n-type semiconductor blocks extends upward from the joint surface with the power semiconductor element and is formed as a cubic column whose height is greater than the diameter of its bottom portion to form a heat capacitor. ,
A power semiconductor device , wherein middle portions of the p-type semiconductor blocks and the n-type semiconductor blocks adjacent to each other in the height direction are electrically connected by metal electrodes . In the power semiconductor device according to claim 1 ,
The power semiconductor device, wherein the p-type semiconductor block and the n-type semiconductor block are made of semiconductor silicon. In the power semiconductor device according to claim 1 or 2 ,
A power semiconductor device further comprising a cooling part in thermal contact with the p-type semiconductor block and the n-type semiconductor block. A method for manufacturing a power semiconductor device comprising a power semiconductor element and a Peltier element bonded to the upper surface of the power semiconductor element,
forming a patterned lower electrode with an insulating film interposed on the power semiconductor element;
alternating a plurality of p-type semiconductor blocks and n-type semiconductor blocks on the lower electrode;
connecting the alternately arranged p-type semiconductor blocks and n-type semiconductor blocks with upper electrodes;
Each of the p-type semiconductor blocks and each of the n-type semiconductor blocks extends upward from the joint surface with the power semiconductor element and is formed as a cubic column whose height is greater than the diameter of its bottom portion to form a heat capacitor. ,
forming the upper electrodes on side surfaces of the p-type semiconductor blocks and the n-type semiconductor blocks before the step of arranging the p-type semiconductor blocks and the n-type semiconductor blocks;
The method of manufacturing a power semiconductor device, wherein the upper electrodes are electrically connected to each other at intermediate portions in the height direction of adjacent semiconductor blocks . In the method for manufacturing a power semiconductor device according to claim 4 ,
A method of manufacturing a power semiconductor device, wherein the p-type semiconductor block and the n-type semiconductor block are made of semiconductor silicon. In the method for manufacturing a power semiconductor device according to claim 4 or 5 ,
The step of arranging each p-type semiconductor block and each n-type semiconductor block includes:
A method of manufacturing a power semiconductor device using a mask having openings at positions where the p-type semiconductor blocks or the n-type semiconductor blocks are arranged.

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