JP7119776B2 - Power semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a power semiconductor device having a heat absorbing element and a manufacturing method thereof.

A configuration is known in which a heat generating portion of a power semiconductor element and a cooling Peltier element are arranged adjacent to each other so as to absorb heat generated from the power semiconductor element.

Patent Document 1 listed below describes a semiconductor device in which intrinsic silicon carbide (i-SiC), which is an insulator and a heat conductor, is continuously formed on a heat generating portion made of silicon carbide of a semiconductor element. It is With this configuration, the thermal resistance at the contact portion between the heat generating portion of the semiconductor element and the Peltier element is reduced, and the heat flow rate (W/m ² ) of exhaust heat to the outside is improved.

Japanese Unexamined Patent Application Publication No. 2017-028118 JP 2012-028520 A

However, even with the configuration disclosed in Document 1, cooling (heat absorption and heat dissipation) by the Peltier device cannot keep up with the instantaneous heat generation from the power semiconductor device mounted on the automobile, and as a result, There is a problem that the output of the semiconductor element must be limited.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the conventional problems described above and to absorb and dissipate heat generated from a power semiconductor element without suppressing the output of the power semiconductor element.

In order to achieve the above object, the present invention is configured to increase the surface area of the side surface of each component constituting the Peltier element and to bring the enlarged side surface into contact with the capacitor.

Specifically, the present invention is directed to a power semiconductor device and a method of manufacturing the same, and has taken the following solutions.

That is, a first invention is a power semiconductor device comprising a power semiconductor element and a Peltier element joined to the power semiconductor element, wherein the Peltier element is formed by electrically connecting a plurality of components, The structure has a surface area enlarged portion that has an enlarged surface area, and includes a heat capacity body that is in thermal contact with at least the surface area enlarged part of the Peltier element, and the heat capacity body is a solid-liquid phase change material.

According to this, the Peltier element has a surface area enlarged portion whose structure has an enlarged surface area, and is provided with a heat capacitor thermally contacting at least the surface area enlarged portion of the Peltier element. As a result, the heat capacity body temporarily stores the amount of heat having a peak momentarily exceeding the heat flux of heat dissipation from the enlarged surface area of the Peltier element, and after the peak of this heat amount passes, the heat stored in the heat capacity body can be radiated from the semiconductor element side. Therefore, it is possible to sufficiently draw out the output of the power semiconductor element.

In addition, although the above-mentioned Patent Document 2 discloses a semiconductor cooling device using a latent heat storage material (capacitor) as a heat absorption part, in this case, heat conduction from a high temperature region to a low temperature region (heat This is different from the configuration using the Peltier element 20 as in the present embodiment, that is, the configuration in which external energy (electrical energy) is actively supplied for heat transfer.

Also, a latent heat storage agent made of a solid-liquid phase change material can be used as the heat capacity body.

In a second invention based on the first invention, the enlarged surface area portion of the Peltier element structure has a triangular roof shape, a plane wave shape, or a porous shape, the ridgeline of which extends parallel to the upper surface of the power semiconductor device. good too.

According to this, the surface area of the structure of the Peltier element can be reliably increased.

According to a third invention, in the first or second invention, the Peltier device may be made of semiconductor silicon.

According to this, the Peltier element can be formed from a semiconductor material that is inexpensive and readily available.

In a fourth aspect based on the first aspect, the solid-liquid phase-change substance may be an organic alcohol or a sugar alcohol.

According to a fifth invention, in any one of the first to fourth inventions, a cooling portion that is in thermal contact with the heat capacity body may be further provided.

According to this, the heat absorbed by the heat capacity body can be rapidly radiated through the cooling portion.

A sixth aspect of the invention is a method of manufacturing a power semiconductor device comprising a power semiconductor element and a Peltier element joined to the power semiconductor element, comprising: a step of arranging the constituents with a lower electrode interposed therebetween; a step of connecting constituents adjacent to each other among the plurality of constituents with the upper electrode; and insulating the plurality of electrically connected constituents. and a step of covering the Peltier element joined to the power semiconductor element with a heat capacitor that is in thermal contact with the Peltier element. and the heat capacity body is a solid-liquid phase change material.

According to this, the plurality of constituent bodies constituting the Peltier element have enlarged surface area portions that have enlarged surface areas, and the heat capacity body is provided in thermal contact with the enlarged surface area portions of the plurality of constituent members. A Peltier element is realized. Since this Peltier element can be joined to a normal (existing) power semiconductor element, it is not limited to the type of power semiconductor element, for example, the application or the semiconductor material, and therefore the range of application can be expanded.

Also, a latent heat storage agent made of a solid-liquid phase change material can be used as the heat capacity body.

In a seventh aspect based on the sixth aspect, the enlarged surface area portion of the structure of the Peltier element has a triangular roof shape, a plane wave shape, or a porous shape, the ridgeline of which extends parallel to the upper surface of the power semiconductor device. good too.

According to this, the surface area of the structure of the Peltier element can be reliably increased.

According to an eighth invention, in the sixth or seventh invention, the Peltier element may be made of semiconductor silicon.

According to this, the Peltier element can be formed from a semiconductor material that is inexpensive and readily available.

In a ninth aspect based on the sixth to eighth aspects, the step of arranging the plurality of constituents may be performed using a mask having openings at the arrangement positions of the respective constituents.

According to this, it is possible to efficiently arrange a minute structure at a predetermined position on the insulating substrate.

According to the present invention, heat generated from a power semiconductor element can be absorbed and released without suppressing the output of the power semiconductor element.

FIG. 1 is a schematic cross-sectional view showing a power semiconductor device according to one embodiment. FIG. 2 is a schematic perspective view showing a power semiconductor element and a Peltier element according to one embodiment. FIG. 3 is a graph showing the time dependency of the heat generation temperature of the power semiconductor element and the required torque of the vehicle motor according to the embodiment. FIG. 4 is a cross-sectional view and a plan view showing a process of forming an electrode of a Peltier device on the upper surface of a power semiconductor element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 5 is a front view and a plan view schematically showing a process of dicing a single-crystal silicon ingot for a Peltier device in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 6 is a front view and a plan view schematically showing a process of increasing the surface area of the silicon for the Peltier element in the method of manufacturing a power semiconductor device according to one embodiment. FIG. 7 is a front view and a plan view showing a step of forming a high-concentration doping layer on the surface of silicon for a Peltier device in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 8 is a cross-sectional view and a plan view showing a step of forming a highly thermally conductive insulating substrate of a Peltier element in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 9 is a cross-sectional view and a plan view showing a step of forming a lower electrode on a highly thermally conductive insulating substrate in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 10 is a cross-sectional view and a plan view showing a step of setting a mask for arranging an n-type silicon layer of a Peltier element on a highly thermally conductive insulating substrate in a method of manufacturing a power semiconductor device according to one embodiment. . FIG. 11 shows a method of manufacturing a power semiconductor device according to one embodiment, showing a step of applying a solder material through a mask onto a lower electrode on a highly thermally conductive insulating substrate and arranging an n-type silicon layer. It is a sectional view and a plan view. FIG. 12 is a cross-sectional view and a plan view showing a step of setting a mask for arranging a p-type silicon layer on a highly thermally conductive insulating substrate in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 13 shows a method of manufacturing a power semiconductor device according to one embodiment, in which a solder material is applied through a mask onto a lower electrode on a high thermal conductive insulating substrate to arrange a p-type silicon layer. It is a sectional view and a plan view. FIG. 14 shows a method of manufacturing a power semiconductor device according to one embodiment, in which an n-type silicon layer and a p-type silicon layer of a Peltier element are arranged on a high thermal conductivity insulating substrate, an upper electrode is formed, and then the power semiconductor device is manufactured. It is sectional drawing and a top view which show the process of joining with. FIG. 15 is a front view showing a process of arranging a plurality of power semiconductor elements in a housing in a method of manufacturing a power semiconductor device according to one embodiment. FIG. 16 is a front view of a method of manufacturing a power semiconductor device according to an embodiment, showing a step of filling a housing in which a power semiconductor element is mounted with a heat capacitor.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail based on the drawings. The following description of preferred embodiments is merely exemplary in nature and is not intended to limit the invention, its applications or its uses. Also, the dimensional ratios of the constituent members in each drawing are for convenience only and do not necessarily represent the dimensional ratios of the actual constituent members.

(one embodiment)
An embodiment of the present invention will be described with reference to the drawings.

1 and 2 schematically show a power semiconductor device according to an embodiment, FIG. 1 shows its cross-sectional configuration, and FIG. 2 schematically shows a power semiconductor element 10 and a Peltier element 20. FIG.

As shown in FIG. 1, the power semiconductor device 1 includes a power semiconductor element 10, a Peltier element 20 placed and fixed on the power semiconductor element 10, and a power semiconductor element 10 and the Peltier element 20 in contact with each other. and a heat capacity body 30 covering it.

The power semiconductor element 10 may be a known power device such as SiC-DMOSFET or Si-IGBT. A SiC-DMOSFET is a double diffused MOSFET (metal oxide semiconductor field effect transistor) made of silicon carbide (SiC), and a Si-IGBT is an insulated gate bipolar transistor made of silicon (Si). Here, the power semiconductor element 10 is fixed, for example, via a power element electrode 11 and a highly thermally conductive adhesive 12 on a base 40 made of metal that also serves as a cooling portion. Base 40 may be the bottom of the housing.

As shown in FIG. 2, the Peltier element 20 includes an n-type silicon layer 20n and a p-type silicon layer 20p, which are structures alternately arranged in a plurality of dots (islands) on the power semiconductor element 10. , the silicon layers 20n and 20p are composed of a lower electrode 21 arranged therebelow and an upper electrode 22 arranged above the silicon layers 20n and 20p so that a current flows alternately. Nickel (Ni), for example, can be used for the lower electrode 21 and the upper electrode 22 . Titanium (Ti), aluminum (Al), tin (Sn), molybdenum (Mo), copper (Cu), or gold (Au) can be used for these electrodes 21 and 22 in addition to nickel (Ni). can.

Here, at least a part of the silicon layers 20n and 20p in the Peltier element 20 is located on the side opposite to the bonding surface with the power semiconductor element 10, that is, on each side surface of the silicon layers 20n and 20p. It is formed in, for example, a triangular roof shape extending parallel to the upper surface of the . By forming the silicon layers 20n and 20p in the shape of a triangular roof in this manner, the surface areas of the side surfaces of the silicon layers 20n and 20p are increased. Hereinafter, the side surface with the enlarged surface area will be referred to as an enlarged surface area portion 20a. Note that the surface area expanding portion 20a is not limited to the triangular roof shape, and may have a corrugated shape in a plan view, or may have a porous shape in which at least each side surface is porous.

The Peltier element 20 is joined to the upper surface of the power semiconductor element 10 with the semiconductor element 10 . Specifically, the Peltier element 20 is for Peltier element connection made of a metal in which the plurality of lower electrodes 21 are electrically connected to two source electrodes (not shown) formed on the upper surface of the power semiconductor element 10. The source electrode 13 and the high thermal conductivity insulating substrate 23 formed on the connecting source electrode 13 are interposed to be thermally connected. That is, the Peltier element 20 and the power semiconductor element 10 are thermally connected to each other via the Peltier element connecting source electrode 13 , the highly thermal conductive insulating substrate 23 and the lower electrode 21 . Both ends of the lower electrode 21 are connected to a DC power supply 53 .

The Peltier device connection source electrode 13 is provided with a plurality of source lead-out lines 15 at the side end portion (see FIG. 4) on the side where the two source electrodes face each other. A gate electrode connecting portion 14 is formed in a region between the two source electrodes on the upper surface of the power semiconductor element 10 and at one end of this region. A gate lead-out line 16 is provided in the gate electrode connecting portion 14 .

Furthermore, as shown in FIG. 1, the Peltier device 20 and the power semiconductor device 10 are covered with a heat capacitor 30 so as to be in contact with each other. Specifically, the side surface of the power semiconductor element 10, the side surfaces of the n-type silicon layer 20n and the p-type silicon layer 20p, and the exposed portions of the high thermal conductive insulating substrate 23 and the lower electrode 21 are in contact with the heat capacitor 30. covered with

A latent heat storage material, which is a solid-liquid phase change material, can be effectively used for the heat capacity body 30, for example. Sugar alcohol, for example, can be used for this latent heat storage material. Examples of useful sugar alcohols include _{erythritol ( C4H10O4} ) or _{mannitol ( C6H14O6} ). Erythritol has a melting point of about 120°C and mannitol has a melting point of about 167°C. That is, these sugar alcohols are solid at room temperature, and therefore, in order to contact and cover the Peltier element 20 and the like with the heat capacity body 30, they are once heated and melted to form a liquid phase.

Although the power semiconductor device 1 shown in FIGS. 1 and 2 shows only one power semiconductor element 10 , it usually has a plurality of power semiconductor elements 10 .

Also, the plurality of power semiconductor elements 10 to which the Peltier elements 20 are respectively joined may be sealed inside the housing. As shown in FIG. 1 , the lid 50 of the housing may contact the upper surface of the heat capacitor 30 . If a metal such as aluminum having a relatively high thermal conductivity is used for the lid 50 , the heat inside the housing and from the heat capacitor 30 can be radiated to the outside through the lid 50 . When the heat capacity body 30 is sealed in the housing, it is necessary to take into consideration that the sugar alcohol described above expands in volume in the solid phase as compared to the liquid phase.

-effect-
As described above, according to the power semiconductor device 1 according to the present embodiment, the Peltier element 20, which is joined and thermally connected to the power semiconductor element 10, is composed of the n-type silicon layer 20n and the p-type silicon layer. Each side of 20p has an enlarged surface area enlargement 20a. Furthermore, these surface area enlarged portions 20 a are in thermal contact with each other through the heat capacity body 30 . As a result, the heat capacity body 30 can temporarily store the amount of heat having a peak instantaneously exceeding the heat flux of the heat radiation from the enlarged surface area portion 20a of the silicon layers 20n and 20p of the Peltier element 20. FIG. Furthermore, within several seconds after the peak of the amount of heat has passed in the case of a vehicle, the polarity of the DC power supply 53 in the Peltier element 20 is reversed, so that the heat stored in the heat capacity body 30 is transferred to the power semiconductor element 10 side. heat can be dissipated from Therefore, it is possible to sufficiently draw out the output (ability) of the power semiconductor device 10 .

FIG. 3 shows the relationship between the required specification value of motor torque and the heat generation temperature of the power semiconductor elements 10 when a power module using a plurality of power semiconductor elements 10 made of IGBTs is mounted on a vehicle, for example. Here, the dashed line graph is the required specification value of the motor torque (right vertical axis), and the solid line graph is the temperature of the power semiconductor device 10 (left vertical axis). As shown in FIG. 3, the temperature of the power semiconductor element 10 rises from about 60.degree. C. to about 90.degree. The temperature rise rate at this time is about 40° C./s. Depending on the configuration of the inverter system, the temperature may rise to about 110°C. (see arrow T1 in Figure ₁ ). In a steady state where the temperature of the power semiconductor element 10 is about 60° C., the heat accumulated in the heat capacitor 30 is radiated through the lid 50 on the upper surface, and the heat is absorbed from the upper electrode 22 of the Peltier element 20, Heat is dissipated through the lower electrode 21, the highly thermally conductive insulating substrate 23, the source electrode 13 for connecting the Peltier element, the power semiconductor element 10, the power element electrode 11, the adhesive 12, and the like to the base 40, which is the cooling part (see FIG. 1). See arrow _T2 ).

(Production method)
The manufacturing method according to this embodiment will be described below with reference to the drawings.

In the first manufacturing method, an existing IGBT, DMOSFET, or the like is used as the power semiconductor element 10, and the Peltier element 20 is formed on the power semiconductor element 10 by bonding.

First, as shown in FIG. 4, on two source electrodes 17 of the existing power semiconductor element 10 used in the power semiconductor device 1, a plate-shaped Peltier element connection source electrode covering the source electrodes 17 in contact with the source electrodes 17 is formed. 13 is fixed with a conductive adhesive. Here, the planar dimension of the power semiconductor element 10 is, for example, approximately 10 mm. Also, the gate electrode connecting portion 14 provided on the upper surface of the power semiconductor element 10 is exposed. A metal plate made of copper (Cu), aluminum (Al), or the like and having a thickness of 1 mm, for example, can be used as the Peltier element connecting source electrode 13 .

On the other hand, as shown in FIG. 5, a wafer 20A made of single crystal silicon having a diameter of about 8 cm and a thickness of about 0.2 cm is formed into a three-dimensional column having a maximum base of about 0.9×0.8 mm ² . A plurality of n-type silicon layers 20An are cut out by dicing. Here, the ingot 20A is made n-type with a predetermined impurity concentration in advance. Although not shown, a plurality of p-type silicon layers 20Ap are similarly cut out from an ingot (not shown) made of p-type single crystal silicon.

Next, as shown in FIG. 6, for each of the formed n-type silicon layers 20An, for example, by using a laser beam, the opposing side surfaces of the cubic column are processed into a triangular roof shape, and the n-type silicon layers 20An are formed. An n-type silicon layer 20n is formed from 20An. Similarly, a p-type silicon layer 20p is formed from each p-type silicon layer 20Ap. The laser light to be used may be a YAG (Yttrium Aluminum Garnet) laser, an ultraviolet (UV) laser, a semiconductor laser, or the like, as long as it can easily process single crystal silicon.

If the plane orientation of the surface (bottom surface) of the ingot 20A made of single crystal silicon is, for example, the {100} plane, and the plane orientation of the opposing side surface of the cubic column is the {001} plane, then the slope of the triangular roof is formed. Since the plane orientation is {101}, processing can be performed more easily and reliably.

Next, as shown in FIG. 7, the surface regions of the silicon layers 20n and 20p are ion-implanted, for example, to form a high-concentration doping layer 20h for contact with the lower electrode 21 and the upper electrode 22. . Phosphorus (P), for example, can be used as a dopant for the n-type silicon layer 20n, and boron (B), for example, can be used as a dopant for the p-type silicon layer 20p.

Next, as shown in FIG. 8, a highly thermally conductive insulating substrate 23 is produced. First, a silicon nitride (Si ₃ N ₄ ) substrate having a planar dimension of approximately 10 mm, a substantially square shape, and a thickness of approximately 0.22 mm is prepared. A pattern 23a for forming a lower electrode circuit is formed on the prepared silicon nitride substrate. One portion of the pattern 23a has a planar dimension that allows the bottom surfaces of a pair of silicon layers 20n and 20p adjacent in the x direction in the figure to be arranged. Here, 50 pairs of patterns 23a are formed. Accordingly, 100 silicon layers 20n and 20p are arranged in a total of 10 rows and 10 columns on the silicon nitride substrate. Note that the x-direction is the direction in which the source lead-out line 15 shown in FIG. 2 is led out. Also, the y-direction is a direction perpendicular to the x-direction.

An insulating wall 23b made of silicon nitride is formed at the boundary between the patterns 23a adjacent to each other in both the x-direction and the y-direction. This prevents the adjacent silicon layers 20n and 20p from electrically contacting the bottoms of the adjacent patterns 23a.

As an example of a method of forming the lower electrode circuit forming pattern 23a, a mask film for masking the formation region of the insulating wall 23b is formed by a resist or an inorganic material by lithography. Subsequently, the masked silicon nitride substrate is subjected to a plasma etching method using, for example, a mixed gas of carbon fluoride (CF ₄ ) and oxygen (O ₂ ) or sulfur fluoride (SF ₆ ) as an etching gas. Then, dry etching is performed to obtain the highly thermally conductive insulating substrate 23 shown in FIG.

Next, as shown in FIG. 9, a plurality of lower electrodes 21 forming a lower electrode circuit formation pattern are formed on the highly thermally conductive insulating substrate 23 . Copper (Cu) having a thickness of about 70 μm, for example, can be used for the lower electrode 21 . As a method for forming the lower electrode 21, a sputtering method using copper as a target material can be used. By using this sputtering method, the lower electrode 21 can be reliably formed on each of the lower electrode circuit forming patterns 23 a on the highly thermally conductive insulating substrate 23 . A plating method (electroplating or electroless plating) can be used for the lower electrode 21 made of copper.

Next, an n-type silicon layer 20n and a p-type silicon layer 20p are placed at predetermined positions on the plurality of lower electrodes 21 on the highly thermally conductive insulating substrate 23, respectively.

Here, as shown in FIGS. 10 to 13, for example, each arrangement position of the n-type silicon layer 20n or the p-type silicon 20p respectively arranged on the lower electrode 21 formed on the high thermal conductivity insulating substrate 23 A mask 60 having a plurality of openings 60a corresponding to . The number of opening patterns in the mask 60 may be one. In this case, for example, when arranging the p-type silicon layer 20p, it may be used by shifting the arrangement position of the n-type silicon layer 20n by one row leftward or rightward in plan view. Also, a metal film may be used as a constituent material of the mask 60 . In this case, the plurality of openings 60a may be formed by etching.

First, as shown in FIG. 10, a mask 60 is placed on the insulating substrate 23 so that each opening 60a of the mask 60 matches each arrangement position of the n-type silicon layer 20n in the lower electrode 21 on the insulating substrate 23 with high thermal conductivity. hold above. Subsequently, a necessary amount of solder material 24 having fluidity (viscosity) such as cream solder is applied or dropped onto the lower electrode 21 through each opening 60 a of the mask 60 .

Next, as shown in FIG. 11, the n-type silicon layer 20n is applied to the solder material 24 on the lower electrode 21 through each opening 60a of the mask 60 held so as to match the arrangement position of the n-type silicon layer 20n. be placed on top of the

Next, as shown in FIG. 12, a mask 60 is placed on the insulating substrate 23 so that each opening 60a of the mask 60 coincides with each arrangement position of the p-type silicon layer 20p in the lower electrode 21 on the insulating substrate 23. Next, as shown in FIG. hold above. Here, the holding position of the mask 60 is shifted leftward by one column compared to the case of the n-type silicon layer 20n. Subsequently, the solder material 24 is applied or dropped onto the lower electrode 21 through each opening 60 a of the mask 60 .

Next, as shown in FIG. 13, the p-type silicon layer 20p is attached to the solder material 24 on the lower electrode 21 through each opening 60a of the mask 60 held so as to match the arrangement position of the p-type silicon layer 20p. be placed on top of the

Thereafter, the mask 60 is removed, and the solder material 24 is cured by heating to a predetermined temperature while pressing the silicon layers 20n and 20p from above. Thereby, each silicon layer 20n, 20p is fixed to the lower electrode 21. Next, as shown in FIG.

Note that the shape of the bottom surface of each of the silicon layers 20n and 20p is rectangular, not square, as described with reference to FIG. As a result, when arranging the n-type silicon layer 20n and the p-type silicon layer 20p shown in FIGS. 11 and 13 through the mask 60, for example, it becomes easy to align the directions of the triangular roof-shaped ridgelines.

Further, in the present embodiment, the n-type silicon layer 20n is arranged before the p-type silicon layer 20p, but the present invention is not limited to this. good too.

Subsequently, as shown in FIG. 14, an upper electrode 22 is formed on each of the plurality of pairs of silicon layers 20n, 20p fixed on the lower electrode 21 on the high thermal conductive insulating substrate 23. Then, as shown in FIG. Specifically, in FIG. 14, the p-type silicon layer 20p located on the left end of the first row from the bottom to the n-type silicon layer 20n located on the right end are connected in series. At this time, the n-type silicon layer 20n located on the right end of the first row from the bottom and the p-type silicon layer 20p located on the right end of the second row from the bottom are connected. Further, the p-type silicon layer 20p located on the right end of the second row from the bottom to the n-type silicon layer 20n located on the left end are connected in series. This series connection is performed for all 10 rows. Note that one lower electrode circuit forming pattern 23a and another lower electrode circuit forming pattern 23a adjacent thereto in the x-direction electrically connect the side surfaces (inclined surfaces) of the adjacent silicon layers 20n and 20p. The upper electrode 22 is formed so as to

As for the method of forming the upper electrode 22, first, a mask film is formed by lithography to mask a region other than the region where the upper electrode 22 is to be formed. Subsequently, for example, a copper film is formed on the entire surface of the highly thermally conductive insulating substrate 23 by a sputtering method using copper as a target material. After that, each upper electrode 22 is formed by a so-called lift-off method of removing the mask film, and the Peltier element 20 is obtained. In this embodiment, a pair of p-type silicon layers 20p and another pair of n-type silicon layers 20n adjacent thereto in the x direction are insulated by insulating walls 23b, and have a certain height. The insulating wall 23b can prevent the upper electrode 22 from being short-circuited with the lower electrode 21. As shown in FIG.

Subsequently, as shown in FIG. 14, the Peltier element 20 and the Peltier element connecting source electrode 13 on the power semiconductor element 10 are joined by an adhesive or the like.

Next, as shown in FIG. 15, the power semiconductor device 1 according to the present embodiment is, as an example, a module on which two sets of three-armed inverter devices are mounted. That is, an inverter device including six power semiconductor elements 10 each having a Peltier element 20 joined thereto is arranged in a housing 51 having external terminals 52 . In addition, in FIG. 15, illustration of wiring is omitted.

Next, as shown in FIG. 16 , a latent heat storage material made of sugar alcohol such as erythritol is enclosed as the heat capacity body 30 inside the housing 51 .

After that, the housing 51 is sealed with the lid 50 shown in FIG. In this case, when erythritol is used for the heat capacity body 30, since the solid phase has a lower density than the liquid phase, its volume shrinks after melting. On the other hand, when mannitol is used, since the density of the liquid phase is lower than that of the solid phase, the volume expands after melting.

- Effect (manufacturing method) -
As described above, according to the method for manufacturing the power semiconductor device 1 according to this embodiment, an existing power semiconductor element such as an IGBT or DMOSFET can be used as the power semiconductor element 10 . Therefore, the Peltier element 20 of the present embodiment can be manufactured in combination with a power semiconductor element having desired performance. can be expanded.

In addition, as described above, the Peltier element 20 of the present embodiment has the enlarged surface area portions 20a in which the side surfaces of the n-type silicon layer 20n and the p-type silicon layer 20p, which are the components of the Peltier element 20, are enlarged. there is Furthermore, these surface area enlarged portions 20 a are in thermal contact with each other through the heat capacity body 30 . With this configuration, the heat capacity body 30 can temporarily store the amount of heat having a peak instantaneously exceeding the heat flux of the heat radiation from the enlarged surface area portion 20a of the silicon layers 20n and 20p of the Peltier element 20. Therefore, it is possible to sufficiently extract the output from the power semiconductor device 10 .

INDUSTRIAL APPLICABILITY The present invention can absorb and dissipate heat generated from a power semiconductor element without suppressing the output of the power semiconductor element, and is particularly useful as a power semiconductor device for vehicles.

1 power semiconductor device 10 power semiconductor element 11 power element electrode 13 Peltier element connecting source electrode 20 Peltier element 20a surface area enlarged portion 20h high-concentration doping layer 20n n-type silicon layer (structure)
20p p-type silicon layer (structure)
21 lower electrode 22 upper electrode 23 high thermal conductivity insulating substrate (insulating substrate)
23a Lower electrode circuit forming pattern 23b Insulating wall 24 Solder material 30 Thermal capacitor 40 Base (cooling part)
50 Lid 51 Housing 60 Mask 60a Opening

Claims (9)

A power semiconductor device comprising a power semiconductor element and a Peltier element joined to the power semiconductor element,
The Peltier element is formed by electrically connecting a plurality of structures,
The structure has a surface area enlarged portion with an enlarged surface area,
a heat capacitor in thermal contact with at least the surface area enlarged portion of the Peltier element ;
The power semiconductor device , wherein the heat capacity body is a solid-liquid phase change material . In the power semiconductor device according to claim 1,
The power semiconductor device, wherein the surface area enlarged portion of the structure of the Peltier element has a triangular roof shape, a plane wave shape, or a porous shape with a ridge line extending parallel to the upper surface of the power semiconductor element. In the power semiconductor device according to claim 1 or 2,
The power semiconductor device, wherein the Peltier element is made of semiconductor silicon. In the power semiconductor device according to claim 1 ,
The power semiconductor device, wherein the solid-liquid phase change substance is organic alcohol or sugar alcohol. In the power semiconductor device according to any one of claims 1 to 4 ,
A power semiconductor device further comprising a cooling portion in thermal contact with the heat capacitor. A method of manufacturing a power semiconductor device comprising a power semiconductor element and a Peltier element joined to the power semiconductor element,
a step of arranging a plurality of structures constituting the Peltier element on an insulating substrate with lower electrodes interposed therebetween;
a step of connecting mutually adjacent constituents among the plurality of constituents by an upper electrode;
a step of bonding a plurality of electrically connected structures to the power semiconductor element with the insulating substrate interposed therebetween;
covering the Peltier element joined to the power semiconductor element with a heat capacitor that is in thermal contact with the Peltier element;
The plurality of constructs have a surface area enlarged portion with an enlarged surface area ,
The method of manufacturing a power semiconductor device, wherein the heat capacity body is a solid-liquid phase change material . In the method for manufacturing a power semiconductor device according to claim 6 ,
A method of manufacturing a power semiconductor device, wherein the surface area enlarged portion of the Peltier element structure has a triangular roof shape, a plane wave shape, or a porous shape with a ridgeline extending parallel to the upper surface of the power semiconductor element. In the method for manufacturing a power semiconductor device according to claim 6 or 7 ,
The method of manufacturing a power semiconductor device, wherein the Peltier element is made of semiconductor silicon. In the method for manufacturing a power semiconductor device according to any one of claims 6 to 8 ,
The step of arranging the plurality of constructs includes:
A method of manufacturing a power semiconductor device using a mask having openings at positions where the constituents are arranged.

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