JP7147668B2 - semiconductor equipment - Google Patents

Description

The disclosure in this specification relates to semiconductor devices.

A semiconductor device disclosed in Patent Document 1 includes a first switching element formed on a Si substrate and a second switching element formed on a SiC substrate. One first switching element and one second switching element are connected to a heat sink (heat radiation member) and connected in parallel with each other. The second switching element has a smaller substrate area than the first switching element.

JP 2016-219532 A

Improving the output may increase the size in the direction in which the first switching element and the second switching element are arranged.

One object of the disclosure is to provide a semiconductor device capable of suppressing an increase in size while improving output.

The semiconductor device disclosed herein is
a heat dissipation member (40);
A first switching element (51) formed on a Si substrate, and a second switching element (52) formed on a SiC substrate and having a smaller substrate area than the first switching element, one of the main electrodes dissipating heat. a plurality of switching elements (50) each connected to the member and connected in parallel with each other.

The switching element includes at least a plurality of first switching elements, and the first switching element and the second switching element are arranged side by side in a predetermined first direction, and the second switching element is arranged between the first switching elements . are placed.

Then, the length in the first direction is shorter in the second switching element than in the first switching element, and the ratio of the length in the second direction perpendicular to the first direction to the length in the first direction is the first switching element. It is made larger in the second switching element than in the element.

According to the disclosed semiconductor device, the second switching element is arranged between the first switching elements and is shorter than the first switching elements in the first direction, which is the alignment direction. Thereby, it is possible to suppress an increase in the physique in the first direction. Also, the second switching element has a larger ratio of the length in the second direction to the length in the first direction than the first switching element. As a result, the substrate area of the second switching element can be increased and the output can be improved compared to a configuration in which the length ratio is the same as that of the first switching element. As a result, it is possible to provide a semiconductor device capable of suppressing an increase in size while improving output power.

The multiple aspects disclosed in this specification employ different technical means to achieve their respective objectives. Reference numerals in parentheses described in the claims and this section are intended to exemplify the correspondence with portions of the embodiments described later, and are not intended to limit the technical scope. Objects, features, and advantages disclosed in this specification will become clearer with reference to the following detailed description and accompanying drawings.

It is a figure which shows the circuit structure of the power converter device to which the semiconductor device of 1st Embodiment is applied. It is a top view which shows the semiconductor device by the side of a lower arm. It is the top view which looked at FIG. 2 from the A direction. 4 is a partial cross-sectional view showing the structure inside the sealing resin body; FIG. 3 is a cross-sectional view taken along line V-V of FIG. 2; FIG. 3 is a cross-sectional view taken along line VI-VI of FIG. 2; FIG. 5 is a diagram showing the semiconductor device on the upper arm side, corresponding to FIG. 4; FIG. It is a figure which shows the arrangement|positioning of a switching element and a thermal radiation member. It is a figure which shows the arrangement|positioning of a switching element and a thermal radiation member. It is a top view which shows the laminated structure with a cooler. It is a top view which shows a modification, and respond|corresponds to FIG. FIG. 5 is a diagram showing the relationship between current paths and non-overlapping regions, corresponding to FIG. 4; It is a figure which shows current imbalance suppression. FIG. 10 is a diagram showing the semiconductor device of the second embodiment, showing heat generation states in two different periods; FIG. 5 is a diagram showing a semiconductor device according to a third embodiment, corresponding to FIG. 4; FIG. 4 is a diagram showing the arrangement of main terminals and current paths; FIG. 8 is a diagram showing a semiconductor device according to a fourth embodiment, corresponding to FIG. 7; It is a figure which shows one of the effects. It is a figure which shows another effect. It is a figure which shows another effect. FIG. 16 is a diagram showing the semiconductor device of the fifth embodiment, corresponding to FIG. 15; It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification. FIG. 16 is a diagram showing the semiconductor device of the sixth embodiment, corresponding to FIG. 15; It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification. It is a figure which shows a modification.

A number of embodiments will be described with reference to the drawings. In several embodiments, functionally and/or structurally corresponding parts are provided with the same reference numerals. The power converter described below is applicable to vehicles such as electric vehicles (EV) and hybrid vehicles (HV).

(First embodiment)
First, based on FIG. 1, a schematic configuration of a vehicle drive system to which a power converter is applied will be described.

<Vehicle drive system>
As shown in FIG. 1 , a vehicle drive system 1 includes a DC power supply 2 , a motor generator 3 , and a power conversion device 4 .

The DC power supply 2 is a DC voltage source composed of a rechargeable secondary battery. Secondary batteries include, for example, lithium-ion batteries and nickel-metal hydride batteries. The motor generator 3 is a three-phase alternating-current rotating electric machine. The motor generator 3 functions as a vehicle drive source, that is, as an electric motor. The motor generator 3 functions as a generator during regeneration. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3 .

<Circuit Configuration of Power Converter>
Next, based on FIG. 1, the circuit configuration of the power conversion device 4 will be described. The power conversion device 4 includes at least a power conversion section. The power converter 4 of this embodiment includes a smoothing capacitor 5 , an inverter 6 that is a power converter, a control circuit 7 , and a drive IC 8 .

Smoothing capacitor 5 is connected between P line 9, which is a power line on the high potential side, and N line 10, which is a power line on the low potential side. The P line 9 is connected to the positive pole of the DC power supply 2 and the N line 10 is connected to the negative pole of the DC power supply 2 . Smoothing capacitor 5 mainly smoothes the DC voltage supplied from DC power supply 2 .

The inverter 6 is a DC-AC converter. The inverter 6 is configured with upper and lower arm circuits 11 for three phases. A connection point of the U-phase upper and lower arm circuits 11 is connected to a U-phase winding provided on the stator of the motor generator 3 . Similarly, the connection point of the V-phase upper and lower arm circuits 11 is connected to the V-phase winding of the motor generator 3 . A connection point of the W-phase upper and lower arm circuits 11 is connected to a W-phase winding of the motor generator 3 . A connection point of the upper and lower arm circuits 11 is connected to a corresponding phase winding through an output line 12 . The output line 12 and the P line 9 and N line 10 described above are configured by bus bars, for example.

The upper and lower arm circuits 11 each have an upper arm 11U and a lower arm 11L. The upper arm 11U and the lower arm 11L are connected in series between the P line 9 and the N line 10 with the upper arm 11U on the P line 9 side. Each arm has an IGBT 111 , a MOSFET 112 and a diode 113 . The IGBT 111 and MOSFET 112 are connected in parallel with each other. In this embodiment, the IGBT 111 and the MOSFET 112 are of n-channel type. A diode 113 is connected anti-parallel to the IGBT 111 for freewheeling. MOSFET 112 has a parasitic diode (not shown).

In one arm, the collector electrode of the IGBT 111 and the drain electrode of the MOSFET 112 are connected together, and the emitter electrode of the IGBT 111 and the source electrode of the MOSFET 112 are connected together. The diode 113 has an anode electrode connected to the emitter electrode and a cathode electrode connected to the collector electrode.

A collector electrode and a drain electrode are connected to the P line 9 in the upper arm 11U. An emitter electrode and a source electrode are connected to the N line 10 in the lower arm 11L. The emitter electrode and source electrode on the upper arm 11U side and the collector electrode and drain electrode on the lower arm 11L side are connected to each other. A semiconductor device 20, which will be described later, constitutes one arm. Two semiconductor devices 20 constitute the upper and lower arm circuits 11 , and six semiconductor devices 20 constitute the inverter 6 .

Inverter 6 converts the DC voltage into a three-phase AC voltage according to switching control by control circuit 7 and outputs the same to motor generator 3 . Thereby, the motor generator 3 is driven to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to the rotational force from the wheels into a DC voltage in accordance with the switching control of the control circuit 7, and outputs the DC voltage to the P line 9. . Thus, inverter 6 performs bidirectional power conversion between DC power supply 2 and motor generator 3 .

The control circuit 7 generates a drive command for operating the IGBT 111 and the MOSFET 112 and outputs it to the drive IC 8 . The control circuit 7 generates a drive command based on a torque request input from a host ECU (not shown) and signals detected by various sensors. Various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects a phase current flowing through each phase winding. The rotation angle sensor detects the rotation angle of the rotor of motor generator 3 . A voltage sensor detects the voltage across the smoothing capacitor 5 . The power conversion device 4 includes these sensors (not shown). The control circuit 7 outputs a PWM signal as a drive command. The control circuit 7 includes, for example, a microcomputer. ECU is an abbreviation for Electronic Control Unit. PWM is an abbreviation for Pulse Width Modulation.

The drive IC 8 generates a gate drive signal based on the drive command from the control circuit 7 . The drive IC 8 outputs the generated gate drive signal to the IGBT 111 and MOSFET 112 of the corresponding arm. Gate electrodes of the IGBT 111 and the MOSFET 112 forming one arm are electrically connected to the same drive IC 8 .

The drive IC 8 drives the IGBT 111 and the MOSFET 112, that is, turns them on and off, using gate drive signals. The drive IC 8 outputs a gate drive signal with a predetermined duty ratio. The drive IC 8 is also called a driver. In this embodiment, one drive IC 8 is provided for one arm. One drive IC 8 may be provided for one upper and lower arm circuit 11 . The drive IC 8 may be provided integrally with the control circuit 7 .

The power conversion device 4 may further include a converter as a power conversion section. A converter is a DC-DC converter that converts a DC voltage into DC voltages of different values. The converter is provided between the DC power supply 2 and the smoothing capacitor 5 . The converter includes, for example, a reactor and the upper and lower arm circuits 11 described above. In this case, the upper and lower arm circuits 11 of the converter can also be configured with two semiconductor devices 20 . Furthermore, a filter capacitor for removing power noise from the DC power supply 2 may be provided. A filter capacitor is provided between the DC power supply 2 and the converter.

<Basic Structure of Semiconductor Device>
Next, a semiconductor device constituting the upper and lower arm circuits 11 will be described with reference to FIGS. 2 to 7. FIG. As shown in FIGS. 2 to 7, the semiconductor device 20 includes a sealing resin body 30, a heat dissipation member 40, a plurality of switching elements 50, terminals 60, a plurality of main terminals 70, and a plurality of signal terminals 80. It has

Hereinafter, the thickness direction of the switching element 50 will be referred to as the Z direction. The direction orthogonal to the Z direction and in which the plurality of switching elements 50 are arranged is indicated as the X direction. A direction orthogonal to the Z direction and the X direction is indicated as the Y direction. Unless otherwise specified, a shape along the XY plane, in other words, a shape viewed from the Z direction is simply referred to as a planar shape. In this embodiment, the X direction corresponds to the first direction, and the Y direction corresponds to the second direction.

The upper and lower arm circuits 11 are composed of two semiconductor devices 20 . In this embodiment, the semiconductor device 20L constituting the lower arm 11L and the semiconductor device 20U constituting the upper arm 11U are separated. 2 to 6 show the semiconductor device 20L, and FIG. 7 shows the semiconductor device 20U. 4 and 7 show semiconductor device 20L. 20U is a partial cross-sectional view showing the structure inside the sealing resin body 30 of each 20U. FIG. In FIG.4 and FIG.7, the 2nd heat radiating member 42 is shown with the broken line.

Appearances of the semiconductor devices 20L and 20U are substantially the same. The semiconductor devices 20</b>L and 20</b>U have substantially the same configuration except for the order of arrangement of the main terminals 70 and the electrical connection structure between the main terminals 70 and the heat dissipation member 40 . Below, unless otherwise specified, the semiconductor devices 20L and 20U have a common structure.

The encapsulating resin body 30 encapsulates other elements forming the semiconductor device 20 , such as the switching element 50 . Sealing resin body 30 is made of, for example, an epoxy resin. The encapsulating resin body 30 is molded by, for example, a transfer molding method. The sealing resin body 30 is sometimes called mold resin. The sealing resin body 30 has one surface 30a and a back surface 30b opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. The sealing resin body 30 has a side surface connecting the one surface 30a and the back surface 30b.

In this embodiment, the sealing resin body 30 has a substantially rectangular planar shape. The sealing resin body 30 has side surfaces 30c and 30d. The side surface 30d is a surface opposite to the side surface 30c in the Y direction. A main terminal 70 protrudes from the side surface 30c. A signal terminal 80 protrudes from the side surface 30d.

The heat radiating member 40 radiates heat generated by the switching element 50 . The heat dissipation member 40 functions as wiring that electrically relays the switching element 50 and the main terminal 70 . The heat dissipation member 40 is formed using at least a metal material (for example, Cu) that is excellent in electrical conductivity and thermal conductivity. Heat dissipation member 40 is, for example, a metal plate. A composite material of an electrical insulator such as resin or ceramics and a metal body can be used instead of the metal plate. The heat dissipation member 40 is arranged on at least one side in the Z direction with respect to the switching element 50 . A plurality of switching elements 50 connected in parallel are electrically connected to the surface of the heat dissipation member 40 on the side of the switching elements 50 .

In this embodiment, a pair of heat dissipation members 40 are provided so as to sandwich the switching element 50 . The heat dissipation member 40 includes a first heat dissipation member 41 arranged on the one surface 30a side and a second heat dissipation member 42 arranged on the back surface 30b side. Hereinafter, the first heat dissipation member 41 and the second heat dissipation member 42 may be simply referred to as heat dissipation members 41 and 42 . As the heat radiation members 41 and 42, members of the same type may be used, or members different from each other may be used. In this embodiment, the same kind of member, specifically a metal plate containing Cu, is used as the heat dissipation members 41 and 42 .

The heat dissipation members 41 and 42 are provided so as to enclose the switching element 50 in plan view from the Z direction. The heat radiating members 41 and 42 include switching elements 50 in regions facing each other. The heat dissipation members 41 and 42 respectively have mounting surfaces 41a and 42a on the side of the switching element 50 and heat dissipation surfaces 41b and 42b opposite to the mounting surfaces 41a and 42a in the Z direction. The mounting surfaces 41a and 42a face each other in the Z direction. The mounting surfaces 41a and 42a are substantially parallel to each other. The plate thickness direction of the heat radiating members 41 and 42 is substantially parallel to the Z direction. The heat radiating members 41 and 42 are longitudinal in the X direction. At least part of each of the heat dissipation members 41 and 42 is sealed with the sealing resin body 30 .

The switching element 50 is formed by forming an element forming the arm on a semiconductor substrate. The switching element 50 is sometimes called a semiconductor element or a semiconductor chip. The plurality of switching elements 50 are electrically connected to the heat dissipation member 40 and connected in parallel with each other.

The switching element 50 has main electrodes on both sides in the Z direction, and has a vertical structure in which the main current flows in the Z direction. The switching element 50 includes a first switching element 51 and a second switching element 52 . The first switching element 51 is formed on a Si (silicon) substrate. The second switching element 52 is formed on a SiC (silicon carbide) substrate. Hereinafter, the first switching element 51 and the second switching element 52 may be simply referred to as switching elements 51 and 52 . An IGBT 111 is formed in the first switching element 51 . In this embodiment, the diode 113 is integrally formed with the IGBT 111 . That is, the first switching element 51 is formed with an RC (Reverse Conducting)-IGBT. A MOSFET 112 is formed in the second switching element 52 .

The first switching element 51 has, as main electrodes, a collector electrode 51c formed on one surface and an emitter electrode 51e formed on the opposite rear surface. The collector electrode 51c also serves as the cathode electrode of the diode 113, and the emitter electrode 51e serves as the anode electrode of the diode 113 as well. The collector electrode 51c is formed on almost the entire surface, and the emitter electrode 51e is formed on part of the back surface. The second switching element 52 has, as main electrodes, a drain electrode 52d formed on one surface and a source electrode 52s formed on the opposite rear surface. The drain electrode 52d is formed on almost the entire surface, and the source electrode 52s is formed on a portion of the back surface.

In a semiconductor substrate, an element formation region is an active region that generates heat when energized. A breakdown voltage structure (for example, a guard ring) (not shown) is formed in an outer peripheral region surrounding the active region. In a plan view from the Z direction, the emitter electrode 51e and the source electrode 52s, which are main electrodes on the low potential side, substantially coincide with the active region.

The switching element 50 has a temperature sensor 53 on the back side of the semiconductor substrate. A temperature sensor 53 detects the substrate temperature (element temperature) for overheat protection. Since the substrate temperature increases closer to the center of the active region, the temperature sensor 53 is provided near the center of the active region in plan view from the Z direction. In this embodiment, a temperature sensitive diode is used as the temperature sensor 53 . A temperature sensitive diode is formed by doping impurities into polysilicon arranged on a semiconductor substrate, for example. A detection signal from the temperature sensor 53 is used to control the switching element 50 . Specifically, the switching element 50 is forcibly turned off before the switching element 50 becomes overheated. The temperature sensitive diode can also be built into the semiconductor substrate.

The first switching element 51 has a pad 51p, which is an electrode for signals, separately from the main electrode. The pad 51p is formed on the same surface as the emitter electrode 51e. The pad 51p is formed at the end opposite to the formation region of the emitter electrode 51e in the Y direction. The second switching element 52 also has a pad 52p. The pad 52p is formed on the same surface as the source electrode 52s. The pad 52p is formed at the end opposite to the formation region of the source electrode 52s in the Y direction. In the Y direction, the emitter electrode 51e and the source electrode 52s are formed on the main terminal 70 side, and the pads 51p and 52p are formed on the signal terminal 80 side.

In this embodiment, the collector electrode 51c is formed on the surface on the first heat dissipation member 41 side, and the emitter electrode 51e is formed on the surface on the second heat dissipation member 42 side. A drain electrode 52d is formed on the surface on the first heat dissipation member 41 side, and a source electrode 52s is formed on the surface on the second heat dissipation member 42 side. A collector electrode 51c and a drain electrode 52d, which are main electrodes on the high potential side, are connected to the mounting surface 41a of the first heat dissipation member 41 via a bonding material 90 . The emitter electrode 51 e and the source electrode 52 s, which are the main electrodes on the low potential side, are connected to the mounting surface 42 a of the second heat dissipation member 42 via the bonding material 90 and the terminal 60 . Solder or a conductive paste containing Ag or the like can be used as the bonding material 90 . The bonding material 90 of this embodiment is solder.

The first switching element 51 has five pads 51p. Specifically, it is for the gate electrode, for detecting the potential of the emitter electrode 51e, for current sensing, for the anode potential of the temperature sensor 53, and for the cathode potential. A plurality of pads 51p are provided side by side in the X direction. Similarly, the second switching element 52 has five pads 52p. Specifically, they are for the gate electrode, for detecting the potential of the source electrode 52s, for current sensing, for the anode potential of the temperature sensor 53, and for the cathode potential. A plurality of pads 52p are provided side by side in the X direction.

The switching element 50 includes a plurality of at least one of the first switching elements 51 and the second switching elements 52 . The first switching elements 51 and the second switching elements 52 are alternately arranged in the X direction in which the switching elements 50 are arranged. Alternating means an arrangement in which the first switching elements 51 and the second switching elements 52 are adjacent to each other in the arrangement direction. An example of an alternating minimum configuration is a combination of two first switching elements 51 and one second switching element 52 . Another example is a combination of one first switching element 51 and two second switching elements 52 .

The switching element 50 of this embodiment includes two first switching elements 51 and one second switching element 52 . The two first switching elements 51 have the same configuration. Hereinafter, one of the first switching elements 51 may be referred to as a first switching element 51a, and the other one as a first switching element 51b. The three switching elements 50 are arranged in order of the first switching element 51a, the second switching element 52, and the first switching element 51b in the X direction. The second switching element 52 is arranged between the first switching elements 51a and 51b. The first switching elements 51a and 51b are connected in parallel with each other. Since the elements formed in the first switching elements 51a and 51b are circuit-wise equivalent, one IGBT 111 and one diode 113 are shown in FIG.

The terminal 60 is interposed between the second heat radiating member 42 and the switching element 50 to ensure a predetermined distance between the second heat radiating member 42 and the switching element 50 . Terminal 60 is sufficiently thicker than switching element 50 . The terminal 60 functions to transfer heat from the switching element 50 to the second heat dissipation member 42 . The terminal 60 functions as wiring that electrically relays the switching element 50 and the second heat dissipation member 42 . Terminal 60 is formed using a metal material such as Cu. The terminal 60 may have either a single-layer structure using one type of metal or a multi-layer structure using multiple types of metals. Terminal 60 is divided by at least a first switching element 51 and a second switching element 52 .

In this embodiment, one terminal 60 is provided for one switching element 50 . Terminal 60 functions as a spacer that secures a predetermined distance between second heat radiating member 42 and switching element 50 . The spacer can prevent the bonding wire 91 from contacting the second heat dissipation member 42 . Each of the terminals 60 has a substantially rectangular parallelepiped shape. The planar shape of the terminal 60 is substantially the same as that of the main electrode to be connected. In the Z direction, one end face of the terminal 60 is connected to the main electrode of the switching element 50 and the other end face is connected to the second heat dissipation member 42 . The terminal 60 is connected to the corresponding main electrodes 51 e and 52 s and the second heat dissipation member 42 via the bonding material 90 .

The main terminal 70 is a terminal through which a main current flows among external connection terminals for electrically connecting the semiconductor device 20 and an external device. The main terminals 70 are electrically connected to corresponding main electrodes. The main terminals 70 include a high potential terminal 71 and a low potential terminal 72 . The high potential terminal 71 is electrically connected to the collector electrode 51c and the drain electrode 52d, which are main electrodes on the high potential side. The high potential terminal is sometimes called a collector terminal and a drain terminal. The low potential terminal 72 is electrically connected to the emitter electrode 51e and the source electrode 52s, which are main electrodes on the low potential side. The low potential terminal 72 is sometimes called an emitter terminal and a source terminal. Hereinafter, the high potential terminal 71 and the low potential terminal 72 may simply be referred to as main terminals 71 and 72 .

The main terminals 70 are connected to corresponding main electrodes via the heat dissipation member 40 . The high potential terminal 71 continues to the first heat radiation member 41 . The low potential terminal 72 continues to the second heat dissipation member 42 . The main terminal 70 is integrally connected to the heat dissipation member 40, for example, as part of a metal member (for example, a lead frame). The main terminal 70 is provided, for example, as a separate member from the heat radiating member 40 and continues to the heat radiating member 40 by connection. The main terminal 70 continues to the corresponding heat dissipation member 40 inside the sealing resin body 30 . The main terminal 70 is continuous with the heat radiating member 40 near the end on the side surface 30c side in the Y direction. All the main terminals 70 extend inside and outside the sealing resin body 30 .

In this embodiment, all the main terminals 70 extend in the Y direction from the corresponding heat dissipation member 40 . All the main terminals 70 protrude outside from the side surface 30c of the sealing resin body 30. As shown in FIG. The main terminals 71 and 72 both have bent portions within the sealing resin body 30, and protrude from substantially the same position in the Z direction on the side surface 30c. In a portion including the projecting portion, the main terminals 71 and 72 are arranged side by side with a predetermined gap in the X direction so that the side faces face each other.

The main terminal 70 includes one of a high potential terminal 71 and a low potential terminal 72 and two of the other. The main terminal 70 has a plurality (two sets) of side-facing portions of a high-potential terminal 71 and a low-potential terminal 72 . As shown in FIGS. 4 and 7 , the high potential terminal 71 is integrally connected to the first heat radiation member 41 . The low potential terminal 72 continues to the second heat dissipation member 42 by connection. The low potential terminal 72 is connected to the mounting surface 42a of the second heat radiating member 42 via a bonding material 90, as shown in FIG. 6, for example.

The semiconductor device 20L has two high potential terminals 71 and one low potential terminal 72 .
The main terminals 71 and 72 are arranged side by side in the X direction. The low potential terminal 72 is arranged between the high potential terminals 71 . As shown in FIG. 4, the first heat radiation member 41 has a recess 41c recessed toward the side surface 30d with respect to the portion where the high potential terminals 71 are connected. The recess 41c is provided in the central region of the first heat radiation member 41 in the X direction. The high potential terminal 71 is connected to each of the peripheral regions sandwiching the central region of the first heat dissipation member 41 . The second heat radiating member 42 includes a portion that overlaps with the concave portion 41c in plan view in the Z direction as a non-facing region that does not face the first heat radiating member 41 . The low potential terminal 72 is connected to a portion of the second heat radiating member 42 which is a non-facing region and overlaps with the recess 41c. Since it is a non-facing region, it is easy to connect the low potential terminal 72 to the second heat dissipation member 42 .

The semiconductor device 20U has one high potential terminal 71 and two low potential terminals. The main terminals 71 and 72 are arranged side by side in the X direction. The high potential terminal 71 is arranged between the low potential terminals 72 . As shown in FIG. 7, the first heat dissipation member 41 of the semiconductor device 20U also has a recess 41c. The recesses 41c are provided in peripheral regions of the first heat radiation member 41 in the X direction. The high-potential terminal 71 is connected to the central region sandwiched between the peripheral regions in the first heat dissipation member 41 . The low potential terminal 72 is connected to a portion of the second heat radiating member 42 which is a non-facing region and overlaps with the recess 41c.

The signal terminals 80 are electrically connected to pads of the corresponding switching elements 50 . The signal terminals 80 include a first signal terminal 81 and a second signal terminal 82 . The first signal terminal 81 is electrically connected to the pad 51p of the first switching element 51 . The second signal terminal 82 is electrically connected to the pad 52p of the second switching element 52 .

The signal terminals 80 of this embodiment are connected to the corresponding pads 51p and 52p via bonding wires 91. As shown in FIG. The signal terminal 80 is connected to the bonding wire 91 inside the sealing resin body 30 . The signal terminals 80 each extend in the Y direction and protrude from the side surface 30d of the sealing resin body 30 to the outside. The signal terminal 80 is part of the lead frame including the main terminal 70 and the first heat dissipation member 41 .

In the semiconductor device 20 configured as described above, at least a portion of each of the heat dissipation members 40, a portion of each of the switching elements 50, the terminals 60 and the main terminals 70, and a portion of each of the signal terminals 80 are formed from the sealing resin body. 30 are integrally sealed. That is, the elements forming one arm are sealed. Therefore, the semiconductor device 20 is also called a 1-in-1 package.

Although an example in which the semiconductor device 20U for the upper arm 11U and the semiconductor device 20L for the lower arm 11L are separately provided as the semiconductor device 20 has been shown, the present invention is not limited to this. Semiconductor device 20 may have a common structure for upper arm 11U and lower arm 11L. For example, the semiconductor device 20L described above may be used not only for the lower arm 11L but also for the upper arm 11U. The semiconductor device 20U may be used not only for the upper arm 11U but also for the lower arm 11L. Thereby, the number of parts can be reduced. Also, the structures of the semiconductor device 20L and the semiconductor device 20U may be interchanged. That is, the semiconductor device 20L may be used for the upper arm 11U, and the semiconductor device 20U may be used for the lower arm 11L.

<Details of switching elements, heat dissipation materials, and main terminals>
Next, details of the semiconductor device 20 will be described with reference to FIGS. 4 to 9. FIG. 8 and 9 are schematic plan views showing the positional relationship between the switching element 50 and the heat dissipation members 41 and 42. FIG. 8 and 9 also show the main terminals 71 and 72. FIG. 8 and 9 show the semiconductor device 20L, but the semiconductor device 20U is the same.

In this embodiment, the substrate area of the second switching element 52 is made smaller than the substrate area of each of the first switching elements 51 . The substrate area is the area perpendicular to the Z direction, which is the thickness direction, that is, the area along the XY plane. The substrate area is sometimes called a chip area or an element area. Increasing the substrate area also increases the active area of the device. By making the SiC substrate smaller than the Si substrate, it is possible to reduce the cost and size. Also, the thickness of the second switching element 52 is made thinner than that of the first switching element 51 . With the same breakdown voltage, SiC can make the drift layer thinner than Si.

The switching element 50 is arranged in the central region in the Y direction on the mounting surface 41a. In the Y direction, the positions of the ends of the first switching element 51 and the second switching element 52 on the signal terminal 80 side are substantially the same. The position of the end on the main terminal 70 side differs between the first switching element 51 and the second switching element 52 .

8 and 9 show a region R1 virtually extending the first switching element 51 in the X direction and a region R2 virtually extending the second switching element 52 in the Y direction. The region R1 is defined by a line virtually extending both ends of the first switching element 51 in the Y direction in the X direction. The region R2 is defined by a line virtually extending both ends of the second switching element 52 in the X direction in the Y direction. In FIGS. 8 and 9, the lines that are virtually extended are indicated by dashed-dotted lines.

As shown in FIG. 8, the first heat radiation member 41 has an intersection region 41d that overlaps the intersection of the regions R1 and R2 in plan view from the Z direction. In FIG. 8, the intersection region 41d is indicated by a dashed line. The intersection region 41 d has an overlapping region 41 e that overlaps the second switching element 52 and a non-overlapping region 41 f that does not overlap the second switching element 52 . The first heat radiation member 41 has an overlapping region 41e and a non-overlapping region 41f in a facing region formed between the two first switching elements 51a and 51b arranged in the X direction. In the first heat dissipation member 41, the overlapping area 41e is a mounting area for the second switching element 52, and the non-overlapping area 41f is a non-mounting area. In the Z direction, the overlapping region 41e is a region facing the second switching element 52, and the non-overlapping region 41f is a non-facing region.

As shown in FIG. 9, the second heat radiating member 42, like the first heat radiating member 41, has an intersection region 42d. In FIG. 9, the intersection area 42d is indicated by a dashed line. The intersection region 42 d has an overlapping region 42 e that overlaps the second switching element 52 and a non-overlapping region 42 f that does not overlap the second switching element 52 . The second heat radiating member 42 has an overlapping area 42e and a non-overlapping area 42f in a facing area formed between the two first switching elements 51a and 51b arranged in the X direction. In the second heat dissipation member 42, the overlapping region 42e is a region facing the second switching element 52, and the non-overlapping region 42f is a non-facing region.

As shown in FIGS. 8 and 9, part of the emitter electrode 51e and part of the source electrode 52s are arranged at the same position in the Y direction. A portion of the emitter electrode 51e is arranged at the same position in the Y direction as a portion of the overlapping regions 41e and 42e. Another portion of the emitter electrode 51e is arranged at the same position in the Y direction as a portion of the non-overlapping region 41f. That is, in the X direction, a portion of the emitter electrode 51e faces the source electrode 52s, and the other portion faces the non-overlapping regions 41f and 42f.

Thus, the heat dissipation member 40 has non-overlapping regions 41f and 42f as part of the intersection regions 41d and 42d. At least parts of the non-overlapping regions 41 f and 42 f are exposed from the sealing resin body 30 . For example, only at least part of the non-overlapping region 41f may be exposed. Only at least part of the non-overlapping region 42f may be exposed. Both non-overlapping regions 41f and 42f may be exposed. When the non-overlapping region 41f is exposed, at least one of the mounting surface 41a and the heat dissipation surface 41b should be exposed. Similarly, when the non-overlapping region 42f is exposed, at least one of the mounting surface 42a and the heat dissipation surface 42b should be exposed.

In this embodiment, the non-overlapping regions 41f and 42f are exposed. The entire non-overlapping region 41f is exposed on the heat dissipation surface 41b side and covered on the mounting surface 41a side. The entire non-overlapping region 42f is exposed on the heat dissipation surface 42b side and covered on the mounting surface 42a side. Furthermore, overlapping regions 41e and 42e are also exposed. The heat dissipation surfaces 41b and 42b are exposed over almost the entire area. The heat dissipation surface 41 b is exposed substantially flush with the one surface 30 a of the sealing resin body 30 . The heat dissipation surface 42b is exposed substantially flush with the rear surface 30b. The semiconductor device 20 has a double-sided heat dissipation structure in which both the heat dissipation surfaces 41 b and 42 b are exposed from the sealing resin body 30 .

A virtual line CL1 shown in FIGS. 4 and 7 to 9 is a line passing through the elemental center of the second switching element 52 and extending in the Y direction. The elemental center is the center of the second switching element 52 (chip). A virtual line CL1 passes through the center of the active area.

In this embodiment, the arrangement of the three switching elements 50 is symmetrical with respect to the virtual line CL1. Thereby, the interval between the switching elements 51a and 52 and the interval between the switching elements 51b and 52 are substantially equal to each other. The non-overlapping regions 41e and 42e described above are positioned on the imaginary line CL1.

The arrangement of the three terminals 60 is also symmetrical with respect to the imaginary line CL1. Each of the first heat radiation member 41 and the second heat radiation member 42 is also line-symmetrical with respect to the virtual line CL1. In the semiconductor device 20L, the low potential terminal 72 is arranged on the virtual line CL1. The center of the width of low potential terminal 72 is located on virtual line CL1. As shown in FIG. 4, the arrangement of the three main terminals 70 is symmetrical with respect to the virtual line CL1. In semiconductor device 20U, high potential terminal 71 is arranged on virtual line CL1. The center of the width of low potential terminal 72 is located on virtual line CL1. As shown in FIG. 7, the arrangement of the three main terminals 70 is symmetrical with respect to the virtual line CL1.

<Cooling structure of semiconductor device>
Next, a cooling structure for the semiconductor device 20 will be described with reference to FIG. The semiconductor devices 20 described above are stacked alternately with the coolers 100 as shown in FIG. Semiconductor device 20 constitutes power module 110 together with cooler 100 .

Cooler 100 has a coolant flow path therein. The coolers 100 are arranged in multiple stages at predetermined intervals in the Z direction. The multistage coolers 100 are connected by a supply pipe 101 on one end side in the X direction. The supply pipe 101 is a tubular body having a flow path formed therein and extends in the Z direction. The supply pipe 101 is connected to each cooler 100 , and the flow path of the supply pipe 101 communicates with the flow path of each cooler 100 .

The multi-stage coolers 100 are connected by a discharge pipe 102 at the end opposite to the supply pipe 101 . The discharge pipe 102 is also a cylindrical body having a flow path formed therein, and extends in the Z direction. The discharge pipe 102 is connected to each cooler 100 , and the flow path of the discharge pipe 102 communicates with the flow path of each cooler 100 . The coolant that has flowed from the supply pipe 101 spreads through the flow paths of the coolers 100 and is discharged from the discharge pipe 102 .

As the refrigerant, a phase-change refrigerant such as water or ammonia, or a phase-invariable refrigerant such as an ethylene glycol-based refrigerant can be used. Cooler 100 mainly cools semiconductor device 20 . However, in addition to the cooling function, it may also have a warming function when the environmental temperature is low. In this case, cooler 100 is referred to as a temperature controller. A refrigerant is also called a heat carrier.

The power module 110 includes six semiconductor devices 20 forming the inverter 6 and a plurality of (multistage) coolers 100 stacked alternately with the semiconductor devices 20 so as to cool each of the semiconductor devices 20 from both sides. ing. The semiconductor device 20 is sandwiched by coolers 100 from both sides in the Z direction. Most of the encapsulating resin body 30 is arranged within the facing region of the adjacent coolers 100 . Each of the main terminals 70 extends to the outside of the facing area in the Y direction, for example, for connection with a bus bar or the like (not shown).

The plurality of semiconductor devices 20 are arranged so as to overlap each other in plan view from the Z direction. In each semiconductor device 20, the switching elements 50 are arranged in order of the first switching element 51a, the second switching element 52, and the first switching element 51b from the upstream side to the downstream side. That is, in the X direction, the first switching element 51a is arranged on the supply pipe 101 side, and the first switching element 51b is arranged on the discharge pipe 102 side.

Semiconductor devices 20L and 20U forming upper and lower arm circuits 11 of the same phase are adjacent to each other in the Z direction. As a result, the low potential terminal 72 of the semiconductor device 20U and the high potential terminal 71 of the semiconductor device 20L, which constitute the same phase, overlap each other in a plan view from the Z direction. Therefore, the connection distance between the upper arm 11U and the lower arm 11L can be shortened, and the inductance can be reduced, for example. Also, connectivity can be improved.

In this way, the semiconductor devices 20 (20U, 20L) are cooled by the cooler 100 while being sandwiched in the Z direction, which is the facing direction.

<Summary of the first embodiment>
In this embodiment, the switching element 50 includes a plurality of at least one of the first switching elements 51 formed on the Si substrate and the second switching elements 52 formed on the SiC substrate. Therefore, the output of the semiconductor device 20 can be improved as compared with the configuration including the switching elements 51 and 52 one by one.

Also, the switching elements 51 and 52 are alternately arranged in the X direction (first direction). The heat dissipation member 40 has non-overlapping regions 41f and 42f as the intersection regions 41d and 42d. The non-overlapping regions 41f and 42f are regions where the heat of the first switching element 51 and the second switching element 52 is transferred. At least part of the non-overlapping regions 41f and 42f are exposed from the sealing resin body 30, and can effectively dissipate heat. Therefore, the heat generated by the switching elements 51 and 52 tends to diffuse toward the non-overlapping regions 41f and 42f. Therefore, an increase in element temperature can be suppressed.

As described above, it is possible to provide the semiconductor device 20 capable of suppressing an increase in the element temperature while improving the output. When the element temperature rises, for example, an increase in on-resistance, a decrease in the reliability of the bonding material 90, a decrease in margin for the rated temperature (decrease in output), and the like can occur. According to this embodiment, it is possible to suppress the occurrence of such a problem.

The heat dissipation member 40 may include at least the non-overlapping regions 41f and 42f as exposed portions. For example, as in the modification shown in FIG. 11, only the non-overlapping region 42f of the second heat dissipation member 42 may be exposed from the sealing resin body 30. As shown in FIG. In FIG. 11, the non-overlapping region 42f is exposed on the heat dissipation surface 42b side.

In this embodiment, at least part of the overlapping regions 41f and 42f are exposed from the sealing resin body 30 in addition to the non-overlapping regions 41f and 42f. The overlapping regions 41 f and 42 f are regions directly below the second switching element 52 . It is possible to effectively suppress the increase in element temperature, particularly the temperature increase in the second switching element 52 .

In particular, in this embodiment, not only the overlapping regions 41e, 42e and the non-overlapping regions 41f, 42f but also the regions overlapping the first switching element 51 are exposed, and substantially the entire areas of the heat dissipation surfaces 41b, 42b are exposed. Heat dissipation on both sides and exposure of the entire area can further suppress the rise in element temperature.

At least the first switching elements 51 and the second switching elements 52 may be arranged alternately, and the number of elements is not particularly limited. For example, two first switching elements 51 and two second switching elements 52 may be included. Three first switching elements 51 may be included and two second switching elements 52 may be included. One first switching element 51 may be included and two second switching elements 52 may be included.

In this embodiment, two first switching elements 51 formed with IGBTs 111 are included, and one second switching element 52 formed with a MOSFET 112 is included. The second switching element 52 is arranged between the first switching elements 51 . Since the substrate area of the second switching element 52 is small, the heat dissipation members 41 and 42 have non-overlapping regions 41f and 42f. The non-overlapping regions 41 f and 42 f are empty regions that do not overlap with the switching element 50 . Since this empty area is actively used for heat dissipation, thermal interference between the first switching elements 51 located on both sides of the non-overlapping areas 41f and 42f can be suppressed. Moreover, the heat of the second switching elements 52 adjacent to the non-overlapping regions 41f and 42f in the Y direction can be effectively released. As a result, it is possible to suppress the temperature rise of the MOSFET 112 and thus suppress the increase in the on-resistance.

The number of main terminals 71 and 72 is not particularly limited. A configuration including one each of the main terminals 71 and 72 may be employed. In this embodiment, the arrangement of the main terminals 71 and 72 is alternate in the arrangement direction of the switching elements 50 . As a result, a plurality of sets of opposing side surfaces of the high-potential terminal 71 and the low-potential terminal 72 are formed. The direction of the main current is substantially opposite between the high potential terminal 71 and the low potential terminal 72 . By providing a plurality of sets, the magnetic flux generated when the main current flows can be canceled out, and the effect of reducing the inductance can be enhanced. Moreover, since at least one of the main terminals 71 and 72 is included in a plurality, the inductance can be reduced by parallelization. For example, surge voltage can be reduced.

In the alternate arrangement, the number of main terminals 71 and 72 is not particularly limited. In this embodiment, one first main terminal, which is one of the main terminals 71 and 72, is included, and two second main terminals, which are the other of the main terminals 71 and 72, are included. In the semiconductor device 20L, the low potential terminal 72 is the first main terminal and the high potential terminal 71 is the second main terminal. In the semiconductor device 20U, the high potential terminal 71 is the first main terminal and the low potential terminal 72 is the second main terminal. The first main terminal is arranged on a virtual line CL1 passing through the elemental center of the second switching element 52 . In a plan view from the Z direction, the non-overlapping regions 41f and 42f are provided on the imaginary line CL1.

For example, in the semiconductor device 20L shown in FIG. 12, the current path between the first main terminal (low potential terminal 72) and the second switching element 52 is provided with a non-overlapping region 42f. Since the number of the first main terminals is smaller than that of the second main terminals, the current density in the non-overlapping region 42f is high. However, the non-overlapping region 42f is exposed from the sealing resin body 30 and can efficiently dissipate heat. Therefore, it is possible to suppress an increase in element temperature, particularly the temperature of the second switching element 52 . Thereby, an increase in the on-resistance of the MOSFET 112 can be suppressed. Although not shown, in the semiconductor device 20U, the current path between the first main terminal (high potential terminal 71) and the second switching element 52 is provided with a non-overlapping region 41f. The non-overlapping region 41f is exposed from the sealing resin body 30 and has the same effect as the semiconductor device 20L.

In this embodiment, the semiconductor device 20 has an odd number of switching elements 50 . The arrangement of the plurality of switching elements 50 is symmetrical with respect to the virtual line CL1. The linear expansion coefficients of the first switching element 51 formed on the Si substrate and the second switching element 52 formed on the SiC substrate are different from each other. However, due to the axisymmetric arrangement, the thermal stress acting on the heat dissipation member 40 based on the difference in linear expansion coefficient between the heat dissipation member 40 and the switching element 50 is also symmetrical. Thereby, local deformation of the semiconductor device 20 can be suppressed. In addition, although the example of 3 pieces was shown as an odd number, it is not limited to this. For example, it can be applied to a configuration including five switching elements 50 .

In this embodiment, the intervals between the second switching element 52 and the first switching elements 51a and 51b are substantially equal. As a result, the heat generated by the second switching element 52 spreads almost evenly to both sides of the first switching elements 51a and 51b in the X direction. Also, the heat generated by the first switching elements 51a and 51b similarly spreads to the second switching element 52 side.

Therefore, it is possible to reduce the temperature difference between the first switching elements 51a and 51b and prevent the DC current from flowing unevenly to one of the first switching elements 51a and 51b. A DC current is a current that flows not during switching but during steady state when the switching element is turned on. Moreover, it is possible to suppress the concentration of heat between one of the first switching elements 51 and the second switching element 52 . For example, it is possible to suppress an increase in on-resistance due to an increase in temperature of the second switching element 52 . In particular, it is effective in a configuration in which the switching elements 51 and 52 are turned on at the same time.

In addition, since the intervals are substantially equal, air remains between one of the first switching elements 51 a and 51 b and the second switching element 52 during molding of the sealing resin body 30 , creating voids in the sealing resin body 30 . can be suppressed. Incidentally, if the intervals between the second switching element 52 and the first switching elements 51a and 51b are substantially equal to each other, the above effect can be obtained regardless of whether the heat dissipation member 40 is exposed or not.

In this embodiment, not only the switching element 50 but also the heat dissipation member 40 and the main terminal 70 are line-symmetrical with respect to the virtual line CL1. Due to the line-symmetrical arrangement, the main current of the first switching element 51a and the main current of the first switching element 51b flow line-symmetrically with respect to the virtual line CL1. For example, in the semiconductor device 20L, as shown in FIG. 13, the lengths of the two current paths are almost equal. One of the current paths is a current path of high potential terminal 71 →first switching element 51a →low potential terminal 72 on the first switching element 51a side. The other one of the current paths is a current path of high potential terminal 71→first switching element 51b→low potential terminal 72 on the first switching element 51b side. Since the inductances of the current paths are substantially equal to each other, it is possible to suppress the AC current from flowing unevenly to one of the first switching elements 51a and 51b. Therefore, unbalance of AC current can be suppressed. The same applies to the semiconductor device 20U. AC current is the current that flows during switching.

(Second embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. This embodiment is characterized by the relationship between the driving and arrangement of the switching elements 50 .

The configuration of the semiconductor device 20 of this embodiment is the same as the semiconductor device 20U (see FIG. 7) shown in the preceding embodiment. The switching element 50 includes a plurality of at least one of the first switching elements 51 and the second switching elements 52 . For example, two first switching elements 51 and one second switching element 52 are included. The arrangement of the switching elements 51, 52 is alternate in the X direction.

In the present embodiment, the control circuit 7 and the driving IC 8 control the first switching element 51 (IGBT 111) and the second switching element 52 (MOSFET 112) so that they are turned on at least during periods different from each other. The control circuit 7 and the drive IC 8 control the switching elements 51 and 52 so that they have periods during which they are individually turned on. As shown in FIG. 14, the second switching element 52 is turned on during the first period, and the first switching element 51 is turned on during the second period. FIG. 14 shows heat generated by the switching element 50 due to ON driving.

The control circuit 7 and the driving IC 8 control the first switching element 51 so that it is off-driven in the first current region and is turned on in the second current region larger than the first current region. The control circuit 7 and the drive IC 8 control the second switching element 52 so that it is ON-driven in the first current region and OFF-driven in the second current region. The first current range is a range below a predetermined first threshold, and the second current range is a range above the first threshold. The first current region is a region with a smaller output current than the second current region, and the second current region is a region with a larger output current than the first current region. The first period is the period in which the output current is within the first current range, and the second period is the period in which the output current within the second current range flows.

In the small current region, the on-resistance of SiC-MOSFET is smaller than that of Si-IGBT. On the other hand, in the large current region, the on-resistance of Si-IGBT is smaller than that of SiC-MOSFET. Therefore, the on-resistance can be reduced in a wide current range by the control described above.

The control circuit 7 and the driving IC 8 control so that the IGBT 111 and the MOSFET 112 have a period in which they are both ON-driven separately from the period in which the IGBT 111 and MOSFET 112 are individually ON-driven. The control circuit 7 and the driving IC 8 control both the IGBT 111 and the MOSFET 112 so as to be ON-driven in the third current region equal to or higher than the second threshold. The second threshold is a current value greater than the first threshold. When the second threshold is provided, the second current range is the range equal to or greater than the first threshold and less than the second threshold. Since both IGBT 111 and MOSFET 112 are driven on during the same period, the output can be further increased.

Thus, the second switching element 52 (MOSFET 112) is ON-driven in the first current region, and the first switching element 51 (IGBT 111) is ON-driven in the second current region. In addition, the switching elements 51 and 52 are turned on in the third current region.

<Summary of Second Embodiment>
In this embodiment, the switching element 50 includes a plurality of at least one of the first switching elements 51 and the second switching elements 52 . As a result, the number of switching elements 50 connected in parallel, particularly the number of switching elements 50 that are turned on during the same period, can be increased, and the output of the semiconductor device 20 can be improved.

Also, the first switching elements 51 and the second switching elements 52 are alternately arranged in the X direction. The first switching element 51 and the second switching element 52 are turned on at least in different periods. As described above, the second switching element 52 is turned on during the first period. In a second period different from the first period, the first switching element 51 is turned on.

A second switching element 52 that is turned on during the first period is arranged between the first switching elements 51 that are turned on during the second period. With this arrangement, as shown in FIG. 14, it is possible to secure a distance between the first switching elements 51 that are turned on during the same period, and to reduce mutual thermal interference between the first switching elements 51 . A semiconductor capable of suppressing an increase in size while improving output compared to a configuration in which switching elements that are ON-driven in the same period are arranged next to each other, such as the order of the first switching element, the first switching element, and the second switching element. Equipment can be provided.

At least the first switching elements 51 and the second switching elements 52 may be arranged alternately. The switching element 50 of this embodiment includes two first switching elements 51 and one second switching element 52 . As described above, the on-resistance of the second switching element (MOSFET 112) is small in the small current region, and the on-resistance of the first switching element 51 (IGBT 111) is small in the large current region.

The second switching element 52 is ON-driven in the first current range, and the first switching element 51 is ON-driven in the second current range larger than the first current range. A single second switching element 52 can cover a small current range, and two first switching elements 51 can cover a large current range over a wide range. Therefore, loss (conduction loss) can be reduced in a wide current range. Moreover, thermal interference can be reduced for the first switching elements 51a and 51b that are turned on in the second current region. Therefore, it is possible to enhance the effect of suppressing an increase in physique while improving the output.

In the present embodiment, an example of switching the driving of the switching element 50 in three current regions was shown, but the present invention is not limited to this example. The switching elements 51 and 52 may be turned on at least in different periods, and various combinations are possible. For example, the switching elements 51 and 52 may not be turned on during the same period. That is, the second switching element 52 may be turned on in a small current range, and the first switching element 51 may be turned on in a larger current range. Also, the second current region may be divided into a region in which one first switching element 51 is ON-driven and a region in which two first switching elements 51 are ON-driven.

Further, by making the energization times of the switching elements 51 and 52 different, specifically by shifting at least one of turn-on and turn-off, the switching elements 51 and 52 may be provided with a period of ON drive and a period of ON drive individually. good. For example, the energization time of the first switching element 51 is set shorter than the energization time of the second switching element 52 in a small current region, and the energization time of the second switching element 52 is set to be shorter than the energization time of the first switching element 51 in a large current region. may be shorter than

The configuration shown in this embodiment can be combined with the configuration described in the previous embodiment. For example, it may be combined with a configuration in which part of the heat radiating member 40 is exposed from the sealing resin body 30 , or may be combined with a configuration in which the entire heat radiating member 40 is covered with the sealing resin body 30 . A configuration using different semiconductor devices 20U and 20L for the upper arm 11U and the lower arm 11L may be combined. The upper arm 11U and the lower arm 11L may be combined with a configuration using the semiconductor device 20 having a common structure. At least one of the heat dissipation member 40, the switching element 50, and the main terminal 70 may be arranged line-symmetrically with respect to the virtual line CL1.

(Third Embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. This embodiment is characterized by the arrangement of the second main terminals.

FIG. 15 shows a semiconductor device 20 of this embodiment. The configuration of this semiconductor device 20 is substantially the same as the semiconductor device 20U (see FIG. 7) shown in the preceding embodiment. The switching element 50 includes two first switching elements 51 and one second switching element 52 . The main terminals 70 include one high potential terminal 71 and two low potential terminals 72 . The high potential terminal 71 is the first main terminal arranged on the imaginary line CL1, and the low potential terminal 72 is the second main terminal. The center of the width of high-potential terminal 71 is located on imaginary line CL1.

A virtual line CL2 shown in FIG. 15 is a line extending in the Y direction passing through the elemental centers of the first switching elements 51a and 51b. The virtual line CL1 passes through the center positions of the two virtual lines CL2. One of the low potential terminals 72 is arranged on the virtual line CL2 on the side of the first switching element 51a, and the other one is arranged on the virtual line CL2 on the side of the first switching element 51b. The center of the width of the low-potential terminals 72 is positioned on the imaginary line CL2.

<Summary of Third Embodiment>
The main terminals of this embodiment include one first main terminal and two second main terminals. The first main terminal is arranged on the virtual line CL1. The second main terminal is arranged on the virtual line CL2. FIG. 16 shows current paths. For the sake of convenience, FIG. 16 omits a portion in the X direction so as to include one of the first switching elements 51 . In FIG. 16, arrows indicate the flow of the main current at predetermined timings. In FIG. 16, a low-potential terminal 72r (second main terminal), which is a reference example, is indicated by a chain double-dashed line.

A high-potential terminal 71, which is a first main terminal, is arranged on the virtual line CL1. The low potential terminal 72, which is the second main terminal, is arranged on the virtual line CL2. Therefore, a current flows as indicated by solid line arrows. A low-potential terminal 72r, which is a reference example, is arranged outside the virtual line CL2 at a position that does not overlap with the virtual line CL2. Therefore, a current flows as indicated by the two-dot chain line arrow. According to the arrangement of the low potential terminals 72 of this embodiment, the current paths of the switching elements 51 and 52 can be shortened compared to the reference example. Also, current loops formed between the high potential terminal 71, the switching elements 51 and 52, and the low potential terminal 72 can be made smaller than in the reference example. Therefore, the inductance can be reduced as compared with the reference example. For example, switching losses can be reduced.

In the present embodiment, an example in which the second main terminals are arranged on the imaginary line CL2 has been shown, but the present invention is not limited to this. The second main terminal may be arranged at a position not overlapping with the virtual line CL2 and inside the virtual line CL2. The second main terminal arranged in this way is indicated by a dashed line in FIG. 16 as the low potential terminal 72a. According to this, a current flows as indicated by the dashed arrow. The current path of the second switching element 52 can be shortened as compared with the reference example described above. Also, the current loops of the switching elements 51 and 52 can be made smaller than in the reference example. Therefore, the inductance can be reduced as compared with the reference example.

Even if the low potential terminal 72 is positioned on the imaginary line CL2, if the center of the width of the low potential terminal 72 is outside the imaginary line CL2, the center of the width of the low potential terminal 72 is positioned on the imaginary line CL2. The current paths of switching elements 51 and 52 are longer than in the configuration. Also, the current loop becomes large. Therefore, the low-potential terminal 72 (second main terminal) should be arranged so that the center of the width is located on the virtual line CL2 or inside the virtual line CL2, that is, close to the virtual line CL1.

In this embodiment, the arrangement of each of the heat dissipation member 40, the switching element 50, and the main terminal 70 is line-symmetrical with respect to the virtual line CL1. Thereby, the imbalance of AC current can be suppressed as in the preceding embodiment. According to the present embodiment, it is possible to reduce switching loss while suppressing current imbalance.

The configuration shown in this embodiment can be combined with the configuration described in the previous embodiment. For example, it may be combined with a configuration in which part of the heat radiating member 40 is exposed from the sealing resin body 30 , or may be combined with a configuration in which the entire heat radiating member 40 is covered with the sealing resin body 30 . A configuration using different semiconductor devices 20U and 20L for the upper arm 11U and the lower arm 11L may be combined. For example, in the case of the semiconductor device 20L shown in FIG. 4, the low potential terminal 72 corresponds to the first main terminal and the high potential terminal 71 corresponds to the second main terminal. The upper arm 11U and the lower arm 11L may be combined with a configuration using the semiconductor device 20 having a common structure.

The driving of the switching elements 51 and 52 is not particularly limited. A combination with a configuration in which the switching elements 51 and 52 are on-driven at least in different periods is possible. In this case, mutual thermal interference between the first switching elements 51 can be reduced.

(Fourth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. This embodiment is characterized by the dimensional relationship between the switching elements 51 and 52 .

FIG. 17 shows a semiconductor device 20 of this embodiment. The switching element 50 includes a plurality of at least one of the first switching elements 51 and the second switching elements 52 . The configuration of the semiconductor device 20 is substantially the same as the semiconductor device 20U (see FIG. 7) shown in the preceding embodiment. The semiconductor device 20 includes two first switching elements 51 and one second switching element 52 . The arrangement of the switching elements 51, 52 is alternate in the X direction.

The substrate area of the second switching element 52 is smaller than that of the first switching element 51 . In the first switching element 51, the length in the X direction is LX1, and the length in the Y direction is LY1. The ratio R1 of the length in the Y direction to the length in the X direction is LY1/LX1. In the second switching element 52, the length in the X direction is LX2, and the length in the Y direction is LY2. The ratio R2 of the length in the Y direction to the length in the X direction is LY2/LX2. The second switching element 52 has a substantially rectangular planar shape whose longitudinal direction is the Y direction.

The length LX2 is shorter than the length LX1 (LX2<LX1). The ratio R2 is greater than the ratio R1 (R2>R1). Further, length LY2 is approximately equal to length LY1. The positions of both ends in the Y direction are substantially the same between the first switching element 51 and the second switching element 52 .

<Summary of the fourth embodiment>
Next, based on FIGS. 18 to 20, effects due to the above-described dimensional relationships will be described. 18 to 20 show a comparison between this embodiment and a reference example. In the reference example, elements that are the same as or related to elements of this embodiment are indicated by adding r to the end of the reference numerals of this embodiment. In this embodiment and the reference example, the dimensions of the first switching element are made equal to each other. Also, the intervals between the first switching element and the second switching element are made equal to each other. 18 to 20 illustrate the semiconductor device in a simplified manner.

In FIG. 18, the uppermost stage is this embodiment, and the lower two stages are reference examples. In Reference Example 1, the length of the second switching element 52r is shorter than that of the first switching element 51r in the X direction. The length of the second switching element 52r is equal to that of the second switching element 52 in the X direction. The length of the second switching element 52r is shorter than that of the second switching element 52 in the Y direction. In Reference Example 1, the length ratio relationship is R2≦R1.

In this embodiment, the length ratio relationship is R2>R1. Therefore, the substrate area of the second switching element 52 is larger than that of the second switching element 52r. As a result, the active area of the element is also larger than that of the first reference example. Therefore, according to the present embodiment, it is possible to improve the output over that of Reference Example 1 while keeping the physical size in the X direction equal to that of Reference Example 1.

In Reference Example 2, the substrate area of the second switching element 52 r is equal to that of the second switching element 52 . The length of the second switching element 52r is longer than that of the second switching element 52 in the X direction. In Reference Example 2, the length ratio relationship is R2≦R1. In Reference Example 2, the substrate area of the second switching element 52r is increased by setting the X direction, which is the alignment direction, as the longitudinal direction.

In the present embodiment, the length ratio relationship is R2>R1, and the length of the second switching element 52 is shorter than that of the second switching element 52r in the X direction. Since the second switching element 52 is short, the physical size in the X direction is smaller than that of the second reference example. Therefore, according to the present embodiment, the size in the X direction can be made smaller than that of Reference Example 1 while the output is the same as that of Reference Example 2.

As described above, according to the semiconductor device 20 of the present embodiment, it is possible to suppress an increase in size while improving the output. Particularly in this embodiment, the length LY2 of the second switching element 52 is approximately equal to the length LY1 of the first switching element 51 . Compared to a configuration that satisfies LY2<LY1, it is possible to increase the substrate area of the second switching element 52 and further improve the output. Also, the positions of both ends in the Y direction are substantially the same between the first switching element 51 and the second switching element 52 . As a result, the output can be improved while suppressing an increase in the size of the semiconductor device 20 in the Y direction.

In FIG. 19, the upper stage is the present embodiment, and the lower stage is the reference example. The configuration of the second switching element 52r shown in FIG. 19 is the same as that of Reference Example 1 shown in FIG. The length ratio relationship is R2≦R1. In the Y direction, the positions of the ends on the signal terminal 80r side are substantially the same between the first switching element 51r and the second switching element 52r. The second switching element 52r is arranged closer to the signal terminal 80r in the Y direction. Therefore, as indicated by the dashed-dotted arrow, the main current path of the second switching element 52r is long.

In this embodiment, the length ratio relationship is R2>R1. The arrangement of the second switching element 52 is closer to the main terminal 70 than in the reference example. Thereby, the current path of the second switching element 52 can be shortened. Therefore, switching loss can be reduced.

Although illustration is omitted, as a reference example, the positions of the ends on the main terminal 70r side in the Y direction are substantially aligned between the first switching element 51r and the second switching element 52r. A configuration in which it is arranged near the main terminal 70r is also conceivable. In this case, the distance between the second switching element 52r and the second signal terminal 82r is increased. Compared to this reference example, the second switching element 52 of this embodiment is positioned closer to the second signal terminal 82 . Therefore, it is advantageous for high-speed switching of the second switching element 52 (MOSFET 112).

FIG. 20 is a simplified view of a cross section taken along line XX-XX of FIG. 17. FIG. In FIG. 20, the upper stage is the present embodiment, and the lower stage is the reference example. In the reference example shown in FIG. 20, the second switching element 52r has the same arrangement as in reference example 1 shown in FIG. The length ratio relationship is R2≦R1. Therefore, the substrate area of the second switching element 52r is small. Also, the cross-sectional area of the terminal 60r is small.

In this embodiment, the length ratio relationship is R2>R1. Thereby, the substrate area of the second switching element 52 is larger than that of the reference example. Also, the cross-sectional area of the terminal 60 is larger than that of the reference example. Therefore, the current density can be reduced compared to the reference example, as indicated by the dashed-dotted arrow. For example, the electromigration effect increases as the current flowing increases. According to this embodiment, the life of the bonding material 90 can be particularly improved by reducing the current density.

Further, as shown in FIG. 20, since the substrate area of the second switching element 52r of the reference example is small, the second switching element 52r and the terminal 60r occupy a small proportion of the opposing region of the heat dissipation members 41r and 42r. That is, many sealing resin bodies 30r enter the opposing region. The sealing resin body 30r has an intermediate portion 30er sandwiched between the heat dissipation members 41r and 42r. A portion of the intervening portion 30er is adjacent to the second switching element 52r in the Y direction. On the other hand, in the present embodiment, the substrate area of the second switching element 52 is larger than that of the reference example, so the intervening portion 30e can be made smaller than that of the reference example. A part of the intervening portion 30er shown in the reference example is replaced with the second switching element 52 and the terminal 60 . Therefore, heat dissipation can be improved.

Note that the length LY2 may be shorter than the length LY1 as long as the length ratio satisfies the relationship of R2>R1. Since the relationship of R2>R1 is satisfied, the output can be improved compared to the configuration where R2≦R1. If the length LY2 is made longer than the length LY1, the output can be further improved, but the physical size in the Y direction increases. Also, when the positions of both ends of the switching elements 51 and 52 are shifted in the Y direction, the size in the Y direction increases. Therefore, as shown in FIG. 17, it is preferable that the length LY2 is approximately equal to the length LY1, and the positions of both ends in the Y direction are approximately the same between the first switching element 51 and the second switching element 52. .

The numbers of the first switching elements 51 and the second switching elements 52 are not particularly limited. Any number can be used as long as it can be arranged alternately.

The configuration shown in this embodiment can be combined with the configuration described in the previous embodiment. For example, it may be combined with a configuration in which part of the heat radiating member 40 is exposed from the sealing resin body 30 , or may be combined with a configuration in which the entire heat radiating member 40 is covered with the sealing resin body 30 . A configuration using different semiconductor devices 20U and 20L for the upper arm 11U and the lower arm 11L may be combined. The upper arm 11U and the lower arm 11L may be combined with a configuration using the semiconductor device 20 having a common structure. The driving of the switching elements 51 and 52 is not particularly limited.

(Fifth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. This embodiment is characterized by the positional relationship between the switching elements 51 and 52 .

In a configuration in which one second switching element 52 is arranged between two first switching elements 51, the intervals between the second switching element 52 and the first switching elements 51a and 51b may be different from each other. .

FIG. 21 shows a semiconductor device 20 of this embodiment. The configuration of this semiconductor device 20 is substantially the same as the semiconductor device 20 (see FIG. 15) shown in the preceding embodiment. As shown in the preceding embodiment, in the cooling structure, the first switching element 51a is on the upstream side of the coolant, and the first switching element 51b is on the downstream side. The first switching elements 51a and 51b are turned on during the same period. In this embodiment, the arrangement of the second switching element 52 is closer to the first switching element 51a than to the first switching element 51b.

<Summary of the fifth embodiment>
According to the arrangement shown in FIG. 21, the heat of the second switching element 52 is easily transferred to the first switching element 51a which is cooled more. Thereby, the temperature difference between the first switching elements 51a and 51b can be reduced. Therefore, the difference between the on-resistances of the first switching elements 51a and 51b is reduced, and the imbalance of the DC current can be suppressed.

In addition, when the first switching element 51a and the first switching element 51b have different ON-drive periods together with the second switching element 52, different intervals may be applied. For example, the first switching element 51a is more frequently turned on together with the second switching element 52 than the first switching element 51b. As an example, the switching elements 51a and 52 are turned on in the A current region, and the switching elements 51a, 51b and 52 are turned on in the B current region larger than the A region. As another example, the switching elements 51a and 52 are turned on in the A current region, and the switching elements 51a and 51b are turned on in the B current region larger than the A region.

By arranging the second switching element 52 near the first switching element 51a, the current paths of the first switching element 51a and the second switching element 52, which are frequently turned on in the same period, become closer to each other. Therefore, the inductance of the current path can be reduced. If the first switching element 51b is more frequently turned on together with the second switching element 52, the second switching element 52 may be placed closer to the first switching element 51b.

<Modification>
The position in the Y direction of the second switching element 52 arranged between the two first switching elements 51 can be changed in various ways.

For example, the second switching element 52 may be arranged such that the centers of the active regions of the first switching element 51 and the second switching element 52 are shifted in the Y direction. In the modification shown in FIG. 22, a temperature sensor 53 (temperature-sensitive diode) is provided substantially in the center of the active area, as in the previous embodiment. The center of the active region, that is, the temperature sensor 53 is shifted in the Y direction between the first switching element 51 and the second switching element 52 . The second switching element 52 is arranged closer to the main terminal 71 in the Y direction. The configuration of the semiconductor device 20 shown in FIG. 22 is the same as that of the previous embodiment (see FIG. 15) except for the arrangement of the second switching element 52. In FIG. In FIG. 22, the bonding wires 91 are omitted for convenience.

As described above, in the device, the maximum heat generation point occurs near the center of the active region. By shifting the center of the active region between the first switching element 51 and the second switching element 52, the distance between the centers becomes longer. As a result, mutual thermal interference can be suppressed in the switching elements 51 and 52 that are turned on during the same period. Also, since the second switching element 52 is close to the main terminal 70, the inductance of the main circuit can be reduced.

Also in the configuration shown in the previous embodiment (for example, see FIGS. 4 and 7), the centers of the active regions of the first switching element 51 and the second switching element 52 are shifted in the Y direction. Therefore, an effect equivalent to that of the configuration shown in FIG. 22 can be obtained. In the preceding embodiment, the positions of the ends of the switching elements 51 and 52 on the signal terminal 80 side are substantially aligned in the Y direction. For example, the gate wiring can be shortened, which is advantageous for high-speed switching of the second switching element 52 (MOSFET 112).

In the modification shown in FIG. 23, the second switching element 52 is arranged between the two switching elements 51a and 51b in the X direction and between the two switching elements 51a and 51b in the Y direction. . The temperature sensors 53 of the switching elements 50 are offset from each other in the Y direction. In FIG. 23 , the temperature sensor 53 of the first switching element 51 a is arranged closest to the main terminal 70 , and the temperature sensor 53 of the first switching element 51 b is arranged furthest from the main terminal 70 . That is, in the three switching elements 50, the positions of the highest heat generating points are shifted from each other in the Y direction perpendicular to the flow direction of the refrigerant. Therefore, it is possible to effectively cool each of the switching elements 51 and 52 that are ON-driven during the same period.

In the example shown in FIG. 23, in the adjacent switching elements 50, the upstream non-active region faces the downstream active region in the X direction. For example, the formation region of pad 51p in first switching element 51a faces the active region of second switching element 52 . Also, the formation region of the pad 52p in the second switching element 52 faces the active region of the first switching element 51b. As a result, in the adjacent switching elements 50, an increase in size in the Y direction can be suppressed while suppressing thermal interference. The configuration of the semiconductor device 20 shown in FIG. 23 is the same as that shown in FIG.

The switching elements 51 and 52 of the modification shown in FIG. 24 are not turned on during the same period. The centers of the active regions of the switching elements 51 and 52 are substantially the same in the Y direction. Since the switching elements 51 and 52 are not turned on at the same time, there is almost no mutual thermal influence. Therefore, the second switching element 52 can be arranged at the center position of the heat dissipation member 40 . This arrangement improves heat dissipation and suppresses the temperature rise of the second switching element 52 . Therefore, an increase in the ON resistance of the second switching element 52 (MOSFET 112) can be suppressed. The configuration of the semiconductor device 20 shown in FIG. 24 is the same as that shown in FIG.

Also in the configuration shown in the preceding embodiment (see FIG. 17), the centers of the active regions of the switching elements 51 and 52 are at substantially the same position in the Y direction. Therefore, in a configuration in which the switching elements 51 and 52 are not turned on in the same period, an effect equivalent to that of the configuration shown in FIG. 24 can be obtained.

The configuration shown in this embodiment can be combined with the configuration described in the preceding embodiment. For example, it may be combined with a configuration in which part of the heat radiating member 40 is exposed from the sealing resin body 30 , or may be combined with a configuration in which the entire heat radiating member 40 is covered with the sealing resin body 30 . A configuration using different semiconductor devices 20U and 20L for the upper arm 11U and the lower arm 11L may be combined. The upper arm 11U and the lower arm 11L may be combined with a configuration using the semiconductor device 20 having a common structure.

(Sixth embodiment)
This embodiment is a modification based on the preceding embodiment, and the description of the preceding embodiment can be used. This embodiment is characterized by the arrangement of the signal terminals 80 .

FIG. 25 shows a semiconductor device 20 of this embodiment. The switching element 50 includes a plurality of at least one of the first switching elements 51 and the second switching elements 52 . The configuration of the semiconductor device 20 is substantially the same as the semiconductor device 20U (see FIG. 7) shown in the preceding embodiment. The switching element 50 includes two first switching elements 51 and one second switching element 52 . The arrangement of the switching elements 51, 52 is alternate in the X direction. In FIG. 25, the switching element 50 and the signal terminal 80 among the elements in the sealing resin body 30 are illustrated with solid lines for convenience. Moreover, the 1st heat radiating member 41 is shown with the broken line among the heat radiating members 40. As shown in FIG.

Switching elements 51 and 52 have corresponding pads 51p and 52p as described above. The flow direction of the coolant substantially coincides with the X direction, which is the direction in which the switching elements 50 are arranged. The pads 51p are provided in the order of reference potential pad 51psp, current sense pad 51psc, gate pad 51pg, and temperature sense pads 51pa and 51pc from the upstream side. The pads 52p are provided in the order of reference potential pad 52psp, current sense pad 52psc, gate pad 52pg, and temperature sense pads 52pa and 52pc from the upstream side. Pads 51p and 52p are arranged in the same order.

Reference potential pads 51psp and 52psp are pads for detecting a reference potential for the gate drive signal. Reference potential pad 51psp is a pad for detecting an emitter potential and is also called a Kelvin emitter pad. Reference potential pad 52psp is a pad for detecting a source potential and is also called a Kelvin source pad.

Current sense pads 51psc and 52psc are pads for detecting the current flowing through the sense elements formed in switching elements 51 and 52, respectively. In the first switching element 51, the structure of the sense element is the same as that of the IGBT 111 formed in the active region. The sense element is formed in a sense region (for example, about 1/1000) smaller in area than the active region, and a current proportional to the IGBT 111 flows. In the second switching element 52, the configuration of the sense element is the same as the MOSFET 112 formed in the active region. A sense element is formed in a sense region that is smaller in area than the active region, and a current proportional to MOSFET 112 flows. Current sense pads 51psc and 52psc are pads for detecting a current correlated with the main current.

The gate pads 51pg and 52pg are pads to which gate drive signals are input. The temperature sense pads 51pa and 51pc are pads for detecting the substrate temperature of the first switching element 51 . The temperature sense pads 51pa and 51pc are electrically connected to the temperature sensor 53 formed in the first switching element 51. As shown in FIG. The temperature sense pads 52pa, 52pc are pads for detecting the substrate temperature of the second switching element 52. FIG. The temperature sense pads 52pa, 52pc are electrically connected to the temperature sensor 53 formed on the second switching element 52. As shown in FIG. The temperature sensing pads 51pa and 52pa are pads for detecting the anode potential of the temperature sensing diode, which is the temperature sensor 53 . Temperature sense pads 51pc and 52pc are pads for detecting the cathode potential.

Among the plurality of switching elements 50, the pad 51p of the first switching element 51b and the pad 52p of the second switching element 52 positioned most downstream are connected to the signal terminal 80, respectively. On the other hand, the reference potential pad 51psp, the current sense pad 51psc, and the gate pad 51pg among the pads 51p of the first switching element 51a positioned most upstream are connected to the corresponding signal terminals 80 . Temperature sense pads 51pa and 51pc are not provided with corresponding signal terminals 80 . Thus, the signal terminals 80 are thinned out. The semiconductor device 20 has 13 signal terminals 80 for 15 pads 51p and 52p.

The drive IC 8 has a determination circuit (not shown). The determination circuit determines whether or not an overcurrent is occurring in the switching element 50 based on signals obtained via the current sense pads 51psc, 52psc and the signal terminal 80, for example. The determination circuit determines whether or not the switching element 50 is in an overheated state based on the signal obtained through the temperature sense pads 51pa, 51pc, 52pa, 52pc and the signal terminal 80. FIG. The drive IC 8 outputs a drive signal according to the determination result. It should be noted that the determination circuit may be provided in the control circuit 7 as well.

<Summary of the sixth embodiment>
In this embodiment, the switching element 50 includes a plurality of at least one of the switching elements 51 and 52 . Specifically, it includes two first switching elements 51 and one second switching element 52 . Therefore, the output of the semiconductor device 20 can be improved as compared with the configuration including the switching elements 51 and 52 one by one.

In addition, due to the alternate arrangement, a plurality of first switching elements 51 having the same type of substrate as the first switching element 51b positioned at the most downstream are included. The plurality of first switching elements 51 have a period during which they are simultaneously turned on. The currents flowing through the first switching elements 51 are substantially the same, and the losses are substantially the same. On the other hand, the temperature of the coolant rises due to heat exchange with the switching element 50, lowers upstream and higher downstream. Therefore, the thermal resistance increases toward the downstream side, and the substrate temperature rises. The temperature sense pads 51pa and 51pc of the first switching element 51b on the most downstream side are connected to the signal terminal 80. As shown in FIG. Therefore, based on the substrate temperature of the first switching element 51b, it is possible to protect the first switching element 51a on the upstream side from overheating.

Further, since the signal terminals 80 corresponding to the temperature sense pads 51pa and 51pc are not provided for the first switching element 51a on the upstream side, the total number of signal terminals 80 provided in the semiconductor device 20 can be reduced. As described above, the number of signal terminals 80 can be reduced while improving the output. It should be noted that the effect can be obtained whether there is a period during which the switching elements 51 and 52 are simultaneously turned on or when there is no period during which the switching elements 51 and 52 are simultaneously turned on.

<Modification>
The arrangement order of the pads 51p and 52p is not limited to the above example. The arrangement order of the temperature sense pads 51pa and 51pc may be reversed. Similarly, the order of arrangement of the temperature sense pads 52pa and 52pc may be reversed.

In the modification shown in FIG. 26, for example, temperature sense pads 51pa and 51pc are upstream of pad 51p. Specifically, the temperature sense pad 51pc and the temperature sense pad 51pa are provided in this order from the upstream side. Pads 52p are also arranged in a similar manner. According to this configuration, in the first switching element 51a, the bonding wire 91 connecting the remaining pads 51p other than the temperature sense pads 51pa and 51pc and the signal terminal 80 becomes longer. According to the configuration shown in FIG. 25, the bonding wires 91 are shorter than the configuration shown in FIG. As a result, it is possible to reduce wire flow (displacement) due to the flow of the resin when molding the encapsulating resin body 30 . Therefore, deterioration in connection reliability of the bonding wires 91 can be suppressed.

The number of switching elements 51 and 52 is not limited to the above example. For example, switching element 50 may include three first switching elements 51 and two second switching elements 52 . In this case, the signal terminals 80 corresponding to the temperature sense pads 51pa and 51pc may be provided only on the most downstream side of the three first switching elements 51 . Alternatively, the signal terminals 80 corresponding to the temperature sense pads 51pa and 51pc may be provided on the two downstream sides, and the signal terminals 80 corresponding to the temperature sense pads 51pa and 51pc may not be provided on the most upstream side.

Although an example in which the first switching element 51 is the most downstream has been shown, it is not limited to this. The second switching element 52 may be the most downstream. When the switching element 50 includes one first switching element 51 and two second switching elements 52 , the most downstream pad 52 p is connected to the signal terminal 80 . Of the most upstream pads 52p, the reference potential pad 52psp, the current sense pad 52psc, and the gate pad 51pg are connected to the signal terminal 80. FIG. Also, the signal terminals 80 of the temperature sensing pads 52pa and 52pc are omitted.

That is, among a plurality of switching elements having the same substrate type as the most downstream switching element, only some of the switching elements including at least the most downstream switching element are provided with signal terminals corresponding to the temperature sense pads. Then, the switching elements on the upstream side of some of them may have a configuration in which no signal terminal corresponding to the temperature sensing pad is provided.

27 differs from FIG. 25 in the arrangement of pads 52p and the number of signal terminals 80. FIG. The arrangement order of the pads 51p is the same as in FIG. The pads 52p are provided in the order of temperature sense pads 52pc and 52pa, gate pad 52pg, current sense pad 52psc, and reference potential pad 52psp from the upstream side. That is, the reference potential pad 51psp is provided most upstream in the first switching element 51 and the reference potential pad 52psp is provided most downstream in the second switching element 52 .

The reference potential pad 51psp of the first switching element 51b and the reference potential pad 52psp of the second switching element 52 are connected to the same signal terminal 80 with each other. By sharing the signal terminal 80 for the adjacent reference potential pads 51psp and 52psp in this manner, the number of signal terminals 80 can be reduced regardless of the drive period of the switching elements 51 and 52 .

Furthermore, in FIG. 27, the signal terminal 80 corresponding to the current sense pad 52psc is not provided. The substrate area of the second switching element 52 is smaller than that of the first switching element 51 . As described above, the on-resistance of the MOSFET 112 increases as the temperature increases. Therefore, the ON resistance of the first switching element 51 is smaller than that of the second switching element 52 in a high temperature range. Therefore, even if the switching elements 51 and 52 are turned on at the same time, current tends to flow through the first switching element 51 in a high temperature range. Therefore, the signal terminal 80 of the current sense pad 52psc can be omitted. It should be noted that the signal terminal 80 of the current sense pad 52psc can be omitted even when the second switching element 52 is ON-driven only in the small current region. As described above, in the configuration shown in FIG. 27, the number of signal terminals 80 is eleven.

In FIG. 27, the signal terminals 80 of the reference potential pads 51psp and 52psp are shared by the first switching element 51b and the second switching element 52 on the downstream side, but the present invention is not limited to this. When the reference potential pad 51psp is provided at the most downstream side and the reference potential pad 52psp is provided at the most upstream side, the switching elements 51a and 52 can share the signal terminal 80 of the reference potential pads 51psp and 52psp.

The modification shown in FIG. 28 has a configuration in which the signal terminal 80 corresponding to the current sense pad 51psc of the first switching element 51a is omitted from the configuration shown in FIG. Due to the coolant, the substrate temperature of the first switching element 51a on the upstream side is lower than that of the first switching element 51b on the downstream side. The on-resistance of the IGBT 111 decreases as the substrate temperature increases. Therefore, in a high temperature range, current tends to flow through the first switching element 51b. Therefore, the signal terminal 80 corresponding to the upstream current sense pad 51psc can be omitted. As described above, in the configuration shown in FIG. 28, the number of signal terminals 80 is ten.

In the modification shown in FIG. 29, the arrangement order of pads 51p and 52p is the same as in FIG. No signal terminal 80 is provided for the temperature sense pads 52pa, 52pc and the current sense pad 52psc of the second switching element 52 . Other pads 51 p and 52 p are connected to signal terminals 80 . 27, the reference potential pad 51psp of the first switching element 51b and the reference potential pad 52psp of the second switching element 52 are connected to the same signal terminal 80 as each other. Thereby, the number of signal terminals 80 can be reduced.

The switching elements 51 and 52 may be turned on in different periods and may not be turned on in the same period. The second switching element 52 is ON-driven in the first current region, and the first switching element 51 is ON-driven in the second current region. There is no setting for the third current range. Since the second switching element 52 is not turned on in a large current region, the signal terminal 80 corresponding to the current sense pad 52psc can be omitted. Further, since the second switching element 52 is ON-driven only in a small current range, the signal terminals 80 corresponding to the temperature sensing pads 52pa and 52pc can be omitted. As described above, the number of signal terminals 80 can be reduced to 11 as shown in FIG.

Also, the three switching elements 50 may satisfy the relationship of electrical characteristics shown below. For example, the gate threshold voltage Vth satisfies the relationship of first switching element 51a>first switching element 51b. The on-voltage Von(RT) at room temperature satisfies the relationship of first switching element 51 a >first switching element 51 b >second switching element 52 . The on-voltage Von(HT) at a high temperature (for example, 100° C.) satisfies the relationship of second switching element 52>first switching element 51a>first switching element 51b. In this case, the maximum current and the maximum temperature can be detected by monitoring the first switching element 51b. Therefore, the signal terminal 80 corresponding to the current sense pad 52psc can be omitted. Also, the signal terminals 80 corresponding to the temperature sensing pads 52pa and 52pc can be omitted. As described above, the number of signal terminals 80 can be reduced to 11 as shown in FIG.

The modification shown in FIG. 30 has a configuration in which the signal terminal 80 corresponding to the current sense pad 51psc of the first switching element 51a is omitted from the configuration shown in FIG. As in the modification shown in FIG. 28, the coolant lowers the substrate temperature of the first switching element 51a on the upstream side, so that the signal terminal 80 corresponding to the current sense pad 51psc on the upstream side can be omitted. As described above, in the configuration shown in FIG. 30, the number of signal terminals 80 is ten.

29 and 30 and the configuration shown in FIG. 25 can be combined. For example, the modification shown in FIG. 31 has a configuration in which signal terminals 80 of temperature sense pads 51pa and 51pc of first switching element 51a are omitted from FIG. As a result, the number of signal terminals 80 is nine.

In the modification shown in FIG. 32, the arrangement order of pads 51p and 52p is the same as in FIG. No signal terminal 80 is provided for reference potential pads 51psp and 52psp of switching elements 51a, 51b and 52, respectively. Other pads 51 p and 52 p are connected to signal terminals 80 . The potentials of the reference potential pads 51psp and 52psp are the same as the potential of the low potential terminal 72 . By sharing the low potential terminal 72, the signal terminal 80 corresponding to the reference potential pads 51psp and 52psp can be omitted. As described above, in the configuration shown in FIG. 32, the number of signal terminals 80 is twelve.

In the case of high-speed switching of the second switching element 52 (MOSFET 112), a signal terminal 80 corresponding to the reference potential pad 52psp may be added to FIG. 32 as in the modification shown in FIG. . As a result, the inductance is reduced as compared with the configuration shown in FIG. 32, and high-speed switching of the second switching element 52 becomes possible. In the configuration shown in FIG. 33, the number of signal terminals 80 is thirteen.

The configuration shown in this embodiment can be combined with the preceding embodiment. For example, it may be combined with a configuration in which part of the heat radiating member 40 is exposed from the sealing resin body 30 , or may be combined with a configuration in which the entire heat radiating member 40 is covered with the sealing resin body 30 . A configuration using different semiconductor devices 20U and 20L for the upper arm 11U and the lower arm 11L may be combined. The upper arm 11U and the lower arm 11L may be combined with a configuration using the semiconductor device 20 having a common structure. At least one of the heat dissipation member 40, the switching element 50, and the main terminal 70 may be arranged line-symmetrically with respect to the virtual line CL1. A second switching element 52 whose longitudinal direction is the Y direction may be employed.

(Other embodiments)
The disclosure in this specification, drawings, etc. is not limited to the illustrated embodiments. The disclosure encompasses the illustrated embodiments and variations thereon by those skilled in the art. For example, the disclosure is not limited to the combinations of parts and/or elements shown in the embodiments. The disclosure can be implemented in various combinations. The disclosure can have additional parts that can be added to the embodiments. The disclosure encompasses omitting parts and/or elements of the embodiments. The disclosure encompasses permutations or combinations of parts and/or elements between one embodiment and another. The disclosed technical scope is not limited to the description of the embodiments. The disclosed technical scope is indicated by the description of the claims, and should be understood to include all modifications within the meaning and range of equivalents to the description of the claims.

The disclosure in the specification, drawings, etc. is not limited by the description in the claims. The disclosure in the specification, drawings, etc. encompasses the technical ideas described in the claims, and further extends to technical ideas that are more diverse and broader than the technical ideas described in the claims. Therefore, various technical ideas can be extracted from the disclosure of the specification, drawings, etc., without being bound by the scope of claims.

The control circuit 7 and drive IC 8 are provided by a control system including at least one computer. The control system includes at least one processor in hardware (hardware processor). A hardware processor may be provided by (i), (ii), or (iii) below.

(i) a hardware processor may be a hardware logic circuit; In this case, the computer is provided by digital circuits containing a large number of programmed logic units (gate circuits). A digital circuit may include a memory that stores programs and/or data. Computers may be provided by analog circuits. Computers may be provided by a combination of digital and analog circuits.

(ii) the hardware processor may be at least one processor core executing a program stored in at least one memory; In this case, the computer is provided by at least one memory and at least one processor core. A processor core is called a CPU, for example. Memory is also referred to as storage medium. A memory is a non-transitory and tangible storage medium that non-temporarily stores "programs and/or data" readable by a processor.

(iii) The hardware processor may be a combination of (i) above and (ii) above. (i) and (ii) are located on different chips or on a common chip.

That is, the means and/or functions provided by the control circuit 7 and the drive IC 8 can be provided by hardware only, software only, or a combination thereof.

The thickness relationship between the switching elements 51 and 52 is not limited to the above example. For example, the switching elements 51 and 52 may have substantially the same thickness.

Although an example in which the semiconductor device 20 includes the terminal 60 is shown, the present invention is not limited to this. For example, the mounting surface 42a of the second heat radiating member 42 may be provided with a convex portion so that the terminal 60 is not provided.

Although an example in which an RC-IGBT is formed in the first switching element 51 has been shown, the present invention is not limited to this. A configuration in which the IGBT 111 is formed in the first switching element 51 and the diode 113 is formed in a chip separate from the switching element 50 may be employed.

The semiconductor device 20 is not limited to the double-sided heat dissipation structure. It can also be applied to a semiconductor device having a single-sided heat dissipation structure in which one heat dissipation member 40 is provided and one surface of the heat dissipation member 40 is connected to the high potential side main electrodes or the low potential side main electrodes of the switching elements 51 and 52 . It is possible. In the case of the single-sided heat dissipation structure, the mounting surface and/or the back surface of the switching elements 51 and 52 in the heat dissipation member should be exposed.

As the semiconductor device 20, an example of a 1-in-1 package in which elements forming one arm are packaged is shown, but the semiconductor device 20 is not limited to this. It can also be applied to a configuration having a plurality of arms in which the switching elements 51 and 52 are connected in parallel to the heat radiating member. For example, it can be applied to a 2-in-1 package in which an element constituting the upper arm 11U and an element constituting the lower arm 11L are packaged.

DESCRIPTION OF SYMBOLS 1... Drive system, 2... DC power supply, 3... Motor generator, 4... Power converter, 5... Smoothing capacitor, 6... Inverter, 7... Control circuit, 8... Drive IC, 9... P line, 10... N line, REFERENCE SIGNS LIST 11 upper and lower arm circuits 11U upper arm 11L lower arm 111 IGBT 112 MOSFET 113 diode 12 output line 20, 20U, 20L semiconductor device 30 sealing resin body 30a 1 surface 30b Back surface 30c, 30d Side surface 30e Interposed portion 40 Heat dissipation member 41 First heat dissipation member 41a Mounting surface 41b Heat dissipation surface 41c Concave portion 41d Intersection region 41e Overlapping area 41f Non-overlapping area 42 Second heat dissipation member 42a Mounting surface 42b Heat dissipation surface 42d Crossing area 42e Overlapping area 42f Non-overlapping area 50 Switching element 51, 51a, 51b first switching element 51c collector electrode 51e emitter electrode 51p pad 51pa, 51pc temperature sense pad 51pg gate pad 51psc current sense pad 51psp reference potential pad 52 second switching element 52d drain electrode 52s source electrode 52p pad 52pa, 52pc temperature sense pad 52pg gate pad 52psc current sense pad 52psp reference potential pad 53 temperature sensitive diode 60 Terminal 70 Main terminal 71 High potential terminal 72 Low potential terminal 80 Signal terminal 81 First signal terminal 82 Second signal terminal 90 Bonding material 91 Bonding wire DESCRIPTION OF SYMBOLS 100... Cooler, 101... Supply pipe, 102... Discharge pipe, 110... Power module

Claims (4)

a heat dissipation member (40);
A first switching element (51) formed on a Si substrate, and a second switching element (52) formed on a SiC substrate and having a smaller substrate area than the first switching element, one of the main electrodes a plurality of switching elements (50) electrically connected to the heat dissipation member and connected in parallel with each other;
with
The switching element includes at least a plurality of the first switching elements,
the first switching element and the second switching element are arranged side by side in a predetermined first direction, and the second switching element is arranged between the first switching elements;
The length in the first direction is shorter in the second switching element than in the first switching element, and the ratio of the length in the second direction perpendicular to the first direction to the length in the first direction is A semiconductor device in which the second switching element is made larger than the first switching element. 2. The semiconductor device according to claim 1, wherein said first switching element and said second switching element have the same length in said second direction. 3. The semiconductor device according to claim 2, wherein the positions of both ends in the second direction are the same between the first switching element and the second switching element. the first switching element is an IGBT,
the second switching element is a MOSFET,
The switching elements include two of the first switching elements and one of the second switching elements,
4. The semiconductor device according to claim 1, wherein said second switching element is arranged between said first switching elements in said first direction.

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