JP7132822B2 - Controller for DC/AC converter - Google Patents

Description

The present invention relates to a control device applied to a DC/AC converter that converts DC voltage to AC voltage.

Patent Literature 1 discloses a control device that operates a drive switch by well-known peak current mode control in order to control a reactor current flowing in a reactor of an AC/DC converter to a command value. This control device reduces the distortion of the output current by adding a current correction value that changes according to the phase of the AC voltage to the command value. Specifically, the current correction value is calculated based on the deviation between the average value of the reactor current and the command value.

JP 2015-198460 A

By the way, in a power conversion device that converts a DC voltage to an AC voltage, it is desired to improve the power factor of the AC power supplied to the AC power supply by improving the distortion of the output voltage.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a controller for a DC/AC converter that can suppress the distortion of the output current.

In order to solve the above problems, the present invention provides an AC power supply having a reactor and a drive switch, converting a DC voltage supplied through an input terminal into an AC voltage, and connecting the converted AC voltage to an output terminal. It relates to a control device for a DC/AC converter that is applied to a DC/AC converter that supplies to. A control device for a DC/AC converter includes a current acquisition unit that acquires a reactor current that is a current value flowing through the reactor, an AC voltage acquisition unit that acquires an AC voltage that is a voltage value of the AC power supply, and an acquired a current control unit that turns on and off the drive switch by peak current mode control in order to control the reactor current to a sinusoidal current command value generated based on the acquired AC voltage; and the peak current mode control. and a mask time setting unit for setting a mask time that determines the minimum value of the ON operation period in one switching cycle of the drive switch when implementing . The mask time setting unit variably sets the mask time so that the mask time has a minimum value within a variable period, which is a period near a zero cross timing at which the acquired AC voltage becomes zero.

In a DC/AC converter using peak current mode control, a current command value for a reactor current flowing through a reactor is set based on an AC voltage in order to improve the power factor of AC power supplied to an AC power supply. Therefore, in the vicinity of the zero-cross timing of the AC power supply, the current command value becomes the smallest value in order to bring the reactor current to a value near zero. Here, in peak current mode control, noise such as switching noise is superimposed on the reactor current detected near the zero-cross timing of the AC power supply, causing the reactor current to exceed the current command value and turn off the drive switch at an unintended timing. A false turn-off may occur that causes it to operate. An erroneous turn-off of the drive switch near the zero-cross timing of the AC voltage causes distortion of the output current. Therefore, it is conceivable to set the minimum ON operation period in one switching cycle of the drive switch to be longer in anticipation of noise superimposition. However, there is a concern that an excessive output current may temporarily flow due to an increase in the ON operation period of the drive switch. For example, when the ON operation period of the drive switch is lengthened, the reactor is overexcited and excessive current flows through the reactor, resulting in a temporary excess output current. In particular, at the zero-crossing timing of the AC voltage when the ON operation period of the drive switch is the minimum value, there is concern that an excessive output current tends to flow through the AC power supply as the mask time is lengthened.

In view of this point, the present invention variably sets the mask time that determines the minimum value of the ON operation period of the drive switch when performing the peak current mode control. Specifically, the mask time is variably set so that the mask time takes the minimum value within the variable period, which is the period near the zero-cross timing of the AC voltage. As a result, it is possible to suitably suppress the distortion of the output current while preventing the generation of excessive output current from the DC/AC converter.

The block diagram of the power converter device which concerns on 1st Embodiment. FIG. 3 is a functional block diagram for explaining functions of a control device; 4 is a timing chart for explaining each signal that flows through the current control unit; A timing chart explaining operation of a power converter. The figure explaining the principle of this invention. The figure explaining mask time. The figure explaining a current correction|amendment part. A timing chart of a power converter. The figure explaining the divergence width. The figure which shows the mask time in a modification. The figure which shows the mask time in a modification. The figure which shows the mask time in a modification. The figure which shows the mask time in a modification. The functional block diagram explaining the function of the control apparatus which concerns on 2nd Embodiment. A timing chart explaining operation of a power converter. The block diagram of the power converter device which concerns on 3rd Embodiment. FIG. 3 is a functional block diagram for explaining functions of a control device; The block diagram of the power converter device which concerns on 4th Embodiment. FIG. 3 is a functional block diagram for explaining functions of a control device; A timing chart explaining operation of a power converter. The block diagram of the power converter device which concerns on the modification of 4th Embodiment. FIG. 3 is a functional block diagram for explaining functions of a control device;

<First embodiment>
A DC/AC converter (hereinafter referred to as a power converter) according to this embodiment will be described. The power converter is connected to an AC power supply via a DC terminal, which is an input terminal, and converts DC power supplied through the DC terminal into AC power and supplies the AC power to the AC power supply.

A DC power supply (not shown) is connected to the first and second DC terminals TD1 and TD2 of the power converter 100 shown in FIG. 1, and an AC power supply 200 is connected to the first and second AC terminals TA1 and TA2 It is connected. The AC power supply 200 is, for example, a commercial power supply, and the DC power supply is a battery.

The power conversion device 100 includes a capacitor 16, a half bridge circuit 15, a reactor 13, a full bridge circuit 12, and first to sixth wirings LP1 to LP6.

A first end of a first wiring LP1 is connected to the first DC terminal TD1, and a first end of a second wiring LP2 is connected to the second DC terminal TD2. A capacitor 16 is connected between the first wiring LP1 and the second wiring LP2.

A half bridge circuit 15 is connected to the second ends of the first and second wirings LP1 and LP2. The half bridge circuit 15 has a fifth switch SW5 and a sixth switch SW6. The fifth and sixth switches SW5 and SW6 are voltage-driven switches, and are N-channel MOSFETs in this embodiment. The source of the fifth switch SW5 and the drain of the sixth switch SW6 are connected. A drain of the fifth switch SW5 is connected to the first wiring LP1, and a source of the sixth switch SW6 is connected to the second wiring LP2. Each of the fifth and sixth switches SW5 and SW6 has a parasitic diode connected in anti-parallel. In this embodiment, the fifth switch SW5 corresponds to the drive switch.

The half bridge circuit 15 and the full bridge circuit 12 are connected by a third wiring LP3 and a fourth wiring LP4. A first end of the third wiring LP3 is connected to a first connection point K1 between the source of the fifth switch SW5 and the drain of the sixth switch SW6. A reactor 13 is provided on the third wiring LP3. Also, the first end of the fourth wiring LP4 is connected to the source of the sixth switch SW6. A second end of each of the third and fourth wirings LP3 and LP4 is connected to the full bridge circuit 12 .

The full bridge circuit 12 includes first to fourth switches SW1 to SW4. The first to fourth switches SW1 to SW4 are voltage-driven switches, and are N-channel MOSFETs in this embodiment. The source of the third switch SW3 and the drain of the fourth switch SW4 are connected. The source of the first switch SW1 and the drain of the second switch SW2 are connected. Drains of the first and third switches SW1 and SW3 are connected to the third wiring LP3, and sources of the second and fourth switches SW2 and SW4 are connected to the fourth wiring LP4.

A second connection point K2 between the source of the third switch SW3 and the drain of the fourth switch SW4 is connected to the first end of the sixth wiring LP6, and the second end of the sixth wiring LP6 is connected to the second alternating current. It is connected to terminal TA2. A third connection point K3 between the first switch SW1 and the second switch SW2 is connected to a first end of the fifth wiring LP5, and a second end of the fifth wiring LP5 is connected to the first AC terminal TA1. there is

The power converter 100 includes a first voltage sensor 31 , a current sensor 32 and a second voltage sensor 33 . The first voltage sensor 31 is connected between the first and second wirings LP1 and LP2 and detects the DC voltage input through the first and second DC terminals TD1 and TD2 as the input voltage Vdc. The current sensor 32 is provided on the fourth line LP4 and detects the current value flowing through the reactor 13 as a reactor current ILr. The second voltage sensor 33 is connected between the fifth and sixth wirings LP5 and LP6, and detects the voltage of the AC power supply 200 as the AC voltage Vac.

The power conversion device 100 includes a control device 30 . The control device 30 operates the first to sixth switches SW1 to SW6. Each function provided by the control device 30 can be provided by, for example, software recorded in a physical memory device, a computer executing the software, hardware, or a combination thereof.

FIG. 2 is a functional block diagram illustrating functions of the control device 30. As shown in FIG. The control device 30 operates the fifth and sixth switches SW5 and SW6 to the on state or the off state by well-known peak current mode control. The control device 30 includes a waveform generation section 34 , a multiplier 35 , an absolute value calculation section 36 , an adder 37 , a current correction section 40 , a current control section 50 and a polarity switching section 55 . In this embodiment, the control device 30 corresponds to a current acquisition section and an AC voltage acquisition section.

Waveform generator 34 generates a reference waveform sinωt of AC voltage Vac. The reference waveform sinωt is a value indicating a voltage change in a half cycle (T/2) of the AC voltage Vac, has an amplitude of 1, and fluctuates in the same cycle as the AC voltage Vac. In this embodiment, the reference waveform sinωt has the same phase as the AC voltage Vac. Waveform generator 34 detects the timing at which AC voltage Vac detected by second voltage sensor 33 becomes 0 as zero-cross timing, and the period in which AC voltage Vac changes from one zero-cross timing to the next zero-cross timing is defined as AC voltage Set as half period (T/2) of Vac.

Multiplier 35 multiplies amplitude command value Ia* of reactor current ILr by reference waveform sinωt. Amplitude command value Ia* is a command value that determines the amplitude of reactor current ILr. Absolute value calculator 36 sets the absolute value of the output value from multiplier 35 as pre-correction command current IL*.

Current correction unit 40 sets current correction value Ic used for correction of pre-correction command current IL* in order to suppress distortion of output current Iac. The adder 37 adds the current correction value Ic to the pre-correction command current IL*, and sets the value after the addition as the post-correction command current ILa*. In this embodiment, the corrected command current ILa* corresponds to the current command value.

Current control unit 50 operates fifth gate signal GS5 for operating fifth switch SW5 and sixth switch SW6 based on reactor current ILr detected by current sensor 32 and corrected command current ILa*. A sixth gate signal GS6 is generated. In this embodiment, the current controller 50 generates the fifth and sixth gate signals GS5 and GS6 by well-known peak current mode control.

The current control section 50 includes a DA converter 351 , a comparator 352 , an adder 353 , an RS flip-flop 357 , a slope compensation section 60 and a mask time setting section 70 . The corrected command current ILa* is input to the DA converter 351 . The DA converter 351 converts the input post-correction command current ILa* from a digital value to an analog value. The post-correction command current ILa* converted into an analog value is input to the inverting input terminal of the comparator 352 . Adder 353 adds reactor current ILr and slope compensation signal Slope set by slope compensator 60, and outputs compensated reactor current ILr. The output from adder 353 is input to the non-inverting input terminal of comparator 352 . Note that the slope compensation signal Slope suppresses oscillation caused by fluctuations in the current flowing through the reactor 13 .

Comparator 352 compares corrected command current ILa* and reactor current ILr, and inputs low state determination signal OUT to mask time setting unit 70 during a period in which reactor current ILr is smaller than corrected command current ILa*. Further, the comparator 352 inputs the determination signal OUT in the high state to the mask time setting section 70 during the period when the reactor current ILr is greater than the post-correction command current ILa*.

In one switching period Tsw of the fifth switch SW5, the mask time setting unit 70 outputs the reset signal RE after the mask time TM has passed, when the determination signal OUT becomes high before the mask time TM has passed. When the determination signal OUT becomes high after the mask time TM has elapsed, the reset signal RE is output in accordance with the input of the determination signal OUT in the high state. The mask time TM is the time that determines the minimum value of the ON operation period Ton in one switching cycle Tsw of the fifth switch SW5. The reset signal RE is a signal that determines the end timing of the ON operation period Ton in one switching cycle Tsw of the fifth switch SW5.

The mask time setting section 70 includes a pulse generation section 71 and an AND circuit 72 . The pulse generator 71 generates a mask signal MSS for setting the mask time TM. In this embodiment, the length of the period during which the mask signal MSS is low in one period of the mask signal MSS is the mask time TM. In this embodiment, one period of the mask signal MSS is the same as one switching period Tsw of the fifth switch SW5.

FIG. 3(a) shows transitions of the reactor current ILr and the post-correction command current ILa*, and FIG. 3(b) shows transitions of the set signal SE. FIG. 3(c) shows transition of the determination signal OUT, and FIG. 3(d) shows transition of the reset signal RE. FIG. 3(d) shows transition of the mask signal MSS, and FIG. 3(e) shows transition of the fifth gate signal GS5 for operating the fifth switch SW5. The set signal SE is a signal that determines one switching cycle Tsw of the fifth switch SW5.

The AND circuit 72 has a first input terminal to which the mask signal MSS from the pulse generator 71 is input, and a second input terminal to which the determination signal OUT from the comparator 352 is input. As shown in FIG. 3C, the AND circuit 72 outputs the reset signal RE in a high state when the determination signal OUT is in a high state during the high period in which the mask signal MSS is in a high state. On the other hand, the AND circuit 72 outputs the reset signal RE in the low state even if the decision signal OUT is in the high state as indicated by the dashed line during the low period (that is, the mask time TM) in which the mask signal MSS is in the low state. do.

The set signal SE from the clock 354 is input to the S terminal of the RS flip-flop 357 . A Q terminal of the RS flip-flop 357 is connected to the gate of the fifth switch SW5. A signal output from the Q terminal to the gate of the fifth switch SW5 becomes the fifth gate signal GS5. Therefore, the period from when the set signal SE in the high state is input to the S terminal until the reset signal RE in the high state is input to the R terminal is the ON operation period Ton of the fifth switch SW5.

The output terminal of the RS flip-flop 357 is connected via the inverter 358 to the gate of the sixth switch SW6. A signal output from the Q terminal through the inverter 358 to the gate of the sixth switch SW6 becomes the sixth gate signal GS6. The sixth gate signal GS6 has a value obtained by inverting the fifth gate signal GS5.

Polarity switching section 55 inverts the output signal according to the polarity of AC voltage Vac. When the polarity switching unit 55 determines that the polarity of the AC voltage Vac is positive, the polarity switching unit 55 outputs a high-state output signal. On the other hand, polarity switching unit 55 outputs a low-state output signal when determining that the polarity of AC voltage Vac is negative.

The output terminal of the polarity switching section 55 is connected to each gate of the first and fourth switches SW1 and SW4. Signals output from the output terminal of the polarity switching unit 55 to the gates of the first and fourth switches SW1 and SW4 are the first and fourth gate signals GS1 and GS4. Also, the output terminal of the polarity switching section 55 is connected to the gates of the second and third switches SW2 and SW3 via an inverter 359. FIG. Signals output from the output terminal of the polarity switching unit 55 to the gates of the second and third switches SW2 and SW3 via the inverter 359 are the second and third gate signals GS2 and GS3. The second and third gate signals GS2 and GS3 have values obtained by inverting the first and fourth gate signals GS1 and GS4.

Next, the operation of the power converter 100 will be described. 4 is a timing chart of the power conversion device 100. FIG. FIG. 4(a) shows changes in the AC voltage Vac and the input voltage Vdc. FIG. 4(b) shows transitions of inverted values of the first and fourth gate signals GS1 and GS4 and the second and third gate signals GS2 and GS3, and FIG. The transition of the inverted value of the sixth gate signal GS6 is shown. FIG. 4(d) shows changes in pre-correction command current IL*, and FIG. 4(e) shows changes in reactor current ILr. FIG. 4(f) shows transition of the output current Iac.

In the first period P1 in which the AC voltage Vac is positive, the first and fourth gate signals GS1 and GS4 are in a high state, thereby turning on the first and fourth switches SW1 and SW4. When the second and third gate signals GS2 and GS3 are low, the second and third switches SW2 and SW3 are turned off. During the first period P1, the fifth gate signal GS5 is turned off and the sixth gate signal GS6 is turned on, thereby closing the reactor 13, the first switch SW1, the fourth switch SW4 and the sixth switch SW6. A circuit is formed. In this closed circuit, an output current Iac flows from the first AC terminal TA1 through the AC power supply 200 toward the second AC terminal TA2. At this time, the reactor current ILr in one switching cycle Tsw has a value corresponding to the duty ratio D (=Ton/Tsw) indicating the ratio of the ON operation period Ton in one switching cycle Tsw of the fifth switch SW5.

During the second period P2 in which the AC voltage Vac is negative, the first and fourth gate signals GS1 and GS4 are low, thereby turning off the first and fourth switches SW1 and SW4. When the second and third gate signals GS2 and GS3 are high, the second and third switches SW2 and SW3 are turned on. Also in the second period P2, the reactor current ILr flows through the reactor 13 according to the duty ratio D of the fifth switch SW5.

In order to improve the power factor of the AC power supplied to AC power supply 200, control device 30 sets a value obtained by multiplying reference waveform sinωt of AC voltage Vac by amplitude command value Ia* as pre-correction command current IL*. there is Therefore, the pre-correction command current IL* has a waveform in which a positive half-wave of a sine wave is repeated at a period of T/2. In FIG. 4, the pre-correction command current IL* increases as the current transitions from the zero cross timings ta and tc of the AC voltage Vac to the peak timings tb and td of the AC voltage Vac. Further, the pre-correction command current IL* decreases as the AC voltage Vac shifts from the peak timings tb, td to the zero-crossing timings tc, te. The peak timing is the timing at which the AC voltage Vac takes the maximum positive value or the minimum negative value in one cycle T of the AC voltage Vac.

Average value Iave of reactor current ILr transitions in a positive half-wave shape so as to take values near 0 at zero-cross timings ta, tc, and te, similarly to pre-correction command current IL*. Therefore, in the peak current mode control, noise such as switching noise is superimposed on the reactor current ILr detected near the zero-crossing timings ta, tc, and te of the AC voltage Vac, so that the reactor current ILr after compensation becomes the corrected command In some cases, the current exceeds the current ILa* and an erroneous turn-off occurs in which the fifth switch SW5 is turned off at timing different from the intended timing.

In FIGS. 5A and 5B, due to an erroneous turn-off of the fifth switch SW5, the on-operation period Ton1 of the fifth switch SW5 ends before the initially intended end timing of the on-operation period Ton2. Therefore, the actual ON operation period Ton1 in one switching period Tsw of the fifth switch SW5 is shorter than the initially intended ON operation period Ton2. Unintentional shortening of the on-operation period Ton excessively changes the output current Iac, so that the erroneous turn-off of the fifth switch SW5 near the zero-cross timing of the AC voltage Vac causes distortion of the output current Iac.

In order to suppress the occurrence of such an erroneous turn-off, it is conceivable to set the mask time TM longer according to the period during which noise is superimposed. In FIG. 5C, as an example, the ON operation period Ton3 of the fifth switch SW5 continues even after the superimposition of the noise ends. When the mask time TM is set to be long, the actual ON operation period Ton3 is different from the intended ON operation period as shown in FIG. There is concern that it will be longer than Ton2. In particular, in the vicinity of the zero-cross timing of AC voltage Vac, an excessive current flows through reactor 13 due to the lengthening of ON operation period Ton, which may temporarily cause excessive output current Iac to flow through AC power supply 200 .

Therefore, in the present embodiment, the mask time setting unit 70 variably sets the mask time TM so that the mask time TM becomes the minimum value near the zero cross timing of the AC voltage Vac. As a result, the distortion of the output current Iac caused by the erroneous turn-off can be suitably suppressed while preventing the generation of an excessive output current Iac.

Next, a method of variably setting the mask signal MSS according to the absolute value of the AC voltage Vac by the pulse generator 71 of the mask time setting unit 70 will be described with reference to FIG. 6, t0 and t8 are zero-up cross timings at which the AC voltage Vac switches from a negative value to a positive value, and t4 is at which the AC voltage Vac switches from a positive value to a negative value. This is the zero downcross timing. t2 and t6 are the positive and negative peak timings of the AC voltage Vac.

The pulse generator 71 sets the mask time TM to the minimum value within the variable period CP in each of the first and second periods P1 and P2, which are half cycles (T/2) of the AC voltage Vac. The variable period CP is a period (t0-t1, t3-t5, t7-t8) in the vicinity of zero-cross timings t0, t4 and t8 of the AC voltage Vac in one cycle of the AC voltage Vac. In this embodiment, the pulse generator 71 sets the mask time TM to the minimum value at the zero-cross timing of the AC voltage Vac. The minimum value of the mask time TM is a value greater than 0. For example, during the operation period of the fifth switch SW5 including the zero-cross timing, the corrected command current ILa* becomes a value smaller than the intended ON operation period Ton. It should be set.

For example, the variable period CP is one cycle of the AC voltage Vac, the period from the zero crossing timing to the timing when the AC voltage Vac reaches 20% of the peak value, and from the timing when the AC voltage Vac reaches 20% of the peak value to zero crossing. It may be set as a period until the timing. More preferably, the variable period CP is one cycle of the AC voltage Vac, and the AC voltage Vac is a period from the zero cross timing to the timing when it reaches 10% of the peak value and the timing when it reaches 10% of the peak value. to the zero-cross timing.

In the DC/AC converter, the duty ratio D, which is the ratio of the ON operation period Ton to one switching period Tsw of the fifth switch SW5, increases as the AC voltage Vac shifts from the zero-cross timing toward the peak timing. It decreases as it shifts from the peak timing side to the zero cross timing side. Therefore, the pulse generator 71 lengthens the mask time TM as the AC voltage Vac shifts from the zero-cross timing toward the peak timing in the variable period CP. The pulse generator 71 shortens the mask time TM as the AC voltage Vac shifts from the peak timing side to the zero-cross timing in the variable period CP. In this embodiment, the pulse generator 71 variably sets the mask time TM in synchronization with one switching period Tsw of the fifth switch SW5.

The pulse generator 71 sets the mask time TM to a fixed value during periods (t1-t3, t5-t7) other than the variable period CP. Specifically, during a period other than the variable period CP in one cycle T of the AC voltage Vac, the mask time TM is set to a value shorter than the maximum value of the ON operation period Ton assumed for the fifth switch SW5. there is

Next, the configuration of the current correction unit 40 according to this embodiment will be described using FIG. In the DC/AC converter, the divergence width Δi, which indicates the difference between the pre-correction command current IL* and the average value Iave of the distorted reactor current ILr, becomes the smallest value near the zero-cross timing. Here, the divergence width Δi becomes a factor of distortion of the output current Iac. Deviation width Δi can be calculated using the following equation (1) obtained by subtracting average value Iave of reactor current ILr from uncorrected command current IL*.

なお、上記式（１）の導出方法については後述する。

A method of deriving the above formula (1) will be described later.

When the input voltage Vdc is converted to the AC voltage Vac according to the above formula (1), the divergence width Δi takes the minimum value at the zero cross timing of the AC voltage Vac and takes the maximum value at the peak timing when the AC voltage Vac becomes maximum. . Therefore, the current correction unit 40 calculates the current correction value Ic according to the divergence width Δi calculated by the above equation (1).

A current correction unit 40 shown in FIG. 7 includes an effective value calculation unit 41 , a coefficient setting unit 42 , a reference correction value calculation unit 43 and a multiplier 44 . For example, the effective value calculator 41 calculates the effective value Vrms of the AC power supply 200 based on the AC voltage Vac.

The reference correction value calculator 43 sets the reference correction value Ih of the current correction value Ic based on the effective value Vrms calculated by the effective value calculator 41 . The reference correction value Ih is a reference value for the current correction value Ic within one switching cycle Tsw of the fifth switch SW5, and is a value corresponding to the divergence width Δi shown in the above formula (1). The reference correction value Ih is set to have a positive half-wave shape that takes a minimum value at the zero-cross timing of the AC voltage Vac and takes a maximum value at the peak timing of the AC voltage Vac. In this embodiment, the reference correction value Ih is set to zero at the zero-cross timing, but is not limited to this, and may be set to a value greater than zero at the zero-cross timing.

The reference correction value calculator 43 has a reference correction value map that records the reference correction value Ih corresponding to the combination of the effective value Vrms, the AC voltage Vac, and the input voltage Vdc. Each reference correction value map has values determined such that the larger the effective value Vrms of AC power supply 200, the smaller the maximum value of reference correction value Ih.

A coefficient setting unit 42 sets a correction coefficient β to be multiplied by the reference correction value Ih based on the AC voltage Vac and the amplitude command value Ia*. The correction coefficient β is set to a value greater than 0 and 1 or less. For example, when the amplitude command value Ia* is smaller than the threshold TH1, the coefficient setting unit 42 sets the correction coefficient β to a larger value as the amplitude command value Ia* increases, and when the amplitude command value Ia* is greater than or equal to the threshold TH1, the correction coefficient β is set to a predetermined value. and

The multiplier 44 multiplies the reference correction value Ih set by the reference correction value calculation unit 43 by the correction coefficient β set by the coefficient setting unit 42 to set the current correction value Ic. As a result, the correction coefficient β becomes a small value at the zero-crossing timing of the AC voltage Vac, so the current correction value Ic is set to a small value.

Next, the operation of power conversion device 100 will be described using FIG. FIG. 8(a) shows transitions of the AC voltage Vac and the input voltage Vdc, and FIG. 8(b) shows transitions of inverted values of the fifth gate signal GS5 and the sixth gate signal GS6. FIG. 8(c) shows the transition of the current correction value Ic, and FIG. 8(d) shows the transition of the pre-correction command current IL*. FIG. 8(e) shows transition of mask time TM, and FIG. 8(f) shows transition of reactor current ILr. FIG. 8(g) shows transition of the output current Iac.

In the first period P1 (t11-t15) in which the AC voltage Vac takes a positive value, in order to reduce the phase difference between the average value Iave of the reactor current ILr and the AC voltage Vac, near the zero cross timing (t11, t15) is set to a small value.

In the first period P1, the mask time TM becomes the minimum value at the zero cross timings (t11, t15). Then, during the variable period CP from time t11 to t12, the mask time TM increases as the AC voltage Vac increases. Also, during the variable period CP from time t14 to t15, the mask time TM decreases as the AC voltage Vac decreases. This prevents erroneous turn-off in the vicinity of the zero-cross timing of AC voltage Vac, thereby suppressing distortion of output current Iac. In addition, in the vicinity of the zero-crossing timing of AC voltage Vac, temporary excessive output current Iac is prevented from flowing.

In addition, the current correction value Ic is set to have a positive half-wave shape that is the minimum value at the zero-cross timing according to the deviation width between the pre-correction command current IL* and the average value Iave of the reactor current ILr. As a result, the duty ratio D of the fifth gate signal GS5 is set so as to reduce the width of deviation, thereby further suppressing the distortion of the output current Iac.

Even in the second period P2 (t15-t19) in which the AC voltage Vac has a negative value, during the variable periods (t15-t16, t18-t19) including the zero cross timing, the mask time TM is changed according to the change in the AC voltage Vac. is variably set. This prevents a temporary excessive flow of output current Iac and suppresses distortion of output current Iac due to erroneous turn-off.

Next, a method of creating a reference correction value map will be described with reference to FIG.

In the present embodiment, the divergence width Δi is a value obtained by subtracting the average value Iave of the reactor current ILr from the pre-correction command current IL*. In FIG. 9, D indicates the duty ratio of the ON operation period of the fifth switch SW5.

From FIG. 9, the width of divergence Δi is obtained by adding half the maximum increase ΔIL of the reactor current ILr (ΔIL/2) to the maximum increase Δslope of the slope compensation signal Slope during the ON operation period (=D×Tsw). can be regarded as Therefore, the divergence width Δi is calculated by the following formula (2).

Δi=IL*−Iave=Δslope+ΔIL/2 (2)
Also, the maximum increase ΔIL of the reactor current ILr can be calculated by the following equation (3) using the voltage generated across the reactor 13 and the inductance L of the reactor 13 .

また、スロープ補償信号Ｓｌｏｐｅの最大増加分Δｓｌｏｐｅは、下記式（４）により算出することができる。
Δｓｌｏｐｅ ＝ ｍｓ×Ｄ×Ｔｓｗ … （４）
例えば、乖離幅Δｉを算出する際のスロープ補償信号Ｓｌｏｐｅの傾きｍｓは、傾きｍｓの平均値を用いればよい。

Also, the maximum increment Δslope of the slope compensation signal Slope can be calculated by the following equation (4).
Δslope=ms×D×Tsw (4)
For example, the average value of the slope ms may be used as the slope ms of the slope compensation signal Slope when calculating the divergence width Δi.

The duty ratio D of the ON operation period Ton of the fifth switch SW5 can be calculated by the following formula (5) using the effective value Vrms of the AC voltage Vac.

上記式（２）～（５）により乖離幅Δｉは上記式（１）として算出される。本実施形態では、上記式（１）で示される乖離幅Δｉを用いて、基準補正値Ｉｈを算出する。例えば、乖離幅Δｉに算出係数αを乗算した値を、基準補正値Ｉｈとして用いることができる。なお、算出係数αは、０より大きく、１以下の値とすることができる。そして、算出した各基準補正値Ｉｈを、実効値Ｖｒｍｓ毎に記録することで、基準補正値マップを作成することができる。

The divergence width Δi is calculated as the above equation (1) from the above equations (2) to (5). In this embodiment, the reference correction value Ih is calculated using the divergence width Δi given by the above equation (1). For example, a value obtained by multiplying the deviation width Δi by the calculation coefficient α can be used as the reference correction value Ih. Note that the calculation coefficient α can be set to a value greater than 0 and 1 or less. By recording each calculated reference correction value Ih for each effective value Vrms, a reference correction value map can be created.

In the embodiment described above, the following effects can be obtained.

The control device 30 variably sets the mask time TM so that the mask time TM has a minimum value within a variable period, which is a period near the zero-cross timing of the AC voltage Vac, when performing peak current mode control. . As a result, it is possible to suitably suppress the distortion of the output current Iac while preventing the generation of an excessive output current Iac from the power conversion device 100 .

In the variable period CP, the control device 30 lengthens the mask time TM as the AC voltage Vac shifts from the zero-cross timing toward the peak timing, and lengthens the mask time TM as the AC voltage Vac shifts from the peak timing toward the zero-cross timing. Shorten TM. As a result, it is possible to prevent the on-operation period Ton of the fifth switch SW5 from deviating significantly from the originally intended length, and to favorably achieve both prevention of excessive output current Iac and suppression of distortion of the output current. can do.

- The control device 30 variably sets the mask time TM in synchronization with one switching period Tsw of the fifth switch SW5. As a result, an increase in the calculation load of the control device 30 required for calculating the mask time TM can be suppressed.

<Modification 1 of the first embodiment>
The mask time TM set by the mask time setting unit 70 may be the minimum value at the zero cross timing of the AC voltage Vac.

10 to 13 are diagrams for explaining the mask time TM according to this embodiment. Any mask time TM takes the minimum value at the zero cross timing of the AC voltage Vac.

10 to 12, the mask time TM takes the maximum value at the peak timing of the AC voltage Vac. In FIG. 10, the mask time TM forms an upwardly convex polygonal line by linearly transitioning between the maximum value and the minimum value in each of the first and second periods P1 and P2. In FIG. 11, the mask time TM has an upwardly convex circular arc by transitioning between the maximum value and the minimum value in each of the first and second periods P1 and P2. . In FIG. 12, the mask time TM has an upward convex step shape in each of the first and second periods P1 and P2.

In FIG. 13, the mask time TM transitions so that it has a minimum value during almost the entire variable period CP. The mask time TM changes to take the maximum value in periods other than the variable period CP in one cycle of the AC voltage Vac. In the mask time TM shown in FIG. 13, periods other than the variable period CP may not be constant.

Also in this embodiment described above, the same effects as in the first embodiment can be obtained.

<Second embodiment>
In the DC/AC converter, the duty ratio D of the fifth switch SW5 is the smallest at the zero cross timing of the AC voltage Vac. Therefore, at the zero-crossing timing of the AC voltage Vac, the ON operation period Ton of the fifth switch SW5 tends to be shorter than the mask time TM, so there is concern that an excessive output current Iac may temporarily flow.

The power conversion device 100 shown in FIG. 14 includes a stop unit 75 that temporarily stops turning on the fifth and sixth switches SW5 and SW6 by the current control unit 50 near the zero cross timing of the AC voltage Vac. Based on the AC voltage Vac, the stopping unit 75 determines whether or not the current switching period Tsw of the fifth switch SW5 includes the zero-cross timing of the AC voltage Vac. Then, when it is determined that the current switching period Tsw of the fifth switch includes the zero cross timing of the AC voltage Vac, the fifth and sixth gate signals from the current control unit 50 to the fifth and sixth switches SW5 and SW6 The supply of GS5 and GS6 is stopped.

Next, the operation of power conversion device 100 will be described using FIG. 15 . FIG. 15(a) shows changes in the AC voltage Vac and the input voltage Vdc. FIG. 15(b) shows transition of the fifth gate signal GS5, and FIG. 15(c) shows transition of the sixth gate signal GS6. FIG. 15(d) shows transition of pre-correction command current IL*, and FIG. 15(e) shows transition of mask time TM. FIG. 15(f) shows changes in reactor current ILr, and FIG. 15(g) shows changes in output current Iac.

During the operation period including the zero crossing timings (t21, t25) of the AC voltage Vac in the first period P1, the fifth and sixth gate signals GS5 and GS6 from the current control unit 50 to the fifth and sixth switches SW5 and SW6 supply is stopped. Therefore, in the vicinity of the zero-cross timing of AC voltage Vac, the excitation of reactor 13 is stopped, thereby making it easier for reactor current ILr to decrease.

Also in the second period P2, the supply of the fifth and sixth gate signals GS5 and GS6 from the current control section 50 to the fifth and sixth switches SW5 and SW6 is stopped at the zero crossing timing (t29) of the AC voltage Vac. . Therefore, reactor current ILr tends to decrease near the zero crossing timing of AC voltage Vac in second period P2.

In the embodiment described above, excessive output current Iac near the zero cross timing of AC voltage Vac can be further suppressed.

<Third Embodiment>
3rd Embodiment mainly demonstrates a different structure from 1st Embodiment. In addition, the structure which attached|subjected the code|symbol same as 1st Embodiment shows the same structure, and the description is not repeated.

In this embodiment, in order to suppress the distortion of the output current Iac, instead of correcting the command current IL* before correction with the current correction value Ic, the reactor current ILr is corrected with the current correction value Ic.

FIG. 16 is a configuration diagram of a power conversion device 100 according to this embodiment. In this embodiment, the current sensor 32 that detects the reactor current ILr is provided closer to the source of the fifth switch SW5 than the first connection point K1 connecting the source of the fifth switch SW5 and the drain of the sixth switch SW6. . In this case, the control device 30 acquires the current flowing through the fifth switch SW5 as the reactor current ILr.

FIG. 17 is a block configuration diagram of the control device 30 according to this embodiment. Current correction unit 40 changes current correction value Ic used to correct reactor current ILr based on AC voltage Vac and input voltage Vdc. In this embodiment, the current correction value Ic set by the current correction unit 40 can be the same as in the first embodiment. In this embodiment, the control device 30 includes a subtractor 53 that subtracts the current correction value Ic from the reactor current ILr. Therefore, a value obtained by subtracting current correction value Ic from reactor current ILr is input to adder 353 . Adder 353 adds slope compensation signal Slope to reactor current ILr from which current correction value Ic has been subtracted, and outputs reactor current ILr after compensation.

Pre-correction command current IL* input to control device 30 is input to DA converter 351 as it is. The pre-correction command current IL* converted into an analog value by the DA converter 351 is input to the inverting input terminal of the comparator 352 . Comparator 352 outputs determination signal OUT in a low state to mask time setting section 70 during a period in which reactor current ILr after compensation is smaller than command current IL* before correction. Comparator 352 also outputs determination signal OUT in a high state to mask time setting section 70 during a period in which reactor current ILr after compensation is greater than command current IL* before correction.

The same effects as those of the first embodiment can be obtained in the present embodiment described above.

<Fourth Embodiment>
In this embodiment, the circuit topology is different from that of the power converter 100 shown in the first embodiment. Specifically, unlike the first embodiment, the power converter 100 according to this embodiment does not include a half-bridge circuit.

FIG. 18 is a diagram showing a power conversion device 100 according to this embodiment. The first DC terminal TD1 and the full bridge circuit 12 are connected via a first wiring LP1. The second DC terminal TD2 and the full bridge circuit 12 are connected via a second wiring LP2.

The full bridge circuit 12 includes first to fourth switches SW11 to SW14. Since the first to fourth switches SW11 to SW14 have the same circuit configuration as the first to fourth switches SW1 to SW4 included in the full bridge circuit 12 of the first embodiment, description thereof will be omitted.

A first current sensor 61 is provided between the source of the third switch SW13 and the drain of the fourth switch SW14. The first current sensor 61 detects currents flowing through the first and fourth switches SW11 and SW14 as a first reactor current IL1r. A second current sensor 62 is provided between the source of the first switch SW11 and the drain of the second switch SW12. The second current sensor 62 detects currents flowing through the second and third switches SW12 and SW13 as a second reactor current IL2r.

FIG. 19 is a functional block diagram showing functions of the control device 30 according to this embodiment. Also in this embodiment, the control device 30 controls the power conversion device 100 by peak current mode control.

The control device 30 includes a subtractor 53 that subtracts the current correction value Ic output by the current correction unit 40 from the first and second reactor currents IL1r and IL2r, a first current control unit 51, and a second current control unit. 52. The first current control unit 51 performs peak current mode control to control the first reactor current IL1r from which the current correction value Ic is subtracted to the post-correction command current ILa*. The second current control unit 52 performs peak current mode control to control the second reactor current IL2r from which the current correction value Ic is subtracted to the post-correction command current ILa*. Since the configurations of the first and second current control units 51 and 52 are the same as the configuration of the current control unit 50, description thereof will be omitted.

The output of the first current control section 51 is connected to one input terminal of the first AND circuit 382 , and the output of the second current control section 52 is connected to one input terminal of the second AND circuit 383 . The output terminal of the polarity switching section 55 is connected to the other input terminal of the second AND circuit 383 and the input terminal of the inverter 360 . The output terminal of inverter 360 is connected to the other input terminal of first AND circuit 382 .

The output signal from the RS flip-flop 357 of the first current control section 51 and the output signal from the polarity switching section 55 are input to the first AND circuit 382 . The output terminal of the first AND circuit 382 is connected to the gate of the fourth switch SW14. A signal output from the first AND circuit 382 to the gate of the fourth switch SW14 becomes the fourth gate signal GS4. Also, the output terminal of the first AND circuit 382 is connected via the inverter 361 to the gate of the third switch SW13. A signal output from the first AND circuit 382 to the gate of the third switch SW13 via the inverter 361 becomes the third gate signal GS3. The third gate signal GS3 is obtained by inverting the fourth gate signal GS4.

The output signal of the RS flip-flop 357 of the second current control section 52 and the output signal from the polarity switching section 55 are input to the second AND circuit 383 . The output side of the second AND circuit 383 is connected to the gate of the second switch SW12. A signal output from the second AND circuit 383 to the gate of the second switch SW12 becomes the second gate signal GS2. Also, the output terminal of the second AND circuit 383 is connected via the inverter 362 to the gate of the first switch SW11. A signal output from the second AND circuit 383 to the gate of the first switch SW11 via the inverter 362 becomes the first gate signal GS1. The first gate signal GS1 is obtained by inverting the second gate signal GS2.

The output signal of the polarity switching unit 55 in the high state and the output signal of the RS flip-flop 357 in the high state are input to the first AND circuit 382, whereby the first AND circuit 382 outputs the fourth gate signal GS4 in the high state. output, and output the third gate signal GS3 in the low state. Further, when the output signal of the polarity switching unit 55 in the high state and the output signal of the RS flip-flop 357 in the high state are input to the second AND circuit 383, the second AND circuit 383 outputs the second gate signal in the high state. GS2 and the first gate signal GS1 in the low state.

FIG. 20 is a timing chart of the power converter 100 according to this embodiment. FIG. 20(a) shows changes in the input voltage Vdc and the AC voltage Vac. FIG. 20(b) shows transition of the first gate signal GS1, and FIG. 20(c) shows transition of the second gate signal GS2. FIG. 20(d) shows transition of the third gate signal GS3, and FIG. 20(e) shows transition of the fourth gate signal GS4. FIG. 20(f) shows transition of pre-correction command current IL*, and FIG. 20(g) shows transition of mask time TM. FIG. 20(h) shows transition of reactor current ILr, and FIG. 20(i) shows transition of output current Iac.

In the first period P1 in which the AC voltage Vac is positive, the first gate signal GS1 is in a high state to turn on the first switch SW11, and the second gate signal GS2 is in a low state to turn on the second switch SW12. is turned off. In the first period P1, the third and fourth gate signals GS3 and GS4 are changed to a high state or a low state by peak current mode control performed by the first and second current controllers 51 and 52, respectively. As a result, the third and fourth switches SW13 and SW14 are operated, and the output current Iac flows from the first AC terminal TA1 through the AC power supply 200 toward the second AC terminal TA2.

In the second period P2 in which the AC voltage Vac is negative, in the full bridge circuit 12, the third gate signal GS3 is in a high state, so that the third switch SW13 is in an ON state and the fourth gate signal GS4 is in a low state. As a result, the fourth switch SW14 is turned off. In the second period P2, the first and second gate signals GS1 and GS2 are changed to a high state or a low state by the peak current mode control performed by the first and second current controllers 52, respectively. As a result, the output current Iac flows from the second AC terminal TA2 through the AC power supply 200 toward the first AC terminal TA1.

Also in the present embodiment, the mask time TM becomes the minimum value at the zero cross timings (t31, t35, t39) of the AC voltage Vac. Also, in the variable period CP near the mask time TM, the mask time TM changes according to the increase or decrease of the AC voltage Vac.

The present embodiment described above has the same effect as the first embodiment.

<Modification 1 of Fourth Embodiment>
The first current sensor 61 may be provided on the drain side of the first switch SW11. A second current sensor 62 may be provided on the drain side of the second switch SW12.

<Modification 2 of the fourth embodiment>
FIG. 21 is a configuration diagram of a power conversion device 100 according to a modification of the fourth embodiment. In this embodiment, the first current sensor 61 is provided on the drain side of the first switch SW11. A second current sensor 62 is provided closer to the second switch SW12 than the fifth connection point K5 in the wiring that connects the source and drain between the first and second switches SW11 and SW12.

FIG. 22 is a functional block diagram of the control device 30 according to the modification of the fourth embodiment. Also in this modification, the control device 30 controls the power conversion device 100 by peak current mode control.

The second reactor current IL2r from which the current correction value Ic has been subtracted by the subtractor 53 is input to the first current control unit 51 . Also, the first reactor current IL1r from which the current correction value Ic has been subtracted by the subtractor 53 is input to the second current control unit 52 .

The output terminal of the polarity switching section 55 is connected to the input terminal of the second AND circuit 383, the gate of the fourth switch SW14, and the input terminal of the inverter 360. The output terminal side of the inverter 360 is connected to the input terminal of the first AND circuit 382 and the gate of the third switch SW13.

The output signal from the RS flip-flop 357 of the first current control section 51 and the output signal from the polarity switching section 55 are input to the first AND circuit 382 . The output terminal of the first AND circuit 382 is connected to the gate of the second switch SW12.

The output signal of the RS flip-flop 357 of the second current control section 52 and the output signal from the polarity switching section 55 are input to the second AND circuit 383 . The output side of the second AND circuit 383 is connected to the gate of the first switch SW11.

A signal output from the first AND circuit 382 to the gate of the second switch SW12 becomes the second gate signal GS2. A signal output from the second AND circuit 383 to the gate of the first switch SW11 becomes the first gate signal GS1. A signal output from the polarity switching unit 55 to the gate of the third switch SW13 via the inverter 360 becomes the third gate signal GS3. A signal output from the polarity switching unit 55 to the gate of the fourth switch SW14 becomes the fourth gate signal GS4.

In the first period P1 in which the AC voltage Vac is positive, the output signal from the polarity switching section 55 is high, so that the fourth gate signal GS4 is high and the third gate signal GS3 is low. Also, in the first period P1, the first and second current controllers 51 and 52 change the first and second gate signals GS1 and GS2 to a high state or a low state by peak current mode control, thereby The second switches SW11 and SW12 are operated.

In the second period P2 when the AC voltage Vac is negative, the output signal from the polarity switching section 55 is low, so that the fourth gate signal GS4 is low and the third gate signal GS3 is high. In the second period P2, the first and second current controllers 51 and 52 change the first and second gate signals GS1 and GS2 to high or low states by peak current mode control to The second switches SW11 and SW12 are operated.

Also in this embodiment, the mask time TM is set to the minimum value at the zero-cross timing of the AC voltage Vac. Also, in the variable period CP near the mask time TM, the mask time TM changes according to the increase or decrease of the AC voltage Vac.

Also in this embodiment described above, the same effects as in the first embodiment can be obtained.

<Other embodiments>
- The mask time setting unit 70 may be provided between each current control unit 50 to 52 and each drive switch. In this case, if the gate signal changes from high to low before the mask time TM elapses, the gate signal may be changed to low after the mask time TM elapses. Also in this case, the mask time setting unit 70 variably sets the mask time TM so that the mask time TM takes the minimum value in the vicinity of the zero cross timing of the AC voltage Vac.

- Control device 30 is good also as composition which does not correct command current and reactor current by a current correction value.

- The full bridge circuit 12 may be configured by a circuit using four IGBTs.

DESCRIPTION OF SYMBOLS 13... Reactor, 30... Control apparatus, 50... Current control part, 70... Mask time setting part, 200... AC power supply, 100... Power converter.

Claims (5)

It has a reactor (13) and drive switches (SW1 to SW14), converts the DC voltage supplied through the input terminals (TD1, TD2) into an AC voltage, and converts the converted AC voltage to the output terminals (TA1, TA2 A control device (30) for a DC-AC converter applied to a DC-AC converter (100) that supplies an alternating current power supply (200) connected to a
a current acquisition unit that acquires a reactor current that is a current value flowing through the reactor;
an AC voltage acquisition unit that acquires an AC voltage that is the voltage value of the AC power supply;
A current control unit (50 to 52) that turns on and off the drive switch by peak current mode control in order to control the acquired reactor current to a sinusoidal current command value generated based on the acquired AC voltage. )When,
a mask time setting unit (70) for setting a mask time that determines a minimum value of an ON operation period in one switching cycle of the drive switch when the peak current mode control is performed;
with
The mask time setting unit DC/AC variably sets the mask time so that the mask time has a minimum value within a variable period that is a period near a zero cross timing at which the acquired AC voltage becomes zero. Control device for conversion device. The mask time setting unit lengthens the mask time as the AC voltage shifts from the zero-cross timing toward the peak timing in the variable period, and the AC voltage shifts from the peak timing toward the zero-cross timing. 2. A controller for a DC/AC converter according to claim 1, wherein said mask time is shortened as much as possible. 3. The controller for a DC/AC converter according to claim 2, further comprising a stopping section (75) for temporarily stopping the ON operation of said drive switch by said current control section in the vicinity of said zero-crossing timing of said AC voltage. 4. The controller for a DC/AC converter according to claim 1, wherein said mask time setting unit variably sets said mask time in synchronization with one switching cycle of said drive switch. In the peak current mode, the current control unit turns on the drive switch during a period in which the acquired reactor current is equal to or less than the current command value, and during a period in which the acquired reactor current exceeds the current command value. The controller for a DC/AC converter according to any one of claims 1 to 4, wherein the drive switch is turned off.

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