JP7101500B2 - Cryptographic device, encryption system, and encryption method - Google Patents

Description

The present invention relates to an encryption device, an encryption system, and an encryption method for encrypting a signal written in a memory.

Conventionally, an encryption technique for encrypting a program is known. For example, Patent Document 1 describes an encryption technique in which a new jump instruction is inserted into a target program and the program after the jump instruction is inserted is encrypted in a cryptographic block chain mode.

Japanese Unexamined Patent Publication No. 2009-21192

If a malicious program is written in a memory that stores a program to be executed by a CPU (Central Processing Unit), the CPU may execute the malicious program.

Therefore, the present invention is an encryption device and encryption that can prevent the CPU from executing the malicious program even if the malicious program is written in the memory that stores the program to be executed by the CPU. It is an object of the present invention to provide an encryption system and an encryption method.

The encryption device according to one aspect of the present invention is an encryption device that encrypts a signal to be written in a memory, and a program including an instruction executed by a CPU output from a recording medium is stored in units of addresses of the memory. , The encryption unit that encrypts the encrypted text and the plain text reversibly by the first encryption method corresponding to one-to-one, and the signal read from the memory is the first in the memory address unit. It includes a decoding unit that decodes by the first decoding method, which is the reverse conversion of the encryption method.

Further, the encryption system according to one aspect of the present invention includes a CPU, a memory, a recording medium, and an encryption device that encrypts a signal written in the memory, and the encryption device is derived from the recording medium. The encryption unit that encrypts the output program including the instruction executed by the CPU by the first encryption method in which the encrypted text and the plain text have a one-to-one correspondence in the address unit of the memory, and the memory. Includes a decoding unit that decodes the signal read from the above in units of addresses of the memory by the first decryption method, which is the reverse conversion of the first encryption method.

Further, the encryption method according to one aspect of the present invention is an encryption method for encrypting a signal to be written in a memory, in which a program output from a recording medium and including at least an instruction executed by a CPU is included in the memory. The encryption step of encrypting by the first encryption method in which the encrypted text and the plain text have a one-to-one correspondence in units, and the first encryption of the signal read from the memory in the address unit of the memory. It includes a decoding step of decoding by a first decoding method, which is an inverse conversion of the encryption method.

According to the present invention, even if a malicious program is written in the memory for storing the program to be executed by the CPU, the execution of the malicious program by the CPU can be suppressed.

FIG. 1 is a block diagram showing a configuration of an encryption system according to the first embodiment. FIG. 2 is a block diagram showing an encryption device configuration according to the first embodiment. FIG. 3A is a schematic diagram showing the relationship between the ciphertext and the plaintext in the first encryption method. FIG. 3B is a schematic diagram showing the relationship between the ciphertext and the plaintext in the second encryption method. FIG. 4A is a schematic diagram showing the relationship between the ciphertext and the plaintext in the first decryption method. FIG. 4B is a schematic diagram showing the relationship between the ciphertext and the plaintext in the second decryption method. FIG. 5 is a schematic diagram showing the operation of the encryption system 1 in the case 1. FIG. 6 is a schematic diagram showing the operation of the encryption system 1 in the case 2. FIG. 7 is a schematic diagram showing the operation of the encryption system 1 in the case 3. FIG. 8 is a schematic diagram showing the operation of the encryption system 1 in the case 4. FIG. 9 is a schematic diagram showing the operation of the encryption system 1 in the case 5. FIG. 10 is a schematic diagram showing the operation of the encryption system 1 in the case 6.

(Background to Obtaining One Aspect of the Present Invention)
The inventor has investigated a method that can prevent the CPU from executing the malicious program even if the malicious program is written in the memory that stores the program to be executed by the CPU. As a result, for the above suppression, the inventor first converts (for example, encrypts) a program to be executed by the CPU into a signal in a format that cannot be directly executed by the CPU, and then stores the program in the memory. When executing a program, it is effective to reverse-convert (for example, decode) the signal to return it to a program in a format that can be executed by the CPU, and then let the CPU execute the program. Then, based on the knowledge, the inventor came up with the encryption device according to one aspect of the present invention.

That is, the encryption device according to one aspect of the present invention, which the inventor came up with, is an encryption device that encrypts a signal to be written in a memory, and includes a program output from a recording medium and including an instruction executed by a CPU. The encryption unit that encrypts the encrypted text and the plain text reversibly by the first encryption method corresponding to one-to-one in the address unit of the memory, and the signal read from the memory of the memory. Each address is provided with a decoding unit that decodes by the first decryption method, which is the reverse conversion of the first encryption method.

According to the above-mentioned encryption device, even if a malicious program is written in the memory, the above-mentioned encryption device decrypts the malicious program read from the memory by the first decryption method. do. Therefore, even if the CPU tries to execute the signal decoded by the first decoding method with respect to the malicious program read from the memory, it is not executed as the malicious program.

Therefore, according to the above-mentioned encryption device, even if a malicious program is written in the memory for storing the program to be executed by the CPU, the execution of the malicious program by the CPU can be suppressed.

Further, the encryption device encrypts the program by a simpler method than, for example, the encryption technique for encrypting the conventional program described in Patent Document 1.

Therefore, according to the above-mentioned encryption device, it is possible to realize an encryption device having a smaller circuit scale than the case of using the conventional encryption technique.

Hereinafter, a specific example of the encryption device according to one aspect of the present invention will be described with reference to the drawings. Each of the embodiments shown here shows a specific example of the present invention. Therefore, the numerical values, shapes, components, arrangement and connection forms of the components, steps (processes), order of steps, etc. shown in the following embodiments are examples and do not limit the present invention. .. Among the components in the following embodiments, the components not described in the independent claims are components that can be arbitrarily added. Further, each figure is a schematic view and is not necessarily exactly illustrated.

(Embodiment)
[1. Constitution]
FIG. 1 is a block diagram showing a configuration of an encryption system 1 according to the present embodiment, including the encryption device 10 according to the present embodiment.

As shown in FIG. 1, the encryption system 1 includes an encryption device 10, a memory 20, a CPU 30, and a recording medium 40.

The CPU 30 is an information processing device called a so-called processor, and is realized by, for example, a semiconductor integrated circuit. The CPU 30 may be configured to include, for example, a CPU core and a cache memory.

The recording medium 40 is a recording medium for recording programs, data, and the like used by the CPU 30. The recording medium 40 may be any recording medium as long as it can record programs, data, and the like used by the CPU 30. The recording medium 40 may be, for example, a hard disk drive (HDD) or a Blu-ray disc (registered trademark). Here, the program stored in the recording medium 40 includes at least one instruction executed by the CPU 30.

The memory 20 is a memory used as the main memory of the CPU 30. The memory 20 is realized by, for example, a semiconductor integrated circuit. The memory 20 may be any memory as long as it is used as the main memory of the CPU 30. The memory 20 may be, for example, a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory).

The memory 20 functions as, for example, a program storage area in which a program recorded on the recording medium 40 is loaded. Further, the memory 20 functions as, for example, a work area for data temporarily used by the CPU. Further, the memory 20 functions as, for example, a disk cache of data recorded on the recording medium 40.

The encryption device 10 encrypts the signal to be written in the memory 20 and decodes the signal read from the memory 20. The encryption device 10 may be realized by, for example, a semiconductor integrated circuit composed of dedicated hardware, or may be realized by the processor executing a program stored in the memory including a processor and a memory.

Hereinafter, the encryption device 10 will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing the configuration of the encryption device 10.

As shown in FIG. 2, the encryption device 10 includes an encryption unit 11, a decryption unit 12, a flag storage unit 13, a flag update unit 14, and an encryption method setting unit 15. To.

The encryption unit 11 encrypts the signal output from the recording medium 40 by the first encryption method in which the ciphertext and the plaintext reversibly correspond to each other in the address unit of the memory 20.

FIG. 3A is a schematic diagram showing the relationship between the ciphertext and the plaintext in the first encryption method.

Here, it is assumed that the first encryption method is a circular shift (rotation) for each address of the memory 20. However, the first encryption method is not necessarily limited to a configuration that is a circular shift as long as it is an encryption method in which the ciphertext and the plaintext have a reversible one-to-one correspondence in the address unit of the memory 20. There is no. For example, an encryption method may be used in which the odd-numbered bits and the even-numbered bits on the one-bit upper bit side thereof are replaced with each other. Further, although the example here is a case where the word length of the memory 20 is 32 bits, the word length of the memory 20 is not necessarily limited to 32 bits. For example, the word length of the memory 20 may be 16 bits.

As shown in FIG. 3A, here, the first encryption method is a left 2-bit circular shift performed in units of 32 bits, which is an address unit of the memory 20.

In the following, in order to make the explanation easier to understand, when the value of 32 bits which is the signal before the first encryption is X, the value of 32 bits which is the signal after the first encryption is F (X). express.

Further, the encryption unit 11 has a second encryption method different from the first encryption method, in which the signal output from the CPU 30 has a one-to-one reversible correspondence between the ciphertext and the plaintext in the address unit of the memory 20. Encrypt with the encryption method.

FIG. 3B is a schematic diagram showing the relationship between the ciphertext and the plaintext in the second encryption method.

Here, it is assumed that the second encryption method is a circular shift (rotation) for each address of the memory 20. However, the second encryption method is not necessarily circular if it is an encryption method different from the first encryption method in which the ciphertext and the plaintext have a reversible one-to-one correspondence in the address unit of the memory 20. It does not have to be limited to a configuration that is a shift. For example, an encryption method may be used in which the order of the bits is reversed. Further, although the example here is a case where the word length of the memory 20 is 32 bits, the word length of the memory 20 is not necessarily limited to 32 bits. For example, the word length of the memory 20 may be 16 bits.

As shown in FIG. 3B, here, the second encryption method is a circular shift of the left 3 bits, which is performed in units of 32 bits, which is an address unit of the memory 20.

In the following, in order to make the explanation easier to understand, when the 32-bit value of the signal before the second encryption is Y, the 32-bit value of the signal after the second encryption is G (Y). express.

The flag storage unit 13 stores a first flag consisting of one bit and a second flag consisting of one bit corresponding to each address of the memory 20. Here, it is assumed that the first flag is in the active state when the logical value of the first flag is 1, and the first flag is in the inactive state when the logical value of the first flag is 0, but vice versa. That is, when the logical value of the first flag is 0, the first flag may be in the active state, and when the logical value of the first flag is 1, the first flag may be in the inactive state. Similarly, here, it is assumed that the second flag is in the active state when the logical value of the second flag is 1, and the second flag is in the inactive state when the logical value of the second flag is 0. However, the opposite, that is, the second flag may be in the active state when the logical value of the second flag is 0, and the second flag may be in the inactive state when the logical value of the second flag is 1. ..

Here, it is assumed that the first flag and the second flag are inactive in the initial state.

Although the flag storage unit 13 is described here as being included inside the encryption device 10, it is not necessarily limited to the configuration included inside the encryption device 10. For example, the flag storage unit 13 may be realized as a part of the storage area of the memory 20.

The flag update unit 14 updates the first flag and the second flag corresponding to each address of the memory 20.

More specifically, the flag updating unit 14 is (1) a first unit corresponding to an address to be written when the ciphertext by the first encryption method of the program output from the recording medium 40 is written to the memory 20. Activates the flag. Further, the flag updating unit 14 activates (2) the second flag corresponding to the written address when the ciphertext by the second encryption method of the signal output from the CPU 30 is written to the memory 20. .. Further, the flag update unit 14 writes (3) when the ciphertext of the program output from the recording medium 40 by the first encryption method is written to the memory 20 when the second flag is in the active state. The second flag corresponding to the address is set to the inactive state. Then, the flag update unit 14 (4) is an address to be written when the ciphertext by the second encryption method of the signal output from the CPU 30 is written to the memory 20 when the second flag is in the active state. The first flag corresponding to is inactive.

The decoding unit 12 converts the signal output from the memory 20 into the first decoding method, which is the reverse conversion of the first encryption method, or the reverse conversion of the second encryption method, in units of addresses of the memory 20. 2 Decrypt by the decryption method.

FIG. 4A is a schematic diagram showing the relationship between the ciphertext and the plaintext in the first decryption method.

As described above, the first decryption method is an inverse conversion of the first encryption method. Therefore, here, the first decoding method is a circular shift of two bits to the right, which is performed in units of 32 bits, which is an address unit of the memory 20.

In the following, for the sake of clarity, the 32-bit value of the signal after the first decoding is F ^-1 (X) when the 32-bit value of the signal before the first decoding is X. ) May be expressed.

Further, since the first decryption method is the inverse conversion of the first encryption method,
F ^-1 {F (X)} = X
Will be.

FIG. 4B is a schematic diagram showing the relationship between the ciphertext and the plaintext in the second decryption method.

As described above, the second decryption method is an inverse conversion of the second encryption method. Therefore, here, the second decoding method is a circular shift of the right 3 bits, which is performed in units of 32 bits, which is an address unit of the memory 20.

In the following, for the sake of clarity, the 32-bit value of the signal after the second decoding is G ^-1 (Y) when the 32-bit value of the signal before the second decoding is Y. ) May be expressed.

Further, since the second decryption method is the inverse conversion of the second encryption method,
G ^-1 {G (Y)} = Y
Will be.

More specifically, in the decoding unit 12, (1) when the signal is read from the memory 20, the first flag corresponding to the address of the signal is active and the first flag corresponding to the address is active. 2 When the flag is in the inactive state, the signal is decoded by the first decoding method. Further, in the decoding unit 12, (2) when the signal is read from the memory 20, the first flag corresponding to the address of the signal is active and the second flag corresponding to the address is active. In the state, if the read destination of the signal is the CPU 30, the signal is decoded by the first decoding method, and if the read destination of the signal is the recording medium 40, the signal is decoded by the second decoding method. Decrypt with. Then, in the decoding unit 12, (3) when the signal is read from the memory 20, the first flag corresponding to the address of the signal is inactive, and the second flag corresponding to the address is set. When in the active state, the signal is decoded by the second decoding method.

The encryption method setting unit 15 receives an operation from the outside and sets the first encryption method and the first decryption method, or the second encryption method and the second decryption method according to the accepted operation. ..

For example, the encryption method setting unit 15 may include a touch panel and accept an operation from the outside by accepting a touch operation from a user who uses the encryption device 10. Further, the encryption method setting unit 15 may include, for example, a communication circuit capable of communicating with an external device (for example, a smartphone), and may accept an operation from the outside by receiving an operation signal from the external device. Further, the encryption method setting unit 15 may include, for example, a DIP switch and accept an operation from the outside by accepting a switch switching operation from a user who uses the encryption device 10.

However, it is desirable that the operation accepted by the encryption method setting unit 15 does not include the operation by the CPU 30. This is to prevent a security hole in the encryption system 1 that may occur by accepting a malicious operation by the CPU 30.

Hereinafter, the operation performed by the encryption system 1 having the above configuration will be described with reference to the drawings.

[2. motion]
First, the operation of the encryption system 1 when the CPU 30 tries to execute the program loaded from the recording medium 40 into the memory 20 (hereinafter, referred to as “case 1”) will be described.

FIG. 5 is a schematic diagram showing the operation of the encryption system 1 in the case 1.

As shown in FIG. 5, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit 11 encrypts the signal by the first encryption method, and the value is obtained. Generates a signal of F (X). Then, a signal having a value of F (X) is written to the write address of the memory 20 (hereinafter, referred to as “address A”). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address A from the initial state (0,0) to (1,0).

After that, when a signal having a value of F (X) is read from the address A of the memory 20 for use by the CPU 30, the decoding unit 12 sets the first flag and the second flag corresponding to the address A. Since it is (1, 0), the signal is decoded by the first decoding method, and a signal having a value of F ^-1 {F (X)}, that is, X is generated. Therefore, the CPU 30 uses the signal (program) restored to the state originally recorded on the recording medium 40.

As described above, in Case 1, the CPU 30 can correctly execute the program loaded from the recording medium 40 into the memory 20.

Next, encryption in the case where the data written from the recording medium 40 to the disk cache area of the memory 20 is to be written back to the recording medium 40 without updating the value (hereinafter referred to as "case 2"). The operation of the system 1 will be described.

FIG. 6 is a schematic diagram showing the operation of the encryption system 1 in the case 2.

As shown in FIG. 6, when a signal (data) having a value of X is output from the recording medium 40, the encryption unit 11 encrypts the signal by the first encryption method, and the value is obtained. Generates a signal of F (X). Then, a signal having a value of F (X) is written to the write address of the memory 20 (hereinafter, referred to as “address B”). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address B from the initial state (0,0) to (1,0).

After that, when a signal having a value of F (X) is read from the address A of the memory 20 in order to write back to the recording medium 40, the decoding unit 12 receives the first flag and the second flag corresponding to the address A. Since the flag is (1, 0), the signal is decoded by the first decoding method, and a signal having a value of F ^-1 {F (X)}, that is, X is generated. As a result, the recording medium 40 is written back with the signal (data) restored to the state originally recorded on the recording medium 40.

As described above, in the case 2, the recording medium 40 is correctly written back.

Next, the encryption in the case where the data written from the recording medium 40 to the disk cache area of the memory 20 is to be written back to the recording medium 40 after the CPU 30 updates the value (hereinafter referred to as “case 3”). The operation of the system 1 will be described.

FIG. 7 is a schematic diagram showing the operation of the encryption system 1 in the case 3.

As shown in FIG. 7, when a signal (data) having a value of X is output from the recording medium 40, the encryption unit 11 encrypts the signal by the first encryption method, and the value is obtained. Generates a signal of F (X). Then, a signal having a value of F (X) is written to the write address of the memory 20 (hereinafter, referred to as “address C”). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address C from the initial state (0,0) to (1,0).

After that, when a signal (data) having a value of Y is output from the CPU 30, the encryption unit 11 encrypts the signal by the second encryption method, and the signal has a value of G (Y). To generate. Then, a signal having a value of G (Y) is written to the address C. That is, it is overwritten and updated with a signal whose value is G (Y). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address C from (1, 0) to (1, 1).

After that, when a signal having a value of G (Y) is read from the address C of the memory 20 in order to write back to the recording medium 40, the decoding unit 12 receives the first flag and the second flag corresponding to the address C. Since the flag is (1, 1) and the read destination is the recording medium 40, the signal is decoded by the second decoding method, and the value is G ^-1 {G (Y)}, that is. , Y to generate a signal. As a result, the recording medium 40 is written back with the signal (data) restored to the state originally output from the CPU 30.

As described above, in the case 3, the recording medium 40 is correctly written back.

Next, in a case where the CPU 30 attempts to execute the illegal program after the CPU 30 rewrites the program loaded from the recording medium 40 into the memory 20 into an invalid program (hereinafter referred to as "case 4"). The operation of the encryption system 1 will be described.

FIG. 8 is a schematic diagram showing the operation of the encryption system 1 in the case 4.

As shown in FIG. 8, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit 11 encrypts the signal by the first encryption method, and the value is obtained. Generates a signal of F (X). Then, a signal having a value of F (X) is written to the write address of the memory 20 (hereinafter, referred to as “address D”). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address D from the initial state (0,0) to (1,0).

After that, when a signal (illegal program) having a value of Y is output from the CPU 30, the encryption unit 11 encrypts the signal by the second encryption method, and the value becomes G (Y). Generates a signal that Then, a signal having a value of G (Y) is written to the address D. That is, it is overwritten and updated with a signal whose value is G (Y). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address D from (1, 0) to (1, 1).

After that, when a signal having a value of G (Y) is read from the address D of the memory 20 for use by the CPU 30, the decoding unit 12 sets the first flag and the second flag corresponding to the address D. (1, 1), and since the read destination is the CPU 30, the signal is decoded by the first decoding method, and a signal having a value of F ^-1 {G (Y)} is generated. ..

The signal of F ^-1 {G (Y)} is a signal different from that of an invalid program having a value of Y. As a result, the CPU 30 does not execute an illegal program whose value is Y.

Thus, in Case 4, the CPU 30 does not execute the malicious program.

At this time, it is desirable that the signal whose value is F ^-1 {G (Y)} is a signal that is not executed by the CPU 30. That is, the relationship between the instruction set of the CPU 30 and the first encryption method and the second encryption method is that any program that can be executed by the CPU 30 is encrypted by the second encryption method and then by the first decryption method. When decoded, it is desirable that the decoded signal becomes a signal that cannot be executed by the CPU 30.

Next, after the CPU 30 writes an invalid program in the memory 20, the malicious program is updated by the program loaded from the recording medium 40 into the memory 20, and then the CPU 30 attempts to execute the updated program. The operation of the encryption system 1 in this case (hereinafter referred to as "case 5") will be described.

FIG. 9 is a schematic diagram showing the operation of the encryption system 1 in the case 5.

As shown in FIG. 9, when a signal (illegal program) having a value of Y is output from the CPU 30, the encryption unit 11 encrypts the signal by the second encryption method, and the value is obtained. Generates a signal of G (Y). Then, a signal having a value of G (Y) is written to the write address of the memory 20 (hereinafter, referred to as “address E”). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address E from the initial state (0, 0) to (0, 1).

After that, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit 11 encrypts the signal by the first encryption method, and the value becomes F (X). Generates a signal that Then, a signal having a value of F (X) is written to the address E. That is, it is overwritten and updated with a signal whose value is F (X). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address E from (0, 1) to (1, 0).

After that, when a signal having a value of F (X) is read from the address E of the memory 20 for use by the CPU 30, the decoding unit 12 sets the first flag and the second flag corresponding to the address E. Since it is (1, 0) and the read destination is the CPU 30, the signal is decoded by the first decoding method, and the value becomes F ^-1 {F (X)}, that is, X. Generate a signal.

As described above, in the case 5, the CPU 30 can correctly execute the program loaded from the recording medium 40 into the memory 20.

Next, when the program loaded from the recording medium 40 into the memory 20 is initialized by the CPU 30, data is written as a work area by the CPU 30, and then the data is to be used by the CPU 30 (hereinafter, "" The operation of the encryption system 1 in (referred to as case 6) will be described.

FIG. 10 is a schematic diagram showing the operation of the encryption system 1 in the case 6.

As shown in FIG. 10, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit 11 encrypts the signal by the first encryption method, and the value is obtained. Generates a signal of F (X). Then, a signal having a value of F (X) is written to the write address of the memory 20 (hereinafter, referred to as “address F”). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address F from the initial state (0,0) to (1,0).

After that, when a signal (initialization data) having a value of Y is output from the CPU 30, the encryption unit 11 encrypts the signal by the second encryption method, and the value becomes G (Y). Generates a signal that Then, a signal having a value of G (Y) is written to the address F. That is, it is overwritten and updated with a signal whose value is G (Y). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address F from (1, 0) to (1, 1).

After that, when a signal (work data) having a value of Z is output from the CPU 30, the encryption unit 11 encrypts the signal by the second encryption method, and the value becomes G (Z). Generate a signal. Then, a signal having a value of G (Z) is written to the address F. That is, it is overwritten and updated with a signal whose value is G (Z). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address F from (1, 1) to (0, 1).

After that, when a signal having a value of G (Z) is read from the address F of the memory 20 for use by the CPU 30, the decoding unit 12 sets the first flag and the second flag corresponding to the address F. (0, 1), and since the read destination is the CPU 30, the signal is decoded by the second decoding method, and the value becomes G ^-1 {G (Z)}, that is, Z. Generate a signal.

As described above, in the case 6, the CPU 30 can correctly use the data written as the work area.

[3. effect]
According to the encryption device 10 having the above configuration, as shown in Cases 4 and 5, even if a malicious program is written in the memory 20 that stores the program to be executed by the CPU 30, the CPU has the malicious program written in the memory 20. 30 can deter the execution of the malicious program.

Further, according to the encryption device 10 having the above configuration, as shown in Case 1, Case 2, Case 3, and Case 6, a malicious program is not written in the memory 20 that stores the program to be executed by the CPU 30. In that case, the CPU 30 operates normally.

(supplement)
As described above, embodiments have been described as an example of the techniques disclosed in this application. However, the technique according to the present invention is not limited to these, and can be applied to embodiments in which changes, replacements, additions, omissions, etc. are made as appropriate.

Hereinafter, an example of a modification of the present invention will be described.

In the embodiment, the encryption unit 11 is different from the first encryption method in which the signal output from the CPU 30 has a reversible one-to-one correspondence between the ciphertext and the plaintext in the address unit of the memory 20. It has been described as an example of a configuration in which encryption is performed by the second encryption method.

On the other hand, in this modification, the encryption unit according to the modification is an example of a configuration in which no conversion is performed on the signal output from the CPU 30. In other words, the encryption unit according to the modified example is an example of a configuration in which the ciphertext and the plaintext are converted to be equal as the second encryption method.

Here, in the second encryption method, since the ciphertext and the plaintext are equal, the 32-bit signal after the second encryption is obtained when the value of the 32-bit signal before the second encryption is Y. When the value of is expressed as G (Y),
G (Y) = Y
Will be.

Further, here, since the second decoding method is the inverse conversion of the second encryption method, the value of 32 bits, which is the signal before the second decoding, is set to Y, and the value after the second decoding is set to Y. When the value of 32 bits, which is a signal, is expressed as G ^-1 (Y), G ^-1 (Y) = Y.
Will be.

That is, in this modification, in the decoding unit according to the modification, (1) when the signal is read from the memory 20, the first flag corresponding to the address of the signal is active and the address is the address. When the second flag corresponding to is in the inactive state, the signal is decoded by the first decoding method. Further, in the decoding unit according to the modified example, (2) when the signal is read from the memory 20, the first flag corresponding to the address of the signal is active and the second flag corresponding to the address is active. When the flag is in the active state, if the read destination of the signal is the CPU 30, the signal is decoded by the first decoding method, and if the read destination of the signal is the recording medium 40, the signal is decoded. Does not convert anything. Then, in the decoding unit according to the embodiment, (3) when the signal is read from the memory 20, the first flag corresponding to the address of the signal is inactive and corresponds to the address. When the second flag is in the active state, nothing is converted for the signal.

According to the encryption device according to the modification, which includes the encryption unit according to the modification instead of the encryption unit 11 and the decryption unit according to the modification instead of the decryption unit 12, the encryption device 10 Similarly, as shown in Cases 4 and 5, even if a malicious program is written in the memory 20 that stores the program to be executed by the CPU 30, the malicious program by 30 is written to the CPU. Can be suppressed.

Further, according to the encryption device according to this modification, as shown in Case 1, Case 2, Case 3, and Case 6, the memory 20 that stores the program to be executed by the CPU 30 is stored, as in the case of the encryption device 10. If no malicious program is written to the CPU 30, the CPU 30 operates normally.

Hereinafter, in each of the cases 1 to 6, the operation performed by the encryption system according to the modification, which includes the encryption device according to the modification instead of the encryption device 10, will be described.

In the cases of Case 1 and Case 2, encryption by the second encryption method and decryption by the second decryption method are not performed. Therefore, the encryption system according to the modified example operates in the same manner as the encryption system 1.

In the case of Case 3, when a signal (data) having a value of X is output from the recording medium 40, the encryption unit according to the modified example encrypts the signal by the first encryption method. , Generates a signal with a value of F (X). Then, a signal having a value of F (X) is written to the write address C of the memory 20. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address C from the initial state (0,0) to (1,0).

After that, when a signal (data) having a value of Y is output from the CPU 30, the encryption unit according to the modified example does not perform encryption. Then, a signal having a value of Y is written to the address C. That is, it is overwritten and updated with a signal whose value is Y. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address C from (1, 0) to (1, 1).

After that, when a signal having a value of Y is read from the address C of the memory 20 in order to write back to the recording medium 40, the decoding unit according to the modified example has the first flag and the second flag corresponding to the address C. Since the flag is (1, 1) and the read destination is the recording medium 40, the signal is not decoded. As a result, the recording medium 40 is written back with a signal (data) whose value originally output from the CPU 30 is Y.

As described above, in the case 3, the recording medium 40 is correctly written back.

In the case of Case 4, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit according to the modified example encrypts the signal by the first encryption method. , Generates a signal with a value of F (X). Then, a signal having a value of F (X) is written to the write address D of the memory 20. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address D from the initial state (0,0) to (1,0).

After that, when a signal (illegal program) having a value of Y is output from the CPU 30, the encryption unit according to the modified example does not perform encryption. Then, a signal having a value of Y is written to the address D. That is, it is overwritten and updated with a signal whose value is Y. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address D from (1, 0) to (1, 1).

After that, when a signal having a value of Y is read from the address D of the memory 20 for use by the CPU 30, the decoding unit according to the modification sets the first flag and the second flag corresponding to the address D. Since the reading destination is the CPU 30 in (1), the signal is decoded by the first decoding method, and a signal having a value of F ^-1 (Y) is generated.

The signal of F ^-1 (Y) is a signal different from that of an invalid program having a value of Y. As a result, the CPU 30 does not execute an illegal program whose value is Y.

Thus, in Case 4, the CPU 30 does not execute the malicious program.

At this time, it is desirable that the signal having a value of F ^-1 (Y) is a signal that is not executed by the CPU 30. That is, the relationship between the instruction set of the CPU 30 and the first encryption method is that when an arbitrary program that can be executed by the CPU 30 is decoded by the first decryption method, the decoded signal is executed by the CPU 30. It is desirable that the relationship results in an impossible signal.

In the case of Case 5, when a signal (illegal program) having a value of Y is output from the CPU 30, the encryption unit according to the modified example does not perform encryption. Then, a signal having a value of Y is written to the write address E of the memory 20. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address E from the initial state (0, 0) to (0, 1).

After that, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit according to the modified example encrypts the signal by the first encryption method, and the value is F ( X) is generated. Then, a signal having a value of F (X) is written to the address E. That is, it is overwritten and updated with a signal whose value is F (X). On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address E from (0, 1) to (1, 0).

After that, when a signal having a value of F (X) is read from the address E of the memory 20 for use by the CPU 30, the decoding unit according to the modified example has the first flag corresponding to the address E, the first flag. Since the 2 flag is (1, 0) and the read destination is the CPU 30, the signal is decoded by the first decoding method, and the value is F ^-1 {F (X)}, that is, Generate a signal that becomes X.

As described above, in the case 5, the CPU 30 can correctly execute the program loaded from the recording medium 40 into the memory 20.

In the case of Case 6, when a signal (program) having a value of X is output from the recording medium 40, the encryption unit according to the modified example encrypts the signal by the first encryption method. , Generates a signal with a value of F (X). Then, a signal having a value of F (X) is written to the write address F of the memory 20. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address F from the initial state (0,0) to (1,0).

After that, when a signal (initialization data) having a value of Y is output from the CPU 30, the encryption unit according to the modified example does not perform encryption. Then, a signal having a value of Y is written to the address F. That is, it is overwritten and updated with a signal whose value is Y. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address F from (1, 0) to (1, 1).

After that, when a signal (work data) having a value of Z is output from the CPU 30, the encryption unit 11 according to the modified example does not perform encryption. Then, a signal having a value of Z is written to the address F. That is, it is overwritten and updated with a signal whose value is Z. On the other hand, the flag updating unit 14 updates the first flag and the second flag corresponding to the address F from (1, 1) to (0, 1).

After that, when a signal having a value Z is read from the address F of the memory 20 for use by the CPU 30, the decoding unit 12 sets the first flag and the second flag (0,) corresponding to the address F. 1), and since the read destination is the CPU 30, decoding is not performed.

As described above, in the case 6, the CPU 30 can correctly use the data written as the work area.

The present invention can be widely used in an encryption device, an encryption system, and an encryption method for encrypting a signal written in a memory.

1 Encryption system 10 Encryption device 11 Encryption unit 12 Decryption unit 13 Flag storage unit 14 Flag update unit 15 Encryption method setting unit 20 Memory 30 CPU
40 Recording medium

Claims (9)

An encryption device that encrypts programs that are written to memory.
Encryption that encrypts the program output from the recording medium, including the instructions executed by the CPU, by the first encryption method, which has a one-to-one correspondence between the ciphertext and the plaintext in units of the memory addresses. Department and
A decoding unit for decoding a signal read from the memory by the first decoding method, which is an inverse conversion of the first encryption method, is provided for each address of the memory.
Further, it is provided with a flag update unit for updating the first flag and the second flag corresponding to each address of the memory.
Further, the encryption unit is different from the first encryption method in which the signal output from the CPU has a one-to-one correspondence between the ciphertext and the plaintext in the address unit of the memory. Encrypt with encryption method,
The flag updater activates (1) the first flag corresponding to the address to be written when the encrypted text of the program output from the recording medium by the first encryption method is written to the memory. (2) When the ciphertext by the second encryption method of the signal output from the CPU is written to the memory, the second flag corresponding to the written address is set to the active state (3). When the second flag is in the active state, the second code corresponding to the address to be written when the encryption text of the program output from the recording medium by the first encryption method is written to the memory. The flag is set to the inactive state, and (4) when the second flag is in the active state, the signal output from the CPU is written when the encrypted text by the second encryption method is written to the memory. The first flag corresponding to the address is set to the inactive state.
In the decoding unit, (1) when a signal is read from the memory, the first flag corresponding to the address of the signal is in the active state, and the second flag corresponding to the address is not. When the signal is decoded by the first decoding method while in the active state, (2) when the signal is read from the memory, the first flag corresponding to the address of the signal is in the active state. If the read destination of the signal is the CPU when the second flag corresponding to the address is in the active state, the signal is decoded by the first decoding method and the read destination of the signal is read. If is the recording medium, the signal is decoded by the second decoding method, which is the reverse conversion of the second encryption method, and (3) when the signal is read out from the memory, the signal of the signal is decoded. When the first flag corresponding to the address is inactive and the second flag corresponding to the address is active, the signal is decoded by the second decoding method.
Cryptographic device. The encryption device according to claim 1, wherein the first encryption method is a circular shift in units of addresses. The relationship between the instruction set of the CPU and the first encryption method is that any program conforming to the instruction set, which can be executed by the CPU, is the inverse conversion of the first encryption method . The encryption device according to claim 1 or 2, wherein the decrypted signal becomes a signal that cannot be executed by the CPU when the decryption method is used. The encryption device according to claim 1 , wherein the second encryption method is a circular shift in units of addresses. The relationship between the instruction set of the CPU, the first encryption method, and the second encryption method is such that any program conforming to the instruction set, which can be executed by the CPU, can be executed by the second encryption method. A claim that the decoded signal becomes a signal that cannot be executed by the CPU when it is encrypted and then decoded by the first decoding method , which is the reverse conversion of the first encryption method. Item 4. The encryption device according to Item 1 . Further, an encryption method that accepts an operation from the outside and sets the first encryption method and the first decryption method, or the second encryption method and the second decryption method according to the operation. The encryption device according to any one of claims 1, 4 to 5 , further comprising a setting unit. The encryption device according to claim 6 , wherein the operation accepted by the encryption method setting unit does not include the operation by the CPU. It includes a CPU, a memory, a recording medium, and an encryption device that encrypts a program written in the memory.
The encryption device is
An encryption unit that encrypts a program output from the recording medium and including an instruction executed by the CPU by the first encryption method in which the ciphertext and the plaintext have a one-to-one correspondence with each address of the memory. When,
A decoding unit that decodes a signal read from the memory by the first decoding method, which is an inverse conversion of the first encryption method, for each address of the memory.
Further, it includes a flag update unit for updating the first flag and the second flag corresponding to each address of the memory.
Further, the encryption unit is different from the first encryption method in which the signal output from the CPU has a one-to-one correspondence between the ciphertext and the plaintext in the address unit of the memory. Encrypt with encryption method,
The flag updater activates (1) the first flag corresponding to the address to be written when the encrypted text of the program output from the recording medium by the first encryption method is written to the memory. (2) When the ciphertext by the second encryption method of the signal output from the CPU is written to the memory, the second flag corresponding to the written address is set to the active state (3). When the second flag is in the active state, the second code corresponding to the address to be written when the encryption text by the first encryption method of the program output from the recording medium is written to the memory. The flag is set to the inactive state, and (4) when the second flag is in the active state, the signal output from the CPU is written when the encrypted text by the second encryption method is written to the memory. The first flag corresponding to the address is set to the inactive state.
In the decoding unit, (1) when a signal is read from the memory, the first flag corresponding to the address of the signal is in the active state, and the second flag corresponding to the address is not. When the signal is decoded by the first decoding method while in the active state, (2) when the signal is read from the memory, the first flag corresponding to the address of the signal is in the active state. If the read destination of the signal is the CPU when the second flag corresponding to the address is in the active state, the signal is decoded by the first decoding method and the read destination of the signal is read. If is the recording medium, the signal is decoded by the second decoding method, which is the reverse conversion of the second encryption method, and (3) when the signal is read out from the memory, the signal of the signal is decoded. When the first flag corresponding to the address is inactive and the second flag corresponding to the address is active, the signal is decoded by the second decoding method.
Cryptographic system. An encryption method that encrypts a program that writes to memory.
An encryption step of encrypting a program output from a recording medium including at least an instruction executed by a CPU by a first encryption method in which a ciphertext and a plaintext have a one-to-one correspondence for each address of the memory. ,
A decoding step of decoding a signal read from the memory by the first decoding method, which is an inverse conversion of the first encryption method, is included in the address unit of the memory.
Further, it includes a flag update step for updating the first flag and the second flag corresponding to each address of the memory.
In the encryption step, further, the signal output from the CPU has a one-to-one correspondence between the ciphertext and the plaintext in the address unit of the memory, which is different from the first encryption method. Encrypt with encryption method,
In the flag update step, (1) when the encryption text of the program output from the recording medium by the first encryption method is written to the memory, the first flag corresponding to the written address is activated. (2) When the ciphertext by the second encryption method of the signal output from the CPU is written to the memory, the second flag corresponding to the written address is set to the active state (3). When the second flag is in the active state, the second code corresponding to the address to be written when the encryption text by the first encryption method of the program output from the recording medium is written to the memory. The flag is set to the inactive state, and (4) when the second flag is in the active state, the signal output from the CPU is written when the encrypted text by the second encryption method is written to the memory. The first flag corresponding to the address is set to the inactive state.
In the decoding step, (1) when the signal is read from the memory, the first flag corresponding to the address of the signal is in the active state, and the second flag corresponding to the address is not. When the signal is decoded by the first decoding method while in the active state, (2) when the signal is read from the memory, the first flag corresponding to the address of the signal is in the active state. If the read destination of the signal is the CPU when the second flag corresponding to the address is in the active state, the signal is decoded by the first decoding method and the read destination of the signal is read. If is the recording medium, the signal is decoded by the second decoding method, which is the reverse conversion of the second encryption method, and (3) when the signal is read out from the memory, the signal of the signal is decoded. When the first flag corresponding to the address is inactive and the second flag corresponding to the address is active, the signal is decoded by the second decoding method.
Encryption method.

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