KR20180059217A - Apparatus and method for secure processing of memory data - Google Patents

Abstract

A security processing device for chip-level data is provided. The device comprises a PUF which provides a first value that is an unpredictable, random and time-invariant digital value using a semiconductor process variation; and a scrambler which performs a scrambling process between a processor and a memory associated with the processor by using the first value provided by the PUF.

Description

[0001] APPARATUS AND METHOD FOR SECURE PROCESSING OF MEMORY DATA [0002]

The present invention relates to a security processing apparatus and method for data in a memory, and more particularly, to a content for security processing of memory data using a PUF (Physically Unclonable Function).

Many factors are used to protect the digital data of a hardware chip for security (H / W chip). Illustratively, a security process such as an encryption process is performed to protect non-volatile memory (NVM) and RAM. Unlike a general encryption algorithm, a scheme called chip scramble is used instead of encryption.

At the chip level, using a block cipher algorithm between a processor and a memory (such as RAM or NVM) has a high security strength. However, if one byte within a block changes its value, the entire block must be decrypted and then re- There is a performance degradation.

On the other hand, the PUF can provide unpredictable digital values. Although the individual PUFs are given an exact manufacturing process and are manufactured in the same process, the digital values provided by the individual PUFs are different. The PUF may be referred to as a physical one-way function practically impossible to duplicated (POWF).

The non-replicable nature of this PUF may be used to generate an identifier of the device for security and / or authentication. For example, a PUF may be used to provide a unique key to distinguish devices from one another. Exemplary contents on how to implement a PUF are presented in the following prior art documents.

(Patent Document 1) KR1139630 10

(Patent Document 2) KR0926214 10

According to one aspect, the PUF provides a first value, which is a random, time-invariant digital value that is unpredictable using semiconductor process variations; And a scrambler scrambling the memory between the processor and the memory associated with the processor using the first value provided by the PUF.

According to one embodiment, the scrambler includes an address scrambler that performs address scrambling between the processor and the memory using the first value.

According to one embodiment, the scrambler includes a data scrambler that scrambles data between the processor and the memory using the first value.

According to another aspect, there is provided a method comprising: providing a PUF included in a chip, the first value being an unpredictable random time-invariant digital value resulting from a semiconductor process variation; And scrambling the scrambler included in the chip between the processor and the memory associated with the processor using the first value provided by the PUF.

According to one embodiment, the scrambling step includes an address scrambler included in the chip performing address scrambling between the processor and the memory using the first value.

According to one embodiment, the scrambling step comprises a data scrambler included in the chip performing data scrambling between the processor and the memory using the first value.

1 is a block diagram of a memory data security processing apparatus according to an embodiment.
2 is an exemplary circuit diagram of a memory data security processing apparatus according to an embodiment.
3 is an exemplary circuit diagram of a memory data security processing apparatus according to another embodiment.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the rights is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

The terms used in the following description are chosen to be generic and universal in the art to which they are related, but other terms may exist depending on the development and / or change in technology, customs, preferences of the technician, and the like. Accordingly, the terminology used in the following description should not be construed as limiting the technical thought, but should be understood in the exemplary language used to describe the embodiments.

Also, in certain cases, there may be a term chosen arbitrarily by the applicant, in which case the meaning of the detailed description in the corresponding description section. Therefore, the term used in the following description should be understood based on the meaning of the term, not the name of a simple term, and the contents throughout the specification.

1 is a block diagram of a memory data security processing apparatus according to an embodiment.

At the chip level, scrambled security processing is performed for memory data security. Scrambles can be arranged by replacing address and data signals or by using simple methods such as specific bit inverse, xor, addition, substitution, or by using functions created by block cipher or hash functions.

Scrambles of NVM are often designed so that all chips are the same, and a scramble of RAM scrambles other data by chip (determines the scramble method), such as the serial number of the NVM.

Even if the scramble method is used, the contents of the circuit and the NVM can be analyzed by reverse engineering to analyze the scramble method (algorithm) and analyze the NVM to know the original data to be hidden.

RAM may be scrambled differently by chip using NVM as described above, but if scramble circuit and NVM can be analyzed, such scramble can also be attacked.

If you encrypt the NVM, RAM, and bus with PUF as the key, you will not be able to figure out the contents until you know the PUF value.

Unlike scramble method in one chip and analyzing chip of attack object, scramble with PUF key, unlike secret data, can find out scramble algorithm (method) Can not be analyzed.

Therefore, in the case of general data, scramble encryption is used. In this case, if PUF is used, data can not be obtained until the PUF value is known.

Scramble can use one or both of converting the address and changing the storage location, or converting the data into byte or word units.

If the parameter that converts the address is also used in the parameter that converts the data, the data can be encrypted differently for different addresses, which can enhance the security.

Since NVM, RAM, and bus are H / W resources, most of them use the shear function (1: 1 correspondence) as the conversion method.

For example, using 9bits to store 8 bits of data increases security but increases chip size and costs.

Therefore, 8bits of storage space or bus is used to store 8bits of data is converted using the shear function.

Addresses often use shear functions to save resources.

Some embodiments involve a case where the original capacity and the storage capacity are the same using a shear function. However, other embodiments include the use of a compression function that requires a storage capacity that is larger than the capacity of the original data, or a compression function that requires only a storage capacity smaller than the capacity of the original data.

Since the converted value must be transferred to the CPU or H / W logic, it must be converted within the fetch time or a signal indicating that the conversion is completed.

2 is an exemplary circuit diagram of a memory data security processing apparatus according to an embodiment. In the embodiment shown in FIG. 2, Bus = Bus xor PUF Key is a method of determining whether to invert the value of the Bus by the PUF Key. Bus 0 = Bus 0 xor (Bus 1 and PUF Key) It is a method to decide whether to xor the value.

The second method can be used to eliminate linearity and can be used to exchange buses.

A? A? B (A? A0? B0)

B ← A ^ B (B ← (A0 ^ B0) ^ B0 = A0)

A ← A ^ B (A ← (A0 ^ B0) ^ A0 = B0)

Designing the circuit so that it can exchange A and B Bus.

Here you can control the exchange with the PUF key.

3 is an exemplary circuit diagram of a memory data security processing apparatus according to another embodiment. An example of performing a scramble using a random function is to construct a random function using the PUF key and other parameters (upper address in case of address, address in case of data, etc.).

For example, suppose you have a system that uses 16 kbytes of RAM to configure your RAM. Then 16kbytes address is composed of 14 signal lines and data is composed of 8 signal lines.

Here, it is possible to control multiple PUFs by controlling one PUF bit to decide whether to combine lines 0 and 11 among 14 addresses, and to apply PUF in such a way that another PUF decides whether to combine lines 2 and 4 . Also, it can be implemented by XORing with the PUF line whether to invert the nth value among 14 addresses.

To eliminate the linearity of the data, a substitution process can be performed. The PUF bit can be used to change a value to another value.

The address line uses the same circuit for encryption and decryption because the address of the data to be used for encryption is the same as that of data to be decrypted.

When designing the decryption circuit of the data line, if the direct operation is performed on the signal line, the replacement logic is redesigned and the logic opposite to the encryption is redesigned, and the addition and subtraction are changed to subtraction.

But decrypts them in reverse to the order of encryption.

If it is scrambled using a random function as in the example of FIG. 3, it can be used as it is for decoding. The eight data signal lines can be better encrypted by encrypting the address signal line using PUF.

If you use the PUF used in the address, the data will be encrypted differently depending on the address, making it more difficult to analyze. This is an embodiment, and the number of address lines and data lines should be matched according to characteristics of CPU and RAM.

The scrambles of the NVM are often encrypted separately for each block unit that writes the NVM.

This means that if you save non-contiguous data when writing, all blocks that contain non-contiguous data need to be encrypted and re-stored, which can increase the execution time and shorten the lifetime.

For example, if the capacity is 16 kbytes and 32 bytes is written in blocks, the address signal line is encrypted by encrypting 9 to 5 to 13, and the remaining address signal lines 0 to 4 are separately encrypted with signals within 32 bytes, You only need to change the location and then encrypt the data.

In other words, a 32byte block scrambles an address and scrambles it only within its designated location if its location is set, so that it can be written at a time when it is actually written.

Thus, when writing one block of NVM, encryption can be performed in one block.

When writing to RAM, if it is designed to write in 2bytes or 4bytes, scramble 1 line or 2 lines separately at address as NVM.

Another advantage of the Scramble method is that it does not know where the encrypted data is located. However, a common scramble can be used to identify the location of a scramble by modifying a part of the same type of chip and analyzing it. However, since the scramble using the PUF is encrypted in the same way only on the same chip, even if the same model chip is obtained and analyzed, it is not helpful to analyze the scramble of the chip to be attacked.

It is also the subject of this patent to inject a key used externally and encrypt it with a PUF. In other words, if a code encrypted by scramble method is mass-produced and connected to an external flash memory, a chip can be recognized by injecting a scramble key from the outside into the chip.

This can also be used in applications where the scramble key is injected externally and encrypted using PUF when storing it. As such, RAM and NVM can be used for applications designed in the chip and for external applications.

The apparatus described above may be implemented as a hardware component, a software component, and / or a combination of hardware components and software components. For example, the apparatus and components described in the embodiments may be implemented within a computer system, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA) A programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing device may execute an operating system (OS) and one or more software applications running on the operating system. The processing device may also access, store, manipulate, process, and generate data in response to execution of the software. For ease of understanding, the processing apparatus may be described as being used singly, but those skilled in the art will recognize that the processing apparatus may have a plurality of processing elements and / As shown in FIG. For example, the processing unit may comprise a plurality of processors or one processor and one controller. Other processing configurations are also possible, such as a parallel processor.

The software may include a computer program, code, instructions, or a combination of one or more of the foregoing, and may be configured to configure the processing device to operate as desired or to process it collectively or collectively Device can be commanded. The software and / or data may be in the form of any type of machine, component, physical device, virtual equipment, computer storage media, or device , Or may be permanently or temporarily embodied in a transmitted signal wave. The software may be distributed over a networked computer system and stored or executed in a distributed manner. The software and data may be stored on one or more computer readable recording media.

The method according to an embodiment may be implemented in the form of a program command that can be executed through various computer means and recorded in a computer-readable medium. The computer-readable medium may include program instructions, data files, data structures, and the like, alone or in combination. The program instructions to be recorded on the medium may be those specially designed and configured for the embodiments or may be available to those skilled in the art of computer software. Examples of computer-readable media include magnetic media such as hard disks, floppy disks and magnetic tape; optical media such as CD-ROMs and DVDs; magnetic media such as floppy disks; Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those produced by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like. The hardware devices described above may be configured to operate as one or more software modules to perform the operations of the embodiments, and vice versa.

Although the embodiments have been described with reference to the drawings, various modifications and variations may be made by those skilled in the art. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (7)

A PUF that uses a semiconductor process variation to provide a first value that is an unpredictable random time constant digital value; And
A scrambler for scrambling between memories between a processor and a memory associated with the processor using the first value provided by the PUF;
And a memory device for storing the data. The method according to claim 1,
Wherein the scrambler comprises an address scrambler for performing address scrambling between the processor and the memory using the first value. The method according to claim 1,
Wherein the scrambler comprises a data scrambler that scrambles data between the processor and the memory using the first value. Providing a PUF included in the chip a first value which is an unpredictable random time-invariant digital value resulting from a semiconductor process variation; And
A scrambler included in the chip scrambling between memories between a processor and a memory associated with the processor using the first value provided by the PUF;
The method comprising the steps of: 5. The method of claim 4,
Wherein the scrambling step comprises an address scrambler included in the chip performing address scrambling between the processor and the memory using the first value. 5. The method of claim 4,
Wherein the scrambling step comprises a data scrambler included in the chip performing data scrambling between the processor and the memory using the first value. A computer-readable recording medium storing a program for performing the memory data security processing method according to any one of claims 4 to 6.

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