JP7090760B2 - Semiconductor devices, semiconductor device manufacturing methods, and power conversion devices - Google Patents

Description

The present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and a power conversion device.

Conventionally, inverter devices used in a wide range of fields such as home appliances, electric vehicles, and railways often drive inductive loads such as inductive motors. Inverter devices include switching elements such as IGBTs (insulated gate bipolar transistors) or MOSFETs (metal-oxide-semiconductor field-effect transistors), and semiconductor devices for power such as freewheeling diodes (hereinafter simply referred to as "diodes"). It is composed of individual pieces. Since inverter devices are required to have high efficiency and low power consumption, the market demands higher performance and lower cost of power semiconductor devices.

In order to improve the performance and cost of power semiconductor devices, a trench MOS gate structure, a thinner semiconductor substrate, and a reverse conduction type IGBT (RC-IGBT: Reverse) in which an IGBT and a diode are integrated in the same semiconductor substrate are integrated. Conducting IGBT) etc. have been developed.

Prior art documents relating to RC-IGBT include, for example, Patent Documents 1 to 4. Patent Document 1 discloses a semiconductor device in which a MOS transistor cell and a diode cell are provided side by side. The semiconductor device of Patent Document 1 includes a first trench and a second trench. A gate insulating film and a gate electrode are formed inside the first trench, and an emitter electrode is embedded inside the second trench.

Patent Document 2 discloses that the contact hole width of the diode operating region of the RC-IGBT is made wider than the contact hole width of the IGBT operating region.

Patent Document 3 proposes that the aluminum silicon of the emitter electrode and the semiconductor substrate are bonded to each other via a barrier metal and a tungsten plug in the IGBT region and directly bonded in the diode region.

Patent Document 4 discloses a configuration in which an anode layer and an aluminum electrode are directly bonded in a diode region without a tungsten plug. However, the first electrode in the diode region is a barrier metal such as titanium (Ti), titanium tungsten (TiW) or titanium nitride (TiN), while the first electrode in the IGBT region is aluminum, and the materials of both are different. Therefore, a problem arises in the assembly process using the semiconductor device. For example, the conditions of wire bonding must be changed. Further, in the manufacturing method, since a step of forming and removing aluminum is required before forming the barrier metal in the IGBT region, aluminum may diffuse to the base layer or etching damage may occur to the base layer. There is.

Japanese Unexamined Patent Publication No. 2009-027152 Japanese Patent No. 5937413 International Publication No. 2016/080269 JP-A-2015-106695

In the conventional RC-IGBT, a laminated structure of a semiconductor substrate, a barrier metal, a tungsten plug, and a surface electrode is provided in the IGBT region. This laminated structure is a structure generally configured in an IGBT, and is also provided in a diode region on the same semiconductor substrate. However, since the contact resistance between the p-type anode layer and the barrier metal is large in the diode region, a high-concentration p + type anode layer is provided between the p-type anode layer and the barrier metal as a countermeasure.

However, the higher the impurity concentration of the p + type anode layer, the larger the supply amount of carriers when the operation is on, so that there is a problem that the carrier discharge when the operation is off is significantly delayed.

In Patent Document 3, the barrier metal and the tungsten plug are used only in the IGBT region, and the aluminum silicon and the p-type anode layer are directly bonded in the diode region to solve the above-mentioned problems. However, since the tungsten plug is used in the IGBT region, there is a problem that the manufacturing cost is high.

Further, in Patent Document 4, although the tungsten plug is not used in the IGBT region, surface electrodes made of different materials are used in the IGBT region and the diode region. Therefore, in the assembly process using the semiconductor device, there is a problem that different process conditions must be applied, such as changing the wire bonding conditions between the IGBT region and the diode region.

The present invention has been made in view of the above problems, and an object of the present invention is to realize good diode characteristics and low cost in a semiconductor device in which a switching element region and a diode region are provided side by side on one semiconductor substrate.

The semiconductor device according to the present invention includes a semiconductor substrate, a first electrode, an interlayer insulating film, and a barrier metal. The semiconductor substrate has one main surface and the other main surface, has a first conductive type drift layer between one main surface and the other main surface, and constitutes a transistor from one main surface to the other main surface. It has a region and a diode region that constitutes a diode from one main surface to the other main surface. The first electrode extends over the transistor region and the diode region and is formed on one main surface of the semiconductor substrate. The transistor region is provided on one main surface side of the second conductive type first base layer provided on one main surface side of the semiconductor substrate and on one main surface side of the first base layer, and the upper surface constitutes one main surface. The second base layer, which is provided on one main surface side of the mold emitter layer and the first base layer, the upper surface thereof constitutes one main surface, and the impurity concentration is higher than that of the first base layer, and the emitter layer from the upper surface of the emitter layer. And a gate electrode provided through an insulating film inside a trench that penetrates the first base layer and reaches the drift layer. The diode region is provided on one main surface side of the semiconductor substrate, and the upper surface constituting the one main surface is in contact with the first electrode and includes a second conductive type anode layer that separates the drift layer and the first electrode. The interlayer insulating film has contact holes that cover the gate electrode and expose the upper surfaces of the second base layer and the emitter layer. The barrier metal is provided between the second base layer and the emitter layer and the first electrode in the contact hole, and comes into contact with the upper surface of the second base layer and the emitter layer and the first electrode.

In the semiconductor device according to the present invention, the semiconductor layer in the transistor region contacts the first electrode via the barrier metal, while the semiconductor layer in the diode region contacts the first electrode without passing through the barrier metal. Therefore, it is not necessary to provide a high-concentration anode layer in the diode region in order to lower the contact resistance, and good diode characteristics can be obtained. Further, since the first electrode enters the inside of the contact hole and comes into contact with the semiconductor layer of the MOS gate structure, an expensive plug contact such as a tungsten plug is not required, and the semiconductor device can be manufactured at low cost.

It is sectional drawing of the IGBT which concerns on the premise technique of this invention. It is sectional drawing of the diode which concerns on the premise technique of this invention. It is sectional drawing of RC-IGBT which concerns on the premise technique of this invention. It is sectional drawing of RC-IGBT which concerns on this invention. It is an enlarged view of the main part of RC-IGBT which concerns on this invention. It is a flowchart which shows the 1st manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 1st manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 1st manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 1st manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 1st manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 1st manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 1st manufacturing method of RC-IGBT which concerns on this invention. It is a flowchart which shows the 2nd manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 2nd manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 2nd manufacturing method of RC-IGBT which concerns on this invention. It is sectional drawing explaining the 2nd manufacturing method of RC-IGBT which concerns on this invention. It is a block diagram which shows the structure of the power conversion system to which the power conversion apparatus which concerns on this invention is applied.

Hereinafter, embodiments will be described with reference to the accompanying drawings. Since the drawings are schematically shown, the interrelationships between the sizes and positions of the images shown in the different drawings are not always accurate and may vary from time to time. Further, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description about them may be omitted.

Also, in the following description, terms such as "top", "bottom", "side", "bottom", "front" or "back" may be used to mean a specific position and direction. The term is used for convenience to facilitate understanding of the contents of the embodiment, and does not limit the direction in which it is actually implemented.

Further, the conductive type of the semiconductor will be described with the first conductive type as the n type and the second conductive type as the p type. However, these may be reversed, and the first conductive type may be p-type and the second conductive type may be n-type. Further, the n + type has a higher impurity concentration than the n type, and the n− type has a lower impurity concentration than the n type. Similarly, the p + type has a higher impurity concentration than the p type, and the p- type has a lower impurity concentration than the p type.

<A. Prerequisite technology>
As a prerequisite technique of the present invention, the configuration of a trench gate type IGBT, a diode, and an RC-IGBT will be described. First, a trench gate type IGBT will be described. FIG. 1 is a cross-sectional view of a trench gate type IGBT 101. The IGBT 101 includes an n-type drift layer 1, a p-type base layer 2, an n-type buffer layer 9, an n + type emitter layer 4, a gate insulating film 6, a gate electrode 7, a p-type collector layer 10, a p + type base layer 3, and an emitter. It includes an electrode 15, a barrier metal 12, a tungsten plug 14, and a collector electrode 16.

The p-type base layer 2 is formed on the upper surface of the n-type drift layer 1. An n + type emitter layer 4 and a p + type base layer 3 are selectively formed on the upper surface of the p-type base layer 2. The n + type emitter layer 4 is formed so as to surround the p + type base layer 3. An n-type buffer layer 9 and a p-type collector layer 10 are formed in this order on the lower surface of the n-type drift layer 1. A collector electrode 16 is formed on the lower surface of the p-type collector layer 10.

A plurality of trenches 5 are formed from the upper surface of the n + type emitter layer 4 through the n + type emitter layer 4 and the p-type base layer 2 to reach the n− type drift layer 1. A gate insulating film 6 and a gate electrode 7 are embedded in the inner wall of the trench 5. The gate electrode 7 faces the p-type base layer 2 via the gate insulating film 6.

The IGBT 101 realizes low loss by increasing the channel density by the trench MOS gate structure and thinning the n-type drift layer 1. When the n-type drift layer 1 is made thinner, a stopper for the depletion layer extending from the pn junction between the p-type base layer 2 and the n-type drift layer 1 is required at the time of switching off, so that the stopper is higher than that of the n-type drift layer 1. An n-type buffer layer 9 having a high impurity concentration is provided. However, the presence or absence of the n-type buffer layer 9 is determined by the product application, and the n-type buffer layer 9 may not be provided depending on the product application.

When the IGBT 101 is turned on, an n-channel MOSFET is formed by the p-type base layer 2, the n + type emitter layer 4, the gate insulating film 6, and the gate electrode 7, and the p-type collector layer 10, the n-type buffer layer 9, and the n-type drift are formed. A current flows through the path of the layer 1, the p-type base layer 2, and the n + type emitter layer 4. That is, the p-type base layer 2, the n + type emitter layer 4, the gate insulating film 6, and the gate electrode 7 have a transistor structure.

The upper surface of the gate electrode 7 is covered with an interlayer insulating film 11, whereby the gate electrode 7 and the emitter electrode 15 are insulated from each other. A contact hole 13 is formed in the interlayer insulating film 11, and the p + type base layer 3 and the n + type emitter layer 4 are exposed from the contact hole 13. The p + type base layer 3 has the effect of sweeping out carriers generated at the time of switching off and reducing the contact resistance with the emitter electrode 15.

A barrier metal 12 is formed on the interlayer insulating film 11 and on the inner wall of the contact hole 13. The barrier metal 12 contacts the upper surfaces of the p + type base layer 3 and the n + type emitter layer 4 in the contact hole 13. A tungsten plug 14 is embedded in the contact hole 13 from above the barrier metal 12. The tungsten plug 14 is used to realize miniaturization of design rules.

The barrier metal 12 is silicidized by contacting with a silicon semiconductor substrate, and has the effect of reducing the contact resistance with the n + type emitter layer 4 and the p + type base layer 3. Further, it has an effect of preventing the WF6 gas used for forming the tungsten plug 14 from reacting with the silicon semiconductor substrate and being chemically etched. When the tungsten plug 14 is used for the contact hole 13, the barrier metal 12 generally uses a multi-layer structure of a transition metal such as titanium or titanium nitride in order to obtain the above-mentioned effects.

An emitter electrode 15 is formed on the barrier metal 12 and the tungsten plug 14. An aluminum alloy is generally used for the emitter electrode 15. The emitter electrode 15 is bonded to the n + type emitter layer 4 and the p + type base layer 3 via the barrier metal 12 and the tungsten plug 14. The above is the configuration of the IGBT 101.

Next, the configuration of the diode will be described. FIG. 2 is a cross-sectional view of the diode 102. The diode 102 has a structure in which a cathode electrode 25, an n + type cathode layer 23, an n− type drift layer 1, a p-type anode layer 21, and an anode electrode 24 are laminated in this order.

For the anode electrode 24, an aluminum alloy that forms good ohmic contact with the p-type diffusion layer is generally used.

When the diode 102 is turned on, a current flows through the path of the p-type anode layer 21, the n-type drift layer 1, and the n + type cathode layer 23. That is, the p-type anode layer 21 and the n-type drift layer 1 have a diode structure.

Next, the configuration of the RC-IGBT will be described. FIG. 3 is a cross-sectional view of RC-IGBT103. The RC-IGBT 103 has a configuration in which an IGBT and a diode are built in the same semiconductor substrate, and the region in which the IGBT is built is the IGBT region 103A and the region in which the diode is built is the diode region 103B. A plurality of IGBT cells are collectively formed in the IGBT region 103A, and a plurality of diode cells are collectively formed in the diode region 103B.

In the IGBT region 103A, the RC-IGBT 103 has an n-type drift layer 1, a p-type base layer 2, a p + type base layer 3, an n + type emitter layer 4, a gate insulating film 6, a gate electrode 7, an n-type buffer layer 9, p. It includes a mold collector layer 10, a barrier metal 12, a tungsten plug 14, and an interlayer insulating film 11. These configurations are the same as the IGBT 101 shown in FIG.

Further, in the IGBT region 103A, the p + type base layer 3 and the n + type emitter layer 4 are joined to the first electrode 31 via the barrier metal 12 and the tungsten plug 14. The first electrode 31 is shared in the IGBT region 103A and the diode region 103B, and functions as an emitter electrode in the IGBT region 103A and an anode electrode in the diode region 103B. An aluminum alloy is generally used for the first electrode 31.

Further, in the IGBT region 103A, the second electrode 32 is formed on the lower surface of the p-type collector layer 10. The second electrode 32 is also formed in the diode region 103B, and is shared in the IGBT region 103A and the diode region 103B. The second electrode 32 functions as a collector electrode in the IGBT region 103A and a cathode electrode in the diode region 103B. An aluminum alloy is generally used for the second electrode 32.

The RC-IGBT 103 includes an n-type drift layer 1, a p-type anode layer 21, and an n + -type cathode layer 23 in the diode region 103B. These configurations are similar to the diode 102 shown in FIG. Further, the RC-IGBT 103 includes an n-type buffer layer 9 between the n-type drift layer 1 and the n + type cathode layer 23 in the diode region 103B, and a p + type anode layer 22 on the p-type anode layer 21. In the IGBT region 103A and the diode region 103B, the n-type drift layer 1 and the n-type buffer layer 9 are commonly used.

In the diode region 103B, a trench 5 is formed from the upper surface of the p + type anode layer 22 through the p + type anode layer 22 and the p-type anode layer 21 to reach the n− type drift layer 1. A gate insulating film 6 and a dummy gate electrode 26 are formed on the inner wall of the trench 5. The dummy gate electrode 26 is generally floating or grounded with the first electrode 31.

The interlayer insulating film 11, the barrier metal 12, and the tungsten plug 14 are provided in the diode region 103B as well as in the IGBT region 103A. That is, the first electrode 31 contacts the p + type anode layer 305 via the tungsten plug 14 and the barrier metal 12 in the diode region 103B. Here, when the barrier metal 12 and the p-type anode layer 21 are brought into direct contact with each other, the ohmic property is poor and the contact resistance is increased. Therefore, the high-concentration p + type anode layer 30 is intended to effectively reduce the contact resistance. ..

The above is the configuration of RC-IGBT103. As described above, the diode region 103B of the RC-IGBT 103 is provided with a high-concentration p + type anode layer 305 in order to reduce the contact resistance with the barrier metal 12. However, the higher the impurity concentration of the p + type anode layer 305, the larger the carrier supply amount when the diode is on, so that there is a problem that the carrier discharge is delayed when the diode is off.

<B. Embodiment 1>
In the first embodiment of the present invention, the above problem is solved by not forming a barrier metal in the diode region of the RC-IGBT.

<B-1. Configuration>
FIG. 4 is a cross-sectional view of RC-IGBT104, which is a semiconductor device according to the first embodiment of the present invention. The RC-IGBT 104 has an IGBT and a diode built in the same semiconductor substrate. The region in which the transistor of the RC-IGBT104 is built is referred to as the transistor region 104A, and the region in which the diode is built is referred to as the diode region 104B. Here, as the semiconductor substrate, for example, one containing silicon (Si) is used.

Compared with the configuration of RC-IGBT103 described in the prerequisite technique, the RC-IGBT 104 does not have a tungsten plug in the transistor region 104A and the diode region 104B, and further in the diode region 104B, the p + type anode layer 22, the interlayer insulating film 11, and the like. And does not have the barrier metal 12. In the transistor region 104A of the RC-IGBT 104, the surface electrode 304 is embedded in the contact hole 13 of the interlayer insulating film 11 instead of the tungsten plug 14. In the diode region 104B of the RC-IGBT 104, the p-type anode layer 21 and the surface electrode 304 are in direct contact with each other. Since the configuration of the RC-IGBT104 other than the above is the same as that of the RC-IGBT103, the description thereof will be omitted.

In the transistor region 104A of the RC-IGBT104, the MOS gate structure 33 is composed of an n-type drift layer 1, a p-type base layer 2, a p + type base layer 3, an n + type emitter layer 4, a gate insulating film 6, and a gate electrode 7. Will be done. Further, in the transistor region 104A of the RC-IGBT104, the n-type drift layer 1 and the p-type anode layer 21 form a diode structure 34 having a pn junction. In the present specification, the configuration including the MOS gate structure 33, the diode structure 34, the n-type buffer layer 9, the p-type collector layer 10, and the n + type cathode layer 23 is referred to as a semiconductor substrate 35. Further, the upper surface of the semiconductor substrate 35 on the paper surface of FIG. 4 is referred to as one main surface 35A, and the lower surface is referred to as the other main surface 35B.

That is, the RC-IGBT 104 has a MOS gate structure 33 on one main surface 35A side of the semiconductor substrate 35 in the transistor region 104A.

Further, the semiconductor substrate 35 includes a p-type collector layer 10 on the other main surface 35B side in the transistor region 104A, and the transistor region 104A constitutes an IGBT.

In the RC-IGBT104, a plurality of trenches 5 are formed in the depth direction (vertical direction in FIG. 4) from one main surface 35A of the semiconductor substrate 35. In FIG. 4, the trench 5 is provided in each of the transistor region 104A and the diode region 104B, but the trench 5 may not be formed in the diode region 104B. The depth direction of the trench 5 is not limited, but the trench 5 is arranged so that the depth direction is the same among the plurality of trenches 5. In the example of FIG. 4, the depth directions of all the trenches 5 are the same in the transistor region 104A and the diode region 104B.

In the transistor region 104A, an n-type carrier stored (CS) layer may be provided below the p-type base layer 2.

In the diode region 104B, a p-type anode layer 21 surrounded by a trench 5 is provided on one main surface 35A side of the semiconductor substrate 35. The impurity concentration of the p-type anode layer 21 is determined so that a desired forward voltage can be obtained.

FIG. 4 shows a case where the dummy gate electrode 26 in the diode region 104B is not covered with the interlayer insulating film 13, but it may be covered.

For the barrier metal 12, for example, titanium as a transition metal is used. The barrier metal 12 is silicated at the interface with the semiconductor substrate for the purpose of reducing the contact resistance with the n + type emitter layer 10. Barrier metals include titanium nitride, titanium carbide, or titanium silicide.

Aluminum alloys such as Al—Si, Al—Cu, and Al—Si—Cu are used for the first electrode 31. The content of components other than aluminum in the aluminum alloy is preferably 0.1% or more in order to suppress mutual diffusion into the silicon semiconductor substrate.

By embedding the first electrode 31 in the contact hole 13 of the interlayer insulating film 11 without using a plug contact, a good semiconductor device can be realized at low cost. The embedding property of the first electrode 31 in the contact hole 13 is affected by the thickness, shape, opening size, and the like of the interlayer insulating film 11. FIG. 5 is an enlarged view of the periphery of the contact hole 13 of the interlayer insulating film 11. As an example, the opening width 13a of the contact hole 13 on the lower surface of the interlayer insulating film 11 shown in FIG. 5 is 500 nm, the opening width 13b of the contact hole 13 on the upper surface of the interlayer insulating film 11 is 800 nm, and the thickness 11a of the interlayer insulating film 11 is 500 nm. In this case, there is no problem in the implantability of the first electrode 31 in the contact hole 13. The pitch width 5a, which is the distance between the two adjacent trenches 5, can be set in consideration of the dimensions of each part of the contact hole 13 described above. For example, if the dimensions of each part of the contact hole 13 are as described above, the pitch width 5a can be 2.4 μm.

No barrier metal is provided in the diode region 104B. Since the p-type anode layer 21 is not bonded to the barrier metal and is in direct contact with the first electrode 31, low contact resistance can be obtained. By using an aluminum alloy for the first electrode 31, it is possible to prevent mutual diffusion of the aluminum component and the silicon component between the first electrode 31 and the p-type anode layer 21. When the dummy gate electrode 26 in the diode region 104B is covered with the interlayer insulating film 11 like the gate electrode 7 in the transistor region 104A, the barrier metal 12 is formed on at least a part of the surface of the interlayer insulating film 11 covering the dummy gate electrode 26. It may be formed. This is because low contact resistance can be obtained as long as the barrier metal 12 is not bonded to the p-type anode layer 21.

The first electrode 31 is formed from the transistor region 104A to the diode region 104B. That is, on the upper surface of the RC-IGBT 104, both the transistor region 104A and the diode region 104B are shared by the first electrode 31. Therefore, in the assembly process of manufacturing a package using RC-IGBT104, it is not necessary to change the conditions such as wire bonding in the transistor region 104A and the diode region 104B.

<B-2. First manufacturing method>
Next, the first manufacturing method of RC-IGBT104 will be described. FIG. 6 is a flowchart showing a process from the formation of the surface element structure to the formation of the first electrode 31 in the first manufacturing method of RC-IGBT104. 7 to 12 are cross-sectional views showing a state in which RC-IGBT104 is being manufactured by the first manufacturing method.

First, the MOS gate structure 33 and the diode structure 34 are created (step S1). Specifically, in the transistor region 104A, the p-type base layer 2 is formed on the upper surface of the n-type drift layer 1, and the p + type base layer 3 and the n + type emitter layer 4 are selectively formed on the upper surface of the p-type base layer 2. To form. Next, when the n + type emitter layer 4 and the p-type base layer 2 are penetrated from the upper surface of the n + type emitter layer 4, a trench 5 is formed. Then, the gate insulating film 6 is formed on the inner wall of the trench 5, and the gate electrode 7 is further embedded in the trench 5. In the diode region 104B, the p-type anode layer 21 is formed on the upper surface of the n-type drift layer 1. Then, a trench 5 is formed from the upper surface of the p-type anode layer 21 to penetrate the p-type anode layer 21. Then, a gate insulating film 6 is formed on the inner wall of the trench 5, and a dummy gate electrode 26 is further embedded in the trench 5. This completes the structure shown in FIG. 7.

Next, the interlayer insulating film 11 is formed on the upper surfaces of the MOS gate structure 33 and the diode structure 34 (step S2). In this way, the structure shown in FIG. 8 is obtained.

Then, the resist mask 36 is formed on the interlayer insulating film 11 by photolithography. The resist mask 36 selectively has an opening on the interlayer insulating film 11 of the transistor region 104A. The resist mask 36 is used to form the contact hole 13 in the interlayer insulating film 11 of the transistor region 104A (step S3). For example, the contact hole 13 can be formed by reactive ion etching (RIE) using trifluoromethane (CHF ₃ ), tetrafluoromethane (CF ₄ ), or the like, or fluorine-based wet etching. In this way, the structure shown in FIG. 9 is obtained. After that, the resist mask 36 is removed.

Next, the barrier metal 12 is formed on the contact hole 13 and the interlayer insulating film 11 from the transistor region 104A to the diode region 104B (step S4). The barrier metal 12 is deposited by sputtering, and its main component is a transition metal such as titanium. The barrier metal 12 is silicidized at the contact interface by contacting with the silicon-based p + type base layer 3 or n + type emitter 4 exposed in the contact hole 13. Further, after sputtering, the surface of the barrier metal 12 is nitrided by heat treatment in a nitrogen atmosphere. In this way, the structure shown in FIG. 10 is obtained. That is, the barrier metal has a structure in which titanium silicide, titanium, and titanium nitride are laminated in this order.

Next, a resist mask 37 is formed in the transistor region 104A, and the barrier metal 12 and the interlayer insulating film 11 in the diode region 104B are removed by using the resist mask 37 (step S5). The barrier metal 12 and the interlayer insulating film 11 in the diode region 104B are removed by dry etching such as RIE using trifluoromethane or tetrafluoromethane. By removing the interlayer insulating film 11 and the barrier metal 12 on the diode structure 34 at once by dry etching, the process becomes a low cost process. In this way, the structure shown in FIG. 11 is obtained. After that, the resist mask 37 is removed.

Next, the first electrode 31 is formed by depositing an aluminum alloy by sputtering over the transistor region 104A and the diode region 104B (step S6). In the transistor region 104A, the first electrode 13 is formed by entering into the contact hole 13. In this way, the structure shown in FIG. 12 is obtained. After that, the structure on the lower surface side of the n-type drift layer 1, that is, the n-type buffer layer 9, the p-type collector layer 10, the n + -type cathode layer 23, and the second electrode 32 were formed, and the RC-IGBT104 shown in FIG. 4 was formed. Is completed.

<B-3. Effect>
The RC-IGBT 104 according to the first embodiment includes a semiconductor substrate 35 and a first electrode 31. The semiconductor substrate 35 has one main surface 35A and the other main surface 35B, a transistor region 104A constituting a transistor from one main surface 35A to the other main surface 35B, and one main surface 35A to the other main surface 35B. It includes a diode region 104B constituting a diode. The first electrode 31 extends over the transistor region 104A and the diode region 104B, and is formed on one main surface 35A of the semiconductor substrate 35. The semiconductor substrate 35 has a MOS gate structure 33 on one side of the main surface 35A in the transistor region 104A. The RC-IGBT 104 includes an interlayer insulating film 11 and a barrier metal 12. The interlayer insulating film 11 has a contact hole 13 that covers the gate electrode 7 of the MOS gate structure 33 and exposes the semiconductor layer of the MOS gate structure 33. The barrier metal 12 is formed inside the contact hole 13. The first electrode 31 enters the contact hole 13, contacts the semiconductor layer of the MOS gate structure 33 inside the contact hole 13 via the barrier metal 12, and directly contacts the semiconductor layer in the diode region 104B of the semiconductor substrate 35.

According to the above configuration, since the semiconductor layer of the MOS gate structure 33 is in contact with the barrier metal 12, the contact resistance is lower than in the case of direct contact with the first electrode 31. In addition, mutual diffusion between Al or the like, which is the metal material of the first electrode 31, and Si, which is the material of the semiconductor layer, can be suppressed. Further, since the p-type anode layer 21 which is the semiconductor layer of the diode region 104B is in direct contact with the first electrode 31, the contact resistance can be lowered without increasing the concentration of the p-type anode layer. Further, since the absence of the high-concentration p-type anode layer, it is not necessary to delay the carrier discharge at the time of off. Further, since the first electrode is shared by the transistor region 104A and the diode region 104B, the conditions such as wire bonding or solder wettability may be the same in the transistor region 104A and the diode region 104B in the assembly process using the RC-IGBT104. can. Further, by inserting the first electrode 31 into the contact hole 13 and contacting it with the semiconductor layer of the MOS gate structure 33, it is not necessary to use an expensive contact plug such as a tungsten plug, so that the manufacturing cost of RC-IGBT104 is reduced. be able to.

Further, the first manufacturing method of RC-IGBT104 is (a) a step of forming a MOS gate structure 33 and a diode structure 34 on one main surface 35A side of a semiconductor substrate 35, and (b) a step of forming a MOS gate structure 33 and a diode structure. A step of forming the interlayer insulating film 11 on the 34 and (c) a step of opening a contact hole 13 for exposing the semiconductor layer of the MOS gate structure 33 in the interlayer insulating film 11 on the MOS gate structure 33 (c). d) A step of forming the barrier metal 12 on the semiconductor layer and the interlayer insulating film 11 in the contact hole 13, and (e) a step of removing the interlayer insulating film 11 and the barrier metal 12 on the diode structure 34, (e). f) The step of forming the first electrode 31 in the contact hole 13 and on the diode structure 34 is provided. According to this manufacturing method, RC-IGBT104 can be manufactured without joining an unnecessary electrode layer to the p-type anode layer 21 even once.

<C. Embodiment 2>
<C-1. Second manufacturing method>
In the second embodiment, a second manufacturing method of RC-IGBT104 will be described. FIG. 13 is a flowchart showing a second manufacturing method of RC-IGBT104. As shown in FIG. 13, steps S1 to S4 and step S6 of the second manufacturing method are the same as those of the first manufacturing method shown in FIG. 6, and steps S5A and S5B are performed instead of step S5 of FIG. Only the points to be done are different. That is, the second manufacturing method is different from the first manufacturing method in that the barrier metal 12 is formed on the entire surfaces of the IGBT region 104A and the diode region 104B, and then the barrier metal 12 is removed from the diode region 104B.

Since steps S1 to S4 in FIG. 13 are the same as the first manufacturing method, the description thereof will be omitted. After step S4, a resist mask 37 is formed in the IGBT region 104A, and the barrier metal 12 and the interlayer insulating film 11 in the diode region 104B are removed by using the resist mask 37 (step S5A). In the first manufacturing method, the interlayer insulating film 11 in the diode region 104B was completely removed by dry etching such as RIE, but in the second manufacturing method, the interlayer insulating film 11 was removed so that the p-type anode layer 21 was not exposed. Leave only the film thickness of the part. In FIG. 14, the interlayer insulating film remaining in step S5A is shown as the interlayer insulating film 11A. Part of the interlayer insulating film 11 is removed by dry etching such as RIE using trifluoromethane or tetrafluoromethane. The thickness of the remaining interlayer insulating film 11A is not particularly limited.

Next, the resist mask 37 is removed to form a new resist mask 38. Like the resist mask 37, the resist mask 38 also has an opening in the diode region 104B, but as shown in FIG. 15, the opening is slightly smaller than the opening of the resist mask 37. That is, the resist mask 38 overlaps the end of the diode region 104B.

Next, the interlayer insulating film 11A is completely removed by wet etching using the resist mask 38 (step S5B). Here, for example, fluorine-based wet etching is used. When the interlayer insulating film 11A is removed to expose the p-type anode layer 21, damage to the p-type anode layer 21 can be suppressed by using wet etching instead of dry etching. In wet etching, the etching rate of the barrier metal 12 is high and the amount of side etching is large. However, as described above, since the resist mask 38 overlaps the end of the diode region 104B, the barrier metal 12 on the side of the IGBT region 104A is on the side. It is not removed by etching.

Next, the first electrode 31 is formed by depositing an aluminum alloy by sputtering over the IGBT region 104A and the diode region 104B (step S6). In this way, the structure shown in FIG. 16 is obtained. After that, the structure on the lower surface side of the n-type drift layer 1, that is, the n-type buffer layer 9, the p-type collector layer 10, the n + -type cathode layer 23, and the second electrode 32 were formed, and the RC-IGBT104 shown in FIG. 4 was formed. Is completed.

<C-2. Effect>
The second manufacturing method of RC-IGBT104 includes (a) a step of forming a MOS gate structure 33 and a diode structure 34 on one main surface 35A side of the semiconductor substrate 35, and (b) a step of forming a MOS gate structure 33 and a diode structure. A step of forming the interlayer insulating film 11 on the 34 and (c) a step of opening a contact hole 13 for exposing the semiconductor layer of the MOS gate structure 33 in the interlayer insulating film 11 on the MOS gate structure 33 (c). d) A step of forming the barrier metal 12 on the semiconductor layer and the interlayer insulating film 11 in the contact hole 13, and (e) a step of removing the interlayer insulating film 11 and the barrier metal 12 on the diode structure 34, (e). f) A step of forming the first electrode 31 on the diode structure 34 is provided, and the step (e) is a step (e1) of the barrier metal 12 on the diode structure 34 and a part of the interlayer insulating film 11. It includes a step of removing the film thickness by dry etching and a step of removing the interlayer insulating film 11 on the diode structure 34 remaining in the step (e2) step (e1) by wet etching. In this way, by using wet etching instead of dry etching for the etching process when the barrier metal 12 in the diode region 104B is removed to expose the p-type anode layer 21, damage to the p-type anode layer 21 due to etching is performed. Can be suppressed.

<D. Embodiment 3>
In this embodiment, the RC-IGBT104 described in the first and second embodiments is applied to a power conversion device. Although the present invention is not limited to a specific power conversion device, the case where the present invention is applied to a three-phase inverter will be described below as the third embodiment.

FIG. 17 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

The power conversion system shown in FIG. 17 includes a power supply 400, a power conversion device 500, and a load 600. The power supply 400 is a DC power supply, and supplies DC power to the power conversion device 500. The power supply 400 can be configured with various things, for example, it can be configured with a DC system, a solar cell, a storage battery, or it can be configured with a rectifier circuit or an AC / DC converter connected to an AC system. May be good. Further, the power supply 400 may be configured by a DC / DC converter that converts the DC power output from the DC system into a predetermined power.

The power conversion device 500 is a three-phase inverter connected between the power supply 400 and the load 600, converts the DC power supplied from the power supply 400 into AC power, and supplies AC power to the load 600. As shown in FIG. 17, the power conversion device 500 includes a main conversion circuit 501 that converts DC power into AC power and outputs it, and a drive circuit 502 that outputs a drive signal that drives each switching element of the main conversion circuit 501. A control circuit 503 that outputs a control signal for controlling the drive circuit 502 to the drive circuit 502 is provided.

The load 600 is a three-phase electric motor driven by AC power supplied from the power conversion device 500. The load 600 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 600 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railroad vehicle, an elevator, or an air conditioner.

Hereinafter, the details of the power conversion device 500 will be described. The main conversion circuit 501 includes a switching element and a freewheeling diode (not shown), and by switching the switching element, the DC power supplied from the power supply 400 is converted into AC power and supplied to the load 600. There are various specific circuit configurations of the main conversion circuit 501, but the main conversion circuit 501 according to the present embodiment is a two-level three-phase full bridge circuit, and has six switching elements and each switching element. It can consist of six anti-parallel freewheeling diodes. The RC-IGBT104 described in the first and second embodiments is applied to each switching element and each freewheeling diode of the main conversion circuit 501. The six switching elements are connected in series for each of the two switching elements to form an upper and lower arm, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. Then, the output terminals of each upper and lower arm, that is, the three output terminals of the main conversion circuit 501 are connected to the load 600.

The drive circuit 502 generates a drive signal for driving the switching element of the main conversion circuit 501 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 501. Specifically, according to the control signal from the control circuit 503 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) equal to or higher than the threshold voltage of the switching element, and when the switching element is kept off, the drive signal is a voltage equal to or lower than the threshold voltage of the switching element. It becomes a signal (off signal).

The control circuit 503 controls the switching element of the main conversion circuit 501 so that the desired power is supplied to the load 600. Specifically, the time (on time) for each switching element of the main conversion circuit 501 to be in the on state is calculated based on the power to be supplied to the load 600. For example, the main conversion circuit 501 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output. Then, a control command (control signal) is output to the drive circuit 502 so that an on signal is output to the switching element that should be turned on at each time point and an off signal is output to the switching element that should be turned off. The drive circuit 502 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power conversion device according to the present embodiment, the RC-IGBT104 described in the first and second embodiments is applied as the switching element of the main conversion circuit 501, so that good diode characteristics and low cost can be realized. ..

In the present embodiment, an example of applying the present invention to a two-level three-phase inverter has been described, but the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used, and when power is supplied to a single-phase load, the present invention is applied to a single-phase inverter. You may apply it. Further, when supplying electric power to a DC load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.

Further, the power conversion device to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor, and is, for example, a power source for a discharge processing machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system. It can be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

1 n-type drift layer, 2 p-type base layer, 5 trench, 6 gate insulating film, 7 gate electrode, 9 n type buffer layer, 10 p type collector layer, 11 interlayer insulating film, 12 barrier metal, 13 contact hole, 14 Tungsten plug, 15 emitter electrode, 16 collector electrode, 21 p-type anode layer, 24 anode electrode, 25 cathode electrode, 26 dummy gate electrode, 31 first electrode, 32 second electrode, 33 MOS gate structure, 34 diode structure, 35 semiconductor substrate, 104A transistor region, 104B diode region, 304 surface electrode, 400 power supply, 500 power conversion device, 501 main conversion circuit, 502 drive circuit, 503 control circuit, 600 load.

Claims (11)

A diode having one main surface and the other main surface, having a first conductive type drift layer between the one main surface and the other main surface, and forming a transistor from the one main surface to the other main surface. A semiconductor substrate having a region and a diode region constituting a diode from the one main surface to the other main surface.
A first electrode formed on the one main surface of the semiconductor substrate over the transistor region and the diode region.
It is a semiconductor device equipped with
The transistor region is
A second conductive type first base layer provided on the one main surface side of the semiconductor substrate, and
A first conductive type emitter layer provided on the one main surface side of the first base layer and having an upper surface constituting the one main surface.
A second base layer provided on the one main surface side of the first base layer, the upper surface constituting the one main surface, and a higher impurity concentration than the first base layer.
The diode region comprises a gate electrode provided via an insulating film inside a trench that penetrates the emitter layer and the first base layer from the upper surface of the emitter layer and reaches the drift layer.
A second conductive type anode layer provided on the one main surface side of the semiconductor substrate and having an upper surface constituting the one main surface in contact with the first electrode and separating the drift layer and the first electrode. Prepare,
The semiconductor device is
An interlayer insulating film having a contact hole that covers the gate electrode and exposes the upper surfaces of the second base layer and the emitter layer.
A barrier metal provided between the second base layer and the emitter layer and the first electrode in the contact hole and in contact with the upper surface of the second base layer and the emitter layer and the first electrode is provided. Prepare, prepare
Semiconductor device. The diode region is
A dummy gate electrode provided via an insulating film inside a trench that penetrates the anode layer from the upper surface of the anode layer and reaches the drift layer, and is in contact with the first electrode.
The semiconductor device according to claim 1. The first electrode contacts only the anode layer in the region of the one main surface of the semiconductor substrate in the diode region where the dummy gate electrode is not provided.
The semiconductor device according to claim 2. The barrier metal comprises titanium nitride, titanium carbide, or titanium silicide.
The semiconductor device according to any one of claims 1 to 3. The first electrode is an aluminum alloy.
The semiconductor device according to any one of claims 1 to 4. The barrier metal has silicide at the contact interface with the second base layer and the emitter layer.
The semiconductor device according to any one of claims 1 to 5. (A) The second conductive type first base layer and the first base layer on the one main surface side of the semiconductor substrate having the first conductive type drift layer between one main surface and the other main surface. On the other hand, a second conductive type second base having a higher impurity concentration than the first conductive type emitter layer provided on the main surface side and the first base layer provided on the one main surface side of the first base layer. A step of forming a MOS gate structure having a layer and a diode structure having a second conductive type anode layer separating the one main surface and the drift layer on the one main surface side of the semiconductor substrate.
(B) A step of forming an interlayer insulating film on the MOS gate structure and the diode structure,
(C) A step of opening a contact hole in the interlayer insulating film on the MOS gate structure to expose the upper surfaces of the emitter layer and the second base layer.
(D) A step of forming a barrier metal on the upper surface of the emitter layer and the second base layer in the contact hole, and the interlayer insulating film.
(E) A step of removing the interlayer insulating film and the barrier metal on the diode structure,
(F) A step of simultaneously forming a first electrode in contact with the barrier metal and the anode layer on the MOS gate structure and the diode structure.
Manufacturing method for semiconductor devices. The first electrode is in contact with the diode structure only by the anode layer.
The method for manufacturing a semiconductor device according to claim 7. The step (e) is a step of removing the interlayer insulating film and the barrier metal on the diode structure by dry etching.
The method for manufacturing a semiconductor device according to claim 7. The step (e) is
(E1) A step of removing the film thickness of the barrier metal and a part of the interlayer insulating film on the diode structure by dry etching.
(E2) The step of removing the interlayer insulating film on the diode structure remaining in the step (e1) by wet etching is provided.
The method for manufacturing a semiconductor device according to claim 7. A main conversion circuit having the semiconductor device according to any one of claims 1 to 5 and converting and outputting input power.
A drive circuit that outputs a drive signal for driving the semiconductor device to the semiconductor device,
A control circuit that outputs a control signal for controlling the drive circuit to the drive circuit is provided.
Power converter.

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