JP7067841B2 - Semiconductor device and voltage generation method - Google Patents

Description

The present invention relates to a semiconductor device and a voltage generation method, particularly a semiconductor device including a voltage generation circuit typified by a DCDC converter and the like, and a voltage generation method.

As a document relating to a conventional voltage generation circuit, for example, Patent Document 1 is known. FIG. 36 shows a block diagram of the voltage generation circuit disclosed in Patent Document 1. The voltage generation circuit disclosed in Patent Document 1 includes a charge pump circuit 2 that boosts the boosted voltage to a higher voltage than the power supply voltage, and an output voltage control circuit 3- that controls the boosted high voltage to a predetermined target voltage. A high voltage generating circuit comprising 1, 3-2, wherein the output voltage control circuit comprises at least two offset-free comparator circuits, or at least one offset-free comparator circuit and at least one differential amplifier, and is offset. The free comparator circuit is a coupling capacitor that inputs a voltage corresponding to a high voltage, a differential amplifier that compares the voltage from the coupling capacitor with a predetermined reference voltage, and outputs the comparison result voltage to the charge pump circuit. Each is connected to a differential amplifier and is equipped with a plurality of switches for canceling the offset of the differential amplifier.

That is, the voltage generation circuit according to Patent Document 1 is a circuit that generates a high voltage higher than the power supply voltage by the charge pump circuit 2 and regulates the generated voltage to a predetermined voltage value. The voltage generation circuit disclosed in Patent Document 1 generates an output voltage Vhv according to the ratio of R0 and R1. Further, the comparator circuits 3-1 and 3-2 that compare the voltage Vdiv obtained by dividing the output voltage Vhv with the reference voltage Vref are configured to automatically cancel the offset by using a switched capacitor.

Japanese Unexamined Patent Publication No. 2016-146725

However, the voltage generation circuit according to Patent Document 1 becomes inefficient when the output load is very small. This is because the current paths of resistors R1 and R0, the comparator circuit, and the current flowing through the clock generation circuit dominate. Further, the voltage generation circuit according to Patent Document 1 needs to supply a clock signal Pclk and a reference voltage Vref from the outside. Since Pclk is involved in the maximum output of the charge pump circuit, it is necessary to select an appropriate frequency according to the output load.
In addition, the reference voltage Vref needs to supply an accurate voltage in order to make the output voltage Vhv highly accurate. Further, considering the versatility of the voltage generation circuit, it is preferable that the reference voltage is variable.

That is, in the prior art such as the voltage generation circuit disclosed in Patent Document 1, the function of suppressing the on-resistance of the switch to a small value to perform high-efficiency step-up and step-down, process (manufacturing) variation, and temperature variation are suppressed. It has been required to have a function of generating a reference voltage, a function of controlling an operating frequency and an output voltage to an optimum value according to an output load, a function of trimming a reference voltage, and the like.

The present invention has been made to solve the above-mentioned problems, and to provide a semiconductor device having high efficiency in a wide load range and suppressing the influence of temperature fluctuation and manufacturing variation, and a voltage generation method. With the goal.

The semiconductor device according to the present invention has a voltage control oscillator that generates a clock signal whose frequency is controlled by an output control signal, and a power supply voltage that is synchronized with the clock signal based on a conversion control signal synchronized with the clock signal. A conversion voltage generation unit that generates the converted conversion voltage, an output voltage generation unit that controls the conversion voltage based on the output control signal and the charge / discharge control signal to generate an output voltage, and a reference control synchronized with the clock signal. A reference conversion voltage generator that synchronizes with the clock signal based on the signal and generates a reference conversion voltage obtained by converting the power supply voltage, and a reference that controls the reference conversion voltage based on the reference charge / discharge control signal to generate a reference voltage. It includes a voltage generation unit and a comparison unit that compares the output voltage and the reference voltage based on the clock signal and generates the output control signal.

The voltage generation method according to the present invention generates a clock signal whose frequency is controlled by an output control signal, synchronizes with the clock signal based on the conversion control signal synchronized with the clock signal, and converts the power supply voltage. , And a reference conversion voltage synchronized with the clock signal and converted with a power supply voltage based on the reference control signal synchronized with the clock signal, and the conversion voltage is controlled based on the output control signal and the charge / discharge control signal. In addition, the output voltage is generated so that the output impedance of the output voltage and the load impedance connected to the output terminal to which the output voltage is output are equal to each other, and the reference conversion voltage is based on the reference charge / discharge control signal. It controls to generate a reference voltage, compares the output voltage with the reference voltage based on the clock signal, and generates the output control signal.

INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a semiconductor device having high efficiency in a wide load range and suppressing the influence of temperature fluctuation and manufacturing variation, and a voltage generation method.

It is a block diagram which shows an example of the structure of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the VCO for UC of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows CP for UC of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the control part (Control Logic for UC) of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the Sub-UC of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the Sub-UC for REF of the semiconductor device which concerns on 1st Embodiment. In the semiconductor device according to the first embodiment, (a) is a time chart showing the operation waveform of Sub-UC, and (b) is a time chart showing the operation waveform of SUB-UC for REF. It is a circuit diagram which shows UC for REF of the semiconductor device which concerns on 1st Embodiment. It is a time chart which shows the operation waveform of UC for REF of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the UC of the semiconductor device which concerns on 1st Embodiment. It is a time chart which shows the operation waveform of UC of the semiconductor device which concerns on 1st Embodiment. It is a circuit diagram which shows the comparison part (Comparator for UC) of the semiconductor device which concerns on 1st Embodiment. It is a block diagram which shows an example of the structure of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the VCO for DC of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows CP for DC of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the control part (Control Logic for DC) of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the Sub-DC of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the Sub-DC for REF of the semiconductor device which concerns on 2nd Embodiment. It is a time chart which shows the operation waveform of the Sub-DC and SUB-DC for REF of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows DC for REF of the semiconductor device which concerns on 2nd Embodiment. It is a time chart which shows the operation waveform of DC for REF of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows DC of the semiconductor device which concerns on 2nd Embodiment. It is a time chart which shows the operation waveform of DC of the semiconductor device which concerns on 2nd Embodiment. It is a circuit diagram which shows the comparison part (Comparator for DC) of the semiconductor device which concerns on 2nd Embodiment. It is a block diagram which shows an example of the structure of the step-up type semiconductor device which concerns on 3rd Embodiment. It is a circuit diagram which shows the VCO for UC of the semiconductor device which concerns on 3rd Embodiment. It is a block diagram which shows an example of the structure of the step-down type semiconductor device which concerns on 3rd Embodiment. It is a circuit diagram which shows the VCO for DC of the semiconductor device which concerns on 3rd Embodiment. According to the fourth embodiment, (a) is a block diagram showing an example of the configuration of a step-up semiconductor device, and (b) is a block diagram showing an example of the configuration of a step-down semiconductor device. (A) is a circuit diagram of Sub-UC, and (b) is a circuit diagram of Sub-UC for REF according to a fourth embodiment. (A) is a circuit diagram of Sub-DC, and (b) is a circuit diagram of Sub-DC for REF according to a fourth embodiment. (A) is a circuit diagram of DC for REF, and (b) is a circuit diagram of UC for REF according to a fourth embodiment. (A) is a circuit diagram of DC, and (b) is a circuit diagram of UC according to a fourth embodiment. It is a circuit diagram of Comparator for DC which concerns on 4th Embodiment. It is a circuit diagram of Comparator for UC which concerns on 4th Embodiment. It is a block diagram which shows the structure of the semiconductor device which concerns on the prior art.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the following description, Out_COMP, Clk_VCO, VCO for UC (DC), Q_1 and Qb_1, Q_3 and Qb_3, Sub_UC (DC), Q_2 and Qb_2, Out_UC (DC), UC (DC), Q_1_REF and Qb_1_REF, Q_3_REF. And Qb_3_REF, Sub_UC (DC) for REF, Q_2_REF and Qb_2_REF, Out_REF, UC_for_REF, Comparator for UC (DC), Vias_CP, CP for UC, For Up (Down) Converter, Control_Logic_for UC (DC), Capacity C _REF , Capacity C Each of the _UCs is an "output control signal", a "clock signal", a "voltage control oscillation unit", a "conversion control signal", a "conversion voltage", a "conversion voltage generation unit", and a "charge / discharge control signal" according to the present invention. , "Output voltage", "Output voltage generator", "Reference control signal""Reference conversion voltage", "Reference conversion voltage generator", "Reference charge / discharge control signal", "Reference voltage", "Reference voltage generation" This is an example of "unit", "comparison unit", "frequency control signal", "voltage control oscillation control unit", "conversion signal generation unit", "generation control unit", "reference capacity", and "output capacity".

[First Embodiment]
A semiconductor device according to this embodiment and a voltage generation method will be described with reference to FIGS. 1 to 12. This embodiment is a mode in which the present invention is applied to a step-up DCDC converter (voltage generation circuit) that boosts a predetermined voltage to generate an output voltage. As shown in FIG. 1, the semiconductor device 10 according to the present embodiment includes a clock generation unit 11, a control unit 12, a booster unit 13, a reference voltage generation unit 14, and a comparison unit 15.

The booster 13 (denoted as "Step Up (Boost) Converter) in FIG. 1) is a switch using UC and UC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) that generate an output voltage Out_UC by boosting operation. It is equipped with a Sub-UC that generates a switch drive signal that controls (P-type MOS transistor p53 shown in FIG. 10). The reference voltage generator 14 (denoted as "Reference Voltage Generator" in FIG. 1) generates a reference voltage Out_REF by boosting operation, and a Sub-UC for generating a driving signal of a MOSFET switch of UC for REF. It has a REF. The comparison unit 15 (denoted as “Comparator for UC” in FIG. 1) compares the output voltage Out_UC with the reference (reference) voltage Out_REF. The control unit 12 (denoted as “Control Logic for UC” in FIG. 1) controls each unit of the semiconductor device 10. The clock generator 11 (denoted as "Clock Generator" in FIG. 1) controls the frequency of the VCO (Voltage Control Oscillator) for UC, which is a voltage control oscillator that generates a clock signal used in the semiconductor device 10, and the frequency of the VCO. It is equipped with a CP (Charge Pump) for UC that generates the voltage of.

FIG. 2 shows a circuit diagram of the VCO for UC. As shown in FIG. 2, VCO for UC includes a P-type MOS transistor pb01-pb07 whose frequency is controlled by Vbias_CP, a P-type MOS transistor p01-p07 and an N-type MOS transistor n01-n07, which are inverters constituting the ring oscillation unit. N-type MOS transistor n011-n014 and P-type MOS transistor p011-p014 that control the on / off of VCO for UC by En_VCO, output capacitance c01-c06, P-type MOS transistor p08-p010 and N-type MOS transistor n08 for dummy -n010, P-type MOS transistor p07 which is the final stage inverter and P-type MOS transistor p015 which improves the gain of N-type MOS transistor n07 are included.

The operation of VCO for UC is as follows. That is, when En_VCO rises from Low to High, the operation starts and Clk_VCO, which is a clock signal output, is output. The frequency of Clk_VCO is mainly determined by the potential of Vbias_CP and the capacitance value of capacitance c01-c06. The Clk VCO, which is a clock signal generated by the VCO for UC, is supplied to the control unit 12 and the comparison unit 15.

FIG. 3 shows a circuit diagram of CP for UC. As shown in FIG. 3, CP for UC includes P-type MOS transistors p13 and N-type MOS transistors n13, a capacitance c11, and P-type MOS transistors p11 and p12 and N in the current mirror unit that form a charge pump unit for current generation. Low level of Vbias_CP by type MOS transistors n11 and n12, capacitances c12 and c13 which are the stabilizing capacitances of the current mirror, P-type MOS transistors p14 and N-type MOS transistors n14, capacitance c14, and Rst_CP of the charge pump section which controls Vbias_CP. It is configured to include an N-type MOS transistor n15 that resets to.

The operation of CP for UC is as follows. That is, since the clock signal Clk_VCO is always input to the charge pump unit for current generation, a predetermined constant current is always flowing. Its current value depends on the frequency and capacitance c11 of the clock signal Clk_VCO. The current flowing through the charge pump section for current generation is supplied to the charge pump section that controls Vbias_CP through the current mirror. When the comparison unit output Out_COMP, which is the output of the comparison unit 15, is Low, the N-type MOS transistor n14 is turned on, and a sink current flows from the N-type MOS transistor n12. At this time, the output capacitance c14 is discharged, and the potential of Vbias_CP drops. On the other hand, when the comparison unit output Out_COMP is High, the P-type MOS transistor p14 is turned on and the source current flows from the P-type MOS transistor p12. At this time, the output capacity c14 is charged and Vbias_CP rises. By the above operation, CP for UC controls the oscillation frequency of VCO for UC based on the output Out COMP of the comparison unit 15.

FIG. 4 shows a circuit diagram of the control unit 12 (Control Logic for UC). As shown in FIG. 4, the control unit 12 (Control Logic for UC) includes a boost signal generation unit (denoted as “For UP Converter” in FIG. 4) 16 and a reference signal generation unit (“For Reference Voltage Generator” in FIG. 4). ”) 17 is included.

The boost signal generation unit 16 is a non-overlap signal generation unit 121 composed of a 1/2 divider 120, three inverters, two OR circuits, and two NOR circuits, and two D latches. It is configured to include the detained D latch portion 122 and the inverter portion 123 composed of two inverters. The boost signal generation unit 16 generates non-overlap signals Q_1, Qb_1, Q_2, and Qb_2 using a signal obtained by dividing the clock signal Clk_VCO from the VCO for UC by 1/2 with the 1/2 divider 120. Here, due to the operation of the D latch unit 122, Q_2 and Qb_2 are output only when the comparison unit output Out_COMP is Low.

The reference signal generation unit 17 includes a 1/4 divider 124, a non-overlap signal generation unit 125 composed of three inverters, two OR circuits, and two NOR circuits, an AND circuit, and a NAND circuit. It is configured to include a counter unit 126 configured to include one each, a D latch unit 127 composed of two D latches, and a trimming signal generation unit (denoted as "Trimming Logic" in FIG. 4) 128 and 129. ing. The reference signal generation unit 17 uses a signal obtained by dividing the clock signal Clk_VCO into 1/8 by the 1/2 divider 120 and the 1/4 divider 124, and is a non-overlapping signal Q_1_REF, Qb_1_REF, Q_2_REF. Generate [6: 0] and Qb_2_REF [6: 0]. For Q_2_REF [6: 0] and Qb_2_REF [6: 0], which signal is output is selected by the trimming signal Trim_REF [6: 0]. The selected signal is output only when the 3-bit counter unit 126 becomes “111”. The selected Q_2_REF [6: 0] and Qb_2_REF [6: 0] are used to select the trimming capacity of UC for REF (see FIG. 8).

FIG. 5 shows a circuit diagram of Sub-UC. As shown in FIG. 5, the Sub-UC is an N-type MOS transistor in the charge pump section that boosts the voltage from the power supply voltage VDD by VDD. It is configured to include transistors n21 and n22, and P-type MOS transistors p21 and p22. Sub-UC generates Q_3 and Qb_3 used in UC based on Q_1 and Qb-1 from the control unit 12.

FIG. 6 shows a circuit diagram of Sub-UC for REF. As shown in FIG. 6, the circuit configuration of Sub-UC for REF is the same as the circuit configuration of Sub-UC shown in FIG. Sub-UC for REF generates Q_3_REF and Qb_3_REF used in UC based on Q_1_REF and Qb-1_REF from the control unit 12.

FIG. 7 (a) shows a time chart of Sub-UC (see FIG. 5), and FIG. 7 (b) shows a time chart of SUB-UC for REF (see FIG. 6). As shown in FIG. 7A, the charge pump unit that boosts the voltage from VDD to 2 VDD receives Qb_1 and Q_1 signals in the capacitances c21 and c22, and Vb_1 and V_1 synchronize with Qb_1 and Q_1 to change from VDD to 2 VDD. Vibrate between. When Vb_1 is VDD and V_1 is 2 VDD, Qb_1 is Low (= VSS) and Q_1 is High (= VDD), so the P-type MOS transistor p21 is off, the N-type MOS transistor n21 is on, and the P-type MOS transistor p22. Is on and the N-type MOS transistor n22 is off, Qb_3 is VSS and Q_3 is 2 VDD. When Vb_1 is 2 VDD and V_1 is VDD, Qb_1 is High (= VDD) and Q_1 is Low (= VSS), so the P-type MOS transistor p21 is on, the N-type MOS transistor n21 is off, and the P-type MOS transistor. p22 is off and the N-type MOS transistor n22 is on, Qb_3 is 2 VDD and Q_3 is VSS. By the above operation, Q_3 and Qb_3 having an amplitude of 2 VDD are output from Sub-UC.

As shown in FIG. 7 (b), Sub-UC for REF performs the same operation as the above Sub-UC with the 1/8 divided signal of Clk_VCO. The reason why the 1/8 frequency division signal is used in Sub-UC for REF is to reduce power consumption.

FIG. 8 shows a circuit diagram of UC for REF. As shown in FIG. 8, UC for REF has a trimming capacitance ct (denoted as "Trimming Capacitor" in FIG. 8) of the reference charge pump section, P-type MOS transistors p41, p42, and N-type MOS transistors n41, n42. It is configured to include. UC for REF generates a reference voltage Out_REF to be output to the comparison unit 15 based on Q_3_REF and Qb3_REF.

ここで、N₀からN₆はTrim_REF[6:0]のトリミングコード値を表している。本実施の形態に係る半導体装置１０では、（式１）に即して参照電圧Out_REFはVDDから1.778×VDDまでトリミングで調整できる。その結果参照電圧Out_REFの電圧値はプロセス（製造）バラつき及び温度バラツキの影響を受けにくくなっている。 FIG. 9 shows a time chart of UC for REF. As shown in FIG. 9, UC for REF charges the reference voltage Out_REF via the capacitive C _REF for 14 out of 16 pulses and discharges Out_REF via the capacitive C _REF for 2 out of 16 pulses. do. That is, Out_REF oscillates periodically with the amplitude of Vripple around the Vref shown in FIG. Q_3_REF, Qb_3_REF and Q_2_REF [6: 0], Qb_2_REF [6: 0] are operating at the time of charging, and only Q_3_REF, Qb_3_REF is operating at the time of discharging. The charge amount for one pulse increases as the code value of the trimming signal Trim_REF [6: 0] increases, and the maximum is VDD × 127 × ct, and the discharge amount is always VDD × 127 × ct. Here, ct is a capacitance value of the trimming capacitance ct shown in FIG. From the above, Out_REF is expressed by (Equation 1) shown below.

Here, N ₀ to N ₆ represent the trimming code value of Trim_REF [6: 0]. In the semiconductor device 10 according to the present embodiment, the reference voltage Out_REF can be adjusted by trimming from VDD to 1.778 × VDD according to (Equation 1). As a result, the voltage value of the reference voltage Out_REF is less susceptible to process (manufacturing) variations and temperature variations.

FIG. 10 shows a circuit diagram of the UC. As shown in FIG. 10, the UC turns on / off the capacitance c51, the P-type MOS transistor p51, the N-type MOS transistor n51, the capacitance c52, the P-type MOS transistor p52, the N-type MOS transistor n52, and the charge pump of the charge pump section. It is configured to include a level shifter circuit (denoted as "Level Shifter" in FIG. 10) that generates a gate voltage of the P-type MOS transistor p53 and the P-type MOS transistor p53, which are switches to be switched.

FIG. 11 shows a time chart of UC. As shown in FIG. 11, when the output voltage Out_UC is lower than the reference voltage Out_REF (Vref), the comparison unit output Out_COMP becomes High and Out_UC is charged via the capacitance C _UC (see FIG. 1). When the output voltage Out_UC is higher than the reference voltage Out_REF, the comparison unit output Out_COMP becomes Low and the UC charging operation via the capacitance C _UC (see FIG. 1) is stopped. When charging, Q_3, Qb_3, Q_2, and Qb_2 are operating, and when stopped, Q_2, Qb_2, and the P-type MOS transistor p53, which is a switch, are off. The operating frequency, that is, the frequency of the clock signal Clk_VCO, gradually decreases as the output voltage Out_UC approaches the reference voltage Out_REF, and finally the output impedance of the charge pump of the UC (see FIG. 10) and the impedance of the output load connected to the Out_UC. Is automatically adjusted to the same operating frequency.
At this time, as shown in FIG. 11, the duty of the comparison unit output Out_COMP becomes about 50% and settles at the equilibrium point. As a result, according to the semiconductor device according to the present embodiment, a highly efficient voltage generation circuit can be obtained.

FIG. 12 shows a circuit diagram of the Comparator for UC. The comparison unit 15 is an inverter latch unit P-type MOS transistor p61, N-type MOS transistor n61, P-type MOS transistor p62, N-type MOS transistor n62, and P-type MOS transistor p63, N-type switch that controls operation and reset. It is composed of MOS transistors n63 and n64, capacitances c61 and c62 for stable operation, and NOR type RS-FF. In the circuit configuration of the comparison unit 15, the number of vertically stacked transistors is suppressed to three stages, which is suitable for low voltage operation.

Here, the comparison unit 15 according to the present embodiment has a configuration in which the back gate terminals of the P-type MOS transistors p61 and p62 are input terminals. Therefore, when the input potential becomes lower than VDD, it is assumed that the parasitic diode turns on and the forward current flows out. Therefore, it is necessary to set the input potential higher than VDD, but in this embodiment, only the potential higher than VDD is handled, so that it does not matter.

Next, the operation of the comparison unit 15 will be described. The comparison unit 15 determines the magnitude of the output voltage Out_UC and the reference voltage Out_REF at the rising timing of the clock signal Clk_VCO, and outputs High as the comparison unit output Out_COMP when the output voltage Out_UC exceeds the reference voltage Out_REF (= Vref). However, when it is lower than that, Low is output as the comparison section output Out_COMP. The time chart is as described in FIG.

Hereinafter, the overall operation of the semiconductor device 10 will be described. First, when the operation of the semiconductor device 10 starts, Rst_CP in CP for UC changes from High to Low, and En_VCO in VCO for UC changes from Low to High. At this time, the potential of the output Vbias_CP of CP for UC has dropped to the VSS level. Therefore, the clock signal Clk_VCO is a high frequency clock signal.

In FIG. 1, the main signals between the control unit 12, the booster unit 13, the reference voltage generation unit 14, and the comparison unit 15 referred to in the following description are occupied by numerical reference numerals. As shown in FIG. 1, the clock signal Clk_VCO is input to the control unit 12 (Control Logic for UC) and the comparison unit 15 (Comparator for UC). The control unit 12 (Control Logic for UC) outputs the signals Q_1, Qb_1, Q_2, Qb_2 and Q_1_REF, Qb_1_REF, Q_2_REF [6: 0], Qb_2_REF [6: 0] synchronized with the clock signal Clk_VCO. Q_1, Qb_1 and Q_1_REF, Qb_1_REF are input to Sub-UC and Sub-UC for REF, respectively, and Q_3, Qb_3 and Q_3_REF, Qb_3_REF are generated. Q_2_REF [6: 0], Qb_2_REF [6: 0], Q_3_REF, and Qb_3_REF are input to UC_for_REF, and the reference voltage Out_REF converges to the value set by the trimming signal Trim_REF [6: 0]. Q_2, Qb_2, Q_3, and Qb_3 are input to the UC and gradually approach the value of the reference voltage Out_REF. Normally, the capacity value of C _UC is set larger than the capacity value of C _REF . As a result, the reference voltage Out_REF converges first, and the output voltage Out_UC follows it.

When the output voltage Out_UC exceeds the reference voltage Out_REF, the comparison unit output Out_Comp rises from Low to High at the rising timing of the clock signal Clk_VCO. At this time, the capacity C14 in CP for UC becomes charged and Vbias_CP gradually increases. Therefore, the frequency of Clk_VCO also decreases. On the other hand, in UC, Q_2, Qb_2 and the P-type MOS transistor p53, which is a switch, are turned off, so that charging to the capacitance C _UC is stopped. If a load is connected to Out_UC in this state, Out_UC will gradually decrease and fall below Out_REF after a certain period of time.

When the output voltage Out_UC falls below the reference voltage Out_REF, the comparison unit output Out_Comp drops from High to Low at the rising timing of the clock signal Clk_VCO. At this time, C14 in CP for UC is in a discharged state, and Vbias_CP gradually decreases. Therefore, the frequency of Clk_VCO also goes up.

When the above operation is repeated, the output voltage Out_UC finally converges to the average value of the reference voltage Out_REF, and the Low and High duties of the comparison unit output Out_Comp become equal. This condition occurs when the amount of charge to C _UC and the amount of discharge from the load connected to Out_UC are equal. That is, the frequency of the clock signal Clk_VCO is automatically adjusted to the optimum value that maximizes the efficiency of the circuit. Even if the impedance of the load connected to Out_UC changes, the frequency of the clock signal Clk_VCO is adjusted to follow the impedance of the load and converges to the optimum value.

As described above, according to the present embodiment, UC for REF can generate a high voltage higher than the power supply voltage, and further, as shown in (Equation 1), the reference voltage Out_REF. Can be adjusted by trimming. Therefore, the reference voltage Out_REF is robust against process fluctuations and temperature fluctuations.

In addition, the UC outputs a voltage equal to the mean of the reference voltage Out_REF as the output voltage Out_UC via an output impedance equal to the output load. The output impedance is automatically adjusted by changing the frequency of the clock signal Clk_VCO, which is the output of the VCO for UC mounted inside the semiconductor device 10. The frequency of the clock signal Clk_VCO is low when the output is low and high when the output is high. Since each circuit block included in the semiconductor device 10 operates in synchronization with the clock signal Clk_VCO, highly efficient operation can be expected in a wide load region.

As described in detail above, according to the semiconductor device and the voltage generation method according to the present embodiment, a step-up DCDC converter (voltage generation circuit) that is highly efficient and robust against temperature variation and process variation over a wide range of load current can be used. It can be realized.

[Second Embodiment]
A semiconductor device according to this embodiment and a voltage generation method will be described with reference to FIGS. 13 to 24. This embodiment is an embodiment in which the present invention is applied to a step-down DCDC converter (voltage generation circuit) that lowers a predetermined voltage to generate an output voltage. As shown in FIG. 13, the semiconductor device 20 according to the present embodiment includes a clock generation unit 21, a control unit 22, a step-down unit 23, a reference voltage generation unit 24, and a comparison unit 25.

The step-down section (denoted as “Step Down (Back) Converter” in FIG. 13) 23 includes a DC that generates an output voltage Out_DC by a step-down operation and a Sub-DC that generates a drive signal for a DC MOSFET switch. Has been done. The reference voltage generator (denoted as "Reference Voltage Generator" in FIG. 13) 24 generates a DC for REF that generates a reference voltage Out_REF by step-down operation, and a Sub-DC that generates a drive signal for a DC for REF MOSFET switch. It is configured to include for REF. The comparison unit (denoted as “Comparator for DC” in FIG. 13) 25 compares the output voltage Out_DC with the reference voltage Out_REF. The control unit (denoted as “Control Logic for DC” in FIG. 13) 22 controls each circuit block of the semiconductor device 20. The clock generation unit 21 includes a VCO for DC that generates a clock signal and a CP for DC that generates a voltage for controlling the frequency of the VCO.

FIG. 14 shows a circuit diagram of the VCO for DC. The circuit configuration of the VCO for DC shown in FIG. 14 is basically the same as the circuit configuration of the VCO for UC shown in FIG. That is, the N-type MOS transistor nb01-nb07 whose frequency is controlled by Vbias_CP, the P-type MOS transistor p01-p07 and N-type MOS transistor n01-n07 which constitute the inverter of the ring oscillation section, and the N-type which controls the on / off of VCO by En_VCO. The MOS transistor n011-n014 and P-type MOS transistor p011-p014, the output capacitance c01-c06, the dummy transistor P-type MOS transistor p08-p010 and N-type MOS transistor n08-n010, and the final stage inverter are configured. It is composed of a P-type MOS transistor p07 and an N-type MOS transistor n015 that improves the gain of the N-type MOS transistor n07.

The operation of VCO for DC is as follows. That is, when the Enb_VCO falls from High to Low, the VCO for DC starts operating and outputs the clock signal Clk_VCO. The frequency of the clock signal Clk_VCO is mainly determined by the potential of Vbias_CP and the capacitance value of the capacitance c01-c06. As shown in FIG. 13, the clock signal Clk_VCO generated by the VCO for DC is supplied to the control unit 22.

FIG. 15 shows a circuit diagram of CP for DC. As shown in FIG. 15, CP for DC consists of P-type MOS transistors p13 and N-type MOS transistors n13, which form a current generation charge pump section, a capacitance c11, and P-type MOS transistors p11 and p12 and N which form a current mirror section. Type MOS transistors n11 and n12, capacitances c12 and c13 for stabilization that make up the current mirror section, P-type MOS transistors p14 and N-type MOS transistors n14 that make up the charge pump section that controls Vbias_CP, capacitance c14, and Rstb_CP It is configured to include a P-type MOS transistor p15 that resets Vbias_CP to the High level.

Next, the operation of CP for DC will be described. Since the clock signal Clk_VCO is always input to the charge pump unit for current generation, a predetermined constant current is constantly flowing. Its current value depends on the frequency and capacitance c11 of the clock signal Clk_VCO. The current is supplied to the charge pump unit that controls Vbias_CP through the current mirror. When the comparison unit output Out_COMP is Low, the N-type MOS transistor n14 is turned on, and a sink current flows from the N-type MOS transistor n12. Therefore, the output capacity c14 is discharged and Vbias_CP drops. On the other hand, when the comparison unit output Out_COMP is High, the P-type MOS transistor p14 is turned on and the source current flows from the P-type MOS transistor p12. Therefore, the output capacity c14 is charged and Vbias_CP rises. The frequency of VCO for DC is controlled by the above operation.

FIG. 16 shows a circuit diagram of the control unit 22 (Control Logic for DC). As shown in FIG. 16, the control unit 22 (Control Logic for DC) includes a boosting signal generation unit 26 and a reference signal generation unit 27.

The boost signal generation unit 26 is composed of an overlap signal generation unit 221, which is composed of a 1/2 frequency divider 220, three inverters, two AND circuits, and a NAND circuit, and two D latch circuits. The D latch unit 222 is provided with an inverter unit 223 composed of two inverters.

The boost signal generation unit 26 uses a signal obtained by dividing the clock signal Clk_VCO by 1/2 by the 1/2 divider 220, and the overlap signal generation unit 221 generates overlap signals Q_1, Qb_1, Q_2, and Qb_2. .. Q_2 and Qb_2 are output only when the comparison unit output Out_COMP is High due to the operation of the D latch unit 222. The inverter unit 223 converts the logic of Q_2 and Qb_2.

The reference signal generation unit 27 is a 1/4 divider 224, 3 inverters, an overlap signal generation unit 225 including two AND circuits and a NAND circuit, and one AND circuit and NAND. It includes a counter unit 226 including a circuit, a D latch unit 227 composed of two D latch circuits, and a trimming signal generation unit 228 and 229.

In the reference signal generation unit 27, the clock signal Clk_VCO is divided into 1/8 by the 1/2 divider 220 and the 1/4 divider 224, and the overlap signals Q_1_REF, Qb_1_REF, and Q_2_REF [6: 0] ] And Qb_2_REF [6: 0] are generated. For Q_2_REF [6: 0] and Qb_2_REF [6: 0], which signal is output is selected by the trimming signal Trim_REF [6: 0]. The selected signal is output only when the 3-bit counter unit 226 becomes “111”.

FIG. 17 shows a circuit diagram of Sub-DC. As shown in FIG. 17, the Sub-DC is an N-type MOS transistor p21, p22, capacitance c21, c22, and an N-type that generates a signal having an amplitude from-VDD to VDD, which constitutes a charge pump unit that steps down by VDD from VSS. It is configured to include MOS transistors n21 and n22, and P-type MOS transistors p23 and p24. Sub-DC generates Q_3 and Qb_3 based on the input Q_1 and Qb_1 and supplies them to UC (see FIG. 13).

FIG. 18 shows a circuit diagram of Sub-DC for REF. As shown in FIG. 18, the circuit configuration of Sub-DC for REF is the same as the circuit configuration of Sub_DC shown in FIG. Sub-DC for REF generates Q_3_REF and Qb_3_REF based on the input Q__1_REF and Qb_1_REF and supplies them to UC (see FIG. 13).

FIG. 19A shows a Sub-DC time chart, and FIG. 19B shows a Sub-DC for REF time chart.

As shown in FIG. 19A, the charge pump unit (see FIG. 17) that steps down by VDD from VSS synchronizes Vb_1 and V_1 with Qb_1 and Q_1 when the signals of Qb_1 and Q_1 are input to the capacities c21 and c22. Then it swings between-VDD and VSS. When Vb_1 is-VDD and V_1 is VSS, Qb_1 is Low (= VSS) and Q_1 is High (= VDD), so the P-type MOS transistor p23 is off and the N-type MOS transistor n21 is on, and P-type. The MOS transistor p24 is turned on and the N-type MOS transistor n22 is turned off, and Qb_3 is-VDD and Q_3 is VDD. On the other hand, when Vb_1 is VSS and V_1 is-VDD, Qb_1 is High (= VDD) and Q_1 is Low (= VSS), so the P-type MOS transistor p23 is turned on and the N-type MOS transistor n21 is turned off. The type MOS transistor p24 is turned off and the N type MOS transistor n22 is turned on, and Qb_3 is VDD and Q_3 is-VDD. As shown in FIG. 19B, Sub-DC for REF performs the same operation with the 1/8 divided signal of the clock signal Clk_VCO.

FIG. 20 shows a circuit diagram of DC for REF. As shown in FIG. 20, the DC for REF includes a trimming capacitance ct of the reference charge pump unit and P-type MOS transistors p41 and p42, and N-type MOS transistors n41 and n42. DC for REF generates a reference voltage Out_REF based on Q_2_REF [6: 0] and Qb_2_REF [6: 0] (see also FIG. 13).

ただしN₀からN₆はトリミング信号Trim_REF[6:0]のトリミングコード値を表している。（式２）から、Out_REFは-0.778×VDDからVSSまでトリミングで調整が可能である。その結果参照電圧Out REFの電圧値はプロセス（製造）バラつき及び温度バラツキの影響が抑制されている。 FIG. 21 shows a DC for REF time chart. DC for REF discharges Out_REF only 14 out of 16 pulses and charges Out_REF only 2 out of 16 pulses. Q_3_REF, Qb_3_REF and Q_2_REF [6: 0], Qb_2_REF [6: 0] are operating at the time of discharge, and only Q_3_REF, Qb_3_REF is operating at the time of charging. The discharge amount at one pulse increases as the code value of the trimming signal Trim_REF [6: 0] increases, and the maximum is VDD × 127 ct, and the charge amount is always VDD × 127 ct. However, ct is a capacity value of the capacity ct shown in FIG. From the above, the reference voltage Out_REF is expressed by (Equation 2) shown below.

However, N ₀ to N ₆ represent the trimming code value of the trimming signal Trim_REF [6: 0]. From (Equation 2), Out_REF can be adjusted by trimming from -0.778 × VDD to VSS. As a result, the voltage value of the reference voltage Out REF is suppressed from the influence of process (manufacturing) variation and temperature variation.

FIG. 22 shows a circuit diagram of DC. As shown in FIG. 22, DC turns on and off the charge pump capacity c51, P-type MOS transistor p51, N-type MOS transistor n51, and capacity c52, P-type MOS transistor p52, N-type MOS transistor n52, and charge pump. It is configured to include an N-type MOS transistor n53, which is a switch, and a level shifter circuit (denoted as “Level Shifter” in FIG. 22) that generates a gate signal of the switch.

FIG. 23 shows a DC time chart. The operation of the DC will be described with reference to FIG. 23. For DC, when the output voltage Out_DC is higher than the reference voltage Out_REF (denoted as “Vref” in FIG. 23), the comparison unit output Out_COMP becomes High and Out_DC is discharged via the capacitance C _DC . If the output voltage Out_DC is lower than the reference voltage Out_REF, the comparison unit output Out_COMP becomes Low, and the DC stops the discharge operation. At the time of discharge, Q_3, Qb_3 and Q_2, Qb_2 are operating, and at the time of stop, Q_2, Qb_2 and the N-type MOS transistor n53, which is a switch, are turned off. The operating frequency, that is, the frequency of the clock signal Clk_VCO, gradually decreases as the output voltage Out_DC approaches the reference voltage Out_REF, and is finally adjusted to the equilibrium point where the output impedance of the charge pump section and the impedance of the output load become equal. To.

FIG. 24 shows a circuit diagram of the Comparator for DC. As shown in FIG. 24, the comparison unit 25 (Comparator for DC) controls the operation and reset of the P-type MOS transistor p61, N-type MOS transistor n61, P-type MOS transistor p62, and N-type MOS transistor n62 of the inverter latch unit. It is configured to include N-type MOS transistors n63, P-type MOS transistors p63, p64, which are switches, capacitances c61 and c62 for stable operation, and NAND type RS-FF. Since the circuit of the comparator 25 (Comparator for DC) suppresses the number of vertically stacked transistors to three stages, it is suitable for low voltage operation. Here, since the comparison unit 25 (Comparator for DC) has a configuration in which the back gate terminals of the N-type MOS transistors n61 and n62 are used as input terminals, when the input potential becomes higher than VSS, the parasitic diode is turned on and the forward current is increased. It is also expected to flow out. Therefore, it is necessary to set the input potential lower than VSS, but in this embodiment, since only the potential lower than VSS is handled, the above phenomenon does not become a problem.

The operation of the comparison unit 25 (Comparator for DC) is as follows. That is, the comparison unit 25 determines the magnitude at the rising timing of the clock signal Clk_VCO, and when the output voltage Out_DC exceeds the reference voltage Out_REF (= Vref), the comparison unit output Out_COMP outputs High, and when the output voltage Out_DC is below the reference voltage Out_REF (= Vref), the comparison unit output Out_COMP outputs High. Output Low. The comparison unit 25 generates the comparison unit output Out_COMP, which is the comparison result, by the above operation, and outputs it to the DC, CP for DC, and the control unit 22 as shown in FIG. The time chart is as described in FIG.

Next, the overall operation of the semiconductor device 20 will be described. First, when the semiconductor device 20 starts operation, Rstb_CP in the CP for DC changes from Low to High, and Enb_VCO in the VCO for DC changes from High to Low. At this time, the potential of the output Vbias_CP of CP for DC has risen to the VDD level. Therefore, the clock signal Clk_VCO is a high frequency clock signal. The clock signal Clk_VCO is input to the control unit 22 (Control Logic for DC) and the comparison unit 25 (Comparator for DC).

The control unit 22 (Control Logic for DC) outputs signals Q_1, Qb_1, Q_2, Qb_2 and Q_1_REF, Qb_1_REF, Q_2_REF [6: 0], Qb_2_REF [6: 0] synchronized with the clock signal Clk_VCO. Q_1, Qb_1 and Q_1_REF, Qb_1_REF are input to Sub-DC and Sub-DC for REF to generate Q_3, Qb_3 and Q_3_REF, Qb_3_REF. Q_2_REF [6: 0], Qb_2_REF [6: 0], Q_3_REF, and Qb_3_REF are input to DC_for_REF, and the reference voltage Out_REF converges to the value set by the trimming signal Trim_REF [6: 0]. Q_2, Qb_2, Q_3, and Qb_3 are input to DC and gradually approach the value of the reference voltage Out_REF. Normally, the capacitance value of the capacitance C _UC is set larger than the capacitance value of the capacitance C _REF , so that the reference voltage Out_REF converges first, and the output voltage Out_DC follows it.

When the output voltage Out_DC falls below the reference voltage Out_REF, the comparison unit output Out_COMP from the comparator 25 (Comparator for DC) drops from High to Low at the rising timing of the clock signal Clk_VCO. At this time, the capacity C14 (see FIG. 15) in the CP for DC is in a discharged state, and Vbias_CP gradually decreases. Therefore, the frequency of the clock signal Clk_VCO also decreases. Further, since the Q_2, Qb_2 and the N-type MOS transistor n53, which is a switch, are turned off in the DC, the discharge to the capacitance C _DC is stopped. If a load is connected to Out_DC in this state, Out_DC gradually rises and exceeds the reference voltage Out_REF after a certain period of time. When the output voltage Out_DC exceeds the reference voltage Out_REF, the comparison unit output Out_COMP from the comparison unit 25 (Comparator for DC) rises from Low to High at the rising timing of the clock signal Clk_VCO. At this time, the capacity C14 in CP for DC becomes charged and Vbias_CP gradually increases. Therefore, the frequency of the clock signal Clk_VCO also rises.

By repeating the above operation, the output voltage Out_DC finally converges to the average value of the reference voltage Out_REF, and the Low and High duties of the comparison unit output Out_COMP become equal. In this state, the amount of discharge to the capacitance C _DC and the amount of charge from the load connected to Out_DC are equal. That is, the frequency of the clock signal Clk_VCO is automatically adjusted to the optimum value that maximizes the efficiency of the circuit. Even if the load connected to Out_DC changes, the frequency of the clock signal Clk_VCO follows the load fluctuation, and as a result, the efficiency of the circuit is adjusted to the optimum value.

As described in detail above, according to the semiconductor device and the voltage generation method according to the present embodiment, DC for REF can generate a lower voltage than VSS, and further refer to (reference) based on (Equation 2). The voltage Out_REF can be adjusted by trimming. As a result, the reference voltage Out ref is robust against process (manufacturing) and temperature fluctuations. In addition, DC outputs the output voltage Out_DC at a voltage equal to the mean of the reference voltage Out_REF and through an output impedance equal to the output load. The output impedance is adjusted by automatically changing the frequency of the clock signal Clk_VCO, which is the output of the VCO for DC mounted inside. That is, the frequency of the clock signal Clk_VCO is low when the output is low and high when the output is high. As described above, since all the circuit blocks mounted on the semiconductor device according to the present embodiment operate in synchronization with the clock signal Clk_VCO, highly efficient operation is achieved in a wide load region.

Based on the above, by adopting the semiconductor device and the voltage generation method according to the present embodiment, a step-down DCDC converter that is highly efficient in a wide load current range and robust against process (manufacturing) variations and temperature variations can be obtained. It can be realized.

[Third Embodiment]
The semiconductor device and the voltage generation method according to the present embodiment will be described with reference to FIGS. 25 to 28. 25 and 26 are embodiments in which the present invention is applied to a step-up DCDC converter (voltage generation circuit) that boosts a predetermined voltage to generate an output voltage. On the other hand, FIGS. 27 and 28 show a form in which the present invention is applied to a step-down DCDC converter (voltage generation circuit) that lowers a predetermined voltage to generate an output voltage.

A step-up DCDC converter (voltage generation circuit) according to the present embodiment will be described with reference to FIGS. 25 and 26. FIG. 25 shows the semiconductor device 30 according to the present embodiment, and FIG. 26 shows a circuit diagram of the VCO for UC among the circuit blocks constituting the semiconductor device 30. As shown in FIG. 25, the semiconductor device 30 according to the present embodiment includes a clock generation unit 31, a control unit 32, a booster unit 33, a reference voltage generation unit 34, and a comparison unit 35. The basic configuration of each of the clock generation unit 31, the control unit 32, the booster unit 33, the reference voltage generation unit 34, and the comparison unit 35 is the clock generation unit 11, the control unit 12, and the booster unit 13 of the semiconductor device 10 shown in FIG. Since it is the same as the reference voltage generation unit 14 and the comparison unit 15, the differences from the semiconductor device 10 will be mainly described below.

As shown in FIG. 25, the semiconductor device 30 is significantly different from the semiconductor device 10 in that the output voltage Out_UC is fed back to the VCO for UC. Then, as shown in FIG. 26, the output voltage Out_UC is input to the back gate terminals of the P-type MOS transistors pb01 to pb07 of the VCO for UC.

In the semiconductor device 10, the speed of the comparator 15 (Comparator for UC) depends on the voltage value of the output voltage Out_UC. For example, when the potential of Out_UC becomes higher, the speed of the comparison unit 15 (Comparator for UC) becomes slower. When the speed of the Comparator 15 (Comparator for UC) becomes slow in this way, it is assumed that the frequency of the VCO for UC cannot be caught up and the state becomes unstable.

Therefore, in this embodiment, the output voltage Out_UC is fed back to the back gate terminals of the P-type MOS transistors pb01 to pb07 of the VCO for UC. Further, the output voltage Out_UC is input to the back gate terminals of the P-type MOS transistors p61 and p62 of the Comparator for UC (see FIG. 12). Here, the characteristics of the back gates of the P-type MOS transistors pb01 to pb07 and p61 and p62 are set to be the same. In this case, as the output voltage Out_UC increases, the speed of the Comparator for UC decreases, but the frequency of the VCO for UC also decreases. That is, the frequency of the VCO for UC decreases in proportion to the decrease in the speed of the comparison unit 35 (Comparator for UC). As a result, the comparison unit 35 (Comparator for UC) cannot follow the frequency of the VCO for UC, and it is suppressed from falling into an unstable state.

As described above, according to the present embodiment, by changing the frequency of the VCO for UC in proportion to the speed of the comparison unit 35 (Comparator for UC), a stable circuit can be provided even at a point where the boost level is higher. It is possible to operate it.

The semiconductor device 40 shown in FIGS. 27 and 28 adopts the above technical concept in the step-down DCDC converter. FIG. 27 shows the semiconductor device 40 according to the present embodiment, and FIG. 28 shows a circuit diagram of the VCO for DC among the circuit blocks constituting the semiconductor device 40. As shown in FIG. 27, the semiconductor device 40 according to the present embodiment includes a clock generation unit 41, a control unit 42, a step-down unit 43, a reference voltage generation unit 44, and a comparison unit 45. The basic configuration of each of the clock generation unit 41, the control unit 42, the step-down unit 43, the reference voltage generation unit 44, and the comparison unit 45 is the clock generation unit 21, the control unit 22, and the step-down unit 23 of the semiconductor device 20 shown in FIG. Since it is the same as the reference voltage generation unit 24 and the comparison unit 25, the differences from the semiconductor device 20 will be mainly described below.

As shown in FIG. 27, the semiconductor device 40 is different from the semiconductor device 20 in that the output voltage Out_DC is fed back to the VCO for DC. As shown in FIG. 28, in the VCO for DC of the semiconductor device 40, the output voltage Out_DC is input to the back gate terminals of the N-type MOS transistors nb01 to nb07.

In the semiconductor device 20, the speed of the comparator for DC depends on the voltage value of the output voltage Out_DC. For example, when the output voltage Out_DC becomes lower, the speed of the Comparator for DC becomes slower. When the speed of the Comparator for DC becomes slow in this way, it cannot keep up with the frequency of the VCO for DC, and it is assumed that an unstable state may occur.

Therefore, in the present embodiment, as shown in FIG. 28, the output voltage Out_DC is fed back to the back gate terminals of the N-type MOS transistors nb01 to nb07 of the VCO for DC. Further, the output voltage Out_DC is input to the back gate terminals of the N-type MOS transistors n61 and n62 of the Comparator for DC (see FIG. 24). Here, the characteristics of the back gates of the N-type MOS transistors nb01 to nb07 and n61 and n62 are set to be the same. In this case, the speed of the comparison unit 45 (Comparator for DC) decreases as the output voltage Out_DC decreases, but the frequency of the VCO for DC also decreases. As a result, the frequency of the VCO for DC also decreases in proportion to the decrease in the speed of the comparison unit 45 (Comparator for DC), so that the comparison unit 45 (Comparator for DC) cannot follow the frequency of the VCO for DC and is unstable. Falling into a state is suppressed.

As described above, according to the present embodiment, the frequency of the VCO for DC is changed in proportion to the speed of the comparison unit 45 (Comparator for DC). As a result, it is possible to operate the circuit stably even when the step-down level is higher.

[Fourth Embodiment]
A semiconductor device and a voltage generation method will be described with reference to FIGS. 29 to 35. This embodiment is a mode in which the semiconductor devices according to the above embodiment are connected in series so that a higher (lower) output voltage can be obtained. That is, the semiconductor device 50 shown in FIG. 29A is a form in which the semiconductor devices 10 according to the above embodiment are connected in series. On the other hand, the semiconductor device 60 shown in FIG. 29B is a form in which the semiconductor devices 20 according to the above embodiment are connected in series.
In the semiconductor device 50 or 60, the number of connections of the semiconductor device 10 or 20 is not particularly limited. Further, in the semiconductor device 50 or 60, the individual semiconductor devices 10 or 20 may be arranged, or the semiconductor devices 10 or 20 may be integrated into one semiconductor device.

FIG. 29 (a) exemplifies a form in which the semiconductor devices 10 are connected in series in M (M is an integer) stage. In FIG. 29 (a), the output voltages Out_UC_1, Out_UC_2, ... Out_UC_M are semiconductor devices 10_1, respectively. , The output of the semiconductor device 10_2, ..., The output of the semiconductor device 10_M is shown. Hereinafter, the output of the semiconductor device 10_X is referred to as Out_UC_x. On the other hand, FIG. 29 (b) illustrates a form in which the semiconductor devices 20 are connected in series in M stages, and in FIG. 29 (b), the output voltages Out_DC_1, Out_DC_2, ... Out_DC_M are the outputs of the semiconductor devices 20_1, respectively. The output of the semiconductor device 20_2, ..., The output of the semiconductor device 20_M is shown. Hereinafter, the output of the semiconductor device 20_X is referred to as Out_DC_x.

Here, the semiconductor device 10 corresponds to the step-up from VDD, and the semiconductor device 20 corresponds to the step-down from VSS. Therefore, the configurations of the booster unit 13 (Step Up Convertor), the reference voltage generator unit 14 (Reference Voltage Generator), and the comparison unit 15 (Comparator for UC) of the semiconductor device 10 shown in FIG. 1 are partially changed. Further, the configurations of the step-down unit 23 (Step Down Convertor), the reference voltage generator unit 24 (Reference Voltage Generator), and the comparison unit 25 (Comparator for DC) of the semiconductor device 20 shown in FIG. 13 are partially changed.

FIG. 30A shows a circuit diagram of Sub-UC, and FIG. 30B shows a circuit diagram of Sub-UC for REF. FIG. 31 (a) shows a circuit diagram of Sub-DC, and FIG. 31 (b) shows a circuit diagram of Sub-DC for REF. FIG. 32 (a) shows a circuit diagram of DC for REF, and FIG. 32 (b) shows a circuit diagram of UC for REF. FIG. 33 (a) shows a circuit diagram of DC, and FIG. 33 (b) shows a circuit diagram of UC. FIG. 34 shows a circuit diagram of Comparator for DC, and FIG. 35 shows a circuit diagram of Comparator for UC.

The Sub-UC shown in FIG. 30 (a) is an N-type MOS transistor n23, n24, capacitance c23, c24 of the charge pump section that boosts the voltage from Out_UC_x by VDD, and a P-type MOS transistor p21 of the charge pump section that steps down by VDD from Out_UC_x. It is composed of p22, capacity c21, and c22. Further, from Q3 and Qb3, a signal having an amplitude of Out_UC_x + VDD is output from Out_UC_x- VDD. The above configuration is the same for the Sub-UC for REF shown in FIG. 30 (b), the Sub-DC shown in FIG. 31 (a), and the Sub-DC for REF shown in FIG. 31 (b).

Regarding the DC for REF shown in FIG. 32 (a), the input is changed from VSS to Out_DC_x in the DC for REF of the semiconductor device 20 shown in FIG. Regarding the UC for REF shown in FIG. 32 (b), the input is changed from VDD to Out_UC_x in the UC for REF of the semiconductor device 10 shown in FIG. Further, for the DC shown in FIG. 33 (a), the input is changed from VSS to Out_DC_x in the DC of the semiconductor device 20 shown in FIG. 22, and for the UC shown in FIG. 33 (b), the semiconductor device 10 shown in FIG. The input has been changed from VSS to Out_DC_x in UC. Further, for the Comparator for DC shown in FIG. 34, the VSS of the Comparator for DC shown in FIG. 24 is changed to Out_UC_x, and for the Comparator for UC shown in FIG. 35, the VDD of the Comparator for UC shown in FIG. 12 is changed to Out_DC_x. ..

ここで、N₀からN₆はトリミング信号Trim_REF[6:0]のトリミングコード値、Ｍは半導体装置１０または半導体装置２０の接続数を示している。（式３）または（式４）の場合、半導体装置１０または半導体装置２０のトリミング信号Trim_REF[6:0]は一律に制御されている。これを半導体装置１０または半導体装置２０において個別に制御すると、Out_UC_1からOut_UC_MまたはOut_DC_1からOut_DC_Mの各出力値を個別に変更できる。換言すれば、本実施の形態に係る半導体装置５０によればはOut_UC_1からOut_UC_Mの全出力を取り出し使用することができ、半導体装置６０によればOut_DC_1からOut_DC_Mまでの全出力を取り出し使用することができる。 According to the semiconductor device 50 or 60 according to the present embodiment, the semiconductor device 10 or the semiconductor device 20 according to the above embodiment can be connected in multiple stages to perform higher step-down and lower step-down. The operation of the semiconductor device 50 or 60 is a combination of the operations of the semiconductor device 10 or 20, and the difference is the value of the voltage finally output. Out_UC_M, which is the output voltage of the semiconductor device 50 according to the present embodiment, and Out_DC_M, which is the output voltage of the semiconductor device 60, can be represented by the following (Equation 3) or (Equation 4), respectively.

Here, N ₀ to N ₆ indicate the trimming code value of the trimming signal Trim_REF [6: 0], and M indicates the number of connections of the semiconductor device 10 or the semiconductor device 20. In the case of (Equation 3) or (Equation 4), the trimming signal Trim_REF [6: 0] of the semiconductor device 10 or the semiconductor device 20 is uniformly controlled. If this is individually controlled by the semiconductor device 10 or the semiconductor device 20, each output value from Out_UC_1 to Out_UC_M or Out_DC_1 to Out_DC_M can be changed individually. In other words, according to the semiconductor device 50 according to the present embodiment, all the outputs of Out_UC_M can be taken out and used, and according to the semiconductor device 60, all the outputs from Out_DC_1 to Out_DC_M can be taken out and used. can.

As described in detail above, according to the semiconductor device 50 or 60 according to the present embodiment, higher step-up and lower step-down are possible by connecting the semiconductor devices 10 or 20 in multiple stages. Further, each semiconductor device 10 or 20 can change the output individually. Further, the output of each semiconductor device 10 or 20 can be taken out and used individually.

In the semiconductor device 50 or 60 according to the present embodiment, by using the same method as the semiconductor device 30 shown in FIG. 25 or the semiconductor device 40 shown in FIG. 27, the VCO for is proportional to the speed of the Comparator for UC or the Comparator for DC. It is also possible to change the frequency of the UC or VCO for DC. Further, Out_REF in each of the above embodiments can be taken out as a reference signal.

Further, by connecting as follows, it is possible to design using a MOS transistor having a lower threshold value. That is, the back gate of the N-type MOS transistor n23 of the Sub-UC shown in FIG. 30 (a) is set to Q_1, the back gate of the N-type MOS transistor n24 is set to Qb_1, and the back gate of the Sub-UC for REF shown in FIG. 30 (b). The back gate of the N-type MOS transistor n33 is connected to Q_1_REF, and the back gate of the N-type MOS transistor n34 is connected to Qb_1_REF. The back gate of the P-type MOS transistor p21 of the Sub-UC shown in FIG. 30 (a) is set to Q_1, the back gate of the P-type MOS transistor p22 is set to Qb_1, and the P-type of the Sub-UC for REF shown in FIG. 30 (b). Connect the back gate of the MOS transistor p31 to Q_1_REF and the back gate of the P-type MOS transistor p32 to Qb_1_REF. Further, the back gate of the P-type MOS transistor p21 of the Sub-UC shown in FIG. 30 (a) is set to V_1, the back gate of the P-type MOS transistor p22 is set to Vb_1, and the back gate of the N-type MOS transistor n23 is set to Vb_1'. Connect the back gate of the N-type MOS transistor n24 to V_1'. The back gate of the P-type MOS transistor p31 of the Sub-UC for REF shown in FIG. 30 (b) is set to V_1, the back gate of the P-type MOS transistor p32 is set to Vb_1, and the back gate of the N-type MOS transistor n33 is set to Vb_1'. Connect the back gate of the N-type MOS transistor n34 to V_1'. The back gate of the P-type MOS transistor p21 of the Sub-UC shown in FIG. 30 (a) is set to Vb_1', the back gate of the P-type MOS transistor p22 is set to V_1', the back gate of the N-type MOS transistor n23 is set to V_1, and N Connect the back gate of the type MOS transistor n24 to Vb_1. The back gate of the P-type MOS transistor p31 of the Sub-UC for REF shown in FIG. 30 (b) is set to Vb_1', the back gate of the P-type MOS transistor p32 is set to V_1', and the back gate of the N-type MOS transistor n33 is set to V_1. , Connect the back gate of the N-type MOS transistor n34 to Vb_1. With the above connection, the effect of increasing the resistance value of the P-type MOS transistor and the N-type MOS transistor at the time of off can be expected, and the leakage current at the time of off can be suppressed. That is, it is possible to design using a MOS transistor having a lower threshold value.

10, 20, 30, 40, 50, 60 Semiconductor device 11, 21, 31, 41 Clock generation unit 12, 22, 32, 42 Control unit 13, 33 Booster unit 14, 24, 34, 44 Reference voltage generation unit 15, 25, 35, 45 Comparison unit 16, 26 Boost signal generation unit 17, 27 Reference signal generation unit 23, 43 Step-down unit 26 Boost signal generation unit 27 Reference signal generation unit 120, 220 1/2 divider 121 Non Overlap signal generation unit 122, 222 D latch unit 123, 223 Inverter unit 124, 224 1/4 divider 125, 225 Non-overlap signal generation unit 126, 226 Counter unit 127, 227 D latch unit 128, 228 Trimming signal Generation unit 129, 229 Trimming signal generation unit 221 Overlap signal generation unit
Clk VCO clock signal
Out COMP Comparison output
Out REF reference voltage
Out UC (DC) output voltage

Claims (13)

A voltage control oscillator that generates a clock signal whose frequency is controlled by an output control signal, and a conversion that synchronizes with the clock signal based on the conversion control signal synchronized with the clock signal and generates a converted voltage obtained by converting the power supply voltage. Voltage generator and
An output voltage generation unit that controls the conversion voltage based on the output control signal and the charge / discharge control signal to generate an output voltage.
A reference conversion voltage generation unit that generates a reference conversion voltage that is synchronized with the clock signal and converted into a power supply voltage based on the reference control signal synchronized with the clock signal.
A reference voltage generator that controls the reference conversion voltage based on the reference charge / discharge control signal to generate a reference voltage.
A comparison unit that compares the output voltage with the reference voltage based on the clock signal and generates the output control signal.
Semiconductor devices including. A current generation unit that generates a current corresponding to the clock signal, and a frequency control signal that controls the oscillation frequency of the voltage control oscillation unit by charging / discharging the current generated by the current generation unit based on the output control signal. The semiconductor device according to claim 1, further comprising a voltage control oscillation control unit including a frequency control signal generation unit to be generated. The second aspect of claim 2, wherein the voltage control oscillation unit has a field effect transistor to which the frequency control signal is input, and the output voltage is fed back to the voltage control oscillation unit via the back gate of the field effect transistor. Semiconductor equipment. The current generator uses a charge pump to generate a current according to the clock signal.
The semiconductor device according to claim 2 or 3, wherein the frequency control signal generation unit generates the frequency control signal by using a charge pump. A conversion signal generation unit that generates the conversion control signal and the charge / discharge control signal based on the clock signal, and a reference signal generation unit that generates the reference control signal and the reference charge / discharge control signal based on the clock signal. The semiconductor device according to any one of claims 1 to 4, further comprising a generation control unit including the unit. The conversion signal generation unit uses the clock signal divided by the first division ratio.
The semiconductor device according to claim 5, wherein the reference signal generation unit uses the clock signal divided by a second division ratio larger than the first division ratio. Any one of claims 1 to 6, wherein each of the conversion control signal, the reference control signal, the charge / discharge control signal, and the reference charge / discharge control signal is a non-overlap signal or an overlap signal. The semiconductor device according to the section. The conversion voltage generation unit generates the conversion voltage by multiplying the power supply voltage by a predetermined constant.
The semiconductor device according to any one of claims 1 to 7, wherein the reference conversion voltage generation unit generates the reference conversion voltage by multiplying the power supply voltage by a predetermined constant. The reference voltage generator has a plurality of charge / discharge capacities that can be adjusted by trimming, and includes a charge pump that generates the reference voltage.
The semiconductor device according to any one of claims 1 to 8, wherein the reference charge / discharge control signal is a trimming signal having a predetermined number of bits for selecting the plurality of charge / discharge capacities. The reference voltage generation unit has a reference capacitance connected to an output terminal of the reference voltage, and charges and discharges the reference capacitance at a predetermined ratio of the number of pulses of the clock signal in synchronization with the clock signal. The semiconductor device according to any one of claims 1 to 9, which generates the reference voltage. The output voltage generation unit has an output capacitance connected to an output terminal of the output voltage, synchronizes with the clock signal, and charges and discharges the output capacitance with the number of pulses of the clock signal at a predetermined ratio. The semiconductor device according to claim 10, wherein the output voltage is generated so that the output impedance of the output voltage generation unit and the load impedance connected to the output terminal are equal to each other. A semiconductor device including the semiconductor device according to any one of claims 1 to 11, which is connected in series. Generates a clock signal whose frequency is controlled by the output control signal,
The conversion voltage synchronized with the clock signal and converted into the power supply voltage based on the conversion control signal synchronized with the clock signal, and the power supply voltage synchronized with the clock signal based on the reference control signal synchronized with the clock signal. Generates the converted reference conversion voltage and
The output voltage is controlled based on the output control signal and the charge / discharge control signal so that the output impedance of the output voltage and the load impedance connected to the output terminal from which the output voltage is output are equal to each other. And control the reference conversion voltage based on the reference charge / discharge control signal to generate the reference voltage.
A voltage generation method for generating the output control signal by comparing the output voltage with the reference voltage based on the clock signal.

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