JP7065147B2 - Semiconductor device - Google Patents

Description

The present invention relates to a display device. In particular, the present invention relates to a display device using a silicon-based semiconductor and an oxide semiconductor.

Low temperature polycrystalline silicon (LTPS: Low Temperature Poly-Silicon) used in liquid crystal display devices has high carrier mobility, and is therefore a technique widely used in current small and medium-sized display devices. Also in organic EL display devices, the development of array processes has been promoted based on LTPS technology.

However, in the excimer laser annealing (ELA) step, it is difficult to form an LTPS layer with sufficiently small unevenness. Variations in thin film transistor (TFT) characteristics caused by uneven LTPS cause uneven brightness of the organic EL display device.

Therefore, measures are taken such as forming a correction circuit in a peripheral circuit or a pixel to reduce variations in TFT characteristics. Further, in the ELA process, measures are taken such that the laser is repeatedly irradiated many times. However, such measures have problems in terms of equipment cost, laser material cost, and the like.

Therefore, in order to reduce power consumption and prevent variations in transistor characteristics, we used not only transistors made of photoresist, which is said to have high driving ability, but also transparent amorphous oxide semiconductors, which are expected to have small variation in characteristics. Transistors are being studied.

For example, in Patent Document 1, one pixel has two or more transistors, and the two or more transistors have a first transistor in which the channel semiconductor layer is polycrystalline silicon and a second transistor in which the channel semiconductor layer is an oxide semiconductor. A display device including a transistor is disclosed.

JP-A-2015-225104

That is, in the invention described in Patent Document 1, a first transistor in which the channel semiconductor layer is polycrystalline silicon and a second transistor in which the channel semiconductor layer is an oxide semiconductor are mixedly mounted in one pixel.

However, Patent Document 1 does not disclose a technique in which a transistor, which is a semiconductor material having different channel semiconductor layers, is mixedly mounted in a circuit including a drive circuit for driving the plurality of pixel circuits in addition to the plurality of pixel circuits.

Therefore, in the present invention, in addition to a plurality of pixel circuits, in a circuit including a drive circuit for driving them, a transistor whose channel semiconductor layer is a different semiconductor material is mixedly mounted, thereby improving display characteristics and reducing manufacturing cost. One of the purposes is to provide the displayed display device.

The display device according to the embodiment of the present invention includes a substrate and a plurality of pixels arranged on one surface of the substrate, and each of the plurality of pixels is a light emitting element, a drive transistor, a selection transistor, and a holding capacity. The drive transistor has a bottom gate structure, the semiconductor layer of the drive transistor includes a first semiconductor, the holding capacity has a first electrode and a second electrode, and the first electrode is It is common with the gate of the drive transistor, and the second electrode is arranged below the first electrode and includes a second semiconductor.

It is a perspective view explaining the schematic structure of the display device which concerns on one Embodiment of this invention. It is a circuit diagram explaining the circuit structure of the display device which concerns on one Embodiment of this invention. It is a circuit diagram explaining the circuit structure of the pixel circuit which the pixel of the display device which concerns on one Embodiment of this invention has. It is a top view explaining the structure of the pixel of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the structure of the pixel of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is a top view explaining the structure of the pixel of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the structure of the pixel of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention. It is sectional drawing explaining the manufacturing method of the display device which concerns on one Embodiment of this invention.

Hereinafter, the display device according to some embodiments of the present invention will be described in detail with reference to the drawings. The display device of the present invention is not limited to the following embodiments, and can be modified in various ways. In all embodiments, the same components will be described with the same reference numerals. Further, the dimensional ratio of the drawing may differ from the actual ratio for convenience of explanation, or a part of the configuration may be omitted from the drawing.
<First Embodiment>
[Appearance composition]
FIG. 1 is a perspective view illustrating an external configuration of the display device 100 according to the present embodiment. The configuration of the appearance of the display device 100 according to the present embodiment will be described with reference to FIG.

The display device 100 according to the present embodiment has an array board 102 and a facing board 106.

The array board 102 has at least a first board 104, a plurality of pixels 110, peripheral circuits, and a plurality of connection terminals 112.

A display area 104a, a terminal area 104b, and a peripheral circuit area 104c are arranged on one surface of the first substrate 104. The first substrate 104 serves as a support for the plurality of pixels 110. As the material of the first substrate 104, a glass substrate, an acrylic resin substrate, an alumina substrate, a polyimide substrate and the like can be used. The first substrate 104 may be a flexible substrate. A resin material is used as the flexible substrate. As the resin material, it is preferable to use a polymer material containing an imide bond as a repeating unit, and for example, polyimide is used. Specifically, as the first substrate 104, a film substrate obtained by molding polyimide into a sheet is used.

The plurality of pixels 110 are arranged on one surface of the first substrate 104. The area where a plurality of pixels are arranged corresponds to the display area 104a. In this embodiment, the plurality of pixels 110 are arranged in a matrix. The number of arrangements of the plurality of pixels 110 is arbitrary. For example, m pixels 110 in the row direction and n pixels 110 in the column direction are arranged (m and n are integers). Each of the plurality of pixels 110 is not shown in FIG. 1, but is composed of a pixel circuit 130 having at least a drive transistor 132, a selection transistor 134, a light emitting element 136, and a holding capacity 138, as will be described later (FIG. 3).

The peripheral circuit is arranged on one surface of the first substrate 104. The area where the peripheral circuit is arranged corresponds to the peripheral circuit area 104c. The peripheral circuit drives a pixel circuit 130 provided in each of the plurality of pixels 110, and controls light emission of the plurality of pixels 110.

The plurality of connection terminals 112 are arranged at one end of the first substrate 104 and outside the facing substrate 106. The area where a plurality of connection terminals are arranged corresponds to the terminal area 104b. Wiring boards (not shown) that connect a device or power supply that outputs a video signal to the display device 100 are connected to the plurality of connection terminals 112. The contacts with the plurality of connection terminals 112 connected to the wiring board are exposed to the outside.

The facing substrate 106 has a second substrate 108. As the second substrate 108, the same substrate as the first substrate 104 may be used. The second substrate 108 is provided on the upper surface of the display area 104a so as to face the first substrate 104. The second substrate 108 is fixed to the first substrate 104 by a sealing material 170 surrounding the display area 104a. The display area 104a arranged on the first substrate 104 is sealed by the second substrate 108 and the sealing material 170. It should be noted that the sealing material 170 does not necessarily have to be used for fixing the first substrate 102 and the second substrate 108, and other means may be used. For example, the use of an adhesive filler or the like can be considered, and in this case, the display area 104a is sealed with the second substrate 108 and the adhesive filler. Of course, other methods may be used.

Although the display device 100 according to the present embodiment has the second substrate 108 as described above, the display device 100 is not limited to the plate-shaped member, but may be a film substrate, a sealing substrate coated with a resin or the like. It may be replaced.

Although not shown, the facing substrate 106 may further include a color filter, a light-shielding layer, a polarizing plate, a phase plate, and the like. The color filter is arranged at a position facing each of the plurality of pixels 110. The light-shielding layer (also referred to as a black matrix) is arranged at a position for partitioning each of the plurality of pixels 110. The polarizing plate and the phase plate cover the plurality of pixels 110 and are arranged on the outer surface of the facing substrate 106. The polarizing plate and the phase plate are arranged in order to suppress deterioration of visibility due to reflection of external light incident on the display device 100 by the pixel electrodes.

The configuration of the appearance of the display device 100 according to the present embodiment has been described above. Next, the circuit configuration of the display device 100 according to the present embodiment will be described with reference to the drawings.

[Circuit configuration]
FIG. 2 is a circuit diagram illustrating a circuit configuration of the display device 100 according to the present embodiment. FIG. 3 is a circuit diagram illustrating a circuit configuration of a pixel circuit 130 included in each of the plurality of pixels 110 of the display device 100 according to the present embodiment.

The display device 100 according to the present embodiment includes a peripheral circuit, a plurality of pixel circuits 130, a plurality of scanning signal lines 140, and a plurality of video signal lines 142.

The peripheral circuit drives a pixel circuit 130 provided in each of the plurality of pixels 110, and controls light emission of the plurality of pixels 110. Peripheral circuits include a control circuit 120, a scanning line drive circuit 122, a video line drive circuit 124, a drive power supply circuit 126, and a reference power supply circuit 128.

The semiconductor layer of the transistor included in the peripheral circuit includes the second semiconductor. The specific material of the second semiconductor will be described later (paragraph [0040]).

The control circuit 120 controls the operation of the scanning line drive circuit 122, the video line drive circuit 124, the drive power supply circuit 126, and the reference power supply circuit 128.

The scan line drive circuit 122 is connected to a plurality of scan signal lines 140. The plurality of scanning signal lines 140 are provided for each horizontal arrangement (pixel row) of the plurality of pixels 110. The scanning line drive circuit 122 sequentially selects a plurality of scanning signal lines 140 according to the timing signal input from the control circuit 120.

The video line drive circuit 124 is connected to a plurality of video signal lines 142. The plurality of video signal lines 142 are provided for each vertical arrangement (pixel sequence) of the plurality of pixels 110. The video line drive circuit 124 receives a video signal from the control circuit 120, and sets a voltage corresponding to the video signal of the selected pixel line in accordance with the selection of the scan signal line 140 by the scan line drive circuit 122 as a plurality of video signals. Write through each of the lines 142.

The drive power supply circuit 126 is connected to a drive power supply line 144 provided for each pixel row. The drive power supply circuit 126 supplies a current that causes the pixel 110 of the selected pixel row to emit light.

The reference power supply circuit 128 is connected to a reference power supply line 146 that is commonly provided in the plurality of pixels 110. The reference power supply circuit 128 applies a constant potential to the common electrodes constituting the cathode electrode of the light emitting element 136.

Next, each circuit configuration of the plurality of pixel circuits 130 will be described with reference to FIG. The circuit configuration of the pixel circuit 130 described below is an example, and is not limited thereto.

Each of the plurality of pixel circuits 130 includes at least a drive transistor 132, a selection transistor 134, a light emitting element 136, and a holding capacity 138.

The drive transistor 132 is a transistor connected to the light emitting element 136 and controlling the light emitting luminance of the light emitting element 136. The drain current of the drive transistor 132 is controlled by the gate-source voltage. In the drive transistor 132, the gate is connected to the drain of the selection transistor 134, the source is connected to the drive power line 144, and the drain is connected to the anode of the light emitting element 136. The semiconductor layer 132d of the drive transistor 132 includes a first semiconductor. The specific material of the first semiconductor will be described later.

The selection transistor 134 is a transistor that controls the conduction state between the video signal line 142 and the gate of the drive transistor 132 by on / off operation. In the selection transistor 134, the gate is connected to the scanning signal line 140, the source is connected to the video signal line 142, and the drain is connected to the gate of the drive transistor 132. The semiconductor layer 134d of the selection transistor 134 includes the first semiconductor like the drive transistor 132. The specific material of the first semiconductor will be described later.

That is, in the present embodiment, the semiconductor (second semiconductor) included in the transistors constituting the peripheral circuit is different from the semiconductor (first semiconductor) included in the selection transistor 134 and the drive transistor 132.

In the light emitting element 136, the anode is connected to the drain of the drive transistor 132, and the cathode is connected to the reference power supply line 146.

The holding capacity 138 is connected between the gate and the drain of the drive transistor 132. The holding capacity 138 holds the gate-drain voltage of the drive transistor 132.

The circuit configuration of the peripheral circuit of the display device 100 and the circuit configuration of the pixel circuit 130 included in each of the plurality of pixels 110 according to the present embodiment have been described above. Here, the characteristics required for the transistors constituting the peripheral circuit, the drive transistor 132 constituting the pixel circuit 130, and the selection transistor 134 will be described. Further, specific materials for the first semiconductor and the second semiconductor will be described. The transistors constituting the peripheral circuit, the drive transistor 132 constituting the pixel circuit 130, and the selection transistor 134 have different required characteristics.

As for the transistor included in the peripheral circuit, it is preferable that the peripheral circuit has high carrier mobility and can form CMOS in order to satisfy the constraint conditions regarding the width of the frame, power consumption and the like. Therefore, in this embodiment, polycrystalline silicon is used as the second semiconductor included in the transistor constituting the peripheral circuit.

The drive transistor 132 is driven in a saturated state. Therefore, it is preferable to have a saturation characteristic with little variation in the on state. Further, it is desirable to have a channel length of a certain level or more. If the channel length of the drive transistor 132 is too short, variations due to the so-called short-channel effect become apparent.

Therefore, as the first semiconductor of the drive transistor 132, a semiconductor capable of suppressing the variation in the on state as much as possible is preferable. In this embodiment, an oxide semiconductor is used as the first semiconductor. When polycrystalline silicon is used as the first semiconductor, variations due to laser irradiation during ELA (Excimer Laser Anneal) occur, but this problem can be avoided by using an oxide semiconductor as the first semiconductor. can.

The selection transistor 134 is desired to have good switching characteristics. That is, it is preferable that the current value in the on state is large and the current value in the off state is small.

Therefore, as the first semiconductor of the selective transistor 134, it is preferable to use a material capable of suppressing the leakage current in the off state of the selective transistor 134 as much as possible. In this embodiment, an oxide semiconductor is used as the first semiconductor as described above. It is known that a transistor using an oxide semiconductor has a sufficiently small leakage current in the off state as compared with a transistor using a silicon-based semiconductor.

Thereby, the selection transistor 134 can reduce the leakage current in the off state. As a result, referring to the pixel circuit 130 shown in FIG. 3, even when the selection transistor 134 is off, it is possible to prevent the charge of the holding capacitance 138 from disappearing due to the leak current between the source and the drain.

Next, the configuration of each of the plurality of pixels 110 included in the display device 100 according to the present embodiment will be described in detail with reference to the drawings.

[Pixel composition]
FIG. 4 is a plan view illustrating the configuration of the pixel 110 included in the display device 100 according to the present embodiment. FIG. 5 is a cross-sectional view illustrating the configuration of the pixel 110 included in the display device 100 according to the present embodiment. FIG. 5 shows a cross section between AA'and BB' in FIG.

The display device 100 according to the present embodiment includes a first substrate 104 and a plurality of pixels 110.

A display area 104a, a terminal area 104b, and a peripheral circuit area 104c are arranged on one surface of the first substrate. Examples of materials that can be used for the first substrate 104 have been described in the description of the appearance configuration.

The plurality of pixels 110 are arranged on one surface of the first substrate 104. The area where the plurality of pixels 110 are arranged corresponds to the display area 104a. Each of the plurality of pixels 110 includes at least a light emitting element 136, a drive transistor 132, a selection transistor 134, a holding capacity 138, a first contact electrode 174a, and a second contact electrode 174b.

The holding capacity 138 is arranged on the first insulating layer 152. The first insulating layer 152 is arranged on one surface of the first substrate 104 over at least the display area 104a. The first insulating layer 152 prevents foreign substances such as impurities contained in the first substrate 104 from invading each of the plurality of pixels 110. As the material of the first insulating layer 152, an inorganic insulating material can be used. As the inorganic insulating material, for example, silicon oxide, silicon nitride and the like can be used. Alternatively, a laminated structure in which these are combined may be used.

The holding capacity 138 has a first electrode 138a and a second electrode 138b. The first electrode 138a is common with the gate 132a of the drive transistor 132. The second electrode 138b is arranged below the first electrode 138a. The material of the second electrode 138b includes a second semiconductor. In the present embodiment, the second semiconductor is polycrystalline silicon as described above. Since the second semiconductor bears one electrode of the capacitance, it is preferable that the carrier mobility is high and the carrier density is high. In the present embodiment, the second electrode is provided with n-type conductivity by injecting impurities such as phosphorus (P) into polycrystalline silicon at a high concentration. Hereinafter, the second semiconductor may be referred to as polycrystalline silicon and will be described.

The holding capacity 138 is formed by the first electrode 138a and the second electrode 138b sandwiching the second insulating layer 154. The second insulating layer 154 is sandwiched between the first electrode and the second electrode in the layer structure. Further, the second insulating layer 154 is arranged over at least the display area 104a in the planar structure. As the material of the second insulating layer 154, the same material as the above-mentioned first insulating layer 152 may be used.

The drive transistor 132 has a so-called bottom gate structure in which a gate is arranged below the semiconductor layer via a gate insulating layer. The semiconductor layer 132d of the drive transistor 132 includes a first semiconductor. In the present embodiment, the first semiconductor is an oxide semiconductor as described above. Hereinafter, the first semiconductor may be referred to as an oxide semiconductor and described. The gate 132a of the drive transistor 132 is common with the first electrode 138a having a holding capacity of 138.

The gate insulating layer of the drive transistor 132 is a third insulating layer 156. The third insulating layer 156 is arranged on the upper layer of the holding capacity 138 for the layer structure. Further, the third insulating layer 156 is arranged over the display area 104a for the planar structure. The third insulating layer 156 functions as a gate insulating layer of the driving transistor 132 and the selection transistor 134. As the material of the third insulating layer 156, the same material as the above-mentioned first insulating layer 152 may be used.

As can be seen from FIG. 4, the channel region of the drive transistor 132 has a region that overlaps with the second electrode 138b in a plan view. Here, the channel region is a region where carriers are accumulated and a channel is formed at the interface between the semiconductor layer and the gate insulating layer. In the present embodiment, the channel region of the drive transistor 132 includes the entire region occupied by the second electrode 138b in a plan view.

That is, the drive transistor 132 and the holding capacity 138 are arranged in different layers in the layer structure, and are arranged in the overlapping region in the plan view. By having such a configuration, the area occupied by the elements arranged in one pixel can be reduced. As a result, the size of one pixel can be reduced to provide a high-definition display device 100.

Further, as can be seen from FIG. 4, the gate 132a of the drive transistor 132 is connected to the jumper wiring 148. The jumper wiring 148 is arranged on the fourth insulating layer 158 and connects the gate 132a of the driving transistor 132 and the drain 134c of the selection transistor 134. The source 132b of the drive transistor 132 is connected to the drive power line 144. The drive power line 144 is arranged on the fourth insulating layer 158. The drain 132c of the drive transistor 132 is connected to the pixel electrode 164. The pixel electrode 164 is arranged on the flattening insulating layer 160.

The selection transistor 134 has a so-called bottom gate structure in which a gate is arranged below the semiconductor layer via a gate insulating layer. The semiconductor layer 134d of the selection transistor 134 includes a first semiconductor (oxide semiconductor) and is arranged in the same layer as the semiconductor layer 132d of the drive transistor 132. In the manufacturing process, the semiconductor layer 134d of the selection transistor 134 and the semiconductor layer 132d of the drive transistor 132 may be formed at the same time by the same photolithography process.

Further, the gate 134a of the selection transistor 134 is arranged on the same layer as the gate 132a of the drive transistor 132. That is, it can be said that the gate 134a of the selection transistor 134 is arranged in the same layer as the first electrode 138a having the holding capacity 138.

As can be seen from FIG. 4, the gate 134a of the selection transistor 134 extends from the scanning signal line 140. The scanning signal line 140 is arranged on the second insulating layer 154. That is, the scanning signal line 140 also serves as the gate 134a of the selection transistor 134. The source 134b of the selection transistor 134 is connected to the video signal line 142. The video signal line 142 is arranged on the fourth insulating layer 158. The drain 134c of the selection transistor 134 is connected to the jumper wiring 148. The jumper wiring 148 is arranged on the fourth insulating layer 158 and is provided to connect the gate 132a of the driving transistor 132 and the drain 134c of the selection transistor 134. The fourth insulating layer 158 is arranged on the upper layer of the driving transistor 132 and the selection transistor 134 in terms of the layer structure. Further, the fourth insulating layer 158 is arranged over the display area 104a for the planar structure. As the material of the fourth insulating layer 158, the same material as the above-mentioned first insulating layer 152 may be used.

The first contact electrode 184a is provided in the first contact hole 182a that reaches the source 132b of the drive transistor 132 from a layer above the drive transistor 132. The first contact hole 182a is provided at a position superimposing on the source 132b of the drive transistor 132 in a plan view, and penetrates the fourth insulating layer 158. The first contact electrode 174a is connected to the source 132b of the drive transistor 132. As a result, the power supply potential line and the source 132b of the drive transistor 132 are connected.

The second contact electrode 184b is provided in the second contact hole 182b that reaches the second electrode 138b from a layer above the drive transistor 132. The second contact hole 182b is provided at a position superimposing on the drain 132c of the drive transistor 132 in a plan view, and penetrates the fourth insulating layer 158, the drain 132c of the drive transistor 132, the third insulating layer 156, and the second insulating layer 154. do. As a result, the second contact electrode 174b is connected to the drain 132c of the drive transistor 132 and the second electrode 138b. As a result, the drain 132c of the drive transistor 132 and the second electrode 138b having the holding capacity 138 are connected. Here, the second contact electrode 184b contacts not only the side wall of the opening penetrating the drain 132c but also the surface around the end of the opening. As a result, it is possible to suppress electrical contact failure between the drain 132c of the drive transistor 132 and the contact electrode 184b.

Here, the first contact hole 182a and the second contact hole 182b have different depths, but can be formed simultaneously by the same photolithography process. When the drain 132c of the drive transistor 132 is formed by the photolithography process, the layout may have an opening at a position where the second contact hole 182b is formed. Alternatively, when the drain 132c of the drive transistor 132 is formed by the photolithography step, the layout may be such that the end portion is in contact with the position where the second contact hole 182b is formed. As a result, the source 132b of the drive transistor 132 serves as an etch stopper for the first contact hole 182a, and the second electrode 138b having a holding capacity of 138 serves as an etch stopper for the second contact hole 182b.

A third electrode 138c extends from the second contact electrode 184b on the fourth insulating layer 158. As shown in FIG. 4, the third electrode 138c has a region overlapping with the second electrode 138b having a holding capacity of 138. In the present embodiment, the third electrode 138c covers the region occupied by the second electrode 138b in a plan view. Thereby, the capacitance can be further formed by the third electrode 138c and the second electrode 138b.

The light emitting element 136 is provided on the flattening insulating layer 160. The light emitting element 136 is a self-luminous type light emitting element. As the self-luminous light emitting element, for example, an organic EL light emitting element can be used. The organic EL light emitting device has a pixel electrode 164, a common electrode 166, and a light emitting layer 168.

The pixel electrode 164 is arranged for each of the plurality of pixels 110. The material of the pixel electrode 164 preferably includes a metal layer having a high reflectance in order to reflect the light generated in the light emitting layer 168 toward the common electrode 166. As the metal layer having a high reflectance, for example, silver (Ag) can be used.

Further, in addition to the above-mentioned metal layer having high reflectance, a transparent conductive layer may be laminated. As the transparent conductive layer, for example, ITO (indium oxide-added indium oxide), IZO (indium oxide / zinc oxide), or the like is preferably used. Moreover, you may use any combination thereof.

The common electrode 166 is arranged over a plurality of pixels 110. As the material of the common electrode 166, a material having translucency and conductivity is preferable in order to transmit the light generated in the light emitting layer 168. As the material of the common electrode 166, for example, ITO (indium oxide-added indium oxide), IZO (indium oxide / zinc oxide) and the like are preferable. Alternatively, as the common electrode 166, a metal layer having a film thickness such that the emitted light can be transmitted may be used. The common electrode 166 may be divided into a plurality of blocks shared by a plurality of pixels 110 instead of the arrangement covering all the pixels as in the present embodiment, or may be provided independently for each pixel 110. good.

The light emitting layer 168 is sandwiched and arranged between the pixel electrode 164 and the common electrode 166. The material of the light emitting layer 168 is an organic EL material that emits light when an electric current is supplied. As the organic EL material, a small molecule-based or high-molecular-weight organic material can be used. When a small molecule organic material is used, the light emitting layer 168 has a hole injection layer, an electron injection layer, a hole transport layer, and an electron transport layer so as to sandwich the light emitting organic material in addition to the light emitting organic material. Etc. are included.

The flattening insulating layer 160 is arranged on the fourth insulating layer 158. The flattening insulating layer 160 is provided to flatten unevenness caused by various transistors and wiring arranged in the lower layer. As the material of the flattening insulating layer 160, an organic insulating material can be used. As the organic insulating material, acrylic resin, polyimide resin and the like can be used.

A bank 162 is provided between two adjacent pixels 110. The bank 162 is provided so as to cover the peripheral edge portion of the pixel electrode 164. Further, it is provided so as to cover the connection portion between the drain 132c of the drive transistor 132 and the pixel electrode 164.

As the material of the bank 162, it is preferable to use an insulating material. As the insulating material, an inorganic insulating material or an organic insulating material can be used. As the inorganic insulating material, for example, silicon oxide, silicon nitride, or a combination thereof can be used. As the organic insulating material, for example, a polyimide resin, an acrylic resin, or a combination thereof can be used. A combination of an inorganic insulating material and an organic insulating material may be used.

By arranging the bank 162 formed of the insulating material, it is possible to prevent the common electrode 166 and the pixel electrode 164 from being short-circuited at the end of the pixel electrode 164. Further, it is possible to reliably insulate between adjacent pixels 110.

[Production method]
6A to 6O are plan views illustrating a method of manufacturing the display device 100 according to the present embodiment. In these figures, the cross section between AA'and BB'in FIG. 4 is shown.

First, the first insulating layer 152 is formed on the first substrate 104, and the polycrystalline silicon layer 171 is formed on the first insulating layer 152 (FIG. 6A).

As the material of the first insulating layer 152, an inorganic insulating material can be used. As the inorganic insulating material, for example, silicon oxide, silicon nitride and the like can be used. Alternatively, a laminated structure in which these are combined can be used. As a film forming method, for example, a CVD method can be used.

To form the polycrystalline silicon layer, first, an amorphous silicon layer is formed by a CVD method. Then, it is polycrystalline by heat treatment or an ELA (Excimer Laser Anneal) method to obtain a polycrystalline silicon layer 171.

Next, the polycrystalline silicon layer 171 is patterned by a photolithography step to form an island-shaped polycrystalline silicon layer 172 (FIG. 6B). In this step, a layer to be the second electrode of the holding capacity and a semiconductor layer of a transistor included in a peripheral circuit (not shown) are formed at the same time.

Next, the polycrystalline silicon layer 172 is subjected to ion implantation treatment as many times as necessary (FIG. 6C). Impurities such as phosphorus (P) are injected to form an n-type region, and impurities such as boron (B) are injected to form a p-type region. In the drawing, the second electrode 138b having a holding capacity is shown, and impurities such as phosphorus (P) are injected into the polycrystalline silicon layer at a high concentration to impart n-type conductivity. As a result, the second electrode 138b having a holding capacity of 138 is formed.

In the above steps, an example in which ion implantation is performed after patterning of the polycrystalline silicon layer 172 is shown, but the order is not limited to this and may be reversed.

Next, a second insulating layer 154 is formed, and a first metal layer 176 is formed on the second insulating layer 154 (FIG. 6D). The second insulating layer 154 is an insulating layer constituting the holding capacity 138. As the second insulating layer 154, an inorganic insulating material can be used. As the inorganic insulating material, for example, silicon oxide, silicon nitride and the like can be used. As a film forming method, for example, a CVD method can be used.

As the first metal layer 176, for example, W, MoW, Mo / Al / Mo, Ti / Al / Ti and the like can be used. As a film forming method, for example, a sputtering method can be used.

Next, the first metal layer 176 is patterned by a photolithography step (FIG. 6E). As the etching method, dry etching or wet etching can be used. By this step, the gate 132a of the drive transistor which also serves as the first electrode 138a of the holding capacity 138, the gate 134a of the selection transistor, and the scanning signal line 140 are formed.

Next, a third insulating layer 156 is formed, and a first semiconductor layer (oxide semiconductor layer) 174 is formed on the third insulating layer 156 (FIG. 6F). The third insulating layer 156 is an insulating layer constituting the gate insulating layer of the driving transistor and the selection transistor. As the third insulating layer 156, an inorganic insulating material can be used. As the inorganic insulating material, for example, silicon oxide, silicon nitride and the like can be used. As a film forming method, for example, a CVD method can be used.

As a film forming method of the oxide semiconductor layer 174, a sputtering method can be used. In the film formation by the sputtering method, the substrate is heated at the time of film formation, the mixed gas Ar / O2 is used, and the gas ratio is Ar <O2. As the power supply for sputtering, a DC power supply or an RF power supply may be used, and the power supply can be determined according to the forming conditions of the sputtering target. If the sputtering target is, for example, InGaZnO, In: Ga: Zn: O = 1: 1: 1: 4 (In2O3: Ga2O3: ZnO = 1: 1: 2) or the like can be used, and the composition ratio is the object (In2O3: Ga2O3: ZnO = 1: 1: 2). It can be determined according to the transistor characteristics, etc.).

An annealing treatment may be performed from the oxide semiconductor layer 174 in order to improve the film quality such as dehydrogenation and density improvement. As the annealing conditions, the atmosphere (vacuum, nitrogen, dry air, or atmosphere), temperature (250 to 500 ° C.), and time (15 minutes to 1 hour) can be determined according to the purpose.

Next, the oxide semiconductor layer 174 is patterned by a photolithography step (FIG. 6G). As a result, the semiconductor layer 132d of the driving transistor 132 and the semiconductor layer 134d of the selection transistor 134 are formed at the same time.

In this embodiment, an example in which annealing is performed before patterning of the oxide semiconductor layer 174 is shown, but the annealing is not limited to this, and annealing may be performed before or after patterning. When the temperature is high, it is preferable before patterning in order to suppress pattern shift due to shrinkage of the oxide semiconductor layer 174.

Next, the second metal layer 178 is formed (FIG. 6H). As the second metal layer 178, for example, W, MoW, Mo / Al / Mo, Ti / Al / Ti and the like can be used. As a film forming method, for example, a sputtering method can be used.

The second metal layer 178 is then patterned by a photolithography step (FIG. 6I). As the etching method, dry etching or wet etching can be used. By this step, the source / drain of the drive transistor 132 and the source / drain of the selection transistor 134 are formed.

Here, at least one opening 133 is formed in the drain 132c of the drive transistor 132. By later forming the contact hole, the first contact hole 182a reaching the source 132b of the drive transistor 132 and the second contact hole 182b penetrating the drain 132c of the drive transistor 132 and reaching the second electrode 138b are simultaneously formed. Because.

Next, the fourth insulating layer 158 is formed (FIG. 6J). As the fourth insulating layer 158, an inorganic insulating material can be used. As the inorganic insulating material, for example, silicon oxide, silicon nitride and the like can be used. As a film forming method, for example, a CVD method can be used.

Next, a plurality of contact holes are formed from the fourth insulating layer 158 by a photolithography step (FIG. 6K). In the present embodiment, the first contact hole 182a that reaches the source 132b of the drive transistor 132, the second contact hole 182b that penetrates the drain 132c of the drive transistor 132 and reaches the second electrode 138b, and the source 134b of the selection transistor 134. A third contact hole 182c reaching the third contact hole 182c and a fourth contact hole 182d reaching the drain 134c of the drive transistor 134 are simultaneously formed. The second contact hole 182b is provided at a position superimposing on the opening 133 provided in advance in the drain 132c of the drive transistor 132. As a result, the first contact hole 182a, the second contact hole 182b, the third contact hole 182c, and the fourth contact hole 182d are the source 132b of the drive transistor 132, the second electrode 138b of the holding capacity 138, and the source of the selection transistor 134, respectively. Since the drain 134c of the selection transistor 134 and the 134b serve as an etch stopper, these contact holes having different depths can be formed at the same time.

At this time, the second contact hole 182b is formed so as to have a region overlapping with the opening 133 in a plan view. Further, at this time, it is preferable that the second contact hole 182b is formed over a region including the region of the opening 133. Alternatively, the area of the second contact hole 182b is preferably larger than the area of the opening 133.

As a result, in the drain 132c of the drive transistor 132, the surface around the end of the opening 133 and the side wall of the opening 133 are exposed. As a result, when the contact electrode is formed later, the second contact electrode 184b that fills the second contact hole 182b is not only on the side wall of the opening 133 but also on the surface around the end of the opening 133 with respect to the drain 132c. Also come into contact. As a result, it is possible to suppress electrical contact failure between the drain 132c of the drive transistor 132 and the contact electrode 184b.

Next, a third metal layer is formed, and the third metal layer is patterned by a photolithography step (FIG. 6L). As the third metal layer, for example, W, MoW, Mo / Al / Mo, Ti / Al / Ti and the like can be used. As a film forming method, for example, a sputtering method can be used. As the etching method, dry etching or wet etching can be used. By this step, the video signal line 142, the drive power supply line 144, and the jumper wiring 148 are formed, and the first contact electrode 184a, the second contact electrode 184b, the third contact electrode 184c, and the fourth contact electrode 184d are formed. ..

Here, the second contact electrode 184b connects the drain 132c of the drive transistor 132 and the second electrode 138b having a holding capacity of 138. As described above, the second contact electrode 184b contacts not only the side wall of the opening 133 but also the surface around the end of the opening 133 with respect to the drain 132c. As a result, it is possible to suppress electrical contact failure between the drain 132c of the drive transistor 132 and the contact electrode 184b.

Next, a flattening insulating layer 160 is formed on the above-mentioned various wirings to form a desired contact opening (FIG. 6M). The flattening insulating layer 160 is provided to flatten unevenness caused by various transistors and wiring arranged in the lower layer. As the material of the flattening insulating layer 160, an organic insulating material can be used. As the organic insulating material, acrylic resin, polyimide resin and the like can be used. As a film forming method, for example, a coating method can be used.

Next, the pixel electrode 164 is formed on the flattening insulating layer 160 (FIG. 6N). As described above, the material of the pixel electrode 164 preferably includes a metal layer having a high reflectance such as silver (Ag). Further, a transparent conductive layer such as ITO (indium oxide-added indium oxide) or IZO (indium oxide / zinc oxide) may be laminated.

Next, a bank 162 is formed between two adjacent pixels 110 (FIG. 6O). The bank 162 is provided so as to cover the peripheral edge portion of the pixel electrode 164. As the material of the bank 162, it is preferable to use an insulating material. As the insulating material, as described above, an inorganic insulating material or an organic insulating material can be used.

Next, a light emitting layer 168 is formed so as to cover the pixel electrodes 164 and the bank 162, and a common electrode 166 that covers the plurality of pixels 110 in the display area 104a is formed to complete the array substrate 102 shown in FIG. .. A thin-film deposition method can be used as the film-forming method for the light emitting layer 168. As a film forming method of the common electrode 166, a sputtering method can be used.

The configuration and manufacturing method of the display device 100 according to the present embodiment have been described above. The display device 100 according to the present embodiment can satisfy the constraint conditions of the width of the frame and the power consumption by using polycrystalline silicon for the transistor constituting the peripheral circuit. Further, by using an oxide semiconductor for the drive transistor 132 constituting the pixel circuit 130, it is possible to suppress variations in the amount of light emitted from the pixel 110. Further, by using an oxide semiconductor for the selection transistor 134 constituting the pixel circuit 130, it is possible to prevent the charge of the holding capacity 138 from disappearing due to the leakage current between the source and the drain. Further, by superimposing the drive transistor 132 and the holding capacity 138 in a plan view, the size of the pixel 110 can be reduced, and a high-definition display device 100 can be provided.

<Second Embodiment>
The configuration of the display device 200 (FIG. 8) according to the present embodiment will be described with reference to the drawings. The matters specifying the invention that are common to the display device 100 according to the first embodiment and the display device 200 according to the present embodiment may be omitted, and the differences will be mainly described.

The display device 200 according to the present embodiment has a different configuration of the selection transistor 134 included in each of the plurality of pixels 110 as compared with the display device 100 according to the first embodiment. Specifically, the semiconductor layer 134d of the selection transistor 134 includes a second semiconductor.

As described above, the selection transistor 134 is desired to have good switching characteristics. That is, it is preferable that the current value in the on state is large and the current value in the off state is small.

Therefore, it is preferable to use a material having high carrier mobility as the second semiconductor of the selection transistor 134. As described in the first embodiment, the second semiconductor is polycrystalline silicon.

Thereby, the selection transistor 134 can supply a sufficiently large current in the on state. Thereby, referring to the pixel circuit 130 shown in FIG. 3, it is possible to suppress the increase in resistance between the video signal line 142 and the gate 132a of the drive transistor 132 in the on state of the selection transistor 134.

FIG. 7 is a plan view illustrating the configuration of the pixel 110 included in the display device 200 according to the present embodiment. FIG. 8 is a cross-sectional view illustrating the configuration of the pixel 110 included in the display device 200 according to the present embodiment. FIG. 8 shows a cross section between AA ′ and BB ′ in FIG. 7.

The selection transistor 134 has a so-called top gate structure in which a gate is arranged above the semiconductor layer via a gate insulating layer. The semiconductor layer 134d of the selection transistor 134 includes a second semiconductor (polycrystalline silicon) and is arranged on the same layer as the second electrode 138b having a holding capacity of 138.

In this embodiment, the selective transistor 134 has a so-called staggered structure in which the electrodes of the gate 134a, the source 134b, and the drain 134c are arranged above the polycrystalline silicon layer 172. Therefore, as compared with the selection transistor 134 of the display device 100 according to the first embodiment having an inverted stagger type structure, the parasitic capacitance is small and the switching operation is speeded up.

[Production method]
9A to 9E are cross-sectional views illustrating a method of manufacturing the display device 200 according to the present embodiment. In these figures, the cross section between AA'and BB'in FIG. 7 is shown.

First, the first insulating layer 152 is formed on the first substrate 104, and the polycrystalline silicon layer 172 is formed on the first insulating layer 152 (FIG. 9A). Since the steps up to this point are the same as the manufacturing method of the display device 100 according to the first embodiment, detailed description thereof will be omitted.

Next, the polycrystalline silicon layer 172 is patterned by a photolithography step (FIG. 9B). In this step, a layer serving as a second electrode 138b having a holding capacity of 138, a semiconductor layer 134d of the selection transistor 134, and a semiconductor layer of a transistor included in a peripheral circuit (not shown) are simultaneously formed.

Next, the polycrystalline silicon layer 172 is subjected to ion implantation treatment as many times as necessary (FIG. 9C). Impurities such as phosphorus (P) are injected to form an n-type region, and impurities such as boron (B) are injected to form a p-type region. In the drawing, a second electrode 138b having a holding capacity of 138 is shown, and impurities such as phosphorus (P) are injected into the polycrystalline silicon layer 172 at a high concentration to impart n-type conductivity. .. At the same time, the semiconductor layer 134d of the selective transistor 134 is shown, and impurities such as phosphorus (P) are selectively injected into the source / drain region of the semiconductor layer 134d at a high concentration, resulting in n-type conductivity. It has been granted.

Since the steps from the next step to the formation of the source / drain of the drive transistor 132 and the source / drain of the selective transistor 134 (FIG. 9D) are the same as those of the first embodiment, the description thereof will be omitted.

After forming the source / drain of the drive transistor 132 and the source / drain of the selective transistor 134, the fourth insulating layer 158 is formed (FIG. 9E).

The method of forming a plurality of contact holes after the formation of the fourth insulating layer 158 is different from that of the first embodiment. In the present embodiment, the layers reached by the third contact hole 182c and the fourth contact hole 182d are different from those in the first embodiment. In the present embodiment, etching is performed under the condition that both the third contact hole 182c and the fourth contact hole 182d reach the semiconductor layer 134d of the selection transistor 134 (FIG. 9D). At this time, for the first contact hole 182a, the source 132b of the drive transistor 132 serves as an etch stopper, and for the second contact hole 182, the second electrode 138b serves as an etch stopper. Thereby, these contact holes having different depths can be formed at the same time.

At this time, as in the first embodiment, the second contact hole 182b is formed so as to have a region overlapping with the opening 133 in a plan view. Further, at this time, it is preferable that the second contact hole 182b is formed over a region including the region of the opening 133. Alternatively, the area of the second contact hole 182b is preferably larger than the area of the opening 133.

As a result, in the drain 132c of the drive transistor 132, the surface around the end of the opening 133 and the side wall of the opening 133 are exposed. As a result, when the contact electrode is formed later, the second contact electrode 184b that fills the second contact hole 182b is not only on the side wall of the opening 133 but also on the surface around the end of the opening 133 with respect to the drain 132c. Also come into contact. As a result, it is possible to suppress electrical contact failure between the drain 132c of the drive transistor 132 and the contact electrode 184b.

Next, a third metal layer is formed, and the third metal layer is patterned by a photolithography step (FIG. 9G). By this step, the video signal line 142, the drive power supply line 144 and the 148 jumper wiring are formed, and the first contact electrode 184a, the second contact electrode 184b, the third contact electrode 184c and the fourth contact electrode 184d are formed. .. Since the following steps are the same as those in the first embodiment, the description thereof will be omitted.

The configuration and manufacturing method of the display device 200 according to the present embodiment have been described above. The display device 200 according to the present embodiment can satisfy the constraint conditions such as the width of the frame and the power consumption by using polycrystalline silicon for the transistor constituting the peripheral circuit. Further, by using an oxide semiconductor for the drive transistor 132 constituting the pixel circuit 130, it is possible to suppress variations in the amount of light emitted from the pixel 110. Further, by using polysilicon for the selection transistor 134 constituting the pixel circuit 130, it is possible to suppress high resistance between the video signal line 142 and the gate 132a of the drive transistor 132 when the selection transistor 134 is on. can do. Further, by superimposing the drive transistor 132 and the holding capacity 138 in a plan view, the size of the pixel 110 can be reduced, and a high-definition display device 200 can be provided.

Although some embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the present invention. Needless to say, it is included in the scope of the invention.

100, 200: Display device 102: Array board 104: First board 104a: Display area 104b: Terminal area 104c: Peripheral circuit area 106: Opposite board 108: Second board 110: Pixel 112: Connection terminal 120: Control circuit 122: Scanning line drive circuit 124: Video line drive circuit 126: Drive power supply circuit 128: Reference power supply circuit 130: Pixel circuit 132: Drive transistor 132a: Gate 132b: Source 132c: Drain 132d: Semiconductor layer 132e: Gate insulation layer 134: Select transistor 134a: Gate 134b: Source 134c: Drain 134d: Semiconductor layer 134e: Gate insulation layer 136: Light emitting element 138: Holding capacity 140: Scan signal line 142: Video signal line 144: Drive power line 146: Reference power line 148: Jumper wiring 152: 1st insulating layer 154: 2nd insulating layer 156: 3rd insulating layer 158: 4th insulating layer 160: Flattening insulating layer 162: Bank 164: Pixel electrode 166: Common electrode 168: Light emitting layer 170: Sealing material 171 , 172: Polycrystalline silicon layer 174 Oxide semiconductor layer 176: First metal layer 178: Second metal layer 182a: First contact hole 182b: Second contact hole 182c: Third contact hole 182d: Fourth contact hole 184a: 1st contact electrode 184b: 2nd contact electrode 184c: 3rd contact electrode 184d: 4th contact electrode

Claims (3)

With the board
It has a first transistor formed on the substrate and a capacitive element, and has.
The first transistor has a first electrode that functions as a gate, and a first semiconductor layer that is formed on the first electrode and overlaps with the first electrode via the first insulating layer.
The capacitive element has a first electrode and a second semiconductor layer formed below the first electrode and superposed on the first electrode via a second insulating layer. Semiconductor device. The first semiconductor layer contains an oxide semiconductor material and contains an oxide semiconductor material.
The semiconductor device according to claim 1, wherein the second semiconductor layer contains polycrystalline silicon. The semiconductor device according to claim 1 , wherein the second semiconductor layer is electrically connected to the drain of the first transistor.

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