JP7057400B2 - Semiconductor device - Google Patents

Description

The present invention relates to a technique for miniaturizing a semiconductor integrated circuit. Some of the inventions disclosed herein include
Elements constituting a semiconductor integrated circuit include an element composed of a compound semiconductor in addition to a silicon semiconductor, and as an example thereof, the present invention relates to a semiconductor device to which an oxide semiconductor is applied and a method for manufacturing the same.

In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

In recent years, the development of semiconductor devices has been promoted, and they are used as LSIs, CPUs, and memories.
A CPU is an aggregate of semiconductor elements having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes as connection terminals formed therein.

Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, for example, printed wiring boards, and are used as one of various electronic device components.

Silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors used in semiconductor circuits. For example, Patent Document 1 proposes a structure in which the distance between the channel forming region and the contact portion is shortened and the resistance generated between them is reduced in order to achieve high integration.

In addition, oxide semiconductors are attracting attention as other materials other than silicon. for example,
Patent Documents 2 and 3 disclose techniques for manufacturing a transistor using zinc oxide and an In—Ga—Zn-based oxide as an oxide semiconductor and using it as a switching element for pixels of a display device.

Japanese Unexamined Patent Publication No. 2004-327617 Japanese Unexamined Patent Publication No. 2007-123861 Japanese Unexamined Patent Publication No. 2007-96055

One of the challenges is to realize fine transistors by shortening the channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories, to increase the operating speed of circuits, and to reduce power consumption. And.

In one aspect of the present invention, it is an object of the present invention to provide a transistor including an oxide semiconductor and capable of high-speed operation and a method for manufacturing the same. Another object of the present invention is to provide a highly reliable semiconductor device including the transistor and a method for manufacturing the same.

By removing impurities that become electron donors in the oxide semiconductor, a channel formation region is formed in the oxide semiconductor, which is a true or substantially genuine semiconductor and has a larger energy gap than the silicon semiconductor. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured by using a transistor.

Contact resistance is generated between the oxide semiconductor and the conductive layer. In order to reduce the contact resistance, it is necessary to secure a sufficient contact area.

Therefore, the contact resistance is reduced by providing a conductive layer in contact with the upper surface of the oxide semiconductor layer and a conductive layer in contact with the lower surface of the oxide semiconductor layer to secure a sufficient contact area.

One aspect of the present invention disclosed herein is a semiconductor substrate, an insulating layer on the semiconductor substrate, an oxide semiconductor layer on the insulating layer, a gate insulating layer on the oxide semiconductor layer, and a gate insulating layer. The gate electrode layer overlaps with the oxide semiconductor layer, the sidewall has a sidewall on the side surface of the gate electrode layer, the insulating layer has a groove having a deep region and a shallow region, and the groove has a conductive region. Is a semiconductor device characterized by overlapping with a shallow region.

One of the features of the above configuration is that the conductive layer is in contact with the sidewall and the oxide semiconductor layer.

Further, in the above configuration, the gate electrode layer is further provided with an interlayer insulating layer and wiring is provided on the interlayer insulating layer, and the wiring overlaps with the conductive type region and is electrically connected to a deep region. It is one.

Further, in the above configuration, one of the features of the conductive type region is that it has a shallow region having a first width in the channel length direction and a deep region having a second width in the channel length direction. Is.

Further, a so-called MCP (Multi Chip Package), in which a plurality of semiconductor integrated circuits are mounted in one package to enhance the integration of semiconductor devices, may be used.

Further, when the semiconductor integrated circuit is mounted on the circuit board, it may be in a face-up form or a flip-chip form (face-down form).

Further, the manufacturing method is also one of the present inventions, and the configuration thereof is a first flattening treatment in which a first insulating film is formed on the first electrode layer and the upper surface of the first electrode layer is exposed. A second electrode layer is formed in contact with the upper surface of the first electrode layer, a second insulating film is formed on the second electrode layer, and the upper surface of the second electrode layer is exposed. A flattening treatment is performed to form an oxide semiconductor film in contact with the upper surface of the second electrode layer, a gate insulating layer is formed on the oxide semiconductor film, and a gate electrode layer and the gate electrode layer are formed on the gate insulating layer. An insulating film covering the upper surface is formed, a sidewall is formed which overlaps with the second electrode layer and is in contact with the side surface of the gate electrode layer, covers the gate electrode layer and the sidewall, and is in contact with the oxide semiconductor film. This is a method for manufacturing a semiconductor device that performs a third flattening process for forming a conductive film and removing a part of the conductive film that overlaps with the gate electrode layer.

When shortening the channel length L of transistors used in semiconductor integrated circuits such as LSIs, CPUs, and memories, the contact resistance of the oxide semiconductor layer is reduced to increase the operating speed of the circuit and further reduce power consumption. do.

It is an example of a sectional view and a top view which show one aspect of this invention. It is a process sectional view which shows one aspect of this invention. It is a process sectional view which shows one aspect of this invention. A cross-sectional view, a plan view, and a circuit diagram showing one aspect of a semiconductor device. A circuit diagram and a perspective view showing one aspect of a semiconductor device. A plan view and a cross-sectional view showing one aspect of a semiconductor device. A circuit diagram showing one aspect of a semiconductor device. The block diagram which shows one aspect of a semiconductor device. The block diagram which shows one aspect of a semiconductor device. The block diagram which shows one aspect of a semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details thereof can be changed in various ways. Further, the present invention is not limited to the description of the embodiments shown below.

(Embodiment 1)
1 (A) and 1 (B) show a cross-sectional view and a top view of the transistor 420 as an example of a semiconductor device. 1 (A) is a cross-sectional view of the transistor 420, and FIG. 1 (A) is FIG. 1 (A).
B) is a cross-sectional view taken along the line XY. In addition, in FIG. 1B, a part of the constituent elements of the transistor 420 (for example, the insulating film 407, the insulating film 410, the interlayer insulating film 415, etc.) is omitted in order to avoid complication. ..

The transistor 420 shown in FIGS. 1A and 1B is embedded in a base insulating layer 436 and a base insulating layer 436 on a substrate 400 having an insulating surface, and at least a part of the upper surface thereof is a base. An oxide semiconductor layer 403 including an electrode layer 425a and an electrode layer 425b exposed from the insulating layer 436, a pair of low resistance regions 404a and 404b, and a channel forming region 409 sandwiched between the low resistance region 404a and the low resistance region 404b. , The gate insulating layer 402 provided on the oxide semiconductor layer 403, the gate electrode layer 401 provided on the channel forming region 409 via the gate insulating layer 402, and the side wall provided on the side surface of the gate electrode layer 401. Insulation layer 412
a, 412b, an insulating film 413 provided on the gate electrode layer 401, and a source electrode layer 40.
The insulating film 410 provided on the 5a and the drain electrode layer 405b, the interlayer insulating film 415 provided on the insulating film 410, the insulating film 407 provided on the interlayer insulating film 415, and the insulating film 4
The source electrode layer 40 is provided through the openings provided in 07, the interlayer insulating film 415, and the insulating film 410.
It includes a first wiring layer 465a and a second wiring layer 465b that are electrically connected to the 5a and the drain electrode layer 405b, respectively.

The interlayer insulating film 415 is provided so as to flatten the unevenness of the transistor 420.
The height of the upper surface is substantially the same as that of the side wall insulating layers 412a and 412b and the insulating film 410. The side wall insulating layers 412a and 412b are also referred to as sidewalls. Further, the heights of the upper surfaces of the source electrode layer 405a and the drain electrode layer 405b are such that the interlayer insulating film 415, the side wall insulating layer 412a, and 4
It is lower than the height of the upper surface of 12b and the insulating film 413, and higher than the height of the upper surface of the gate electrode layer 401. The height referred to here is the height from the upper surface of the substrate 400.

Further, in FIG. 1, the electrode layer 425a and the electrode layer 425b are formed so as to embed a groove having a deep region and a shallow region in the underlying insulating layer 436. Side wall insulation layers 412a, 412
b overlaps the shallow region. Further, the first wiring layer 465a and the second wiring layer 465b are formed at positions overlapping with the deep region.

Further, in FIG. 1, the insulating film 407 is provided in contact with the interlayer insulating film 415, the source electrode layer 405a, the drain electrode layer 405b, the side wall insulating layer 412a, 412b, the insulating film 413, and the insulating film 410.

The dopant is introduced into the oxide semiconductor film 403 in a self-aligned manner using the gate electrode layer 401 as a mask, and the resistance of the oxide semiconductor film 403 is lower than that of the channel forming region 409 sandwiching the channel forming region 409, and the resistance is lower than that of the channel forming region 409. The resistance regions 404a and 404b are formed. The dopant is an impurity that changes the conductivity of the oxide semiconductor film 403. As a method for introducing the dopant, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used.

The oxide semiconductor film 403 including the low resistance regions 404a and 404b with the channel forming region 409 sandwiched in the channel length direction and the source electrode layer 40 in contact with a part of the upper surface of the oxide semiconductor film 403.
The electrode layer 4 that partially contacts the 5a and the drain electrode layer 405b and the lower surface of the oxide semiconductor film 403.
By having the 25a and the electrode layer 425b, the transistor 420 has high on-characteristics (for example, on-current and field-effect mobility), and enables high-speed operation and high-speed response.

The oxide semiconductor used for the oxide semiconductor film 403 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. Further, it is preferable to use the oxide semiconductor and to have gallium (Ga) in addition to them as a stabilizer for reducing oxygen deficiency of the oxide semiconductor. Further, it is preferable to have tin (Sn) as the stabilizer. Also, as a stabilizer, hafnium (Hf)
) Is preferable. Further, it is preferable to have aluminum (Al) as the stabilizer. Further, it is preferable to have zirconium (Zr) as the stabilizer.

In addition, as other stabilizers, lanthanoids such as lanthanum (La) and cerium (
Ce), placeodim (Pr), neodym (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), formium (Ho), elbium (Er), thulium ( It may have one or more of Tm), ytterbium (Yb), and lutethium (Lu).

For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, which are oxides of binary metals, are used. Oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides (also referred to as IGZO), which are ternary metal oxides, In- Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides Material, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn-based oxide, In-Nd-Zn-based oxide, In-Sm-Zn-based oxide, In-Eu -Zn-based oxide, In-Gd-Zn-based oxide,
In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, I
n-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In
-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, which is a quaternary metal oxide, I
n-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-
Zn-based oxides, In—Sn—Hf—Zn-based oxides, and In—Hf-Al—Zn-based oxides can be used.

Here, for example, the In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn does not matter. Also, In and G
Metal elements other than a and Zn may be contained.

Further, as an oxide semiconductor, InMO ₃ (ZnO) _m (m> 0, and m is not an integer).
The material indicated by may be used. In addition, M represents one metal element selected from Ga, Fe, Mn and Co, or a plurality of metal elements. In addition, as an oxide semiconductor, In ₂ SnO ₅
(ZnO) A material represented by _n (n> 0 and n is an integer) may be used.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Z
n = 2: 2: 1 (= 2/5: 2/5: 1/5) or In: Ga: Zn = 3: 1: 2
An In—Ga—Zn-based oxide having an atomic number ratio of (= 1/2: 1/6: 1/3) or an oxide in the vicinity of its composition can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3 :)
1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1/2) or In: Sn: Zn = 2: 1: 5 (= 1 /) In-Sn with an atomic number ratio of 4: 1/8: 5/8)
-It is advisable to use a Zn-based oxide or an oxide in the vicinity of its composition.

However, the present invention is not limited to these, and a semiconductor having an appropriate composition may be used according to the required semiconductor characteristics (mobility, threshold value, variation, etc.). Further, in order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, the impurity concentration, the defect density, the atomic number ratio between the metal element and oxygen, the interatomic bond distance, the density and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, even with In—Ga—Zn-based oxides, the mobility can be increased by lowering the defect density in the bulk.

For example, the atomic number ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b +).
The composition of the oxide having c = 1) has an atomic number ratio of In: Ga: Zn = A: B: C (A + B + C).
= 1) When a, b, and c are in the vicinity of r in the composition of the oxide, (aA) ² + (bB)
) ² + (c-C) ² ≤ r ² is satisfied. The r may be, for example, 0.05. The same applies to other oxides.

The oxide semiconductor film 403 is in a state of single crystal, polycrystal (also referred to as polycrystal) or amorphous.

Preferably, the oxide semiconductor film is CAAC-OS (C Axis Aligned Cr).
ystalline Oxide Semiconductor) film.

Here, CAAC (C Axis Aligned Crystal) has a triangular or hexagonal atomic arrangement in which the c-axis is oriented in a direction perpendicular to the formed surface or surface of the oxide semiconductor film and is viewed from a direction perpendicular to the ab surface. A mixed phase structure of crystals and amorphous, in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers when viewed from the direction perpendicular to the c-axis. In this mixed phase structure, the directions of the a-axis and the b-axis of the CAACs may be different from each other.

CAAC oxide semiconductor (CAAC-OS: C Axis Aligned Crysta)
The line Oxide Semiconductor) membrane is neither completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure. The size of the crystal is estimated to be several nm to several tens of nm, but it is a transmission electron microscope (TE).
In the observation by M: Transmission Electron Microscope), the boundary between the amorphous substance contained in the CAAC-OS film and CAAC is not always clear.
In addition, no grain boundaries (also referred to as grain boundaries) are confirmed in the CAAC-OS film. Since the CAAC-OS film does not have grain boundaries, the electron mobility due to the grain boundaries is unlikely to decrease.

In the CAAC-OS film, the distribution of the crystal region in the film does not have to be uniform.
For example, when crystals grow from the surface side of the CAAC-OS film, the proportion of crystals may be high in the vicinity of the surface of the CAAC-OS film, and the proportion of amorphous material may be high in the vicinity of the surface to be formed. ..

Since the c-axis of the crystal portion in CAAC faces the direction perpendicular to the formed surface or surface of the CAAC-OS film, the c-axis depends on the shape of the CAAC-OS film (cross-sectional shape of the formed surface or the cross-sectional shape of the surface). May be facing different directions. The direction in which the c-axis of the crystal portion in CAAC faces is a direction substantially perpendicular to the surface to be formed or the surface when the CAAC-OS film is formed. CAAC is formed by performing a crystallization treatment such as a heat treatment at the same time as the film formation or after the film formation.

By using the CAAC-OS film, fluctuations in the electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light are reduced, so that a highly reliable transistor can be obtained.

A part of oxygen constituting the oxide semiconductor film may be replaced with nitrogen.

The film thickness of the oxide semiconductor film 403 is 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 n).
(m or less), sputtering method, MBE (Molecular Beam Epita)
xy) method, CVD method, pulsed laser deposition method, ALD (Atomic Layer Dep)
The option) method or the like can be appropriately used. Further, the oxide semiconductor film 403 is a sputtering apparatus (Columner Plasma Spu) that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface.
A film may be formed using a ttering system).

2 (A) to (E) and FIGS. 3 (A) to 3 (D) show an example of a method for manufacturing a semiconductor device having a transistor 420.

First, the electrode layers 422a and 422b are formed on the substrate 400 having an insulating surface. Electrode layer 4
Examples of 22a and 422b include a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal nitride film containing the above-mentioned element as a component (titanium nitride film, nitriding). A molybdenum film, a tungsten nitride film, etc.) can be used. Also, Al, C
A refractory metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is laminated on one or both of the lower side or the upper side of the metal film such as u. It may be configured.

There is no major limitation on the substrate that can be used for the substrate 400 having an insulating surface, but it is necessary that the substrate has at least enough heat resistance to withstand the subsequent heat treatment. For example, glass substrates such as barium borosilicate glass and aluminoborosilicate glass, ceramic substrates,
A quartz substrate, a sapphire substrate, or the like can be used. Further, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element is provided on these substrates. It may be used as a substrate 400.

Next, an insulating film 423 that covers the electrode layers 422a and 422b is formed. The state up to this point is shown in FIG. 2 (A).

The insulating film 423 is formed by a plasma CVD method, a sputtering method, or the like, using silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, gallium oxide, or a mixed material thereof.

Next, the insulating film 423 and the electrode layers 422a and 422b are cut (ground and polished). Cutting(
As a method of grinding and polishing, chemical mechanical polishing (Chemical Mechanical)
The Polishing (CMP) method can be preferably used.

Next, the electrode layers 424a and 424b are formed so as to overlap the electrode layers 422a and 422b. Examples of the electrode layers 424a and 424b include Al, Cr, Cu, Ta, Ti, and Mo.
A metal film containing an element selected from W, or a metal nitride film containing the above-mentioned elements as a component (
Titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.) can be used. Further, a refractory metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is formed on one or both of the lower side or the upper side of the metal film such as Al and Cu. May be a laminated configuration.

Next, an insulating film 426 covering the electrode layers 424a and 424b is formed. The state up to this point is shown in FIG. 2 (B). The boundary between the insulating film 423 and the insulating film 426 is shown by a dotted line, but if the same material is used, the clear boundary disappears. Therefore, the dotted line indicating the boundary is omitted in the following figures, and the insulating film 423 and the insulating film 426 are omitted. Is illustrated as the underlying insulating layer 436. In addition, the electrode layer 422a
If the same material is used for 422b and the electrode layers 424a and 424b, there is no clear boundary. Therefore, in the following figures, the dotted line indicating the boundary is omitted, and the electrode layer 422a and 422b and the electrode layer 42 are omitted.
The laminate of 4a and 424b is illustrated as an electrode layer 425a and 425b.

Next, the insulating film 426 and the electrode layers 424a and 424b are cut (ground and polished). Cutting(
The CMP method is used as the (grinding and polishing) method.

Next, the oxide semiconductor film 403 is formed on the base insulating layer 436 and the electrode layers 425a and 425b.

In the present embodiment, the target for producing the oxide semiconductor film 403 by the sputtering method is an oxide target having an composition ratio of In: Ga: Zn = 3: 1: 2 [atomic number ratio]. Is used to form an In—Ga—Zn-based oxide film (IGZO film).

As the sputtering gas used for forming the oxide semiconductor film 403, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl groups or hydrides have been removed.

The substrate is held in the film forming chamber kept under reduced pressure. Then, a sputter gas from which hydrogen and water have been removed is introduced while removing residual water in the film forming chamber, and the substrate 40 is used using the above target.
An oxide semiconductor film 403 is formed on 0. In order to remove the residual water in the film forming chamber, it is preferable to use an adsorption type vacuum pump, for example, a cryopump, an ion pump, or a titanium sublimation pump. Further, as the exhaust means, a turbo molecular pump to which a cold trap is added may be used. The film formation chamber exhausted using the cryopump is, for example,
Since hydrogen atoms, compounds containing hydrogen atoms such as water ( _H2O ) (more preferably compounds containing carbon atoms) and the like are exhausted, impurities contained in the oxide semiconductor film 403 formed in the film forming chamber are contained. The concentration of hydrogen can be reduced.

The oxide semiconductor film 403 can be formed by processing a film-shaped oxide semiconductor film into an island-shaped oxide semiconductor film by a photolithography step.

Further, a resist mask for forming the island-shaped oxide semiconductor film 403 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, the manufacturing cost can be reduced because the photomask is not used.

The oxide semiconductor film may be etched by dry etching or wet etching, or both may be used. For example, as the etching solution used for wet etching of the oxide semiconductor film, a solution in which phosphoric acid, acetic acid, and nitric acid are mixed can be used. Also, IT
O-07N (manufactured by Kanto Chemical Co., Inc.) may be used. In addition, ICP (Inductively)
Coupled Plasma: Inductively coupled plasma) Etching may be performed by dry etching by an etching method. For example, the IGZO film is etched by the ICP etching method (etching conditions: etching gas (BCl ₃ : Cl ₂ = 60 sccm:).
20 sccm), power supply power 450 W, bias power 100 W, pressure 1.9 Pa), and can be processed into an island shape.

Further, the oxide semiconductor film 403 may be heat-treated to remove (dehydrogenate or dehydrogenate) excess hydrogen (including water and hydroxyl groups). The temperature of the heat treatment is 300 ° C or higher and 700.
The temperature should be below ° C or below the strain point of the substrate. The heat treatment can be performed under reduced pressure or in a nitrogen atmosphere. For example, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor film 403 is heat-treated at 450 ° C. for 1 hour under a nitrogen atmosphere.

The heat treatment device is not limited to the electric furnace, and a device that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, GRTA (Gas R)
apid Thermal Anneal) device, LRTA (Lamp Rapid T)
RTA (Rapid Thermal Anneal) such as a hermal Anneal device
al) A device can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using a high-temperature gas. For hot gas,
A rare gas such as argon or an inert gas such as nitrogen that does not react with the object to be treated by heat treatment is used.

For example, as the heat treatment, the substrate may be placed in an inert gas heated to a high temperature of 650 ° C. to 700 ° C., heated for several minutes, and then GRTA may be performed to remove the substrate from the inert gas.

In the heat treatment, it is preferable that nitrogen, a rare gas such as helium, neon, or argon does not contain water, hydrogen, or the like. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon to be introduced into the heat treatment apparatus is 6N (99.99999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 1 ppm or less). Is 0.1
It is preferably ppm or less).

The timing of the heat treatment for dehydration or dehydrogenation may be after the formation of the film-shaped oxide semiconductor film or after the formation of the island-shaped oxide semiconductor film 403.

Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times, or may be combined with other heat treatments.

Further, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is introduced into the oxide semiconductor film 403 that has been dehydrated or dehydrogenated to supply oxygen into the film. May be good.

Further, by dehydration or dehydrogenation treatment, oxygen, which is a main component material constituting an oxide semiconductor, may be simultaneously desorbed and reduced. In the oxide semiconductor film, oxygen deficiency exists at the place where oxygen is desorbed, and the oxygen deficiency causes a donor level that causes a change in the electrical characteristics of the transistor.

By introducing oxygen into the oxide semiconductor film 403 that has been dehydrated or dehydrogenated and supplying oxygen into the film, the oxide semiconductor film 403 is highly purified and electrically type I (intrinsic). ) Can be converted. The transistor having the oxide semiconductor film 403 which has been made highly purified and electrically made type I (intrinsic) has suppressed fluctuations in electrical characteristics and is electrically stable.

As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

In the oxygen introduction step, when oxygen is introduced into the oxide semiconductor film 403, it may be introduced directly into the oxide semiconductor film 403, or it may pass through another film such as the gate insulating layer 402 to pass through the oxide semiconductor film 40.
It may be introduced to 3. When oxygen is introduced through another film, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like may be used, but when oxygen is directly introduced into the exposed oxide semiconductor film 403. Can also be used for plasma processing and the like.

The introduction of oxygen into the oxide semiconductor film 403 is preferably after dehydration or dehydrogenation treatment, but is not particularly limited. Further, the oxide semiconductor film 40 subjected to the above dehydration or dehydrogenation treatment
Oxygen may be introduced into 3 multiple times.

Next, the gate insulating layer 402 covering the oxide semiconductor film 403 is formed (see FIG. 2C).
..

The film thickness of the gate insulating layer 402 shall be 1 nm or more and 20 nm or less, and the sputtering method may be used.
A method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be appropriately used. Further, the gate insulating layer 402 may be formed by using a sputtering apparatus, a so-called CP sputtering apparatus, in which a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

As the material of the gate insulating layer 402, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon nitride film, an aluminum nitride film, or a silicon nitride film can be used. The gate insulating layer 402 is an oxide semiconductor film 40.
It is preferable that oxygen is contained in the portion in contact with 3. In particular, the gate insulating layer 402 preferably contains at least an amount of oxygen in the film (in the bulk) that exceeds the stoichiometric ratio. For example, when a silicon oxide film is used as the gate insulating layer 402, SiO is used. _{2 + α} (where α> 0). In this embodiment, a silicon oxide film having SiO _{2 + α} (where α> 0) is used as the gate insulating layer 402. This silicon oxide film is used as the gate insulating layer 40.
When used as 2, oxygen can be supplied to the oxide semiconductor film 403 and the characteristics can be improved. Further, the gate insulating layer 402 is preferably formed in consideration of the size of the transistor to be manufactured and the step covering property of the gate insulating layer 402.

Further, as the material of the gate insulating layer 402, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x Oy (x> 0, _y > 0)) and nitrogen-added hafnium silicate (HfSiO _x N _y (x> 0,) y> 0)), hafnium aluminate (HfAl _x O)
The gate leakage current can be reduced by using a high-k material such as _y (x> 0, y> 0)) and lanthanum oxide. Further, the gate insulating layer 402 may have a single-layer structure or a laminated structure.

Next, a laminate of a conductive film and an insulating film is formed on the gate insulating layer 402, and the conductive film and the insulating film are etched to form a laminate of the gate electrode layer 401 and the insulating film 413 (FIG. 2C). reference).

The material of the gate electrode layer 401 can be formed by using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium, or an alloy material containing these as a main component. Further, as the gate electrode layer 401, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The gate electrode layer 401 may have a single-layer structure or a laminated structure.

The insulating film 413 is typically an inorganic insulating film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, an aluminum nitride film, a silicon nitride film, an aluminum nitride film, a silicon nitride film, or an aluminum nitride film. Can be used. The insulating layer 413 can be formed by using a plasma CVD method, a sputtering method, or the like.

Next, the dopant 421 is introduced into the oxide semiconductor film 403 using the gate electrode layer 401 and the insulating film 413 as masks to form low resistance regions 404a and 404b (see FIG. 2D).

The dopant 421 is an impurity that changes the conductivity of the oxide semiconductor film 403. Dopant 421 includes Group 15 elements (typically phosphorus (P), arsenic (As), and antimony (Sb)), boron (B), aluminum (Al), nitrogen (N), and argon (Ar).
, Neon (Ne), Indium (In), Titanium (Ti), and Zinc (Zn) can be used.

The dopant 421 is passed through another film (for example, the gate insulating layer 402) by the injection method.
It can also be introduced into the oxide semiconductor film 403. As a method of introducing the dopant 421,
Ion implantation method, ion doping method, plasma immersion ion implantation method and the like can be used.

The introduction step of the dopant 421 may be controlled by appropriately setting the injection conditions such as the acceleration voltage and the dose amount, and the film thickness of the film to be passed. In the present embodiment, phosphorus is implanted by the ion implantation method using phosphorus as the dopant 421. The dose amount of the dopant 421 may be 1 × 10 ¹³ ions / cm ² or more and 5 × 10 ¹⁶ ions / cm ² or less.

The concentration of dopant 421 in the low resistance region is 5 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²² .
It is preferably / cm ³ or less.

When introducing the dopant 421, the substrate 400 may be heated.

The process of introducing the dopant 421 into the oxide semiconductor film 403 may be performed a plurality of times, and a plurality of types of dopants may be used.

Further, the heat treatment may be performed after the introduction treatment of the dopant 421. As the heating conditions, it is preferable to carry out the heating at a temperature of 300 ° C. or higher and 700 ° C. or lower, preferably 300 ° C. or higher and 450 ° C. or lower for 1 hour in an oxygen atmosphere. Further, the heat treatment may be performed under a nitrogen atmosphere, a reduced pressure, and an atmosphere (ultra-dry air).

In the present embodiment, phosphorus (P) ions are implanted into the oxide semiconductor film 403 by the ion implantation method. The conditions for injecting phosphorus (P) ions are an acceleration voltage of 30 kV and a dose amount of 1.0 × 1.
It is set to 0 ¹⁵ ions / cm ² .

When the oxide semiconductor film 403 is a CAAC-OS film, the introduction of the dopant 421 results in the introduction of the dopant 421.
It may be partially amorphized. In this case, the crystallinity of the oxide semiconductor film 403 can be restored by performing a heat treatment after the introduction of the dopant 421.

By the above steps, the oxide semiconductor film 403 provided with the low resistance regions 404a and 404b across the channel forming region 409 is formed.

Next, an insulating film is formed on the gate electrode layer 401 and the insulating film 413, and the insulating film is etched to form the side wall insulating layers 412a and 412b. Further, using the gate electrode layer 401 and the side wall insulating layer 412a and 412b as masks, the gate electrode layer 401 and the side wall insulating layer 412a,
The gate insulating layer other than the region overlapping with 412b is etched to form the gate insulating layer 402 (see FIG. 3A).

The side wall insulating layers 412a and 412b can be formed by using the same material and method as the insulating film 413. In this embodiment, a silicon oxynitride film formed by the CVD method is used.

Next, a source electrode layer and a drain electrode layer (wiring formed of the same layer) are placed on the oxide semiconductor film 403, the gate insulating layer 402, the gate electrode layer 401, the side wall insulating layers 412a, 412b, and the insulating film 413. Includes) to form a conductive film.

The conductive film uses a material that can withstand the subsequent heat treatment. The conductive film used for the source electrode layer and the drain electrode layer is, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, or a metal containing the above-mentioned element as a component. Nitride film (titanium nitride film,
A molybdenum nitride film, a tungsten nitride film, etc.) can be used. Further, a refractory metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is formed on one or both of the lower side or the upper side of the metal film such as Al and Cu. May be a laminated configuration.

A resist mask is formed on the conductive film by a photolithography step, and etching is selectively performed to form an island-shaped conductive film 445, and then the resist mask is removed. In the etching step, the conductive film 445 on the gate electrode layer 401 is not removed.

When a tungsten film having a thickness of 30 nm is used as the conductive film, the tungsten film is etched by, for example, a dry etching method (etching conditions: etching gas (CF ₄ : Cl ₂ : O ₂ = 55 sccm: 45 sccm: 45 sccm:). 55 sccm, power supply power 3000 W, bias power 140 W, pressure 0.67 Pa)) may be applied to form an island-shaped tungsten film.

An insulating film 410 and an insulating film 446 to be an interlayer insulating film are laminated on the island-shaped conductive film 445 (see FIG. 3B).

The insulating film 410 uses a highly dense inorganic insulating film (typically an aluminum oxide film), and may be a single layer or a laminated film, and preferably contains at least an aluminum oxide film.

The insulating film 446 can be formed by using the same material and method as the insulating film 413. The insulating film 446 is formed with a film thickness capable of flattening the unevenness caused by the transistor 420. In the present embodiment, a silicon oxynitride film formed by the CVD method is formed at 300 nm.

Next, the insulating film 446 and the conductive film 445 are polished by a chemical mechanical polishing method, and the insulating film 4 is formed.
Part of the insulating film 446, the insulating film 410, and the conductive film 445 is removed so that the 13 is exposed.

By the polishing treatment, the insulating film 446 is processed into an interlayer insulating film 415, the conductive film 445 on the gate electrode layer 401 is removed, and the source electrode layer 405a and the drain electrode layer 405b are formed.

In the present embodiment, the chemical mechanical polishing method is used for removing the insulating film 446, the insulating film 410, and the conductive film 445, but other cutting (grinding, polishing) methods may be used. Further, the gate electrode layer 4
In the step of removing the conductive film 445 on 01, in addition to a cutting (grinding, polishing) method such as a chemical mechanical polishing method, an etching (dry etching, wet etching) method, plasma treatment, or the like may be combined. For example, after the removal step by a chemical mechanical polishing method, a dry etching method or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treated surface. When the cutting (grinding, polishing) method is combined with the etching method, plasma treatment, etc., the process order is not particularly limited, and the material, film thickness, and surface of the insulating film 446, the insulating film 410, and the conductive film 445 are not particularly limited. It may be set appropriately according to the uneven state.

In the present embodiment, the source electrode layer 405a and the drain electrode layer 405b are provided so as to be in contact with the side surface of the side wall insulating layer 412a and 412b provided on the side surface of the gate electrode layer 401, and the side wall insulating layer 412a, The side surface of 412b is covered to a position slightly lower than the upper end portion. The shapes of the source electrode layer 405a and the drain electrode layer 405b differ depending on the conditions of the polishing treatment for removing the conductive film 445, and as shown in the present embodiment, the side wall insulating layers 412a and 4
12b, the insulating film 413 may have a shape recessed in the film thickness direction from the polished surface. However, depending on the polishing treatment conditions, the source electrode layer 405a and the drain electrode layer 405
In some cases, the upper end portion of b and the upper end portion of the side wall insulating layers 412a and 412b substantially coincide with each other.

Through the above steps, the transistor 420 of the present embodiment is manufactured (see FIG. 3C).

By such a manufacturing method, the distance between the region where the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 are in contact (first contact region) and the gate electrode layer 401 can be shortened. Further, the distance between the region where the electrode layers 425a and 425b and the oxide semiconductor film 403 are in contact (second contact region) and the gate electrode layer 401 can be shortened. Therefore, the resistance between the region where the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor film 403 are in contact (first contact region) and the gate electrode layer 401 is reduced, and the on-characteristics of the transistor 420 are improved. Is possible.

Further, in the step of removing the conductive film 445 on the gate electrode layer 401 in the step of forming the source electrode layer 405a and the drain electrode layer 405b, a part of the insulating film 413 or the insulating film 4
13 All may be removed. Further, a part of the upper part of the gate electrode layer 401 may be removed. The transistor structure that exposes the gate electrode layer 401 is useful in an integrated circuit in which other wiring or semiconductor elements are laminated above the transistor.

A highly dense inorganic insulating film (typically, an aluminum oxide film) as a protective insulating film may be provided on the transistor 420.

In the present embodiment, the insulating film 4 is in contact with the insulating film 413, the source electrode layer 405a, the drain electrode layer 405b, the side wall insulating layer 412a, 412b, the insulating film 410, and the interlayer insulating film 415.
Form 07 (see FIG. 3D).

The insulating film 407 may be a single layer or a laminated layer, and preferably contains at least an aluminum oxide film.

The insulating film 407 can be formed by a plasma CVD method, a sputtering method, a vapor deposition method, or the like.

In addition to the aluminum oxide film, as the insulating films 407 and 410, an inorganic insulating film such as a silicon oxide film, a silicon nitride film, an aluminum nitride film, or a gallium oxide film can be typically used. Further, a hafnium oxide film, a magnesium oxide film, a zirconium oxide film, a lanthanum oxide film, a barium oxide film, or a metal nitride film (for example, an aluminum nitride film) can also be used.

In the present embodiment, an aluminum oxide film is formed as the insulating films 407 and 410 by a sputtering method. By making the aluminum oxide film high density (film density 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 420. The film density is Rutherford backscattering method (RBS: Rutherford).
It can be measured by d Backscattering Spectrum) or an X-ray reflectivity measurement method (XRR: X-Ray Reflectivity).

The aluminum oxide film that can be used as the insulating films 407 and 410 provided on the oxide semiconductor film 403 has a high blocking effect (blocking effect) that prevents the film from passing through both impurities such as hydrogen and water and oxygen. ..

Further, in FIG. 1A, an opening reaching the source electrode layer 405a and the drain electrode layer 405b is formed in the insulating film 410, the interlayer insulating film 415, and the insulating film 407, and the wiring layer 435a is formed in the opening.
An example of forming 435b is shown. The wiring layers 435a and 435b can be connected to other transistors and elements to form various circuits.

The wiring layer 435a and the wiring layer 435b can be formed by using the same materials and methods as the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b, for example, Al.
, Cr, Cu, Ta, Ti, Mo, W, a metal film containing an element selected from, or a metal nitride film containing the above-mentioned elements as a component (titanium nitride film, molybdenum nitride film, tungsten nitride film, etc.), etc. Can be used. Further, a refractory metal film such as Ti, Mo, W or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is formed on one or both of the lower side or the upper side of the metal film such as Al and Cu. May be a laminated configuration.

(Embodiment 2)
In the present embodiment, an example of a semiconductor device using the transistor shown in the first embodiment, which can retain the stored contents even when power is not supplied and has no limit on the number of writes.
This will be described with reference to the drawings. The semiconductor device of the present embodiment is configured by applying the transistor 420 according to the first embodiment as the transistor 162.

FIG. 4 is an example of the configuration of a semiconductor device. FIG. 4 (A) shows a cross-sectional view of the semiconductor device, and FIG. 4 (B).
) Shows a plan view of the semiconductor device, and FIG. 4C shows a circuit diagram of the semiconductor device. here,
FIG. 4A corresponds to the cross section in C1-C2 and D1-D2 of FIG. 4B.

The semiconductor device shown in FIGS. 4 (A) and 4 (B) has a transistor 160 using the first semiconductor material at the lower part and a transistor 162 using the second semiconductor material at the upper part. .. The transistor 162 can have the same configuration as the transistor 420 shown in the first embodiment.

Here, it is desirable that the first semiconductor material and the second semiconductor material have different forbidden band widths. For example, the first semiconductor material is a semiconductor material other than an oxide semiconductor (such as silicon).
The second semiconductor material can be an oxide semiconductor. Transistors using materials other than oxide semiconductors are easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can hold a charge for a long time due to its characteristics.

Since the transistor 162 is a transistor containing an oxide semiconductor and has a small off-current, it is possible to retain the stored contents for a long period of time by using this transistor. That is, it is possible to use a semiconductor storage device that does not require a refresh operation or has an extremely low frequency of refresh operations, so that power consumption can be sufficiently reduced.

Although all of the above transistors are described as n-channel transistors, it goes without saying that p-channel transistors can be used. Further, since the technical essence of the disclosed invention is that an oxide semiconductor is used for the transistor 162 to hold information, the specific material of the semiconductor device such as the material used for the semiconductor device and the structure of the semiconductor device is specified. The configuration need not be limited to that shown here.

The transistor 160 in FIG. 4A has a channel forming region 116 provided on the substrate 100 containing a semiconductor material (for example, silicon, etc.), an impurity region 120 provided so as to sandwich the channel forming region 116, and an impurity region. The metal compound region 124 in contact with 120 and
It has a gate insulating layer 108 provided on the channel forming region 116 and a gate electrode layer 110 provided on the gate insulating layer 108. In the figure, the source electrode and the drain electrode may not be explicitly provided, but for convenience, such a state may be included and referred to as a transistor. Further, in this case, in order to explain the connection relationship of the transistors, the source electrode and the drain electrode may be expressed including the source region and the drain region. in short,
In the present specification, the description of the source electrode may include a source region.

An element separation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160, and an insulating layer 130 is provided so as to cover the transistor 160. In order to realize high integration, it is desirable that the transistor 160 does not have a sidewall insulating layer as shown in FIG. 4A. On the other hand, when the characteristics of the transistor 160 are emphasized, a sidewall insulating layer may be provided on the side surface of the gate electrode layer 110 to provide an impurity region 120 including regions having different impurity concentrations.

The transistor 162 shown in FIG. 4A is a transistor using an oxide semiconductor in the channel forming region. Further, the oxide semiconductor layer 144 has a low resistance region 144a and a low resistance region 14.
Includes 4b and channel formation region 144c. The low resistance region 144a is formed in contact with the conductive layer 143a, the low resistance region 144b is formed in contact with the conductive layer 143b, and the channel forming region 144c is an insulation sandwiched between the conductive layer 143a and the conductive layer 143b. It is formed in contact with the layer 154.

The transistor 162 is used as a source electrode layer and a drain electrode layer by using a step of removing the conductive film provided on the gate electrode 148, the insulating film 137, and the side wall insulating layers 136a and 136b by a chemical mechanical polishing process in the manufacturing process. It forms functional electrode layers 142a, 142b.

Therefore, the transistor 162 can shorten the distance between the region (contact region) in which the electrode layers 142a and 142b functioning as the source electrode layer or the drain electrode layer and the oxide semiconductor layer 144 are in contact with each other and the gate electrode 148. The region where the electrode layers 142a and 142b and the oxide semiconductor layer 144 are in contact (contact region) and the resistance between the gate electrodes 148 are reduced, and the on-characteristics of the transistor 162 can be improved.

An insulating film 149, an interlayer insulating film 135, and an insulating film 150 are provided on the transistor 162 in a single layer or in a laminated manner. In this embodiment, an aluminum oxide film is used as the insulating film 149 and the insulating film 150. By making the aluminum oxide film high density (film density 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistor 162.

Further, a conductive layer 153 is provided in a region overlapping the conductive layer 143a via the insulating film 149, the interlayer insulating film 135, and the insulating film 150, and the conductive layer 143a, the insulating film 149, and the interlayer insulation are provided. The capacitive element 164 is composed of the film 135, the insulating film 150, and the conductive layer 153. That is, the conductive layer 143a functions as one electrode of the capacitive element 164, and the conductive layer 153 functions as the other electrode of the capacitive element 164. If the capacitance is not required, the capacitance element 164 may not be provided. Further, the capacitive element 164 may be separately provided above the transistor 162.

An insulating film 152 is provided on the transistor 162 and the capacitive element 164. The transistor 162 and the wirings 156a and 156b for connecting the other transistors are provided on the insulating film 152. The wiring 156a includes an insulating film 149 and an interlayer insulating film 13.
5. It is electrically connected to the conductive layer 143a via an electrode formed in an opening formed in the insulating film 150, the insulating film 152, or the like. The wiring 156b includes an insulating film 149 and an interlayer insulating film 135.
, The insulating film 150, and the conductive layer 143b are electrically connected to the conductive layer 143b via electrodes formed in the openings formed in the insulating film 152 and the like.

In FIGS. 4A and 4B, the transistor 160 and the transistor 162 are
It is preferably provided so that at least a part thereof overlaps with each other, and it is preferable that at least a part thereof overlaps with the source region or drain region of the transistor 160 and a part of the oxide semiconductor layer 144. Further, the transistor 162 and the capacitive element 164 are provided so as to overlap with at least a part of the transistor 160. For example, the conductive layer 153 of the capacitive element 164 is provided so that at least a part thereof overlaps with the gate electrode layer 110 of the transistor 160. By adopting such a planar layout, it is possible to reduce the occupied area of the semiconductor device, so that high integration can be achieved.

Next, an example of the circuit configuration corresponding to FIGS. 4 (A) and 4 (B) is shown in FIG. 4 (C).

In FIG. 4C, the first wiring (1st Line) and the source electrode of the transistor 160 are electrically connected, and the second wiring (2nd Line) and the drain electrode of the transistor 160 are electrically connected. It is connected. Further, the third wiring (3rd Line) and one of the source electrode or the drain electrode of the transistor 162 are electrically connected to each other, and the fourth wiring is electrically connected.
The wiring (4th Line) and the gate electrode layer of the transistor 162 are electrically connected. Then, one of the gate electrode layer of the transistor 160 and the source electrode or the drain electrode of the transistor 162 is electrically connected to the other of the electrodes of the capacitive element 164.
The fifth wiring (5th Line) and the other of the electrodes of the capacitive element 164 are electrically connected.

In the semiconductor device shown in FIG. 4C, information can be written, held, and read as follows by taking advantage of the feature that the potential of the gate electrode layer of the transistor 160 can be held.

Writing and retaining information will be described. First, the potential of the fourth wiring is set to the transistor 1
The potential at which 62 is turned on is set, and the transistor 162 is turned on. This will result in
The potential of the third wiring is given to the gate electrode layer of the transistor 160 and the node (node FG) to which the capacitive element 164 is connected. That is, a predetermined charge is given to the node FG (writing). Here, it is assumed that one of the charges giving two different potential levels (hereinafter referred to as Low level charge and High level charge) is given. After that, the 4th
The potential of the wiring of the transistor 162 is set to the potential at which the transistor 162 is turned off.
By turning off the state, the electric charge given to the node FG is retained (retained).

Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode layer of the transistor 160 is retained for a long time.

Next, reading information will be described. When a predetermined potential (constant potential) is applied to the first wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the second wiring is applied according to the amount of electric charge held in the node FG. Takes different potentials. Generally, when the transistor 160 is an n-channel type, the node FG (which can be rephrased as the gate electrode of the transistor 160).
The apparent threshold V _{th_H} when a High level charge is given to the node F
This is because it is lower than the apparent threshold value _{Vth_L} when a Low level charge is given to G. Here, the apparent threshold voltage means the potential of the fifth wiring required to put the transistor 160 in the “on state”. Therefore, by setting the potential of the fifth wiring to the potential V ₀ between V _{th_H} and V _{th_L} , the electric charge given to the node FG can be discriminated. For example, in writing, when a high level charge is given, the transistor 160 is in the “on state” when the potential of the fifth wiring becomes V ₀ (> V _{th_H} ). When a Low level charge is given, the potential of the fifth wire is V ₀ (
Even when <V _{th_L} ) is set, the transistor 160 remains in the “off state”. Therefore, the retained information can be read out by looking at the potential of the second wiring.

When the memory cells are arranged in an array and used, it is necessary to be able to read only the information of the desired memory cells. When the information is not read out in this way, the potential at which the transistor 160 is in the “off state” regardless of the state of the gate electrode layer, that is, V _{th_H}
A smaller potential may be applied to the fifth wire. Alternatively, a potential that causes the transistor 160 to be “on” regardless of the state of the gate electrode layer, that is, a potential larger than _{Vth_L} may be applied to the fifth wiring.

In the semiconductor device shown in the present embodiment, it is possible to retain the stored contents for an extremely long period of time by applying a transistor using an oxide semiconductor and having an extremely small off-current to the channel forming region. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Further, even when there is no power supply (however, it is desirable that the potential is fixed), it is possible to retain the stored contents for a long period of time.

Further, the semiconductor device shown in the present embodiment does not require a high voltage for writing information, and there is no problem of deterioration of the element. For example, unlike conventional non-volatile memory, there is no need to inject electrons into the floating gate or withdraw electrons from the floating gate.
There is no problem such as deterioration of the gate insulating layer. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in the conventional non-volatile memory, and the reliability is dramatically improved. Further, since information is written depending on whether the transistor is on or off, high-speed operation can be easily realized.

Further, in the transistor 162, the low resistance region 144a of the oxide semiconductor layer is in contact with the conductive layer 143a embedded in the underlying insulating layer and the electrode layer 142a to be electrically connected to each other.
The contact resistance can be reduced, and a transistor having excellent electrical characteristics (for example, having high on-current characteristics) can be obtained. Therefore, by applying the transistor 162, it is possible to achieve high performance of the semiconductor device. In addition, the transistor 162
Since is a highly reliable transistor, it is possible to improve the reliability of the semiconductor device.

As described above, the configurations and methods shown in the present embodiment can be appropriately combined with the configurations and methods shown in other embodiments.

(Embodiment 3)
In the second embodiment, the semiconductor device using the transistor shown in the first embodiment, which can retain the stored contents even when power is not supplied and has no limit on the number of writes, is described in the second embodiment. A configuration different from the shown configuration will be described with reference to FIGS. 5 and 6. The semiconductor device of the present embodiment is configured by applying the transistor according to the first embodiment as the transistor 162. As the transistor 162, any structure of the transistor shown in the first embodiment can be applied.

FIG. 5A is a conceptual diagram showing an example of a circuit configuration of a semiconductor device, and FIG. 5B is a conceptual diagram showing an example of a semiconductor device. First, the semiconductor device shown in FIG. 5A will be described, and then FIG. 5 (A) will be described.
The semiconductor device shown in B) will be described below.

In the semiconductor device shown in FIG. 5A, the bit wire BL and the source electrode or drain electrode of the transistor 162 are electrically connected, and the word wire WL and the gate electrode layer of the transistor 162 are electrically connected to each other. The source electrode or drain electrode of 162 and the first terminal of the capacitive element 254 are electrically connected.

The transistor 162 using an oxide semiconductor has a feature that the off-current is extremely small. Therefore, by turning off the transistor 162, the first capacitive element 254 is set.
It is possible to hold the potential of the terminal (or the electric charge stored in the capacitive element 254) for an extremely long time.

Next, a case where information is written and held in the semiconductor device (memory cell 250) shown in FIG. 5A will be described.

First, the potential of the word line WL is set to the potential at which the transistor 162 is turned on, and the transistor 162 is turned on. As a result, the potential of the bit line BL is applied to the first terminal of the capacitive element 254 (writing). After that, the potential of the word line WL is applied to the transistor 1.
By turning off the transistor 162 as the potential for turning off 62, the potential of the first terminal of the capacitive element 254 is held (held).

Since the off-current of the transistor 162 is extremely small, the potential (or the electric charge stored in the capacitive element) of the first terminal of the capacitive element 254 can be held for a long time.

Next, reading information will be described. When the transistor 162 is turned on, the floating bit wire BL and the capacitive element 254 are conducted, and the charge is redistributed between the bit wire BL and the capacitive element 254. As a result, the potential of the bit line BL changes. The amount of change in the potential of the bit line BL takes a different value depending on the potential of the first terminal of the capacitive element 254 (or the electric charge accumulated in the capacitive element 254).

For example, the potential of the first terminal of the capacitive element 254 is V, the capacitance of the capacitive element 254 is C, the capacitive component of the bit line BL (hereinafter, also referred to as bit wire capacitance) is CB, and before the charge is redistributed. Assuming that the potential of the bit line BL is VB0, the potential of the bit line BL after the charge is redistributed is
It becomes (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of the first terminal of the capacitive element 254 takes two states of V1 and V0 (V1> V0) as the state of the memory cell 250, the potential of the bit line BL when the potential V1 is held. (= CB x VB0 + C x V1)
/ (CB + C) is the potential of the bit line BL when the potential V0 is held (= CB × VB0).
It can be seen that it is higher than + C × V0) / (CB + C)).

Then, the information can be read out by comparing the potential of the bit line BL with a predetermined potential.

As described above, the semiconductor device shown in FIG. 5A has a feature that the off-current of the transistor 162 is extremely small, so that the electric charge accumulated in the capacitive element 254 can be retained for a long time. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Moreover, even when there is no power supply, it is possible to retain the stored contents for a long period of time.

Next, the semiconductor device shown in FIG. 5B will be described.

The semiconductor device shown in FIG. 5 (B) has a memory cell 2 shown in FIG. 5 (A) as a storage circuit at the top.
It has a memory cell array 251a and a memory cell array 251b having a plurality of 50, and has a peripheral circuit 253 necessary for operating the memory cell array 251a and the memory cell array 251b at the lower part. The peripheral circuit 253 is electrically connected to the memory cell array 251a and the memory cell array 251b.

By adopting the configuration shown in FIG. 5 (B), the peripheral circuit 253 is connected to the memory cell array 251a.
And since it can be provided directly under the memory cell array 251b, the semiconductor device can be miniaturized.

It is more preferable that the transistor provided in the peripheral circuit 253 uses a semiconductor material different from that of the transistor 162. For example, silicon, germanium, silicon germanium,
Silicon carbide, gallium arsenide, or the like can be used, and it is preferable to use a single crystal semiconductor. Alternatively, an organic semiconductor material or the like may be used. Transistors using such semiconductor materials are capable of sufficiently high-speed operation. Therefore, it is possible to suitably realize various circuits (logic circuit, drive circuit, etc.) that require high-speed operation by the transistor.

In the semiconductor device shown in FIG. 5B, a configuration in which two memory cell arrays, a memory cell array 251a and a memory cell array 251b, are stacked is exemplified, but the number of stacked memory cell array is not limited to this. A configuration in which three or more memory cell arrays are stacked may be used.

Next, a specific configuration of the memory cell 250 shown in FIG. 5A will be described with reference to FIG.

FIG. 6 is an example of the configuration of the memory cell 250. 6 (A) shows a plan view of the memory cell 250, and FIG. 6 (B) shows a cross-sectional view of the line segment AB of FIG. 6 (A).

The transistor 162 shown in FIGS. 6A and 6B can have the same configuration as that shown in the first embodiment.

As shown in FIG. 6B, a transistor 162 is provided on the electrode 502 and the electrode 504. The electrode 502 is a wiring that functions as the bit line BL in FIG. 6A, and is provided in contact with the low resistance region of the transistor 162. Further, the electrode 504 is shown in FIG. 6 (A).
), It functions as one electrode of the capacitive element 254 and is provided in contact with the low resistance region of the transistor 162. On the transistor 162, the electrode 506 provided in the region overlapping with the electrode 504 functions as the other electrode of the capacitive element 254.

Further, as shown in FIG. 6A, the other electrode 506 of the capacitance element 254 is electrically connected to the capacitance line 508. The gate electrode 148 provided on the oxide semiconductor layer 144 via the gate insulating layer 146 is electrically connected to the word wire 509.

Further, FIG. 6C shows a cross-sectional view of the connection portion between the memory cell array and the peripheral circuit.
Peripheral circuits include, for example, an n-channel transistor 510 and a p-channel transistor 51.
It can be configured to include 2. As the semiconductor material used for the n-channel transistor 510 and the p-channel transistor 512, it is preferable to use a semiconductor material (silicon or the like) other than the oxide semiconductor. By using such a material, high-speed operation of the transistor included in the peripheral circuit can be achieved.

By adopting the planar layout shown in FIG. 6A, the occupied area of the semiconductor device can be reduced, so that high integration can be achieved.

As described above, the plurality of memory cells formed in multiple layers on the upper surface are formed by transistors using oxide semiconductors. Since a transistor using a highly purified and purified oxide semiconductor has a small off-current, it is possible to retain the stored contents for a long period of time by using the transistor. That is, since the frequency of the refresh operation can be extremely reduced, the power consumption can be sufficiently reduced. Further, the capacitive element 254 is shown in FIG. 6 (
As shown in B), the electrode 504, the oxide semiconductor layer 144, the gate insulating layer 146, and the electrode 506.
Are formed by stacking.

In this way, peripheral circuits using transistors using materials other than oxide semiconductors (in other words, transistors capable of sufficiently high-speed operation) and transistors using oxide semiconductors (in a broader sense, sufficiently off). By integrally providing a storage circuit using a transistor (transistor with a small current), it is possible to realize a semiconductor device having unprecedented characteristics. Further, by forming the peripheral circuit and the storage circuit in a laminated structure, it is possible to integrate the semiconductor device.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example in which the semiconductor device shown in the previous embodiment is applied to a mobile device such as a mobile phone, a smartphone, or an electronic book will be described with reference to FIGS. 7 to 10.

In mobile devices such as mobile phones, smartphones, and electronic books, SRAM or DRAM is used for temporary storage of image data. The reason why SRAM or DRAM is used is that flash memory has a slow response and is not suitable for image processing.
On the other hand, when SRAM or DRAM is used for temporary storage of image data, it has the following features.

In a normal SRAM, as shown in FIG. 7A, one memory cell is a transistor 801 to 8
It is composed of six transistors of 06, which are driven by an X decoder 807 and a Y decoder 808. Transistor 803, transistor 805, transistor 80
4 and the transistor 806 form an inverter and enable high-speed driving. However, since one memory cell is composed of 6 transistors, there is a drawback that the cell area is large. When the minimum dimension of the design rule is F, the memory cell area of SRAM is usually 100.
~ 150F ² . Therefore, SRAM has the highest unit price per bit among various types of memory.

On the other hand, in the DRAM, the memory cell is composed of the transistor 811 and the holding capacity 812 as shown in FIG. 7B, and the memory cell is driven by the X decoder 813 and the Y decoder 814. One cell has one transistor and one capacitance, and the area is small. D
The memory cell area of the RAM is usually 10F ² or less. However, DRAM always needs to be refreshed and consumes power even if it is not rewritten.

However, the memory cell area of the semiconductor device described in the previous embodiment is around 10F ² , and frequent refreshing is unnecessary. Therefore, the memory cell area can be reduced and the power consumption can be reduced.

FIG. 8 shows a block diagram of a mobile device. The portable device shown in FIG. 8 is an RF circuit 901, an analog baseband circuit 902, a digital baseband circuit 903, a battery 904, a power supply circuit 905, an application processor 906, a flash memory 910, a display controller 911, a memory circuit 912, a display 913, and a touch. It is composed of a sensor 919, a voice circuit 917, a keyboard 918, and the like. Display 913 is a display unit 9
It is composed of 14, a source driver 915, and a gate driver 916. The application processor 906 has a CPU 907, a DSP 908, and an interface (IF) 9.
Has 09. Generally, the memory circuit 912 is composed of SRAM or DRAM, and by adopting the semiconductor device described in the previous embodiment for this portion, information can be written and read at high speed and can be stored for a long period of time. Moreover, the power consumption can be sufficiently reduced.

FIG. 9 shows an example in which the semiconductor device described in the previous embodiment is used for the memory circuit 950 of the display. The memory circuit 950 shown in FIG. 9 includes a memory 952, a memory 953, a switch 954, a switch 955, and a memory controller 951. Further, the memory circuit includes a signal line from image data (input image data), a memory 952, and a memory 9.
A display controller 956 that reads and controls data (stored image data) stored in 53 and a display 957 that displays by a signal from the display controller 956 are connected.

First, certain image data is formed by an application processor (not shown) (input image data A). The input image data A is stored in the memory 952 via the switch 954. Then, the image data (stored image data A) stored in the memory 952 is sent to the display 957 via the switch 955 and the display controller 956 and displayed.

When there is no change in the input image data A, the stored image data A is usually read from the memory 952 via the switch 955 from the display controller 956 at a cycle of about 30 to 60 Hz.

Next, for example, when the user rewrites the screen (that is, the input image data A).
If there is a change in), the application processor forms new image data (input image data B). The input image data B is stored in the memory 953 via the switch 954. During this period, the stored image data A is periodically read from the memory 952 via the switch 955. When new image data (stored image data B) is stored in the memory 953,
The stored image data B is read from the next frame of the display 957, and the switch 95 is read.
The stored image data B is sent to the display 957 via the display controller 956 and the display controller 956 to display the stored image data B. This reading is further continued until the next new image data is stored in the memory 952.

In this way, the memory 952 and the memory 953 display the display 957 by alternately writing the image data and reading the image data. Memory 9
The 52 and the memory 953 are not limited to different memories, and one memory may be divided and used. By adopting the semiconductor device described in the previous embodiment for the memory 952 and the memory 953, it is possible to write and read information at high speed, to hold the memory for a long period of time, and to sufficiently reduce the power consumption. can.

FIG. 10 shows a block diagram of an electronic book. FIG. 10 shows the battery 1001 and the power supply circuit 1002.
, Microprocessor 1003, flash memory 1004, audio circuit 1005, keyboard 1006, memory circuit 1007, touch panel 1008, display 1009, display controller 1010.

Here, the semiconductor device described in the previous embodiment can be used for the memory circuit 1007 of FIG. The memory circuit 1007 has a function of temporarily holding the contents of a book. For example, when a user is reading an e-book and wants to mark a specific part (change the color of the display, underline, thicken the text, change the typeface of the text, etc.), the user specifies it. It has a function to temporarily store and retain the information of the location. If this information is to be stored for a long period of time, it may be copied to the flash memory 1004. Even in such a case, by adopting the semiconductor device described in the previous embodiment, information can be written and read at high speed, storage can be retained for a long period of time, and power consumption can be sufficiently reduced. Can be done.

As described above, the mobile device shown in the present embodiment is equipped with the semiconductor device according to the previous embodiment. Therefore, a portable device that can be read at high speed, can be stored for a long period of time, and has reduced power consumption is realized.

The configuration, method, etc. shown in this embodiment can be used in appropriate combination with the configuration, method, etc. shown in other embodiments.

100 Substrate 106 Element separation insulating layer 108 Gate insulating layer 110 Gate electrode layer 116 Channel forming region 120 Impure region 124 Metal compound region 130 Insulating layer 135 Interlayer insulating film 136a Side wall insulating layer 136b Side wall insulating layer 137 Insulating film 142a Electrode layer 142b Electrode layer 143a Conductive layer 143b Conductive layer 144 Oxide semiconductor layer 144a Low resistance region 144b Low resistance region 144c Channel formation region 146 Gate insulating layer 148 Gate electrode 149 Insulating film 150 Insulating film 152 Insulating film 153 Conductive layer 154 Insulating layer 156a Wiring 156b Wiring 160 Transistor 162 Transistor 164 Capacitive element 250 Memory cell 251a Memory cell array 251b Memory cell array 253 Peripheral circuit 254 Capacitive element 400 Substrate 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor film 404a Low resistance region 404b Low resistance region 405 Electrode layer 405a Electrode layer 405b Electrode layer 407 Insulation film 409 Channel formation region 410 Insulation film 412a Side wall insulating layer 412b Side wall insulating layer 413 Insulating film 415 Interlayer insulating film 420 Transistor 421 Dopant 422a Electrode layer 422b Electrode layer 423 Insulation film 424a Electrode layer 424b Electrode layer 425a Electrode layer 425b Electrode layer 426 Insulation film 436 Underlayer insulating layer 445 Conductive 446 Insulation film 502 Electrode 504 Electrode 506 Electrode 508 Capacitance line 509 Word line 510 n-channel transistor 512 p-channel transistor 801 Trans-803 Transistor 804 Transistor 805 Transistor 807 Transistor 807 X Decoder 808 Y Decoder 811 Transistor 812 Retention Capacity 813 X Decoder 814 Y Decoder 901 RF Circuit 902 Analog Baseband Circuit 903 Digital Baseband Circuit 904 Battery 905 Power Circuit 906 Application Processor 907 CPU
908 DSP
910 Flash memory 911 Display controller 912 Memory circuit 913 Display 914 Display unit 915 Source driver 916 Gate driver 917 Voice circuit 918 Keyboard 919 Touch sensor 950 Memory circuit 951 Memory controller 952 Memory 953 Memory 954 Switch 955 Switch 956 Display controller 957 Display 1001 Battery 1002 Power circuit 1003 Microprocessor 1004 Flash memory 1005 Voice circuit 1006 Keyboard 1007 Memory circuit 1008 Touch panel 1009 Display 1010 Display controller

Claims (3)

The first transistor having silicon in the channel formation region,
A semiconductor device having an oxide semiconductor in a channel forming region and having a second transistor arranged on an upper layer of the first transistor.
The first conductive layer is arranged below the semiconductor layer of the second transistor.
The first conductive layer is arranged above the channel forming region of the first transistor.
A second conductive layer having a function as a gate of the second transistor is arranged above the semiconductor layer.
Above the semiconductor layer, a third conductive layer and a fourth conductive layer having a function as a source or drain of the second transistor are arranged.
In a plan view, the first conductive layer has a shorter distance in the channel length direction from the second conductive layer than the third conductive layer.
In a plan view, the third conductive layer and the fourth conductive layer are semiconductor devices that do not overlap with the second conductive layer. The first transistor having silicon in the channel formation region,
A semiconductor device having an oxide semiconductor in a channel forming region and having a second transistor arranged on an upper layer of the first transistor.
The first conductive layer is arranged below the semiconductor layer of the second transistor.
The first conductive layer is arranged above the channel forming region of the first transistor.
A second conductive layer having a function as a gate of the second transistor is arranged above the semiconductor layer.
Above the semiconductor layer, a third conductive layer and a fourth conductive layer having a function as a source or drain of the second transistor are arranged.
In a plan view, the first conductive layer has a shorter distance in the channel length direction from the second conductive layer than the third conductive layer.
In a plan view, the third conductive layer and the fourth conductive layer do not overlap with the second conductive layer.
In a plan view, the channel forming region of the first transistor is a semiconductor device that does not overlap with the semiconductor layer. In claim 1 or 2,
The oxide semiconductor is a semiconductor device containing In, Ga, and Zn.

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