JP7055799B2 - Display system - Google Patents

Description

One embodiment of the present invention relates to a display system. In particular, the present invention relates to a display system used for electronic devices such as mobile information terminals that require low power consumption.

It should be noted that one embodiment of the present invention is not limited to the above technical fields. The technical field of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one embodiment of the invention relates to a process, machine, manufacture, or composition (composition of matter).

Display devices that use liquid crystals, organic EL (Electroluminescence), etc. as display elements are widely used. Display devices are incorporated and used in various electronic devices, but when used in electronic devices such as mobile information terminals whose main power supply source is a battery, low power consumption is strongly required.

As one of the techniques for reducing the power consumption of the display device, idling stop drive (hereinafter referred to as IDS drive) has been proposed. In the IDS drive, a transistor having a small off-current is applied to the transistor that drives the display element, and when it is not necessary to rewrite the display image (for example, when displaying a still image), the display image is not temporarily rewritten. It is a technology.

Patent Document 1 and Patent Document 2 disclose a method of applying an IDS drive by applying a transistor having an oxide semiconductor (Oxide Semiconductor) to a channel forming region (hereinafter referred to as an OS transistor) as a transistor having a small off-current. ing.

Further, an example in which an OS transistor is applied to a non-volatile storage device by utilizing the small off-current is disclosed (Patent Document 3).

Japanese Unexamined Patent Publication No. 2011-141522 Japanese Unexamined Patent Publication No. 2011-141524 Japanese Unexamined Patent Publication No. 2011-151383

The display device is composed of a plurality of components such as a pixel array, a display unit having a gate driver and a source driver for driving the pixel array, and a controller IC for supplying image data, control signals, and the like to the display unit. In addition, display devices used in electronic devices such as personal digital assistants often have a touch sensor unit.

Here, the above-mentioned IDS drive is a technique for stopping the operation of the gate driver and the source driver and temporarily not performing the rewriting operation of the pixel array. Since it is not necessary to supply image data, control signals, etc. from the controller IC during the IDS drive period, the power supply to some circuits of the controller IC is cut off (hereinafter referred to as power gating) and displayed. There was room to reduce the power consumption of the device.

Further, depending on the type of image displayed by the display device, the frequency of rewriting the displayed image can be reduced. The frequency of rewriting the display image means the number of times of rewriting per second, and is hereinafter referred to as a frame frequency. For example, in contrast to games and TV broadcasts that require a high frame frequency, text creation represented by e-mail does not require a high frame frequency. Depending on the type of image displayed by the display device, there was room for reducing the power consumption of the display device by lowering the frame frequency.

Further, when power gating of a controller IC is performed, in some circuits of the controller IC, data is stored in a non-volatile register in which data is not lost even when the power supply is cut off, before the power supply is cut off. It is necessary to save) (hereinafter referred to as "preparation for power gating"). If power gating preparations are made after the display image does not need to be rewritten, the time during which power gating can be performed will be shortened. Therefore, the timing of power gating preparations is predicted using a neural network. be able to. By appropriately changing the parameters (also called weighting factors) of the neural network according to the type of image displayed by the display device, the time during which power gating can be performed can be as long as possible and the power consumption of the display device can be reduced. There was room.

One of the issues is to reduce power consumption in a display system in which an application processor (also referred to as a host) for classifying the types of images displayed by the display device is added to the display device. Another issue is to provide a display system capable of lowering the frame frequency within a range that does not affect the display quality. Another issue is to provide a display system that does not affect the display quality even if the power supply of some circuits is cut off.

One of the problems of one embodiment of the present invention is to provide a novel display system. Another issue is to provide a new display system with low power consumption. Alternatively, one of the objects of the present invention is to provide an electronic device having a new display system. Alternatively, one of the issues is to provide an electronic device having a new display system with low power consumption.

It should be noted that one embodiment of the present invention does not necessarily have to solve all of the above problems, but may solve at least one problem. Moreover, the description of the above-mentioned problem does not prevent the existence of other problems. Issues other than these are self-evident from the description of the description, claims, drawings, etc., and it is possible to extract issues other than these from the description of the specification, claims, drawings, etc. It is possible.

One embodiment of the present invention is a display system including an application processor and a display device. The display device includes a controller, a display unit, and a touch sensor unit. The application processor outputs image data and control signals to the controller, and the controller outputs the touch information detected by the touch sensor unit to the application processor. Is output. The application processor generates a first signal indicating the frame frequency of the display unit from the image data and the touch information, and the first signal is one of the control signals.

Further, in the above embodiment, the display unit has a gate driver and a source driver, and the application processor temporarily stops the operation of either or both of the gate driver and the source driver from the image data and the touch information. The second signal is generated, and the second signal is one of the control signals.

Further, in the above embodiment, the controller has a frame memory, an image processing unit, and a register, the frame memory has a function of storing image data, and the image processing unit has a function of processing image data. The register has a function of storing parameters for the image processing unit to perform processing. The frame memory has a function of holding image data when the power supply to the frame memory is cut off, and the register has a function of holding parameters when the power supply to the register is cut off. Have. The application processor generates a third signal from the image data and touch information that temporarily cuts off the power supply to the frame memory, the image processing unit, and the register, and the third signal is one of the control signals. It is characterized by that.

Further, in the above embodiment, the register has a volatile register and a holding circuit, the holding circuit has a function of storing the data of the volatile register, and the volatile register stores the data stored in the holding circuit. It has a function to read. The holding circuit has a function of holding the stored data in a state where the power supply to the register is cut off, and the application processor stores the data of the volatile register from the image data and the touch information. A fourth signal indicating timing is generated, and the fourth signal is one of the control signals.

Further, in the above embodiment, the fourth signal is output at the timing when the application processor outputs the image data to the controller.

Further, in the above embodiment, the application processor has a neural network.

Further, in the above embodiment, the application processor has a function of changing the parameters of the neural network from the image data and the touch information.

Further, in the above embodiment, the neural network has a product-sum calculation circuit using an analog memory.

Further, in the above embodiment, the transistor constituting the analog memory contains a metal oxide in the channel forming region.

Further, in the above embodiment, the display unit has a transistor containing a metal oxide in the channel forming region.

Further, in the above embodiment, the controller has a transistor containing a metal oxide in the channel forming region.

Further, one embodiment of the present invention is an electronic device including an application processor and a display device. The display device includes a controller and a display unit, and the application processor outputs image data and control signals to the controller. The application processor has a function of classifying the applications operating in the electronic device, and the application processor generates a first signal indicating the frame frequency of the display unit from the result of classifying the applications, and the first signal is the first signal. , It is one of the control signals.

Further, in the above embodiment, the display unit has a gate driver and a source driver. The application processor generates a second signal from the result of classifying the application to temporarily stop the operation of one or both of the gate driver and the source driver, and the second signal is one of the control signals. It is characterized by being.

Further, in the above embodiment, the controller has a frame memory, an image processing unit, and a register, the frame memory has a function of storing image data, and the image processing unit has a function of processing image data. The register has a function of storing parameters for the image processing unit to perform processing. The frame memory has a function of holding image data when the power supply to the frame memory is cut off, and the register has a function of holding parameters when the power supply to the register is cut off. Have. From the result of classifying the application, the application processor generates a third signal that temporarily cuts off the power supply to the frame memory, the image processing unit, and the register, and the third signal is one of the control signals. It is characterized by that.

Further, in the above embodiment, the register has a volatile register and a holding circuit, the holding circuit has a function of storing the data of the volatile register, and the volatile register stores the data stored in the holding circuit. It has a function to read. The holding circuit has a function of holding the stored data while the power supply to the register is cut off, and the application processor stores the data of the volatile register from the result of classifying the application. A fourth signal indicating timing is generated, and the fourth signal is one of the control signals.

Further, in the above embodiment, the fourth signal is output at the timing when the application processor outputs the image data to the controller.

Further, in the above embodiment, the application processor has a neural network.

Further, in the above embodiment, the application processor has a function of changing the parameters of the neural network from the result of classifying the applications.

Further, in the above embodiment, the neural network has a product-sum calculation circuit using an analog memory.

Further, in the above embodiment, the transistor constituting the analog memory contains a metal oxide in the channel forming region.

Further, in the above embodiment, the display unit has a transistor containing a metal oxide in the channel forming region.

Further, in the above embodiment, the controller has a transistor containing a metal oxide in the channel forming region.

The display system has an application processor and a display device, and when the type of image displayed by the display device does not require a high frame frequency, the power consumption can be reduced by lowering the frame frequency.

Further, the display device has a controller IC and a display unit, and when it is not necessary to rewrite the image displayed by the display device, the IDS drive of the display unit and the power gating of the controller IC can be performed to reduce the power consumption. ..

Further, by predicting the timing of preparing for power gating by using a neural network, it is possible to prolong the time during which power gating can be performed and reduce the power consumption of the display device. The parameters of the neural network are appropriately changed depending on the type of image displayed by the display device, and the time during which power gating can be performed can be made as long as possible.

One embodiment of the present invention can provide a novel display system. Alternatively, it is possible to provide a new display system with low power consumption. Alternatively, one embodiment of the present invention can provide an electronic device having a novel display system. Alternatively, it is possible to provide an electronic device having a novel display system with low power consumption.

The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. Other effects are those not mentioned in this section, which are described below. Effects not mentioned in this item can be derived from the description in the specification, drawings, etc. by those skilled in the art, and can be appropriately extracted from these descriptions. It should be noted that one embodiment of the present invention has at least one of the above-listed effects and other effects. Therefore, in some cases, one embodiment of the present invention may not have the effects listed above.

A block diagram showing a configuration example of a display system. The figure which shows the configuration example of a touch sensor unit. The block diagram which shows the configuration example of a controller IC. The figure explaining the parameter. The figure which shows the configuration example of a frame memory. A block diagram showing an example of register configuration. A circuit diagram showing an example of register configuration. Top view showing a configuration example of a display unit. Sectional drawing which shows the structural example of a display unit. Sectional drawing which shows the structural example of a display unit. Sectional drawing which shows the structural example of a display unit. Sectional drawing which shows the structural example of a display unit. Sectional drawing which shows the structural example of a display unit. (A) A block diagram showing a configuration example of a display unit, (B) a circuit diagram showing a configuration example of a pixel circuit, and (C) a circuit diagram showing a configuration example of a pixel circuit. A block diagram showing a configuration example of a display unit. The figure which shows the configuration example of a hierarchical neural network and the circuit configuration used for arithmetic processing. A schematic diagram of the error back propagation method and a diagram showing a circuit configuration used for arithmetic processing. The figure which shows the structural example of the product-sum operation processing circuit. The figure which shows the structure of the storage circuit and the reference storage circuit. The figure which shows the circuit structure and connection relation of a memory cell. The figure which shows the structure of the circuit 13, the circuit 14, and the current source circuit. Timing chart. The figure explaining the structure of the electronic device. The figure explaining the structure of the electronic device. The figure explaining the structure of the electronic device.

Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiments can be implemented in many different embodiments, and the embodiments and details can be variously changed without departing from the spirit and scope thereof. To. Therefore, the present invention is not construed as being limited to the description of the following embodiments. In addition, the plurality of embodiments shown below can be appropriately combined.

In the drawings attached to this specification, the components are classified by function and the block diagram is shown as blocks independent of each other. However, it is difficult to completely separate the actual components by function, and one component is used. A component may be involved in multiple functions.

Further, in drawings and the like, the size, layer thickness, region and the like may be exaggerated for clarification. Therefore, it is not necessarily limited to that scale. The drawings schematically show an ideal example and are not limited to the shapes or values shown in the drawings.

Further, in drawings and the like, the same elements or elements having the same function, elements of the same material, elements formed at the same time, etc. may be designated by the same reference numerals, and the repeated description thereof may be omitted. be.

Further, in the present specification and the like, the term "membrane" and the term "layer" can be interchanged with each other. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Further, in the present specification and the like, the terms indicating the arrangement such as "upper" and "lower" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, the expression "gate electrode on the gate insulating layer" does not exclude those containing other components between the gate insulating layer and the gate electrode.

Further, in the present specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Further, "vertical" means a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included.

Further, in the present specification and the like, the ordinal numbers such as "first", "second", and "third" are added to avoid confusion of the components, and are not limited numerically.

Further, in the present specification and the like, "electrically connected" includes the case where they are connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. For example, "things having some kind of electrical action" include electrodes, wirings, switching elements such as transistors, resistance elements, inductors, capacitive elements, and other elements having various functions.

Further, in the present specification and the like, the “voltage” often refers to a potential difference between a certain potential and a reference potential (for example, a ground potential). Therefore, the voltage and the potential difference can be rephrased.

Further, in the present specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. It has a channel region between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and is located between the source and the drain via the channel region. It is possible to pass an electric current through. In the present specification and the like, the channel region refers to a region in which a current mainly flows.

Further, the functions of the source and the drain may be switched when transistors having different polarities are adopted or when the direction of the current changes in the circuit operation. Therefore, in the present specification and the like, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, unless otherwise specified, the off current means a drain current when the transistor is in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, the off state means that the gate voltage Vgs with respect to the source is lower than the threshold voltage Vth in the n-channel transistor, and the gate voltage Vgs with respect to the source is the threshold voltage in the p-channel transistor. A state higher than the voltage Vth. That is, the off-current of the n-channel transistor may be the drain current when the voltage Vgs of the gate with respect to the source is lower than the threshold voltage Vth.

In the above description of the off-current, the drain may be read as the source. That is, the off current may refer to the source current when the transistor is in the off state.

Further, in the present specification and the like, it may be described as a leak current in the same meaning as an off current. Further, in the present specification and the like, the off current may refer to the current flowing between the source and the drain when the transistor is in the off state.

Further, in the present specification and the like, the metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS) and the like. For example, when a metal oxide is used for the active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when the metal oxide has at least one of an amplification action, a rectifying action, and a switching action, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. Further, in the case of describing as an OS transistor or an OS FET, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

(Embodiment 1)
In this embodiment, a display system including an application processor and a display device will be described.

<Display system>
FIG. 1 is a block diagram showing a configuration example of a display system. The display system 100 includes an application processor 90 and a display device 80. Further, the display device 80 includes a display unit 60, a touch sensor unit 70, and a controller IC 75.

The application processor 90 has a function as a processor capable of performing arithmetic processing, and can be configured to have, for example, an arithmetic circuit, a control circuit, a memory circuit, various interfaces, and the like. The processor performs various data processing and program control by interpreting and executing instructions from various programs. The program executed by the processor may be stored in a memory area of the processor, or may be stored in a storage device provided separately.

For example, a CPU (Central Processing Unit) or the like can be used for the application processor 90. The application processor 90 may use a DSP (Digital Signal Processor), a GPU (Graphics Processing Unit), or the like in combination with the CPU. The application processor 90 can also serve as an application processor for an electronic device having a display system 100.

The application processor 90 supplies image data, control signals, and the like to the controller IC 75. The controller IC 75 supplies the application processor 90 with information such as the presence / absence of a touch detected by the touch sensor unit 70 and the touch position.

Although not shown, the application processor 90 can be configured to have an artificial neural network (Artificial Neural Network: ANN, hereinafter abbreviated as a neural network). A neural network is a circuit configuration that imitates a neural network composed of neurons and synapses. An example of how to use the neural network will be described later, and an example of the configuration of the neural network will be described in the fourth embodiment.

<Display unit>
The display unit 60 includes a pixel array 61, a gate driver 62, a gate driver 63, and a source driver IC 64.

The pixel array 61 has a plurality of pixels 10, and each pixel 10 is an active element driven by using a transistor. Further, the pixel array 61 has a function of forming a display area of the display unit 60 and displaying an image. A more specific configuration example of the pixel array 61 will be described with reference to Embodiment 2 and Embodiment 3.

The gate driver 62 and the gate driver 63 (hereinafter referred to as “gate drivers 62, 63”) have a function of driving a gate line for selecting the pixel 10. Only one of the gate drivers 62 and 63 may be used. In the example of FIG. 1, the gate drivers 62 and 63 are provided on the same substrate together with the pixel array 61, but the gate drivers 62 and 63 can also be dedicated ICs.

The source driver IC 64 has a function of driving a source line that supplies a data signal of image data to the pixel 10. The number of source driver ICs 64 is determined according to the number of output terminals of the source driver IC64 and the number of pixels of the pixel array 61.

Here, the mounting method of the source driver IC64 is a COG (Chip on Glass) method, but there are no particular restrictions on the mounting method, and a COF (Chip on Flexible) method, a TAB (Tape Automated Bonding) method, or the like may be used. The same applies to the IC mounting method of the touch sensor unit 70, which will be described later.

The data signal of the image data is image data corresponding to the pixel 10 selected by the gate drivers 62 and 63, and is a signal whose potential and the like are adjusted according to the characteristics of the display element possessed by the pixel 10. Further, the display element of the pixel 10 includes one that emits light by itself, one that changes the ratio of light transmission, one that changes the ratio of light reflection, and the like, and the brightness and color are changed depending on the display element of the pixel 10. The method of expressing is different.

Examples of the display element applicable to the pixel 10 include a transmissive liquid crystal element, a reflective liquid crystal element, and the like, as well as an organic EL, a QLED (Quantum-dot Light Emitting Diode), an LED (Light Emitting Diode), and the like. Examples thereof include light emitting type display elements such as semiconductor lasers. In addition, semi-transmissive liquid crystal elements, shutter type MEMS (Micro Electro Electro Mechanical Systems) elements, optical interference type MEMS elements, microcapsules, electrophoresis, electrowetting, and electronic powder fluid (registered trademark). ) A display element using a method or the like can be mentioned.

An OS transistor can be applied as the transistor used for the pixel 10. The OS transistor has a feature that the off-current is lower than that of the Si transistor.

The OS transistor preferably has a metal oxide in the channel forming region. Further, the metal oxide applied to the OS transistor is preferably an oxide containing at least one of indium (In) and zinc (Zn).

Examples of such oxides include In—M—Zn oxide, In—M oxide, Zn—M oxide, and In—Zn oxide (element M is, for example, aluminum (Al), gallium (Ga), etc. Ittrium (Y), tin (Sn), boron (B), silicon (Si), titanium (Ti), iron (Fe), nickel (Ni), germanium (Ge), gallium (Zr), molybdenum (Mo), Lantern (La), cerium (Ce), neodymium (Nd), vanadium (V), berylium (Be), hafnium (Hf), tantalum (Ta), tungsten (W), etc.) are typical.

The OS transistor can reduce the off-current per 1 μm of channel width to about 1 yA / μm (y; Yocto, 10-24) or more and 1 zA / μm (z; ^{Zepto, 10-21 )} or less.

Further, it is preferable to use CAC (Cloud-Aligned Complex) -OS as the OS transistor. The details of the CAC-OS will be described in the sixth embodiment.

Alternatively, as the transistor used for the pixel 10, if the off-current is low, the OS transistor can not be applied. For example, a transistor using a semiconductor having a large band gap may be applied. A semiconductor having a large bandgap may refer to a semiconductor having a bandgap of 2.2 eV or more. For example, silicon carbide, gallium nitride, diamond and the like can be mentioned.

By using a transistor having a low off current for the pixel 10, the gate drivers 62 and 63 and the source driver IC 64 can be temporarily stopped when the display unit 60 does not need to rewrite the display image (described above). , IDS drive). By driving the IDS, the power consumption of the display unit 60 can be reduced.

<Touch sensor unit>
The touch sensor unit 70 shown in FIG. 1 has a sensor array 71 and a peripheral circuit 72. The peripheral circuit 72 includes a touch sensor driver (hereinafter referred to as a TS driver) 73 and a sense circuit 74. The peripheral circuit 72 can be configured with a dedicated IC.

The sensor array 71 forms a region where the touch sensor unit 70 can detect a touch, and the user of the display device 80 inputs to this region using a finger, a stylus, or the like. The sensor array 71 is arranged in an area overlapping the pixel array 61, and the display device 80 displays an image in the display area of the display unit 60 and obtains information as to which position in the display area the user points to. be able to.

FIG. 2 is a diagram showing a configuration example of the touch sensor unit 70. Here, an example in which the touch sensor unit 70 is a touch sensor unit of a projection type capacitance method (mutual capacitance method) is shown, but in addition to the projection type capacitance method, a surface type capacitance method, a resistance film method, A touch sensor unit 70 of any detection method such as an ultrasonic surface acoustic wave method, an optical method, and an electromagnetic induction method can be used.

The sensor array 71 has m (m is an integer of 1 or more) wiring DRL and n (n is an integer of 1 or more) wiring SNL. The wiring DRL is a drive line, and the wiring SNL is a sense line. Here, the wiring DRL of the αth (α is an integer of 1 or more and m or less) is called the wiring DRL <α>, and the wiring SNL of the β (β is an integer of 1 or more and n or less) is called the wiring SNL <β>. I will call it. The capacitance CT _αβ is a capacitance formed between the wiring DRL <α> and the wiring SNL <β>.

The m wiring DRLs are electrically connected to the TS driver 73. The TS driver 73 has a function of driving the wiring DRL. The n wiring SNLs are electrically connected to the sense circuit 74. The sense circuit 74 has a function of detecting a signal of the wiring SNL. The signal of the wiring SNL <β> when the wiring DRL <α> is driven by the TS driver 73 has information on the amount of change in the capacitance value of the capacitance CT _αβ . By analyzing the signals of the n wiring SNLs, it is possible to obtain information such as the presence / absence of touch and the touch position.

<Controller IC>
FIG. 3 is a block diagram showing a configuration example of the controller IC75. The controller IC 75 includes an interface 150, a frame memory 151, a decoder 152, a sensor controller 153, a controller 154, a clock generation circuit 155, an image processing unit 160, a memory 170, a timing controller 173, a register 175, and a touch sensor controller 184.

Communication between the controller IC 75 and the application processor 90 is performed via the interface 150. Image data, various control signals, and the like are sent from the application processor 90 to the controller IC 75. Further, the controller IC 75 sends information such as the touch position acquired by the touch sensor controller 184 to the application processor 90. Each circuit of the controller IC 75 is appropriately discarded according to the specifications of the application processor 90, the display unit 60, the touch sensor unit 70, and the like.

The frame memory 151 is a memory for storing the image data input to the controller IC 75. When the compressed image data is sent from the application processor 90, the frame memory 151 can store the compressed image data. The decoder 152 is a circuit for decompressing compressed image data. If it is not necessary to decompress the image data, the decoder 152 does not perform any processing. Alternatively, the decoder 152 may be arranged between the frame memory 151 and the interface 150.

The image processing unit 160 has a function of performing various image processing on the image data. For example, the image processing unit 160 includes a gamma correction circuit 161, a dimming circuit 162, a toning circuit 163, and an EL correction circuit 164.

The EL correction circuit 164 is provided when the source driver IC 64 is provided with a current detection circuit for detecting the current flowing through the pixel 10. The EL correction circuit 164 has a function of adjusting the brightness of the pixel 10 based on the signal transmitted from the current detection circuit of the source driver IC64.

The image data processed by the image processing unit 160 is output to the source driver IC 64 of the display unit 60 via the memory 170. The memory 170 is a memory for temporarily storing image data. The source driver IC 64 has a function of processing the input image data and writing it to the source line of the pixel array 61.

The timing controller 173 has a function of generating a timing signal used by the touch sensor controller 184, the source driver IC 64 of the display unit 60, and the gate drivers 62 and 63.

The touch sensor controller 184 has a function of controlling the TS driver 73 and the sense circuit 74 of the touch sensor unit 70. The signal including the touch information read by the sense circuit 74 is processed by the touch sensor controller 184 and sent to the application processor 90 via the interface 150. The application processor 90 generates image data reflecting the touch information and sends it to the controller IC 75. The controller IC 75 can also be configured to reflect the touch information in the image data.

The clock generation circuit 155 has a function of generating a clock signal used in the controller IC 75. The controller 154 has a function of processing various control signals sent from the application processor 90 via the interface 150 and controlling various circuits in the controller IC 75.

Further, the controller 154 has a function of controlling power supply to various circuits in the controller IC 75. The controller IC temporarily cuts off the power supply to the unused circuit in the controller IC 75, so that the controller IC performs power gating. Note that FIG. 3 shows the main signal flow, and the clock supply line, power supply line, and the like are omitted.

The register 175 stores data used for the operation of the controller IC 75. The data stored in the register 175 includes parameters used by the image processing unit 160 for performing correction processing, parameters used by the timing controller 173 to generate waveforms of various timing signals, and the like. The register 175 includes a scan chain register composed of a plurality of registers.

An optical sensor 143 is electrically connected to the sensor controller 153. The optical sensor 143 detects the light 145 and generates a detection signal. The sensor controller 153 generates a control signal based on the detection signal. The control signal generated by the sensor controller 153 is output to, for example, the controller 154.

The image processing unit 160 can adjust the brightness of the pixel 10 according to the brightness of the light 145 measured by using the optical sensor 143 and the sensor controller 153. That is, in an environment where the brightness of the light 145 is dark, the glare can be reduced and the power consumption can be reduced by lowering the brightness of the pixel 10. Further, in an environment where the brightness of the light 145 is bright, it is possible to obtain display quality having excellent visibility by increasing the brightness of the pixel 10. These adjustments may be centered on the brightness set by the user. Here, the adjustment is referred to as dimming or dimming processing. Further, the circuit that executes the process is called a dimming circuit.

Further, the function of measuring the color tone of the light 145 can be added to the optical sensor 143 and the sensor controller 153 to correct the color tone. For example, in a reddish environment at dusk, the eyes of the user of the display device 80 undergo chromatic adaptation, and the reddish color is perceived as white. In this case, since the display of the display device 80 looks pale, the color tone can be corrected by emphasizing the R (red) component of the display device 80. Here, the correction is referred to as toning or toning processing. Further, the circuit that executes the process is called a toning circuit.

When the display area of the display unit 60 has a backlight, the dimming process and the toning process may be performed on the backlight.

The image processing unit 160 may have another processing circuit such as an RGB-RGBW conversion circuit depending on the specifications of the display unit 60. The RGB-RGBW conversion circuit is a circuit that converts RGB (red, green, blue) image data into RGBW (red, green, blue, white) image data. That is, when the pixel array 61 has pixels of four RGBW colors, the W (white) component in the image data is displayed by using the W (white) pixels, so that the power consumption can be reduced. When the display unit 60 has four RGB color pixels, for example, an RGB-RGBY (red, green, blue, yellow) conversion circuit can be used.

<Parameter>
Image correction processing such as gamma correction, dimming, and toning corresponds to processing for creating output correction data Y with respect to input image data X. The parameter used by the image processing unit 160 is a parameter for converting the image data X into the correction data Y.

The parameter setting method includes a table method and a function approximation method. In the table method shown in FIG. 4A, the correction data Y _n is stored in the table as a parameter for the image data X _n . The table method requires a large number of registers for storing the parameters corresponding to the table, but the degree of freedom of correction is high. On the other hand, when the correction data Y for the image data X can be determined empirically in advance, it is effective to adopt the function approximation method as shown in FIG. 4B. The parameters are a1, a2, b2, and the like. Here, the method of linear approximation for each section is shown, but the method of approximation by a nonlinear function is also possible. In the function approximation method, the degree of freedom of correction is low, but the number of registers that store the parameters that define the function is small.

The parameter used by the timing controller 173 indicates, for example, as shown in FIG. 4C, the timing at which the generated signal of the timing controller 173 becomes “L” (or “H”) with respect to the reference signal. be. The parameter Ra (or Rb) indicates how many clock cycles the timing of becoming “L” (or “H”) with respect to the reference signal is.

The above parameters for correction can be stored in the register 175. In addition to the above, parameters that can be stored in the register 175 include data of the EL correction circuit 164, brightness, color tone, and energy saving setting of the display device 80 set by the user (time until the display is darkened or turned off). ), The sensitivity of the touch sensor controller 184, and the like.

<Power gating>
The controller 154 can power gate a part of the circuit in the controller IC 75 when there is no change in the image data supplied from the application processor 90. Specifically, for example, the circuit in the area 190 (frame memory 151, decoder 152, image processing unit 160, memory 170, timing controller 173, register 175) can be power gated.

Since the controller IC 75 has the frame memory 151, the application processor 90 does not need to supply the image data to the controller IC 75 when there is no change in the image data. Alternatively, the application processor 90 may be configured to transmit a control signal indicating that there is no change in the image data to the controller IC 75. The controller IC 75 can perform power gating when new image data is no longer supplied, or when a control signal indicating that there is no change in the image data is detected by the controller 154.

Since the circuit in the area 190 is a circuit related to the image data and a circuit for driving the display unit 60, the circuit in the area 190 can be temporarily stopped if there is no change in the image data. Even when there is no change in the image data, the time during which the transistor used for the pixel 10 can hold the data (the time during which the IDS can be driven) may be considered. For example, by incorporating a timer function into the controller 154, the timing for restarting the power supply to the circuit in the region 190 may be determined based on the time measured by the timer.

For example, the controller 154 may incorporate a timer function to determine the timing at which power supply to the circuit in the region 190 is restarted based on the time measured by the timer. It is possible to store the image data in the frame memory 151 or the memory 170 and use the image data as the image data to be supplied to the display unit 60 at the time of inversion drive. With such a configuration, inversion drive can be executed without transmitting image data from the application processor 90. Therefore, the amount of data transmitted from the application processor 90 can be reduced, and the power consumption of the display system 100 can be reduced.

In order to perform power gating of the controller IC, it is necessary to prepare the register 175 to store (save) the data in the non-volatile register in which the data is not lost even when the power supply is cut off. It is preferable to perform this preparatory operation before the image data changes, because a long power gating time can be secured.

Hereinafter, a specific circuit configuration of the frame memory 151 and the register 175 will be described. The circuit in the region 190 described as a circuit capable of power gating is not limited to this. Various combinations can be considered depending on the configuration of the controller IC 75, the standard of the application processor 90, the specifications of the display device 80, and the like.

<Frame memory 151>
FIG. 5A shows a configuration example of the frame memory 151. The frame memory 151 includes a control unit 202, a cell array 203, and a peripheral circuit 208. The peripheral circuit 208 includes a sense amplifier circuit 204, a driver 205, a main amplifier 206, and an input / output circuit 207.

The control unit 202 has a function of controlling the frame memory 151. For example, the control unit 202 controls the driver 205, the main amplifier 206, and the input / output circuit 207.

A plurality of wiring WLs and CSELs are electrically connected to the driver 205. The driver 205 generates a signal to be output to a plurality of wiring WLs and CSELs.

The cell array 203 has a plurality of memory cells 209. The memory cell 209 is electrically connected to the wiring WL, LBL (or LBLB), and BGL. The wiring WL is a word line, and the wiring LBL and LBLB are local bit lines. In the example of FIG. 5A, the configuration of the cell array 203 is a folded bit line method, but an open bit line method can also be used.

FIG. 5B shows a configuration example of the memory cell 209. The memory cell 209 has a transistor NW1 and a capacitive element CS1. The memory cell 209 has a circuit configuration similar to that of a memory cell of a DRAM (Dynamic Random Access Memory). Here, the transistor NW1 is a transistor having a back gate. The back gate of the transistor NW1 is electrically connected to the wiring BGL. The voltage Vbg_w1 is input to the wiring BGL.

The transistor NW1 is an OS transistor. Since the off-current of the OS transistor is extremely small, by configuring the memory cell 209 with the OS transistor, it is possible to suppress the leakage of electric charge from the capacitive element CS1, so that the frequency of the refresh operation of the frame memory 151 can be reduced. Further, even if the power supply is cut off, the frame memory 151 can hold the image data for a long time. Further, by setting the voltage Vbg_w1 to a negative voltage, the threshold voltage of the transistor NW1 can be shifted to the positive potential side, and the holding time of the memory cell 209 can be lengthened.

The off-current here means the current flowing between the source and the drain when the transistor is in the off state. When the transistor is an n-channel type, for example, when the threshold voltage is about 0V to 2V, the current flowing between the source and the drain when the gate voltage with respect to the source is a negative voltage is turned off. Can be called.

Further, the extremely small off-current means that, for example, the off-current per 1 μm of the channel width is 100 zA (z; Zepto, ^10-21 ) or less. Since the smaller the off current is, the more preferable it is, so that the standardized off current is preferably 10 zA / μm or less, preferably 1 zA / μm or less, and more preferably 10 ^yA / μm (y; Yocto, 10-24) or less. preferable.

Since the transistor NW1 of the plurality of memory cells 209 of the cell array 203 is an OS transistor, the transistor of the other circuit can be, for example, a Si transistor manufactured on a silicon wafer. As a result, the cell array 203 can be stacked and provided on the sense amplifier circuit 204. Therefore, the circuit area of the frame memory 151 can be reduced, which leads to the miniaturization of the controller IC 75. However, the configuration of one aspect of the present invention is not limited to this. For example, both the cell array 203 and other circuits (typically, the control unit 202, the peripheral circuit 208, etc.) may be formed by the OS transistor. With this configuration, a unipolar circuit configuration can be obtained, so that the manufacturing cost can be reduced. Further, by using only the OS transistor as the circuit configuration, the dielectric breakdown resistance is higher than that of the Si transistor, so that a highly reliable semiconductor device can be provided.

The cell array 203 is provided so as to be laminated on the sense amplifier circuit 204. The sense amplifier circuit 204 has a plurality of sense amplifiers SA. The sense amplifier SA is electrically connected to adjacent wiring LBL, LBLB (local bit line pair), wiring GBL, GBLB (global bit line pair), and a plurality of wiring CSELs. The sense amplifier SA has a function of amplifying the potential difference between the wiring LBL and the wiring LBLB.

The sense amplifier circuit 204 is provided with one wiring GBL for four wiring LBBLs and one wiring GBLB for four wiring LBLBs. However, the configuration of the sense amplifier circuit 204 is provided. Is not limited to the configuration example of FIG. 5 (A).

The main amplifier 206 is connected to the sense amplifier circuit 204 and the input / output circuit 207. The main amplifier 206 has a function of amplifying the potential difference between the wiring GBL and the wiring GBLB. The main amplifier 206 can be omitted.

The input / output circuit 207 reads the potential corresponding to the write data to the wiring GBL and the wiring GBLB or the main amplifier 206, the potential of the wiring GBL and the wiring GBLB, or the output potential of the main amplifier 206, and reads the potential to the outside as data. It has a function to output. A sense amplifier SA for reading data and a sense amplifier SA for writing data can be selected by the signal of the wiring CSEL. Therefore, since the input / output circuit 207 does not require a selection circuit such as a multiplexer, the circuit configuration can be simplified and the occupied area can be reduced.

<Register 175>
FIG. 6 is a block diagram showing a configuration example of the register 175. The register 175 has a scan chain register unit 175A and a register unit 175B. The scan chain register unit 175A has a plurality of registers 230. A scan chain register is composed of a plurality of registers 230. The register unit 175B has a plurality of volatile registers 231.

The register 230 is a non-volatile register in which data is not lost even when the power supply is cut off. In order to make the register 230 non-volatile, here, the register 230 includes a holding circuit using an OS transistor.

On the other hand, the volatile register 231 is volatile. There are no particular restrictions on the circuit configuration of the volatile register 231 as long as it is a circuit capable of storing data, and it may be configured with a latch circuit, a flip-flop circuit, or the like. The image processing unit 160 and the timing controller 173 access the register unit 175B and take in data from the corresponding volatile register 231. Alternatively, the image processing unit 160 and the timing controller 173 control the processing content according to the data supplied from the register unit 175B.

When updating the data stored in the register 175, first, the data in the scan chain register unit 175A is changed. After rewriting the data of each register 230 of the scan chain register unit 175A, the data of each register 230 of the scan chain register unit 175A is collectively loaded into each volatile register 231 of the register unit 175B.

As a result, the image processing unit 160, the timing controller 173, and the like can perform various processes using the collectively updated data. Since the simultaneity of data update is maintained, stable operation of the controller IC75 can be realized. By providing the scan chain register unit 175A and the register unit 175B, the data of the scan chain register unit 175A can be updated even while the image processing unit 160 and the timing controller 173 are operating.

When power gating of the controller IC 75 is executed, data is stored (saved) in the holding circuit in the register 230, and then the power supply is cut off. After the power is restored, the data in the register 230 is restored (loaded) to the volatile register 231 and the normal operation is resumed. If the data stored in the register 230 and the data stored in the volatile register 231 do not match, the data in the volatile register 231 is saved in the register 230, and then the holding circuit of the register 230 is used again. A configuration for storing data is preferable. Examples of cases where the data do not match include inserting update data into the scan chain register unit 175A.

FIG. 7 shows a circuit configuration example of the register 230 and the volatile register 231. FIG. 7 shows a register 230 for two stages of the scan chain register unit 175A and two volatile registers 231 corresponding to these registers 230. The signal Scan In is input to the register 230, and the signal Scan Out is output.

The register 230 has a holding circuit 17, a selector 18, and a flip-flop circuit 19. A scan flip-flop circuit is composed of a selector 18 and a flip-flop circuit 19. The signal SAVE1 is input to the selector 18.

The signals SAVE2 and LOAD2 are input to the holding circuit 17. The holding circuit 17 includes transistors T1 to T6 and capacitive elements C4 and C6. The transistors T1 and T2 are OS transistors. The transistors T1 and T2 may be OS transistors with a back gate in the same manner as the transistor NW1 of the memory cell 209 (see FIG. 5B).

The transistors T1, T3, T4 and the capacitive element C4 form a three-transistor type gain cell. Similarly, the transistors T2, T5, T6 and the capacitive element C6 form a three-transistor type gain cell. The two gain cells store complementary data held by the flip-flop circuit 19. Since the transistors T1 and T2 are OS transistors, the holding circuit 17 can hold data for a long time even when the power supply is cut off. In the register 230, the transistors other than the transistors T1 and T2 may be composed of Si transistors.

The holding circuit 17 stores complementary data held by the flip-flop circuit 19 according to the signal SAVE2, and loads the held data into the flip-flop circuit 19 according to the signal LOAD2.

The output terminal of the selector 18 is electrically connected to the input terminal of the flip-flop circuit 19, and the input terminal of the volatile register 231 is electrically connected to the data output terminal. The flip-flop circuit 19 includes inverters 20 to 25 and analog switches 27 and 28. The on / off of the analog switches 27 and 28 is controlled by a scan clock (denoted as Scan Clock in FIG. 7) signal. The flip-flop circuit 19 is not limited to the circuit configuration of FIG. 7, and various flip-flop circuits 19 can be applied.

The output terminal of the volatile register 231 is electrically connected to one of the two input terminals of the selector 18, and the output terminal of the flip-flop circuit 19 in the previous stage is electrically connected to the other. Data is input from the outside of the register 175 to the input terminal of the selector 18 in the first stage of the scan chain register unit 175A.

The volatile register 231 includes inverters 31 to 33, a clocked inverter 34, an analog switch 35, and a buffer 36. The volatile register 231 loads the data of the flip-flop circuit 19 based on the signal LOAD1. The transistor of the volatile register 231 may be composed of a Si transistor.

<Application processor>
The application processor 90 can obtain information about an application operating in an electronic device having a display system 100 by monitoring image data supplied to the controller IC 75, touch information detected by the touch sensor unit 70, and the like. ..

For example, when an electronic device having a display system 100 is used as a game, or when a TV broadcast, a video movie, or the like is displayed on the electronic device having a display system 100 (hereinafter referred to as a category 1 application). The image data is constantly updated, and the application processor 90 needs to supply the image data with high frequency.

For example, when an electronic device having a display system 100 is used for viewing an electronic book, viewing a photo, etc. (hereinafter referred to as a category 2 application), the touch information detected by the touch sensor unit 70 may be an image scroll or a page. There are many flicks used for feeding, and pinch-in and pinch-out operations used for enlarging and reducing images. Further, after the flick, pinch-in, and pinch-out operations, the image data is updated, and the application processor 90 supplies the image data. At the timing when the touch sensor unit 70 does not detect the touch information, the image data is updated less (many still images).

For example, when an electronic device having a display system 100 is used for browsing the Internet (hereinafter referred to as a classification 3 application), after the touch sensor unit 70 detects a tap operation corresponding to a mouse click, the image data is displayed. Updated and the application processor 90 supplies image data. At the timing when the touch sensor unit 70 does not detect the touch information, the image data is not updated so much, but the moving image may be displayed in a part of the display area of the display unit 60.

For example, when an electronic device having a display system 100 is used mainly for user input such as text creation represented by e-mail or table creation (hereinafter referred to as an application of classification 4), image data. The update of is relatively small, and the image data is updated for a part of the display area of the display unit 60. Further, when the handwriting input function is used, the image data around the touch position detected by the touch sensor unit 70 is updated.

As described above, the image data supplied by the application processor 90 to the controller IC 75 and the touch information detected by the touch sensor unit 70 have characteristics according to the application operating in the electronic device having the display system 100, and the application. The processor 90 can obtain information about the application.

The application processor 90 can change the frame frequency of the display device 80 by obtaining information about an application operating in the electronic device having the display system 100. For example, when the application of classification 1 is operating, the maximum frame frequency that can be displayed by the display device 80 can be set.

For example, when the maximum frame frequency that can be displayed by the display device 80 is 120 Hz, when the application of category 1 is operating, the frame frequency of the display device 80 is set to 120 Hz, and the applications of category 2 and category 3 are operating. When the display device 80 is operating, the frame frequency of the display device 80 can be set to 60 Hz, and when the application of classification 4 is operating, the frame frequency of the display device 80 can be set to 30 Hz.

The application processor 90 supplies a signal relating to the frame frequency of the display device 80 as one of the control signals supplied to the controller IC 75, and can change the frame frequency of the display device 80. When an application operating in an electronic device having a display system 100 does not require a high frame frequency, the application processor 90 can reduce power consumption by lowering the frame frequency of the display device 80.

The target monitored by the application processor 90 is not limited to the image data supplied to the controller IC 75 and the touch information detected by the touch sensor unit 70. For example, by monitoring the communication with the external network performed by the electronic device having the display system 100, it is possible to efficiently obtain information about the application of the classification 1 and the application of the classification 3. Further, for example, by monitoring the input / output in the application processor 90 or to a storage device provided separately from the application processor 90, information on the application of category 2 can be efficiently obtained. Alternatively, it is possible to describe in the program of the application information about the application operating in the electronic device having the display system 100.

<Neural network>
The application processor 90 can utilize a neural network to obtain information about an application running on an electronic device having a display system 100. A neural network is one of the methods for realizing artificial intelligence (AI), and artificial intelligence is a computer that imitates human intelligence. Artificial intelligence can perform operations according to learning by using a neural network or the like.

The neural network of the application processor 90 operates in an electronic device having a display system 100 by learning features such as image data supplied by the application processor 90 to the controller IC 75 and touch information detected by the touch sensor unit 70. You can estimate which application you have.

Further, the neural network of the application processor 90 can predict the timing at which the controller IC 75 can shift to power gating and indicate the timing at which the preparatory operation for power gating is performed.

The controller IC 75 can perform power gating when the image data does not change and new image data is no longer supplied from the application processor 90, or a control signal indicating that the image data does not change is detected by the controller 154. Immediately before this, it is possible to find features regarding the area where the image data is rewritten, the touch information detected by the touch sensor unit 70, and the like.

That is, the neural network of the application processor 90 monitors the image data supplied by the application processor 90 to the controller IC 75, the touch information detected by the touch sensor unit 70, and the like, so that the timing at which the controller IC 75 can shift to power gating can be determined. Can be predicted.

For example, when there is no input to the touch sensor unit 70 and the area where the image data can be rewritten decreases, it can be predicted that the image data will not change soon. Further, for example, it is possible to predict that there will be no change in the image data after the input is input to the touch sensor unit 70 and the change in the image data continues for a while.

Specifically, for example, after the touch sensor unit 70 has a tap or double tap operation corresponding to a mouse click, there is a processing operation of the application, and it is predicted that the image data will not change when the display is completed. can. Further, since dragging is an operation performed when the image is desired to be moved, it can be predicted that the display will be completed relatively quickly after the dragging and the image data will not change.

Further, after the touch sensor unit 70 has a flick operation performed in the case of scrolling or page turning of an image, the image data may be changed in a large area of the display area for a while, and then the image data may not be changed. Can be predicted. Further, after the touch sensor unit 70 has a pinch-in and pinch-out operations performed when it is desired to enlarge or reduce an image, the image data is changed in a large area of the display area, and then the image data is converted to the image data relatively quickly. It can be predicted that there will be no change.

After these operations, the user of the display device 80 can predict that the image will be confirmed for a while, so that it can be predicted that there will be a time when the image data does not change.

In this way, the neural network of the application processor 90 monitors the image data supplied by the application processor 90 to the controller IC 75, the touch information detected by the touch sensor unit 70, and the like, so that the controller IC 75 can shift to power gating. It is possible to predict the timing and specify the timing to perform the preparatory operation for power gating.

After that, when there is no change in the image data and new image data is not supplied from the application processor 90, or when the controller 154 detects a control signal indicating that there is no change in the image data, the display unit 60 has an IDS. It drives and the controller IC75 performs power gating. By performing the power gating preparation operation before the image data changes, the time during which the controller IC 75 can perform power gating can be lengthened, and the power consumption of the display device 80 can be reduced more efficiently.

Actually, even if the neural network of the application processor 90 instructs the preparatory operation for power gating, the change of the image data does not stop and power gating may not be possible. In this case, the power consumption of the controller IC 75 is increased by performing the preparatory operation. Therefore, after instructing the preparatory operation for power gating, the neural network possessed by the application processor 90 learns using information as to whether or not power gating is actually performed as teacher data. According to the learning, the parameters (also referred to as weighting factors) of the neural network possessed by the application processor 90 are adjusted so as to increase the success probability of power gating.

The neural network parameters of the application processor 90 are also adjusted by information about the application running on the electronic device having the display system 100. For example, when the application of classification 2 is operating, it can be predicted that there is no change in the image data while the user of the display device 80 is checking the image, so that the preparatory operation for power gating is positively performed. It can be carried out.

In this way, the application processor 90 lowers the frame frequency of the display device 80 by obtaining information about the application operating in the electronic device having the display system 100, and the display unit 60 has a low off current in the pixel 10. The display system 100 can reduce the power consumption by driving the IDS by using a transistor and performing power gating by the controller IC75. Further, the controller IC 75 performs a power gating preparation operation before there is no change in the image data.

It should be noted that this embodiment can be appropriately combined with other embodiments described in the present specification.

(Embodiment 2)
In this embodiment, an example of a display unit applicable to the display device 80 illustrated in the above embodiment will be described.

<Configuration example>
FIG. 8A is a top view showing an example of the display unit. The display unit 700 shown in FIG. 8A has a pixel unit 702 provided on the first substrate 701, a source driver circuit unit 704 and a gate driver circuit unit 706 provided on the first substrate 701, and pixels. It has a sealing material 712 arranged so as to surround the unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706, and a second substrate 705 provided so as to face the first substrate 701. The pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 are sealed by the first substrate 701, the sealing material 712, and the second substrate 705. Although not shown in FIG. 8A, a display element is provided between the first substrate 701 and the second substrate 705.

Further, the display unit 700 electrically has a pixel unit 702, a source driver circuit unit 704, and a gate driver circuit unit 706 in a region different from the region surrounded by the sealing material 712 on the first substrate 701. An FPC terminal unit 708 (FPC: Flexible Printed Circuits) connected to the FPC terminal unit 708 (FPC: Flexible Printed Circuits) is provided. Further, the FPC 716 is connected to the FPC terminal unit 708, and various signals and the like are supplied to the pixel unit 702, the source driver circuit unit 704, and the gate driver circuit unit 706 by the FPC 716. Further, a signal line 710 is connected to each of the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708. Various signals and the like supplied by the FPC 716 are given to the pixel unit 702, the source driver circuit unit 704, the gate driver circuit unit 706, and the FPC terminal unit 708 via the signal line 710.

Further, the display unit 700 may be provided with a plurality of gate driver circuit units 706. Further, the display unit 700 shows an example in which the source driver circuit unit 704 and the gate driver circuit unit 706 are formed on the same first substrate 701 as the pixel unit 702, but the configuration is not limited to this. For example, only the gate driver circuit unit 706 may be formed on the first substrate 701, or only the source driver circuit unit 704 may be formed on the first substrate 701. In this case, a substrate on which a source driver circuit, a gate driver circuit, or the like is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) may be formed on the first substrate 701. .. The method for connecting the separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.

Further, the display unit 700 can have various elements. Examples of the element include an electroluminescence (EL) element (EL element containing organic and inorganic substances, an organic EL element, an inorganic EL element, an LED, etc.), a light emitting transistor element (a transistor that emits light according to a current), and an electron. Emission element, liquid crystal element, electronic ink element, electrophoresis element, electrowetting element, plasma display panel (PDP), MEMS (micro electromechanical system) display (for example, grating light valve (GLV), digital micromirror Devices (DMDs), digital microshutter (DMS) devices, interferrometric modulation (IMOD) devices, etc.), piezoelectric ceramic displays, and the like.

Further, as an example of a display unit using an EL element, there is an EL display or the like. As an example of a display unit using an electron emitting element, there is a field emission display (FED) or an SED type planar display (SED: Surface-conduction Electron-emitter Display). An example of a display unit using a liquid crystal element is a liquid crystal display (transmissive liquid crystal display, semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display). An example of a display unit using an electronic ink element or an electrophoresis element is electronic paper. In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

As the display method in the display unit 700, a progressive method, an interlaced method, or the like can be used. Further, the color elements controlled by the pixels at the time of color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it may be composed of four pixels of R pixel, G pixel, B pixel, and W (white) pixel. Alternatively, as in the pentile arrangement, one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element. Alternatively, one or more colors such as yellow, cyan, and magenta may be added to RGB. The size of the display area may be different for each dot of the color element. However, the disclosed invention is not limited to the display unit for color display, and can be applied to the display unit for monochrome display.

Further, a colored layer (also referred to as a color filter) may be used in order to display the display unit in full color by using white light emission (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.). .. As the colored layer, for example, red (R), green (G), blue (B), yellow (Y) and the like can be appropriately combined and used. By using the colored layer, the color reproducibility can be improved as compared with the case where the colored layer is not used. At this time, the white light in the region without the colored layer may be directly used for display by arranging the region having the colored layer and the region without the colored layer. By arranging a region that does not have a colored layer in a part thereof, it is possible to reduce the decrease in brightness due to the colored layer and reduce the power consumption by about 20% to 30% in a bright display. However, when full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, R, G, B, Y, and W may be emitted from an element having each emission color. By using the self-luminous element, the power consumption may be further reduced as compared with the case of using the colored layer.

In addition to the above-mentioned method of converting part of the light emitted from white light emitted into red, green, and blue by passing it through a color filter (color filter method), the colorization method also emits red, green, and blue light. A method used for each (three-color method) or a method of converting a part of the light emitted from the blue light to red or green (color conversion method, quantum dot method) may be applied.

The display unit 700A shown in FIG. 8B is a display unit that can be suitably used for an electronic device having a large screen. For example, it can be suitably used for a television device, a monitoring device, a digital signage, or the like.

The display unit 700A has a plurality of source driver ICs 721 and a pair of gate driver circuits 722.

Each of the plurality of source drivers IC721 is attached to the FPC723. Further, in the plurality of FPC723s, one terminal is connected to the first board 701 and the other terminal is connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be arranged on the back side of the pixel portion 702 and mounted on an electronic device.

On the other hand, the gate driver circuit 722 is formed on the first substrate 701. This makes it possible to realize an electronic device having a narrow frame.

With such a configuration, a large-sized and high-resolution display unit can be realized. For example, it can be applied to a display unit having a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more diagonally. In addition, it is possible to realize a display unit having an extremely high resolution such as full high-definition, ultra-high-definition, or super high-definition.

<Cross section configuration example>
Hereinafter, a configuration using a liquid crystal element and an EL element as display elements will be described with reference to FIGS. 9 to 11. 9 and 10 are cross-sectional views taken along the alternate long and short dash line QR shown in FIG. 8, and have a configuration in which a liquid crystal element is used as the display element. Further, FIG. 11 is a cross-sectional view of the alternate long and short dash line QR shown in FIG. 8, and has a configuration in which an EL element is used as a display element.

First, the common parts shown in FIGS. 9 to 11 will be described first, and then different parts will be described.

<Explanation of common parts of display unit>
The display unit 700 shown in FIGS. 9 to 11 includes a routing wiring unit 711, a pixel unit 702, a source driver circuit unit 704, and an FPC terminal unit 708. Further, the routing wiring portion 711 has a signal line 710. Further, the pixel unit 702 has a transistor 750 and a capacitive element 790. Further, the source driver circuit unit 704 has a transistor 752.

For the transistor provided in each pixel, it is preferable to apply a metal oxide (oxide semiconductor) to the semiconductor layer on which the channel is formed. As a result, the electric field effect mobility of the transistor can be increased as compared with the case of using amorphous silicon, so that the size (occupied area) of the transistor can be reduced. As a result, the parasitic capacitance of the source line and the gate line can be made smaller.

In particular, by applying a transistor using an oxide semiconductor, various effects as shown below can be obtained. For example, since the size (occupied area) of the transistor can be reduced, the parasitic capacitance of the transistor itself can be reduced. Further, as compared with the case of using amorphous silicon, the aperture ratio can be improved, the wiring width can be increased without sacrificing the aperture ratio, and the wiring resistance can be reduced. Further, since the on-current of the transistor can be increased, the period required for writing the pixel can be shortened. Due to such an effect, the charge / discharge period of the gate line and the source line can be shortened, and the frame frequency can be increased.

Further, since the transistor using the oxide semiconductor can make the off-current extremely small, the holding period of the potential written in the pixel can be lengthened, and the frame frequency can be lowered. For example, the frame frequency can be made variable in the range of 0.1 Hz or more and 480 Hz or less. Further, in a television device or the like, the frame frequency can be set to 30 Hz or more and 480 Hz or less, preferably 60 Hz or more and 240 Hz or less.

Another effect of using a transistor with an extremely small off-current is that the pixel holding capacity can be reduced. This makes it possible to increase the aperture ratio of the pixels and shorten the period required for writing the pixels.

In addition, if the electrical resistance and capacitance of each source line are made as small as possible, it becomes possible to drive at a higher frame frequency and to make a larger display unit. For example, using a low resistance material (eg copper, aluminum, etc.) for the source wire material, increasing the thickness and width of the source wire, thickening the interlayer insulating film between the source wire and other wiring, etc. For example, reducing the area of the intersection between the source line and other wiring.

The transistor used in this embodiment has an oxide semiconductor film that has been purified to a high degree and suppresses the formation of oxygen deficiency. The transistor can reduce the off-current. Therefore, it is possible to lengthen the holding time of an electric signal such as a data signal of image data, and it is possible to set a long writing interval. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, since the transistor used in this embodiment can obtain a relatively high field effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed drive for the display unit, it is possible to form the switching transistor of the pixel portion and the driver transistor used for the drive circuit portion on the same substrate. That is, since it is not necessary to separately use a semiconductor device formed of a silicon wafer or the like as a drive circuit, the number of parts of the semiconductor device can be reduced. Further, even in the pixel portion, by using a transistor capable of high-speed driving, it is possible to provide a high-quality image.

Further, a transistor using a semiconductor containing silicon can also be used for the semiconductor layer on which the channel is formed. For example, a transistor using amorphous silicon, microcrystalline silicon, polycrystalline silicon, or the like can be applied. In particular, it is preferable to use amorphous silicon because it can be formed on a large substrate with good yield. When amorphous silicon is used, it is preferable to use hydrided amorphous silicon (a—Si: may be referred to as H) in which dangling bonds are terminated by hydrogen.

The capacitive element 790 has a lower electrode formed through a step of processing the same conductive film as the conductive film having the same conductive film as the first gate electrode of the transistor 750, and a conductive film having the transistor 750 as a second gate electrode. It has an upper electrode formed through a step of processing the same conductive film as the film. Further, an insulating film formed between the lower electrode and the upper electrode through a step of forming the same insulating film as the insulating film functioning as the first gate insulating film of the transistor 750, and the transistor 750. An insulating film formed through a step of forming the same insulating film as the insulating film functioning as a protective insulating film is provided. That is, the capacitive element 790 has a laminated structure in which an insulating film functioning as a dielectric film is sandwiched between a pair of electrodes.

Further, in FIGS. 9 to 11, a flattening insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitive element 790.

Further, in FIGS. 9 to 11, the configuration in which the transistor 750 of the pixel unit 702 and the transistor 752 of the source driver circuit unit 704 use transistors having the same structure is illustrated, but the present invention is not limited thereto. For example, the pixel unit 702 and the source driver circuit unit 704 may use different transistors. Specifically, a top gate type transistor is used for the pixel unit 702 and a bottom gate type transistor is used for the source driver circuit unit 704, or a bottom gate type transistor is used for the pixel unit 702 and the source driver circuit unit 704 is used. For example, a configuration using a top gate type transistor can be mentioned. The source driver circuit unit 704 may be read as a gate driver circuit unit.

Further, the signal line 710 is formed through the same steps as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. When a material containing a copper element is used as the signal line 710, for example, signal delay due to wiring resistance is small, and display on a large screen is possible.

Further, the FPC terminal portion 708 has a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed through the same steps as the conductive film that functions as the source electrode and the drain electrode of the transistors 750 and 752. Further, the connection electrode 760 is electrically connected to the terminal of the FPC 716 via the anisotropic conductive film 780.

Further, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Further, a flexible substrate may be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate and the like.

Further, a structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705. A spherical spacer may be used as the structure 778.

Further, on the second substrate 705 side, a light-shielding film 738 that functions as a black matrix, a colored film 736 that functions as a color filter, and an insulating film 734 that is in contact with the light-shielding film 738 and the colored film 736 are provided.

<Example of configuration of display unit using liquid crystal element>
The display unit 700 shown in FIG. 9 has a liquid crystal element 775. The liquid crystal element 775 has a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and has a function as a counter electrode. The display unit 700 shown in FIG. 9 can display an image by controlling the transmission and non-transmission of light by changing the orientation state of the liquid crystal layer 776 by the voltage applied to the conductive film 772 and the conductive film 774.

Further, the conductive film 772 is electrically connected to a conductive film having a function as a source electrode or a drain electrode of the transistor 750. The conductive film 772 is formed on the flattening insulating film 770 and functions as a pixel electrode, that is, one electrode of the display element.

As the conductive film 772, a conductive film having a translucent light in visible light or a conductive film having a reflective property in visible light can be used. As the conductive film having translucency in visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) may be used. As the conductive film having a reflective property in visible light, for example, a material containing aluminum or silver may be used.

When a conductive film having a reflective light in visible light is used for the conductive film 772, the display unit 700 becomes a reflective liquid crystal display unit. Further, when a conductive film having a translucent light in visible light is used for the conductive film 772, the display unit 700 becomes a transmissive liquid crystal display unit. In the case of a reflective liquid crystal display unit, a polarizing plate is provided on the visual recognition side. On the other hand, in the case of a transmissive liquid crystal display unit, a pair of polarizing plates sandwiching the liquid crystal element are provided.

Further, by changing the configuration on the conductive film 772, the driving method of the liquid crystal element can be changed. An example of this case is shown in FIG. Further, the display unit 700 shown in FIG. 10 is an example of a configuration in which a lateral electric field method (for example, FFS mode) is used as a drive method for the liquid crystal element. In the case of the configuration shown in FIG. 10, the insulating film 773 is provided on the conductive film 772, and the conductive film 774 is provided on the insulating film 773. In this case, the conductive film 774 has a function as a common electrode (also referred to as a common electrode), and the orientation of the liquid crystal layer 776 is caused by the electric field generated between the conductive film 772 and the conductive film 774 via the insulating film 773. The state can be controlled.

Further, although not shown in FIGS. 9 and 10, an alignment film may be provided on either one or both of the conductive film 772 and the conductive film 774 on the side in contact with the liquid crystal layer 776. Further, although not shown in FIGS. 9 and 10, optical members (optical substrates) such as a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like depending on the conditions.

Further, when the transverse electric field method is adopted, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several weight% or more is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require an orientation treatment because it has a short response rate and is optically isotropic. Further, since the alignment film does not need to be provided, the rubbing process is not required, so that the electrostatic breakdown caused by the rubbing process can be prevented, and the defect or damage of the liquid crystal display unit during the manufacturing process can be reduced. .. Further, the liquid crystal material showing the blue phase has a small viewing angle dependence.

When a liquid crystal element is used as the display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Birefringent Optical Cell) mode, and an ASM (Axially Birefringent Optical Cell) mode are used. A Compensated Birefringence mode, a FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Antiferroelectric Liquid Crystal) mode, and the like can be used.

Further, a normally black type liquid crystal display unit, for example, a transmissive type liquid crystal display unit adopting a vertical orientation (VA) mode may be used. As the vertical orientation mode, for example, an MVA (Multi-Domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASV (Advanced Super View) mode, and the like can be used.

<Configuration example of display unit using light emitting element>
The display unit 700 shown in FIG. 11 has a light emitting element 782. The light emitting element 782 has a conductive film 772, an EL layer 786, and a conductive film 788. The display unit 700 shown in FIG. 11 can display an image by emitting light from the EL layer 786 included in the light emitting element 782 provided for each pixel. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

Examples of the material that can be used for the organic compound include a fluorescent material and a phosphorescent material. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, and core-type quantum dot materials. Further, a material containing an element group of Group 12 and Group 16, Group 13 and Group 15, or Group 14 and Group 16 may be used. Alternatively, cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As). ), Aluminum (Al), and other quantum dot materials may be used.

The display unit 700 shown in FIG. 11 is provided with an insulating film 730 on the flattening insulating film 770 and the conductive film 772. The insulating film 730 covers a part of the conductive film 772. The light emitting element 782 has a top emission structure. Therefore, the conductive film 788 has translucency and transmits the light emitted by the EL layer 786. In this embodiment, the top emission structure is exemplified, but the present invention is not limited to this. For example, it can be applied to a bottom emission structure that emits light to the conductive film 772 side and a dual emission structure that emits light to both the conductive film 772 and the conductive film 788.

Further, a colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the routing wiring section 711, and the source driver circuit section 704. Further, the colored film 736 and the light-shielding film 738 are covered with the insulating film 734. Further, the space between the light emitting element 782 and the insulating film 734 is filled with the sealing film 732. In the display unit 700 shown in FIG. 11, the configuration in which the colored film 736 is provided has been illustrated, but the present invention is not limited to this. For example, when the EL layer 786 is formed in an island shape for each pixel, that is, it is formed by painting separately, a configuration may be configured in which the colored film 736 is not provided.

<Configuration example of providing an input / output device to the display unit>
Further, an input / output device may be provided in the display unit 700 shown in FIGS. 9 to 11. Examples of the input / output device include a touch sensor and the like.

FIG. 12 shows a configuration in which the touch sensor 791 is provided in the display unit 700 shown in FIG. 10, and FIG. 13 shows a configuration in which the touch sensor 791 is provided in the display unit 700 shown in FIG.

FIG. 12 is a cross-sectional view of the configuration in which the touch sensor 791 is provided on the display unit 700 shown in FIG. 10, and FIG. 13 is a cross-sectional view of the configuration in which the touch sensor 791 is provided on the display unit 700 shown in FIG.

First, the touch sensor 791 shown in FIGS. 12 and 13 will be described below.

The touch sensor 791 shown in FIGS. 12 and 13 is a so-called in-cell type touch sensor provided between the second substrate 705 and the colored film 736. The touch sensor 791 may be formed on the second substrate 705 side before forming the colored film 736.

The touch sensor 791 has a light-shielding film 738, an insulating film 792, an electrode 793, an electrode 794, an insulating film 795, an electrode 796, and an insulating film 797. For example, it is possible to detect a change in capacitance between the electrode 793 and the electrode 794 that may occur when an object to be detected such as a finger or a stylus approaches.

Further, above the transistor 750 shown in FIGS. 12 and 13, the intersection between the electrode 793 and the electrode 794 is clearly shown. The electrode 796 is electrically connected to two electrodes 793 sandwiching the electrode 794 via an opening provided in the insulating film 795. In addition, in FIGS. 12 and 13, the configuration in which the region where the electrode 796 is provided is provided in the pixel portion 702 is exemplified, but the present invention is not limited to this, and the region may be formed in the source driver circuit portion 704, for example.

The electrodes 793 and 794 are provided in a region overlapping the light-shielding film 738. Further, as shown in FIG. 13, it is preferable that the electrode 793 is provided so as not to overlap with the light emitting element 782. Further, as shown in FIG. 12, it is preferable that the electrode 793 is provided so as not to overlap with the liquid crystal element 775. In other words, the electrode 793 has an opening in a region overlapping the light emitting element 782 and the liquid crystal element 775. That is, the electrode 793 has a mesh shape. With such a configuration, the electrode 793 can be configured not to block the light emitted by the light emitting element 782. Alternatively, the electrode 793 can be configured not to block the light transmitted through the liquid crystal element 775. Therefore, since the decrease in brightness due to the arrangement of the touch sensor 791 is extremely small, it is possible to realize a display unit having high visibility and reduced power consumption. The electrode 794 may have the same configuration.

Further, since the electrode 793 and the electrode 794 do not overlap with the light emitting element 782, a metal material having a low visible light transmittance can be used for the electrode 793 and the electrode 794. Alternatively, since the electrode 793 and the electrode 794 do not overlap with the liquid crystal element 775, a metal material having a low visible light transmittance can be used for the electrode 793 and the electrode 794.

Therefore, the resistance of the electrode 793 and the electrode 794 can be lowered as compared with the electrode using the oxide material having a high visible light transmittance, and the sensor sensitivity of the touch sensor can be improved.

For example, conductive nanowires may be used for the electrodes 793, 794, 796. The nanowire may have an average diameter of 1 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 5 nm or more and 25 nm or less. Further, as the nanowire, a metal nanowire such as Ag nanowire, Cu nanowire, Al nanowire, or carbon nanotube may be used. For example, when Ag nanowires are used for any one or all of the electrodes 793, 794, and 796, the light transmittance in visible light can be 89% or more, and the sheet resistance value can be 40Ω / □ or more and 100Ω / □ or less. ..

Further, in FIGS. 12 and 13, the configuration of the in-cell type touch sensor has been illustrated, but the present invention is not limited thereto. For example, it may be a so-called on-cell type touch sensor formed on the display unit 700 or a so-called out-cell type touch sensor used by being attached to the display unit 700.

As described above, the display unit according to one aspect of the present invention can be used in combination with various types of touch sensors.

It should be noted that this embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.

(Embodiment 3)
In this embodiment, an example of a display unit applicable to the display device 80 illustrated in the above embodiment will be described with reference to FIG.

<Circuit configuration example of display unit>
The display unit shown in FIG. 14A has a region having pixels of a display element (hereinafter referred to as a pixel unit 502) and a circuit unit (hereinafter referred to as a circuit unit) arranged outside the pixel unit 502 and having a circuit for driving the pixels. , Drive circuit unit 504), a circuit having an element protection function (hereinafter referred to as protection circuit 506), and a terminal unit 507. The protection circuit 506 may not be provided.

It is desirable that a part or all of the drive circuit unit 504 is formed on the same substrate as the pixel unit 502. As a result, the number of parts and the number of terminals can be reduced. When a part or all of the drive circuit unit 504 is not formed on the same substrate as the pixel unit 502, a part or all of the drive circuit unit 504 is provided by COG or TAB (Tape Implemented Bonding). Can be implemented.

The pixel unit 502 has a circuit (hereinafter referred to as a pixel circuit 501) for driving a plurality of display elements arranged in the X row (X is a natural number of 2 or more) and the Y column (Y is a natural number of 2 or more). The drive circuit unit 504 is a circuit for outputting a signal (scanning signal) for selecting a pixel (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a gate driver 504a). Hereinafter, it has a drive circuit such as a source driver 504b).

The gate driver 504a has a shift register and the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs the signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, and the like, and outputs a pulse signal. The gate driver 504a has a function of controlling the potential of the wiring (hereinafter referred to as gate lines GL_1 to GL_X) to which the scanning signal is given. A plurality of gate drivers 504a may be provided, and the gate lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a. Alternatively, the gate driver 504a has a function of supplying an initialization signal. However, the present invention is not limited to this, and the gate driver 504a can also supply another signal.

The source driver 504b has a shift register and the like. In the source driver 504b, in addition to the signal for driving the shift register, a signal (image data) that is the source of the data signal is input via the terminal portion 507. The source driver 504b has a function of generating a data signal to be written in the pixel circuit 501 based on the image data. Further, the source driver 504b has a function of controlling the output of a data signal according to a pulse signal obtained by inputting a start pulse, a clock signal, or the like. Further, the source driver 504b has a function of controlling the potential of the wiring (hereinafter referred to as source lines DL_1 to DL_Y) to which the data signal is given. Alternatively, the source driver 504b has a function of supplying an initialization signal. However, the present invention is not limited to this, and the source driver 504b can also supply another signal.

The source driver 504b is configured by using, for example, a plurality of analog switches. The source driver 504b can output a time-division signal of image data as a data signal by sequentially turning on a plurality of analog switches. Further, the source driver 504b may be configured by using a shift register or the like.

In each of the plurality of pixel circuits 501, the pulse signal is input via one of the plurality of gate line GLs to which the scan signal is given, and the data signal is input through one of the plurality of source line DLs to which the data signal is given. Entered. Further, in each of the plurality of pixel circuits 501, the writing and holding of the data of the data signal is controlled by the gate driver 504a. For example, in the pixel circuit 501 in the m-th row and n-th column, a pulse signal is input from the gate driver 504a via the gate line GL_m (m is a natural number of X or less), and the source line DL_n (n) depends on the potential of the gate line GL_m. Is a natural number less than or equal to Y), and a data signal is input from the source driver 504b.

The protection circuit 506 shown in FIG. 14A is connected to, for example, the gate line GL which is the wiring between the gate driver 504a and the pixel circuit 501. Alternatively, the protection circuit 506 is connected to the source line DL, which is the wiring between the source driver 504b and the pixel circuit 501. Alternatively, the protection circuit 506 can be connected to the wiring between the gate driver 504a and the terminal portion 507. Alternatively, the protection circuit 506 can be connected to the wiring between the source driver 504b and the terminal portion 507. The terminal portion 507 refers to a portion provided with a terminal for inputting a power supply, a control signal, and image data from an external circuit to the display unit.

The protection circuit 506 is a circuit that makes the wiring and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.

As shown in FIG. 14A, by providing protection circuits 506 in the pixel unit 502 and the drive circuit unit 504, respectively, the resistance of the display unit to overcurrent generated by ESD (Electrostatic Discharge) or the like is enhanced. be able to. However, the configuration of the protection circuit 506 is not limited to this, and for example, the configuration may be such that the protection circuit 506 is connected to the gate driver 504a or the protection circuit 506 is connected to the source driver 504b. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.

Further, FIG. 14A shows an example in which the drive circuit unit 504 is formed by the gate driver 504a and the source driver 504b, but the configuration is not limited to this. For example, a configuration may be configured in which only the gate driver 504a is formed and a substrate on which a separately prepared source driver circuit is formed (for example, a drive circuit board formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted.

Here, FIG. 15 shows a configuration different from that of FIG. 14 (A). In FIG. 15, a pair of source lines (for example, source line DLa1 and source line DLb1) are arranged so as to sandwich a plurality of pixels arranged in the source line direction. Further, two adjacent gate lines (for example, gate line GL_1 and gate line GL_1) are electrically connected.

Further, the pixels connected to the gate line GL_1 are connected to one source line (source line DLa1, source line DLa2, etc.), and the pixels connected to the gate line GL_1 are connected to the other source line (source line DLb1, source). It is connected to the line DLb2 etc.).

With such a configuration, two gate lines can be selected at the same time. Thereby, the length of one horizontal period can be doubled as compared with the configuration shown in FIG. 14 (A). This facilitates higher resolution and larger screen of the display unit.

Further, the plurality of pixel circuits 501 shown in FIG. 14A can be configured as shown in FIG. 14B, for example.

The pixel circuit 501 shown in FIG. 14B includes a liquid crystal element 570, a transistor 550, and a capacitive element 560.

The potential of one of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The orientation state of the liquid crystal element 570 is set according to the written data. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 570 of each of the plurality of pixel circuits 501. Further, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 570 of the pixel circuit 501 of each row.

For example, as a method of driving the display unit provided with the liquid crystal element 570, a TN mode, an STN mode, a VA mode, an ASM (Axially Cymetric Aligned Micro-cell) mode, an OCB (Optically Applied Birefringence) mode, and a FLC (Ferric crystal) mode are used. , AFLC (AntiFerroelectric Liquid Crystal) mode, MVA mode, PVA (Patterned Vertical Birefringence) mode, IPS mode, FFS mode, TBA (Transverse Bend Alignment) mode and the like may be used. In addition to the above-mentioned driving method, the display unit can be driven by an ECB (Electrically Controlled Birefringence) mode, a PDLC (Polymer Dispersed Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, a PNLC (Polymer Network Liquid Crystal) mode, or the like. However, the present invention is not limited to these, and various liquid crystal elements and various driving methods thereof can be used.

In the pixel circuit 501 in the m-th row and n-th column, one of the source electrode or the drain electrode of the transistor 550 is electrically connected to the source line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. To. Further, the gate electrode of the transistor 550 is electrically connected to the gate wire GL_m. The transistor 550 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitive element 560 is electrically connected to the wiring to which the potential is supplied (hereinafter referred to as the potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. Will be done. The potential value of the potential supply line VL is appropriately set according to the specifications of the pixel circuit 501. The capacitive element 560 has a function as a holding capacitance for holding the written data.

For example, in the display unit having the pixel circuit 501 of FIG. 14 (B), for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 14 (A), the transistor 550 is turned on, and the data signal is displayed. Write data.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 550 is turned off. By doing this sequentially line by line, the image can be displayed.

Further, the plurality of pixel circuits 501 shown in FIG. 14A can be configured as shown in FIG. 14C, for example.

Further, the pixel circuit 501 shown in FIG. 14C has transistors 552, 554, a capacitive element 562, and a light emitting element 57 2.

One of the source electrode and the drain electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a signal line DL_n) to which a data signal is given. Further, the gate electrode of the transistor 552 is electrically connected to a wiring (hereinafter referred to as a gate line GL_m) to which a gate signal is given.

The transistor 552 has a function of controlling data writing of a data signal by being turned on or off.

One of the pair of electrodes of the capacitive element 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Will be done.

The capacitance element 562 has a function as a holding capacitance for holding the written data.

One of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

One of the anode and cathode of the light emitting device 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

As the light emitting element 572, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light emitting element 572 is not limited to this, and an inorganic EL element made of an inorganic material may be used.

One of the potential supply line VL_a and the potential supply line VL_b is given a high power supply potential VDD, and the other is given a low power supply potential VSS.

In the display unit having the pixel circuit 501 of FIG. 14C, for example, the pixel circuit 501 of each row is sequentially selected by the gate driver 504a shown in FIG. 14A, the transistor 552 is turned on, and the data of the data signal is input. Write.

The pixel circuit 501 in which the data is written is put into a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled according to the potential of the written data signal, and the light emitting element 572 emits light with brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

It should be noted that this embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.

(Embodiment 4)
In this embodiment, the details of the neural network included in the application processor 90 exemplified in the above embodiment will be described.

<Neural network>
A neural network is an information processing system modeled on a neural network. It is expected that a computer with higher performance than the conventional Von Neumann computer can be realized by using a neural network, and in recent years, various studies for constructing a neural network on an electronic circuit have been advanced.

A neural network has a structure in which units imitating neurons are connected to each other, and a plurality of data are input to each neuron. The multiple data input to the neuron are each multiplied by a "weighting factor" that represents the strength of the bond, and the results are added together. When the result of the product-sum operation thus obtained exceeds the threshold value, the neuron outputs a high-level signal. This phenomenon is called "ignition".

The image data supplied to the controller IC 75 by the application processor 90, the touch information detected by the touch sensor unit 70, and the like, which are described in the first embodiment, are input to the neural network of the application processor 90. Further, after that, information on whether or not the power gating of the controller IC75 is actually performed is input.

The neural network of the application processor 90 uses the above-mentioned image data supplied by the application processor 90 to the controller IC 75, touch information detected by the touch sensor unit 70, and the like as learning data, and power gating of the controller IC 75 is actually performed. Supervised learning is performed using the information on whether or not the data is used as teacher data. Learning is performed by changing the "weight coefficient" or the like, which represents the strength of the bond.

The neural network of the application processor 90 performs power gating of the controller IC 75 from input data such as image data supplied by the application processor 90 to the controller IC 75 and touch information detected by the touch sensor unit 70 by learning. It is possible to output a signal that predicts whether or not it will be lost.

When the neural network of the application processor 90 outputs a signal predicting that power gating will be performed, the operation of storing the complementary data held by the flip-flop circuit 19 in the holding circuit 17 is performed (see FIG. 7). After that, when it is confirmed that there is no change in the image data, power gating is performed.

In this way, by predicting whether or not power gating is performed before there is no change in the image data, it is possible to promptly perform power gating after there is no change in the image data. This makes it possible to secure a long time for power gating and enhance the effect of reducing power consumption.

Hereinafter, a hierarchical neural network and supervised learning will be described as an example of a neural network that can be used for the neural network of the application processor 90.

FIG. 16A shows a configuration example of a hierarchical neural network. In FIG. 16A, neurons in each layer are shown in circles. Then, in FIG. 16A, a first layer having a function as an input layer, a first layer having a function as an intermediate layer (hidden layer), and a first layer having a function as an output layer (a). A configuration example of a hierarchical neural network having neurons (formal neurons) divided into three layers of l + 1) is shown (l is an integer of 2 or more). Then, M neurons in the (l-1) layer (M is an integer of 2 or more), N neurons in the lth layer (N is an integer of 2 or more), and neurons in the (l + 1) layer. Is K (K is an integer of 2 or more).

In addition, in FIG. 16A, five neurons among the plurality of neurons possessed by the layer (l-1) are illustrated, and four neurons among the plurality of neurons possessed by the layer l are illustrated. Of the plurality of neurons in the (l + 1) layer, three neurons are illustrated.

Further, although FIG. 16A shows a configuration example of a hierarchical neural network in which the intermediate layer is composed of one layer, the intermediate layer may be composed of a plurality of layers. Therefore, in the case of a hierarchical neural network composed of L layers (L is an integer of 3 or more), the first layer corresponds to the input layer, and the second layer to the (L-1) layer corresponds to the intermediate layer. , The Lth layer corresponds to the output layer.

In FIG. 16A, the output _zm ^(l-1) of the mth neuron (m is an integer of 1 or more and M or less) possessed by the neuron of the layer (l-1) is the thth layer possessed by the neuron of the first layer. It is assumed that n is input to a neuron (n is an integer of 1 or more and N or less). Further, it is assumed that the output z _n ^(l) of the nth neuron is input to the kth neuron (k is an integer of 1 or more and K or less) possessed by the neuron of the layer (l + 1). Further, the output of the kth neuron is z _k ^{(l + 1)} . Then, the weighting coefficient for the input to the nth neuron of the lth layer is w _nm ^(l) , and the weighting coefficient for the input to the kth neuron of the (l + 1) layer is w _kn ^{(l + 1)} .

Under the above conditions, the sum of the inputs (net values) to the nth neuron in the first layer is expressed by the following equation a1.

The arithmetic processing of the equation a1 can be performed by using the product-sum arithmetic processing circuit described later.

Further, the output z _n ^(l) of the nth neuron in the lth layer is expressed by the following equation a2.

In addition, f is an output function of a neuron ,. As the output function f of the neuron, a step function, a linear ramp function, a sigmoid function, or the like can be used. For example, the arithmetic processing of the equation a2 can be executed by using the circuit 270 shown in FIG. 16 (B). In the circuit 270, the output function f corresponds to the output characteristic of the OP amplifier. Further, the arithmetic processing of the equation a2 can be realized by performing the arithmetic processing in the arithmetic circuit corresponding to the desired output function using the output signal from the OP amplifier.

Similarly, the sum of the inputs (net values) to the kth neuron in the (l + 1) layer is expressed by the following equation a3.

The arithmetic processing of the equation a3 can be performed by using the product-sum arithmetic processing circuit described later.

Further, the output zk ^{(l + 1)} of the _kth neuron in the (l + 1) layer is expressed by the following equation a4.

For example, the arithmetic processing of the equation a4 can be executed by using the circuit 271 shown in FIG. 16 (C). In the circuit 271, the output function f corresponds to the output characteristics of the OP amplifier as in the circuit 270. Further, the arithmetic processing of the equation a4 can be realized by performing the arithmetic processing in the arithmetic circuit corresponding to the desired output function using the output signal from the OP amplifier.

With the above configuration, the output zk ^{(l + 1)} of the _kth neuron can be obtained.

Next, supervised learning will be described. Supervised learning is all the weighting coefficients of a hierarchical neural network when the output result and the desired result (sometimes called teacher data or teacher signal) are different in the above-mentioned function of the hierarchical neural network. Refers to the operation of updating based on the output result and the desired result.

As a specific example of supervised learning, a learning method using an error back propagation method will be described. FIG. 17A shows a schematic diagram of the error back propagation method. The error back propagation method is a method of changing the weighting coefficient so that the error between the output of the hierarchical neural network and the teacher data becomes small.

Specifically, in the error back propagation method, the update amount of the weighting coefficient w _nm ^(l) of the first layer is ∂ with respect to the error energy E determined by the output z _k ^(L) of the output layer and the teacher data t _k . Change the weighting factor as E / ∂w _nm ^(l) .

For example, if the error δ _n ^(l) of the first layer is defined as δ _n ^(l) ≡ ∂E / ∂u _n ^(l) , the error δ _n ^(l) is expressed by the following equation a5 and the update amount. ∂E / ∂w _nm ^(l) is expressed by the following formula a6. Note that f'is a derivative of the output function of the neuron.

For example, the arithmetic processing of the equation a5 can be executed by using the circuit 272 shown in FIG. 17 (B). Further, the arithmetic processing of the equation a6 can be executed by using the circuit 273 shown in FIG. 17 (C). As the derivative, for example, the output signal from the OP amplifier can be used to perform arithmetic processing in the arithmetic circuit corresponding to the desired derivative.

A part of the arithmetic processing of the equation a5 can be performed by using the product-sum arithmetic processing circuit described later.

Further, the error δ _k ^{(l + 1)} of the third (l + 1) layer, which is the output layer, is expressed by the following equation a7, and the update amount ∂E / ∂w _kn ^{(l + 1)} is expressed by the following equation a8.

For example, the arithmetic processing of the equation a7 can be executed by using the circuit 274 shown in FIG. 17 (D). The arithmetic processing of the equation a8 can be executed by using the circuit 273 shown in FIG. 17 (C).

<Multiply-accumulate processing circuit>
FIG. 18 shows an example of a product-sum operation processing circuit that performs arithmetic processing represented by equations a1 and a3 in a hierarchical neural network shown as an example of a neural network that can be used for a neural network included in the application processor 90. ..

An example of the product-sum calculation processing circuit shown in FIG. 18 has a function of performing analog calculation processing using analog data. By having a function of performing analog arithmetic processing, it is possible to perform arithmetic processing without converting analog data into digital data or while suppressing the frequency of converting analog data into digital data as much as possible. Therefore, a huge amount of arithmetic processing can be reduced, and the scale of the arithmetic circuit can be kept small. In addition, the time required for arithmetic processing can be reduced.

FIG. 18 shows a block diagram of the semiconductor device 107 as an example of the product-sum calculation processing circuit. The semiconductor device 107 shown in FIG. 18 includes a storage circuit 11 (MEM), a reference storage circuit 12 (RMEM), a circuit 13, and a circuit 14. The semiconductor device 107 may further include a current source circuit 15 (CREF).

The storage circuit 11 (MEM) has a memory cell MC exemplified by the memory cell MC [i, j] and the memory cell MC [i + 1, j]. Further, each memory cell MC has an element having a function of converting an input potential into a current. As an element having the above function, an active element such as a transistor can be used. FIG. 18 illustrates a case where each memory cell MC has a transistor Tr21.

A first analog potential is input to the memory cell MC from the wiring WD exemplified by the wiring WD [j]. The first analog potential corresponds to the first analog data. The memory cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr21 obtained when the first analog potential is supplied to the gate of the transistor Tr21 can be used as the first analog current. Hereinafter, the current flowing through the memory cell MC [i, j] is referred to as I [i, j], and the current flowing through the memory cell MC [i + 1, j] is referred to as I [i + 1, j].

When the transistor Tr21 operates in the saturation region, its drain current does not depend on the voltage between the source and drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is desirable to operate the transistor Tr21 in the saturation region. In order to operate the transistor Tr21 in the saturation region, it is assumed that the gate voltage and the voltage between the source and the drain are appropriately set to the voltage in the range in which the transistor Tr21 operates in the saturation region.

Specifically, in the semiconductor device 107 shown in FIG. 18, the first analog potential Vx [i, j] is input from the wiring WD [j] to the memory cell MC [i, j]. The memory cell MC [i, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i, j]. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the first analog current.

Specifically, in the semiconductor device 107 shown in FIG. 18, the first analog potential Vx [i + 1, j] is input from the wiring WD [j] to the memory cell MC [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a first analog current corresponding to the first analog potential Vx [i + 1, j]. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the first analog current.

The memory cell MC has a function of holding the first analog potential. That is, it can be said that the memory cell MC has a function of holding the first analog current corresponding to the first analog potential by holding the first analog potential.

Further, a second analog potential is input to the memory cell MC from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The second analog potential corresponds to the second analog data. The memory cell MC has a function of adding a second analog potential to the first analog potential already held, and a function of holding a third analog potential obtained by the addition. Then, the memory cell MC has a function of generating a second analog current corresponding to the third analog potential. That is, it can be said that the memory cell MC has a function of holding a second analog current corresponding to the third analog potential by holding the third analog potential.

Specifically, in the semiconductor device 107 shown in FIG. 18, the second analog potential Vw [i, j] is input from the wiring RW [i] to the memory cell MC [i, j]. The memory cell MC [i, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i, j] and the second analog potential Vw [i, j]. The memory cell MC [i, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i, j] of the memory cell MC [i, j] corresponds to the second analog current.

Further, in the semiconductor device 107 shown in FIG. 18, the second analog potential Vw [i + 1, j] is input from the wiring RW [i + 1] to the memory cell MC [i + 1, j]. The memory cell MC [i + 1, j] has a function of holding a third analog potential corresponding to the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1, j]. The memory cell MC [i + 1, j] has a function of generating a second analog current corresponding to the third analog potential. That is, in this case, the current I [i + 1, j] of the memory cell MC [i + 1, j] corresponds to the second analog current.

Then, the current I [i, j] flows between the wiring BL [j] and the wiring VR [j] via the memory cell MC [i, j]. The current I [i + 1, j] flows between the wiring BL [j] and the wiring VR [j] via the memory cell MC [i + 1, j]. Therefore, the current I [j] corresponding to the sum of the current I [i, j] and the current I [i + 1, j] passes through the memory cell MC [i, j] and the memory cell MC [i + 1, j]. It will flow between the wiring BL [j] and the wiring VR [j].

The reference storage circuit 12 (RMEM) has a memory cell MCR exemplified by the memory cell MCR [i] and the memory cell MCR [i + 1]. The first reference potential VPR is input to the memory cell MCR from the wiring WDREF. Then, the memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR [i] is referred to as IREF [i], and the current flowing through the memory cell MCR [i + 1] is referred to as IREF [i + 1].

Specifically, in the semiconductor device 107 shown in FIG. 18, the first reference potential VPR is input from the wiring WDREF to the memory cell MCR [i]. The memory cell MCR [i] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the first reference current.

Further, in the semiconductor device 107 shown in FIG. 18, the first reference potential VPR is input from the wiring WDREF to the memory cell MCR [i + 1]. The memory cell MCR [i + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the first reference current.

The memory cell MCR has a function of holding the first reference potential VPR. That is, it can be said that the memory cell MCR has a function of holding the first reference current corresponding to the first reference potential VPR by holding the first reference potential VPR.

Further, a second analog potential is input to the memory cell MCR from the wiring RW exemplified by the wiring RW [i] and the wiring RW [i + 1]. The memory cell MCR has a function of adding a second analog potential to the already held first reference potential VPR and holding the second reference potential obtained by the addition. Then, the memory cell MCR has a function of generating a second reference current according to the second reference potential. That is, it can be said that the memory cell MCR has a function of holding the second reference current corresponding to the second reference potential by holding the second reference potential.

Specifically, in the semiconductor device 107 shown in FIG. 18, the second analog potential Vw [i, j] is input from the wiring RW [i] to the memory cell MCR [i]. The memory cell MCR [i] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i, j]. The memory cell MCR [i] has a function of generating a second reference current according to the second reference potential. That is, in this case, the current IREF [i] of the memory cell MCR [i] corresponds to the second reference current.

Further, in the semiconductor device 107 shown in FIG. 18, the second analog potential Vw [i + 1, j] is input from the wiring RW [i + 1] to the memory cell MCR [i + 1]. The memory cell MCR [i + 1] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw [i + 1, j]. The memory cell MCR [i + 1] has a function of generating a second reference current according to the second reference potential. That is, in this case, the current IREF [i + 1] of the memory cell MCR [i + 1] corresponds to the second reference current.

Then, the current IREF [i] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i]. The current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i + 1]. Therefore, the current IREF corresponding to the sum of the current IREF [i] and the current IREF [i + 1] flows between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1]. Become.

The current source circuit 15 has a function of supplying the wiring BL with a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF. Then, when setting the offset current described later, the current flowing between the wiring BL [j] and the wiring VR [j] via the memory cells MC [i, j] and the memory cells MC [i + 1, j]. When I [j] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF via the memory cell MCR [i] and the memory cell MCR [i + 1], the difference current flows in the circuit 13 or the circuit 14. The circuit 13 has a function as a current source circuit, and the circuit 14 has a function as a current sink circuit.

Specifically, when the current I [j] is larger than the current IREF, the circuit 13 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. Further, the circuit 13 has a function of supplying the generated current ΔI [j] to the wiring BL [j]. That is, it can be said that the circuit 13 has a function of holding the current ΔI [j].

Further, when the current I [j] is smaller than the current IREF, the circuit 14 has a function of generating a current ΔI [j] corresponding to the difference between the current I [j] and the current IREF. Further, the circuit 14 has a function of drawing the generated current ΔI [j] from the wiring BL [j]. That is, it can be said that the circuit 14 has a function of holding the current ΔI [j].

Next, an example of the operation of the semiconductor device 107 shown in FIG. 18 will be described.

First, the potential corresponding to the first analog potential is stored in the memory cell MC [i, j]. Specifically, the potential VPR-Vx [i, j] obtained by subtracting the first analog potential Vx [i, j] from the first reference potential VPR is the memory cell MC [i] via the wiring WD [j]. , J]. In the memory cell MC [i, j], the potential VPR-Vx [i, j] is held. Further, in the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR-Vx [i, j] is generated. For example, the first reference potential VPR is a high level potential higher than the ground potential. Specifically, it is desirable that the potential is higher than the ground potential and equal to or lower than the high-level potential VDD supplied to the current source circuit 15.

Further, the first reference potential VPR is stored in the memory cell MCR [i]. Specifically, the first reference potential VPR is input to the memory cell MCR [i] via the wiring WDREF. In the memory cell MCR [i], the first reference potential VPR is held. Further, in the memory cell MCR [i], the current IREF [i] corresponding to the first reference potential VPR is generated.

Further, the potential corresponding to the first analog potential is stored in the memory cell MC [i + 1, j]. Specifically, the potential VPR-Vx [i + 1, j] obtained by subtracting the first analog potential Vx [i + 1, j] from the first reference potential VPR is the memory cell MC [i + 1] via the wiring WD [j]. , J]. In the memory cell MC [i + 1, j], the potential VPR-Vx [i + 1, j] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR-Vx [i + 1, j] is generated.

Further, the first reference potential VPR is stored in the memory cell MCR [i + 1]. Specifically, the first reference potential VPR is input to the memory cell MCR [i + 1] via the wiring WDREF. In the memory cell MCR [i + 1], the first reference potential VPR is held. Further, in the memory cell MCR [i + 1], a current IREF [i + 1] corresponding to the first reference potential VPR is generated.

In the above operation, the wiring RW [i] and the wiring RW [i + 1] are set to the reference potential. For example, as the reference potential, a ground potential, a low level potential VSS lower than the reference potential, or the like can be used. Alternatively, if a potential between the potential VSS and the potential VDD is used as the reference potential, the potential of the wiring RW can be made higher than the ground potential even if the second analog potential Vw is positive or negative, so that signal generation can be facilitated. This is preferable because it enables product calculation for positive and negative analog data.

By the above operation, a current including the currents generated in the memory cells MC electrically connected to the wiring BL [j] flows through the wiring BL [j]. Specifically, in FIG. 18, the current I [i, j] generated by the memory cell MC [i, j] and the current I [i + 1, j] generated by the memory cell MC [i + 1, j] are combined. The current I [j] flows. Further, by the above operation, a current including the currents generated in the memory cells MCR electrically connected to the wiring BLREF will flow through the wiring BLREF. Specifically, in FIG. 18, a current IREF that is a combination of the current IREF [i] generated by the memory cell MCR [i] and the current IREF [i + 1] generated by the memory cell MCR [i + 1] flows.

Next, from the difference between the current I [j] obtained by the first analog potential and the current IREF obtained by the first reference potential, while keeping the potentials of the wiring RW [i] and the wiring RW [i + 1] as the reference potentials. The current offset [j] of the obtained offset is held in the circuit 13 or the circuit 14.

Specifically, when the current I [j] is larger than the current IREF, the circuit 13 supplies the current Office [j] to the wiring BL [j]. That is, the current ICM [j] flowing through the circuit 13 corresponds to the current Office [j]. Then, the value of the current ICM [j] is held in the circuit 13. Further, when the current I [j] is smaller than the current IREF, the circuit 14 draws the current Office [j] from the wiring BL [j]. That is, the current ICP [j] flowing through the circuit 14 corresponds to the current Office [j]. Then, the value of the current ICP [j] is held in the circuit 14.

Next, the second analog potential is stored in the memory cell MC [i, j] so as to be added to the first analog potential already held in the memory cell MC [i, j]. Specifically, by setting the potential of the wiring RW [i] to a potential higher than the reference potential by Vw [i], the second analog potential Vw [i] is stored in the memory via the wiring RW [i]. It is input to the cell MC [i, j]. In the memory cell MC [i, j], the potential VPR-Vx [i, j] + Vw [i] is held. Further, in the memory cell MC [i, j], a current I [i, j] corresponding to the potential VPR-Vx [i, j] + Vw [i] is generated.

Further, the second analog potential is stored in the memory cell MC [i + 1, j] so as to be added to the first analog potential already held in the memory cell MC [i + 1, j]. Specifically, by setting the potential of the wiring RW [i + 1] to a potential higher than the reference potential by Vw [i + 1], the second analog potential Vw [i + 1] becomes a memory via the wiring RW [i + 1]. It is input to the cell MC [i + 1, j]. In the memory cell MC [i + 1, j], the potential VPR-Vx [i + 1, j] + Vw [i + 1] is held. Further, in the memory cell MC [i + 1, j], a current I [i + 1, j] corresponding to the potential VPR-Vx [i + 1, j] + Vw [i + 1] is generated.

When the transistor Tr21 operating in the saturation region is used as an element for converting the potential into a current, the potential of the wiring RW [i] is Vw [i] and the potential of the wiring RW [i + 1] is Vw [i + 1]. Assuming that, since the drain current of the transistor Tr21 of the memory cell MC [i, j] corresponds to the current I [i, j], the second analog current is expressed by the following equation a9. Note that k is a coefficient and Vth is the threshold voltage of the transistor Tr21.

Further, since the drain current of the transistor Tr21 of the memory cell MCR [i] corresponds to the current IREF [i], the second reference current is represented by the following equation a10.

Then, the current I [j] corresponding to the sum of the current I [i, j] flowing in the memory cell MC [i, j] and the current I [i + 1, j] flowing in the memory cell MC [i + 1, j] is I [j] = Σ _i I [i, j], and the current corresponding to the sum of the current IREF [i] flowing in the memory cell MCR [i] and the current IREF [i + 1] flowing in the memory cell MCR [i + 1]. The IREF is IREF = Σ _i IREF [i], and the current ΔI [j] corresponding to the difference is expressed by the following equation a11.

From the equations a9, a10, and a11, the current ΔI [j] is derived as in the following equation a12.

In the formula a12, the term represented by 2kΣ _i (Vw [i] · Vx [i, j]) is the product of the first analog potential Vx [i, j] and the second analog potential Vw [i]. It corresponds to the sum of the product of the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1].

Further, the office [j] is a current ΔI when all the potentials of the wiring RW are set as the reference potential, that is, when the second analog potential Vw [i] is 0 and the second analog potential Vw [i + 1] is 0. If [j] is set, the following equation a13 is derived from the equation a12.

Therefore, from equations a11 to a13, 2kΣ _i (Vw [i] · Vx [i, j]) corresponding to the sum of products of the first analog data and the second analog data is represented by the following equation a14. It turns out that it will be done.

If the sum of the currents flowing in the memory cell MC is the current I [j], the sum of the currents flowing in the memory cell MCR is the current IREF, and the current flowing in the circuit 13 or the circuit 14 is the current office [j], the wiring RW [i]. ] Is Vw [i], and the potential of the wiring RW [i + 1] is Vw [i + 1]. It is represented by. From the equation a14, the current Iout [j] is 2kΣ _i (Vw [i] · Vx [i, j]), and the first analog potential Vx [i, j] and the second analog potential Vw [i]. It can be seen that it corresponds to the sum of the product of the first analog potential Vx [i + 1, j] and the product of the second analog potential Vw [i + 1].

It is desirable to operate the transistor Tr21 in the saturation region, but even if the operating region of the transistor Tr21 is different from the ideal saturation region, the first analog potential Vx [i, j] and the second analog potential A current corresponding to the sum of the product of Vw [i] and the product of the first analog potential Vx [i + 1, j] and the second analog potential Vw [i + 1] can be obtained without any problem with an accuracy within a desired range. If this is possible, the transistor Tr21 can be regarded as operating in the saturation region.

For example, the weight coefficients w _n1 ^(l) to w _nM ^(l) of each neuron in the first layer are stored as the first analog data in the memory cells MC [1, j] to [M, j] in the jth column. Then, the output z ₁ ^(l-1) to the output z _M ^(l-1) of the neurons in the layer (l-1) are set to the memory cell MC [1,] via the wiring RW [1] to the wiring RW [M]. It is input as the second analog data in j] to the memory cell MC [M, j], respectively. By the above operation, the sum (net value) un ^(l) of the inputs to the _nth neuron of the first layer can be obtained from the current ΔIout [j]. Therefore, the operation of the equation a1 can be performed by using the semiconductor device 107.

For example, in the memory cells MC [1, j] to [M, j] in the jth column, the weight coefficients w _n1 ^{(l + 1)} to w _nM ^{(l + 1)} of each neuron in the layer (l + 1) are used as the first analog data. Each of them is stored, and the output z ₁ ^l to the output z _M ^l of the neurons in the first layer are stored in the memory cell MC [1, j] to the memory cell MC [M, j] via the wiring RW [1] to the wiring RW [M]. ] As the second analog data. By the above operation, the total (net value) uk ^{(l + 1)} of the inputs to the _kth neuron of the (l + 1) layer can be obtained from the current ΔIout [j]. Therefore, by using the semiconductor device 107, the calculation of the equation a3 can be performed.

For example, in the memory cells MC [1, j] to [K, j] in the jth column, the weight coefficients w _n1 ^{(l + 1)} to w _nK ^{(l + 1)} of each neuron in the layer (l + 1) are used as the first analog data. The errors δ ₁ ^{(l + 1)} to δ _K ^{(l + 1)} of the neurons in the layer (l + 1) are stored in the memory cells MC [1, j] to [K] via the wiring RW [1] to the wiring RW [K]. , J] as the second analog data, respectively. By the above operation, the values of Σ _k δ _k ^{(l + 1)} and w _kn ^{(l + 1)} in the equation a5 can be obtained from the current ΔIout [j]. Therefore, by using the semiconductor device 107, a part of the calculation of the equation a5 can be performed.

According to one aspect of the present invention, the arithmetic processing of analog data can be executed without being converted into digital data, so that the circuit scale of the arithmetic circuit can be kept small. Alternatively, according to one aspect of the present invention, the calculation process of analog data can be executed without being converted into digital data, so that the time required for the calculation process of analog data can be suppressed. Alternatively, according to one aspect of the present invention, it is possible to reduce the power consumption of the arithmetic circuit while suppressing the time required for the arithmetic processing of analog data.

Next, an example of a specific configuration of the storage circuit 11 (MEM) and the reference storage circuit 12 (RMEM) will be described with reference to FIG.

FIG. 19 illustrates a case where the storage circuit 11 (MEM) has a plurality of memory cell MCs in y rows and x columns, and the reference storage circuit 12 (RMEM) has a plurality of memory cell MCRs in y rows and 1 column. ing.

The storage circuit 11 is electrically connected to the wiring RW, the wiring WW, the wiring WD, the wiring VR, and the wiring BL. In FIG. 19, the wiring RW [1] to the wiring RW [y] are electrically connected to the memory cell MC of each row, and the wiring WW [1] to the wiring WW [y] are electrically connected to the memory cell MC of each row. Wiring WD [1] to wiring WD [x] are electrically connected to the memory cell MC in each row, and wiring BL [1] to BL [x] are connected to the memory cell MC in each row, respectively. The case where they are electrically connected is illustrated. Further, FIG. 19 illustrates a case where the wiring VR [1] to the wiring VR [x] are electrically connected to the memory cells MC in each row. The wiring VR [1] to the wiring VR [x] may be electrically connected to each other.

The reference storage circuit 12 is electrically connected to the wiring RW, the wiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. In FIG. 19, the wiring RW [1] to the wiring RW [y] are electrically connected to the memory cell MCR of each row, and the wiring WW [1] to the wiring WW [y] are electrically connected to the memory cell MCR of each row. The wiring WDREF is electrically connected to each of the rows of memory cells MCR, the wiring BLREF is electrically connected to each of the rows of memory cells MCR, and the wiring VRREF is electrically connected to each of the rows of memory cells MCR. The case where it is done is illustrated. The wiring VRREF may be electrically connected to the wiring VR [1] to the wiring VR [x].

Next, among the plurality of memory cell MCs shown in FIG. 19, any two-row, two-column memory cell MC, and among the plurality of memory cell MCRs shown in FIG. 19, any two-row, one-column memory cell MCR. The specific circuit configuration and connection relationship with the above are shown in FIG. 20 as an example.

Specifically, in FIG. 20, the memory cell MC [i, j] in the i-row j-th column, the memory cell MC [i + 1, j] in the i + 1-row j-th column, and the memory cell MC [i + 1, j] in the i-row j + 1-th column. , J + 1] and the memory cells MC [i + 1, j + 1] in the i + 1 row, j + 1 column. Specifically, FIG. 20 illustrates the memory cell MCR [i] in the i-th row and the memory cell MCR [i + 1] in the i + 1 row. In addition, i is an arbitrary number from 1 to y-1, and j is an arbitrary number from 1 to x-1.

The memory cell MC [i, j] in the i-th row, the memory cell MC [i, j + 1], and the memory cell MCR [i] are electrically connected to the wiring RW [i] and the wiring WW [i]. There is. Further, the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] in the i + 1 row are electrically connected to the wiring RW [i + 1] and the wiring WW [i + 1]. Has been done.

The memory cell MC [i, j] in the j-th column and the memory cell MC [i + 1, j] are electrically connected to the wiring WD [j], the wiring VR [j], and the wiring BL [j]. .. Further, the memory cells MC [i, j + 1] in the j + 1th column and the memory cells MC [i + 1, j + 1] are electrically connected to the wiring WD [j + 1], the wiring VR [j + 1], and the wiring BL [j + 1]. ing. Further, the memory cell MCR [i] and the memory cell MCR [i + 1] on the i + 1 row are electrically connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

Each memory cell MC and each memory cell MCR has a transistor Tr21, a transistor Tr22, and a capacitive element C11. The transistor Tr22 has a function of controlling the input of the first analog potential to the memory cell MC or the memory cell MCR. The transistor Tr21 has a function of generating an analog current according to the potential input to the gate. The capacitive element C11 has a function of adding a second analog potential to the first analog potential held in the memory cell MC or the memory cell MCR.

Specifically, in the memory cell MC shown in FIG. 20, in the transistor Tr22, the gate is electrically connected to the wiring WW, one of the source or drain is electrically connected to the wiring WD, and the other of the source or drain is a transistor. It is electrically connected to the gate of Tr21. Further, in the transistor Tr21, one of the source and the drain is electrically connected to the wiring VR, and the other of the source and the drain is electrically connected to the wiring BL. In the capacitive element C11, the first electrode is electrically connected to the wiring RW, and the second electrode is electrically connected to the gate of the transistor Tr21.

Further, in the memory cell MCR shown in FIG. 20, in the transistor Tr22, the gate is electrically connected to the wiring WW, one of the source or the drain is electrically connected to the wiring WDREF, and the other of the source or the drain is the transistor Tr21. It is electrically connected to the gate. Further, in the transistor Tr21, one of the source and the drain is electrically connected to the wiring VRREF, and the other of the source and the drain is electrically connected to the wiring BLREF. In the capacitive element C11, the first electrode is electrically connected to the wiring RW, and the second electrode is electrically connected to the gate of the transistor Tr21.

Assuming that the gate of the transistor Tr21 is the node N in the memory cell MC, in the memory cell MC, the first analog potential is input to the node N via the transistor Tr22, and then when the transistor Tr22 is turned off, the node N becomes a floating state. , The first analog potential is held at the node N. Further, in the memory cell MC, when the node N is in a floating state, a second analog potential input to the first electrode of the capacitive element C11 is given to the node N. By the above operation, the node N becomes a potential obtained by adding the second analog potential to the first analog potential.

Since the potential of the first electrode of the capacitive element C11 is given to the node N via the capacitive element C11, the amount of change in the potential of the first electrode is actually reflected in the amount of change in the potential of the node N as it is. Not done. Specifically, the coupling coefficient uniquely determined from the capacitance value of the capacitance element C11, the capacitance value of the gate capacitance of the transistor Tr21, and the capacitance value of the parasitic capacitance is multiplied by the amount of change in the potential of the first electrode. , The amount of change in the potential of the node N can be calculated accurately. Hereinafter, for the sake of clarity, the description will be made assuming that the amount of change in the potential of the first electrode is substantially reflected in the amount of change in the potential of the node N.

The drain current of the transistor Tr21 is determined according to the potential of the node N. Therefore, when the potential of the node N is held by turning off the transistor Tr22, the value of the drain current of the transistor Tr21 is also held. The drain current reflects the first analog potential and the second analog potential.

Further, when the gate of the transistor Tr21 is a node NREF in the memory cell MCR, in the memory cell MCR, the first reference potential is input to the node NREF via the transistor Tr22, and then when the transistor Tr22 is turned off, the node NREF is in a floating state. And the first reference potential is held in the node NREF. Further, in the memory cell MCR, when the node NREF is in a floating state, a second analog potential input to the first electrode of the capacitive element C11 is given to the node NREF. By the above operation, the node NREF becomes a potential obtained by adding the second analog potential to the first reference potential.

The drain current of the transistor Tr21 is determined according to the potential of the node NREF. Therefore, when the potential of the node NREF is maintained by turning off the transistor Tr22, the value of the drain current of the transistor Tr21 is also maintained. The drain current reflects the first reference potential and the second analog potential.

Assuming that the drain current flowing through the transistor Tr21 of the memory cell MC [i, j] is the current I [i, j] and the drain current flowing through the transistor Tr21 of the memory cell MC [i + 1, j] is the current I [i + 1, j]. , The sum of the currents supplied from the wiring BL [j] to the memory cells MC [i, j] and the memory cells MC [i + 1, j] is the current I [j]. Further, the drain current flowing through the transistor Tr21 of the memory cell MC [i, j + 1] is the current I [i, j + 1], and the drain current flowing through the transistor Tr21 of the memory cell MC [i + 1, j + 1] is the current I [i + 1, j + 1]. Then, the sum of the currents supplied from the wiring BL [j + 1] to the memory cells MC [i, j + 1] and the memory cells MC [i + 1, j + 1] is the current I [j + 1]. Further, assuming that the drain current flowing through the transistor Tr21 of the memory cell MCR [i] is the current IREF [i] and the drain current flowing through the transistor Tr21 of the memory cell MCR [i + 1] is the current IREF [i + 1], the memory cell is connected to the wiring BLREF. The sum of the currents supplied to the MCR [i] and the memory cell MCR [i + 1] is the current IREF.

Next, an example of a specific configuration of the circuit 13, the circuit 14, and the current source circuit 15 (CREF) will be described with reference to FIG. 21.

FIG. 21 shows an example of the configuration of the circuit 13, the circuit 14, and the current source circuit 15 corresponding to the memory cell MC and the memory cell MCR shown in FIG. Specifically, the circuit 13 shown in FIG. 21 has a circuit 13 [j] corresponding to the memory cell MC in the jth column and a circuit 13 [j + 1] corresponding to the memory cell MC in the j + 1th column. Further, the circuit 14 shown in FIG. 21 has a circuit 14 [j] corresponding to the memory cell MC in the jth column and a circuit 14 [j + 1] corresponding to the memory cell MC in the j + 1th column.

The circuit 13 [j] and the circuit 14 [j] are electrically connected to the wiring BL [j]. Further, the circuit 13 [j + 1] and the circuit 14 [j + 1] are electrically connected to the wiring BL [j + 1].

The current source circuit 15 is electrically connected to the wiring BL [j], the wiring BL [j + 1], and the wiring BLREF. The current source circuit 15 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL [j] and the wiring BL [j + 1]. Has.

Specifically, the circuit 13 [j] and the circuit 13 [j + 1] have transistors Tr27 to Tr29 and a capacitive element C13, respectively. When setting the offset current, in the circuit 13 [j], the transistor Tr27 has a current ICM [j] corresponding to the difference between the current I [j] and the current IREF when the current I [j] is larger than the current IREF. j] has a function of generating. Further, in the circuit 13 [j + 1], the transistor Tr27 has a function of generating a current ICM [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is larger than the current IREF. Have. The current ICM [j] and the current ICM [j + 1] are supplied from the circuit 13 [j] and the circuit 13 [j + 1] to the wiring BL [j] and the wiring BL [j + 1].

Then, in the circuit 13 [j] and the circuit 13 [j + 1], the transistor Tr27 is electrically connected to the wiring BL to which one of the source and the drain corresponds, and a predetermined potential is supplied to the other of the source and the drain. It is electrically connected to the wiring. In the transistor Tr28, one of the source and the drain is electrically connected to the wiring BL, and the other of the source and the drain is electrically connected to the gate of the transistor Tr27. In the transistor Tr29, one of the source and the drain is electrically connected to the gate of the transistor Tr27, and the other of the source and the drain is electrically connected to the wiring to which a predetermined potential is supplied. In the capacitive element C13, the first electrode is electrically connected to the gate of the transistor Tr27, and the second electrode is electrically connected to the wiring to which a predetermined potential is supplied.

The gate of the transistor Tr28 is electrically connected to the wiring OSM, and the gate of the transistor Tr29 is electrically connected to the wiring ORM.

Note that FIG. 21 illustrates a case where the transistor Tr27 is a p-channel type and the transistors Tr28 and Tr29 are an n-channel type.

Further, the circuit 14 [j] and the circuit 14 [j + 1] have transistors Tr24 to Tr26 and a capacitive element C12, respectively. When setting the offset current, in the circuit 14 [j], the transistor Tr24 has a current ICP [j] corresponding to the difference between the current I [j] and the current IREF when the current I [j] is smaller than the current IREF. j] has a function of generating. Further, in the circuit 14 [j + 1], the transistor Tr24 has a function of generating a current ICP [j + 1] corresponding to the difference between the current I [j + 1] and the current IREF when the current I [j + 1] is smaller than the current IREF. Have. The current ICP [j] and the current ICP [j + 1] are drawn into the circuit 14 [j] and the circuit 14 [j + 1] from the wiring BL [j] and the wiring BL [j + 1].

The current ICM [j] and the current ICP [j] correspond to the office set [j]. Further, the current ICM [j + 1] and the current ICP [j + 1] correspond to the Offset [j + 1].

Then, in the circuit 14 [j] and the circuit 14 [j + 1], the transistor Tr24 is electrically connected to the wiring BL to which one of the source and the drain corresponds, and a predetermined potential is supplied to the other of the source and the drain. It is electrically connected to the wiring. In the transistor Tr25, one of the source and the drain is electrically connected to the wiring BL, and the other of the source and the drain is electrically connected to the gate of the transistor Tr24. In the transistor Tr26, one of the source and the drain is electrically connected to the gate of the transistor Tr24, and the other of the source and the drain is electrically connected to the wiring to which a predetermined potential is supplied. In the capacitive element C12, the first electrode is electrically connected to the gate of the transistor Tr24, and the second electrode is electrically connected to the wiring to which a predetermined potential is supplied.

The gate of the transistor Tr25 is electrically connected to the wiring OSP, and the gate of the transistor Tr26 is electrically connected to the wiring ORP.

Note that FIG. 21 illustrates a case where the transistors Tr24 to Tr26 are of the n-channel type.

Further, the current source circuit 15 has a transistor Tr30 corresponding to the wiring BL and a transistor Tr31 corresponding to the wiring BLREF. Specifically, the current source circuit 15 shown in FIG. 21 has a transistor Tr30 [j] corresponding to the wiring BL [j] and a transistor Tr30 [j + 1] corresponding to the wiring BL [j + 1] as the transistor Tr30. Is illustrated.

The gate of the transistor Tr30 is electrically connected to the gate of the transistor Tr31. Further, in the transistor Tr30, one of the source and the drain is electrically connected to the corresponding wiring BL, and the other of the source and the drain is electrically connected to the wiring to which a predetermined potential is supplied. In the transistor Tr31, one of the source and the drain is electrically connected to the wiring BLREF, and the other of the source and the drain is electrically connected to the wiring to which a predetermined potential is supplied.

The transistor Tr30 and the transistor Tr31 have the same polarity. FIG. 21 illustrates a case where both the transistor Tr30 and the transistor Tr31 have a p-channel type.

The drain current of the transistor Tr31 corresponds to the current IREF. Since the transistor Tr30 and the transistor Tr31 have a function as a current mirror circuit, the drain current of the transistor Tr30 is substantially the same as the drain current of the transistor Tr31 or a value corresponding to the drain current of the transistor Tr31.

A switch may be provided between the circuit 13 [j] and the circuit 14 [j] shown in FIG. Further, a switch may be provided between the circuit 13 [j + 1] and the circuit 14 [j + 1]. Alternatively, a switch may be provided between the transistor Tr 31 included in the current source circuit 15 and the reference storage circuit 12.

Next, an example of a specific operation of the semiconductor device 107 according to one aspect of the present invention will be described with reference to FIGS. 20 and 21.

FIG. 22 corresponds to an example of a timing chart showing the operations of the memory cell MC and the memory cell MCR shown in FIG. 20 and the circuits 13, the circuit 14, and the current source circuit 15 shown in FIG. 21. In FIG. 22, at time T01 to time T04, the operation of storing the first analog data in the memory cell MC and the memory cell MCR is performed. At time T05 to time T10, an operation of setting an offset current Office is performed in the circuit 13 and the circuit 14. At time T11 to time T16, an operation of acquiring data corresponding to the product-sum value of the first analog data and the second analog data is performed.

It is assumed that a low level potential is supplied to the wiring VR [j] and the wiring VR [j + 1]. Further, it is assumed that all the wirings electrically connected to the circuit 13 having a predetermined potential are supplied with a high level potential VDD. Further, it is assumed that all the wiring having a predetermined potential electrically connected to the circuit 14 is supplied with the low level potential VSS. Further, it is assumed that all the wiring having a predetermined potential electrically connected to the current source circuit 15 is supplied with a high level potential VDD.

Further, it is assumed that the transistors Tr21, Tr24, Tr27, Tr30 [j], Tr30 [j + 1], and Tr31 operate in the saturation region.

First, at time T01 to time T02, a high level potential is given to the wiring WW [i], and a low level potential is given to the wiring WW [i + 1]. By the above operation, the transistor Tr22 is turned on in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i] shown in FIG. Further, the transistor Tr22 is maintained in the off state in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1].

Further, at time T01 to time T02, the wiring WD [j] and the wiring WD [j + 1] shown in FIG. 20 are given potentials obtained by subtracting the first analog potential from the first reference potential VPR. Specifically, the potential VPR-Vx [i, j] is given to the wiring WD [j], and the potential VPR-Vx [i, j + 1] is given to the wiring WD [j + 1]. Further, the wiring WDREF is given a first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD, for example, a potential (whether + VSS) / 2 as a reference potential. Given.

Therefore, the potential VPR-Vx [i, j] is given to the node N [i, j] of the memory cell MC [i, j] shown in FIG. 20 via the transistor Tr22, and the memory cell MC [i, j + 1] The potential VPR-Vx [i, j + 1] is given to the node N [i, j + 1] of the memory cell MCR [i] via the transistor Tr22, and the potential VPR is given to the node NREF [i] of the memory cell MCR [i] via the transistor Tr22. Given.

When the time T02 ends, the potential given to the wiring WW [i] shown in FIG. 20 changes from a high level to a low level, and the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR In [i], the transistor Tr22 is turned off. By the above operation, the potential VPR-Vx [i, j] is held in the node N [i, j], the potential VPR-Vx [i, j + 1] is held in the node N [i, j + 1], and the node NREF is held. The potential VPR is held in [i].

Then, at time T03 to time T04, the potential of the wiring WW [i] shown in FIG. 20 is maintained at a low level, and the potential of the wiring WW [i + 1] is given a high level. By the above operation, the transistor Tr22 is turned on in the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR [i + 1] shown in FIG. Further, the transistor Tr22 is maintained in the off state in the memory cell MC [i, j], the memory cell MC [i, j + 1], and the memory cell MCR [i].

Further, at time T03 to time T04, the wiring WD [j] and the wiring WD [j + 1] shown in FIG. 20 are given potentials obtained by subtracting the first analog potential from the first reference potential VPR. Specifically, the potential VPR-Vx [i + 1, j] is given to the wiring WD [j], and the potential VPR-Vx [i + 1, j + 1] is given to the wiring WD [j + 1]. Further, the wiring WDREF is given a first reference potential VPR, and the wiring RW [i] and the wiring RW [i + 1] have a potential between the potential VSS and the potential VDD, for example, a potential (whether + VSS) / 2 as a reference potential. Given.

Therefore, the potential VPR-Vx [i + 1, j] is given to the node N [i + 1, j] of the memory cell MC [i + 1, j] shown in FIG. 20 via the transistor Tr22, and the memory cell MC [i + 1, j + 1] The potential VPR-Vx [i + 1, j + 1] is given to the node N [i + 1, j + 1] of the memory cell MCR [i + 1] via the transistor Tr22, and the first node NREF [i + 1] of the memory cell MCR [i + 1] is given the potential VPR-Vx [i + 1, j + 1] via the transistor Tr22. A reference potential VPR is given.

When the time T04 ends, the potential given to the wiring WW [i + 1] shown in FIG. 20 changes from a high level to a low level, and the memory cell MC [i + 1, j], the memory cell MC [i + 1, j + 1], and the memory cell MCR At [i + 1], the transistor Tr22 is turned off. By the above operation, the potential VPR-Vx [i + 1, j] is held in the node N [i + 1, j], the potential VPR-Vx [i + 1, j + 1] is held in the node N [i + 1, j + 1], and the node NREF is held. The first reference potential VPR is held in [i + 1].

Then, at time T05 to time T06, a high level potential is applied to the wiring ORP and the wiring ORM shown in FIG. In the circuit 13 [j] and the circuit 13 [j + 1] shown in FIG. 21, the transistor Tr29 is turned on by applying a high level potential to the wiring ORM, and the gate of the transistor Tr27 is reset by applying the potential VDD. Will be done. Further, in the circuit 14 [j] and the circuit 14 [j + 1] shown in FIG. 21, the transistor Tr26 is turned on by applying a high level potential to the wiring ORP, and the gate of the transistor Tr24 is given a potential VSS. It is reset by.

When the time T06 ends, the potential applied to the wiring ORP and the wiring ORM shown in FIG. 21 changes from high level to low level, the transistor Tr29 is turned off in the circuit 13 [j] and the circuit 13 [j + 1], and the circuit 14 The transistor Tr26 is turned off in [j] and the circuit 14 [j + 1]. By the above operation, the potential VDD is held in the gate of the transistor Tr27 in the circuit 13 [j] and the circuit 13 [j + 1], and the potential VSS is held in the gate of the transistor Tr24 in the circuit 14 [j] and the circuit 14 [j + 1]. ..

Then, at time T07 to time T08, a high level potential is applied to the wiring OSP shown in FIG. Further, the wiring RW [i] and the wiring RW [i + 1] shown in FIG. 20 are given a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as a reference potential. When a high level potential is applied to the wiring OSP, the transistor Tr25 is turned on in the circuit 14 [j] and the circuit 14 [j + 1].

When the current I [j] flowing in the wiring BL [j] is smaller than the current IREF flowing in the wiring BLREF, that is, when the current ΔI [j] is positive, the transistor Tr21 of the memory cell MC [i, j] shown in FIG. 20 It means that the sum of the current that can be drawn in and the current that can be drawn in by the transistor Tr21 of the memory cell MC [i + 1, j] is smaller than the drain current of the transistor Tr30 [j]. Therefore, when the current ΔI [j] is positive, when the transistor Tr25 is turned on in the circuit 14 [j], a part of the drain current of the transistor Tr30 [j] flows into the gate of the transistor Tr24, and the potential of the gate rises. Begin to. Then, when the drain current of the transistor Tr24 becomes substantially equal to the current ΔI [j], the potential of the gate of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to the potential at which the drain current of the transistor Tr24 becomes the current ΔI [j], that is, the officeset [j] (= ICP [j]). That is, it can be said that the transistor Tr24 of the circuit 14 [j] is set to a current source through which the current ICP [j] can flow.

Similarly, when the current I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, when the transistor Tr25 is turned on in the circuit 14 [j + 1]. , A part of the drain current of the transistor Tr30 [j + 1] flows into the gate of the transistor Tr24, and the potential of the gate starts to rise. Then, when the drain current of the transistor Tr24 becomes substantially equal to the current ΔI [j + 1], the potential of the gate of the transistor Tr24 converges to a predetermined value. The potential of the gate of the transistor Tr24 at this time corresponds to a potential at which the drain current of the transistor Tr24 becomes a current ΔI [j + 1], that is, an office set [j + 1] (= ICP [j + 1]). That is, it can be said that the transistor Tr24 of the circuit 14 [j + 1] is set to a current source through which the current ICP [j + 1] can flow.

When the time T08 ends, the potential given to the wiring OSP shown in FIG. 21 changes from a high level to a low level, and the transistor Tr25 is turned off in the circuit 14 [j] and the circuit 14 [j + 1]. By the above operation, the potential of the gate of the transistor Tr24 is maintained. Therefore, the circuit 14 [j] maintains the state set to the current source capable of passing the current ICP [j], and the circuit 14 [j + 1] maintains the state set to the current source capable of flowing the current ICP [j + 1]. do.

Then, at time T09 to time T10, a high level potential is applied to the wiring OSM shown in FIG. Further, the wiring RW [i] and the wiring RW [i + 1] shown in FIG. 20 are given a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2 as a reference potential. When a high level potential is applied to the wiring OSM, the transistor Tr28 is turned on in the circuit 13 [j] and the circuit 13 [j + 1].

When the current I [j] flowing in the wiring BL [j] is larger than the current IREF flowing in the wiring BLREF, that is, when the current ΔI [j] is negative, the transistor Tr21 of the memory cell MC [i, j] shown in FIG. 20 It means that the sum of the current that can be drawn in and the current that can be drawn in by the transistor Tr21 of the memory cell MC [i + 1, j] is larger than the drain current of the transistor Tr30 [j]. Therefore, when the current ΔI [j] is negative, when the transistor Tr28 is turned on in the circuit 13 [j], a current flows from the gate of the transistor Tr27 to the wiring BL [j], and the potential of the gate starts to decrease. Then, when the drain current of the transistor Tr27 becomes substantially equal to the absolute value of the current ΔI [j], the potential of the gate of the transistor Tr27 converges to a predetermined value. The potential of the gate of the transistor Tr27 at this time corresponds to the potential at which the drain current of the transistor Tr27 becomes the absolute value of the current ΔI [j], that is, Officeset [j] (= ICM [j]). That is, it can be said that the transistor Tr27 of the circuit 13 [j] is set to a current source through which the current ICM [j] can flow.

Similarly, when the current I [j + 1] flowing through the wiring BL [j + 1] is larger than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is negative, the transistor Tr28 is turned on in the circuit 13 [j + 1]. , A current flows from the gate of the transistor Tr27 to the wiring BL [j + 1], and the potential of the gate begins to drop. Then, when the drain current of the transistor Tr27 becomes substantially equal to the absolute value of the current ΔI [j + 1], the potential of the gate of the transistor Tr27 converges to a predetermined value. The potential of the gate of the transistor Tr27 at this time corresponds to the potential at which the drain current of the transistor Tr27 becomes the absolute value of the current ΔI [j + 1], that is, Officeset [j + 1] (= ICM [j + 1]). That is, it can be said that the transistor Tr27 of the circuit 13 [j + 1] is set to a current source through which the current ICM [j + 1] can flow.

When the time T10 ends, the potential given to the wiring OSM shown in FIG. 21 changes from a high level to a low level, and the transistor Tr28 is turned off in the circuit 13 [j] and the circuit 13 [j + 1]. By the above operation, the potential of the gate of the transistor Tr27 is maintained. Therefore, the circuit 13 [j] maintains the state set to the current source capable of passing the current ICM [j], and the circuit 13 [j + 1] maintains the state set to the current source capable of flowing the current ICM [j + 1]. do.

In the circuit 14 [j] and the circuit 14 [j + 1], the transistor Tr24 has a function of drawing a current. Therefore, when the current I [j] flowing in the wiring BL [j] is larger than the current IREF flowing in the wiring BLREF and the current ΔI [j] is negative at time T07 to time T08, or the current flowing in the wiring BL [j + 1] When I [j + 1] is larger than the current IREF flowing through the wiring BLREF and the current ΔI [j + 1] is negative, the wiring BL [j] or the wiring BL [j + 1] is just right from the circuit 14 [j] or the circuit 14 [j + 1]. May be difficult to supply current to. In this case, in order to balance the current flowing through the wiring BL [j] or the wiring BL [j + 1] with the current flowing through the wiring BLREF, the transistor Tr21 of the memory cell MC and the circuit 14 [j] or the circuit 14 [j + 1] are used. ], And the transistor Tr30 [j] or Tr30 [j + 1] may both be difficult to operate in the saturation region.

Even when the current ΔI [j] is negative at time T07 to time T08, at time T05 to time T06, in order to ensure operation in the saturation region of the transistors Tr21, Tr24, Tr30 [j] or Tr30 [j + 1]. Instead of resetting the gate of the transistor Tr27 to the potential VDD, the potential of the gate of the transistor Tr27 may be set to a height sufficient to obtain a predetermined drain current. With the above configuration, since the current is supplied from the transistor Tr27 in addition to the drain current of the transistor Tr30 [j] or Tr30 [j + 1], the current that cannot be drawn in the transistor Tr21 can be drawn to some extent in the transistor Tr24. , The operation in the saturation region of the transistors Tr21, Tr24, Tr30 [j] or Tr30 [j + 1] can be ensured.

At time T09 to time T10, when the current I [j] flowing through the wiring BL [j] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j] is positive, the time T07 to the time T08 Since the circuit 14 [j] is already set as a current source through which the current ICP [j] can flow, the potential of the gate of the transistor Tr27 in the circuit 13 [j] remains substantially the potential VDD. Similarly, when the current I [j + 1] flowing through the wiring BL [j + 1] is smaller than the current IREF flowing through the wiring BLREF, that is, when the current ΔI [j + 1] is positive, the circuit 14 [j + 1] is set at time T07 to time T08. Since the current ICP [j + 1] is already set as a current source through which the current ICP [j + 1] can flow, the potential of the gate of the transistor Tr27 in the circuit 13 [j + 1] remains substantially the potential VDD.

Next, at time T11 to time T12, the wiring RW [i] shown in FIG. 20 is given a second analog potential Vw [i]. Further, the wiring RW [i + 1] is still given a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, as a reference potential. Specifically, the potential of the wiring RW [i] is higher by the potential difference Vw [i] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2. For the sake of clarity, it is assumed that the potential of the wiring RW [i] is the potential Vw [i].

Assuming that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, the memory shown in FIG. 20 The potential of the node N in the cell MC [i, j] is VPR-Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR-Vx [i, j + 1] + Vw. It becomes [i]. Then, from the above equation a14, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i, j] is the current obtained by subtracting the Offset [j] from the current ΔI [j]. That is, it can be seen that it is reflected in the current Iout [j] flowing out from the wiring BL [j]. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] is the current obtained by subtracting the office [j + 1] from the current ΔI [j + 1], that is, the wiring BL [ It can be seen that it is reflected in the current Iout [j + 1] flowing out from j + 1].

When the time T12 ends, the wiring RW [i] is again given a potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (whether + VSS) / 2.

Next, at time T13 to time T14, the wiring RW [i + 1] shown in FIG. 20 is given a second analog potential Vw [i + 1]. Further, the wiring RW [i] is still given a potential between the potential VSS and the potential VDD, for example, a potential (whether + VSS) / 2 as a reference potential. Specifically, the potential of the wiring RW [i + 1] is higher by the potential difference Vw [i + 1] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2, but the following For the sake of clarity, it is assumed that the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

Assuming that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, the memory shown in FIG. 20 The potential of the node N in the cell MC [i + 1, j] is VPR-Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR-Vx [i + 1, j + 1] + Vw. It becomes [i + 1]. Then, from the above equation a14, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i + 1, j] is the current obtained by subtracting the Offset [j] from the current ΔI [j]. That is, it can be seen that it is reflected in the current Iout [j]. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i + 1, j + 1] is the current obtained by subtracting the office [j + 1] from the current ΔI [j + 1], that is, the current Iout [. It can be seen that it is reflected in j + 1].

When the time T14 ends, the wiring RW [i + 1] is again given a potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (whether + VSS) / 2.

Next, at time T15 to time T16, the wiring RW [i] shown in FIG. 20 is given a second analog potential Vw [i], and the wiring RW [i + 1] is given a second analog potential Vw [i + 1]. .. Specifically, the potential of the wiring RW [i] is higher by the potential difference Vw [i] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2, and the wiring RW [i] The potential of i + 1] is higher by the potential difference Vw [i + 1] with respect to the potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (VDD + VSS) / 2, but in order to make the explanation below easy to understand. It is assumed that the potential of the wiring RW [i] is the potential Vw [i] and the potential of the wiring RW [i + 1] is the potential Vw [i + 1].

Assuming that when the wiring RW [i] becomes the potential Vw [i], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, the memory shown in FIG. 20 The potential of the node N in the cell MC [i, j] is VPR-Vx [i, j] + Vw [i], and the potential of the node N in the memory cell MC [i, j + 1] is VPR-Vx [i, j + 1] + Vw. It becomes [i]. Further, assuming that when the wiring RW [i + 1] becomes the potential Vw [i + 1], the amount of change in the potential of the first electrode of the capacitive element C11 is substantially reflected in the amount of change in the potential of the node N, FIG. 20 shows. The potential of the node N in the memory cell MC [i + 1, j] shown is VPR-Vx [i + 1, j] + Vw [i + 1], and the potential of the node N in the memory cell MC [i + 1, j + 1] is VPR-Vx [i + 1, j + 1]. ] + Vw [i + 1].

Then, from the above equation a14, the product sum value of the first analog data and the second analog data corresponding to the memory cells MC [i, j] and the memory cells MC [i + 1, j] is the current ΔI [j]. ] And Ioffset [j] is subtracted, that is, it is reflected in the current Iout [j]. Further, the product sum value of the first analog data and the second analog data corresponding to the memory cell MC [i, j + 1] and the memory cell MC [i + 1, j + 1] is from the current ΔI [j + 1] to the office [j + 1]. It can be seen that it is reflected in the current obtained by subtracting, that is, the current Iout [j + 1].

When the time T16 ends, the wiring RW [i] and the wiring RW [i + 1] are again given a potential between the potential VSS and the potential VDD, which is the reference potential, for example, the potential (whether + VSS) / 2.

With the above configuration, the product-sum operation can be performed on a small circuit scale. Further, with the above configuration, the product-sum operation can be performed at high speed. Further, with the above configuration, the product-sum calculation can be performed with low power consumption.

As the transistors Tr22, Tr25, Tr26, Tr28, and Tr29, it is desirable to use transistors having a significantly low off-current. By using a transistor having a significantly low off current for the transistor Tr22, the potential of the node N can be maintained for a long period of time. Further, by using a transistor having a remarkably low off current for the transistors Tr25 and Tr26, the potential of the gate of the transistor Tr24 can be maintained for a long time. Further, by using a transistor having a remarkably low off current for the transistors Tr28 and Tr29, the potential of the gate of the transistor Tr27 can be maintained for a long time.

In order to reduce the off-current of the transistor, for example, the channel formation region may be formed of a semiconductor having a large bandgap. As described above, the semiconductor having a large bandgap may refer to a semiconductor having a bandgap of 2.2 eV or more, and examples of such a semiconductor material include oxide semiconductors. An OS transistor may be used as the transistors Tr22, Tr25, Tr26, Tr28, and Tr29.

It should be noted that this embodiment can be carried out by appropriately combining at least a part thereof with other embodiments described in the present specification.

(Embodiment 5)
In the present embodiment, an example of an electronic device equipped with a display system according to one aspect of the present invention will be described.

23 (A) and 23 (B) show an example of the mobile information terminal 1800. The mobile information terminal 1800 has a housing 1801, a housing 1802, a display unit 1803, a display unit 1804, a hinge unit 1805, and the like.

The housing 1801 and the housing 1802 are connected by a hinge portion 1805. The mobile information terminal 1800 can open the housing 1801 and the housing 1802 as shown in FIG. 23 (B) from the folded state as shown in FIG. 23 (A).

For example, document information can be displayed on the display unit 1803 and the display unit 1804, and can also be used as an electronic book terminal. Further, a still image or a moving image can be displayed on the display unit 1803 and the display unit 1804.

As described above, the portable information terminal 1800 can be folded when it is carried, so that it is excellent in versatility.

The housing 1801 and the housing 1802 may have a power button, an operation button, an external connection port, a speaker, a microphone, and the like.

FIG. 23C shows an example of a mobile information terminal. The portable information terminal 1810 shown in FIG. 23C has a housing 1811, a display unit 1812, an operation button 1813, an external connection port 1814, a speaker 1815, a microphone 1816, a camera 1817, and the like.

The mobile information terminal 1810 includes a touch sensor on the display unit 1812. All operations such as making a phone call or inputting characters can be performed by touching the display unit 1812 with a finger or a stylus.

Further, by operating the operation button 1813, it is possible to switch the power ON / OFF operation and the type of the image displayed on the display unit 1812. For example, you can switch from the mail composition screen to the main menu screen.

Further, by providing a detection device such as a gyro sensor or an acceleration sensor inside the mobile information terminal 1810, the orientation (vertical or horizontal) of the mobile information terminal 1810 is determined, and the orientation of the screen display of the display unit 1812 is determined. It can be switched automatically. Further, the orientation of the screen display can be switched by touching the display unit 1812, operating the operation button 1813, voice input using the microphone 1816, or the like.

The mobile information terminal 1810 has one or more functions selected from, for example, a telephone, a notebook, an information browsing device, and the like. Specifically, it can be used as a smartphone. The personal digital assistant 1810 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, video playback, Internet communication, and games.

FIG. 23 (D) shows an example of a camera. The camera 1820 has a housing 1821, a display unit 1822, an operation button 1823, a shutter button 1824, and the like. A detachable lens 1826 is attached to the camera 1820.

Here, the camera 1820 has a configuration in which the lens 1826 can be removed from the housing 1821 and replaced, but the lens 1826 and the housing may be integrated.

The camera 1820 can capture a still image or a moving image by pressing the shutter button 1824. Further, the display unit 1822 has a function as a touch sensor, and it is possible to take an image by touching the display unit 1822.

The camera 1820 can be separately equipped with a strobe device, a viewfinder, and the like. Alternatively, these may be incorporated in the housing 1821.

FIG. 24A shows a television device 1830. The television device 1830 has a display unit 1831, a housing 1832, a speaker 1833, and the like. Further, it may have an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

Further, the television device 1830 can be operated by the remote controller operating device 1834.

Examples of the broadcast radio wave that can be received by the television device 1830 include terrestrial waves and radio waves transmitted from satellites. Further, as broadcast radio waves, there are analog broadcasting, digital broadcasting, etc., and there are also video and audio broadcasting, or audio-only broadcasting. For example, it is possible to receive broadcast radio waves transmitted in a specific frequency band within the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, for example, by using a plurality of data received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, an image having a resolution exceeding full high-definition can be displayed on the display unit 1831. For example, it is possible to display an image having a resolution of 4K-2K, 8K-4K, 16K-8K, or higher.

In addition, a configuration that generates an image to be displayed on the display unit 1831 using broadcast data transmitted by data transmission technology via a computer network such as the Internet, LAN (Local Area Network), or Wi-Fi (registered trademark). May be. At this time, the television device 1830 does not have to have a tuner.

FIG. 24B shows a digital signage 1840 attached to a columnar pillar 1842. The digital signage 1840 has a display unit 1841.

The wider the display unit 1841, the more information can be provided at one time. Further, the wider the display unit 1841, the easier it is for people to see, and for example, the advertising effect of the advertisement can be enhanced.

By applying the touch sensor to the display unit 1841, not only the image or moving image can be displayed on the display unit 1841, but also the user can intuitively operate the display unit 1841, which is preferable. In addition, when used for the purpose of providing information such as route information or traffic information, usability can be improved by intuitive operation.

FIG. 24C shows a notebook personal computer 1850. The personal computer 1850 has a display unit 1851, a housing 1852, a touch pad 1853, a connection port 1854, and the like.

The touch pad 1853 functions as an input means for a pointing device, a pen tablet, or the like, and can be operated with a finger, a stylus, or the like.

Further, a display element is incorporated in the touch pad 1853. As shown in FIG. 24C, by displaying the input key 1855 on the surface of the touchpad 1853, the touchpad 1853 can be used as a keyboard. At this time, a vibration module may be incorporated in the touch pad 1853 in order to realize a tactile sensation by vibration when the input key 1855 is touched.

25 (A), (B), and (C) show foldable electronic devices, respectively.

The electronic device 1900 shown in FIG. 25A has a housing 1901a, a housing 1901b, a hinge 1903, a display unit 1902a, a display unit 1902b, and the like. The display unit 1902a is incorporated in the housing 1901a, and the display unit 1902b is incorporated in the housing 1901b.

The housing 1901a and the housing 1901b are rotatably connected by a hinge 1903. The electronic device 1900 can be transformed into a state in which the housing 1901a and the housing 1901b are closed and a state in which the housing 1901b is open as shown in FIG. 25 (A). As a result, it is excellent in portability when it is carried, and it is excellent in visibility due to the large display area when it is used.

Further, it is preferable that the hinge 1903 has a locking mechanism so that when the housing 1901a and the housing 1901b are opened, these angles do not become larger than a predetermined angle. For example, the angle at which the lock is applied (does not open any further) is preferably 90 degrees or more and less than 180 degrees, and can be typically 90 degrees, 120 degrees, 135 degrees, or 150 degrees. .. This can enhance convenience, safety, and reliability.

At least one of the display unit 1902a and the display unit 1902b functions as a touch sensor and can be operated with a finger, a stylus, or the like.

A wireless communication module is provided in either the housing 1901a or the housing 1901b, and data is transmitted / received via a computer network such as the Internet, LAN (Local Area Network), or Wi-Fi (registered trademark). Is possible.

A flexible display may be incorporated in the display unit 1902a and the display unit 1902b. As a result, continuous display without interruption can be performed between the display unit 1902a and the display unit 1902b.

FIG. 25B shows an electronic device 1910 that functions as a portable game machine. The electronic device 1910 includes a housing 1911a, a housing 1911b, a display unit 1912a, a display unit 1912b, a hinge 1913, an operation button 1914a, an operation button 1914b, and the like.

Further, the cartridge 1915 can be inserted into the housing 1911b. The cartridge 1915 stores application software such as a game, and by exchanging the cartridge 1915, various applications can be executed by the electronic device 1910.

Further, FIG. 25B shows an example in which the size of the display unit 1912a and the size of the display unit 1912b are different. Specifically, the display unit 1912a provided in the housing 1911a is larger than the display unit 1912b included in the housing 1911b provided with the operation buttons 1914a and the operation buttons 1914b. For example, each display unit can be used properly, such as displaying a main screen on the display unit 1912a and displaying an operation screen on the display unit 1912b.

The electronic device 1920 shown in FIG. 25C is provided with a flexible display unit 1922 over the housing 1921a and the housing 1921b connected by the hinge 1923.

At least a part of the display unit 1922 can be curved. In the display unit 1922, pixels are continuously arranged from the housing 1921a to the housing 1921b, and a curved surface can be displayed.

Since the hinge 1923 has the lock mechanism described above, it is possible to prevent the display unit 1922 from being damaged without applying an excessive force to the display unit 1922. Therefore, a highly reliable electronic device can be realized.

The display system 100 exemplified in the above embodiment can be mounted on the electronic device shown in FIGS. 23 to 25. Therefore, it is possible to reduce the power consumption of the electronic device by changing the frame frequency of the display unit and performing IDS drive when displaying a still image depending on the application operating on the electronic device.

It should be noted that this embodiment can be appropriately combined with other embodiments described in the present specification.

(Embodiment 6)
In this embodiment, a metal oxide that can be used for the OS transistor will be described. In particular, the details of metal oxides and CAC (Cloud-Aligned Complex) will be described below.

The CAC-OS or CAC-metal oxide has a conductive function in a part of the material, an insulating function in a part of the material, and a semiconductor function in the whole material. When CAC-OS or CAC-metal oxide is used in the channel formation region of the transistor, the conductive function is the function of flowing electrons (or holes) to be carriers, and the insulating function is the carrier. It is a function that does not allow electrons to flow. By making the conductive function and the insulating function act in a complementary manner, a switching function (on / off function) can be imparted to the CAC-OS or the CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.

Further, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. Further, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Further, the conductive region and the insulating region may be unevenly distributed in the material. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.

Further, in CAC-OS or CAC-metal oxide, when the conductive region and the insulating region are dispersed in the material in a size of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively. There is.

Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide gap due to an insulating region and a component having a narrow gap due to a conductive region. In the case of this configuration, when the carrier is flown, the carrier mainly flows in the component having a narrow gap. Further, the component having a narrow gap acts complementarily to the component having a wide gap, and the carrier flows to the component having a wide gap in conjunction with the component having a narrow gap. Therefore, when the CAC-OS or CAC-metal oxide is used in the channel forming region of the transistor, a high current driving force, that is, a large on-current and a high field effect mobility can be obtained in the on state of the transistor.

That is, the CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

The CAC-OS is, for example, a composition of a material in which the elements constituting the metal oxide are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or a size in the vicinity thereof. The state of being mixed in is also called a mosaic shape or a patch shape.

The metal oxide preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, berylium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.

For example, CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide may be particularly referred to as CAC-IGZO in CAC-OS) is an indium oxide (hereinafter, InO _X1 ). (X1 is a real number greater than 0), or indium zinc oxide (hereinafter, In _X2 Zn _Y2 O _Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide ( Hereinafter, GaO _X3 (X3 is a real number larger than 0), or gallium zinc oxide (hereinafter, Ga _X4 Zn _Y4 O _Z4 (X4, Y4, and Z4 are real numbers larger than 0)) and the like. The material is separated into a mosaic-like structure, and the mosaic-like InO _X1 or In _X2 Zn _{Y2 OZ2} is uniformly distributed in the film (hereinafter, also referred to as cloud-like).

That is, CAC-OS is a composite metal oxide having a structure in which a region containing GaO _X3 as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component are mixed. In the present specification, for example, the atomic number ratio of In to the element M in the first region is larger than the atomic number ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the region 2.

In addition, IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO ₃ (ZnO) _m1 (m1 is a natural number) or In _{(1 + x0)} Ga _(1-x0) O ₃ (ZnO) _m0 (-1≤x0≤1, m0 is an arbitrary number). Crystalline compounds can be mentioned.

The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystalline) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without being oriented on the ab plane.

On the other hand, CAC-OS relates to the material composition of the metal oxide. CAC-OS is a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

The CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.

In some cases, a clear boundary cannot be observed between the region containing GaO _X3 as the main component and the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as the main component.

Instead of gallium, choose from aluminum, ittrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium. When one or more of these species are contained, CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component. The regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.

The CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated. When the CAC-OS is formed by the sputtering method, one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good. Further, the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..

CAC-OS is characterized by the fact that no clear peak is observed when measured using the θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction, it can be seen that the orientation of the measurement region in the ab plane direction and the c-axis direction is not observed.

Further, CAC-OS has a ring-shaped high-luminance region and a plurality of bright spots in the ring region in an electron beam diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm. Is observed. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.

Further, for example, in CAC-OS in In-Ga-Zn oxide, a region containing GaO _X3 as a main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). And, it can be confirmed that In _X2 Zn _Y2 O _Z2 or a region containing InO _X1 as a main component is unevenly distributed and has a mixed structure.

CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO _X3 or the like as a main component and a region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.

Here, the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component is a region having higher conductivity than the region in which GaO _X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component. Therefore, a high field effect mobility (μ) can be realized by distributing the region containing In _X2 Zn _Y2 O _Z2 or InO _X1 as a main component in the oxide semiconductor in a cloud shape.

On the other hand, the region in which GaO _X3 or the like is the main component is a region having higher insulating properties than the region in which In _X2 Zn _Y2 O _Z2 or InO _X1 is the main component. That is, since the region containing GaO _X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.

Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO _X3 and the like and the conductivity caused by In _X2 Zn _Y2 O _Z2 or InO _X1 act in a complementary manner, so that the insulation is high. _On current (Ion) and high field effect mobility (μ) can be achieved.

Further, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices.

It should be noted that this embodiment can be appropriately combined with other embodiments described in the present specification.

C4: Capacitive element, C6: Capacitive element, C11: Capacitive element, C12: Capacitive element, C13: Capacitive element, CS1: Capacitive element, DL_Y: Source line, DL_1: Source line, DLa1: Source line, DLa2: Source line, DLb1: source line, DLb2: source line, GL_X: gate line, GL_1: gate line, GL_2: gate line, LOAD1: signal, LOAD2: signal, NW1: transistor, SAVE1: signal, SAVE2: signal, T01: time, T1 : Transistor, T02: Time, T2: Transistor, T03: Time, T04: Time, T05: Time, T06: Time, T6: Transistor, T07: Time, T08: Time, T09: Time, T10: Time, T11: Time , T12: Time, T13: Time, T14: Time, T15: Time, T16: Time, Tr21: Transistor, Tr22: Transistor, Tr24: Transistor, Tr25: Transistor, Tr26: Transistor, Tr27: Transistor, Tr28: Transistor, Tr29 : Transistor, Tr30: Transistor, Tr31: Transistor, 10: Pixel, 11: Storage circuit, 12: Reference storage circuit, 13: Circuit, 14: Circuit, 15: Current source circuit, 17: Holding circuit, 18: Selector, 19: Flip flop circuit, 20: Inverter, 21: Inverter, 22: Inverter, 23: Inverter, 24: Inverter, 25: Inverter, 27: Analog switch, 28: Analog switch, 31: Inverter, 32: Inverter, 33: Inverter, 34: Clocked transistor, 35: Analog switch, 36: Buffer, 60: Display unit, 61: Pixel array, 62: Gate driver, 63: Gate driver, 64: Source driver IC, 70: Touch sensor unit, 71 : Sensor array, 72: Peripheral circuit, 73: TS driver, 74: Sense circuit, 75: Controller IC, 80: Display device, 90: Application processor, 100: Display system, 107: Semiconductor device, 143: Optical sensor, 145 : Optical, 150: Interface, 151: Frame memory, 152: Decoder, 153: Sensor controller, 154: Controller, 155: Clock generation circuit, 160: Image processing unit, 161: Gamma correction circuit, 162: Dimming circuit, 163 : Toning circuit, 164: EL correction circuit, 170: Memory, 173: Timing controller, 175: Register, 175A: Scan chain register unit, 175B: Register unit, 184: Touch sensor controller, 190: Area, 202: Control unit, 203: Cellular array, 204: Sense amplifier circuit, 205: Driver, 206: Main amplifier, 207: Input / output Circuit, 208: Peripheral circuit, 209: Memory cell, 230: Register, 231: Volatile register, 270: Circuit, 271: Circuit, 272: Circuit, 273: Circuit, 274: Circuit, 501: Pixel circuit, 502: Pixel Unit, 504: Drive circuit unit, 504a: Gate driver, 504b: Source driver, 506: Protection circuit, 507: Terminal unit, 550: Transistor, 552: Transistor, 554: Transistor, 560: Capacitive element, 562: Capacitive element, 570: liquid crystal element, 572: light emitting element, 700: display unit, 700A: display unit, 701: substrate, 702: pixel unit, 704: source driver circuit unit, 705: substrate, 706: gate driver circuit unit, 708: FPC Terminal part, 710: Signal line, 711: Wiring part, 712: Sealing material, 716: FPC, 721: Source driver IC, 722: Gate driver circuit, 723: FPC, 724: Printed board, 730: Insulation film, 732: Sealing film, 734: Insulating film, 736: Colored film, 738: Light-shielding film, 750: Transistor, 752: Transistor, 760: Connection electrode, 770: Flattening insulating film, 772: Conductive film, 773: Insulating film, 774 : Conductive, 775: Liquid crystal element, 776: Liquid crystal layer, 778: Structure, 780: Anisotropic conductive film, 782: Light emitting element, 786: EL layer, 788: Conductive, 790: Capacitive element, 791: Touch Sensor, 792: Insulation film, 793: Electrode, 794: Electrode, 795: Insulation film, 796: Electrode, 797: Insulation film, 1800: Mobile information terminal, 1801: Housing, 1802: Housing, 1803: Display unit, 1804: Display unit, 1805: Hinge unit, 1810: Mobile information terminal, 1811: Housing, 1812: Display unit, 1813: Operation button, 1814: External connection port, 1815: Speaker, 1816: Microphone, 1817: Camera, 1820 : Camera, 1821: Housing, 1822: Display, 1823: Operation button, 1824: Shutter button, 1826: Lens, 1830: Television device, 1831: Display, 1832: Housing, 1833: Speaker, 1834: Remote control Operation machine, 1840: Digital signage, 1841: Display Unit, 1842: Pillar, 1850: Personal computer, 1851: Display unit, 1852: Housing, 1851: Touch pad, 1854: Connection port, 1855: Input key, 1900: Electronic device, 1901a: Housing, 1901b: Housing 1902a: Display unit, 1902b: Display unit, 1903: Hinge, 1910: Electronic device, 1911a: Housing, 1911b: Housing, 1912a: Display unit, 1912b: Display unit, 1913: Hinge, 1914a: Operation button, 1914b : Operation button, 1915: Cartridge, 1920: Electronic device, 1921a: Housing, 1921b: Housing, 1922: Display, 1923: Hinge

Claims (7)

With the application processor
With a display device,
The display device includes a controller, a display unit, and a touch sensor unit.
The application processor outputs image data and control signals to the controller.
The controller outputs the touch information detected by the touch sensor unit to the application processor, and outputs the touch information to the application processor.
The application processor generates a first signal indicating the frame frequency of the display unit from the image data and the touch information.
The first signal is one of the control signals.
The controller has a frame memory, an image processing unit, and a register.
The frame memory has a function of storing the image data, and has a function of storing the image data.
The image processing unit has a function of processing the image data, and has a function of processing the image data.
The register has a function of storing parameters for the image processing unit to perform processing.
The frame memory has a function of holding the image data in a state where the power supply to the frame memory is cut off.
The register has a function of holding the parameter while the power supply to the register is cut off.
The application processor generates a third signal from the image data and the touch information to temporarily cut off the power supply to the frame memory, the image processing unit, and the register.
The third signal is one of the control signals.
The register has a volatile register and a holding circuit.
The holding circuit has a function of storing the data of the volatile register.
The volatile register has a function of reading data stored in the holding circuit.
The holding circuit has a function of holding the stored data in a state where the power supply to the register is cut off.
The application processor has a neural network and
The neural network predicts the timing at which the power supply to the register can be cut off from the image data and the touch information, and outputs a fourth signal indicating the timing at which the holding circuit stores the data of the volatile register. Generate and
After the instruction, the information on whether or not the power supply is cut off is learned as teacher data, and the parameters of the neural network are adjusted so as to increase the success probability of cutting off the power supply.
The fourth signal is one of the control signals, a display system. In claim 1,
The display unit has a gate driver and a source driver.
The application processor generates a second signal from the image data and the touch information to temporarily stop the operation of either or both of the gate driver and the source driver.
A display system, characterized in that the second signal is one of the control signals. In claim 1 or 2 ,
The display system, characterized in that the fourth signal is output at the timing when the application processor outputs the image data to the controller. In any one of claims 1 to 3,
The neural network is a display system having a product-sum calculation circuit using an analog memory. In claim 4,
The transistor constituting the analog memory is a display system containing a metal oxide in a channel forming region. In claim 1,
The display unit is a display system having a transistor containing a metal oxide in a channel forming region. In claim 1,
The controller is a display system having a transistor containing a metal oxide in a channel forming region.

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