WO2018158651A1 - Display panel, display device, input/output device, and information processing device - Google Patents

Display panel, display device, input/output device, and information processing device Download PDF

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Publication number
WO2018158651A1
WO2018158651A1 PCT/IB2018/051017 IB2018051017W WO2018158651A1 WO 2018158651 A1 WO2018158651 A1 WO 2018158651A1 IB 2018051017 W IB2018051017 W IB 2018051017W WO 2018158651 A1 WO2018158651 A1 WO 2018158651A1
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WIPO (PCT)
Prior art keywords
transistor
semiconductor
display
circuit
display panel
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PCT/IB2018/051017
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French (fr)
Japanese (ja)
Inventor
山崎舜平
高橋圭
Original Assignee
株式会社半導体エネルギー研究所
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Publication of WO2018158651A1 publication Critical patent/WO2018158651A1/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09FDISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00Electroluminescent light sources
    • H05B33/12Light sources with substantially two-dimensional radiating surfaces
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05BELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B33/00Electroluminescent light sources
    • H05B33/12Light sources with substantially two-dimensional radiating surfaces
    • H05B33/14Light sources with substantially two-dimensional radiating surfaces characterised by the chemical or physical composition or the arrangement of the electroluminescent material, or by the simultaneous addition of the electroluminescent material in or onto the light source
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/131Interconnections, e.g. wiring lines or terminals

Definitions

  • One embodiment of the present invention relates to a display panel, a display device, an input / output device, or an information processing device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, as a technical field of one embodiment of the present invention disclosed more specifically in this specification, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof, Can be cited as an example.
  • Display devices tend to have higher performance such as multi-gradation and higher definition.
  • an IC Integrated Circuit; hereinafter also referred to as a driver IC
  • a driver IC is employed for a drive circuit of a display device, particularly a source driver.
  • the driver IC has a gradation voltage generation circuit for generating an analog signal to be supplied to the pixel.
  • This gradation voltage generation circuit is a so-called D / A conversion circuit that generates an analog signal based on a digital signal.
  • the D / A converter circuit adopts a so-called R-DAC (Resistor digital-to-analog converter) that uses a resistor provided in series in consideration of the fact that a high response speed is required.
  • R-DAC Resistor digital-to-analog converter
  • the number of switches exponentially increases as the number of bits of a digital signal increases, so that the circuit area of the driver IC increases.
  • Patent Documents 1 to 3 propose a configuration in which a desired analog signal is obtained by separately converting a digital signal into upper bits and lower bits and synthesizing respective analog signals.
  • An object of one embodiment of the present invention is to provide a novel display panel that is highly convenient or reliable. Another object is to provide a novel display device that is highly convenient or reliable. Another object is to provide a novel input / output device that is highly convenient or reliable. Another object is to provide a novel information processing device that is highly convenient or reliable. Another object is to provide a novel display panel, a novel display device, a novel input / output device, a novel information processing device, or a novel semiconductor device.
  • One embodiment of the present invention is a display panel including a buffer amplifier and a display region.
  • the buffer amplifier includes a first transistor and a second transistor.
  • the display area includes signal lines and pixels.
  • the pixel includes a pixel circuit, and the pixel circuit includes a third transistor.
  • the signal line is electrically connected to one of the source electrode and the drain electrode of the first transistor, the signal line is electrically connected to one of the source electrode and the drain electrode of the second transistor, and the signal line is connected to the third transistor It is electrically connected to one of a source electrode and a drain electrode of the transistor.
  • the first transistor includes a first semiconductor
  • the second transistor includes a second semiconductor
  • the third transistor includes a third semiconductor.
  • the third semiconductor includes an element contained in the second semiconductor.
  • a current for charging the signal line can be supplied using the first transistor.
  • the signal line can be discharged using the second transistor.
  • heat generated when the signal line is charged or discharged from the signal line can be efficiently radiated.
  • an increase in the temperature of the buffer amplifier can be suppressed.
  • the second transistor in the step of forming the third transistor used for the pixel circuit, the second transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
  • Another embodiment of the present invention is the above display panel in which the first semiconductor includes single crystal silicon and the second semiconductor includes a metal oxide.
  • the drive capability of the first transistor can be increased.
  • the breakdown voltage of the second transistor can be increased.
  • the current flowing through the second transistor can be increased.
  • the second transistor can be kept away from the first transistor.
  • the first transistor and the second transistor serving as heat sources can be separated from each other.
  • heat generated by the second transistor can be radiated to the wiring or the like.
  • an increase in temperature of the single crystal silicon substrate over which the first transistor is formed can be suppressed. As a result, a novel display panel that is highly convenient or reliable can be provided.
  • One embodiment of the present invention is the above display panel including a semiconductor device.
  • the semiconductor device includes a digital-analog conversion circuit, the semiconductor device includes a first terminal, a second terminal, and a third terminal, and the semiconductor device includes a first transistor.
  • the first terminal is electrically connected to the digital / analog conversion circuit.
  • the second terminal is electrically connected to the source electrode or the drain electrode of the first transistor, and the second terminal is electrically connected to the signal line.
  • the third terminal is electrically connected to the gate electrode of the second transistor.
  • an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to one signal line.
  • the first transistor can be formed.
  • One embodiment of the present invention is a display panel including a display region and a digital-analog conversion circuit.
  • the display region includes a pixel and a signal line, the pixel includes a pixel circuit, and the pixel circuit includes a third transistor.
  • the signal line is electrically connected to one of the source electrode and the drain electrode of the third transistor.
  • the third transistor includes a third semiconductor, and the third semiconductor includes a metal oxide.
  • the digital-analog conversion circuit is supplied with a parallel signal, and the digital-analog conversion circuit supplies an analog signal.
  • the digital-analog conversion circuit includes a pass transistor / logic circuit and a resistor string.
  • the resistor string is electrically connected to the pass transistor logic circuit, and the pass transistor logic circuit includes a fourth transistor.
  • the signal line is electrically connected to one of the source electrode and the drain electrode of the fourth transistor.
  • the fourth transistor includes a fourth semiconductor, and the fourth semiconductor includes an element contained in the third semiconductor.
  • an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to a pixel electrically connected to the signal line.
  • a transistor having the same semiconductor as that of a pixel transistor can be used for the pass transistor / logic circuit of the digital-analog converter circuit.
  • part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit.
  • One embodiment of the present invention is the above display panel including a shift register and a latch circuit.
  • the latch circuit is electrically connected to the shift register.
  • the pass transistor logic circuit is electrically connected to the latch circuit.
  • the shift register includes only n-type transistors, and the latch circuit includes only n-type transistors.
  • a digital-analog conversion circuit and a pixel circuit can be configured using only n-type transistors.
  • a transistor including the same semiconductor as a semiconductor included in a pixel transistor can be used for the digital-analog conversion circuit.
  • part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit.
  • the manufacturing process of the digital-analog converter circuit can be simplified. As a result, a novel display panel that is highly convenient or reliable can be provided.
  • One embodiment of the present invention is the above display panel in which a display region includes a group of a plurality of pixels, another group of a plurality of pixels, and a scan line.
  • the group of the plurality of pixels is arranged in the row direction, and the group of the plurality of pixels includes the pixel.
  • Another group of the plurality of pixels is arranged in the column direction intersecting the row direction.
  • the scan line is electrically connected to a group of a plurality of pixels.
  • the signal line is electrically connected to another group of a plurality of pixels.
  • an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to the other group of pixels.
  • a novel display panel that is highly convenient or reliable can be provided.
  • One embodiment of the present invention is the above display panel in which the display region includes a plurality of pixels in a matrix.
  • the display area includes 7600 or more pixels in the row direction, and the display area includes 4300 or more pixels in the column direction.
  • an image signal in which deterioration is suppressed can be supplied to pixels having a larger number than a high-vision image or a 4K image.
  • the image signal can be supplied to the pixels at high speed while suppressing the deterioration of the image signal.
  • a high-definition image can be displayed.
  • display can be performed at a refresh rate of 60 Hz or higher, preferably 120 Hz or higher.
  • One embodiment of the present invention is the above display panel in which a display region includes a first pixel, a second pixel, and a third pixel.
  • the first pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of greater than 0.680 and less than or equal to 0.720, and a chromaticity y of 0.260 or more and 0.320 or less.
  • the second pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of 0.130 or more and 0.250 or less and a chromaticity y of greater than 0.710 and 0.810 or less.
  • the third pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of 0.120 or more and 0.170 or less and a chromaticity y of 0.020 or more and less than 0.060.
  • One embodiment of the present invention is a display device including the display panel and a control unit.
  • the control unit is supplied with image information and control information, the control unit generates information based on the image information, and the control unit supplies the information.
  • the information includes gradations of 12 bits or more.
  • the display panel is supplied with information.
  • the scanning line is supplied with a selection signal at a frequency of 60 Hz or more.
  • the display element displays based on the information.
  • One embodiment of the present invention is an input / output device including an input portion and a display portion.
  • the display unit includes the display panel.
  • the input unit includes a detection region, and the input unit detects an object close to the detection region.
  • the detection area includes an area that overlaps with the pixel.
  • position information can be input using a finger or the like that is brought close to the display portion as a pointer.
  • the position information can be associated with image information displayed on the display unit.
  • One embodiment of the present invention includes one or more of a keyboard, a hardware button, a pointing device, a touch sensor, an illuminance sensor, an imaging device, a voice input device, a line-of-sight input device, and a posture detection device, And an information processing apparatus including a display panel.
  • image information or control information can be generated by the arithmetic device.
  • a novel information processing apparatus that is highly convenient or reliable can be provided.
  • the terms “source” and “drain” of a transistor interchange with each other depending on the polarity of the transistor or the level of potential applied to each terminal.
  • a terminal to which a low potential is applied is called a source
  • a terminal to which a high potential is applied is called a drain
  • a terminal to which a high potential is applied is called a source.
  • the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .
  • the source of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode connected to the semiconductor film.
  • a drain of a transistor means a drain region that is part of the semiconductor film or a drain electrode connected to the semiconductor film.
  • the gate means a gate electrode.
  • the state where the transistors are connected in series means, for example, a state where only one of the source and the drain of the first transistor is connected to only one of the source and the drain of the second transistor.
  • the state where the transistors are connected in parallel means that one of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor, and the other of the source and the drain of the first transistor is connected. It means a state of being connected to the other of the source and the drain of the second transistor.
  • connection means an electrical connection, and corresponds to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily indicate a directly connected state, and a wiring, a resistor, a diode, a transistor, or the like is provided so that current, voltage, or potential can be supplied or transmitted.
  • the state of being indirectly connected through a circuit element is also included in the category.
  • connection includes a case where one conductive film has functions of a plurality of components.
  • one of a first electrode and a second electrode of a transistor refers to a source electrode, and the other refers to a drain electrode.
  • a novel display panel that is highly convenient or reliable can be provided.
  • a novel display device that is highly convenient or reliable can be provided.
  • a novel input / output device that is highly convenient or reliable can be provided.
  • a novel information processing device that is highly convenient or reliable can be provided.
  • a novel display panel, a novel display device, a novel input / output device, a novel information processing device, or a novel semiconductor device can be provided.
  • FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment. 4A and 4B illustrate a structure of a display panel according to Embodiment.
  • FIG. 6 is a circuit diagram illustrating a structure of a buffer amplifier that can be used for the display panel according to Embodiment;
  • FIG. 6 is a top view illustrating a structure of a display panel according to Embodiment.
  • FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment.
  • 10A and 10B are a cross-sectional view and a circuit diagram illustrating a structure of a display panel according to an embodiment.
  • 4 is a cross-sectional view illustrating a structure of a display panel according to Embodiment.
  • FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment.
  • 4A and 4B illustrate a structure of a display panel according to Embodiment.
  • FIG. 6 is
  • FIGS. 10A and 10B are a cross-sectional view and a circuit diagram illustrating a structure of a display panel according to an embodiment.
  • 4 is a cross-sectional view illustrating a structure of a display panel according to Embodiment.
  • FIG. 4A and 4B illustrate a display device according to an embodiment.
  • FIG. 3 is a block diagram illustrating a structure of an input / output device according to an embodiment.
  • FIG. 2 is a block diagram and a projection view illustrating a configuration of an information processing device according to an embodiment.
  • FIG. 6 is a flowchart illustrating a method for driving the information processing apparatus according to the embodiment.
  • 6A and 6B are a flowchart and a timing chart illustrating a method for driving an information processing apparatus according to an embodiment.
  • FIG. 2A and 2B illustrate a structure of an information processing device according to an embodiment.
  • 2A and 2B illustrate a structure of an information processing device according to an embodiment.
  • FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment.
  • 4A and 4B are a block diagram and a circuit diagram illustrating a structure of a display panel according to Embodiment;
  • One embodiment of the present invention is a display panel including a buffer amplifier and a display region.
  • the buffer amplifier includes a first transistor and a second transistor, and the display region includes a signal line and a pixel.
  • the pixel includes a pixel circuit, and the pixel circuit includes a third transistor.
  • the signal line is electrically connected to the source electrode or the drain electrode of the first transistor, is electrically connected to the source electrode or the drain electrode of the second transistor, and is connected to the source electrode or the drain electrode of the third transistor. Electrically connected.
  • the first transistor includes a first semiconductor
  • the second transistor includes a second semiconductor
  • the third transistor includes a third semiconductor
  • the third semiconductor includes a second semiconductor. Contains elements contained in semiconductors.
  • a current for charging the signal line can be supplied using the first transistor.
  • the signal line can be discharged using the second transistor.
  • the signal line can be charged or discharged from the signal line.
  • an increase in the temperature of the buffer amplifier can be suppressed.
  • the second transistor in the step of forming the third transistor used for the pixel circuit, the second transistor can be formed.
  • FIG. 1 illustrates a structure of a display panel of one embodiment of the present invention.
  • FIG. 2 illustrates a structure of a display panel of one embodiment of the present invention.
  • a variable having an integer value of 1 or more may be used for the sign.
  • (p) including a variable p that takes an integer value of 1 or more may be used as a part of a code that identifies any of the maximum p components.
  • a variable m that takes an integer value of 1 or more and (m, n) including a variable n may be used as part of a code that identifies any of the maximum m ⁇ n components.
  • a display panel 700 described in this embodiment includes a buffer amplifier BA and a display region 231 (see FIG. 1).
  • the buffer amplifier BA includes a transistor Tr1 and a transistor Tr2 (see FIG. 2).
  • the circuit 11 and the circuit 12 can be used for the buffer amplifier BA.
  • CMOS circuit including the transistor Tr1 and the transistor Tr2 can be used for the circuit 12.
  • a differential amplifier circuit can be used for the circuit 11.
  • the circuit illustrated in FIG. 3 can be used for the circuit 11.
  • wirings for supplying a predetermined bias voltage can be used for the wirings VB1 to VB6.
  • the display area 231 includes a signal line S1 (j) and a pixel 702 (i, j) (see FIG. 1).
  • the pixel 702 (i, j) includes a pixel circuit 530 (i, j), and the pixel circuit 530 (i, j) includes a transistor Tr3 (see FIG. 2).
  • the signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr1.
  • the signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr2.
  • the wiring Vdd is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr1.
  • the wiring Vss is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr2. Note that the wiring Vdd has a function of supplying a higher potential than the potential supplied by the wiring Vss.
  • the signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr3.
  • the transistor Tr1 includes a first semiconductor
  • the transistor Tr2 includes a second semiconductor
  • the transistor Tr3 includes a third semiconductor.
  • the third semiconductor includes an element contained in the second semiconductor.
  • a semiconductor formed over a substrate over which the second semiconductor is formed can be used for the third semiconductor.
  • a semiconductor that can be formed in the step of forming the second semiconductor can be used for the third semiconductor.
  • a current for charging the signal line can be supplied using the first transistor.
  • the signal line can be discharged using the second transistor.
  • heat generated when the signal line is charged or discharged from the signal line can be efficiently radiated.
  • an increase in the temperature of the buffer amplifier can be suppressed.
  • the second transistor in the step of forming the third transistor used for the pixel circuit, the second transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
  • the first semiconductor described in this embodiment includes single crystal silicon
  • the second semiconductor includes a metal oxide.
  • a single crystal silicon substrate can be used for the first semiconductor.
  • a semiconductor film formed over an insulating substrate can be used for the second semiconductor.
  • an insulating material containing glass or resin can be used for the insulating substrate.
  • the drive capability of the first transistor can be increased.
  • the breakdown voltage of the second transistor can be increased.
  • the current flowing through the second transistor can be increased.
  • the second transistor can be kept away from the first transistor.
  • the first transistor and the second transistor serving as heat sources can be separated from each other.
  • heat generated by the second transistor can be radiated to the wiring or the like.
  • an increase in temperature of the single crystal silicon substrate over which the first transistor is formed can be suppressed. As a result, a novel display panel that is highly convenient or reliable can be provided.
  • a display panel 700 described in this embodiment includes a driver circuit SD (1) (see FIG. 1).
  • the drive circuit SD (1) has a function of supplying an image signal based on the information V11.
  • the driver circuit SD (1) has a function of generating an image signal and a function of supplying the image signal to a pixel circuit that is electrically connected to one display element.
  • a digital operation unit (Digital Block) can be used for the drive circuit SD (1).
  • the digital arithmetic unit has a function of converting serial data into parallel data, for example.
  • various sequential circuits such as a shift register can be used for the digital arithmetic unit.
  • an integrated circuit formed over a silicon substrate can be used for the drive circuit SD (1).
  • the following semiconductor device can be used for the drive circuit SD (1).
  • the semiconductor device includes a digital-analog conversion circuit DAC (1) (see FIG. 1).
  • the semiconductor device includes a first terminal Tm11, a second terminal Tm12, and a third terminal Tm13.
  • the semiconductor device includes a transistor Tr1 (see FIG. 2).
  • the first terminal Tm11 is electrically connected to the digital / analog conversion circuit DAC (1) (see FIG. 1).
  • the second terminal Tm12 is electrically connected to the source electrode or the drain electrode of the transistor Tr1, and the second terminal Tm12 is electrically connected to the signal line S1 (j) (see FIG. 2).
  • the third terminal Tm13 is electrically connected to the gate electrode of the transistor Tr2.
  • an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to one signal line.
  • the first transistor can be formed.
  • the semiconductor device can be electrically connected to the signal line S1 (j) by using a COG (Chip on glass) method or a COF (Chip on Film) method.
  • the semiconductor device can be electrically connected to the signal line S1 (j) using an anisotropic conductive film.
  • the drive circuit GD has a function of supplying a selection signal based on the control information.
  • a function of supplying a selection signal to one scanning line at a frequency of 30 Hz or higher, preferably 60 Hz or higher is provided based on the control information. Thereby, a moving image can be displayed smoothly.
  • a function of supplying a selection signal to one scanning line at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute based on the control information is provided. Thereby, a still image can be displayed in a state where flicker is suppressed.
  • the frame frequency can be made variable.
  • display can be performed at a frame frequency of 1 Hz to 120 Hz.
  • display can be performed at a frame frequency of 120 Hz using a progressive method.
  • An extremely high-resolution display that satisfies 2020-2 can be performed.
  • extremely high resolution display can be performed.
  • the display region 231 includes a group of a plurality of pixels 702 (i, 1) to 702 (i, n), another group of a plurality of pixels 702 (1, j) to pixels 702 (m, j), and a scanning line G1. (I) is provided (see FIG. 1).
  • a group of the plurality of pixels 702 (i, 1) to 702 (i, n) is arranged in a row direction (a direction indicated by an arrow R1 in the drawing).
  • a group of the plurality of pixels 702 (i, 1) to 702 (i, n) includes the pixel 702 (i, j).
  • Another group of the plurality of pixels 702 (1, j) to 702 (m, j) is arranged in a column direction (direction indicated by an arrow C1 in the drawing) intersecting the row direction.
  • the scan line G1 (i) is electrically connected to a group of the plurality of pixels 702 (i, 1) to 702 (i, n).
  • the signal line S1 (j) is electrically connected to the other group of the plurality of pixels 702 (1, j) to 702 (m, j).
  • an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to the other group of pixels.
  • a novel display panel that is highly convenient or reliable can be provided.
  • the display area 231 includes a plurality of pixels in a matrix.
  • the display area 231 includes 7600 or more pixels in the row direction and 4300 or more pixels in the column direction.
  • 7680 pixels are provided in the row direction
  • 4320 pixels are provided in the column direction.
  • an image signal in which deterioration is suppressed can be supplied to pixels having a larger number than a high-vision image or a 4K image.
  • the image signal can be supplied to the pixels at high speed while suppressing the deterioration of the image signal.
  • a high-definition image can be displayed.
  • display can be performed at a refresh rate of 60 Hz or higher, preferably 120 Hz or higher.
  • a display panel 700 described in this embodiment includes a plurality of pixels.
  • the plurality of pixels have a function of displaying colors having different hues.
  • hue colors that cannot be displayed by the pixels can be displayed by additive color mixing.
  • the display region 231 includes a pixel 702 (i, j), a pixel 702 (i, j + 1), and a pixel 702 (i, j + 2) (see FIGS. 4A and 4C).
  • the pixel 702 (i, j) displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of greater than 0.680 and less than or equal to 0.720, and a chromaticity y of 0.260 to 0.320.
  • the pixel 702 (i, j + 1) displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of 0.130 or more and 0.250 or less, and a chromaticity y of greater than 0.710 and 0.810 or less.
  • the pixel 702 (i, j + 2) displays a color having a chromaticity x of 0.120 to 0.170 and a chromaticity y of 0.020 to less than 0.060 in the CIE 1931 chromaticity coordinates.
  • each pixel can be referred to as a sub-pixel.
  • a plurality of sub-pixels can be referred to as a pixel.
  • the pixel 702 (i, j), the pixel 702 (i, j + 1), or the pixel 702 (i, j + 2) can be rephrased as a sub-pixel, and the pixel 702 (i, j), the pixel 702 (i, j + 1), and The pixel 702 (i, j + 2) can be referred to as a pixel 703 (i, k) as a set (see FIG. 4C).
  • a set of a subpixel that displays blue, a subpixel that displays green, and a subpixel that displays red can be used for the pixel 703 (i, k).
  • a sub-pixel for displaying cyan, a sub-pixel for displaying magenta, and a sub-pixel for displaying yellow can be used as a set for the pixel 703 (i, k).
  • a sub-pixel for displaying white can be used for the pixel in addition to the above set.
  • the pixel 702 (i, j), the pixel 702 (i, j + 1), and the pixel 702 (i, j + 2) are represented by BT.
  • the area ratio to the 2020 color gamut is 80% or more, or the coverage ratio to the color gamut is 75% or more.
  • the area ratio is 90% or more, or the coverage is 85% or more.
  • the display panel can include a plurality of driver circuits.
  • the display panel 700 includes a drive circuit GDA and a drive circuit GDB (see FIG. 5).
  • a digital operation unit Digital Block
  • the drive circuit SD (1) can be used for the drive circuit SD (1).
  • the frequency with which the drive circuit GDA supplies the selection signal and the frequency with which the drive circuit GDB supplies the selection signal can be made different.
  • the selection signal can be supplied to another region displaying the moving image at a frequency higher than the frequency of supplying the selection signal to one region displaying the still image.
  • FIG. 4A is a top view illustrating a structure of a display panel of one embodiment of the present invention
  • FIG. 4B is a top view illustrating part of FIG. 4A.
  • FIG. ) Is a top view illustrating another part.
  • FIG. 6A is a cross-sectional view taken along cutting lines X1-X2, X3-X4, and X9-X10 in FIG. 4A
  • FIG. 6B is a circuit diagram illustrating a pixel circuit. is there.
  • FIG. 7 is a cross-sectional view illustrating the structure of a display panel of one embodiment of the present invention.
  • FIG. 7A is a cross-sectional view illustrating a structure of a pixel
  • FIG. 7B is a cross-sectional view illustrating a part of FIG.
  • FIG. 7C is a cross-sectional view illustrating a structure of a transistor that can be used in the buffer amplifier BA illustrated in FIG.
  • the display panel 700 includes a driver circuit SD (1), a driver circuit GD, and a terminal 519B (see FIG. 4A).
  • the display panel 700 includes a substrate 510, a substrate 770, a functional layer 520, and an insulating film 501C (see FIG. 7A).
  • the display panel 700 includes a functional layer 720, a functional film 770P, and a functional film 770D.
  • the display panel 700 includes a buffer amplifier BA (see FIG. 2).
  • the buffer amplifier BA includes a transistor Tr2 over the insulating film 501C (see FIG. 7C).
  • the insulating film 501C includes a region sandwiched between the substrate 510 and the substrate 770, and the functional layer 520 includes a region sandwiched between the insulating film 501C and the substrate 770.
  • the pixel 702 (i, j) includes a functional layer 520 and a display element 750 (i, j) (see FIG. 6A).
  • the functional layer 520 includes a pixel circuit 530 (i, j), an insulating film 521A, and an insulating film 521B (see FIGS. 6A and 7A).
  • ⁇ Configuration Example 1 of Pixel Circuit 530 (i, j) For example, a switch, a transistor, a diode, a resistor, an inductor, a capacitor, or the like can be used for the pixel circuit 530 (i, j).
  • the pixel circuit 530 (i, j) has a function of driving the display element 750 (i, j).
  • the pixel circuit illustrated in FIG. 6B has a function of driving a liquid crystal display element.
  • Pixel circuit 530 (i, j) includes a switch SW1 and a capacitor C11.
  • a transistor can be used for the switch SW1 (see FIGS. 6B, 7A, and 7B).
  • the transistor includes a semiconductor film 508, a conductive film 504, a conductive film 512A, and a conductive film 512B (see FIG. 7B).
  • the semiconductor film 508 includes a region 508A electrically connected to the conductive film 512A and a region 508B electrically connected to the conductive film 512B.
  • the semiconductor film 508 includes a region 508C between the region 508A and the region 508B.
  • the conductive film 504 includes a region overlapping with the region 508C, and the conductive film 504 functions as a gate electrode.
  • the insulating film 506 includes a region sandwiched between the semiconductor film 508 and the conductive film 504.
  • the insulating film 506 has a function of a gate insulating film.
  • the conductive film 512A has one of the function of the source electrode and the function of the drain electrode, and the conductive film 512B has the other of the function of the source electrode and the function of the drain electrode.
  • a semiconductor film that can be formed in the same step can be used for a driver circuit and a transistor of a pixel circuit.
  • a bottom-gate transistor, a top-gate transistor, or the like can be used for a driver circuit transistor, a buffer amplifier BA transistor, or a pixel circuit transistor.
  • a transistor of a type included in the transistor Tr3 included in the pixel circuit 530 (i, j) can be used as the transistor Tr2.
  • a semiconductor containing a Group 14 element can be used for the semiconductor film 508.
  • a semiconductor containing silicon can be used for the semiconductor film 508.
  • single crystal silicon, polysilicon, microcrystalline silicon, amorphous silicon, or the like can be used for the semiconductor film.
  • the temperature required for manufacturing a transistor using polysilicon as a semiconductor is lower than that of a transistor using single crystal silicon as a semiconductor.
  • the field effect mobility of a transistor using polysilicon as a semiconductor is higher than that of a transistor using amorphous silicon as a semiconductor.
  • the aperture ratio of the pixel can be improved.
  • a pixel provided with extremely high definition, a gate driver circuit, and a source driver circuit can be formed over the same substrate. As a result, the number of parts constituting the electronic device can be reduced.
  • the reliability of a transistor using polysilicon as a semiconductor is superior to a transistor using amorphous silicon as a semiconductor.
  • a transistor using a compound semiconductor can be used.
  • a semiconductor containing gallium arsenide can be used for the semiconductor film.
  • a transistor using an organic semiconductor can be used.
  • an organic semiconductor containing polyacenes or graphene can be used for the semiconductor film.
  • a transistor including an oxide semiconductor can be used.
  • an oxide semiconductor containing indium or an oxide semiconductor containing indium, gallium, and zinc can be used for the semiconductor film.
  • a transistor whose leakage current in an off state is smaller than that of a transistor using amorphous silicon as a semiconductor film can be used.
  • a transistor in which an oxide semiconductor is used for a semiconductor film can be used.
  • the time during which the pixel circuit can hold an image signal can be lengthened.
  • the selection signal can be supplied at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute while suppressing the occurrence of flicker.
  • fatigue accumulated in the user of the information processing apparatus can be reduced.
  • power consumption associated with driving can be reduced.
  • a 25-nm-thick film containing indium, gallium, and zinc can be used for the semiconductor film 508.
  • a conductive film in which a 10-nm-thick film containing tantalum and nitrogen and a 300-nm-thick film containing copper are stacked can be used for the conductive film 504.
  • the film containing copper includes a region between which the film containing tantalum and nitrogen is sandwiched between the film containing copper.
  • a stacked film in which a 400-nm-thick film containing silicon and nitrogen and a 200-nm-thick film containing silicon, oxygen, and nitrogen are stacked can be used for the insulating film 506.
  • the film containing silicon and nitrogen includes a region between the semiconductor film 508 and the film containing silicon, oxygen, and nitrogen.
  • the film containing tungsten includes a region in contact with the semiconductor film 508.
  • a bottom-gate transistor production line using amorphous silicon as a semiconductor can be easily modified to a bottom-gate transistor production line using an oxide semiconductor as a semiconductor.
  • a top gate transistor production line using polysilicon as a semiconductor can be easily modified to a top gate transistor production line using an oxide semiconductor as a semiconductor. Both modifications can make effective use of existing production lines.
  • the display element 750 (i, j) includes a region overlapping with the functional layer 520 (see FIGS. 6A and 7A). In addition, the display element 750 (i, j) is electrically connected to the pixel circuit 530 (i, j).
  • a display element having a function of controlling reflection or transmission of light can be used for the display element 750 (i, j).
  • a configuration in which a liquid crystal element and a polarizing plate are combined, a shutter-type MEMS display element, an optical interference-type MEMS display element, or the like can be used.
  • a display element using a reflective liquid crystal display element, a microcapsule method, an electrophoresis method, an electrowetting method, or the like can be used for the display element 750 (i, j).
  • a reflective display element By using a reflective display element, power consumption of the display panel can be suppressed.
  • a transmissive liquid crystal display element can be used for the display element 750 (i, j). Further, the display panel 700 has a function of displaying an image by controlling transmission of light emitted from the backlight BL.
  • IPS In-Plane-Switching
  • TN Transmission Nematic
  • FFS Fe Field Switched
  • ASM Analy Symmetrically Applied Micro-cell
  • OCB OpticBridge
  • a liquid crystal element that can be driven using a driving method such as a Crystal) mode or an AFLC (Antiferroelectric Liquid Crystal) mode can be used.
  • VA vertical alignment
  • MVA Multi-Domain Vertical Alignment
  • PVA Plasma Vertical Alignment
  • ECB Electrical Controlled Birefringence ACP mode
  • CPB CPB mode
  • a liquid crystal element that can be driven by a driving method such as an (Advanced Super-View) mode can be used.
  • the display element 750 includes an electrode 751 (i, j), an electrode 752, and a layer 753 containing a liquid crystal material.
  • the electrode 751 (i, j) is electrically connected to the pixel circuit 530 (i, j) at the connection portion 591A.
  • the electrode 752 is disposed so as to form an electric field for controlling the alignment of the liquid crystal material between the electrode 751 (i, j).
  • the display element 750 (i, j) includes an alignment film AF1 and an alignment film AF2.
  • the layer 753 containing a liquid crystal material includes a region sandwiched between the alignment film AF1 and the alignment film AF2.
  • a liquid crystal material having a specific resistivity of 1.0 ⁇ 10 13 ⁇ ⁇ cm or more, preferably 1.0 ⁇ 10 14 ⁇ ⁇ cm or more, more preferably 1.0 ⁇ 10 15 ⁇ ⁇ cm or more is used as the liquid crystal material.
  • the layer 753 containing can be used. Thereby, the fluctuation
  • the structure KB1 has a function of providing a predetermined gap between the functional layer 520 and the substrate 770.
  • the functional layer 720 includes a coloring film CF1, an insulating film 771, and a light shielding film BM.
  • the colored film CF1 includes a region sandwiched between the substrate 770 and the display element 750 (i, j).
  • the light shielding film BM includes an opening in a region overlapping with the pixel 702 (i, j).
  • the insulating film 771 includes a region sandwiched between the colored film CF1 and the layer 753 containing a liquid crystal material or a region sandwiched between the light shielding film BM and the layer 753 containing a liquid crystal material.
  • corrugation based on the thickness of colored film CF1 can be made flat.
  • impurity diffusion from the light-blocking film BM, the coloring film CF1, or the like to the layer 753 containing a liquid crystal material can be suppressed.
  • the functional film 770P includes a region overlapping with the display element 750 (i, j).
  • the functional film 770D includes a region overlapping with the display element 750 (i, j).
  • an antireflection film, a polarizing film, a retardation film, a light diffusion film, a light collecting film, or the like can be used for the functional film 770P or the functional film 770D.
  • a circularly polarizing film can be used for the functional film 770P.
  • a light diffusion film can be used for the functional film 770D.
  • antistatic film that suppresses adhesion of dust
  • water-repellent film that makes it difficult to adhere dirt
  • antireflection film anti-reflection film
  • non-glossy film anti-glare film
  • scratches caused by use A hard coat film or the like that suppresses the above can be used for the functional film 770P.
  • FIG. 4A is a top view illustrating a structure of a display panel of one embodiment of the present invention
  • FIG. 4B is a top view illustrating part of FIG. 4A.
  • FIG. ) Is a top view illustrating another part.
  • FIG. 8A is a cross-sectional view taken along cutting lines X1-X2, X3-X4, and X9-X10 in FIG. 4A
  • FIG. 8B is a circuit diagram illustrating a pixel circuit. is there.
  • FIG. 9 is a cross-sectional view illustrating a structure of a display panel of one embodiment of the present invention.
  • FIG. 9A is a cross-sectional view illustrating a structure of a pixel
  • FIG. 9B is a cross-sectional view illustrating part of FIG. 9A.
  • FIG. 9C is a cross-sectional view illustrating a structure of a transistor that can be used in the buffer amplifier BA illustrated in FIG.
  • the display panel 700 includes a driver circuit SD (1), a driver circuit GD, and a terminal 519B (see FIG. 4A).
  • the display panel 700 includes a substrate 510, a substrate 770, a functional layer 520, and an insulating film 501C (see FIGS. 9A and 9B). In addition, the display panel 700 can include a functional film 770P.
  • the display panel 700 includes a buffer amplifier BA (see FIG. 2).
  • the buffer amplifier BA includes a transistor Tr2 over the insulating film 501C (see FIG. 9C).
  • the insulating film 501C includes a region sandwiched between the substrate 510 and the substrate 770, and the functional layer 520 includes a region sandwiched between the insulating film 501C and the substrate 770.
  • the pixel 702 (i, j) includes a functional layer 520 and a display element 550 (i, j) (see FIG. 8A).
  • the functional layer 520 includes a pixel circuit 530 (i, j), an insulating film 521, an insulating film 528, and a coloring film CF1 (see FIGS. 8A and 9A).
  • a switch, a transistor, a diode, a resistor, an inductor, a capacitor, or the like can be used for the pixel circuit 530 (i, j).
  • the pixel circuit 530 (i, j) has a function of driving the display element 550 (i, j).
  • an organic electroluminescent element can be driven using the pixel circuit illustrated in FIG.
  • the pixel circuit 530 (i, j) includes a transistor M and a capacitor C12 (see FIGS. 8B, 9A, and 9B).
  • the transistor M includes a semiconductor film 508, a conductive film 504, a conductive film 512A, and a conductive film 512B (see FIG. 9B).
  • a transistor including the conductive film 524 can be used for the pixel circuit 530 (i, j).
  • the conductive film 524 includes a region in which the semiconductor film 508 is sandwiched between the conductive film 504 and the conductive film 504.
  • the insulating film 516 includes a region sandwiched between the conductive film 524 and the semiconductor film 508.
  • the conductive film 524 can be electrically connected to a wiring that supplies the same potential as the conductive film 504.
  • the display element 550 (i, j) includes a region overlapping with the functional layer 520 (see FIGS. 8A and 9A).
  • the display element 550 (i, j) is electrically connected to the pixel circuit 530 (i, j).
  • a display element having a function of emitting light can be used for the display element 550 (i, j) (see FIG. 8A).
  • an organic electroluminescent element, an inorganic electroluminescent element, or a light-emitting diode can be used for the display element 550 (i, j).
  • quantum dots can be used for the display element 550 (i, j).
  • QDLED Quadabutum Dot LED
  • the half value width of a spectrum is narrow and can emit the light of a bright color.
  • the display element 550 includes an electrode 551 (i, j), an electrode 552, and a layer 553 (j) containing a light-emitting material.
  • the electrode 551 (i, j) is electrically connected to the pixel circuit 530 (i, j) at the connection portion 591A.
  • the pixel circuit 530 (i, j) is electrically connected to the wiring ANO at the connection portion 591B.
  • a layer containing a light-emitting material such as a laminated material laminated so as to emit blue light, a laminated material laminated so as to emit green light, or a laminated material laminated so as to emit red light. 553 (j).
  • a strip-shaped stacked material that is long in the column direction along the signal line S1 (j) can be used for the layer 553 (j) containing a light-emitting material.
  • a stacked material stacked to emit white light can be used for the display element 550 (i, j).
  • a layer including a light emitting material including a fluorescent material that emits blue light a layer including a material other than a fluorescent material that emits green and red light, or a material other than a fluorescent material that emits yellow light.
  • a stack material in which the layers including the layers are stacked can be used for the display element 550 (i, j).
  • the desiccant 578 includes a region sandwiched between the functional layer 520 and the substrate 770.
  • FIG. 17 illustrates a structure of a display panel of one embodiment of the present invention.
  • FIG. 17A is a block diagram illustrating a structure of a display panel of one embodiment of the present invention
  • FIG. 17B is a circuit diagram illustrating a structure of the pixel illustrated in FIG.
  • FIG. 18A illustrates a structure of the driver circuit SD (1) of the display panel of one embodiment of the present invention
  • FIG. 18B illustrates a structure of the digital-analog converter circuit.
  • a display panel 700 described in this embodiment includes a display region 231 and a digital-analog converter circuit DAC (1) (see FIG. 17A).
  • DAC (1) digital-analog converter circuit
  • a digital operation unit Digital Block
  • Digital Block can be used for the drive circuit SD (1).
  • the display area 231 includes a pixel 702 (i, j) and a signal line S1 (j).
  • the pixel 702 (i, j) includes a pixel circuit 530 (i, j) (see FIG. 17B).
  • the pixel circuit 530 (i, j) includes a transistor Tr3.
  • the signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr3.
  • the transistor Tr3 includes a third semiconductor, and the third semiconductor includes a metal oxide.
  • the metal oxide described in Embodiment 3 can be used.
  • Digital-to-analog converter circuit DAC The digital-analog conversion circuit DAC is supplied with a parallel signal and supplies an analog signal.
  • the digital-analog converter circuit DAC includes a pass transistor / logic circuit PTL and a resistor string R-string (see FIGS. 18A and 18B).
  • the resistor string R-string is electrically connected to the pass transistor logic circuit PTL.
  • the pass transistor / logic circuit PTL includes a transistor Tr4.
  • the signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr4.
  • the transistor Tr4 includes a fourth semiconductor, and the fourth semiconductor includes an element included in the third semiconductor. Note that the transistor Tr4 has a switch function. For example, the resistor string R-string and the signal line S1 (j) are electrically connected based on the signal DATAB_LS [7].
  • an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to a pixel electrically connected to the signal line.
  • a transistor having the same semiconductor as that of a pixel transistor can be used for the pass transistor / logic circuit of the digital-analog converter circuit.
  • part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit.
  • a display panel 700 described in this embodiment includes a shift register SR and a latch circuit LTC (see FIG. 18A).
  • the latch circuit LTC is electrically connected to the shift register SR.
  • a parallel signal can be supplied using the shift register SR and the latch circuit LTC.
  • the pass transistor / logic circuit PTL is electrically connected to the latch circuit LTC.
  • Shift register SR includes only n-type transistors, and the latch circuit includes only n-type transistors.
  • a digital-analog conversion circuit and a pixel circuit can be configured using only n-type transistors.
  • a transistor including the same semiconductor as a semiconductor included in a pixel transistor can be used for the digital-analog conversion circuit.
  • part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit.
  • the manufacturing process of the digital-analog converter circuit can be simplified. As a result, a novel display panel that is highly convenient or reliable can be provided.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • an oxide semiconductor called a semi-crystalline oxide semiconductor can be given.
  • a semicrystalline oxide semiconductor has an intermediate structure between a single crystal oxide semiconductor and an amorphous oxide semiconductor.
  • a semicrystalline oxide semiconductor has a more stable structure than an amorphous oxide semiconductor.
  • a semicrystalline oxide semiconductor there is an oxide semiconductor having a CAAC structure and a CAC (Cloud-Aligned Composite) structure. Details of the CAC will be described below.
  • CAC-OS Cloud-Aligned Composite Oxide Semiconductor
  • non-single-crystal oxide semiconductor or CAC-OS can be preferably used for the semiconductor layer of the transistor disclosed in one embodiment of the present invention.
  • non-single-crystal oxide semiconductor nc-OS or CAAC-OS can be preferably used.
  • a CAC-OS is preferably used as the semiconductor layer of the transistor.
  • the CAC-OS high electrical characteristics or high reliability can be imparted to the transistor.
  • CAC-OS Details of the CAC-OS will be described below.
  • the CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is a carrier. This function prevents electrons from flowing.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be referred to as a matrix composite (metal matrix composite) or a metal matrix composite (metal matrix composite).
  • the CAC-OS is one structure of a material in which an element constituting a metal oxide is unevenly distributed with a size of 0.5 nm to 10 nm, preferably, 1 nm to 2 nm or near.
  • an element constituting a metal oxide is unevenly distributed with a size of 0.5 nm to 10 nm, preferably, 1 nm to 2 nm or near.
  • a metal oxide one or more metal elements are unevenly distributed, and a region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm or near.
  • the mixed state is also called mosaic or patch.
  • the metal oxide preferably contains at least indium.
  • One kind or plural kinds selected from may be included.
  • a CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
  • X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter, click Also called Udo-like.) A.
  • CAC-OS includes a region GaO X3 is the main component, and In X2 Zn Y2 O Z2, or InO X1 is the main component region is a composite metal oxide having a structure that is mixed.
  • the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
  • IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystal) structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
  • CAC-OS relates to a material structure of a metal oxide.
  • CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In.
  • the region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
  • a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
  • a region GaO X3 is the main component, and In X2 Zn Y2 O Z2 or InO X1 is the main component region, in some cases clear boundary can not be observed.
  • the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In.
  • the region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
  • the CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example.
  • a CAC-OS is formed by a sputtering method
  • any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good.
  • the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .
  • the CAC-OS has a feature that a clear peak is not observed when measurement is performed using a ⁇ / 2 ⁇ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
  • XRD X-ray diffraction
  • an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • a region in which GaO X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component is unevenly distributed and mixed.
  • EDX energy dispersive X-ray spectroscopy
  • CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has a property different from that of an IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
  • the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2 or InO X1, is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In X2 Zn Y2 O Z2 or InO X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility ( ⁇ ) can be realized.
  • areas such as GaO X3 is the main component, as compared to the In X2 Zn Y2 O Z2 or InO X1 is the main component area, it is highly regions insulating. That is, a region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in high An on-current (I on ) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-OS is optimal for various semiconductor devices including a display.
  • a transistor using a CAAC-OS or a CAC-OS for a semiconductor film can have a short channel length, can have a large on-state current, can have a very small off-state current, and can suppress variations. And can be manufactured on a large glass substrate of 8th to 10th generation. Thereby, it can use suitably for the backplane of a large sized organic EL television.
  • FIG. 10 illustrates a structure of a display device of one embodiment of the present invention.
  • FIG. 10A is a block diagram of a display device of one embodiment of the present invention
  • FIGS. 10B-1 to 10B-3 are projections illustrating the appearance of the display device of one embodiment of the present invention.
  • FIG. 10A is a block diagram of a display device of one embodiment of the present invention
  • FIGS. 10B-1 to 10B-3 are projections illustrating the appearance of the display device of one embodiment of the present invention.
  • FIG. 10A is a block diagram of a display device of one embodiment of the present invention
  • FIGS. 10B-1 to 10B-3 are projections illustrating the appearance of the display device of one embodiment of the present invention.
  • the display device described in this embodiment includes a control portion 238 and a display panel 700B (see FIG. 10A).
  • the control unit 238 has a function to which the image information V1 and the control information SS are supplied.
  • a clock signal or a timing signal can be used for the control information SS.
  • the control unit 238 has a function of generating information V11 based on the image information V1.
  • the control unit 238 has a function of supplying the information V11.
  • the information V11 includes a gradation of 8 bits or more, preferably 12 bits or more.
  • control unit 238 includes a timing controller 233, an expansion circuit 234, and an image processing circuit 235M.
  • Timing controller 233 sends the control information SS to the drive circuit GDA (1) and the drive circuit GDB (1), the drive circuit GDA (2) and the drive circuit GDB (2), and the drive circuits SD (1) to SD (3).
  • the timing controller 233 can be included in the display panel.
  • the timing controller 233 mounted on a rigid board can be used for a display panel by being electrically connected to a driving circuit using a flexible printed board.
  • the display panel 700B has a function of being supplied with the information V11.
  • the display panel 700B includes a pixel 702 (i, j).
  • the scanning line G1 (i) is supplied with a selection signal at a frequency of 60 Hz or more, preferably 120 Hz or more.
  • the driver circuit GDA (1), the driver circuit GDB (1), the driver circuit GDA (2), and the driver circuit GDB (2) have a function of supplying a selection signal.
  • the pixel 702 (i, j) includes a display element.
  • the display element has a function of displaying based on the information V11.
  • a liquid crystal element can be used for the display element.
  • the display panel described in Embodiment 1 can be used for the display panel 700B.
  • a novel display device that is highly convenient or reliable can be provided.
  • a television receiving system see FIG. 10B-1
  • a video monitor see FIG. 10B-2
  • a notebook computer see FIG. 10B-3
  • the expansion circuit 234 has a function of expanding the image information V1 supplied in a compressed state.
  • the decompression circuit 234 includes a storage unit.
  • the storage unit has a function of storing, for example, decompressed image information.
  • the image processing circuit 235M includes a region, for example.
  • the area has a function of storing information included in the image information V1, for example.
  • the image processing circuit 235M has, for example, a function of correcting the image information V1 based on a predetermined characteristic curve to generate the information V11 and a function of supplying the information V11. Specifically, it has a function of generating information V11 so that the display element displays a good image.
  • FIG. 11 is a block diagram illustrating a structure of the input / output device of one embodiment of the present invention.
  • the input / output device described in this embodiment includes an input unit 240 and a display unit 230 (see FIG. 11).
  • the display panel 700 described in Embodiment 1 can be used for the display portion 230.
  • a structure including the input portion 240 and the display portion 230 can be referred to as an input / output panel 700TP.
  • the input unit 240 includes a detection area 241.
  • the input unit 240 has a function of detecting an object close to the detection area 241.
  • the detection region 241 includes a region overlapping with the pixel 702 (i, j).
  • the input unit 240 includes a detection area 241.
  • the input unit 240 can include an oscillation circuit OSC and a detection circuit DC (see FIG. 11).
  • the detection area 241 includes, for example, one or a plurality of detection elements.
  • the detection region 241 includes a group of detection elements 775 (g, 1) to detection elements 775 (g, q) and another group of detection elements 775 (1, h) to detection elements 775 (p, h). (See FIG. 11). Note that g is an integer of 1 to p, h is an integer of 1 to q, and p and q are integers of 1 or more.
  • the group of sensing elements 775 (g, 1) to 775 (g, q) includes the sensing elements 775 (g, h) and are arranged in the row direction (direction indicated by an arrow R2 in the drawing). Note that the direction indicated by the arrow R2 in FIG. 11 may be the same as or different from the direction indicated by the arrow R1 in FIG.
  • another group of the detection elements 775 (1, h) to 775 (p, h) includes the detection elements 775 (g, h), and the column direction (in the drawing, indicated by an arrow C2) that intersects the row direction. (Direction shown).
  • the detection element has a function of detecting an adjacent pointer.
  • a finger or a stylus pen can be used as the pointer.
  • a metal piece or a coil can be used for the stylus pen.
  • a capacitive proximity sensor an electromagnetic induction proximity sensor, an optical proximity sensor, a resistive proximity sensor, or the like can be used as the detection element.
  • a plurality of types of sensing elements can also be used in combination.
  • a detection element that detects a finger and a detection element that detects a stylus pen can be used in combination.
  • the type of the pointer can be determined.
  • different instructions can be associated with the detection information based on the determined type of pointer. Specifically, when it is determined that a finger is used as the pointer, the detection information can be associated with the gesture. Alternatively, when it is determined that the stylus pen is used as the pointer, the detection information can be associated with the drawing process.
  • a finger can be detected by using a capacitive or optical proximity sensor.
  • the stylus pen can be detected using an electromagnetic induction type or optical type proximity sensor.
  • FIG. 12A is a block diagram illustrating a structure of an information processing device of one embodiment of the present invention.
  • 12B and 12C are projection views for explaining an example of the appearance of the information processing apparatus 200.
  • FIG. 12A is a block diagram illustrating a structure of an information processing device of one embodiment of the present invention.
  • 12B and 12C are projection views for explaining an example of the appearance of the information processing apparatus 200.
  • FIG. 12A is a block diagram illustrating a structure of an information processing device of one embodiment of the present invention.
  • 12B and 12C are projection views for explaining an example of the appearance of the information processing apparatus 200.
  • FIG. 13 is a flowchart illustrating a program according to one embodiment of the present invention.
  • FIG. 13A is a flowchart illustrating main processing of a program of one embodiment of the present invention
  • FIG. 13B is a flowchart illustrating interrupt processing.
  • FIG. 14 is a diagram illustrating a program according to one embodiment of the present invention.
  • FIG. 14A is a flowchart illustrating a program interrupt process of one embodiment of the present invention
  • FIG. 14B is a timing chart illustrating the operation of the information processing device of one embodiment of the present invention.
  • the information processing device 200 described in this embodiment includes an input / output device 220 and an arithmetic device 210 (see FIG. 12A).
  • the input / output device is electrically connected to the arithmetic device 210.
  • the information processing device 200 can include a housing (see FIG. 12B or FIG. 12C).
  • the input / output device 220 includes a display portion 230 and an input portion 240 (see FIG. 12A).
  • the input / output device 220 includes a detection unit 250.
  • the input / output device 220 can include a communication unit 290.
  • the input / output device 220 has a function of supplying image information V1 or control information SS, and a function of supplying position information P1 or detection information DS.
  • the arithmetic device 210 has a function of being supplied with the position information P1 or the detection information DS.
  • the arithmetic device 210 has a function of supplying image information V1.
  • the arithmetic device 210 has a function of operating based on the position information P1 or the detection information DS, for example.
  • the housing has a function of housing the input / output device 220 or the arithmetic device 210.
  • the housing has a function of supporting the display unit 230 or the arithmetic device 210.
  • the display unit 230 has a function of displaying an image based on the image information V1.
  • the display unit 230 has a function of displaying an image based on the control information SS.
  • the input unit 240 has a function of supplying the position information P1.
  • the detection unit 250 has a function of supplying detection information DS.
  • the detection unit 250 has a function of detecting the illuminance of an environment where the information processing apparatus 200 is used, and a function of supplying illuminance information.
  • the information processing apparatus can operate by grasping the intensity of light received by the casing of the information processing apparatus in an environment where the information processing apparatus is used.
  • the user of the information processing apparatus can select a display method.
  • a novel information processing apparatus that is highly convenient or reliable can be provided.
  • a touch panel in which a touch sensor is superimposed on a display panel is not only a display unit but also an input unit.
  • the information processing device 200 of one embodiment of the present invention includes a housing or the arithmetic device 210.
  • the computing device 210 includes a computing unit 211, a storage unit 212, a transmission path 214, and an input / output interface 215.
  • the information processing device of one embodiment of the present invention includes the input / output device 220.
  • the input / output device 220 includes a display unit 230, an input unit 240, a detection unit 250, and a communication unit 290.
  • the information processing device of one embodiment of the present invention includes the arithmetic device 210 or the input / output device 220.
  • the calculation device 210 includes a calculation unit 211 and a storage unit 212.
  • a transmission path 214 and an input / output interface 215 are provided.
  • the calculation unit 211 has a function of executing a program, for example.
  • Storage unit 212 has a function of storing, for example, a program executed by the calculation unit 211, initial information, setting information, or an image.
  • a hard disk a flash memory, a memory including a transistor including an oxide semiconductor, or the like can be used.
  • the input / output interface 215 includes a terminal or a wiring, and has a function of supplying information and receiving information.
  • the transmission line 214 can be electrically connected.
  • the input / output device 220 can be electrically connected.
  • the transmission path 214 includes wiring, supplies information, and has a function of being supplied with information.
  • the input / output interface 215 can be electrically connected. Further, it can be electrically connected to the calculation unit 211, the storage unit 212, or the input / output interface 215.
  • the input / output device 220 includes a display unit 230, an input unit 240, a detection unit 250, or a communication unit 290.
  • the input / output device described in Embodiment 5 can be used. Thereby, power consumption can be reduced.
  • the display unit 230 includes a control unit 238, a drive circuit GD, a drive circuit SD, and a display panel 700B (see FIG. 10).
  • the display device described in Embodiment 4 can be used for the display portion 230.
  • Input unit 240 >> Various human interfaces or the like can be used for the input unit 240 (see FIG. 12).
  • a keyboard, mouse, touch sensor, microphone, camera, or the like can be used for the input unit 240.
  • a touch sensor including a region overlapping with the display portion 230 can be used.
  • An input / output device including a touch sensor including a display unit 230 and a region overlapping with the display unit 230 can be referred to as a touch panel or a touch screen.
  • the user can make various gestures (tap, drag, swipe, pinch in, etc.) using a finger touching the touch panel as a pointer.
  • various gestures tap, drag, swipe, pinch in, etc.
  • the computing device 210 may analyze information such as the position or trajectory of a finger that touches the touch panel, and a specific gesture may be supplied when the analysis result satisfies a predetermined condition. Accordingly, the user can supply a predetermined operation command associated with the predetermined gesture in advance using the gesture.
  • the user can supply a “scroll command” for changing the display position of the image information using a gesture for moving a finger that touches the touch panel along the touch panel.
  • the detection unit 250 has a function of detecting surrounding conditions and supplying detection information. Specifically, illuminance information, posture information, pressure information, position information, and the like can be supplied.
  • a light detector for example, a light detector, an attitude detector, an acceleration sensor, an orientation sensor, a GPS (Global positioning System) signal receiving circuit, a pressure sensor, a temperature sensor, a humidity sensor, a camera, or the like can be used for the detection unit 250.
  • a GPS Global positioning System
  • the communication unit 290 has a function of supplying information to the network and acquiring information from the network.
  • program The program of one embodiment of the present invention includes the following steps (see FIG. 13A).
  • predetermined image information to be displayed at startup a predetermined mode for displaying the image information, and information for specifying a predetermined display method for displaying the image information are acquired from the storage unit 212.
  • one still image information or other moving image information can be used as predetermined image information.
  • the first mode or the second mode can be used as a predetermined mode.
  • interrupt processing is permitted (see FIGS. 13A and S2).
  • an arithmetic unit that is permitted to perform interrupt processing can perform interrupt processing in parallel with main processing.
  • the arithmetic unit that has returned to the main process from the interrupt process can reflect the result obtained by the interrupt process to the main process.
  • the arithmetic unit performs interrupt processing, and when returning from the interrupt processing, the counter may be set to a value other than the initial value. As a result, interrupt processing can always be performed after the program is started.
  • the image information is displayed using the predetermined mode or the predetermined display method selected in the first step or the interruption process (see FIGS. 13A and 13).
  • the predetermined mode specifies a mode for displaying image information
  • the predetermined display method specifies a method for displaying image information. Further, for example, it can be used as information for displaying the image information V1.
  • one method for displaying the image information V1 can be associated with the first mode.
  • another method for displaying the image information V1 can be associated with the second mode. Thereby, a display method can be selected based on the selected mode.
  • a method of supplying a selection signal to one scanning line at a frequency of 30 Hz or more, preferably 60 Hz or more, and displaying based on the selection signal can be associated with the first mode.
  • the selection signal when the selection signal is supplied at a frequency of 30 Hz or higher, preferably 60 Hz or higher, the motion of the moving image can be displayed smoothly.
  • an image when an image is updated at a frequency of 30 Hz or higher, preferably 60 Hz or higher, an image that changes so as to smoothly follow the user's operation can be displayed on the information processing apparatus 200 being operated by the user.
  • Second mode a method for supplying a selection signal to one scanning line at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute, and performing display based on the selection signal, Can be associated with a mode.
  • the selection signal is supplied at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute, a display in which flicker or flicker is suppressed can be displayed. In addition, power consumption can be reduced.
  • the display can be updated at a frequency of once per second or a frequency of once per minute.
  • the light-emitting element when a light-emitting element is used as a display element, the light-emitting element can emit light in a pulse shape to display image information.
  • the organic EL element can emit light in a pulse shape, and the afterglow can be used for display. Since the organic EL element has excellent frequency characteristics, there are cases where the time for driving the light emitting element can be shortened and the power consumption can be reduced. Alternatively, heat generation is suppressed, so that deterioration of the light-emitting element can be reduced in some cases.
  • an end command supplied in the interrupt process may be used for determination.
  • the interrupt process includes the following sixth to eighth steps (see FIG. 13B).
  • the detection unit 250 is used to detect the illuminance of the environment in which the information processing apparatus 200 is used (see FIGS. 13B and S6). Note that the color temperature or chromaticity of the ambient light may be detected instead of the illuminance of the environment.
  • a display method is determined based on the detected illuminance information (see FIGS. 13B and S7). For example, the display brightness is determined not to be too dark or too bright.
  • the display color may be adjusted.
  • FIG. 14A is a flowchart illustrating a program of one embodiment of the present invention.
  • FIG. 14A is a flowchart for explaining interrupt processing different from the interrupt processing shown in FIG.
  • the configuration example 2 of the information processing device is different from the interrupt processing described with reference to FIG. 13B in that the interrupt processing includes a step of changing the mode based on the supplied predetermined event.
  • the interrupt processing includes a step of changing the mode based on the supplied predetermined event.
  • the interrupt process includes the following sixth to eighth steps (see FIG. 14A).
  • the process when a predetermined event is supplied, the process proceeds to the seventh step, and when the predetermined event is not supplied, the process proceeds to the eighth step (see FIGS. 14A and U6). ).
  • the predetermined period can be a period of 5 seconds or less, 1 second or less, or 0.5 seconds or less, preferably 0.1 seconds or less and longer than 0 seconds.
  • the mode is changed (see FIGS. 14A and U7). Specifically, when the first mode is selected, the second mode is selected, and when the second mode is selected, the first mode is selected.
  • the display mode can be changed for some areas of the display unit 230. Specifically, the display mode can be changed for a region where the driver circuit GDB of the display portion 230 including the driver circuit GDA, the driver circuit GDB, and the driver circuit GDC supplies a selection signal (see FIG. 14B). .
  • the display mode of the area can be changed. Specifically, the frequency of the selection signal supplied by the drive circuit GDB can be changed. Thereby, for example, the display of the region where the drive circuit GDB supplies the selection signal can be updated without operating the drive circuit GDA and the drive circuit GDC. Alternatively, power consumed by the driver circuit can be suppressed.
  • interrupt processing is ended (see FIGS. 14A and U8). Note that interrupt processing may be repeatedly executed during a period in which main processing is being executed.
  • Predetermined event For example, an event such as “click” or “drag” supplied using a pointing device such as a mouse, an event such as “tap”, “drag” or “swipe” supplied to a touch panel using a finger or the like as a pointer Can be used.
  • an event such as “click” or “drag” supplied using a pointing device such as a mouse
  • an event such as “tap”, “drag” or “swipe” supplied to a touch panel using a finger or the like as a pointer Can be used.
  • an argument of a command associated with a predetermined event can be given using the position of the slide bar pointed to by the pointer, the swipe speed, the drag speed, or the like.
  • the information detected by the detection unit 250 can be compared with a preset threshold value, and the comparison result can be used as an event.
  • a pressure-sensitive detector or the like that contacts a button or the like that can be pushed into the housing can be used for the detection unit 250.
  • an end instruction can be associated with a particular event.
  • a “page turning command” for switching display from one displayed image information to another image information can be associated with a predetermined event.
  • an argument that determines a page turning speed used when executing the “page turning instruction” can be given using a predetermined event.
  • a “scroll command” for moving the display position of a part of one image information displayed to display another part continuous to the part can be associated with a predetermined event. It should be noted that an argument that determines the speed of moving the display position used when executing the “scroll command” can be given using a predetermined event.
  • a command for setting a display method or a command for generating image information can be associated with a predetermined event.
  • An argument that determines the brightness of the image to be generated can be associated with a predetermined event.
  • an argument for determining the brightness of the image to be generated may be determined based on the brightness of the environment detected by the detection unit 250.
  • a command for acquiring information distributed using a push-type service using the communication unit 290 can be associated with a predetermined event.
  • the teaching material distributed in a classroom such as a school or a university can be received and the information processing apparatus 200 can be used as a textbook (see FIG. 12C).
  • a material distributed in a conference room of a company or the like can be received and used as a conference material.
  • FIGS. 15B to 15E are perspective views illustrating the configuration of the information processing apparatus.
  • 16A to 16E are perspective views illustrating the configuration of the information processing device.
  • An information processing device 5200B described in this embodiment includes an arithmetic device 5210 and an input / output device 5220 (see FIG. 15A).
  • the arithmetic device 5210 has a function of supplying operation information and a function of supplying image information based on the operation information.
  • the input / output device 5220 includes a display unit 5230, an input unit 5240, a detection unit 5250, and a communication unit 5290, and has a function of supplying operation information and a function of supplying image information.
  • the input / output device 5220 has a function of supplying detection information, a function of supplying communication information, and a function of supplying communication information.
  • the input unit 5240 has a function of supplying operation information.
  • the input unit 5240 supplies operation information based on the operation of the user of the information processing apparatus 5200B.
  • a keyboard Specifically, a keyboard, hardware buttons, a pointing device, a touch sensor, a voice input device, a line-of-sight input device, or the like can be used for the input unit 5240.
  • the display portion 5230 includes a display panel and has a function of displaying image information.
  • the display panel described in Embodiment 1 can be used for the display portion 5230.
  • the detection unit 5250 has a function of supplying detection information. For example, it has a function of detecting the surrounding environment where the information processing apparatus is used and supplying it as detection information.
  • an illuminance sensor an imaging device, a posture detection device, a pressure sensor, a human sensor, or the like can be used for the detection unit 5250.
  • the communication unit 5290 has a function for supplying communication information and a function for supplying communication information. For example, a function of connecting to another electronic device or a communication network by wireless communication or wired communication is provided. Specifically, it has functions such as wireless local area communication, telephone communication, and short-range wireless communication.
  • an outer shape along a cylindrical column or the like can be applied to the display portion 5230 (see FIG. 15B).
  • the information processing device 5200B has a function of changing a display method according to the illuminance of the usage environment.
  • the information processing device 5200B has a function of detecting the presence of a person and changing display contents.
  • the information processing apparatus 5200B can be installed on a pillar of a building.
  • the information processing device 5200B can display an advertisement, a guidance, or the like.
  • the information processing device 5200B can be used for digital signage or the like.
  • the information processing device 5200B has a function of generating image information based on a locus of a pointer used by the user (see FIG. 15C).
  • a display panel having a diagonal line length of 20 inches or more, preferably 40 inches or more, more preferably 55 inches or more can be used.
  • a plurality of display panels can be arranged and used for one display area.
  • a plurality of display panels can be arranged and used for a multi-screen.
  • the information processing apparatus 5200B can be used for an electronic blackboard, an electronic bulletin board, an electronic signboard, and the like.
  • the information processing device 5200B has a function of changing the display method in accordance with the illuminance of the usage environment (see FIG. 15D). Thereby, for example, the power consumption of the smart watch can be reduced. Alternatively, for example, an image can be displayed on the smart watch so that the smart watch can be suitably used even in an environment with strong external light such as outdoors on a sunny day.
  • the display portion 5230 includes, for example, a curved surface that bends gently along the side surface of the housing (see FIG. 15E).
  • the display unit 5230 includes a display panel, and the display panel has a function of displaying image information on, for example, a front surface, a side surface, and an upper surface. Thereby, for example, image information can be displayed not only on the front surface of the mobile phone but also on the side surface and the upper surface.
  • the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16A). Thereby, the power consumption of a smart phone can be reduced. Or an image can be displayed on a smart phone so that a smart phone can be used conveniently also in an environment with strong external light, such as the outdoors of fine weather.
  • the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16B).
  • a display method in accordance with the illuminance of the usage environment (see FIG. 16B).
  • an image can be displayed on the television system so that the television system can be suitably used even when strong outside light that is inserted indoors on a sunny day.
  • the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16C). Thereby, for example, an image can be displayed on the tablet computer so that the tablet computer can be suitably used even in an environment with strong external light such as outdoors on a sunny day.
  • the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16D).
  • the subject can be displayed on the digital camera so that the image can be suitably viewed even in an environment with strong external light such as outdoors on a sunny day.
  • the information processing device 5200B has a function of changing the display method in accordance with the illuminance of the usage environment (see FIG. 16E).
  • an image can be displayed on the personal computer so that the personal computer can be used favorably even in an environment with strong external light such as outdoors on a sunny day.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y
  • elements for example, switches, transistors, capacitive elements, inductors
  • resistor element for example, a diode, a display element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2.
  • Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y.
  • X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other.
  • the drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order.
  • the source (or the first terminal or the like) of the transistor is electrically connected to X
  • the drain (or the second terminal or the like) of the transistor is electrically connected to Y
  • X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order.
  • X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
  • Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order.
  • a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor.
  • the first connection path is a path through Z1
  • the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path.
  • the third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2.
  • the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path.
  • the second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path.
  • Y, and the third connection path does not have the second connection path.
  • the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor;
  • the drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path.
  • the fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor.
  • X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).
  • the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
  • AF1 Alignment film AF2 Alignment film C11 Capacitance element C12 Capacitance element DS Detection information G1 Scan line KB1 Structure M Transistor P1 Position information S1 Signal line SS Control information SW1 Switch Tm11 Terminal Tm12 Terminal Tm13 Terminal Tr1 Transistor Tr2 Transistor Tr3 Transistor Tr4 Transistor V1 Image Information V11 Information 200 Information processing device 210 Computing device 211 Computing unit 212 Storage unit 214 Transmission path 215 I / O interface 220 I / O device 230 Display unit 231 Display area 233 Timing controller 234 Expansion circuit 235M Image processing circuit 238 Control unit 240 Input unit 241 Detection region 250 Detection unit 290 Communication unit 501C Insulating film 504 Conductive film 506 Insulating film 508 Semiconductor film 508A Region 50 B region 508C region 510 substrate 512A conductive film 512B conductive film 516 insulating film 519B terminal 520 functional layer 521 insul

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Abstract

Provided is a novel display panel that is excellent in convenience or reliability. A display panel that has a buffer amplifier and a display area. The buffer amplifier comprises a first transistor and a second transistor. The display area comprises signal lines and pixels. The pixels comprise pixel circuits. The pixel circuits comprise a third transistor. The signal lines are electrically connected to a source electrode or a drain electrode of the first transistor, to a source electrode or a drain electrode of the second transistor, and to a source electrode or a drain electrode of the third transistor. The first transistor comprises a first semiconductor. The second transistor comprises a second semiconductor. The third transistor comprises a third semiconductor. The third semiconductor includes an element that is included in the second semiconductor.

Description

表示パネル、表示装置、入出力装置および情報処理装置Display panel, display device, input / output device, and information processing device
本発明の一態様は、表示パネル、表示装置、入出力装置または情報処理装置に関する。 One embodiment of the present invention relates to a display panel, a display device, an input / output device, or an information processing device.
なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する発明の一態様の技術分野は、物、方法、または、製造方法に関するものである。または、本発明の一態様は、プロセス、マシン、マニュファクチャ、または、組成物(コンポジション・オブ・マター)に関するものである。そのため、より具体的に本明細書で開示する本発明の一態様の技術分野としては、半導体装置、表示装置、発光装置、蓄電装置、記憶装置、それらの駆動方法、または、それらの製造方法、を一例として挙げることができる。 Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). Therefore, as a technical field of one embodiment of the present invention disclosed more specifically in this specification, a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof, Can be cited as an example.
表示装置は、多階調化、及び高精細化等の高性能化の傾向にある。この高性能化に対応するため、表示装置の駆動回路、特にソースドライバには、IC(Integrated Circuit;以下ドライバICともいう)が採用されている。 Display devices tend to have higher performance such as multi-gradation and higher definition. In order to cope with this high performance, an IC (Integrated Circuit; hereinafter also referred to as a driver IC) is employed for a drive circuit of a display device, particularly a source driver.
ドライバICは、画素に与えるアナログ信号を生成するための階調電圧生成回路を有する。この階調電圧生成回路は、デジタル信号を基に、アナログ信号を生成する、所謂D/A変換回路である。 The driver IC has a gradation voltage generation circuit for generating an analog signal to be supplied to the pixel. This gradation voltage generation circuit is a so-called D / A conversion circuit that generates an analog signal based on a digital signal.
D/A変換回路は、高速での応答速度が求められる点を考慮して、直列に設けた抵抗を使用する、所謂R−DAC(Resistor digital−to−analog converter)が採用されている。R−DACは、デジタル信号のビット数の増加に伴ってスイッチの数が指数関数的に増加するため、ドライバICの回路面積が増加する。 The D / A converter circuit adopts a so-called R-DAC (Resistor digital-to-analog converter) that uses a resistor provided in series in consideration of the fact that a high response speed is required. In the R-DAC, the number of switches exponentially increases as the number of bits of a digital signal increases, so that the circuit area of the driver IC increases.
そのため、特許文献1乃至3では、上位ビットと下位ビットとで別々にデジタル信号を変換して、それぞれのアナログ信号を合成することで、所望のアナログ信号を得る構成が提案されている。 For this reason, Patent Documents 1 to 3 propose a configuration in which a desired analog signal is obtained by separately converting a digital signal into upper bits and lower bits and synthesizing respective analog signals.
米国特許出願公開第2005/0140630号明細書US Patent Application Publication No. 2005/0140630 米国特許出願公開第2010/0156867号明細書US Patent Application Publication No. 2010/0156867 米国特許出願公開第2010/0141493号明細書US Patent Application Publication No. 2010/0141493
本発明の一態様は、利便性または信頼性に優れた新規な表示パネルを提供することを課題の一とする。または、利便性または信頼性に優れた新規な表示装置を提供することを課題の一とする。または、利便性または信頼性に優れた新規な入出力装置を提供することを課題の一とする。または、利便性または信頼性に優れた新規な情報処理装置を提供することを課題の一とする。または、新規な表示パネル、新規な表示装置、新規な入出力装置、新規な情報処理装置または新規な半導体装置を提供することを課題の一とする。 An object of one embodiment of the present invention is to provide a novel display panel that is highly convenient or reliable. Another object is to provide a novel display device that is highly convenient or reliable. Another object is to provide a novel input / output device that is highly convenient or reliable. Another object is to provide a novel information processing device that is highly convenient or reliable. Another object is to provide a novel display panel, a novel display device, a novel input / output device, a novel information processing device, or a novel semiconductor device.
なお、これらの課題の記載は、他の課題の存在を妨げるものではない。なお、本発明の一態様は、これらの課題の全てを解決する必要はないものとする。なお、これら以外の課題は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の課題を抽出することが可能である。 Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.
(1)本発明の一態様は、バッファアンプと、表示領域と、を有する表示パネルである。 (1) One embodiment of the present invention is a display panel including a buffer amplifier and a display region.
バッファアンプは、第1のトランジスタおよび第2のトランジスタを備える。 The buffer amplifier includes a first transistor and a second transistor.
表示領域は信号線および画素を備える。 The display area includes signal lines and pixels.
画素は画素回路を備え、画素回路は、第3のトランジスタを備える。 The pixel includes a pixel circuit, and the pixel circuit includes a third transistor.
信号線は第1のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、信号線は第2のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、信号線は第3のトランジスタのソース電極またはドレイン電極の一方と電気的に接続される。 The signal line is electrically connected to one of the source electrode and the drain electrode of the first transistor, the signal line is electrically connected to one of the source electrode and the drain electrode of the second transistor, and the signal line is connected to the third transistor It is electrically connected to one of a source electrode and a drain electrode of the transistor.
第1のトランジスタは第1の半導体を備え、第2のトランジスタは第2の半導体を備え、第3のトランジスタは第3の半導体を備える。 The first transistor includes a first semiconductor, the second transistor includes a second semiconductor, and the third transistor includes a third semiconductor.
第3の半導体は第2の半導体に含まれる元素を含む。 The third semiconductor includes an element contained in the second semiconductor.
これにより、第1のトランジスタを用いて、信号線を充電する電流を供給することができる。または、第2のトランジスタを用いて、信号線から放電することができる。または、信号線を充電または信号線から放電する際に生じる熱を効率よく放熱することができる。または、バッファアンプの温度の上昇を抑制することができる。または、画素回路に用いる第3のトランジスタを形成する工程において、第2のトランジスタを形成することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Accordingly, a current for charging the signal line can be supplied using the first transistor. Alternatively, the signal line can be discharged using the second transistor. Alternatively, heat generated when the signal line is charged or discharged from the signal line can be efficiently radiated. Alternatively, an increase in the temperature of the buffer amplifier can be suppressed. Alternatively, in the step of forming the third transistor used for the pixel circuit, the second transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
(2)また、本発明の一態様は、第1の半導体が単結晶シリコンを含み、第2の半導体が金属酸化物を含む、上記の表示パネルである。 (2) Another embodiment of the present invention is the above display panel in which the first semiconductor includes single crystal silicon and the second semiconductor includes a metal oxide.
これにより、第1のトランジスタの駆動能力を高めることができる。または、第2のトランジスタの耐圧を高めることができる。または、第2のトランジスタに流す電流を大きくすることができる。または、第2のトランジスタを第1のトランジスタから遠ざけることができる。または、熱源になる第1のトランジスタおよび第2のトランジスタを、互いに遠ざけることができる。または、第2のトランジスタの発熱を配線等に放熱することができる。または、第1のトランジスタが形成された単結晶シリコン基板の温度の上昇を抑制することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thereby, the drive capability of the first transistor can be increased. Alternatively, the breakdown voltage of the second transistor can be increased. Alternatively, the current flowing through the second transistor can be increased. Alternatively, the second transistor can be kept away from the first transistor. Alternatively, the first transistor and the second transistor serving as heat sources can be separated from each other. Alternatively, heat generated by the second transistor can be radiated to the wiring or the like. Alternatively, an increase in temperature of the single crystal silicon substrate over which the first transistor is formed can be suppressed. As a result, a novel display panel that is highly convenient or reliable can be provided.
(3)また、本発明の一態様は、半導体装置を有する上記の表示パネルである。 (3) One embodiment of the present invention is the above display panel including a semiconductor device.
半導体装置はデジタルアナログ変換回路を備え、半導体装置は第1の端子、第2の端子および第3の端子を備え、半導体装置は第1のトランジスタを備える。 The semiconductor device includes a digital-analog conversion circuit, the semiconductor device includes a first terminal, a second terminal, and a third terminal, and the semiconductor device includes a first transistor.
第1の端子はデジタルアナログ変換回路と電気的に接続される。 The first terminal is electrically connected to the digital / analog conversion circuit.
第2の端子は第1のトランジスタのソース電極またはドレイン電極と電気的に接続され、第2の端子は信号線と電気的に接続される。 The second terminal is electrically connected to the source electrode or the drain electrode of the first transistor, and the second terminal is electrically connected to the signal line.
第3の端子は第2のトランジスタのゲート電極と電気的に接続される。 The third terminal is electrically connected to the gate electrode of the second transistor.
これにより、デジタル信号を所定の電圧に変換したアナログ信号を一の信号線に供給することができる。デジタルアナログ変換回路に用いるトランジスタを形成する工程において、第1のトランジスタを形成することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thereby, an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to one signal line. In the step of forming a transistor used for the digital-analog converter circuit, the first transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
(4)また、本発明の一態様は、表示領域と、デジタルアナログ変換回路と、を有する表示パネルである。 (4) One embodiment of the present invention is a display panel including a display region and a digital-analog conversion circuit.
表示領域は画素および信号線を備え、画素は画素回路を備え、画素回路は第3のトランジスタを備える。信号線は第3のトランジスタのソース電極またはドレイン電極の一方と電気的に接続される。 The display region includes a pixel and a signal line, the pixel includes a pixel circuit, and the pixel circuit includes a third transistor. The signal line is electrically connected to one of the source electrode and the drain electrode of the third transistor.
第3のトランジスタは第3の半導体を備え、第3の半導体は金属酸化物を含む。 The third transistor includes a third semiconductor, and the third semiconductor includes a metal oxide.
デジタルアナログ変換回路はパラレル信号を供給され、デジタルアナログ変換回路はアナログ信号を供給する。また、デジタルアナログ変換回路はパストランジスタ・ロジック回路および抵抗ストリングを備える。 The digital-analog conversion circuit is supplied with a parallel signal, and the digital-analog conversion circuit supplies an analog signal. The digital-analog conversion circuit includes a pass transistor / logic circuit and a resistor string.
抵抗ストリングはパストランジスタ・ロジック回路と電気的に接続され、パストランジスタ・ロジック回路は第4のトランジスタを備える。信号線は第4のトランジスタのソース電極またはドレイン電極の一方と電気的に接続される。 The resistor string is electrically connected to the pass transistor logic circuit, and the pass transistor logic circuit includes a fourth transistor. The signal line is electrically connected to one of the source electrode and the drain electrode of the fourth transistor.
第4のトランジスタは第4の半導体を備え、第4の半導体は第3の半導体に含まれる元素を含む。 The fourth transistor includes a fourth semiconductor, and the fourth semiconductor includes an element contained in the third semiconductor.
これにより、信号線に電気的に接続される画素に、デジタル信号を所定の電圧に変換したアナログ信号を供給することができる。または、デジタルアナログ変換回路のパストランジスタ・ロジック回路に、画素のトランジスタが備える半導体と同じ半導体を備えるトランジスタを用いることができる。または、画素回路を作製する工程の一部を、パストランジスタ・ロジック回路を作製する工程の一部と兼ねることができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Accordingly, an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to a pixel electrically connected to the signal line. Alternatively, a transistor having the same semiconductor as that of a pixel transistor can be used for the pass transistor / logic circuit of the digital-analog converter circuit. Alternatively, part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit. As a result, a novel display panel that is highly convenient or reliable can be provided.
(5)また、本発明の一態様は、シフトレジスタと、ラッチ回路と、を有する上記の表示パネルである。 (5) One embodiment of the present invention is the above display panel including a shift register and a latch circuit.
ラッチ回路はシフトレジスタと電気的に接続される。 The latch circuit is electrically connected to the shift register.
パストランジスタ・ロジック回路はラッチ回路と電気的に接続される。 The pass transistor logic circuit is electrically connected to the latch circuit.
シフトレジスタはn型のトランジスタのみを含み、ラッチ回路はn型のトランジスタのみを含む。 The shift register includes only n-type transistors, and the latch circuit includes only n-type transistors.
これにより、n型のトランジスタのみを用いて、デジタルアナログ変換回路および画素回路を構成することができる。または、デジタルアナログ変換回路に、画素のトランジスタが備える半導体と同じ半導体を備えるトランジスタを用いることができる。または、画素回路を作製する工程の一部を、パストランジスタ・ロジック回路を作製する工程の一部と兼ねることができる。または、デジタルアナログ変換回路の作製工程を簡略化することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thus, a digital-analog conversion circuit and a pixel circuit can be configured using only n-type transistors. Alternatively, a transistor including the same semiconductor as a semiconductor included in a pixel transistor can be used for the digital-analog conversion circuit. Alternatively, part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit. Alternatively, the manufacturing process of the digital-analog converter circuit can be simplified. As a result, a novel display panel that is highly convenient or reliable can be provided.
(6)また、本発明の一態様は、表示領域が一群の複数の画素、他の一群の複数の画素、走査線を備える上記の表示パネルである。 (6) One embodiment of the present invention is the above display panel in which a display region includes a group of a plurality of pixels, another group of a plurality of pixels, and a scan line.
一群の複数の画素は行方向に配設され、一群の複数の画素は画素を含む。 The group of the plurality of pixels is arranged in the row direction, and the group of the plurality of pixels includes the pixel.
他の一群の複数の画素は、行方向と交差する列方向に配設される。 Another group of the plurality of pixels is arranged in the column direction intersecting the row direction.
走査線は一群の複数の画素と電気的に接続される。 The scan line is electrically connected to a group of a plurality of pixels.
信号線は他の一群の複数の画素と電気的に接続される。 The signal line is electrically connected to another group of a plurality of pixels.
これにより、他の一群の複数の画素に、デジタル信号を所定の電圧に変換したアナログ信号を供給することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thus, an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to the other group of pixels. As a result, a novel display panel that is highly convenient or reliable can be provided.
(7)また、本発明の一態様は、表示領域が複数の画素を行列状に備える上記の表示パネルである。 (7) One embodiment of the present invention is the above display panel in which the display region includes a plurality of pixels in a matrix.
表示領域は7600個以上の画素を行方向に備え、表示領域は4300個以上の画素を列方向に備える。 The display area includes 7600 or more pixels in the row direction, and the display area includes 4300 or more pixels in the column direction.
これにより、例えば、ハイビジョン画像または4K画像より数が多い画素に、劣化が抑制された画像信号を供給することができる。または、画像信号の劣化を抑制しながら、画素に画像信号を高速に供給することができる。または、高精細な画像を表示することができる。または、60Hz以上、好ましくは120Hz以上のリフレッシュレートで表示をすることができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thereby, for example, an image signal in which deterioration is suppressed can be supplied to pixels having a larger number than a high-vision image or a 4K image. Alternatively, the image signal can be supplied to the pixels at high speed while suppressing the deterioration of the image signal. Alternatively, a high-definition image can be displayed. Alternatively, display can be performed at a refresh rate of 60 Hz or higher, preferably 120 Hz or higher. As a result, a novel display panel that is highly convenient or reliable can be provided.
(8)また、本発明の一態様は、表示領域が第1の画素、第2の画素および第3の画素を備える上記の表示パネルである。 (8) One embodiment of the present invention is the above display panel in which a display region includes a first pixel, a second pixel, and a third pixel.
第1の画素は、CIE1931色度座標における色度xが0.680より大きく0.720以下、色度yが0.260以上0.320以下の色を表示する。 The first pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of greater than 0.680 and less than or equal to 0.720, and a chromaticity y of 0.260 or more and 0.320 or less.
第2の画素は、CIE1931色度座標における色度xが0.130以上0.250以下、色度yが0.710より大きく0.810以下の色を表示する。 The second pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of 0.130 or more and 0.250 or less and a chromaticity y of greater than 0.710 and 0.810 or less.
第3の画素は、CIE1931色度座標における色度xが0.120以上0.170以下、色度yが0.020以上0.060未満の色を表示する。 The third pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of 0.120 or more and 0.170 or less and a chromaticity y of 0.020 or more and less than 0.060.
(9)また、本発明の一態様は、上記の表示パネルと、制御部と、を有する表示装置である。 (9) One embodiment of the present invention is a display device including the display panel and a control unit.
制御部は画像情報および制御情報を供給され、制御部は画像情報に基づいて情報を生成し、制御部は情報を供給する。 The control unit is supplied with image information and control information, the control unit generates information based on the image information, and the control unit supplies the information.
情報は、12bit以上の階調を含む。 The information includes gradations of 12 bits or more.
表示パネルは情報を供給される。 The display panel is supplied with information.
走査線は60Hz以上の頻度で選択信号を供給される。 The scanning line is supplied with a selection signal at a frequency of 60 Hz or more.
表示素子は情報に基づいて表示する。 The display element displays based on the information.
これにより、表示素子を用いて画像情報を表示することができる。その結果、利便性または信頼性に優れた新規な表示装置を提供することができる。 Thereby, image information can be displayed using a display element. As a result, a novel display device that is highly convenient or reliable can be provided.
(10)また、本発明の一態様は、入力部と、表示部と、を有する入出力装置である。 (10) One embodiment of the present invention is an input / output device including an input portion and a display portion.
表示部は上記の表示パネルを備える。 The display unit includes the display panel.
入力部は検知領域を備え、入力部は検知領域に近接するものを検知する。また、検知領域は画素と重なる領域を備える。 The input unit includes a detection region, and the input unit detects an object close to the detection region. The detection area includes an area that overlaps with the pixel.
これにより、表示部を用いて画像情報を表示しながら、表示部と重なる領域に近接するものを検知することができる。または、表示部に近接させる指などをポインタに用いて、位置情報を入力することができる。または、位置情報を表示部に表示する画像情報に関連付けることができる。その結果、利便性または信頼性に優れた新規な入出力装置を提供することができる。 Accordingly, it is possible to detect an object that is close to a region overlapping with the display unit while displaying image information using the display unit. Alternatively, position information can be input using a finger or the like that is brought close to the display portion as a pointer. Alternatively, the position information can be associated with image information displayed on the display unit. As a result, a novel input / output device that is highly convenient or reliable can be provided.
(11)また、本発明の一態様は、キーボード、ハードウェアボタン、ポインティングデバイス、タッチセンサ、照度センサ、撮像装置、音声入力装置、視線入力装置、姿勢検出装置、のうち一以上と、上記の表示パネルと、を含む、情報処理装置である。 (11) One embodiment of the present invention includes one or more of a keyboard, a hardware button, a pointing device, a touch sensor, an illuminance sensor, an imaging device, a voice input device, a line-of-sight input device, and a posture detection device, And an information processing apparatus including a display panel.
これにより、さまざまな入力装置を用いて供給する情報に基づいて、画像情報または制御情報を演算装置に生成させることができる。その結果、利便性または信頼性に優れた新規な情報処理装置を提供することができる。 Thereby, based on the information supplied using various input devices, image information or control information can be generated by the arithmetic device. As a result, a novel information processing apparatus that is highly convenient or reliable can be provided.
本明細書に添付した図面では、構成要素を機能ごとに分類し、互いに独立したブロックとしてブロック図を示しているが、実際の構成要素は機能ごとに完全に切り分けることが難しく、一つの構成要素が複数の機能に係わることもあり得る。 In the drawings attached to the present specification, the components are classified by function, and the block diagram is shown as an independent block. However, it is difficult to completely separate the actual components for each function. May involve multiple functions.
本明細書においてトランジスタが有するソースとドレインは、トランジスタの極性及び各端子に与えられる電位の高低によって、その呼び方が入れ替わる。一般的に、nチャネル型トランジスタでは、低い電位が与えられる端子がソースと呼ばれ、高い電位が与えられる端子がドレインと呼ばれる。また、pチャネル型トランジスタでは、低い電位が与えられる端子がドレインと呼ばれ、高い電位が与えられる端子がソースと呼ばれる。本明細書では、便宜上、ソースとドレインとが固定されているものと仮定して、トランジスタの接続関係を説明する場合があるが、実際には上記電位の関係に従ってソースとドレインの呼び方が入れ替わる。 In this specification, the terms “source” and “drain” of a transistor interchange with each other depending on the polarity of the transistor or the level of potential applied to each terminal. In general, in an n-channel transistor, a terminal to which a low potential is applied is called a source, and a terminal to which a high potential is applied is called a drain. In a p-channel transistor, a terminal to which a low potential is applied is called a drain, and a terminal to which a high potential is applied is called a source. In this specification, for the sake of convenience, the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .
本明細書においてトランジスタのソースとは、活性層として機能する半導体膜の一部であるソース領域、或いは上記半導体膜に接続されたソース電極を意味する。同様に、トランジスタのドレインとは、上記半導体膜の一部であるドレイン領域、或いは上記半導体膜に接続されたドレイン電極を意味する。また、ゲートはゲート電極を意味する。 In this specification, the source of a transistor means a source region that is part of a semiconductor film functioning as an active layer or a source electrode connected to the semiconductor film. Similarly, a drain of a transistor means a drain region that is part of the semiconductor film or a drain electrode connected to the semiconductor film. The gate means a gate electrode.
本明細書においてトランジスタが直列に接続されている状態とは、例えば、第1のトランジスタのソースまたはドレインの一方のみが、第2のトランジスタのソースまたはドレインの一方のみに接続されている状態を意味する。また、トランジスタが並列に接続されている状態とは、第1のトランジスタのソースまたはドレインの一方が第2のトランジスタのソースまたはドレインの一方に接続され、第1のトランジスタのソースまたはドレインの他方が第2のトランジスタのソースまたはドレインの他方に接続されている状態を意味する。 In this specification, the state where the transistors are connected in series means, for example, a state where only one of the source and the drain of the first transistor is connected to only one of the source and the drain of the second transistor. To do. In addition, the state where the transistors are connected in parallel means that one of the source and the drain of the first transistor is connected to one of the source and the drain of the second transistor, and the other of the source and the drain of the first transistor is connected. It means a state of being connected to the other of the source and the drain of the second transistor.
本明細書において接続とは、電気的な接続を意味しており、電流、電圧または電位が、供給可能、或いは伝送可能な状態に相当する。従って、接続している状態とは、直接接続している状態を必ずしも指すわけではなく、電流、電圧または電位が、供給可能、或いは伝送可能であるように、配線、抵抗、ダイオード、トランジスタなどの回路素子を介して間接的に接続している状態も、その範疇に含む。 In this specification, the connection means an electrical connection, and corresponds to a state where current, voltage, or potential can be supplied or transmitted. Therefore, the connected state does not necessarily indicate a directly connected state, and a wiring, a resistor, a diode, a transistor, or the like is provided so that current, voltage, or potential can be supplied or transmitted. The state of being indirectly connected through a circuit element is also included in the category.
本明細書において回路図上は独立している構成要素どうしが接続されている場合であっても、実際には、例えば配線の一部が電極として機能する場合など、一の導電膜が、複数の構成要素の機能を併せ持っている場合もある。本明細書において接続とは、このような、一の導電膜が、複数の構成要素の機能を併せ持っている場合も、その範疇に含める。 In this specification, even when independent components on the circuit diagram are connected to each other, in practice, for example, when a part of the wiring functions as an electrode, In some cases, it also has the functions of the components. In this specification, the term “connection” includes a case where one conductive film has functions of a plurality of components.
また、本明細書中において、トランジスタの第1の電極または第2の電極の一方がソース電極を、他方がドレイン電極を指す。 In this specification, one of a first electrode and a second electrode of a transistor refers to a source electrode, and the other refers to a drain electrode.
本発明の一態様によれば、利便性または信頼性に優れた新規な表示パネルを提供することができる。または、利便性または信頼性に優れた新規な表示装置を提供することができる。または、利便性または信頼性に優れた新規な入出力装置を提供することができる。または、利便性または信頼性に優れた新規な情報処理装置を提供することができる。または、新規な表示パネル、新規な表示装置、新規な入出力装置、新規な情報処理装置または、新規な半導体装置を提供することができる。 According to one embodiment of the present invention, a novel display panel that is highly convenient or reliable can be provided. Alternatively, a novel display device that is highly convenient or reliable can be provided. Alternatively, a novel input / output device that is highly convenient or reliable can be provided. Alternatively, a novel information processing device that is highly convenient or reliable can be provided. Alternatively, a novel display panel, a novel display device, a novel input / output device, a novel information processing device, or a novel semiconductor device can be provided.
なお、これらの効果の記載は、他の効果の存在を妨げるものではない。なお、本発明の一態様は、必ずしも、これらの効果の全てを有する必要はない。なお、これら以外の効果は、明細書、図面、請求項などの記載から、自ずと明らかとなるものであり、明細書、図面、請求項などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.
実施の形態に係る表示パネルの構成を説明するブロック図。FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment. 実施の形態に係る表示パネルの構成を説明する図。4A and 4B illustrate a structure of a display panel according to Embodiment. 実施の形態に係る表示パネルに用いることができるバッファアンプの構成を説明する回路図。FIG. 6 is a circuit diagram illustrating a structure of a buffer amplifier that can be used for the display panel according to Embodiment; 実施の形態に係る表示パネルの構成を説明する上面図。FIG. 6 is a top view illustrating a structure of a display panel according to Embodiment. 実施の形態に係る表示パネルの構成を説明するブロック図。FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment. 実施の形態に係る表示パネルの構成を説明する断面図および回路図。10A and 10B are a cross-sectional view and a circuit diagram illustrating a structure of a display panel according to an embodiment. 実施の形態に係る表示パネルの構成を説明する断面図。4 is a cross-sectional view illustrating a structure of a display panel according to Embodiment. FIG. 実施の形態に係る表示パネルの構成を説明する断面図および回路図。10A and 10B are a cross-sectional view and a circuit diagram illustrating a structure of a display panel according to an embodiment. 実施の形態に係る表示パネルの構成を説明する断面図。4 is a cross-sectional view illustrating a structure of a display panel according to Embodiment. FIG. 実施の形態に係る表示装置を説明する図。4A and 4B illustrate a display device according to an embodiment. 実施の形態に係る入出力装置の構成を説明するブロック図。FIG. 3 is a block diagram illustrating a structure of an input / output device according to an embodiment. 実施の形態に係る情報処理装置の構成を説明するブロック図および投影図。FIG. 2 is a block diagram and a projection view illustrating a configuration of an information processing device according to an embodiment. 実施の形態に係る情報処理装置の駆動方法を説明するフロー図。FIG. 6 is a flowchart illustrating a method for driving the information processing apparatus according to the embodiment. 実施の形態に係る情報処理装置の駆動方法を説明するフロー図およびタイミングチャート。6A and 6B are a flowchart and a timing chart illustrating a method for driving an information processing apparatus according to an embodiment. 実施の形態に係る情報処理装置の構成を説明する図。2A and 2B illustrate a structure of an information processing device according to an embodiment. 実施の形態に係る情報処理装置の構成を説明する図。2A and 2B illustrate a structure of an information processing device according to an embodiment. 実施の形態に係る表示パネルの構成を説明するブロック図。FIG. 6 is a block diagram illustrating a structure of a display panel according to Embodiment. 実施の形態に係る表示パネルの構成を説明するブロック図および回路図。4A and 4B are a block diagram and a circuit diagram illustrating a structure of a display panel according to Embodiment;
本発明の一態様は、バッファアンプと、表示領域と、を有する表示パネルであって、バッファアンプは第1のトランジスタおよび第2のトランジスタを備え、表示領域は信号線および画素を備える。画素は画素回路を備え、画素回路は第3のトランジスタを備える。また、信号線は第1のトランジスタのソース電極またはドレイン電極と電気的に接続され、第2のトランジスタのソース電極またはドレイン電極と電気的に接続され、第3のトランジスタのソース電極またはドレイン電極と電気的に接続される。また、第1のトランジスタは、第1の半導体を備え、第2のトランジスタは、第2の半導体を備え、第3のトランジスタは、第3の半導体を備え、第3の半導体は、第2の半導体に含まれる元素を含む。 One embodiment of the present invention is a display panel including a buffer amplifier and a display region. The buffer amplifier includes a first transistor and a second transistor, and the display region includes a signal line and a pixel. The pixel includes a pixel circuit, and the pixel circuit includes a third transistor. In addition, the signal line is electrically connected to the source electrode or the drain electrode of the first transistor, is electrically connected to the source electrode or the drain electrode of the second transistor, and is connected to the source electrode or the drain electrode of the third transistor. Electrically connected. The first transistor includes a first semiconductor, the second transistor includes a second semiconductor, the third transistor includes a third semiconductor, and the third semiconductor includes a second semiconductor. Contains elements contained in semiconductors.
これにより、第1のトランジスタを用いて、信号線を充電する電流を供給することができる。または、第2のトランジスタを用いて、信号線から放電することができる。または、信号線を充電または信号線から放電することができる。または、バッファアンプの温度の上昇を抑制することができる。または、画素回路に用いる第3のトランジスタを形成する工程において、第2のトランジスタを形成することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Accordingly, a current for charging the signal line can be supplied using the first transistor. Alternatively, the signal line can be discharged using the second transistor. Alternatively, the signal line can be charged or discharged from the signal line. Alternatively, an increase in the temperature of the buffer amplifier can be suppressed. Alternatively, in the step of forming the third transistor used for the pixel circuit, the second transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
実施の形態について、図面を用いて詳細に説明する。但し、本発明は以下の説明に限定されず、本発明の趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。なお、以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。 Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.
(実施の形態1)
本実施の形態では、本発明の一態様の表示パネルの構成について、図1および図2を参照しながら説明する。
(Embodiment 1)
In this embodiment, the structure of the display panel of one embodiment of the present invention will be described with reference to FIGS.
図1は本発明の一態様の表示パネルの構成を説明する図である。 FIG. 1 illustrates a structure of a display panel of one embodiment of the present invention.
図2は本発明の一態様の表示パネルの構成を説明する図である。 FIG. 2 illustrates a structure of a display panel of one embodiment of the present invention.
なお、本明細書において、1以上の整数を値にとる変数を符号に用いる場合がある。例えば、1以上の整数の値をとる変数pを含む(p)を、最大p個の構成要素のいずれかを特定する符号の一部に用いる場合がある。また、例えば、1以上の整数の値をとる変数mおよび変数nを含む(m,n)を、最大m×n個の構成要素のいずれかを特定する符号の一部に用いる場合がある。 In the present specification, a variable having an integer value of 1 or more may be used for the sign. For example, (p) including a variable p that takes an integer value of 1 or more may be used as a part of a code that identifies any of the maximum p components. Further, for example, a variable m that takes an integer value of 1 or more and (m, n) including a variable n may be used as part of a code that identifies any of the maximum m × n components.
<表示パネルの構成例1.>
本実施の形態で説明する表示パネル700は、バッファアンプBAと、表示領域231と、を有する(図1参照)。
<Configuration Example of Display Panel 1. >
A display panel 700 described in this embodiment includes a buffer amplifier BA and a display region 231 (see FIG. 1).
《バッファアンプBAの構成例》
バッファアンプBAは、トランジスタTr1およびトランジスタTr2を備える(図2参照)。例えば、回路11および回路12をバッファアンプBAに用いることができる。
<< Configuration Example of Buffer Amplifier BA >>
The buffer amplifier BA includes a transistor Tr1 and a transistor Tr2 (see FIG. 2). For example, the circuit 11 and the circuit 12 can be used for the buffer amplifier BA.
具体的には、トランジスタTr1およびトランジスタTr2を備えるCMOS回路を、回路12に用いることができる。また、例えば、差動増幅回路を回路11に用いることができる。具体的には、図3に示す回路を回路11に用いることができる。なお、所定のバイアス電圧を供給する配線を配線VB1乃至配線VB6に用いることができる。 Specifically, a CMOS circuit including the transistor Tr1 and the transistor Tr2 can be used for the circuit 12. For example, a differential amplifier circuit can be used for the circuit 11. Specifically, the circuit illustrated in FIG. 3 can be used for the circuit 11. Note that wirings for supplying a predetermined bias voltage can be used for the wirings VB1 to VB6.
《表示領域231の構成例1.》
表示領域231は、信号線S1(j)および画素702(i,j)を備える(図1参照)。
<< Configuration Example 1 of Display Area 231 >>
The display area 231 includes a signal line S1 (j) and a pixel 702 (i, j) (see FIG. 1).
画素702(i,j)は、画素回路530(i,j)を備え、画素回路530(i,j)は、トランジスタTr3を備える(図2参照)。 The pixel 702 (i, j) includes a pixel circuit 530 (i, j), and the pixel circuit 530 (i, j) includes a transistor Tr3 (see FIG. 2).
《信号線S1(j)の構成例》
信号線S1(j)は、トランジスタTr1のソース電極またはドレイン電極の一方と電気的に接続される。信号線S1(j)は、トランジスタTr2のソース電極またはドレイン電極の一方と電気的に接続される。また、配線Vddは、トランジスタTr1のソース電極またはドレイン電極の他方と電気的に接続される。配線Vssは、トランジスタTr2のソース電極またはドレイン電極の他方と電気的に接続される。なお、配線Vddは、配線Vssが供給する電位より高い電位を供給する機能を備える。
<< Configuration Example of Signal Line S1 (j) >>
The signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr1. The signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr2. The wiring Vdd is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr1. The wiring Vss is electrically connected to the other of the source electrode and the drain electrode of the transistor Tr2. Note that the wiring Vdd has a function of supplying a higher potential than the potential supplied by the wiring Vss.
また、信号線S1(j)は、トランジスタTr3のソース電極またはドレイン電極の一方と電気的に接続される。 The signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr3.
《トランジスタの構成例1.》
トランジスタTr1は第1の半導体を備え、トランジスタTr2は第2の半導体を備え、トランジスタTr3は、第3の半導体を備える。
<< Configuration Example 1 of Transistor >>
The transistor Tr1 includes a first semiconductor, the transistor Tr2 includes a second semiconductor, and the transistor Tr3 includes a third semiconductor.
第3の半導体は、第2の半導体に含まれる元素を含む。例えば、第2の半導体が形成される基板上に形成される半導体を、第3の半導体に用いることができる。または、第2の半導体を形成する工程において形成することができる半導体を、第3の半導体に用いることができる。 The third semiconductor includes an element contained in the second semiconductor. For example, a semiconductor formed over a substrate over which the second semiconductor is formed can be used for the third semiconductor. Alternatively, a semiconductor that can be formed in the step of forming the second semiconductor can be used for the third semiconductor.
これにより、第1のトランジスタを用いて、信号線を充電する電流を供給することができる。または、第2のトランジスタを用いて、信号線から放電することができる。または、信号線を充電または信号線から放電する際に生じる熱を効率よく放熱することができる。または、バッファアンプの温度の上昇を抑制することができる。または、画素回路に用いる第3のトランジスタを形成する工程において、第2のトランジスタを形成することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Accordingly, a current for charging the signal line can be supplied using the first transistor. Alternatively, the signal line can be discharged using the second transistor. Alternatively, heat generated when the signal line is charged or discharged from the signal line can be efficiently radiated. Alternatively, an increase in the temperature of the buffer amplifier can be suppressed. Alternatively, in the step of forming the third transistor used for the pixel circuit, the second transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
《トランジスタの構成例2.》
また、本実施の形態で説明する、第1の半導体は単結晶シリコンを含み、第2の半導体は金属酸化物を含む。例えば、単結晶シリコン基板を第1の半導体に用いることができる。または、絶縁性の基板に形成された半導体膜を第2の半導体に用いることができる。具体的には、ガラスまたは樹脂を含む絶縁性の材料を絶縁性の基板に用いることができる。
<< Configuration Example 2 of Transistor >>
In addition, the first semiconductor described in this embodiment includes single crystal silicon, and the second semiconductor includes a metal oxide. For example, a single crystal silicon substrate can be used for the first semiconductor. Alternatively, a semiconductor film formed over an insulating substrate can be used for the second semiconductor. Specifically, an insulating material containing glass or resin can be used for the insulating substrate.
これにより、第1のトランジスタの駆動能力を高めることができる。または、第2のトランジスタの耐圧を高めることができる。または、第2のトランジスタに流す電流を大きくすることができる。または、第2のトランジスタを第1のトランジスタから遠ざけることができる。または、熱源になる第1のトランジスタおよび第2のトランジスタを、互いに遠ざけることができる。または、第2のトランジスタの発熱を配線等に放熱することができる。または、第1のトランジスタが形成された単結晶シリコン基板の温度の上昇を抑制することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thereby, the drive capability of the first transistor can be increased. Alternatively, the breakdown voltage of the second transistor can be increased. Alternatively, the current flowing through the second transistor can be increased. Alternatively, the second transistor can be kept away from the first transistor. Alternatively, the first transistor and the second transistor serving as heat sources can be separated from each other. Alternatively, heat generated by the second transistor can be radiated to the wiring or the like. Alternatively, an increase in temperature of the single crystal silicon substrate over which the first transistor is formed can be suppressed. As a result, a novel display panel that is highly convenient or reliable can be provided.
<表示パネルの構成例2.>
本実施の形態で説明する表示パネル700は、駆動回路SD(1)を有する(図1参照)。
<Configuration Example of Display Panel 2. >
A display panel 700 described in this embodiment includes a driver circuit SD (1) (see FIG. 1).
《駆動回路SD(1)》
駆動回路SD(1)は、情報V11に基づいて画像信号を供給する機能を有する。
<< Drive circuit SD (1) >>
The drive circuit SD (1) has a function of supplying an image signal based on the information V11.
駆動回路SD(1)は、画像信号を生成する機能と、当該画像信号を一の表示素子と電気的に接続される画素回路に供給する機能を備える。 The driver circuit SD (1) has a function of generating an image signal and a function of supplying the image signal to a pixel circuit that is electrically connected to one display element.
例えば、デジタル演算部(Digital Block)を駆動回路SD(1)に用いることができる。デジタル演算部は、例えば、シリアルデータをパラレルデータに変換する機能を備える。具体的には、シフトレジスタ等のさまざまな順序回路等をデジタル演算部に用いることができる。 For example, a digital operation unit (Digital Block) can be used for the drive circuit SD (1). The digital arithmetic unit has a function of converting serial data into parallel data, for example. Specifically, various sequential circuits such as a shift register can be used for the digital arithmetic unit.
例えば、シリコン基板上に形成された集積回路を駆動回路SD(1)に用いることができる。 For example, an integrated circuit formed over a silicon substrate can be used for the drive circuit SD (1).
具体的には、下記の半導体装置を駆動回路SD(1)に用いることができる。 Specifically, the following semiconductor device can be used for the drive circuit SD (1).
《半導体装置の構成例1.》
半導体装置は、デジタルアナログ変換回路DAC(1)を備える(図1参照)。半導体装置は、第1の端子Tm11、第2の端子Tm12および第3の端子Tm13を備える。また、半導体装置はトランジスタTr1を備える(図2参照)。
<< Configuration Example 1 of Semiconductor Device >>
The semiconductor device includes a digital-analog conversion circuit DAC (1) (see FIG. 1). The semiconductor device includes a first terminal Tm11, a second terminal Tm12, and a third terminal Tm13. The semiconductor device includes a transistor Tr1 (see FIG. 2).
第1の端子Tm11は、デジタルアナログ変換回路DAC(1)と電気的に接続される(図1参照)。 The first terminal Tm11 is electrically connected to the digital / analog conversion circuit DAC (1) (see FIG. 1).
第2の端子Tm12はトランジスタTr1のソース電極またはドレイン電極と電気的に接続され、第2の端子Tm12は信号線S1(j)と電気的に接続される(図2参照)。 The second terminal Tm12 is electrically connected to the source electrode or the drain electrode of the transistor Tr1, and the second terminal Tm12 is electrically connected to the signal line S1 (j) (see FIG. 2).
第3の端子Tm13はトランジスタTr2のゲート電極と電気的に接続される。 The third terminal Tm13 is electrically connected to the gate electrode of the transistor Tr2.
これにより、デジタル信号を所定の電圧に変換したアナログ信号を一の信号線に供給することができる。デジタルアナログ変換回路に用いるトランジスタを形成する工程において、第1のトランジスタを形成することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thereby, an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to one signal line. In the step of forming a transistor used for the digital-analog converter circuit, the first transistor can be formed. As a result, a novel display panel that is highly convenient or reliable can be provided.
例えば、COG(Chip on glass)法またはCOF(Chip on Film)法を用いて、半導体装置を信号線S1(j)と電気的に接続することができる。具体的には、異方性導電膜を用いて、半導体装置を信号線S1(j)と電気的に接続することができる。 For example, the semiconductor device can be electrically connected to the signal line S1 (j) by using a COG (Chip on glass) method or a COF (Chip on Film) method. Specifically, the semiconductor device can be electrically connected to the signal line S1 (j) using an anisotropic conductive film.
《駆動回路GD》
駆動回路GDは、制御情報に基づいて選択信号を供給する機能を有する。
<< Drive circuit GD >>
The drive circuit GD has a function of supplying a selection signal based on the control information.
一例を挙げれば、制御情報に基づいて、30Hz以上、好ましくは60Hz以上の頻度で一の走査線に選択信号を供給する機能を備える。これにより、動画像をなめらかに表示することができる。 For example, a function of supplying a selection signal to one scanning line at a frequency of 30 Hz or higher, preferably 60 Hz or higher is provided based on the control information. Thereby, a moving image can be displayed smoothly.
例えば、制御情報に基づいて、30Hz未満、好ましくは1Hz未満、より好ましくは一分に一回未満の頻度で一の走査線に選択信号を供給する機能を備える。これにより、フリッカーが抑制された状態で静止画像を表示することができる。 For example, a function of supplying a selection signal to one scanning line at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute based on the control information is provided. Thereby, a still image can be displayed in a state where flicker is suppressed.
ところで、フレーム周波数を可変にすることができる。または、例えば、1Hz以上120Hz以下のフレーム周波数で表示をすることができる。または、プログレッシブ方式を用いて、120Hzのフレーム周波数で表示をすることができる。または、国際規格であるRecommendationITU−R BT.2020−2を満たす、極めて高解像度な表示をすることができる。または、極めて高解像度な表示をすることができる。 By the way, the frame frequency can be made variable. Alternatively, for example, display can be performed at a frame frequency of 1 Hz to 120 Hz. Alternatively, display can be performed at a frame frequency of 120 Hz using a progressive method. Alternatively, Recommendation ITU-R BT. An extremely high-resolution display that satisfies 2020-2 can be performed. Alternatively, extremely high resolution display can be performed.
《表示領域231の構成例2.》
表示領域231は、一群の複数の画素702(i,1)乃至画素702(i,n)、他の一群の複数の画素702(1,j)乃至画素702(m,j)および走査線G1(i)を備える(図1参照)。
<< Configuration Example of Display Area 231 >>
The display region 231 includes a group of a plurality of pixels 702 (i, 1) to 702 (i, n), another group of a plurality of pixels 702 (1, j) to pixels 702 (m, j), and a scanning line G1. (I) is provided (see FIG. 1).
一群の複数の画素702(i,1)乃至画素702(i,n)は、行方向(図中に矢印R1で示す方向)に配設される。一群の複数の画素702(i,1)乃至画素702(i,n)は、画素702(i,j)を含む。 A group of the plurality of pixels 702 (i, 1) to 702 (i, n) is arranged in a row direction (a direction indicated by an arrow R1 in the drawing). A group of the plurality of pixels 702 (i, 1) to 702 (i, n) includes the pixel 702 (i, j).
他の一群の複数の画素702(1,j)乃至画素702(m,j)は、行方向と交差する列方向(図中に矢印C1で示す方向)に配設される。 Another group of the plurality of pixels 702 (1, j) to 702 (m, j) is arranged in a column direction (direction indicated by an arrow C1 in the drawing) intersecting the row direction.
走査線G1(i)は、一群の複数の画素702(i,1)乃至画素702(i,n)と電気的に接続される。 The scan line G1 (i) is electrically connected to a group of the plurality of pixels 702 (i, 1) to 702 (i, n).
信号線S1(j)は、他の一群の複数の画素702(1,j)乃至画素702(m,j)と電気的に接続される。 The signal line S1 (j) is electrically connected to the other group of the plurality of pixels 702 (1, j) to 702 (m, j).
これにより、他の一群の複数の画素に、デジタル信号を所定の電圧に変換したアナログ信号を供給することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thus, an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to the other group of pixels. As a result, a novel display panel that is highly convenient or reliable can be provided.
《表示領域231の構成例3.》
表示領域231は、複数の画素を行列状に備える。例えば、表示領域231は7600個以上の画素を行方向に備え、4300個以上の画素を列方向に備える。例えば、7680個の画素を行方向に備え、4320個の画素を列方向に備える。
<< Configuration Example of Display Area 231 3. >>
The display area 231 includes a plurality of pixels in a matrix. For example, the display area 231 includes 7600 or more pixels in the row direction and 4300 or more pixels in the column direction. For example, 7680 pixels are provided in the row direction, and 4320 pixels are provided in the column direction.
これにより、例えば、ハイビジョン画像または4K画像より数が多い画素に、劣化が抑制された画像信号を供給することができる。または、画像信号の劣化を抑制しながら、画素に画像信号を高速に供給することができる。または、高精細な画像を表示することができる。または、60Hz以上、好ましくは120Hz以上のリフレッシュレートで表示をすることができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thereby, for example, an image signal in which deterioration is suppressed can be supplied to pixels having a larger number than a high-vision image or a 4K image. Alternatively, the image signal can be supplied to the pixels at high speed while suppressing the deterioration of the image signal. Alternatively, a high-definition image can be displayed. Alternatively, display can be performed at a refresh rate of 60 Hz or higher, preferably 120 Hz or higher. As a result, a novel display panel that is highly convenient or reliable can be provided.
<表示パネルの構成例3.>
本実施の形態で説明する表示パネル700は、複数の画素を備える。当該複数の画素は、色相が互いに異なる色を表示する機能を備える。または、当該複数の画素を用いて、各々その画素では表示できない色相の色を、加法混色により表示することができる。
<Configuration Example of Display Panel 3. >
A display panel 700 described in this embodiment includes a plurality of pixels. The plurality of pixels have a function of displaying colors having different hues. Alternatively, by using the plurality of pixels, hue colors that cannot be displayed by the pixels can be displayed by additive color mixing.
《表示領域231の構成例4.》
表示領域231は、画素702(i,j)、画素702(i,j+1)および画素702(i,j+2)を備える(図4(A)および図4(C)参照)。
<< Configuration Example of Display Area 231 4. >>
The display region 231 includes a pixel 702 (i, j), a pixel 702 (i, j + 1), and a pixel 702 (i, j + 2) (see FIGS. 4A and 4C).
画素702(i,j)は、CIE1931色度座標における色度xが0.680より大きく0.720以下、色度yが0.260以上0.320以下の色を表示する。 The pixel 702 (i, j) displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of greater than 0.680 and less than or equal to 0.720, and a chromaticity y of 0.260 to 0.320.
画素702(i,j+1)は、CIE1931色度座標における色度xが0.130以上0.250以下、色度yが0.710より大きく0.810以下の色を表示する。 The pixel 702 (i, j + 1) displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of 0.130 or more and 0.250 or less, and a chromaticity y of greater than 0.710 and 0.810 or less.
画素702(i,j+2)は、CIE1931色度座標における色度xが0.120以上0.170以下、色度yが0.020以上0.060未満の色を表示する。 The pixel 702 (i, j + 2) displays a color having a chromaticity x of 0.120 to 0.170 and a chromaticity y of 0.020 to less than 0.060 in the CIE 1931 chromaticity coordinates.
なお、色相が異なる色を表示することができる複数の画素を混色に用いる場合において、それぞれの画素を副画素と言い換えることができる。また、複数の副画素を一組にして、画素と言い換えることができる。 Note that in the case where a plurality of pixels that can display colors having different hues are used for color mixing, each pixel can be referred to as a sub-pixel. In addition, a plurality of sub-pixels can be referred to as a pixel.
例えば、画素702(i,j)、画素702(i,j+1)または画素702(i,j+2)を副画素と言い換えることができ、画素702(i,j)、画素702(i,j+1)および画素702(i,j+2)を一組にして、画素703(i,k)と言い換えることができる(図4(C)参照)。 For example, the pixel 702 (i, j), the pixel 702 (i, j + 1), or the pixel 702 (i, j + 2) can be rephrased as a sub-pixel, and the pixel 702 (i, j), the pixel 702 (i, j + 1), and The pixel 702 (i, j + 2) can be referred to as a pixel 703 (i, k) as a set (see FIG. 4C).
具体的には、青色を表示する副画素、緑色を表示する副画素および赤色を表示する副画素を一組にして、画素703(i,k)に用いることができる。また、シアンを表示する副画素、マゼンタを表示する副画素およびイエローを表示する副画素を一組にして、画素703(i,k)に用いることができる。 Specifically, a set of a subpixel that displays blue, a subpixel that displays green, and a subpixel that displays red can be used for the pixel 703 (i, k). Further, a sub-pixel for displaying cyan, a sub-pixel for displaying magenta, and a sub-pixel for displaying yellow can be used as a set for the pixel 703 (i, k).
また、例えば、白色を表示する副画素等を上記の一組に加えて、画素に用いることができる。 Further, for example, a sub-pixel for displaying white can be used for the pixel in addition to the above set.
また、画素702(i,j)、画素702(i,j+1)および画素702(i,j+2)を、CIE色度図(x,y)におけるBT.2020の色域に対する面積比が80%以上、または、該色域に対するカバー率が75%以上になるように備える。好ましくは、面積比が90%以上、または、カバー率が85%以上になるように備える。 In addition, the pixel 702 (i, j), the pixel 702 (i, j + 1), and the pixel 702 (i, j + 2) are represented by BT. In the CIE chromaticity diagram (x, y). The area ratio to the 2020 color gamut is 80% or more, or the coverage ratio to the color gamut is 75% or more. Preferably, the area ratio is 90% or more, or the coverage is 85% or more.
<表示パネルの構成例4.>
また、表示パネルは、複数の駆動回路を有することができる。例えば、表示パネル700は、駆動回路GDAおよび駆動回路GDBを有する(図5参照)。また、デジタル演算部(Digital Block)を駆動回路SD(1)に用いることができる。
<Configuration Example of Display Panel 4. >
In addition, the display panel can include a plurality of driver circuits. For example, the display panel 700 includes a drive circuit GDA and a drive circuit GDB (see FIG. 5). In addition, a digital operation unit (Digital Block) can be used for the drive circuit SD (1).
また、例えば、複数の駆動回路を備える場合、駆動回路GDAが選択信号を供給する頻度と、駆動回路GDBが選択信号を供給する頻度とを、異ならせることができる。具体的には、静止画像を表示する一の領域に選択信号を供給する頻度より高い頻度で、動画像を表示する他の領域に選択信号を供給することができる。これにより、一の領域にフリッカーが抑制された状態で静止画像を表示し、他の領域に滑らかに動画像を表示することができる。 For example, when a plurality of drive circuits are provided, the frequency with which the drive circuit GDA supplies the selection signal and the frequency with which the drive circuit GDB supplies the selection signal can be made different. Specifically, the selection signal can be supplied to another region displaying the moving image at a frequency higher than the frequency of supplying the selection signal to one region displaying the still image. Thereby, a still image can be displayed in a state where flicker is suppressed in one area, and a moving image can be displayed smoothly in another area.
<表示パネルの構成例5.>
本実施の形態で説明する表示パネル700の構成について、図4、図6および図7を参照しながら説明する。
<Configuration Example of Display Panel 5. >
The structure of the display panel 700 described in this embodiment will be described with reference to FIGS.
図4(A)は本発明の一態様の表示パネルの構成を説明する上面図であり、図4(B)は図4(A)の一部を説明する上面図であり、図4(C)は他の一部を説明する上面図である。 4A is a top view illustrating a structure of a display panel of one embodiment of the present invention, and FIG. 4B is a top view illustrating part of FIG. 4A. FIG. ) Is a top view illustrating another part.
図6(A)は、図4(A)の切断線X1−X2、切断線X3−X4、切断線X9−X10における断面図であり、図6(B)は画素回路を説明する回路図である。 6A is a cross-sectional view taken along cutting lines X1-X2, X3-X4, and X9-X10 in FIG. 4A, and FIG. 6B is a circuit diagram illustrating a pixel circuit. is there.
図7は本発明の一態様の表示パネルの構成を説明する断面図である。図7(A)は画素の構成を説明する断面図であり、図7(B)は図7(A)の一部を説明する断面図である。また、図7(C)は図2に示すバッファアンプBAに用いることができるトランジスタの構成を説明する断面図である。 FIG. 7 is a cross-sectional view illustrating the structure of a display panel of one embodiment of the present invention. FIG. 7A is a cross-sectional view illustrating a structure of a pixel, and FIG. 7B is a cross-sectional view illustrating a part of FIG. FIG. 7C is a cross-sectional view illustrating a structure of a transistor that can be used in the buffer amplifier BA illustrated in FIG.
表示パネル700は、駆動回路SD(1)、駆動回路GDおよび端子519Bを備える(図4(A)参照)。 The display panel 700 includes a driver circuit SD (1), a driver circuit GD, and a terminal 519B (see FIG. 4A).
また、表示パネル700は、基板510、基板770、機能層520および絶縁膜501Cを備える(図7(A)参照)。また、表示パネル700は、機能層720、機能膜770Pおよび機能膜770Dを備える。なお、表示パネル700は、バッファアンプBAを備える(図2参照)。バッファアンプBAは、トランジスタTr2を絶縁膜501C上に備える(図7(C)参照)。 The display panel 700 includes a substrate 510, a substrate 770, a functional layer 520, and an insulating film 501C (see FIG. 7A). The display panel 700 includes a functional layer 720, a functional film 770P, and a functional film 770D. The display panel 700 includes a buffer amplifier BA (see FIG. 2). The buffer amplifier BA includes a transistor Tr2 over the insulating film 501C (see FIG. 7C).
絶縁膜501Cは、基板510および基板770の間に挟まれる領域を備え、機能層520は、絶縁膜501Cおよび基板770の間に挟まれる領域を備える。 The insulating film 501C includes a region sandwiched between the substrate 510 and the substrate 770, and the functional layer 520 includes a region sandwiched between the insulating film 501C and the substrate 770.
《画素の構成例1.》
画素702(i,j)は機能層520および表示素子750(i,j)を備える(図6(A)参照)。
<< Pixel Configuration Example 1. >>
The pixel 702 (i, j) includes a functional layer 520 and a display element 750 (i, j) (see FIG. 6A).
《機能層520の構成例1.》
機能層520は、画素回路530(i,j)、絶縁膜521Aおよび絶縁膜521Bを備える(図6(A)および図7(A)参照)。
<< Configuration Example 1 of Functional Layer 520 >>
The functional layer 520 includes a pixel circuit 530 (i, j), an insulating film 521A, and an insulating film 521B (see FIGS. 6A and 7A).
《画素回路530(i,j)の構成例1.》
例えば、スイッチ、トランジスタ、ダイオード、抵抗素子、インダクタまたは容量素子等を画素回路530(i,j)に用いることができる。
<< Configuration Example 1 of Pixel Circuit 530 (i, j) >>
For example, a switch, a transistor, a diode, a resistor, an inductor, a capacitor, or the like can be used for the pixel circuit 530 (i, j).
画素回路530(i,j)は、表示素子750(i,j)を駆動する機能を備える。例えば、図6(B)に示す画素回路は、液晶表示素子を駆動する機能を備える。 The pixel circuit 530 (i, j) has a function of driving the display element 750 (i, j). For example, the pixel circuit illustrated in FIG. 6B has a function of driving a liquid crystal display element.
画素回路530(i,j)は、スイッチSW1および容量素子C11を含む。 Pixel circuit 530 (i, j) includes a switch SW1 and a capacitor C11.
例えば、トランジスタをスイッチSW1に用いることができる(図6(B)、図7(A)および図7(B)参照)。 For example, a transistor can be used for the switch SW1 (see FIGS. 6B, 7A, and 7B).
《トランジスタ》
トランジスタは、半導体膜508、導電膜504、導電膜512Aおよび導電膜512Bを備える(図7(B)参照)。
<Transistor>
The transistor includes a semiconductor film 508, a conductive film 504, a conductive film 512A, and a conductive film 512B (see FIG. 7B).
半導体膜508は、導電膜512Aと電気的に接続される領域508A、導電膜512Bと電気的に接続される領域508Bを備える。半導体膜508は、領域508Aおよび領域508Bの間に領域508Cを備える。 The semiconductor film 508 includes a region 508A electrically connected to the conductive film 512A and a region 508B electrically connected to the conductive film 512B. The semiconductor film 508 includes a region 508C between the region 508A and the region 508B.
導電膜504は領域508Cと重なる領域を備え、導電膜504はゲート電極の機能を備える。 The conductive film 504 includes a region overlapping with the region 508C, and the conductive film 504 functions as a gate electrode.
絶縁膜506は、半導体膜508および導電膜504の間に挟まれる領域を備える。絶縁膜506はゲート絶縁膜の機能を備える。 The insulating film 506 includes a region sandwiched between the semiconductor film 508 and the conductive film 504. The insulating film 506 has a function of a gate insulating film.
導電膜512Aはソース電極の機能またはドレイン電極の機能の一方を備え、導電膜512Bはソース電極の機能またはドレイン電極の機能の他方を備える。 The conductive film 512A has one of the function of the source electrode and the function of the drain electrode, and the conductive film 512B has the other of the function of the source electrode and the function of the drain electrode.
なお、例えば、同一の工程で形成することができる半導体膜を駆動回路および画素回路のトランジスタに用いることができる。 Note that, for example, a semiconductor film that can be formed in the same step can be used for a driver circuit and a transistor of a pixel circuit.
例えば、ボトムゲート型のトランジスタまたはトップゲート型のトランジスタなどを駆動回路のトランジスタ、バッファアンプBAのトランジスタまたは画素回路のトランジスタに用いることができる。具体的には、画素回路530(i,j)が含むトランジスタTr3が備える形式のトランジスタを、トランジスタTr2に用いることができる。 For example, a bottom-gate transistor, a top-gate transistor, or the like can be used for a driver circuit transistor, a buffer amplifier BA transistor, or a pixel circuit transistor. Specifically, a transistor of a type included in the transistor Tr3 included in the pixel circuit 530 (i, j) can be used as the transistor Tr2.
《半導体膜508》
例えば、14族の元素を含む半導体を半導体膜508に用いることができる。具体的には、シリコンを含む半導体を半導体膜508に用いることができる。例えば、単結晶シリコン、ポリシリコン、微結晶シリコンまたはアモルファスシリコンなどを半導体膜に用いることができる。
<< Semiconductor film 508 >>
For example, a semiconductor containing a Group 14 element can be used for the semiconductor film 508. Specifically, a semiconductor containing silicon can be used for the semiconductor film 508. For example, single crystal silicon, polysilicon, microcrystalline silicon, amorphous silicon, or the like can be used for the semiconductor film.
なお、半導体にポリシリコンを用いるトランジスタの作製に要する温度は、半導体に単結晶シリコンを用いるトランジスタに比べて低い。 Note that the temperature required for manufacturing a transistor using polysilicon as a semiconductor is lower than that of a transistor using single crystal silicon as a semiconductor.
また、ポリシリコンを半導体に用いるトランジスタの電界効果移動度は、アモルファスシリコンを半導体に用いるトランジスタに比べて高い。これにより、画素の開口率を向上することができる。また、極めて高い精細度で設けられた画素と、ゲート駆動回路およびソース駆動回路を同一の基板上に形成することができる。その結果、電子機器を構成する部品数を低減することができる。 In addition, the field effect mobility of a transistor using polysilicon as a semiconductor is higher than that of a transistor using amorphous silicon as a semiconductor. Thereby, the aperture ratio of the pixel can be improved. In addition, a pixel provided with extremely high definition, a gate driver circuit, and a source driver circuit can be formed over the same substrate. As a result, the number of parts constituting the electronic device can be reduced.
また、ポリシリコンを半導体に用いるトランジスタの信頼性は、アモルファスシリコンを半導体に用いるトランジスタに比べて優れる。 Further, the reliability of a transistor using polysilicon as a semiconductor is superior to a transistor using amorphous silicon as a semiconductor.
また、化合物半導体を用いるトランジスタを利用することができる。具体的には、ガリウムヒ素を含む半導体を半導体膜に用いることができる。 In addition, a transistor using a compound semiconductor can be used. Specifically, a semiconductor containing gallium arsenide can be used for the semiconductor film.
また、有機半導体を用いるトランジスタを利用することができる。具体的には、ポリアセン類またはグラフェンを含む有機半導体を半導体膜に用いることができる。 In addition, a transistor using an organic semiconductor can be used. Specifically, an organic semiconductor containing polyacenes or graphene can be used for the semiconductor film.
例えば、酸化物半導体を用いるトランジスタを利用することができる。具体的には、インジウムを含む酸化物半導体またはインジウムとガリウムと亜鉛を含む酸化物半導体を半導体膜に用いることができる。 For example, a transistor including an oxide semiconductor can be used. Specifically, an oxide semiconductor containing indium or an oxide semiconductor containing indium, gallium, and zinc can be used for the semiconductor film.
一例を挙げれば、オフ状態におけるリーク電流が、半導体膜にアモルファスシリコンを用いたトランジスタより小さいトランジスタを用いることができる。具体的には、酸化物半導体を半導体膜に用いたトランジスタを用いることができる。 As an example, a transistor whose leakage current in an off state is smaller than that of a transistor using amorphous silicon as a semiconductor film can be used. Specifically, a transistor in which an oxide semiconductor is used for a semiconductor film can be used.
これにより、アモルファスシリコンを半導体膜に用いたトランジスタを利用する画素回路と比較して、画素回路が画像信号を保持することができる時間を長くすることができる。具体的には、フリッカーの発生を抑制しながら、選択信号を30Hz未満、好ましくは1Hz未満、より好ましくは一分に一回未満の頻度で供給することができる。その結果、情報処理装置の使用者に蓄積する疲労を低減することができる。また、駆動に伴う消費電力を低減することができる。 Accordingly, as compared with a pixel circuit using a transistor using amorphous silicon as a semiconductor film, the time during which the pixel circuit can hold an image signal can be lengthened. Specifically, the selection signal can be supplied at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute while suppressing the occurrence of flicker. As a result, fatigue accumulated in the user of the information processing apparatus can be reduced. In addition, power consumption associated with driving can be reduced.
例えば、インジウム、ガリウムおよび亜鉛を含む厚さ25nmの膜を、半導体膜508に用いることができる。 For example, a 25-nm-thick film containing indium, gallium, and zinc can be used for the semiconductor film 508.
例えば、タンタルおよび窒素を含む厚さ10nmの膜と、銅を含む厚さ300nmの膜と、を積層した導電膜を導電膜504に用いることができる。なお、銅を含む膜は、絶縁膜506との間に、タンタルおよび窒素を含む膜を挟む領域を備える。 For example, a conductive film in which a 10-nm-thick film containing tantalum and nitrogen and a 300-nm-thick film containing copper are stacked can be used for the conductive film 504. Note that the film containing copper includes a region between which the film containing tantalum and nitrogen is sandwiched between the film containing copper.
例えば、シリコンおよび窒素を含む厚さ400nmの膜と、シリコン、酸素および窒素を含む厚さ200nmの膜と、を積層した積層膜を、絶縁膜506に用いることができる。なお、シリコンおよび窒素を含む膜は、半導体膜508との間に、シリコン、酸素および窒素を含む膜を挟む領域を備える。 For example, a stacked film in which a 400-nm-thick film containing silicon and nitrogen and a 200-nm-thick film containing silicon, oxygen, and nitrogen are stacked can be used for the insulating film 506. Note that the film containing silicon and nitrogen includes a region between the semiconductor film 508 and the film containing silicon, oxygen, and nitrogen.
例えば、タングステンを含む厚さ50nmの膜と、アルミニウムを含む厚さ400nmの膜と、チタンを含む厚さ100nmの膜と、をこの順で積層した導電膜を、導電膜512Aまたは導電膜512Bに用いることができる。なお、タングステンを含む膜は、半導体膜508と接する領域を備える。 For example, a conductive film in which a 50-nm-thick film containing tungsten, a 400-nm-thick film containing aluminum, and a 100-nm-thick film containing titanium are stacked in this order as the conductive film 512A or the conductive film 512B. Can be used. Note that the film containing tungsten includes a region in contact with the semiconductor film 508.
ところで、例えば、アモルファスシリコンを半導体に用いるボトムゲート型のトランジスタの製造ラインは、酸化物半導体を半導体に用いるボトムゲート型のトランジスタの製造ラインに容易に改造できる。また、例えばポリシリコンを半導体に用いるトップゲート型のトランジスタの製造ラインは、酸化物半導体を半導体に用いるトップゲート型のトランジスタの製造ラインに容易に改造できる。いずれの改造も、既存の製造ラインを有効に活用することができる。 By the way, for example, a bottom-gate transistor production line using amorphous silicon as a semiconductor can be easily modified to a bottom-gate transistor production line using an oxide semiconductor as a semiconductor. For example, a top gate transistor production line using polysilicon as a semiconductor can be easily modified to a top gate transistor production line using an oxide semiconductor as a semiconductor. Both modifications can make effective use of existing production lines.
《表示素子750(i,j)の構成例》
表示素子750(i,j)は、機能層520と重なる領域を備える(図6(A)および図7(A)参照)。また、表示素子750(i,j)は、画素回路530(i,j)と電気的に接続される。
<< Configuration Example of Display Element 750 (i, j) >>
The display element 750 (i, j) includes a region overlapping with the functional layer 520 (see FIGS. 6A and 7A). In addition, the display element 750 (i, j) is electrically connected to the pixel circuit 530 (i, j).
例えば、光の反射または透過を制御する機能を備える表示素子を、表示素子750(i,j)に用いることができる。具体的には、液晶素子と偏光板を組み合わせた構成またはシャッター方式のMEMS表示素子、光干渉方式のMEMS表示素子等を用いることができる。 For example, a display element having a function of controlling reflection or transmission of light can be used for the display element 750 (i, j). Specifically, a configuration in which a liquid crystal element and a polarizing plate are combined, a shutter-type MEMS display element, an optical interference-type MEMS display element, or the like can be used.
例えば、反射型の液晶表示素子、マイクロカプセル方式、電気泳動方式、エレクトロウエッティング方式などを用いる表示素子を、表示素子750(i,j)に用いることができる。反射型の表示素子を用いることにより、表示パネルの消費電力を抑制することができる。 For example, a display element using a reflective liquid crystal display element, a microcapsule method, an electrophoresis method, an electrowetting method, or the like can be used for the display element 750 (i, j). By using a reflective display element, power consumption of the display panel can be suppressed.
例えば、透過型の液晶表示素子を表示素子750(i,j)に用いることができる。また、表示パネル700は、バックライトBLが射出する光の透過を制御して、画像を表示する機能を備える。 For example, a transmissive liquid crystal display element can be used for the display element 750 (i, j). Further, the display panel 700 has a function of displaying an image by controlling transmission of light emitted from the backlight BL.
例えば、IPS(In−Plane−Switching)モード、TN(Twisted Nematic)モード、FFS(Fringe Field Switching)モード、ASM(Axially Symmetric aligned Micro−cell)モード、OCB(Optically Compensated Birefringence)モード、FLC(Ferroelectric Liquid Crystal)モード、AFLC(AntiFerroelectric Liquid Crystal)モードなどの駆動方法を用いて駆動することができる液晶素子を用いることができる。 For example, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, FFS (Fringe Field Switched) mode, ASM (Axially Symmetrically Applied Micro-cell) mode, OCB (OpticBridge) mode. A liquid crystal element that can be driven using a driving method such as a Crystal) mode or an AFLC (Antiferroelectric Liquid Crystal) mode can be used.
また、例えば垂直配向(VA)モード、具体的には、MVA(Multi−Domain Vertical Alignment)モード、PVA(Patterned Vertical Alignment)モード、ECB(Electrically Controlled Birefringence)モード、CPA(Continuous Pinwheel Alignment)モード、ASV(Advanced Super−View)モードなどの駆動方法を用いて駆動することができる液晶素子を用いることができる。 In addition, for example, vertical alignment (VA) mode, specifically, MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, ECB (Electrically Controlled Birefringence ACP mode, CPB mode) A liquid crystal element that can be driven by a driving method such as an (Advanced Super-View) mode can be used.
表示素子750(i,j)は、電極751(i,j)、電極752および液晶材料を含む層753を備える。 The display element 750 (i, j) includes an electrode 751 (i, j), an electrode 752, and a layer 753 containing a liquid crystal material.
電極751(i,j)は、接続部591Aにおいて画素回路530(i,j)と電気的に接続される。 The electrode 751 (i, j) is electrically connected to the pixel circuit 530 (i, j) at the connection portion 591A.
電極752は、液晶材料の配向を制御する電界を、電極751(i,j)との間に形成するように配設される。 The electrode 752 is disposed so as to form an electric field for controlling the alignment of the liquid crystal material between the electrode 751 (i, j).
表示素子750(i,j)は、配向膜AF1および配向膜AF2を備える。 The display element 750 (i, j) includes an alignment film AF1 and an alignment film AF2.
液晶材料を含む層753は、配向膜AF1および配向膜AF2に挟まれる領域を備える。 The layer 753 containing a liquid crystal material includes a region sandwiched between the alignment film AF1 and the alignment film AF2.
例えば、1.0×1013Ω・cm以上、好ましくは1.0×1014Ω・cm以上、さらに好ましくは1.0×1015Ω・cm以上の固有抵抗率を備える液晶材料を液晶材料を含む層753に用いることができる。これにより、表示素子750(i,j)の透過率の変動を抑制することができる。または、表示素子750(i,j)のチラツキを抑制することができる。または、表示素子750(i,j)を書き換える頻度を低減することができる。 For example, a liquid crystal material having a specific resistivity of 1.0 × 10 13 Ω · cm or more, preferably 1.0 × 10 14 Ω · cm or more, more preferably 1.0 × 10 15 Ω · cm or more is used as the liquid crystal material. The layer 753 containing can be used. Thereby, the fluctuation | variation of the transmittance | permeability of the display element 750 (i, j) can be suppressed. Alternatively, flickering of the display element 750 (i, j) can be suppressed. Alternatively, the frequency of rewriting the display element 750 (i, j) can be reduced.
《構造体KB1》
構造体KB1は、機能層520および基板770の間に所定の間隙を設ける機能を備える。
<< Structure KB1 >>
The structure KB1 has a function of providing a predetermined gap between the functional layer 520 and the substrate 770.
《機能層720》
機能層720は、着色膜CF1、絶縁膜771および遮光膜BMを備える。
<< Functional layer 720 >>
The functional layer 720 includes a coloring film CF1, an insulating film 771, and a light shielding film BM.
着色膜CF1は、基板770および表示素子750(i,j)の間に挟まれる領域を備える。 The colored film CF1 includes a region sandwiched between the substrate 770 and the display element 750 (i, j).
遮光膜BMは、画素702(i,j)と重なる領域に開口部を備える。 The light shielding film BM includes an opening in a region overlapping with the pixel 702 (i, j).
絶縁膜771は、着色膜CF1と液晶材料を含む層753の間に挟まれる領域または遮光膜BMと液晶材料を含む層753の間に挟まれる領域を備える。これにより、着色膜CF1の厚さに基づく凹凸を平坦にすることができる。または、遮光膜BMまたは着色膜CF1等から液晶材料を含む層753への不純物の拡散を、抑制することができる。 The insulating film 771 includes a region sandwiched between the colored film CF1 and the layer 753 containing a liquid crystal material or a region sandwiched between the light shielding film BM and the layer 753 containing a liquid crystal material. Thereby, the unevenness | corrugation based on the thickness of colored film CF1 can be made flat. Alternatively, impurity diffusion from the light-blocking film BM, the coloring film CF1, or the like to the layer 753 containing a liquid crystal material can be suppressed.
《機能膜770P、機能膜770D等》
機能膜770Pは、表示素子750(i,j)と重なる領域を備える。また、機能膜770Dは、表示素子750(i,j)と重なる領域を備える。
<< Functional film 770P, Functional film 770D, etc. >>
The functional film 770P includes a region overlapping with the display element 750 (i, j). The functional film 770D includes a region overlapping with the display element 750 (i, j).
例えば、反射防止フィルム、偏光フィルム、位相差フィルム、光拡散フィルムまたは集光フィルム等を機能膜770Pまたは機能膜770Dに用いることができる。 For example, an antireflection film, a polarizing film, a retardation film, a light diffusion film, a light collecting film, or the like can be used for the functional film 770P or the functional film 770D.
具体的には、円偏光フィルムを機能膜770Pに用いることができる。また、光拡散フィルムを機能膜770Dに用いることができる。 Specifically, a circularly polarizing film can be used for the functional film 770P. In addition, a light diffusion film can be used for the functional film 770D.
また、ゴミの付着を抑制する帯電防止膜、汚れを付着しにくくする撥水性の膜、反射防止膜(アンチ・リフレクション膜)、非光沢処理膜(アンチ・グレア膜)、使用に伴う傷の発生を抑制するハードコート膜などを、機能膜770Pに用いることができる。 In addition, antistatic film that suppresses adhesion of dust, water-repellent film that makes it difficult to adhere dirt, antireflection film (anti-reflection film), non-glossy film (anti-glare film), and scratches caused by use A hard coat film or the like that suppresses the above can be used for the functional film 770P.
<表示パネルの構成例6.>
本実施の形態で説明する表示パネル700の構成について、図4、図8および図9を参照しながら説明する。
<Configuration Example of Display Panel 6. >
The structure of the display panel 700 described in this embodiment will be described with reference to FIGS.
図4(A)は本発明の一態様の表示パネルの構成を説明する上面図であり、図4(B)は図4(A)の一部を説明する上面図であり、図4(C)は他の一部を説明する上面図である。 4A is a top view illustrating a structure of a display panel of one embodiment of the present invention, and FIG. 4B is a top view illustrating part of FIG. 4A. FIG. ) Is a top view illustrating another part.
図8(A)は、図4(A)の切断線X1−X2、切断線X3−X4、切断線X9−X10における断面図であり、図8(B)は画素回路を説明する回路図である。 8A is a cross-sectional view taken along cutting lines X1-X2, X3-X4, and X9-X10 in FIG. 4A, and FIG. 8B is a circuit diagram illustrating a pixel circuit. is there.
図9は本発明の一態様の表示パネルの構成を説明する断面図である。図9(A)は画素の構成を説明する断面図であり、図9(B)は図9(A)の一部を説明する断面図である。また、図9(C)は図2に示すバッファアンプBAに用いることができるトランジスタの構成を説明する断面図である。 FIG. 9 is a cross-sectional view illustrating a structure of a display panel of one embodiment of the present invention. FIG. 9A is a cross-sectional view illustrating a structure of a pixel, and FIG. 9B is a cross-sectional view illustrating part of FIG. 9A. FIG. 9C is a cross-sectional view illustrating a structure of a transistor that can be used in the buffer amplifier BA illustrated in FIG.
表示パネル700は、駆動回路SD(1)、駆動回路GDおよび端子519Bを備える(図4(A)参照)。 The display panel 700 includes a driver circuit SD (1), a driver circuit GD, and a terminal 519B (see FIG. 4A).
また、表示パネル700は、基板510、基板770、機能層520および絶縁膜501Cを備える(図9(A)および図9(B)参照)。また、表示パネル700は、機能膜770Pを備えることができる。なお、表示パネル700は、バッファアンプBAを備える(図2参照)。バッファアンプBAは、トランジスタTr2を絶縁膜501C上に備える(図9(C)参照)。 The display panel 700 includes a substrate 510, a substrate 770, a functional layer 520, and an insulating film 501C (see FIGS. 9A and 9B). In addition, the display panel 700 can include a functional film 770P. The display panel 700 includes a buffer amplifier BA (see FIG. 2). The buffer amplifier BA includes a transistor Tr2 over the insulating film 501C (see FIG. 9C).
絶縁膜501Cは、基板510および基板770の間に挟まれる領域を備え、機能層520は、絶縁膜501Cおよび基板770の間に挟まれる領域を備える。 The insulating film 501C includes a region sandwiched between the substrate 510 and the substrate 770, and the functional layer 520 includes a region sandwiched between the insulating film 501C and the substrate 770.
《画素の構成例2.》
画素702(i,j)は、機能層520および表示素子550(i,j)を備える(図8(A)参照)。
<< Pixel Configuration Example 2. >>
The pixel 702 (i, j) includes a functional layer 520 and a display element 550 (i, j) (see FIG. 8A).
《機能層520の構成例2.》
機能層520は、画素回路530(i,j)、絶縁膜521、絶縁膜528および着色膜CF1を備える(図8(A)および図9(A)参照)。
<< Configuration Example 2 of Functional Layer 520 >>
The functional layer 520 includes a pixel circuit 530 (i, j), an insulating film 521, an insulating film 528, and a coloring film CF1 (see FIGS. 8A and 9A).
《画素回路530(i,j)の構成例2.》
例えば、スイッチ、トランジスタ、ダイオード、抵抗素子、インダクタまたは容量素子等を画素回路530(i,j)に用いることができる。
<< Configuration Example of Pixel Circuit 530 (i, j) 2. >>
For example, a switch, a transistor, a diode, a resistor, an inductor, a capacitor, or the like can be used for the pixel circuit 530 (i, j).
画素回路は530(i,j)は、表示素子550(i,j)を駆動する機能を備える。例えば、図8(B)に示す画素回路を用いて、有機エレクトロルミネッセンス素子を駆動することができる。 The pixel circuit 530 (i, j) has a function of driving the display element 550 (i, j). For example, an organic electroluminescent element can be driven using the pixel circuit illustrated in FIG.
画素回路530(i,j)は、トランジスタMおよび容量素子C12を含む(図8(B)、図9(A)および図9(B)参照)。 The pixel circuit 530 (i, j) includes a transistor M and a capacitor C12 (see FIGS. 8B, 9A, and 9B).
《トランジスタM》
トランジスタMは、半導体膜508、導電膜504、導電膜512Aおよび導電膜512Bを備える(図9(B)参照)。また、導電膜524を有するトランジスタを画素回路530(i,j)に用いることができる。
<< Transistor M >>
The transistor M includes a semiconductor film 508, a conductive film 504, a conductive film 512A, and a conductive film 512B (see FIG. 9B). In addition, a transistor including the conductive film 524 can be used for the pixel circuit 530 (i, j).
導電膜524は、導電膜504との間に半導体膜508を挟む領域を備える。なお、絶縁膜516は、導電膜524および半導体膜508の間に挟まれる領域を備える。また、例えば、導電膜504と同じ電位を供給する配線に導電膜524を電気的に接続することができる。 The conductive film 524 includes a region in which the semiconductor film 508 is sandwiched between the conductive film 504 and the conductive film 504. Note that the insulating film 516 includes a region sandwiched between the conductive film 524 and the semiconductor film 508. For example, the conductive film 524 can be electrically connected to a wiring that supplies the same potential as the conductive film 504.
《表示素子550(i,j)の構成例》
表示素子550(i,j)は、機能層520と重なる領域を備える(図8(A)および図9(A)参照)。また、表示素子550(i,j)は、画素回路530(i,j)と電気的に接続される。
<< Configuration Example of Display Element 550 (i, j) >>
The display element 550 (i, j) includes a region overlapping with the functional layer 520 (see FIGS. 8A and 9A). The display element 550 (i, j) is electrically connected to the pixel circuit 530 (i, j).
例えば、光を射出する機能を備える表示素子を、表示素子550(i,j)に用いることができる(図8(A)参照)。具体的には、有機エレクトロルミネッセンス素子、無機エレクトロルミネッセンス素子または発光ダイオードを表示素子550(i,j)に用いることができる。 For example, a display element having a function of emitting light can be used for the display element 550 (i, j) (see FIG. 8A). Specifically, an organic electroluminescent element, an inorganic electroluminescent element, or a light-emitting diode can be used for the display element 550 (i, j).
例えば、量子ドットを表示素子550(i,j)に用いることができる。具体的には、QDLED(Quabtumn Dot LED)等を用いることができる。これにより、スペクトルの半値幅が狭く、鮮やかな色の光を発することができる。 For example, quantum dots can be used for the display element 550 (i, j). Specifically, QDLED (Quabutum Dot LED) or the like can be used. Thereby, the half value width of a spectrum is narrow and can emit the light of a bright color.
表示素子550(i,j)は、電極551(i,j)、電極552および発光性の材料を含む層553(j)を備える。 The display element 550 (i, j) includes an electrode 551 (i, j), an electrode 552, and a layer 553 (j) containing a light-emitting material.
電極551(i,j)は、接続部591Aにおいて画素回路530(i,j)と電気的に接続される。また、画素回路530(i,j)は、接続部591Bにおいて配線ANOと電気的に接続される。 The electrode 551 (i, j) is electrically connected to the pixel circuit 530 (i, j) at the connection portion 591A. In addition, the pixel circuit 530 (i, j) is electrically connected to the wiring ANO at the connection portion 591B.
例えば、青色の光を発するように積層された積層材料、緑色の光を発するように積層された積層材料または赤色の光を発するように積層された積層材料等を、発光性の材料を含む層553(j)に用いることができる。 For example, a layer containing a light-emitting material such as a laminated material laminated so as to emit blue light, a laminated material laminated so as to emit green light, or a laminated material laminated so as to emit red light. 553 (j).
例えば、信号線S1(j)に沿って列方向に長い帯状の積層材料を、発光性の材料を含む層553(j)に用いることができる。 For example, a strip-shaped stacked material that is long in the column direction along the signal line S1 (j) can be used for the layer 553 (j) containing a light-emitting material.
例えば、白色の光を発するように積層された積層材料を、表示素子550(i,j)に用いることができる。具体的には、青色の光を発する蛍光材料を含む発光性の材料を含む層と、緑色および赤色の光を発する蛍光材料以外の材料を含む層または黄色の光を発する蛍光材料以外の材料を含む層と、を積層した積層材料を、表示素子550(i,j)に用いることができる。 For example, a stacked material stacked to emit white light can be used for the display element 550 (i, j). Specifically, a layer including a light emitting material including a fluorescent material that emits blue light, a layer including a material other than a fluorescent material that emits green and red light, or a material other than a fluorescent material that emits yellow light. A stack material in which the layers including the layers are stacked can be used for the display element 550 (i, j).
《乾燥剤578》
乾燥剤578は、機能層520および基板770の間に挟まれる領域を備える。
<< Dryant 578 >>
The desiccant 578 includes a region sandwiched between the functional layer 520 and the substrate 770.
なお、本実施の形態は、本明細書で示す他の実施の形態と適宜組み合わせることができる。 Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(実施の形態2)
本実施の形態では、本発明の一態様の表示パネルの構成について、図17および図18を参照しながら説明する。
(Embodiment 2)
In this embodiment, the structure of the display panel of one embodiment of the present invention will be described with reference to FIGS.
図17は本発明の一態様の表示パネルの構成を説明する図である。図17(A)は本発明の一態様の表示パネルの構成を説明するブロック図であり、図17(B)は図17(A)に示す画素の構成を説明する回路図である。 FIG. 17 illustrates a structure of a display panel of one embodiment of the present invention. FIG. 17A is a block diagram illustrating a structure of a display panel of one embodiment of the present invention, and FIG. 17B is a circuit diagram illustrating a structure of the pixel illustrated in FIG.
図18(A)は本発明の一態様の表示パネルの駆動回路SD(1)の構成を説明する図であり、図18(B)はデジタルアナログ変換回路の構成を説明する図である。 18A illustrates a structure of the driver circuit SD (1) of the display panel of one embodiment of the present invention, and FIG. 18B illustrates a structure of the digital-analog converter circuit.
<表示パネルの構成例1.>
本実施の形態で説明する表示パネル700は、表示領域231と、デジタルアナログ変換回路DAC(1)と、を有する(図17(A)参照)。また、デジタル演算部(Digital Block)を駆動回路SD(1)に用いることができる。
<Configuration Example of Display Panel 1. >
A display panel 700 described in this embodiment includes a display region 231 and a digital-analog converter circuit DAC (1) (see FIG. 17A). In addition, a digital operation unit (Digital Block) can be used for the drive circuit SD (1).
《表示領域231》
表示領域231は、画素702(i,j)および信号線S1(j)を備える。
<< Display area 231 >>
The display area 231 includes a pixel 702 (i, j) and a signal line S1 (j).
画素702(i,j)は、画素回路530(i,j)を備える(図17(B)参照)。 The pixel 702 (i, j) includes a pixel circuit 530 (i, j) (see FIG. 17B).
画素回路530(i,j)は、トランジスタTr3を備える。 The pixel circuit 530 (i, j) includes a transistor Tr3.
信号線S1(j)は、トランジスタTr3のソース電極またはドレイン電極の一方と電気的に接続される。 The signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr3.
トランジスタTr3は、第3の半導体を備え、第3の半導体は、金属酸化物を含む。例えば、実施の形態3で説明する金属酸化物を用いることができる。 The transistor Tr3 includes a third semiconductor, and the third semiconductor includes a metal oxide. For example, the metal oxide described in Embodiment 3 can be used.
《デジタルアナログ変換回路DAC》
デジタルアナログ変換回路DACは、パラレル信号を供給され、アナログ信号を供給する。
<< Digital-to-analog converter circuit DAC >>
The digital-analog conversion circuit DAC is supplied with a parallel signal and supplies an analog signal.
デジタルアナログ変換回路DACは、パストランジスタ・ロジック回路PTLおよび抵抗ストリングR−stringを備える(図18(A)および図18(B)参照)。 The digital-analog converter circuit DAC includes a pass transistor / logic circuit PTL and a resistor string R-string (see FIGS. 18A and 18B).
抵抗ストリングR−stringは、パストランジスタ・ロジック回路PTLと電気的に接続される。 The resistor string R-string is electrically connected to the pass transistor logic circuit PTL.
パストランジスタ・ロジック回路PTLは、トランジスタTr4を備える。 The pass transistor / logic circuit PTL includes a transistor Tr4.
信号線S1(j)は、トランジスタTr4のソース電極またはドレイン電極の一方と電気的に接続される。 The signal line S1 (j) is electrically connected to one of the source electrode and the drain electrode of the transistor Tr4.
トランジスタTr4は、第4の半導体を備え、第4の半導体は、第3の半導体に含まれる元素を含む。なお、トランジスタTr4はスイッチの機能を備える。例えば、信号DATAB_LS[7]に基づいて、抵抗ストリングR−stringと信号線S1(j)を電気的に接続する。 The transistor Tr4 includes a fourth semiconductor, and the fourth semiconductor includes an element included in the third semiconductor. Note that the transistor Tr4 has a switch function. For example, the resistor string R-string and the signal line S1 (j) are electrically connected based on the signal DATAB_LS [7].
これにより、信号線に電気的に接続される画素に、デジタル信号を所定の電圧に変換したアナログ倡号を供給することができる。または、デジタルアナログ変換回路のパストランジスタ・ロジック回路に、画素のトランジスタが備える半導体と同じ半導体を備えるトランジスタを用いることができる。または、画素回路を作製する工程の一部を、パストランジスタ・ロジック回路を作製する工程の一部と兼ねることができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thus, an analog signal obtained by converting a digital signal into a predetermined voltage can be supplied to a pixel electrically connected to the signal line. Alternatively, a transistor having the same semiconductor as that of a pixel transistor can be used for the pass transistor / logic circuit of the digital-analog converter circuit. Alternatively, part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit. As a result, a novel display panel that is highly convenient or reliable can be provided.
<表示パネルの構成例2.>
本実施の形態で説明する表示パネル700は、シフトレジスタSRと、ラッチ回路LTCと、を有する(図18(A)参照)。
<Configuration Example of Display Panel 2. >
A display panel 700 described in this embodiment includes a shift register SR and a latch circuit LTC (see FIG. 18A).
ラッチ回路LTCは、シフトレジスタSRと電気的に接続される。例えば、シフトレジスタSRおよびラッチ回路LTCを用いて、パラレル信号を供給することができる。 The latch circuit LTC is electrically connected to the shift register SR. For example, a parallel signal can be supplied using the shift register SR and the latch circuit LTC.
パストランジスタ・ロジック回路PTLは、ラッチ回路LTCと電気的に接続される。 The pass transistor / logic circuit PTL is electrically connected to the latch circuit LTC.
シフトレジスタSRは、n型のトランジスタのみを含み、ラッチ回路は、n型のトランジスタのみを含む。 Shift register SR includes only n-type transistors, and the latch circuit includes only n-type transistors.
これにより、n型のトランジスタのみを用いて、デジタルアナログ変換回路および画素回路を構成することができる。または、デジタルアナログ変換回路に、画素のトランジスタが備える半導体と同じ半導体を備えるトランジスタを用いることができる。または、画素回路を作製する工程の一部を、パストランジスタ・ロジック回路を作製する工程の一部と兼ねることができる。または、デジタルアナログ変換回路の作製工程を簡略化することができる。その結果、利便性または信頼性に優れた新規な表示パネルを提供することができる。 Thus, a digital-analog conversion circuit and a pixel circuit can be configured using only n-type transistors. Alternatively, a transistor including the same semiconductor as a semiconductor included in a pixel transistor can be used for the digital-analog conversion circuit. Alternatively, part of the process for manufacturing the pixel circuit can be combined with part of the process for manufacturing the pass transistor / logic circuit. Alternatively, the manufacturing process of the digital-analog converter circuit can be simplified. As a result, a novel display panel that is highly convenient or reliable can be provided.
なお、本実施の形態は、本明細書で示す他の実施の形態と適宜組み合わせることができる。 Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(実施の形態3)
本実施の形態では、本発明の一態様で開示されるトランジスタの半導体層に用いることができる金属酸化物について説明する。なお、トランジスタの半導体層に金属酸化物を用いる場合、当該金属酸化物を酸化物半導体と読み替えてもよい。
(Embodiment 3)
In this embodiment, a metal oxide that can be used for the semiconductor layer of the transistor disclosed in one embodiment of the present invention will be described. Note that in the case where a metal oxide is used for the semiconductor layer of the transistor, the metal oxide may be read as an oxide semiconductor.
酸化物半導体は、単結晶酸化物半導体と、非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、CAAC−OS(c−axis−aligned crystalline oxide semiconductor)、多結晶酸化物半導体、nc−OS(nanocrystalline oxide semiconductor)、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、及び非晶質酸化物半導体などがある。 An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
また、非単結晶酸化物半導体の1つとして、半結晶性酸化物半導体(Semi−crystalline oxide semiconductor)と呼称される酸化物半導体が挙げられる。半結晶性酸化物半導体とは、単結晶酸化物半導体と非晶質酸化物半導体との中間構造を有する。半結晶性酸化物半導体は、非晶質酸化物半導体と比較して構造が安定である。例えば、半結晶性酸化物半導体としては、CAAC構造を有し、かつCAC(Cloud−Aligned Composite)構成である酸化物半導体がある。CACの詳細については、以下で説明を行う。 Further, as one of non-single-crystal oxide semiconductors, an oxide semiconductor called a semi-crystalline oxide semiconductor can be given. A semicrystalline oxide semiconductor has an intermediate structure between a single crystal oxide semiconductor and an amorphous oxide semiconductor. A semicrystalline oxide semiconductor has a more stable structure than an amorphous oxide semiconductor. For example, as a semicrystalline oxide semiconductor, there is an oxide semiconductor having a CAAC structure and a CAC (Cloud-Aligned Composite) structure. Details of the CAC will be described below.
また、本発明の一態様で開示されるトランジスタの半導体層には、CAC−OS(Cloud−Aligned Composite oxide semiconductor)を用いてもよい。 Alternatively, a CAC-OS (Cloud-Aligned Composite Oxide Semiconductor) may be used for the semiconductor layer of the transistor disclosed in one embodiment of the present invention.
なお、本発明の一態様で開示されるトランジスタの半導体層は、上述した非単結晶酸化物半導体またはCAC−OSを好適に用いることができる。また、非単結晶酸化物半導体としては、nc−OSまたはCAAC−OSを好適に用いることができる。 Note that the above-described non-single-crystal oxide semiconductor or CAC-OS can be preferably used for the semiconductor layer of the transistor disclosed in one embodiment of the present invention. As the non-single-crystal oxide semiconductor, nc-OS or CAAC-OS can be preferably used.
なお、本発明の一態様では、トランジスタの半導体層として、CAC−OSを用いると好ましい。CAC−OSを用いることで、トランジスタに高い電気特性または高い信頼性を付与することができる。 Note that in one embodiment of the present invention, a CAC-OS is preferably used as the semiconductor layer of the transistor. With the use of the CAC-OS, high electrical characteristics or high reliability can be imparted to the transistor.
以下では、CAC−OSの詳細について説明する。 Details of the CAC-OS will be described below.
CAC−OSまたはCAC−metal oxideは、材料の一部では導電性の機能と、材料の一部では絶縁性の機能とを有し、材料の全体では半導体としての機能を有する。なお、CAC−OSまたはCAC−metal oxideを、トランジスタのチャネル形成領域に用いる場合、導電性の機能は、キャリアとなる電子(またはホール)を流す機能であり、絶縁性の機能は、キャリアとなる電子を流さない機能である。導電性の機能と、絶縁性の機能とを、それぞれ相補的に作用させることで、スイッチングさせる機能(On/Offさせる機能)をCAC−OSまたはCAC−metal oxideに付与することができる。CAC−OSまたはCAC−metal oxideにおいて、それぞれの機能を分離させることで、双方の機能を最大限に高めることができる。 The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function prevents electrons from flowing. A function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
また、CAC−OSまたはCAC−metal oxideは、導電性領域、及び絶縁性領域を有する。導電性領域は、上述の導電性の機能を有し、絶縁性領域は、上述の絶縁性の機能を有する。また、材料中において、導電性領域と、絶縁性領域とは、ナノ粒子レベルで分離している場合がある。また、導電性領域と、絶縁性領域とは、それぞれ材料中に偏在する場合がある。また、導電性領域は、周辺がぼけてクラウド状に連結して観察される場合がある。 In addition, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.
また、CAC−OSまたはCAC−metal oxideにおいて、導電性領域と、絶縁性領域とは、それぞれ0.5nm以上10nm以下、好ましくは0.5nm以上3nm以下のサイズで材料中に分散している場合がある。 In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
また、CAC−OSまたはCAC−metal oxideは、異なるバンドギャップを有する成分により構成される。例えば、CAC−OSまたはCAC−metal oxideは、絶縁性領域に起因するワイドギャップを有する成分と、導電性領域に起因するナローギャップを有する成分と、により構成される。当該構成の場合、キャリアを流す際に、ナローギャップを有する成分において、主にキャリアが流れる。また、ナローギャップを有する成分が、ワイドギャップを有する成分に相補的に作用し、ナローギャップを有する成分に連動してワイドギャップを有する成分にもキャリアが流れる。このため、上記CAC−OSまたはCAC−metal oxideをトランジスタのチャネル形成領域に用いる場合、トランジスタのオン状態において高い電流駆動力、つまり大きなオン電流、及び高い電界効果移動度を得ることができる。 Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
すなわち、CAC−OSまたはCAC−metal oxideは、マトリックス複合材(matrix composite)または金属マトリックス複合材(metal matrix composite)と呼称することもできる。 That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite (metal matrix composite) or a metal matrix composite (metal matrix composite).
CAC−OSは、例えば、金属酸化物を構成する元素が、0.5nm以上10nm以下、好ましくは、1nm以上2nm以下またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つあるいはそれ以上の金属元素が偏在し、該金属元素を有する領域が、0.5nm以上10nm以下、好ましくは、1nm以上2nm以下またはその近傍のサイズで混合した状態をモザイク状またはパッチ状ともいう。 The CAC-OS is one structure of a material in which an element constituting a metal oxide is unevenly distributed with a size of 0.5 nm to 10 nm, preferably, 1 nm to 2 nm or near. In the following, in a metal oxide, one or more metal elements are unevenly distributed, and a region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm or near. The mixed state is also called mosaic or patch.
なお、金属酸化物は、少なくともインジウムを含むことが好ましい。特にインジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種または複数種が含まれていてもよい。 Note that the metal oxide preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind or plural kinds selected from may be included.
例えば、In−Ga−Zn酸化物におけるCAC−OS(CAC−OSの中でもIn−Ga−Zn酸化物を、特にCAC−IGZOと呼称してもよい。)とは、インジウム酸化物(以下、InOX1(X1は0よりも大きい実数)とする。)、またはインジウム亜鉛酸化物(以下、InX2ZnY2Z2(X2、Y2、及びZ2は0よりも大きい実数)とする。)と、ガリウム酸化物(以下、GaOX3(X3は0よりも大きい実数)とする。)、またはガリウム亜鉛酸化物(以下、GaX4ZnY4Z4(X4、Y4、及びZ4は0よりも大きい実数)とする。)などと、に材料が分離することでモザイク状となり、モザイク状のInOX1、またはInX2ZnY2Z2が、膜中に均一に分布した構成(以下、クラウド状ともいう。)である。 For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter, click Also called Udo-like.) A.
つまり、CAC−OSは、GaOX3が主成分である領域と、InX2ZnY2Z2、またはInOX1が主成分である領域とが、混合している構成を有する複合金属酸化物である。なお、本明細書において、例えば、第1の領域の元素Mに対するInの原子数比が、第2の領域の元素Mに対するInの原子数比よりも大きいことを、第1の領域は、第2の領域と比較して、Inの濃度が高いとする。 That, CAC-OS includes a region GaO X3 is the main component, and In X2 Zn Y2 O Z2, or InO X1 is the main component region is a composite metal oxide having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
なお、IGZOは通称であり、In、Ga、Zn、及びOによる1つの化合物をいう場合がある。代表例として、InGaO(ZnO)m1(m1は自然数)、またはIn(1+x0)Ga(1−x0)(ZnO)m0(−≦x0≦1、m0は任意数)で表される結晶性の化合物が挙げられる。 Note that IGZO is a common name and sometimes refers to one compound of In, Ga, Zn, and O. As a typical example, a crystal represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (− ≦ x0 ≦ 1, m0 is an arbitrary number). Compounds.
上記結晶性の化合物は、単結晶構造、多結晶構造、またはCAAC(c−axis aligned crystal)構造を有する。なお、CAAC構造とは、複数のIGZOのナノ結晶がc軸配向を有し、かつa−b面においては配向せずに連結した結晶構造である。 The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystal) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
一方、CAC−OSは、金属酸化物の材料構成に関する。CAC−OSとは、In、Ga、Zn、及びOを含む材料構成において、一部にGaを主成分とするナノ粒子状に観察される領域と、一部にInを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。従って、CAC−OSにおいて、結晶構造は副次的な要素である。 On the other hand, CAC-OS relates to a material structure of a metal oxide. CAC-OS refers to a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn, and O, and nanoparticles that are partially composed mainly of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
なお、CAC−OSは、組成の異なる二種類以上の膜の積層構造は含まないものとする。例えば、Inを主成分とする膜と、Gaを主成分とする膜との2層からなる構造は、含まない。 Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
なお、GaOX3が主成分である領域と、InX2ZnY2Z2、またはInOX1が主成分である領域とは、明確な境界が観察できない場合がある。 Incidentally, a region GaO X3 is the main component, and In X2 Zn Y2 O Z2 or InO X1 is the main component region, in some cases clear boundary can not be observed.
なお、ガリウムの代わりに、アルミニウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれている場合、CAC−OSは、一部に該金属元素を主成分とするナノ粒子状に観察される領域と、一部にInを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。 Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
CAC−OSは、例えば基板を意図的に加熱しない条件で、スパッタリング法により形成することができる。また、CAC−OSをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス(代表的にはアルゴン)、酸素ガス、及び窒素ガスの中から選ばれたいずれか一つまたは複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましく、例えば酸素ガスの流量比を0%以上30%未満、好ましくは0%以上10%以下とすることが好ましい。 The CAC-OS can be formed by a sputtering method under a condition where the substrate is not intentionally heated, for example. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .
CAC−OSは、X線回折(XRD:X−ray diffraction)測定法のひとつであるOut−of−plane法によるθ/2θスキャンを用いて測定したときに、明確なピークが観察されないという特徴を有する。すなわち、X線回折から、測定領域のa−b面方向、及びc軸方向の配向は見られないことが分かる。 The CAC-OS has a feature that a clear peak is not observed when measurement is performed using a θ / 2θ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
またCAC−OSは、プローブ径が1nmの電子線(ナノビーム電子線ともいう。)を照射することで得られる電子線回折パターンにおいて、リング状に輝度の高い領域と、該リング領域に複数の輝点が観測される。従って、電子線回折パターンから、CAC−OSの結晶構造が、平面方向、及び断面方向において、配向性を有さないnc(nano−crystal)構造を有することがわかる。 In addition, in the CAC-OS, an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
また例えば、In−Ga−Zn酸化物におけるCAC−OSでは、エネルギー分散型X線分光法(EDX:Energy Dispersive X−ray spectroscopy)を用いて取得したEDXマッピングにより、GaOX3が主成分である領域と、InX2ZnY2Z2、またはInOX1が主成分である領域とが、偏在し、混合している構造を有することが確認できる。 Further, for example, in a CAC-OS in an In—Ga—Zn oxide, a region in which GaO X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component is unevenly distributed and mixed.
CAC−OSは、金属元素が均一に分布したIGZO化合物とは異なる構造であり、IGZO化合物と異なる性質を有する。つまり、CAC−OSは、GaOX3などが主成分である領域と、InX2ZnY2Z2、またはInOX1が主成分である領域と、に互いに相分離し、各元素を主成分とする領域がモザイク状である構造を有する。 CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has a property different from that of an IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
ここで、InX2ZnY2Z2、またはInOX1が主成分である領域は、GaOX3などが主成分である領域と比較して、導電性が高い領域である。つまり、InX2ZnY2Z2、またはInOX1が主成分である領域を、キャリアが流れることにより、酸化物半導体としての導電性が発現する。従って、InX2ZnY2Z2、またはInOX1が主成分である領域が、酸化物半導体中にクラウド状に分布することで、高い電界効果移動度(μ)が実現できる。 Here, the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2 or InO X1, is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In X2 Zn Y2 O Z2 or InO X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.
一方、GaOX3などが主成分である領域は、InX2ZnY2Z2、またはInOX1が主成分である領域と比較して、絶縁性が高い領域である。つまり、GaOX3などが主成分である領域が、酸化物半導体中に分布することで、リーク電流を抑制し、良好なスイッチング動作を実現できる。 On the other hand, areas such as GaO X3 is the main component, as compared to the In X2 Zn Y2 O Z2 or InO X1 is the main component area, it is highly regions insulating. That is, a region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
従って、CAC−OSを半導体素子に用いた場合、GaOX3などに起因する絶縁性と、InX2ZnY2Z2、またはInOX1に起因する導電性とが、相補的に作用することにより、高いオン電流(Ion)、及び高い電界効果移動度(μ)を実現することができる。 Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in high An on-current (I on ) and high field effect mobility (μ) can be realized.
また、CAC−OSを用いた半導体素子は、信頼性が高い。従って、CAC−OSは、ディスプレイをはじめとするさまざまな半導体装置に最適である。 In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimal for various semiconductor devices including a display.
また、CAAC−OSまたはCAC−OSを半導体膜に用いるトランジスタは、チャネル長を短くすることができ、オン電流を大きくすることができ、オフ電流をきわめて小さくすることができ、ばらつきを抑制することができ、信頼性が高く、第8世代から第10世代程度の大型のガラス基板に作製することができる。これにより、大型の有機ELテレビのバックプレーンに好適に用いることができる。 In addition, a transistor using a CAAC-OS or a CAC-OS for a semiconductor film can have a short channel length, can have a large on-state current, can have a very small off-state current, and can suppress variations. And can be manufactured on a large glass substrate of 8th to 10th generation. Thereby, it can use suitably for the backplane of a large sized organic EL television.
本実施の形態は、他の実施の形態と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
(実施の形態4)
本実施の形態では、本発明の一態様の表示装置の構成について、図10を参照しながら説明する。
(Embodiment 4)
In this embodiment, the structure of the display device of one embodiment of the present invention is described with reference to FIGS.
図10は本発明の一態様の表示装置の構成を説明する図である。図10(A)は本発明の一態様の表示装置のブロック図であり、図10(B−1)乃至図10(B−3)は本発明の一態様の表示装置の外観を説明する投影図である。 FIG. 10 illustrates a structure of a display device of one embodiment of the present invention. FIG. 10A is a block diagram of a display device of one embodiment of the present invention, and FIGS. 10B-1 to 10B-3 are projections illustrating the appearance of the display device of one embodiment of the present invention. FIG.
<表示装置の構成例>
本実施の形態で説明する表示装置は、制御部238と、表示パネル700Bと、を有する(図10(A)参照)。
<Configuration example of display device>
The display device described in this embodiment includes a control portion 238 and a display panel 700B (see FIG. 10A).
《制御部238》
制御部238は、画像情報V1および制御情報SSを供給される機能を備える。例えば、クロック信号またはタイミング信号などを制御情報SSに用いることができる。
<Control unit 238>
The control unit 238 has a function to which the image information V1 and the control information SS are supplied. For example, a clock signal or a timing signal can be used for the control information SS.
制御部238は、画像情報V1に基づいて情報V11を生成する機能を備える。制御部238は、情報V11を供給する機能を備える。例えば、情報V11は、8bit以上好ましくは12bit以上の階調を含む。 The control unit 238 has a function of generating information V11 based on the image information V1. The control unit 238 has a function of supplying the information V11. For example, the information V11 includes a gradation of 8 bits or more, preferably 12 bits or more.
例えば、制御部238は、タイミングコントローラ233、伸張回路234および画像処理回路235Mを備える。 For example, the control unit 238 includes a timing controller 233, an expansion circuit 234, and an image processing circuit 235M.
《タイミングコントローラ233》
タイミングコントローラ233は、制御情報SSを駆動回路GDA(1)および駆動回路GDB(1)、駆動回路GDA(2)および駆動回路GDB(2)、駆動回路SD(1)乃至駆動回路SD(3)などに供給する機能を備える。これにより、複数の駆動回路の動作を同期することができる。
<< Timing controller 233 >>
The timing controller 233 sends the control information SS to the drive circuit GDA (1) and the drive circuit GDB (1), the drive circuit GDA (2) and the drive circuit GDB (2), and the drive circuits SD (1) to SD (3). The function to supply to. As a result, the operations of the plurality of drive circuits can be synchronized.
なお、タイミングコントローラ233を表示パネルに含めることもできる。例えば、リジッド基板に実装されたタイミングコントローラ233を、フレキシブルプリント基板を用いて駆動回路と電気的に接続して、表示パネルに用いることができる。 Note that the timing controller 233 can be included in the display panel. For example, the timing controller 233 mounted on a rigid board can be used for a display panel by being electrically connected to a driving circuit using a flexible printed board.
《表示パネル700B》
表示パネル700Bは、情報V11を供給される機能を備える。また、表示パネル700Bは、画素702(i,j)を備える。例えば、走査線G1(i)は、60Hz以上、好ましくは120Hz以上の頻度で選択信号を供給される。例えば、駆動回路GDA(1)、駆動回路GDB(1)、駆動回路GDA(2)および駆動回路GDB(2)は、選択信号を供給する機能を備える。
<< Display panel 700B >>
The display panel 700B has a function of being supplied with the information V11. The display panel 700B includes a pixel 702 (i, j). For example, the scanning line G1 (i) is supplied with a selection signal at a frequency of 60 Hz or more, preferably 120 Hz or more. For example, the driver circuit GDA (1), the driver circuit GDB (1), the driver circuit GDA (2), and the driver circuit GDB (2) have a function of supplying a selection signal.
画素702(i,j)は、表示素子を備える。表示素子は、情報V11に基づいて表示する機能を備える。例えば、液晶素子を、表示素子に用いることができる。 The pixel 702 (i, j) includes a display element. The display element has a function of displaying based on the information V11. For example, a liquid crystal element can be used for the display element.
例えば、実施の形態1で説明する表示パネルを表示パネル700Bに用いることができる。 For example, the display panel described in Embodiment 1 can be used for the display panel 700B.
これにより、表示素子を用いて画像情報を表示することができる。その結果、利便性または信頼性に優れた新規な表示装置を提供することができる。または、例えば、テレビジョン受像システム(図10(B−1)参照)、映像モニター(図10(B−2)参照)またはノートブックコンピュータ(図10(B−3)参照)などを提供することができる。 Thereby, image information can be displayed using a display element. As a result, a novel display device that is highly convenient or reliable can be provided. Alternatively, for example, a television receiving system (see FIG. 10B-1), a video monitor (see FIG. 10B-2), a notebook computer (see FIG. 10B-3), or the like is provided. Can do.
《伸張回路234》
伸張回路234は、圧縮された状態で供給される画像情報V1を伸張する機能を備える。伸張回路234は、記憶部を備える。記憶部は、例えば伸張された画像情報を記憶する機能を備える。
<< Extension circuit 234 >>
The expansion circuit 234 has a function of expanding the image information V1 supplied in a compressed state. The decompression circuit 234 includes a storage unit. The storage unit has a function of storing, for example, decompressed image information.
《画像処理回路235M》
画像処理回路235Mは、例えば、領域を備える。
<< Image processing circuit 235M >>
The image processing circuit 235M includes a region, for example.
領域は、例えば、画像情報V1に含まれる情報を記憶する機能を備える。 The area has a function of storing information included in the image information V1, for example.
画像処理回路235Mは、例えば、所定の特性曲線に基づいて画像情報V1を補正して情報V11を生成する機能と、情報V11を供給する機能と、を備える。具体的には、表示素子が良好な画像を表示するように、情報V11を生成する機能を備える。 The image processing circuit 235M has, for example, a function of correcting the image information V1 based on a predetermined characteristic curve to generate the information V11 and a function of supplying the information V11. Specifically, it has a function of generating information V11 so that the display element displays a good image.
なお、本実施の形態は、本明細書で示す他の実施の形態と適宜組み合わせることができる。 Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(実施の形態5)
本実施の形態では、本発明の一態様の入出力装置の構成について、図11を参照しながら説明する。
(Embodiment 5)
In this embodiment, the structure of the input / output device of one embodiment of the present invention is described with reference to FIGS.
図11は本発明の一態様の入出力装置の構成を説明するブロック図である。 FIG. 11 is a block diagram illustrating a structure of the input / output device of one embodiment of the present invention.
<入出力装置の構成例>
本実施の形態で説明する入出力装置は、入力部240と、表示部230と、を有する(図11参照)。例えば、実施の形態1に記載の表示パネル700を表示部230に用いることができる。なお、入力部240および表示部230を有する構成を入出力パネル700TPということができる。
<Configuration example of input / output device>
The input / output device described in this embodiment includes an input unit 240 and a display unit 230 (see FIG. 11). For example, the display panel 700 described in Embodiment 1 can be used for the display portion 230. Note that a structure including the input portion 240 and the display portion 230 can be referred to as an input / output panel 700TP.
入力部240は検知領域241を備える。入力部240は検知領域241に近接するものを検知する機能を備える。 The input unit 240 includes a detection area 241. The input unit 240 has a function of detecting an object close to the detection area 241.
検知領域241は、画素702(i,j)と重なる領域を備える。 The detection region 241 includes a region overlapping with the pixel 702 (i, j).
《入力部240》
入力部240は検知領域241を備える。入力部240は発振回路OSCおよび検知回路DCを備えることができる(図11参照)。
<< Input unit 240 >>
The input unit 240 includes a detection area 241. The input unit 240 can include an oscillation circuit OSC and a detection circuit DC (see FIG. 11).
《検知領域241》
検知領域241は、例えば、単数または複数の検知素子を備える。
<< Detection area 241 >>
The detection area 241 includes, for example, one or a plurality of detection elements.
検知領域241は、一群の検知素子775(g,1)乃至検知素子775(g,q)と、他の一群の検知素子775(1,h)乃至検知素子775(p,h)と、を有する(図11参照)。なお、gは1以上p以下の整数であり、hは1以上q以下の整数であり、pおよびqは1以上の整数である。 The detection region 241 includes a group of detection elements 775 (g, 1) to detection elements 775 (g, q) and another group of detection elements 775 (1, h) to detection elements 775 (p, h). (See FIG. 11). Note that g is an integer of 1 to p, h is an integer of 1 to q, and p and q are integers of 1 or more.
一群の検知素子775(g,1)乃至検知素子775(g,q)は、検知素子775(g,h)を含み、行方向(図中に矢印R2で示す方向)に配設される。なお、図11に矢印R2で示す方向は、図11に矢印R1で示す方向と同じであっても良いし、異なっていてもよい。 The group of sensing elements 775 (g, 1) to 775 (g, q) includes the sensing elements 775 (g, h) and are arranged in the row direction (direction indicated by an arrow R2 in the drawing). Note that the direction indicated by the arrow R2 in FIG. 11 may be the same as or different from the direction indicated by the arrow R1 in FIG.
また、他の一群の検知素子775(1,h)乃至検知素子775(p,h)は、検知素子775(g,h)を含み、行方向と交差する列方向(図中に矢印C2で示す方向)に配設される。 Further, another group of the detection elements 775 (1, h) to 775 (p, h) includes the detection elements 775 (g, h), and the column direction (in the drawing, indicated by an arrow C2) that intersects the row direction. (Direction shown).
《検知素子》
検知素子は近接するポインタを検知する機能を備える。例えば、指やスタイラスペン等をポインタに用いることができる。例えば、金属片またはコイル等を、スタイラスペンに用いることができる。
<< Sensing element >>
The detection element has a function of detecting an adjacent pointer. For example, a finger or a stylus pen can be used as the pointer. For example, a metal piece or a coil can be used for the stylus pen.
具体的には、静電容量方式の近接センサ、電磁誘導方式の近接センサ、光学方式の近接センサ、抵抗膜方式の近接センサなどを、検知素子に用いることができる。 Specifically, a capacitive proximity sensor, an electromagnetic induction proximity sensor, an optical proximity sensor, a resistive proximity sensor, or the like can be used as the detection element.
また、複数の方式の検知素子を併用することもできる。例えば、指を検知する検知素子と、スタイラスペンを検知する検知素子とを、併用することができる。これにより、ポインタの種類を判別することができる。または、判別したポインタの種類に基づいて、異なる命令を検知情報に関連付けることができる。具体的には、ポインタに指を用いたと判別した場合は、検知情報をジェスチャーと関連付けることができる。または、ポインターにスタイラスペンを用いたと判別した場合は、検知情報を描画処理と関連付けることができる。 A plurality of types of sensing elements can also be used in combination. For example, a detection element that detects a finger and a detection element that detects a stylus pen can be used in combination. Thereby, the type of the pointer can be determined. Alternatively, different instructions can be associated with the detection information based on the determined type of pointer. Specifically, when it is determined that a finger is used as the pointer, the detection information can be associated with the gesture. Alternatively, when it is determined that the stylus pen is used as the pointer, the detection information can be associated with the drawing process.
具体的には、静電容量方式または光学方式の近接センサを用いて、指を検知することができる。または、電磁誘導方式または光学方式の近接センサを用いて、スタイラスペンを検知することができる。 Specifically, a finger can be detected by using a capacitive or optical proximity sensor. Alternatively, the stylus pen can be detected using an electromagnetic induction type or optical type proximity sensor.
なお、本実施の形態は、本明細書で示す他の実施の形態と適宜組み合わせることができる。 Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(実施の形態6)
本実施の形態では、本発明の一態様の情報処理装置の構成について、図12乃至図14を参照しながら説明する。
(Embodiment 6)
In this embodiment, a structure of an information processing device of one embodiment of the present invention will be described with reference to FIGS.
図12(A)は本発明の一態様の情報処理装置の構成を説明するブロック図である。図12(B)および図12(C)は、情報処理装置200の外観の一例を説明する投影図である。 FIG. 12A is a block diagram illustrating a structure of an information processing device of one embodiment of the present invention. 12B and 12C are projection views for explaining an example of the appearance of the information processing apparatus 200. FIG.
図13は、本発明の一態様のプログラムを説明するフローチャートである。図13(A)は、本発明の一態様のプログラムの主の処理を説明するフローチャートであり、図13(B)は、割り込み処理を説明するフローチャートである。 FIG. 13 is a flowchart illustrating a program according to one embodiment of the present invention. FIG. 13A is a flowchart illustrating main processing of a program of one embodiment of the present invention, and FIG. 13B is a flowchart illustrating interrupt processing.
図14は、本発明の一態様のプログラムを説明する図である。図14(A)は、本発明の一態様のプログラムの割り込み処理を説明するフローチャートであり、図14(B)は、本発明の一態様の情報処理装置の動作を説明するタイミングチャートである。 FIG. 14 is a diagram illustrating a program according to one embodiment of the present invention. FIG. 14A is a flowchart illustrating a program interrupt process of one embodiment of the present invention, and FIG. 14B is a timing chart illustrating the operation of the information processing device of one embodiment of the present invention.
<情報処理装置の構成例1.>
本実施の形態で説明する情報処理装置200は、入出力装置220と、演算装置210と、を有する(図12(A)参照)。入出力装置は、演算装置210と電気的に接続される。また、情報処理装置200は筐体を備えることができる(図12(B)または図12(C)参照)。
<Configuration example 1 of information processing apparatus>>
The information processing device 200 described in this embodiment includes an input / output device 220 and an arithmetic device 210 (see FIG. 12A). The input / output device is electrically connected to the arithmetic device 210. Further, the information processing device 200 can include a housing (see FIG. 12B or FIG. 12C).
入出力装置220は表示部230および入力部240を備える(図12(A)参照)。入出力装置220は検知部250を備える。また、入出力装置220は通信部290を備えることができる。 The input / output device 220 includes a display portion 230 and an input portion 240 (see FIG. 12A). The input / output device 220 includes a detection unit 250. In addition, the input / output device 220 can include a communication unit 290.
入出力装置220は画像情報V1または制御情報SSを供給される機能を備え、位置情報P1または検知情報DSを供給する機能を備える。 The input / output device 220 has a function of supplying image information V1 or control information SS, and a function of supplying position information P1 or detection information DS.
演算装置210は位置情報P1または検知情報DSを供給される機能を備える。演算装置210は画像情報V1を供給する機能を備える。演算装置210は、例えば、位置情報P1または検知情報DSに基づいて動作する機能を備える。 The arithmetic device 210 has a function of being supplied with the position information P1 or the detection information DS. The arithmetic device 210 has a function of supplying image information V1. The arithmetic device 210 has a function of operating based on the position information P1 or the detection information DS, for example.
なお、筐体は入出力装置220または演算装置210を収納する機能を備える。または、筐体は表示部230または演算装置210を支持する機能を備える。 Note that the housing has a function of housing the input / output device 220 or the arithmetic device 210. Alternatively, the housing has a function of supporting the display unit 230 or the arithmetic device 210.
表示部230は画像情報V1に基づいて画像を表示する機能を備える。表示部230は制御情報SSに基づいて画像を表示する機能を備える。 The display unit 230 has a function of displaying an image based on the image information V1. The display unit 230 has a function of displaying an image based on the control information SS.
入力部240は、位置情報P1を供給する機能を備える。 The input unit 240 has a function of supplying the position information P1.
検知部250は検知情報DSを供給する機能を備える。検知部250は、例えば、情報処理装置200が使用される環境の照度を検出する機能を備え、照度情報を供給する機能を備える。 The detection unit 250 has a function of supplying detection information DS. For example, the detection unit 250 has a function of detecting the illuminance of an environment where the information processing apparatus 200 is used, and a function of supplying illuminance information.
これにより、情報処理装置は、情報処理装置が使用される環境において、情報処理装置の筐体が受ける光の強さを把握して動作することができる。または、情報処理装置の使用者は、表示方法を選択することができる。その結果、利便性または信頼性に優れた新規な情報処理装置を提供することができる。 Thereby, the information processing apparatus can operate by grasping the intensity of light received by the casing of the information processing apparatus in an environment where the information processing apparatus is used. Alternatively, the user of the information processing apparatus can select a display method. As a result, a novel information processing apparatus that is highly convenient or reliable can be provided.
以下に、情報処理装置を構成する個々の要素について説明する。なお、これらの構成は明確に分離できず、一つの構成が他の構成を兼ねる場合や他の構成の一部を含む場合がある。例えばタッチセンサが表示パネルに重ねられたタッチパネルは、表示部であるとともに入力部でもある。 Below, each element which comprises information processing apparatus is demonstrated. Note that these configurations cannot be clearly separated, and one configuration may serve as another configuration or may include a part of another configuration. For example, a touch panel in which a touch sensor is superimposed on a display panel is not only a display unit but also an input unit.
《構成例》
本発明の一態様の情報処理装置200は、筐体または演算装置210を有する。
<Configuration example>
The information processing device 200 of one embodiment of the present invention includes a housing or the arithmetic device 210.
演算装置210は、演算部211、記憶部212、伝送路214、入出力インターフェース215を備える。 The computing device 210 includes a computing unit 211, a storage unit 212, a transmission path 214, and an input / output interface 215.
また、本発明の一態様の情報処理装置は、入出力装置220を有する。 Further, the information processing device of one embodiment of the present invention includes the input / output device 220.
入出力装置220は、表示部230、入力部240、検知部250および通信部290を備える。 The input / output device 220 includes a display unit 230, an input unit 240, a detection unit 250, and a communication unit 290.
《情報処理装置》
本発明の一態様の情報処理装置は、演算装置210または入出力装置220を備える。
《Information processing device》
The information processing device of one embodiment of the present invention includes the arithmetic device 210 or the input / output device 220.
《演算装置210》
演算装置210は、演算部211および記憶部212を備える。また、伝送路214および入出力インターフェース215を備える。
<< Calculation device 210 >>
The calculation device 210 includes a calculation unit 211 and a storage unit 212. A transmission path 214 and an input / output interface 215 are provided.
《演算部211》
演算部211は、例えばプログラムを実行する機能を備える。
<< Calculation unit 211 >>
The calculation unit 211 has a function of executing a program, for example.
《記憶部212》
記憶部212は、例えば演算部211が実行するプログラム、初期情報、設定情報または画像等を記憶する機能を有する。
<< Storage unit 212 >>
The storage unit 212 has a function of storing, for example, a program executed by the calculation unit 211, initial information, setting information, or an image.
具体的には、ハードディスク、フラッシュメモリまたは酸化物半導体を含むトランジスタを用いたメモリ等を用いることができる。 Specifically, a hard disk, a flash memory, a memory including a transistor including an oxide semiconductor, or the like can be used.
《入出力インターフェース215、伝送路214》
入出力インターフェース215は端子または配線を備え、情報を供給し、情報を供給される機能を備える。例えば、伝送路214と電気的に接続することができる。また、入出力装置220と電気的に接続することができる。
<< Input / output interface 215, transmission path 214 >>
The input / output interface 215 includes a terminal or a wiring, and has a function of supplying information and receiving information. For example, the transmission line 214 can be electrically connected. Further, the input / output device 220 can be electrically connected.
伝送路214は配線を備え、情報を供給し、情報を供給される機能を備える。例えば、入出力インターフェース215と電気的に接続することができる。また、演算部211、記憶部212または入出力インターフェース215と電気的に接続することができる。 The transmission path 214 includes wiring, supplies information, and has a function of being supplied with information. For example, the input / output interface 215 can be electrically connected. Further, it can be electrically connected to the calculation unit 211, the storage unit 212, or the input / output interface 215.
《入出力装置220》
入出力装置220は、表示部230、入力部240、検知部250または通信部290を備える。例えば、実施の形態5において説明する入出力装置を用いることができる。これにより、消費電力を低減することができる。
<< Input / output device 220 >>
The input / output device 220 includes a display unit 230, an input unit 240, a detection unit 250, or a communication unit 290. For example, the input / output device described in Embodiment 5 can be used. Thereby, power consumption can be reduced.
《表示部230》
表示部230は、制御部238と、駆動回路GDと、駆動回路SDと、表示パネル700Bと、を有する(図10参照)。例えば、実施の形態4で説明する表示装置を表示部230に用いることができる。
<< Display unit 230 >>
The display unit 230 includes a control unit 238, a drive circuit GD, a drive circuit SD, and a display panel 700B (see FIG. 10). For example, the display device described in Embodiment 4 can be used for the display portion 230.
《入力部240》
さまざまなヒューマンインターフェイス等を入力部240に用いることができる(図12参照)。
<< Input unit 240 >>
Various human interfaces or the like can be used for the input unit 240 (see FIG. 12).
例えば、キーボード、マウス、タッチセンサ、マイクまたはカメラ等を入力部240に用いることができる。なお、表示部230に重なる領域を備えるタッチセンサを用いることができる。表示部230と表示部230に重なる領域を備えるタッチセンサを備える入出力装置を、タッチパネルまたはタッチスクリーンということができる。 For example, a keyboard, mouse, touch sensor, microphone, camera, or the like can be used for the input unit 240. Note that a touch sensor including a region overlapping with the display portion 230 can be used. An input / output device including a touch sensor including a display unit 230 and a region overlapping with the display unit 230 can be referred to as a touch panel or a touch screen.
例えば、使用者は、タッチパネルに触れた指をポインタに用いて様々なジェスチャー(タップ、ドラッグ、スワイプまたはピンチイン等)をすることができる。 For example, the user can make various gestures (tap, drag, swipe, pinch in, etc.) using a finger touching the touch panel as a pointer.
例えば、演算装置210は、タッチパネルに接触する指の位置または軌跡等の情報を解析し、解析結果が所定の条件を満たすとき、特定のジェスチャーが供給されたとすることができる。これにより、使用者は、所定のジェスチャーにあらかじめ関連付けられた所定の操作命令を、当該ジェスチャーを用いて供給できる。 For example, the computing device 210 may analyze information such as the position or trajectory of a finger that touches the touch panel, and a specific gesture may be supplied when the analysis result satisfies a predetermined condition. Accordingly, the user can supply a predetermined operation command associated with the predetermined gesture in advance using the gesture.
一例を挙げれば、使用者は、画像情報の表示位置を変更する「スクロール命令」を、タッチパネルに沿ってタッチパネルに接触する指を移動するジェスチャーを用いて供給できる。 For example, the user can supply a “scroll command” for changing the display position of the image information using a gesture for moving a finger that touches the touch panel along the touch panel.
《検知部250》
検知部250は、周囲の状態を検知して検知情報を供給する機能を備える。具体的には、照度情報、姿勢情報、圧力情報、位置情報等を供給できる。
<< Detection unit 250 >>
The detection unit 250 has a function of detecting surrounding conditions and supplying detection information. Specifically, illuminance information, posture information, pressure information, position information, and the like can be supplied.
例えば、光検出器、姿勢検出器、加速度センサ、方位センサ、GPS(Global positioning System)信号受信回路、圧力センサ、温度センサ、湿度センサまたはカメラ等を、検知部250に用いることができる。 For example, a light detector, an attitude detector, an acceleration sensor, an orientation sensor, a GPS (Global positioning System) signal receiving circuit, a pressure sensor, a temperature sensor, a humidity sensor, a camera, or the like can be used for the detection unit 250.
《通信部290》
通信部290は、ネットワークに情報を供給し、ネットワークから情報を取得する機能を備える。
<< Communication unit 290 >>
The communication unit 290 has a function of supplying information to the network and acquiring information from the network.
《プログラム》
本発明の一態様のプログラムは、下記のステップを有する(図13(A)参照)。
"program"
The program of one embodiment of the present invention includes the following steps (see FIG. 13A).
[第1のステップ]
第1のステップにおいて、設定を初期化する(図13(A)(S1)参照)。
[First step]
In the first step, the settings are initialized (see FIGS. 13A and S1).
例えば、起動時に表示する所定の画像情報と、当該画像情報を表示する所定のモードと、当該画像情報を表示する所定の表示方法を特定する情報と、を記憶部212から取得する。具体的には、一の静止画像情報または他の動画像情報を所定の画像情報に用いることができる。また、第1のモードまたは第2のモードを所定のモードに用いることができる。 For example, predetermined image information to be displayed at startup, a predetermined mode for displaying the image information, and information for specifying a predetermined display method for displaying the image information are acquired from the storage unit 212. Specifically, one still image information or other moving image information can be used as predetermined image information. Further, the first mode or the second mode can be used as a predetermined mode.
[第2のステップ]
第2のステップにおいて、割り込み処理を許可する(図13(A)(S2)参照)。なお、割り込み処理が許可された演算装置は、主の処理と並行して割り込み処理を行うことができる。割り込み処理から主の処理に復帰した演算装置は、割り込み処理をして得た結果を主の処理に反映することができる。
[Second step]
In the second step, interrupt processing is permitted (see FIGS. 13A and S2). Note that an arithmetic unit that is permitted to perform interrupt processing can perform interrupt processing in parallel with main processing. The arithmetic unit that has returned to the main process from the interrupt process can reflect the result obtained by the interrupt process to the main process.
なお、カウンタの値が初期値であるとき、演算装置に割り込み処理をさせ、割り込み処理から復帰する際に、カウンタを初期値以外の値としてもよい。これにより、プログラムを起動した後に常に割り込み処理をさせることができる。 Note that when the counter value is an initial value, the arithmetic unit performs interrupt processing, and when returning from the interrupt processing, the counter may be set to a value other than the initial value. As a result, interrupt processing can always be performed after the program is started.
[第3のステップ]
第3のステップにおいて、第1のステップまたは割り込み処理において選択された、所定のモードまたは所定の表示方法を用いて画像情報を表示する(図13(A)(S3)参照)。なお、所定のモードは画像情報を表示するモードを特定し、所定の表示方法は画像情報を表示する方法を特定する。また、例えば、画像情報V1を表示する情報に用いることができる。
[Third step]
In the third step, the image information is displayed using the predetermined mode or the predetermined display method selected in the first step or the interruption process (see FIGS. 13A and 13). The predetermined mode specifies a mode for displaying image information, and the predetermined display method specifies a method for displaying image information. Further, for example, it can be used as information for displaying the image information V1.
例えば、画像情報V1を表示する一の方法を、第1のモードに関連付けることができる。または、画像情報V1を表示する他の方法を第2のモードに関連付けることができる。これにより、選択されたモードに基づいて表示方法を選択することができる。 For example, one method for displaying the image information V1 can be associated with the first mode. Alternatively, another method for displaying the image information V1 can be associated with the second mode. Thereby, a display method can be selected based on the selected mode.
《第1のモード》
具体的には、30Hz以上、好ましくは60Hz以上の頻度で一の走査線に選択信号を供給し、選択信号に基づいて表示をする方法を、第1のモードに関連付けることができる。
<First mode>
Specifically, a method of supplying a selection signal to one scanning line at a frequency of 30 Hz or more, preferably 60 Hz or more, and displaying based on the selection signal can be associated with the first mode.
例えば、30Hz以上、好ましくは60Hz以上の頻度で選択信号を供給すると、動画像の動きを滑らかに表示することができる。 For example, when the selection signal is supplied at a frequency of 30 Hz or higher, preferably 60 Hz or higher, the motion of the moving image can be displayed smoothly.
例えば、30Hz以上、好ましくは60Hz以上の頻度で画像を更新すると、使用者の操作に滑らかに追従するように変化する画像を、使用者が操作中の情報処理装置200に表示することができる。 For example, when an image is updated at a frequency of 30 Hz or higher, preferably 60 Hz or higher, an image that changes so as to smoothly follow the user's operation can be displayed on the information processing apparatus 200 being operated by the user.
《第2のモード》
具体的には、30Hz未満、好ましくは1Hz未満、より好ましくは一分に一回未満の頻度で一の走査線に選択信号を供給し、選択信号に基づいて表示をする方法を、第2のモードに関連付けることができる。
<< Second mode >>
Specifically, a method for supplying a selection signal to one scanning line at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute, and performing display based on the selection signal, Can be associated with a mode.
30Hz未満、好ましくは1Hz未満、より好ましくは一分に一回未満の頻度で選択信号を供給すると、フリッカーまたはちらつきが抑制された表示をすることができる。また、消費電力を低減することができる。 When the selection signal is supplied at a frequency of less than 30 Hz, preferably less than 1 Hz, more preferably less than once per minute, a display in which flicker or flicker is suppressed can be displayed. In addition, power consumption can be reduced.
例えば、情報処理装置200を時計に用いる場合、1秒に一回の頻度または1分に一回の頻度等で表示を更新することができる。 For example, when the information processing apparatus 200 is used for a clock, the display can be updated at a frequency of once per second or a frequency of once per minute.
ところで、例えば、発光素子を表示素子に用いる場合、発光素子をパルス状に発光させて、画像情報を表示することができる。具体的には、パルス状に有機EL素子を発光させて、その残光を表示に用いることができる。有機EL素子は優れた周波数特性を備えるため、発光素子を駆動する時間を短縮し、消費電力を低減することができる場合がある。または、発熱が抑制されるため、発光素子の劣化を軽減することができる場合がある。 By the way, for example, when a light-emitting element is used as a display element, the light-emitting element can emit light in a pulse shape to display image information. Specifically, the organic EL element can emit light in a pulse shape, and the afterglow can be used for display. Since the organic EL element has excellent frequency characteristics, there are cases where the time for driving the light emitting element can be shortened and the power consumption can be reduced. Alternatively, heat generation is suppressed, so that deterioration of the light-emitting element can be reduced in some cases.
[第4のステップ]
第4のステップにおいて、終了命令が供給された場合は第5のステップに進み、終了命令が供給されなかった場合は第3のステップに進むように選択する(図13(A)(S4)参照)。
[Fourth step]
In the fourth step, if the end command is supplied, the process proceeds to the fifth step, and if the end command is not supplied, the third step is selected (see FIGS. 13A and S4). ).
例えば、割り込み処理において供給された終了命令を判断に用いてもよい。 For example, an end command supplied in the interrupt process may be used for determination.
[第5のステップ]
第5のステップにおいて、プログラムを終了する(図13(A)(S5)参照)。
[Fifth step]
In the fifth step, the program is terminated (see FIGS. 13A and S5).
《割り込み処理》
割り込み処理は以下の第6のステップ乃至第8のステップを備える(図13(B)参照)。
<Interrupt processing>
The interrupt process includes the following sixth to eighth steps (see FIG. 13B).
[第6のステップ]
第6のステップにおいて、例えば、検知部250を用いて、情報処理装置200が使用される環境の照度を検出する(図13(B)(S6)参照)。なお、環境の照度に代えて環境光の色温度や色度を検出してもよい。
[Sixth Step]
In the sixth step, for example, the detection unit 250 is used to detect the illuminance of the environment in which the information processing apparatus 200 is used (see FIGS. 13B and S6). Note that the color temperature or chromaticity of the ambient light may be detected instead of the illuminance of the environment.
[第7のステップ]
第7のステップにおいて、検出した照度情報に基づいて表示方法を決定する(図13(B)(S7)参照)。例えば、表示の明るさを暗すぎないように、または明るすぎないように決定する。
[Seventh Step]
In the seventh step, a display method is determined based on the detected illuminance information (see FIGS. 13B and S7). For example, the display brightness is determined not to be too dark or too bright.
なお、第6のステップにおいて環境光の色温度や環境光の色度を検出した場合は、表示の色味を調節してもよい。 When the color temperature of ambient light or the chromaticity of ambient light is detected in the sixth step, the display color may be adjusted.
[第8のステップ]
第8のステップにおいて、割り込み処理を終了する(図13(B)(S8)参照)。
[Eighth step]
In the eighth step, the interrupt process is terminated (see FIGS. 13B and S8).
<情報処理装置の構成例2.>
本発明の一態様の情報処理装置の別の構成について、図14を参照しながら説明する。
<Configuration example 2 of information processing apparatus>>
Another structure of the information processing device of one embodiment of the present invention is described with reference to FIG.
図14(A)は、本発明の一態様のプログラムを説明するフローチャートである。図14(A)は、図13(B)に示す割り込み処理とは異なる割り込み処理を説明するフローチャートである。 FIG. 14A is a flowchart illustrating a program of one embodiment of the present invention. FIG. 14A is a flowchart for explaining interrupt processing different from the interrupt processing shown in FIG.
なお、情報処理装置の構成例2は、供給された所定のイベントに基づいて、モードを変更するステップを割り込み処理に有する点が、図13(B)を参照しながら説明する割り込み処理とは異なる。ここでは、異なる部分について詳細に説明し、同様の構成を用いることができる部分について上記の説明を援用する。 The configuration example 2 of the information processing device is different from the interrupt processing described with reference to FIG. 13B in that the interrupt processing includes a step of changing the mode based on the supplied predetermined event. . Here, different portions will be described in detail, and the above description will be applied to portions that can use the same configuration.
《割り込み処理》
割り込み処理は以下の第6のステップ乃至第8のステップを備える(図14(A)参照)。
<Interrupt processing>
The interrupt process includes the following sixth to eighth steps (see FIG. 14A).
[第6のステップ]
第6のステップにおいて、所定のイベントが供給された場合は、第7のステップに進み、所定のイベントが供給されなかった場合は、第8のステップに進む(図14(A)(U6)参照)。例えば、所定の期間に所定のイベントが供給されたか否かを条件に用いることができる。具体的には、5秒以下、1秒以下または0.5秒以下好ましくは0.1秒以下であって0秒より長い期間を所定の期間とすることができる。
[Sixth Step]
In the sixth step, when a predetermined event is supplied, the process proceeds to the seventh step, and when the predetermined event is not supplied, the process proceeds to the eighth step (see FIGS. 14A and U6). ). For example, it can be used as a condition whether or not a predetermined event is supplied during a predetermined period. Specifically, the predetermined period can be a period of 5 seconds or less, 1 second or less, or 0.5 seconds or less, preferably 0.1 seconds or less and longer than 0 seconds.
[第7のステップ]
第7のステップにおいて、モードを変更する(図14(A)(U7)参照)。具体的には、第1のモードを選択していた場合は、第2のモードを選択し、第2のモードを選択していた場合は、第1のモードを選択する。
[Seventh Step]
In the seventh step, the mode is changed (see FIGS. 14A and U7). Specifically, when the first mode is selected, the second mode is selected, and when the second mode is selected, the first mode is selected.
例えば、表示部230の一部の領域について、表示モードを変更することができる。具体的には、駆動回路GDA、駆動回路GDBおよび駆動回路GDCを備える表示部230の駆動回路GDBが選択信号を供給する領域について、表示モードを変更することができる(図14(B)参照)。 For example, the display mode can be changed for some areas of the display unit 230. Specifically, the display mode can be changed for a region where the driver circuit GDB of the display portion 230 including the driver circuit GDA, the driver circuit GDB, and the driver circuit GDC supplies a selection signal (see FIG. 14B). .
例えば、所定のイベントが、駆動回路GDBが選択信号を供給する領域の入力部240に供給された場合に、当該領域の表示モードを変更することができる。具体的には、駆動回路GDBが供給する選択信号の頻度を変更することができる。これにより、例えば、駆動回路GDBが選択信号を供給する領域の表示を、駆動回路GDAおよび駆動回路GDCを動作することなく更新することができる。または、駆動回路が消費する電力を抑制することができる。 For example, when a predetermined event is supplied to the input unit 240 of an area where the drive circuit GDB supplies a selection signal, the display mode of the area can be changed. Specifically, the frequency of the selection signal supplied by the drive circuit GDB can be changed. Thereby, for example, the display of the region where the drive circuit GDB supplies the selection signal can be updated without operating the drive circuit GDA and the drive circuit GDC. Alternatively, power consumed by the driver circuit can be suppressed.
[第8のステップ]
第8のステップにおいて、割り込み処理を終了する(図14(A)(U8)参照)。なお、主の処理を実行している期間に割り込み処理を繰り返し実行してもよい。
[Eighth step]
In the eighth step, the interrupt process is ended (see FIGS. 14A and U8). Note that interrupt processing may be repeatedly executed during a period in which main processing is being executed.
《所定のイベント》
例えば、マウス等のポインティング装置を用いて供給する、「クリック」や「ドラッグ」等のイベント、指等をポインタに用いてタッチパネルに供給する、「タップ」、「ドラッグ」または「スワイプ」等のイベントを用いることができる。
《Predetermined event》
For example, an event such as “click” or “drag” supplied using a pointing device such as a mouse, an event such as “tap”, “drag” or “swipe” supplied to a touch panel using a finger or the like as a pointer Can be used.
また、例えば、ポインタが指し示すスライドバーの位置、スワイプの速度、ドラッグの速度等を用いて、所定のイベントに関連付けられた命令の引数を与えることができる。 Further, for example, an argument of a command associated with a predetermined event can be given using the position of the slide bar pointed to by the pointer, the swipe speed, the drag speed, or the like.
例えば、検知部250が検知した情報をあらかじめ設定された閾値と比較して、比較結果をイベントに用いることができる。 For example, the information detected by the detection unit 250 can be compared with a preset threshold value, and the comparison result can be used as an event.
具体的には、筐体に押し込むことができるように配設されたボタン等に接する感圧検知器等を検知部250に用いることができる。 Specifically, a pressure-sensitive detector or the like that contacts a button or the like that can be pushed into the housing can be used for the detection unit 250.
《所定のイベントに関連付ける命令》
例えば、終了命令を、特定のイベントに関連付けることができる。
《Instructions related to predetermined events》
For example, an end instruction can be associated with a particular event.
例えば、表示されている一の画像情報から他の画像情報に表示を切り替える「ページめくり命令」を、所定のイベントに関連付けることができる。なお、「ページめくり命令」を実行する際に用いるページをめくる速度などを決定する引数を、所定のイベントを用いて与えることができる。 For example, a “page turning command” for switching display from one displayed image information to another image information can be associated with a predetermined event. Note that an argument that determines a page turning speed used when executing the “page turning instruction” can be given using a predetermined event.
例えば、一の画像情報の表示されている一部分の表示位置を移動して、一部分に連続する他の部分を表示する「スクロール命令」などを、所定のイベントに関連付けることができる。なお、「スクロール命令」を実行する際に用いる表示位置を移動する速度などを決定する引数を、所定のイベントを用いて与えることができる。 For example, a “scroll command” for moving the display position of a part of one image information displayed to display another part continuous to the part can be associated with a predetermined event. It should be noted that an argument that determines the speed of moving the display position used when executing the “scroll command” can be given using a predetermined event.
例えば、表示方法を設定する命令または画像情報を生成する命令などを、所定のイベントに関連付けることができる。なお、生成する画像の明るさを決定する引数を所定のイベントに関連付けることができる。また、生成する画像の明るさを決定する引数を、検知部250が検知する環境の明るさに基づいて決定してもよい。 For example, a command for setting a display method or a command for generating image information can be associated with a predetermined event. An argument that determines the brightness of the image to be generated can be associated with a predetermined event. Further, an argument for determining the brightness of the image to be generated may be determined based on the brightness of the environment detected by the detection unit 250.
例えば、プッシュ型のサービスを用いて配信される情報を、通信部290を用いて取得する命令などを、所定のイベントに関連付けることができる。 For example, a command for acquiring information distributed using a push-type service using the communication unit 290 can be associated with a predetermined event.
なお、情報を取得する資格の有無を、検知部250が検知する位置情報を用いて判断してもよい。具体的には、ユーザーが特定の教室、学校、会議室、企業、建物等の内部または領域にいる場合に、情報を取得する資格を有すると判断してもよい。これにより、例えば、学校または大学等の教室で配信される教材を受信して、情報処理装置200を教科書等に用いることができる(図12(C)参照)。または、企業等の会議室で配信される資料を受信して、会議資料に用いることができる。 In addition, you may determine the presence or absence of the qualification to acquire information using the positional information which the detection part 250 detects. Specifically, when a user is inside or in a specific classroom, school, conference room, company, building, etc., it may be determined that he / she is qualified to acquire information. Accordingly, for example, the teaching material distributed in a classroom such as a school or a university can be received and the information processing apparatus 200 can be used as a textbook (see FIG. 12C). Alternatively, a material distributed in a conference room of a company or the like can be received and used as a conference material.
なお、本実施の形態は、本明細書で示す他の実施の形態と適宜組み合わせることができる。 Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
(実施の形態7)
本実施の形態では、本発明の一態様の情報処理装置の構成について、図15および図16を参照しながら説明する。
(Embodiment 7)
In this embodiment, a structure of an information processing device of one embodiment of the present invention will be described with reference to FIGS.
図15および図16は、本発明の一態様の情報処理装置の構成を説明する図である。図15(A)は情報処理装置のブロック図であり、図15(B)乃至図15(E)は情報処理装置の構成を説明する斜視図である。また、図16(A)乃至図16(E)は情報処理装置の構成を説明する斜視図である。 15 and 16 are diagrams illustrating a configuration of an information processing device of one embodiment of the present invention. FIG. 15A is a block diagram of the information processing apparatus, and FIGS. 15B to 15E are perspective views illustrating the configuration of the information processing apparatus. 16A to 16E are perspective views illustrating the configuration of the information processing device.
<情報処理装置>
本実施の形態で説明する情報処理装置5200Bは、演算装置5210と、入出力装置5220とを、有する(図15(A)参照)。
<Information processing device>
An information processing device 5200B described in this embodiment includes an arithmetic device 5210 and an input / output device 5220 (see FIG. 15A).
演算装置5210は、操作情報を供給される機能を備え、操作情報に基づいて画像情報を供給する機能を備える。 The arithmetic device 5210 has a function of supplying operation information and a function of supplying image information based on the operation information.
入出力装置5220は、表示部5230、入力部5240、検知部5250、通信部5290を備え、操作情報を供給する機能および画像情報を供給される機能を備える。また、入出力装置5220は、検知情報を供給する機能、通信情報を供給する機能および通信情報を供給される機能を備える。 The input / output device 5220 includes a display unit 5230, an input unit 5240, a detection unit 5250, and a communication unit 5290, and has a function of supplying operation information and a function of supplying image information. The input / output device 5220 has a function of supplying detection information, a function of supplying communication information, and a function of supplying communication information.
入力部5240は操作情報を供給する機能を備える。例えば、入力部5240は、情報処理装置5200Bの使用者の操作に基づいて操作情報を供給する。 The input unit 5240 has a function of supplying operation information. For example, the input unit 5240 supplies operation information based on the operation of the user of the information processing apparatus 5200B.
具体的には、キーボード、ハードウェアボタン、ポインティングデバイス、タッチセンサ、音声入力装置、視線入力装置などを、入力部5240に用いることができる。 Specifically, a keyboard, hardware buttons, a pointing device, a touch sensor, a voice input device, a line-of-sight input device, or the like can be used for the input unit 5240.
表示部5230は表示パネルを備え、画像情報を表示する機能を備える。例えば、実施の形態1において説明する表示パネルを表示部5230に用いることができる。 The display portion 5230 includes a display panel and has a function of displaying image information. For example, the display panel described in Embodiment 1 can be used for the display portion 5230.
検知部5250は検知情報を供給する機能を備える。例えば、情報処理装置が使用されている周辺の環境を検知して、検知情報として供給する機能を備える。 The detection unit 5250 has a function of supplying detection information. For example, it has a function of detecting the surrounding environment where the information processing apparatus is used and supplying it as detection information.
具体的には、照度センサ、撮像装置、姿勢検出装置、圧力センサ、人感センサなどを検知部5250に用いることができる。 Specifically, an illuminance sensor, an imaging device, a posture detection device, a pressure sensor, a human sensor, or the like can be used for the detection unit 5250.
通信部5290は通信情報を供給される機能および供給する機能を備える。例えば、無線通信または有線通信により、他の電子機器または通信網と接続する機能を備える。具体的には、無線構内通信、電話通信、近距離無線通信などの機能を備える。 The communication unit 5290 has a function for supplying communication information and a function for supplying communication information. For example, a function of connecting to another electronic device or a communication network by wireless communication or wired communication is provided. Specifically, it has functions such as wireless local area communication, telephone communication, and short-range wireless communication.
《情報処理装置の構成例1.》
例えば、円筒状の柱などに沿った外形を表示部5230に適用することができる(図15(B)参照)。また、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える。また、情報処理装置5200Bは人の存在を検知して、表示内容を変更する機能を備える。これにより、例えば、情報処理装置5200Bを建物の柱に設置することができる。または、情報処理装置5200Bは広告または案内等を表示することができる。または、情報処理装置5200Bはデジタル・サイネージ等に用いることができる。
<< Configuration Example 1 of Information Processing Apparatus >>
For example, an outer shape along a cylindrical column or the like can be applied to the display portion 5230 (see FIG. 15B). Further, the information processing device 5200B has a function of changing a display method according to the illuminance of the usage environment. Further, the information processing device 5200B has a function of detecting the presence of a person and changing display contents. Thereby, for example, the information processing apparatus 5200B can be installed on a pillar of a building. Alternatively, the information processing device 5200B can display an advertisement, a guidance, or the like. Alternatively, the information processing device 5200B can be used for digital signage or the like.
《情報処理装置の構成例2.》
例えば、情報処理装置5200Bは使用者が使用するポインタの軌跡に基づいて画像情報を生成する機能を備える(図15(C)参照)。具体的には、対角線の長さが20インチ以上、好ましくは40インチ以上、より好ましくは55インチ以上の表示パネルを用いることができる。または、複数の表示パネルを並べて1つの表示領域に用いることができる。または、複数の表示パネルを並べてマルチスクリーンに用いることができる。これにより、例えば、情報処理装置5200Bを電子黒板、電子掲示板、電子看板等に用いることができる。
<< Configuration Example 2 of Information Processing Apparatus >>
For example, the information processing device 5200B has a function of generating image information based on a locus of a pointer used by the user (see FIG. 15C). Specifically, a display panel having a diagonal line length of 20 inches or more, preferably 40 inches or more, more preferably 55 inches or more can be used. Alternatively, a plurality of display panels can be arranged and used for one display area. Alternatively, a plurality of display panels can be arranged and used for a multi-screen. Accordingly, for example, the information processing apparatus 5200B can be used for an electronic blackboard, an electronic bulletin board, an electronic signboard, and the like.
《情報処理装置の構成例3.》
例えば、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える(図15(D)参照)。これにより、例えば、スマートウオッチの消費電力を低減することができる。または、例えば、晴天の屋外等の外光の強い環境においてもスマートウオッチを好適に使用できるように、画像をスマートウオッチに表示することができる。
<< Configuration Example 3 of Information Processing Apparatus >>
For example, the information processing device 5200B has a function of changing the display method in accordance with the illuminance of the usage environment (see FIG. 15D). Thereby, for example, the power consumption of the smart watch can be reduced. Alternatively, for example, an image can be displayed on the smart watch so that the smart watch can be suitably used even in an environment with strong external light such as outdoors on a sunny day.
《情報処理装置の構成例4.》
表示部5230は、例えば、筐体の側面に沿って緩やかに曲がる曲面を備える(図15(E)参照)。または、表示部5230は表示パネルを備え、表示パネルは、例えば、前面、側面および上面に画像情報を表示する機能を備える。これにより、例えば、携帯電話の前面だけでなく、側面および上面に画像情報を表示することができる。
<< Configuration Example 4 of Information Processing Apparatus >>
The display portion 5230 includes, for example, a curved surface that bends gently along the side surface of the housing (see FIG. 15E). Alternatively, the display unit 5230 includes a display panel, and the display panel has a function of displaying image information on, for example, a front surface, a side surface, and an upper surface. Thereby, for example, image information can be displayed not only on the front surface of the mobile phone but also on the side surface and the upper surface.
《情報処理装置の構成例5.》
例えば、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える(図16(A)参照)。これにより、スマートフォンの消費電力を低減することができる。または、例えば、晴天の屋外等の外光の強い環境においてもスマートフォンを好適に使用できるように、画像をスマートフォンに表示することができる。
<< Configuration Example 5 of Information Processing Apparatus >>
For example, the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16A). Thereby, the power consumption of a smart phone can be reduced. Or an image can be displayed on a smart phone so that a smart phone can be used conveniently also in an environment with strong external light, such as the outdoors of fine weather.
《情報処理装置の構成例6.》
例えば、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える(図16(B)参照)。これにより、晴天の日に屋内に差し込む強い外光が当たってもテレビジョンシステムを好適に使用できるように、映像をテレビジョンシステムに表示することができる。
<< Configuration Example of Information Processing Apparatus 6. >>
For example, the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16B). Thus, an image can be displayed on the television system so that the television system can be suitably used even when strong outside light that is inserted indoors on a sunny day.
《情報処理装置の構成例7.》
例えば、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える(図16(C)参照)。これにより、例えば、晴天の屋外等の外光の強い環境においてもタブレットコンピュータを好適に使用できるように、画像をタブレットコンピュータに表示することができる。
<< Configuration Example 7 of Information Processing Apparatus >>
For example, the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16C). Thereby, for example, an image can be displayed on the tablet computer so that the tablet computer can be suitably used even in an environment with strong external light such as outdoors on a sunny day.
《情報処理装置の構成例8.》
例えば、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える(図16(D)参照)。これにより、例えば、晴天の屋外等の外光の強い環境においても画像を好適に閲覧できるように、被写体をデジタルカメラに表示することができる。
<< Configuration Example of Information Processing Apparatus 8. >>
For example, the information processing device 5200B has a function of changing a display method in accordance with the illuminance of the usage environment (see FIG. 16D). Thus, for example, the subject can be displayed on the digital camera so that the image can be suitably viewed even in an environment with strong external light such as outdoors on a sunny day.
《情報処理装置の構成例9.》
例えば、情報処理装置5200Bは使用環境の照度に応じて、表示方法を変更する機能を備える(図16(E)参照)。これにより、例えば、晴天の屋外等の外光の強い環境においてもパーソナルコンピュータを好適に使用できるように、画像をパーソナルコンピュータに表示することができる。
<< Configuration Example 9 of Information Processing Apparatus >>
For example, the information processing device 5200B has a function of changing the display method in accordance with the illuminance of the usage environment (see FIG. 16E). Thus, for example, an image can be displayed on the personal computer so that the personal computer can be used favorably even in an environment with strong external light such as outdoors on a sunny day.
なお、本実施の形態は、本明細書で示す他の実施の形態と適宜組み合わせることができる。 Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.
例えば、本明細書等において、XとYとが接続されている、と明示的に記載されている場合は、XとYとが電気的に接続されている場合と、XとYとが機能的に接続されている場合と、XとYとが直接接続されている場合とが、本明細書等に開示されているものとする。したがって、所定の接続関係、例えば、図または文章に示された接続関係に限定されず、図または文章に示された接続関係以外のものも、図または文章に記載されているものとする。 For example, in this specification and the like, when X and Y are explicitly described as being connected, X and Y are electrically connected, and X and Y are functional. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.
ここで、X、Yは、対象物(例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など)であるとする。 Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
XとYとが直接的に接続されている場合の一例としては、XとYとの電気的な接続を可能とする素子(例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など)が、XとYとの間に接続されていない場合であり、XとYとの電気的な接続を可能とする素子(例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など)を介さずに、XとYとが、接続されている場合である。 As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.
XとYとが電気的に接続されている場合の一例としては、XとYとの電気的な接続を可能とする素子(例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など)が、XとYとの間に1個以上接続されることが可能である。なお、スイッチは、オンオフが制御される機能を有している。つまり、スイッチは、導通状態(オン状態)、または、非導通状態(オフ状態)になり、電流を流すか流さないかを制御する機能を有している。または、スイッチは、電流を流す経路を選択して切り替える機能を有している。なお、XとYとが電気的に接続されている場合は、XとYとが直接的に接続されている場合を含むものとする。 As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.
XとYとが機能的に接続されている場合の一例としては、XとYとの機能的な接続を可能とする回路(例えば、論理回路(インバータ、NAND回路、NOR回路など)、信号変換回路(DA変換回路、AD変換回路、ガンマ補正回路など)、電位レベル変換回路(電源回路(昇圧回路、降圧回路など)、信号の電位レベルを変えるレベルシフタ回路など)、電圧源、電流源、切り替え回路、増幅回路(信号振幅または電流量などを大きく出来る回路、オペアンプ、差動増幅回路、ソースフォロワ回路、バッファ回路など)、信号生成回路、記憶回路、制御回路など)が、XとYとの間に1個以上接続されることが可能である。なお、一例として、XとYとの間に別の回路を挟んでいても、Xから出力された信号がYへ伝達される場合は、XとYとは機能的に接続されているものとする。なお、XとYとが機能的に接続されている場合は、XとYとが直接的に接続されている場合と、XとYとが電気的に接続されている場合とを含むものとする。 As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
なお、XとYとが電気的に接続されている、と明示的に記載されている場合は、XとYとが電気的に接続されている場合(つまり、XとYとの間に別の素子又は別の回路を挟んで接続されている場合)と、XとYとが機能的に接続されている場合(つまり、XとYとの間に別の回路を挟んで機能的に接続されている場合)と、XとYとが直接接続されている場合(つまり、XとYとの間に別の素子又は別の回路を挟まずに接続されている場合)とが、本明細書等に開示されているものとする。つまり、電気的に接続されている、と明示的に記載されている場合は、単に、接続されている、とのみ明示的に記載されている場合と同様な内容が、本明細書等に開示されているものとする。 In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that
なお、例えば、トランジスタのソース(又は第1の端子など)が、Z1を介して(又は介さず)、Xと電気的に接続され、トランジスタのドレイン(又は第2の端子など)が、Z2を介して(又は介さず)、Yと電気的に接続されている場合や、トランジスタのソース(又は第1の端子など)が、Z1の一部と直接的に接続され、Z1の別の一部がXと直接的に接続され、トランジスタのドレイン(又は第2の端子など)が、Z2の一部と直接的に接続され、Z2の別の一部がYと直接的に接続されている場合では、以下のように表現することが出来る。 Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. Then, it can be expressed as follows.
例えば、「XとYとトランジスタのソース(又は第1の端子など)とドレイン(又は第2の端子など)とは、互いに電気的に接続されており、X、トランジスタのソース(又は第1の端子など)、トランジスタのドレイン(又は第2の端子など)、Yの順序で電気的に接続されている。」と表現することができる。または、「トランジスタのソース(又は第1の端子など)は、Xと電気的に接続され、トランジスタのドレイン(又は第2の端子など)はYと電気的に接続され、X、トランジスタのソース(又は第1の端子など)、トランジスタのドレイン(又は第2の端子など)、Yは、この順序で電気的に接続されている」と表現することができる。または、「Xは、トランジスタのソース(又は第1の端子など)とドレイン(又は第2の端子など)とを介して、Yと電気的に接続され、X、トランシスタのソース(又は第1の端子など)、トランジスタのドレイン(又は第2の端子など)、Yは、この接続順序で設けられている」と表現することができる。これらの例と同様な表現方法を用いて、回路構成における接続の順序について規定することにより、トランジスタのソース(又は第1の端子など)と、ドレイン(又は第2の端子など)とを、区別して、技術的範囲を決定することができる。 For example, “X and Y, and the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are electrically connected to each other. The drain of the transistor (or the second terminal, etc.) and the Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Or the first terminal or the like, the drain of the transistor (or the second terminal, or the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal) and the drain (or the second terminal) of the transistor, and X is the source of the transistor (or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are separated. Apart from that, the technical scope can be determined.
または、別の表現方法として、例えば、「トランジスタのソース(又は第1の端子など)は、少なくとも第1の接続経路を介して、Xと電気的に接続され、前記第1の接続経路は、第2の接続経路を有しておらず、前記第2の接続経路は、トランジスタを介した、トランジスタのソース(又は第1の端子など)とトランジスタのドレイン(又は第2の端子など)との間の経路であり、前記第1の接続経路は、Z1を介した経路であり、トランジスタのドレイン(又は第2の端子など)は、少なくとも第3の接続経路を介して、Yと電気的に接続され、前記第3の接続経路は、前記第2の接続経路を有しておらず、前記第3の接続経路は、Z2を介した経路である。」と表現することができる。または、「トランジスタのソース(又は第1の端子など)は、少なくとも第1の接続経路によって、Z1を介して、Xと電気的に接続され、前記第1の接続経路は、第2の接続経路を有しておらず、前記第2の接続経路は、トランジスタを介した接続経路を有し、トランジスタのドレイン(又は第2の端子など)は、少なくとも第3の接続経路によって、Z2を介して、Yと電気的に接続され、前記第3の接続経路は、前記第2の接続経路を有していない。」と表現することができる。または、「トランジスタのソース(又は第1の端子など)は、少なくとも第1の電気的パスによって、Z1を介して、Xと電気的に接続され、前記第1の電気的パスは、第2の電気的パスを有しておらず、前記第2の電気的パスは、トランジスタのソース(又は第1の端子など)からトランジスタのドレイン(又は第2の端子など)への電気的パスであり、トランジスタのドレイン(又は第2の端子など)は、少なくとも第3の電気的パスによって、Z2を介して、Yと電気的に接続され、前記第3の電気的パスは、第4の電気的パスを有しておらず、前記第4の電気的パスは、トランジスタのドレイン(又は第2の端子など)からトランジスタのソース(又は第1の端子など)への電気的パスである。」と表現することができる。これらの例と同様な表現方法を用いて、回路構成における接続経路について規定することにより、トランジスタのソース(又は第1の端子など)と、ドレイン(又は第2の端子など)とを、区別して、技術的範囲を決定することができる。 Alternatively, as another expression method, for example, “a source (or a first terminal or the like of a transistor) is electrically connected to X through at least a first connection path, and the first connection path is The second connection path does not have a second connection path, and the second connection path includes a transistor source (or first terminal or the like) and a transistor drain (or second terminal or the like) through the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path. The third connection path is connected and does not have the second connection path, and the third connection path is a path through Z2. " Or, “the source (or the first terminal or the like) of the transistor is electrically connected to X via Z1 by at least a first connection path, and the first connection path is a second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal, etc.) of the transistor is at least connected to Z2 by the third connection path. , Y, and the third connection path does not have the second connection path. Or “the source of the transistor (or the first terminal or the like) is electrically connected to X through Z1 by at least a first electrical path, and the first electrical path is a second electrical path Does not have an electrical path, and the second electrical path is an electrical path from the source (or first terminal or the like) of the transistor to the drain (or second terminal or the like) of the transistor; The drain (or the second terminal or the like) of the transistor is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path is a fourth electrical path. The fourth electrical path is an electrical path from the drain (or second terminal or the like) of the transistor to the source (or first terminal or the like) of the transistor. can do. Using the same expression method as those examples, by defining the connection path in the circuit configuration, the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are distinguished. The technical scope can be determined.
なお、これらの表現方法は、一例であり、これらの表現方法に限定されない。ここで、X、Y、Z1、Z2は、対象物(例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など)であるとする。 In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).
なお、回路図上は独立している構成要素同士が電気的に接続しているように図示されている場合であっても、1つの構成要素が、複数の構成要素の機能を併せ持っている場合もある。例えば配線の一部が電極としても機能する場合は、一の導電膜が、配線の機能、及び電極の機能の両方の構成要素の機能を併せ持っている。したがって、本明細書における電気的に接続とは、このような、一の導電膜が、複数の構成要素の機能を併せ持っている場合も、その範疇に含める。 In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
AF1  配向膜
AF2  配向膜
C11  容量素子
C12  容量素子
DS  検知情報
G1  走査線
KB1  構造体
M  トランジスタ
P1  位置情報
S1  信号線
SS  制御情報
SW1  スイッチ
Tm11  端子
Tm12  端子
Tm13  端子
Tr1  トランジスタ
Tr2  トランジスタ
Tr3  トランジスタ
Tr4  トランジスタ
V1  画像情報
V11  情報
200  情報処理装置
210  演算装置
211  演算部
212  記憶部
214  伝送路
215  入出力インターフェース
220  入出力装置
230  表示部
231  表示領域
233  タイミングコントローラ
234  伸張回路
235M  画像処理回路
238  制御部
240  入力部
241  検知領域
250  検知部
290  通信部
501C  絶縁膜
504  導電膜
506  絶縁膜
508  半導体膜
508A  領域
508B  領域
508C  領域
510  基板
512A  導電膜
512B  導電膜
516  絶縁膜
519B  端子
520  機能層
521  絶縁膜
521A  絶縁膜
521B  絶縁膜
524  導電膜
528  絶縁膜
530  画素回路
550  表示素子
551  電極
552  電極
553  発光性の材料を含む層
578  乾燥剤
591A  接続部
591B  接続部
700  表示パネル
700B  表示パネル
700TP  入出力パネル
702  画素
703  画素
720  機能層
750  表示素子
751  電極
752  電極
753  液晶材料を含む層
770  基板
770D  機能膜
770P  機能膜
771  絶縁膜
775  検知素子
5200B  情報処理装置
5210  演算装置
5220  入出力装置
5230  表示部
5240  入力部
5250  検知部
5290  通信部
AF1 Alignment film AF2 Alignment film C11 Capacitance element C12 Capacitance element DS Detection information G1 Scan line KB1 Structure M Transistor P1 Position information S1 Signal line SS Control information SW1 Switch Tm11 Terminal Tm12 Terminal Tm13 Terminal Tr1 Transistor Tr2 Transistor Tr3 Transistor Tr4 Transistor V1 Image Information V11 Information 200 Information processing device 210 Computing device 211 Computing unit 212 Storage unit 214 Transmission path 215 I / O interface 220 I / O device 230 Display unit 231 Display area 233 Timing controller 234 Expansion circuit 235M Image processing circuit 238 Control unit 240 Input unit 241 Detection region 250 Detection unit 290 Communication unit 501C Insulating film 504 Conductive film 506 Insulating film 508 Semiconductor film 508A Region 50 B region 508C region 510 substrate 512A conductive film 512B conductive film 516 insulating film 519B terminal 520 functional layer 521 insulating film 521A insulating film 521B insulating film 524 conductive film 528 insulating film 530 pixel circuit 550 display element 551 electrode 552 electrode 553 light emitting material Layer 578 desiccant 591A connecting portion 591B connecting portion 700 display panel 700B display panel 700TP input / output panel 702 pixel 703 pixel 720 functional layer 750 display element 751 electrode 752 electrode 753 layer containing liquid crystal material 770 substrate 770D functional film 770P functional film 771 Insulating film 775 Detection element 5200B Information processing device 5210 Arithmetic device 5220 Input / output device 5230 Display unit 5240 Input unit 5250 Detection unit 5290 Communication unit

Claims (11)

  1.  バッファアンプと、
     表示領域と、を有し、
     前記バッファアンプは、第1のトランジスタおよび第2のトランジスタを備え、
     前記表示領域は、信号線および画素を備え、
     前記画素は、画素回路を備え、
     前記画素回路は、第3のトランジスタを備え、
     前記信号線は、前記第1のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、
     前記信号線は、前記第2のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、
     前記信号線は、前記第3のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、
     前記第1のトランジスタは、第1の半導体を備え、
     前記第2のトランジスタは、第2の半導体を備え、
     前記第3のトランジスタは、第3の半導体を備え、
     前記第3の半導体は、前記第2の半導体に含まれる元素を含む、表示パネル。
    A buffer amplifier,
    A display area;
    The buffer amplifier includes a first transistor and a second transistor,
    The display area includes signal lines and pixels,
    The pixel includes a pixel circuit;
    The pixel circuit includes a third transistor,
    The signal line is electrically connected to one of a source electrode and a drain electrode of the first transistor;
    The signal line is electrically connected to one of a source electrode or a drain electrode of the second transistor;
    The signal line is electrically connected to one of a source electrode or a drain electrode of the third transistor;
    The first transistor includes a first semiconductor,
    The second transistor includes a second semiconductor,
    The third transistor includes a third semiconductor,
    The display panel, wherein the third semiconductor includes an element included in the second semiconductor.
  2.  前記第1の半導体は、単結晶シリコンを含み、
     前記第2の半導体は、金属酸化物を含む、請求項1に記載の表示パネル。
    The first semiconductor includes single crystal silicon;
    The display panel according to claim 1, wherein the second semiconductor includes a metal oxide.
  3.  半導体装置を有し、
     前記半導体装置は、デジタルアナログ変換回路を備え、
     前記半導体装置は、第1の端子、第2の端子および第3の端子を備え、
     前記半導体装置は、前記第1のトランジスタを備え、
     前記第1の端子は、前記デジタルアナログ変換回路と電気的に接続され、
     前記第2の端子は、前記第1のトランジスタの前記ソース電極または前記ドレイン電極と電気的に接続され、
     前記第2の端子は、前記信号線と電気的に接続され、
     前記第3の端子は、前記第2のトランジスタのゲート電極と電気的に接続される、請求項1または請求項2に記載の表示パネル。
    Having a semiconductor device,
    The semiconductor device includes a digital-analog conversion circuit,
    The semiconductor device includes a first terminal, a second terminal, and a third terminal,
    The semiconductor device includes the first transistor,
    The first terminal is electrically connected to the digital-analog conversion circuit,
    The second terminal is electrically connected to the source electrode or the drain electrode of the first transistor;
    The second terminal is electrically connected to the signal line;
    The display panel according to claim 1, wherein the third terminal is electrically connected to a gate electrode of the second transistor.
  4.  表示領域と、
     デジタルアナログ変換回路と、を有し、
     前記表示領域は、画素および信号線を備え、
     前記画素は、画素回路を備え、
     前記画素回路は、第3のトランジスタを備え、
     前記信号線は、前記第3のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、
     前記第3のトランジスタは、第3の半導体を備え、
     前記第3の半導体は、金属酸化物を含み、
     前記デジタルアナログ変換回路は、パラレル信号を供給され、
     前記デジタルアナログ変換回路は、アナログ信号を供給し、
     前記デジタルアナログ変換回路は、パストランジスタ・ロジック回路および抵抗ストリングを備え、
     前記抵抗ストリングは、前記パストランジスタ・ロジック回路と電気的に接続され、
     前記パストランジスタ・ロジック回路は、第4のトランジスタを備え、
     前記信号線は、前記第4のトランジスタのソース電極またはドレイン電極の一方と電気的に接続され、
     前記第4のトランジスタは、第4の半導体を備え、
     前記第4の半導体は、前記第3の半導体に含まれる元素を含む、表示パネル。
    A display area;
    A digital-analog conversion circuit,
    The display area includes pixels and signal lines,
    The pixel includes a pixel circuit;
    The pixel circuit includes a third transistor,
    The signal line is electrically connected to one of a source electrode or a drain electrode of the third transistor;
    The third transistor includes a third semiconductor,
    The third semiconductor includes a metal oxide,
    The digital-analog converter circuit is supplied with a parallel signal,
    The digital-analog converter circuit supplies an analog signal,
    The digital-analog converter circuit includes a pass transistor logic circuit and a resistor string,
    The resistor string is electrically connected to the pass transistor logic circuit;
    The pass transistor logic circuit includes a fourth transistor;
    The signal line is electrically connected to one of a source electrode and a drain electrode of the fourth transistor;
    The fourth transistor includes a fourth semiconductor,
    The display panel, wherein the fourth semiconductor includes an element included in the third semiconductor.
  5.  シフトレジスタと、
     ラッチ回路と、を有し、
     前記ラッチ回路は、前記シフトレジスタと電気的に接続され、
     前記パストランジスタ・ロジック回路は、前記ラッチ回路と電気的に接続され、
     前記シフトレジスタは、n型のトランジスタのみを含み、
     前記ラッチ回路は、n型のトランジスタのみを含む請求項4に記載の表示パネル。
    A shift register;
    And a latch circuit,
    The latch circuit is electrically connected to the shift register;
    The pass transistor logic circuit is electrically connected to the latch circuit;
    The shift register includes only n-type transistors,
    The display panel according to claim 4, wherein the latch circuit includes only an n-type transistor.
  6.  前記表示領域は、一群の複数の画素、他の一群の複数の画素、走査線を備え、
     前記一群の複数の画素は、行方向に配設され、
     前記一群の複数の画素は、前記画素を含み、
     前記他の一群の複数の画素は、行方向と交差する列方向に配設され、
     前記走査線は、前記一群の複数の画素と電気的に接続され、
     前記信号線は、前記他の一群の複数の画素と電気的に接続される、請求項1、請求項2、請求項4および請求項5のいずれか一に記載の表示パネル。
    The display area includes a group of a plurality of pixels, another group of a plurality of pixels, and a scanning line.
    The group of pixels is arranged in a row direction,
    The group of pixels includes the pixels;
    The other group of the plurality of pixels is arranged in a column direction intersecting the row direction,
    The scanning line is electrically connected to the plurality of pixels in the group,
    The display panel according to claim 1, wherein the signal line is electrically connected to the plurality of pixels of the other group.
  7.  前記表示領域は、複数の画素を行列状に備え、
     前記表示領域は、7600個以上の画素を行方向に備え、
     前記表示領域は、4300個以上の画素を列方向に備える、請求項1または請求項2に記載の表示パネル。
    The display area includes a plurality of pixels in a matrix,
    The display area comprises 7600 or more pixels in the row direction,
    The display panel according to claim 1, wherein the display area includes 4300 or more pixels in a column direction.
  8.  前記表示領域は、第1の画素、第2の画素および第3の画素を備え、
     前記第1の画素は、CIE1931色度座標における色度xが0.680より大きく0.720以下、色度yが0.260以上0.320以下の色を表示し、
     前記第2の画素は、CIE1931色度座標における色度xが0.130以上0.250以下、色度yが0.710より大きく0.810以下の色を表示し、
     前記第3の画素は、CIE1931色度座標における色度xが0.120以上0.170以下、色度yが0.020以上0.060未満の色を表示する、請求項1または請求項2に記載の表示パネル。
    The display area includes a first pixel, a second pixel, and a third pixel,
    The first pixel displays a color having a chromaticity x in the CIE 1931 chromaticity coordinates of greater than 0.680 and less than or equal to 0.720, and a chromaticity y of 0.260 or more and 0.320 or less.
    The second pixel displays a color having a chromaticity x in the CIE1931 chromaticity coordinates of 0.130 or more and 0.250 or less, and a chromaticity y of more than 0.710 and 0.810 or less.
    The third pixel displays a color having a chromaticity x in a CIE1931 chromaticity coordinate of 0.120 to 0.170 and a chromaticity y of 0.020 to less than 0.060. The display panel described in 1.
  9.  請求項1請求項2に記載の表示パネルと、
     制御部と、を有し、
     前記制御部は、画像情報および制御情報を供給され、
     前記制御部は、前記画像情報に基づいて情報を生成し、
     前記制御部は、前記情報を供給し、
     前記情報は、12bit以上の階調を含み、
     前記表示パネルは、前記情報を供給され、
     前記走査線は、60Hz以上の頻度で選択信号を供給され、
     前記表示素子は、前記情報に基づいて表示する、表示装置。
    A display panel according to claim 1;
    A control unit,
    The control unit is supplied with image information and control information,
    The control unit generates information based on the image information,
    The controller supplies the information;
    The information includes a gradation of 12 bits or more,
    The display panel is supplied with the information,
    The scanning line is supplied with a selection signal at a frequency of 60 Hz or more,
    The display device displays based on the information.
  10.  入力部と、表示部と、を有し、
     前記表示部は、請求項1、請求項2、請求項4および請求項5のいずれか一に記載の表示パネルを備え、
     前記入力部は、検知領域を備え、
     前記入力部は、前記検知領域に近接するものを検知し、
     前記検知領域は、前記画素と重なる領域を備える入出力装置。
    An input unit and a display unit;
    The display unit includes the display panel according to any one of claims 1, 2, 4, and 5,
    The input unit includes a detection area,
    The input unit detects an object close to the detection area,
    The input / output device, wherein the detection area includes an area overlapping with the pixel.
  11.  キーボード、ハードウェアボタン、ポインティングデバイス、タッチセンサ、照度センサ、撮像装置、音声入力装置、視線入力装置、姿勢検出装置、のうち一以上と、請求項1、請求項2、請求項4および請求項5のいずれか一に記載の表示パネルと、を含む、情報処理装置。 One or more of a keyboard, a hardware button, a pointing device, a touch sensor, an illuminance sensor, an imaging device, a voice input device, a line-of-sight input device, and a posture detection device; and claim 1, claim 2, claim 4, and claim 4. An information processing apparatus comprising: the display panel according to claim 5.
PCT/IB2018/051017 2017-03-03 2018-02-20 Display panel, display device, input/output device, and information processing device WO2018158651A1 (en)

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