JP7045148B2 - Differential circuit - Google Patents

Description

The present invention relates to a differential circuit.

An operational amplifier, which is an example of a differential circuit, is used in various electronic devices. For example, the operational amplifier described in Patent Document 1 is used in a liquid crystal drive device.

Japanese Unexamined Patent Publication No. 2011-172203

Further improvement in noise of the output signal of the operational amplifier is desired.
An object of the present invention is to provide a differential circuit capable of reducing noise in an output signal.

[1] In the differential circuit for solving the above problems, the first power supply wiring to which the first power supply voltage is applied and the second power supply to which the second power supply voltage different from the first power supply voltage is applied are applied. The source potential of the first MOS transistor and the second MOS transistor with respect to the differential pair including the first MOS transistor and the second MOS transistor provided between the wiring and the back gate of the first MOS transistor and the second MOS transistor. It also includes a backgate bias circuit that applies a bias voltage closer to the first power supply voltage.

The inventors of the present application have focused on the transconductance of the first MOS transistor and the second MOS transistor constituting the differential pair as a parameter that affects the noise of the output signal of the differential circuit. Specifically, as the transconductance increases, the noise of the output signal of the differential circuit decreases. Then, the inventors of the present application describe the transformers of the first MOS transistor and the second MOS transistor as the voltage between the back gate and the source, which is the voltage between the back gate and the source of the first MOS transistor and the second MOS transistor constituting the differential pair, increases. We have found that the conductance increases. Therefore, when the bias voltage applied to the back gates of the first MOS transistor and the second MOS transistor is closer to the first power supply voltage than the source potential, the bias voltage is the back gate of the first MOS transistor and the second MOS transistor and the source. The transconductivity of the first MOS transistor and the second MOS transistor is larger than that of the case where the voltage is equal to the voltage between them.

Therefore, in this differential circuit, a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor is applied to the back gate of the first MOS transistor and the second MOS transistor by the back gate bias circuit. .. As a result, the voltage between the back gate and the source of the first MOS transistor and the second MOS transistor becomes large. As a result, the transconductance of the first MOS transistor and the second MOS transistor is increased, so that the noise of the output signal of the differential circuit can be reduced.

[2] In the differential circuit, the first MOS transistor and the first MOS transistor are provided between the first power supply wiring and the differential pair, and the first power supply voltage is set higher than the first power supply voltage. It is preferable to include a voltage conversion circuit that converts a voltage closer to the source potential of the 2MOS transistor.

According to the above configuration, the backgate-source voltage, which is the voltage between the backgate and the source of the first MOS transistor and the second MOS transistor, can be increased. Therefore, the noise of the output signal of the differential circuit can be reduced.

[3] In the differential circuit, the backgate bias circuit generates the bias voltage by a third power supply voltage different from the first power supply voltage, and the first power supply voltage is the third power supply voltage. It is preferable that the voltage is closer to the source potential of the first MOS transistor and the second MOS transistor than the power supply voltage.

According to the above configuration, the backgate-source voltage, which is the voltage between the backgate and the source of the first MOS transistor and the second MOS transistor, can be increased. Therefore, the noise of the output signal of the differential circuit can be reduced.

[4] In the differential circuit, the bias voltage is preferably a voltage excluding the voltage within a predetermined range including the first power supply voltage, which is the same as the first power supply voltage.
According to the above configuration, the noise of the first power supply wiring is less likely to be affected, and the transconductance of the first MOS transistor and the second MOS transistor is increased. Therefore, the noise of the output signal of the differential circuit can be further reduced.

[5] In the differential circuit, the first power supply voltage is higher than the second power supply voltage, the first MOS transistor and the second MOS transistor are P-channel MOS transistors, and the bias voltage is the first. It is preferably higher than the power supply voltage of 1.

According to the above configuration, the noise of the output signal of the differential circuit can be further reduced.
[6] In the differential circuit, the bias voltage is preferably less than the voltage at which the parasitic diodes of the first MOS transistor and the second MOS transistor are turned on.

According to the above configuration, the first MOS transistor and the second MOS transistor can operate stably.
[7] In the differential circuit, the bias voltage is preferably a voltage within ± 20% of the first power supply voltage.

According to the above configuration, the noise of the output signal of the differential circuit can be effectively reduced.
[8] In the differential circuit, the second power supply voltage is higher than the first power supply voltage, the first MOS transistor and the second MOS transistor are N-channel MOS transistors, and the bias voltage is the first. It is preferably lower than the power supply voltage of 1.

According to the above configuration, the noise of the output signal of the differential circuit can be further reduced.
[9] In the differential circuit, an active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor, the third MOS transistor, and the second power supply wiring. It is preferable to provide a first resistance portion provided between the two, and a second resistance portion provided between the fourth MOS transistor and the second power supply wiring.

As the transconductance of the third MOS transistor and the fourth MOS transistor as the active load becomes smaller, the noise of the output signal of the differential circuit becomes smaller.
In this regard, according to the above configuration, when a drain current flows through the 3rd MOS transistor and the 4th MOS transistor and the gate-source voltage of the 3rd MOS transistor and the 4th MOS transistor rises, the first resistance section and the second resistance section provide a second resistance. The source potential of the 3MOS transistor and the 4th MOS transistor rises. As a result, it operates so as to prevent an increase in the drain current flowing through the third MOS transistor and the fourth MOS transistor. That is, as the effective transconductivity of the 3rd MOS transistor and the 4th MOS transistor, when viewed from the drain side of the 3rd MOS transistor and the 4th MOS transistor, the 3rd MOS transistor and the 4th MOS transistor depend on the 1st resistance portion and the 2nd resistance portion. The voltage between the gate and source becomes smaller. As a result, the third MOS transistor and the fourth MOS transistor operate in the direction of reducing the drain current. Therefore, the transconductance on the circuits of the third MOS transistor and the fourth MOS transistor is lowered. This makes it possible to reduce the noise of the output signal of the differential circuit.

[10] In the differential circuit, a first control unit that controls the source potential of the third MOS transistor by supplying a current between the source of the third MOS transistor and the first resistance unit, and the first control unit. It is preferable to include a second control unit that controls the source potential of the fourth MOS transistor by supplying a current between the source of the 4MOS transistor and the second resistance unit.

According to the above configuration, the source potential of the third MOS transistor can be controlled by the first control unit, and the source potential of the fourth MOS transistor can be controlled by the second control unit. Therefore, the effective transconductance of the third MOS transistor and the fourth MOS transistor can be determined. Can be made smaller. Therefore, the noise of the output signal of the differential circuit can be reduced.

[11] In the differential circuit, the first control unit includes a first control transistor connected between the source of the third MOS transistor and the first resistance unit, and the second control unit includes the first control transistor. The voltage of the control terminal of the first control transistor and the second control transistor includes the second control transistor connected between the source of the fourth MOS transistor and the second resistance portion. , It is preferable that the control is performed by the gate voltage of the third MOS transistor and the fourth MOS transistor.

According to the above configuration, the increase in the current flowing through the first MOS transistor and the second MOS transistor can be suppressed from flowing to the third MOS transistor and the fourth MOS transistor, and the source potential of the third MOS transistor and the fourth MOS transistor can be increased. can.

[12] In the differential circuit, the first control unit further includes a first current source connected to the first power supply wiring and the first control transistor, and the second control unit is the second control unit. It is preferable to further include a first power supply wiring and a second current source connected to the second control transistor.

[13] In the differential circuit, it is preferable to further include a current adjusting unit that makes the current flowing through the first MOS transistor and the second MOS transistor larger than the current flowing through the third MOS transistor and the fourth MOS transistor.

As the transconductivity of the first MOS transistor and the second MOS transistor constituting the differential pair increases, the noise of the output signal of the differential circuit decreases, while the transconductivity of the third MOS transistor and the fourth MOS transistor constituting the active load increases. As the result increases, the noise of the output signal of the differential circuit increases.

In this regard, according to the above configuration, the current adjusting unit increases the transconductance of the first MOS transistor and the second MOS transistor by increasing the current flowing through the first MOS transistor and the second MOS transistor constituting the differential pair. On the other hand, since the current flowing through the 3rd MOS transistor and the 4th MOS transistor constituting the active load is smaller than the current flowing through the 1st MOS transistor and the 2nd MOS transistor, the current flowing through the 1st MOS transistor and the 2nd MOS transistor is increased. The increase in the transconductivity of the 3MOS transistor and the 4th MOS transistor is suppressed. Therefore, the noise of the output signal of the differential circuit can be reduced.

[14] In the differential circuit, the current adjusting unit is connected in parallel with the first adjusting transistor connected in parallel with the third MOS transistor, and the control terminal is connected in parallel with the fourth MOS transistor. It is preferable to have a second adjusting transistor connected to the control terminal of the adjusting transistor.

According to the above configuration, a part of the current from the first MOS transistor and the second MOS transistor flows to the first adjustment transistor and the second adjustment transistor, and does not flow to the drain of the third MOS transistor and the fourth MOS transistor. Therefore, the current flowing through the third MOS transistor and the fourth MOS transistor is smaller than the current flowing through the first MOS transistor and the second MOS transistor. Therefore, the noise of the output signal of the differential circuit can be reduced.

[15] In the differential circuit, the current adjusting unit calculates the adjusting current of the total amount of the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor. It is preferable to have a current supply unit that supplies the differential pair.

According to the above configuration, the current supplied to the differential pair by the current supply unit is passed through the first adjusting transistor and the second adjusting transistor, so that the amount of current supplied to the differential pair increases. On the other hand, the amount of current supplied to the active load does not increase. Therefore, while the transconductance of the first MOS transistor and the second MOS transistor increases, the transconductance of the third MOS transistor and the fourth MOS transistor does not increase. Therefore, the noise of the output signal of the differential circuit can be reduced.

[16] In the differential circuit, the current supply unit is a first supply transistor and a second supply transistor connected in series between the first power supply wiring and the second power supply wiring. And a third supply transistor provided between the first power supply wiring and the differential pair, and a second supply transistor provided between the second supply transistor and the second power supply wiring. The first supply transistor including the three resistance portions is provided between the second supply transistor and the first power supply wiring, and the second supply transistor has a control terminal thereof. The third supply transistor is connected to the control terminal of the first adjustment transistor and the control terminal of the second adjustment transistor, and the third supply transistor constitutes the current mirror circuit with the first supply transistor. It is preferable to supply the adjustment current to the differential pair.

According to the above configuration, the current supplied to the differential pair by the current supply unit is passed through the first adjusting transistor and the second adjusting transistor, so that the amount of current supplied to the differential pair increases. On the other hand, the amount of current supplied to the active load does not increase. Therefore, the noise of the output signal of the differential circuit can be reduced.

[17] In the differential circuit, it is preferable that the first adjusting transistor and the second adjusting transistor pass a current equal to or less than the current flowing through the third MOS transistor.

When there is a difference between the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor due to the element variation of the first adjusting transistor and the second adjusting transistor, the third MOS transistor and the third MOS transistor and The current flowing through the 4th MOS transistor may be affected, and the offset voltage of the 3rd MOS transistor and the 4th MOS transistor may be generated.

In that respect, according to the above configuration, the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor are equal to or less than the current flowing through the third MOS transistor, so that the elements of each adjusting transistor vary. The effect on the current flowing through the third MOS transistor and the fourth MOS transistor can be reduced.

[18] In the differential circuit, an active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor and having a gate connected to the gate of the third MOS transistor. It is preferable to include a current adjusting unit that makes the current flowing through the first MOS transistor and the second MOS transistor larger than the current flowing through the third MOS transistor and the fourth MOS transistor.

According to the above configuration, the current adjusting unit increases the transconductance of the first MOS transistor and the second MOS transistor by increasing the current flowing through the first MOS transistor and the second MOS transistor constituting the differential pair. On the other hand, since the current flowing through the 3rd MOS transistor and the 4th MOS transistor constituting the active load is smaller than the current flowing through the 1st MOS transistor and the 2nd MOS transistor, the current flowing through the 1st MOS transistor and the 2nd MOS transistor is increased. The increase in the transconductivity of the 3MOS transistor and the 4th MOS transistor is suppressed. Therefore, the noise of the output signal of the differential circuit can be reduced.

[19] In the differential circuit, the current adjusting unit is connected in parallel with the first adjusting transistor connected in parallel with the third MOS transistor, and the control terminal is connected in parallel with the fourth MOS transistor. It is preferable to have a second adjusting transistor connected to the control terminal of the adjusting transistor.

According to the above configuration, a part of the current from the first MOS transistor and the second MOS transistor flows to the first adjustment transistor and the second adjustment transistor, and does not flow to the drain of the third MOS transistor and the fourth MOS transistor. Therefore, the current flowing through the third MOS transistor and the fourth MOS transistor is smaller than the current flowing through the first MOS transistor and the second MOS transistor. Therefore, the noise of the output signal of the differential circuit can be reduced.

[20] In the differential circuit, the current adjusting unit determines the adjusting current of the total amount of the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor. It is preferable to have a current supply unit that supplies the differential pair.

According to the above configuration, the current supplied to the differential pair by the current supply unit is passed through the first adjusting transistor and the second adjusting transistor, so that the amount of current supplied to the differential pair increases. On the other hand, the amount of current supplied to the active load does not increase. Therefore, while the transconductance of the first MOS transistor and the second MOS transistor increases, the transconductance of the third MOS transistor and the fourth MOS transistor does not increase. Therefore, the noise of the output signal of the differential circuit can be reduced.

[21] In the differential circuit, the current supply unit is a first supply transistor and a second supply transistor connected in series between the first power supply wiring and the second power supply wiring. And a third supply transistor provided between the first power supply wiring and the differential pair, the first supply transistor includes the second supply transistor and the first supply transistor. The second supply transistor is provided between the power supply wiring and the control terminal thereof is connected to the control terminal of the first adjustment transistor and the control terminal of the second adjustment transistor. It is preferable that the supply transistor of No. 3 constitutes a current mirror circuit with the first supply transistor and supplies the adjustment current to the differential pair.

According to the above configuration, the current supplied to the differential pair by the current supply unit is passed through the first adjusting transistor and the second adjusting transistor, so that the amount of current supplied to the differential pair increases. On the other hand, the amount of current supplied to the active load does not increase. Therefore, the noise of the output signal of the differential circuit can be reduced.

[22] In the differential circuit, it is preferable that the first adjusting transistor and the second adjusting transistor pass a current equal to or less than the current flowing through the third MOS transistor.

When there is a difference between the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor due to the element variation of the first adjusting transistor and the second adjusting transistor, the third MOS transistor and the third MOS transistor and The current flowing through the 4th MOS transistor may be affected, and the offset voltage of the 3rd MOS transistor and the 4th MOS transistor may be generated.

In that respect, according to the above configuration, the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor are equal to or less than the current flowing through the third MOS transistor, so that the elements of each adjusting transistor vary. The effect on the current flowing through the third MOS transistor and the fourth MOS transistor can be reduced.

[23] In the differential circuit, the current supply unit biases the first adjusting transistor and the second adjusting transistor by a current source so that a current equal to or less than the current flowing through the third MOS transistor flows. It is preferable to do so.

According to the above configuration, the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor are equal to or less than the current flowing through the third MOS transistor, which is caused by the element variation of each adjusting transistor. The influence on the current flowing through the 3MOS transistor and the 4th MOS transistor can be reduced.

[24] In the differential circuit, the backgate bias circuit includes a plurality of MOS transistors, and the plurality of MOS transistors are high-concentration transistors in which the impurity concentration in the channel region is the first concentration, and the first MOS. The transistor and the second MOS transistor are preferably low-concentration transistors having a second concentration in which the impurity concentration in the channel region is lower than the first concentration.

According to the above configuration, the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor constituting the differential pair which is easily affected by 1 / f noise in the differential circuit affects the influence of 1 / f noise in the differential circuit. It becomes lower than the impurity concentration in the channel region in a plurality of transistors constituting the backgate bias circuit which is difficult to receive. Therefore, the fluctuation of the mobility can be suppressed, and the fluctuation of the drain current can be suppressed. Therefore, the 1 / f noise of the differential circuit can be effectively reduced.

Further, since the high-concentration transistor is used for the plurality of MOS transistors in the backgate bias circuit, the variation in the threshold voltage of the plurality of MOS transistors can be suppressed, so that the backgate bias circuit can operate stably.

[25] In the differential circuit, the second concentration is preferably about ½ or less of the first concentration.
According to the above configuration, 1 / f noise can be effectively reduced in the differential circuit.

[26] In the differential circuit, the second concentration is preferably about 1/10 of the first concentration.
According to the above configuration, 1 / f noise can be effectively reduced in the differential circuit.

[27] In the differential circuit, it is preferable that the third MOS transistor and the fourth MOS transistor of the active load are the low concentration transistors.
According to the above configuration, fluctuations in mobility can be suppressed by using low-concentration transistors for the third MOS transistor and the fourth MOS transistor that form an active load that is easily affected by 1 / f noise in the differential circuit. Fluctuations in drain current can be suppressed. Therefore, the 1 / f noise of the differential circuit can be effectively reduced.

[28] In the differential circuit, the third MOS transistor and the fourth MOS transistor are preferably embedded channel type MOS transistors.
According to the above configuration, in the third MOS transistor and the fourth MOS transistor that form an active load that is easily affected by 1 / f noise in the differential circuit, the influence of the interface between the gate insulating film and the semiconductor substrate by the embedded channel is affected by the channel region. You can suppress receiving. Therefore, the fluctuation of the mobility can be suppressed, and the fluctuation of the drain current can be suppressed. Therefore, the 1 / f noise of the differential circuit can be effectively reduced.

[29] In the differential circuit, the differential circuit includes a cascode current mirror circuit as an active load, and the cascode current mirror circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor. Including, the drain of the 5th MOS transistor is connected to the drain of the 1st MOS transistor, the source of the 5th MOS transistor is connected to the 2nd power supply wiring, and the drain of the 6th MOS transistor is connected to the drain of the 2nd MOS transistor. Connected, the source of the 6th MOS transistor is connected to the 2nd power supply wiring, the source of the 7th MOS transistor is connected to the drain of the 5th MOS transistor, and the source of the 8th MOS transistor is the 6th MOS transistor. The 7th MOS transistor and the gate of the 8th MOS transistor are connected in common, a predetermined bias voltage is applied, and the 5th MOS transistor and the 6th MOS transistor are the low concentration transistors. The 7th MOS transistor and the 8th MOS transistor are preferably high-concentration transistors.

According to the above configuration, the mobility is increased by using low-concentration transistors for the 5th and 6th MOS transistors that form the constant current source of the cascode current mirror circuit, which is easily affected by 1 / f noise in the differential circuit. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, the 1 / f noise of the differential circuit can be effectively reduced.

[30] In the differential circuit, the fifth MOS transistor and the sixth MOS transistor may be embedded channel type MOS transistors, and the seventh MOS transistor and the eighth MOS transistor may be surface channel type MOS transistors. preferable.

According to the above configuration, the embedded channel type MOS transistor is used in the 5th MOS transistor and the 6th MOS transistor constituting the constant current source of the cascode current mirror circuit which is easily affected by 1 / f noise in the differential circuit. Fluctuations in mobility can be suppressed, and fluctuations in drain current can be suppressed. Therefore, the 1 / f noise of the differential circuit can be effectively reduced.

[31] In the differential circuit, the plurality of MOS transistors are preferably surface channel type MOS transistors.
[32] In the differential circuit, the first MOS transistor and the second MOS transistor are preferably embedded channel type MOS transistors.

According to the above configuration, the mobility fluctuation is caused by using the embedded channel type MOS transistor in the first MOS transistor and the second MOS transistor which form a differential pair which is easily affected by 1 / f noise in the differential circuit. It can be suppressed and the fluctuation of the drain current can be suppressed. Therefore, the 1 / f noise of the differential circuit can be effectively reduced.

[33] In the differential circuit, the impurity concentration in the channel region of the first control transistor and the second control transistor is higher than the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor. Is preferable.

According to the above configuration, since the impurity concentration in the channel region of the first control transistor and the second control transistor is high, variation in the threshold voltage of each control transistor can be suppressed, and the first control unit and the first control unit and the first control transistor can be used. 2 The control unit can operate stably.

[34] In the differential circuit, the first control transistor and the second control transistor are preferably surface channel type MOS transistors.
[35] In the differential circuit, the impurity concentration in the channel region of the first adjusting transistor and the second adjusting transistor is higher than the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor. Is preferable.

According to the above configuration, since the impurity concentration in the channel region of the first adjusting transistor and the second adjusting transistor is high, it is possible to suppress the variation in the threshold voltage of each adjusting transistor and stabilize the current adjusting unit. Can work.

[36] In the differential circuit, the first adjusting transistor and the second adjusting transistor are preferably surface channel type MOS transistors.
[37] In the differential circuit, the impurity concentration in the channel region of the first supply transistor, the second supply transistor, and the third supply transistor is the first MOS transistor and the second MOS transistor. It is preferable that the concentration is higher than the impurity concentration in the channel region in.

According to the above configuration, since the impurity concentration in the channel region of the first to third supply transistors is high, variation in the threshold voltage of each supply transistor can be suppressed, and the current supply unit can operate stably.

[38] In the differential circuit, the first supply transistor, the second supply transistor, and the third supply transistor are preferably surface channel type MOS transistors.

[ 39 ] The differential circuit is preferably used as an operational amplifier.

According to the differential circuit, the noise of the output signal can be reduced.

The circuit diagram of the operational amplifier which comprises the differential circuit of 1st Embodiment. A circuit diagram of an operational amplifier showing an example of a backgate bias circuit of an operational amplifier. A graph showing the relationship between the transconductance of a differential pair and the backgate-source voltage of the differential pair. A graph showing the relationship between frequency and input-converted noise voltage. Sectional drawing of the 6th transistor which constitutes the back gate bias circuit of an operational amplifier. Sectional drawing of the 3rd transistor constituting the active load of an operational amplifier. Sectional drawing of the 8th transistor which constitutes the back gate bias circuit of an operational amplifier. FIG. 3 is a cross-sectional view of a first transistor constituting a differential pair of an operational amplifier. The cross-sectional view for demonstrating the manufacturing process of the 1st transistor, the 3rd transistor, the 6th transistor, and the 8th transistor. FIG. 6A is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6A. FIG. 6B is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6B. FIG. 6C is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6C. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6D. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6E. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6F. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6G. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6H. FIG. 6I is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6I. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6J. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6K. FIG. 6 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 6L. The schematic diagram for demonstrating the operation of this embodiment. The schematic diagram for demonstrating the operation of the comparative example. A graph showing the relationship between frequency and input-converted noise voltage. The circuit diagram of the operational amplifier of the modification of 1st Embodiment. FIG. 3 is a cross-sectional view of a third transistor constituting the active load of the operational amplifier in the differential circuit of the second embodiment. FIG. 3 is a cross-sectional view of a first transistor constituting a differential pair of an operational amplifier. The cross-sectional view for demonstrating the manufacturing process of the 1st transistor, the 3rd transistor, the 6th transistor, and the 8th transistor. FIG. 11A is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 11A. The schematic diagram for demonstrating the operation of this embodiment. The schematic diagram for demonstrating the operation of the comparative example. FIG. 3 is a cross-sectional view of a third transistor constituting the active load of the operational amplifier in the differential circuit of the third embodiment. FIG. 3 is a cross-sectional view of a first transistor constituting a differential pair of an operational amplifier. The cross-sectional view for demonstrating the manufacturing process of the 1st transistor, the 3rd transistor, the 6th transistor, and the 8th transistor. FIG. 14A is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 14A. FIG. 14B is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 14B. The circuit diagram of the operational amplifier of the 4th embodiment. The circuit diagram of the operational amplifier of the modification of 4th Embodiment. In the differential circuit of the fifth embodiment, (a) is a circuit diagram of an operational amplifier which is an example of a differential circuit, and (b) is a circuit diagram of a step-down circuit. The circuit diagram of the operational amplifier of the modification of 5th Embodiment. The circuit diagram of the operational amplifier of the sixth embodiment. The circuit diagram of the operational amplifier of the modification of 6th Embodiment. The circuit diagram of the operational amplifier of the 7th embodiment. A graph showing the relationship between frequency and input-converted noise voltage. The circuit diagram of the operational amplifier of the eighth embodiment. The circuit diagram of the operational amplifier of the 9th embodiment. A graph showing the relationship between frequency and input-converted noise voltage. The circuit diagram of the operational amplifier of the tenth embodiment. The circuit diagram of the operational amplifier of the eleventh embodiment. The circuit diagram of the operational amplifier of the twelfth embodiment. The circuit diagram of the operational amplifier of the thirteenth embodiment. The circuit diagram of the operational amplifier of the 14th embodiment. The circuit diagram of the operational amplifier of the fifteenth embodiment. The circuit diagram of the operational amplifier of the modification of the fifteenth embodiment. The circuit diagram of the operational amplifier of the 16th embodiment. The circuit diagram of the operational amplifier of the 17th embodiment. The circuit diagram of the operational amplifier of 18th Embodiment. The circuit diagram of the operational amplifier of the 19th embodiment. The circuit diagram of the operational amplifier of 20th Embodiment. The circuit diagram of the operational amplifier of the 21st embodiment. The circuit diagram of the operational amplifier of the 22nd embodiment. The circuit diagram of the operational amplifier of the 23rd embodiment. The circuit diagram of the integrating circuit which is an example of the differential circuit of 24th Embodiment. The circuit diagram of the integrator circuit of the 25th embodiment. The circuit diagram of the integrator circuit of the 26th embodiment. The circuit diagram of the operational amplifier of the 27th embodiment. The circuit diagram of the operational amplifier of the 28th embodiment. FIG. 3 is a cross-sectional view of a first transistor constituting a differential pair of an operational amplifier and a third transistor constituting an active load in a differential circuit of a modified example. The cross-sectional view for demonstrating the manufacturing process of the 1st transistor and the 3rd transistor. FIG. 4 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47A. FIG. 47B is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47B. FIG. 4 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47C. FIG. 4 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47D. FIG. 4 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47E. FIG. 4 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47F. FIG. 4 is a cross-sectional view for explaining the next step of the manufacturing process of each transistor of FIG. 47G.

Hereinafter, each embodiment of the differential circuit will be described with reference to the drawings. Each embodiment shown below exemplifies a configuration and a method for embodying a technical idea, and limits the material, shape, structure, arrangement, dimensions, etc. of each component to the following. is not it. Various modifications can be made to each of the following embodiments.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, and the member A and the member B are electrically connected. This includes the case of being indirectly connected via another member that does not affect the connection state.

Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and the member A. This includes the case where the member C and the member C, or the member B and the member C are indirectly connected via another member that does not affect the electrical connection state.

(First Embodiment)
As shown in FIG. 1, the operational amplifier 1 which is an example of the differential circuit amplifies the potential difference between the inverting input terminal INN and the non-inverting input terminal INP, and outputs an output signal Sout which is a voltage signal from the output terminal OUT. The operational amplifier 1 includes a differential pair 10, a constant current source 11, a current mirror circuit 12 as an active load, a reference current source 13, and a backgate bias circuit 20. The operational amplifier 1 is integrally integrated on one semiconductor substrate.

The differential pair 10 is a first transistor M1 provided between the first power supply wiring 2 to which the first power supply voltage VDD is applied and the second power supply wiring 3 to which the second power supply voltage VSS is applied. And the second transistor M2. The second power supply voltage VSS is a voltage different from that of the first power supply voltage VDD. In this embodiment, the second power supply voltage VSS is lower than the first power supply voltage VDD. The first transistor M1 and the second transistor M2 of this embodiment are P-channel MOSFETs. The first transistor M1 and the second transistor M2 may have either a depletion type structure or an enhancement type structure. In the present embodiment, the first transistor M1 and the second transistor M2 have an enhancement type structure. The gate of the first transistor M1 is connected to the non-inverting input terminal INP, and the gate of the second transistor M2 is connected to the inverting input terminal INN. The source of the first transistor M1 and the source of the second transistor M2 are commonly connected. The back gates of the first transistor M1 and the second transistor M2 are common. The back gates of the first transistor M1 and the second transistor M2 are connected to the bias terminal BIAS. The differential pair 10 generates differential currents ID1 and ID2 corresponding to the input voltages Vinn and Vinp of the inverting input terminal INN and the non-inverting input terminal INP, respectively.

The constant current source 11 is provided between the first power supply wiring 2 and the differential pair 10. The constant current source 11 is connected to the source of each transistor M1 and M2. The constant current source 11 of this embodiment includes a transistor. The transistor of the constant current source 11 is a P-channel MOSFET. The source of the transistor of the constant current source 11 is connected to the first power supply wiring 2, and the first power supply voltage VDD is applied.

The current mirror circuit 12 includes a third transistor M3 and a fourth transistor M4 connected to the differential pair 10. The third transistor M3 and the fourth transistor M4 of this embodiment are enhancement type N-channel MOSFETs. The sources of the third transistor M3 and the fourth transistor M4 are connected to the second power supply wiring 3, and the second power supply voltage VSS is applied. The drain and the gate of the third transistor M3 are commonly connected to the drain of the first transistor M1. The gate of the fourth transistor M4 is connected to the gate of the third transistor M3, and the drain of the fourth transistor M4 is connected to the drain of the second transistor M2. The back gates of the third transistor M3 and the fourth transistor M4 are connected to the second power supply wiring 3. An output terminal OUT is connected to the node N1 between the drain of the fourth transistor M4 and the drain of the second transistor M2.

The reference current source 13 supplies a current to the constant current source 11 so that the constant current source 11 can generate a constant current It. The reference current source 13 includes a transistor. The transistor of the reference current source 13 is a P-channel MOSFET. The source of the transistor of the reference current source 13 is connected to the first power supply wiring 2, and the drain of the transistor is connected to the second power supply wiring 3. The gate of the transistor is connected to the gate of the transistor of the constant current source 11 and is connected to a bias circuit (not shown). As described above, the transistor of the reference current source 13 constitutes the current mirror circuit with the transistor of the constant current source 11.

The backgate bias circuit 20 is connected to the bias terminal BIAS and the first power supply wiring 2, and is the backgate of the first transistor M1 and the second transistor M2 which are the back gates of the first transistor M1 and the second transistor M2 (FIG. 5D). Bias voltage VB is applied to the N-type well layer 39) in the above. Here, in FIG. 5D, the mode of applying the bias voltage VB to the back gate of the first transistor M1 is simplified (BG in FIG. 5D), but in reality, the bias voltage VB is shown to the back gate of the first transistor M1. A contact region (not shown) for applying the above is provided in the N-type well layer 39.

FIG. 2 is a circuit diagram of the operational amplifier 1 showing an example of the back gate bias circuit 20. The backgate bias circuit 20 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a constant current source 21. The fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 of the present embodiment are P-channel MOSFETs, and the sixth transistor M6 and the seventh transistor M7 are N-channel MOSFETs.

The fifth transistor M5 and the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8, the ninth transistor M9 and the constant current source 21 are respectively the first power supply wiring 2 and the second power supply wiring 3. They are connected in series between them. The sixth transistor M6 and the seventh transistor M7 form a current mirror circuit, and the eighth transistor M8 and the ninth transistor M9 form a current mirror circuit.

More specifically, the source of the 5th transistor M5 is connected to the 1st power supply wiring 2, the drain of the 5th transistor M5 is connected to the drain of the 6th transistor M6, and the gate of the 5th transistor M5 is connected to the 5th transistor M5. It is connected to the drain of. The back gate of the fifth transistor M5 is connected to the source of the fifth transistor M5. A bias terminal BIAS is connected to the node N2 between the drain of the fifth transistor M5 and the drain of the sixth transistor M6. The source of the sixth transistor M6 is connected to the second power supply wiring 3, and the gate of the sixth transistor M6 is connected to the gate of the seventh transistor M7. The source of the 7th transistor M7 is connected to the 2nd power supply wiring 3, and the gate of the 7th transistor M7 is connected to the drain of the 7th transistor M7. As described above, the sixth transistor M6 and the seventh transistor M7 form a current mirror circuit. The drain of the 7th transistor M7 is connected to the drain of the 8th transistor M8. The source of the eighth transistor M8 is connected to the first power supply wiring 2. The gate of the eighth transistor M8 is connected to the gate of the ninth transistor M9. The source of the 9th transistor M9 is connected to the first power supply wiring 2, the drain of the 9th transistor M9 is connected to the constant current source 21, and the gate of the 9th transistor M9 is connected to the drain of the 9th transistor M9. .. The back gate of the ninth transistor M9 is connected to the first power supply wiring 2.

The constant current source 21 includes a transistor. The transistor of the constant current source 21 is an N-channel MOSFET. The drain of the transistor of the constant current source 21 is connected to the drain of the ninth transistor M9, the source of the transistor is connected to the second power supply wiring 3, and the gate of the transistor is commonly connected to the gate of the transistor of the reference current source 13. ing. The transistor of the constant current source 21 and the transistor of the reference current source 13 form a current mirror circuit.

In the back gate bias circuit 20, the voltage drop due to the fifth transistor M5, that is, the difference between the first power supply voltage VDD and the gate-source voltage Vgs of the fifth transistor M5 (VDD-Vgs) and the current flowing through the sixth transistor M6. Ibg determines the voltage applied to the bias terminal BIAS, that is, the voltage applied to the back gates of the first transistor M1 and the second transistor M2 (bias voltage VB).

In the operational amplifier 1 having such a configuration, it is preferable that the noise of the output signal Sout is small. The noise of the output signal Sout is determined by the input conversion noise voltage Vn ² , which is the noise input to the operational amplifier 1.

The input conversion noise voltage Vn ² of the output signal Sout is represented by the following (Equation 1).

Here, gm12 is the transconductance of the differential pair 10, that is, the transconductance of the first transistor M1 and the second transistor M2, and gm34 is the transconductance of the active load, that is, the transconductance of the third transistor M3 and the fourth transistor M4. Is. Kp and Kn are process-specific noise parameter constants, k is the Boltzmann constant, T is the absolute temperature, W is the channel width, L is the channel length, and Cox is the capacitance of the gate oxide film. , F are frequencies.

Further, the transconductance gm (gm12, gm34) is represented by the following (Equation 2).

In the above (Equation 2), Vgs is the gate-source voltage, Vth is the threshold voltage, μ is the mobility, and ID is the drain current flowing through the transistor. The mobility μ and the oxide film volume Cox are process-specific.

As can be seen from the above (Equation 1), in order to reduce the input conversion noise voltage Vn ² , at least one of the channel width W and the channel length L of the first transistor M1 to the fourth transistor M4 should be increased, and the transconductance gm34. At least one of the smaller and the larger the transistor conductance gm12 is required. Further, as can be seen from the above (Equation 2), in order to reduce the transconductance gm34, at least one of increasing the channel length L and decreasing the channel width W is required, and the transconductance gm12 is increased. For this purpose, it is necessary to increase the channel width W, decrease the channel length L, and increase the drain current ID at least one of them.

When the channel width W of the first transistor M1 and the second transistor M2 is increased, or when the channel length L of the third transistor M3 and the fourth transistor M4 is increased, the element area increases. When the element area increases, it becomes a factor of deterioration of transistor characteristics such as an increase in parasitic capacitance. On the other hand, when the channel length L of the first transistor M1 and the second transistor M2 is reduced, or when the channel width W of the third transistor M3 and the fourth transistor M4 is reduced, the threshold value is set due to the short channel effect or the narrow channel effect. The voltage fluctuates. Further, when the drain current IDs (Im1 and Im2) of the first transistor M1 and the second transistor M2 are increased, the current consumption of the operational amplifier 1 increases.

Under such circumstances, the inventors of the present application have focused on the substrate bias effect of the first transistor M1 and the second transistor M2 as a result of diligent studies.
Generally, the threshold voltage VT of the transistor considering the substrate bias effect is represented by (Equation 3).

Here, VFB is a flat band voltage, φb is a work function, γ is a substrate bias coefficient, and VSB is a source-back gate voltage.
The drain current ID in consideration of the substrate bias effect is represented by (Equation 4).

Since the result of differentiating the drain current ID with respect to the gate-source voltage Vgs is the transconductance gm of the transistor, the conductance gmb between the source and back gates is expressed in (Equation 5) and (Equation 6) from (Equation 3) and (Equation 4). Shown.

When the conductance gmb between source back gates is expressed by the transconductance gm, it becomes as shown in (Equation 7).

Generally, the drain current ID in consideration of the substrate bias effect is represented by (Equation 8).

From (Equation 8), it can be seen that when the source back gate voltage VSB is large, the substrate bias effect increases and the transconductance gm increases.
FIG. 3 is a simulation result showing the relationship between the back gate source voltage VBS and the transconductance gm12. As can be seen from FIG. 3, the backgate source voltage VBS connects the backgates of the transistors M1 and M2 to the sources of the first transistor M1 and the second transistor M2, and the backgate source voltage (hereinafter, simply “back”). The transistor conduction gm12 becomes smaller as it approaches (referred to as "gate-source voltage VBSL"). Backgate source voltage VBS backgate source voltage when the backgate of the first transistor M1 and second transistor M2 is connected to the first power supply voltage VDD (hereinafter, simply referred to as “backgate source voltage VBSH”). The transconductance gm12 becomes larger as it approaches (referred to as). Even when the backgate-source voltage VBS is larger than the backgate-source voltage VBSH, the transconductance gm12 increases as the backgate-source voltage VBS increases.

As described above, due to the increase in the transconductance gm12, the backgate bias circuit 20 first sets the bias voltage VB so as to be closer to the first power supply voltage VDD than the source potentials of the first transistor M1 and the second transistor M2. It is applied to the back gate of the transistor M1 and the second transistor M2. In other words, the backgate bias circuit 20 has a bias voltage such that the voltage is on the first power supply voltage VDD side of the intermediate voltage between the source potential of the first transistor M1 and the second transistor M2 and the first power supply voltage VDD. VB is applied to the back gates of the first transistor M1 and the second transistor M2. That is, the backgate bias circuit 20 applies a bias voltage VB to the first transistor M1 and the second transistor M2 so that the backgate source voltage VBS becomes large. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be higher than the first power supply voltage VDD. In this case, the bias voltage VB is preferably higher than the first power supply voltage VDD within a range in which the parasitic diodes of the first transistor M1 and the second transistor M2 are not turned on. That is, the bias voltage VB is preferably less than the voltage at which the parasitic diodes of the first transistor M1 and the second transistor M2 are turned on. An example of the voltage at which the parasitic diode of the first transistor M1 and the second transistor M2 is turned on is a voltage (ldap + 0.5 to 0.6) higher than the first power supply voltage VDD by 0.5 to 0.6 V. The bias voltage VB is preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within a predetermined range including the first power supply voltage VDD. More specifically, the bias voltage VB is more preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within ± 20% of the first power supply voltage VDD. As a result, the backgate-source voltage VBS becomes a voltage excluding the backgate-source voltage VBSH among the voltages within ± 20% of the backgate-source voltage VBSH.

As shown in FIG. 3, when the backgate-source voltage VBSH is 1.5V, the backgate-source voltage VBS may be 1.2V or more and 1.8V or less (excluding 1.5V). preferable. More preferably, the backgate-source voltage VBS is 1.4 V or more and 1.6 V or less (excluding 1.5 V). In the present embodiment, since the backgate bias circuit 20 shown in FIG. 2 is connected to the first power supply wiring 2, the backgate source voltage VBS is lower than the backgate source voltage VBSH. In this embodiment, the backgate source voltage VBS is 1.45V.

As a result, as shown in FIG. 4, when the back gate source voltage VBS of the present embodiment is closer to the first power supply voltage VDD (graph G1), the back gate of the first transistor M1 and the second transistor M2 is changed to the first. Compared with the case of connecting to the source of the 1-transistor M1 and the 2nd transistor M2 (graph G2), the input conversion noise voltage caused by both 1 / f noise and thermal noise becomes smaller.

Further, in the present embodiment, in order to further reduce the 1 / f noise of the output signal Sout of the operational amplifier 1, the impurity concentration in the channel region of some of the transistors of the operational amplifier 1 is set to each transistor of the operational amplifier 1. It is lower than the impurity concentration in the channel region in the other transistors. That is, the plurality of transistors of the operational amplifier 1 include a high-concentration transistor in which the impurity concentration in the channel region is the first concentration and a low-concentration transistor in which the impurity concentration in the channel region is a second concentration lower than the first concentration. Specifically, the impurity concentration in the channel region of the transistor susceptible to 1 / f noise of the output signal Sout of each transistor of the operational amplifier 1 is set to 1 / f of the output signal Sout of each transistor of the operational amplifier 1. It is lower than the impurity concentration in the channel region of the transistor, which is not easily affected by noise. That is, a low-concentration transistor is used for a transistor that is more susceptible to 1 / f noise of the output signal Sout among a plurality of transistors than a high-concentration transistor, and a high-concentration transistor is more than a plurality of low-concentration transistors. It is used for a transistor that is not easily affected by 1 / f noise of the output signal Sout among the transistors. Specifically, in the operational amplifier 1, the differential pair 10 and the current mirror circuit 12 are susceptible to the 1 / f noise of the output signal Sout, and the constant current source 11, the reference current source 13, and the back gate bias circuit 20 output. It is not easily affected by 1 / f noise of the signal Sout.

In the present embodiment, the impurity concentration in the channel region of the transistor of the differential pair 10 and the current mirror circuit 12 is larger than the impurity concentration of the channel region in the transistor of the constant current source 11, the reference current source 13, and the back gate bias circuit 20. It is low. That is, the transistors constituting the differential pair 10 and the current mirror circuit 12 are low-concentration transistors, and the transistors constituting the constant current source 11, the reference current source 13, and the backgate bias circuit 20 are high-concentration transistors. .. Specifically, the impurity concentration in the channel region of the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 is set to the constant current source 11 transistor, the reference current source 13 transistor, and the fifth transistor. It is lower than the impurity concentration in the channel region of M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9. That is, the transistors M1 to M4 are low-concentration transistors, the constant current source 11 transistor, the reference current source 13 transistor, and the transistors M5 to M9 are high-concentration transistors.

Further, the operational amplifier 1 realizes a high degree of integration because the transistors M1 to M9 are manufactured by the miniaturization technology of the semiconductor process. Each transistor M1 to M9 uses an STI (Shallow Trench Isolation) structure as an element separation structure.

As shown in FIG. 5A, the sixth transistor M6, which is an N-channel MOSFET, is formed on a P-type epitaxial layer 31 grown on a P-type silicon substrate 30 as a semiconductor substrate. A shallow trench 32 that separates the P-type epitaxial layer 31 into a plurality of regions is formed on the surface layer portion of the P-type epitaxial layer 31. A silicon oxide film 33 is embedded in the trench 32. The width of the trench 32 (silicon oxide film 33) is, for example, 0.22 μm. An active region separated (STI) by the trench 32 is formed in the P-type epitaxial layer 31. The active region shown in FIG. 5A is an element forming region 34 in which the sixth transistor M6 is formed. On the other hand, the region corresponding to the trench 32 is the element separation region 35. The element separation region 35 includes a P-type well layer 36 and a P-type drift layer 37. The P-shaped well layer 36 is provided so as to be adjacent to the bottom of the trench 32. The P-type drift layer 37 is provided on the silicon substrate 30 side of the P-type well layer 36 so as to be adjacent to the P-type well layer 36. As a result, more reliable element separation is achieved. Further, in the element separation region 35, a P-type embedded layer (LI) 38 is formed on the silicon substrate 30 side at intervals in the depth direction with respect to the P-type drift layer 37. The P-type embedded layer 38 is formed at the boundary between the silicon substrate 30 and the P-type epitaxial layer 31.

The device forming region 34 has a deep N-type well layer 39 (HVNW) and an N-type embedded layer (BL) 40. The N-type well layer 39 is a high withstand voltage well region and is separated by an element separation region 35. The N-type embedded layer 40 is formed in the element forming region 34 on the silicon substrate 30 side with a space in the depth direction with respect to the N-type well layer 39. The N-type embedded layer 40 is formed at the boundary between the silicon substrate 30 and the P-type epitaxial layer 31.

A P-type well layer 41 is formed on the surface layer of the N-type well layer 39 so as to be surrounded by the N-type well layer 39. The P-type well layer 41 is a region doped with P-type impurities. As the P-type impurity, for example, B (boron) or the like can be used. The P-type well layer 41 is a region doped with P-type impurities so that the concentration of P-type impurities is, for example, 1E + 17 to 1E + 18 cm ^-3 .

A gate insulating film 42 is formed on the surface of the P-type well layer 41. The gate insulating film 42 is made of, for example, a silicon oxide film. The thickness of the gate insulating film 42 is, for example, 1 to 20 nm.

A gate electrode 43 is formed on the gate insulating film 42. The gate electrode 43 is made of, for example, Si, Co, Hf, Zr, Al, Ti, Ta, Mo, or the like, and includes an alloy thereof. The thickness of the gate electrode 43 is, for example, 50 to 250 nm. Further, on the surface of the P-shaped well layer 41, a sidewall 44 is formed which surrounds the side wall of the gate electrode 43 over the entire circumference. The sidewall 44 comprises, for example, silicon oxide, silicon nitride, or a laminated structure thereof.

The P-type well layer 41 has N-type source regions 45 and N on one side (left side in FIG. 5A) and the other side (right side in FIG. 5A) including a region (channel region) facing the gate insulating film 42, respectively. A drain region 46 of the mold is formed.

In the present embodiment, the channel region of the sixth transistor M6 is arranged below the gate insulating film 42 in the P-type well layer 41 and between the source region 45 and the drain region 46. In the present embodiment, the channel region of the sixth transistor M6 includes an interface between the P-type well layer 41 and the gate insulating film 42. The impurity concentration in the channel region of the sixth transistor M6 is the same as the impurity concentration in the P-type well layer 41.

The source region 45 has a structure in which N-type impurities are double-diffused at low and high concentrations. The source region 45 has an N ^- type low-concentration source region 47 in which N-type impurities are diffused at a low concentration, and an N ⁺ -type high-concentration source region 48 in which N-type impurities are diffused at a high concentration.

The low-concentration source region 47 is a region doped with N-type impurities so that the concentration of N-type impurities is, for example, 5E + 17 to 5E + 18 cm ^-3 , and spreads in the depth direction from the surface of the P-type well layer 41. The portion is formed so as to face one side edge portion in the width direction of the gate insulating film 42. The depth of the low concentration source region 47 is, for example, 100 to 400 nm.

The high-concentration source region 48 is a region doped with N-type impurities so that the concentration of N-type impurities is, for example, 5E + 19 to 5E + 20 cm ^-3 . It is self-consistent with respect to 44. The depth of the high concentration source region 48 is, for example, 50 to 200 nm.

The drain region 46 has a structure in which the N-type impure concentration is double-diffused at a low concentration and a high concentration. The drain region 46 has an N ^- type low-concentration drain region 49 in which N-type impurities are diffused at a low concentration, and an N ⁺ -type high-concentration drain region 50 in which N-type impurities are diffused at a high concentration.

The low-concentration drain region 49 is a region doped with N-type impurities so that the concentration of N-type impurities is, for example, 5E + 17 to 5E + 18 cm ^-3 , and spreads in the depth direction from the surface of the P-type well layer 41. The portion is formed so as to face the other side edge portion in the width direction of the gate insulating film 42. The depth of the low concentration drain region 49 is, for example, the same as the depth of the low concentration source region 47.

The high-concentration drain region 50 is a region doped with N-type impurities so that the concentration of N-type impurities is, for example, 5E + 19 to 5E + 20 cm ^-3 . It is self-consistent with respect to 44. The depth of the high concentration drain region 50 is the same as the depth of the high concentration source region 48.

The first insulating layer 51 and the second insulating layer 52 as an insulating film are laminated on the silicon substrate 30 in this order.
The first insulating layer 51 has a film 53 formed on the surface of the P-type epitaxial layer 31 and the side surface of the sidewall 44, and a first interlayer insulating film 54 formed on the film 53. The film 53 is made of, for example, silicon nitride (SiN). The first interlayer insulating film 54 is made of, for example, silicon oxide (SiO ₂ ). The thickness of the film 53 is, for example, 10 to 100 nm, and the thickness of the first interlayer insulating film 54 is, for example, 300 to 500 nm.

The second insulating layer 52 is a single-layer film made of silicon oxide (SiO ₂ ). The thickness of the second insulating layer 52 is, for example, 100 to 300 nm.
A source contact hole 55 and a drain contact hole 56 that continuously penetrate the source region 45 and the drain region 46 are formed in the first insulating layer 51 and the second insulating layer 52 so as to face the source region 45 and the drain region 46.

A source contact plug 57 is embedded in the source contact hole 55. The source contact plug 57 has a W / TiN / Ti laminated structure and is in contact with the source region 45. A source wiring 58 having a laminated structure of Al / TiN / Ti, which is integrated with the source contact plug 57, is formed on the second insulating layer 52.

A drain contact plug 59 is embedded in the drain contact hole 56. The drain contact plug 59 has a W / TiN / Ti laminated structure and is in contact with the drain region 46. A drain wiring 60 having a laminated structure of Al / TiN / Ti, which is integrated with the drain contact plug 59, is formed on the second insulating layer 52. Further, a gate wiring 61 is connected to the gate electrode 43. The seventh transistor M7 has the same configuration as the sixth transistor M6.

As shown in FIG. 5B, the third transistor M3, which is an N-channel MOSFET, is formed on the surface layer portion of the P-type epitaxial layer 31 like the sixth transistor M6. In the P-type epitaxial layer 31 shown in FIG. 5B, the active region separated (STI) by the trench 32 is the device forming region 34 in which the third transistor M3 is formed. The third transistor M3 has the same structure as the sixth transistor M6 except that the back gate of the third transistor M3 is connected to the source of the third transistor M3 and the impurity concentration of the P-type well layer 62. A contact region (not shown) for applying a voltage to the back gate is formed in the N-type well layer 39 of the third transistor M3.

The P-type well layer 62 of the third transistor M3 is formed in the element forming region 34 in which the third transistor M3 is formed in the P-type epitaxial layer 31. The depth and width of the P-type well layer 62 are substantially the same as the depth and width of the P-type well layer 41 of the sixth transistor M6. On the other hand, the concentration of P-type impurities in the P-type well layer 62 is lower than the concentration of P-type impurities in the P-type well layer 41 of the sixth transistor M6. Specifically, the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6 is the P-type impurity concentration according to the scaling law (proportional reduction law). The P-type impurity concentration of the P-type well layer 62 of the third transistor M3 is lower than the P-type impurity concentration according to the scaling law. The P-type impurity concentration of the P-type well layer 62 is preferably as low as possible within a range in which the device characteristics do not excessively deviate due to the decrease in the P-type impurity concentration. In one example, the P-type impurity concentration of the P-type well layer 62 is about ½ or less of the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6. Preferably, the P-type impurity concentration of the P-type well layer 62 is about 1/10 of the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6. The concentration of P-type impurities in the P-type well layer 62 of the present embodiment is 1E + 16 to 1E + 17 cm ^-3 .

In the present embodiment, the channel region of the third transistor M3 is arranged below the gate insulating film 42 in the P-type well layer 62 and between the source region 45 and the drain region 46. In the present embodiment, the channel region of the third transistor M3 includes an interface between the P-type well layer 62 and the gate insulating film 42. The impurity concentration in the channel region of the third transistor M3 is the same as the impurity concentration in the P-type well layer 62. Further, the fourth transistor M4 has the same configuration as the third transistor M3.

As shown in FIG. 5C, the eighth transistor M8, which is a P-channel MOSFET, is formed on the surface layer portion of the P-type epitaxial layer 31 like the sixth transistor M6. In the P-type epitaxial layer 31 shown in FIG. 5C, the active region separated (STI) by the trench 32 is the device forming region 34 in which the eighth transistor M8 is formed.

The element forming region 34 has an N-type well layer 63. The N-type well layer 63 is formed so as to be surrounded by the N-type well layer 39 in the surface layer portion of the N-type well layer 39. The N-type well layer 63 is a region doped with N-type impurities. As the N-type impurity, for example, P (phosphorus) or the like can be used. The N-type well layer 63 is a region doped with N-type impurities so that the concentration of N-type impurities is, for example, 1E + 17 to 1E + 18 cm ^-3 .

Similar to the sixth transistor M6, a gate insulating film 42 is formed on the surface of the N-type well layer 63, and a gate electrode 43 is formed on the gate insulating film 42. The material and thickness of the gate insulating film 42 and the gate electrode 43 are the same as those of the gate insulating film 42 and the gate electrode 43 of the sixth transistor M6. Further, on the surface of the N-shaped well layer 63, a sidewall 44 is formed which surrounds the side wall of the gate electrode 43 over the entire circumference. The sidewall 44 is made of, for example, silicon oxide.

The N-type well layer 63 has a P-type source region 64 and P on one side (left side in FIG. 5C) and the other side (right side in FIG. 5C) including a region (channel region) facing the gate insulating film 42, respectively. A drain region 65 of the mold is formed.

In the present embodiment, the channel region of the eighth transistor M8 is arranged below the gate insulating film 42 in the N-type well layer 63 and between the source region 64 and the drain region 65. In the present embodiment, the channel region of the eighth transistor M8 includes an interface between the N-type well layer 63 and the gate insulating film 42. The impurity concentration in the channel region of the eighth transistor M8 is the same as the impurity concentration in the N-type well layer 63.

The source region 64 has a structure in which the P-type impure concentration is double-diffused at a low concentration and a high concentration. The source region 64 has a P ^- type low-concentration source region 66 in which P-type impurities are diffused at a low concentration, and a P ⁺ -type high-concentration source region 67 in which P-type impurities are diffused at a high concentration.

The low-concentration source region 66 is a region doped with P-type impurities so that the P-type impurity concentration is, for example, 5E + 17 to 5E + 18 cm ^-3 , and extends from the surface of the N-type well layer 63 in the depth direction thereof. The portion is formed so as to face one side edge portion in the width direction of the gate insulating film 42. The depth of the low concentration source region 66 is, for example, 50 to 300 nm.

The high-concentration source region 67 is a region doped with P-type impurities so that the P-type impurity concentration is, for example, 1E + 19 to 1E + 20 cm ^-3 , spreads in the depth direction from the surface of the N-type well layer 63, and is a sidewall. It is self-consistent with respect to 44. The depth of the high concentration source region 67 is, for example, 50 to 150 nm.

The drain region 65 has a structure in which the P-type impure concentration is double-diffused at a low concentration and a high concentration. The drain region 65 has a P ^- type low-concentration drain region 68 in which P-type impurities are diffused at a low concentration, and a P ⁺ -type high-concentration drain region 69 in which P-type impurities are diffused at a high concentration.

The low-concentration drain region 68 is a region doped with P-type impurities so that the P-type impurity concentration is, for example, 5E + 17 to 5E + 18 cm ^-3 , and extends from the surface of the N-type well layer 63 in the depth direction thereof. The portion is formed so as to face the other side edge portion in the width direction of the gate insulating film 42. The depth of the low concentration drain region 68 is, for example, the same as the depth of the low concentration source region 66.

The high-concentration drain region 69 is a region doped with P-type impurities so that the P-type impurity concentration is, for example, 1E + 19 to 1E + 20 cm ^-3 , spreads in the depth direction from the surface of the N-type well layer 63, and is a sidewall. It is self-consistent with respect to 44. The depth of the high concentration drain region 69 is the same as the depth of the high concentration source region 67.

The first insulating layer 51 and the second insulating layer 52 as an insulating film are laminated on the P-type epitaxial layer 31 in this order. A source contact hole 55 and a drain contact hole 56 are formed in the first insulating layer 51 and the second insulating layer 52, and a source contact plug 57 and a drain contact plug 59 are embedded in the first insulating layer 51 and the second insulating layer 52, respectively. The first insulating layer 51, the second insulating layer 52, the source contact hole 55, the drain contact hole 56, the source contact plug 57, and the drain contact plug 59 of the eighth transistor M8 are the first insulating layer 51 of the sixth transistor M6. It has the same structure as the second insulating layer 52, the source contact hole 55, the drain contact hole 56, the source contact plug 57, and the drain contact plug 59. The MOS transistor of the constant current source 11, the fifth transistor M5, and the ninth transistor M9 have the same structure as the eighth transistor M8. However, the 9th transistor M9 has an N-type well layer at a point where the back gate is connected to the source of the 9th transistor M9 (first power supply wiring 2) and a contact region for applying a voltage to the back gate. The difference is that it is provided in 39.

As shown in FIG. 5D, the first transistor M1 which is a P-channel MOSFET is formed on the surface layer portion of the P-type epitaxial layer 31 like the eighth transistor M8. The first transistor M1 has the same structure as the eighth transistor M8 except that the back gate of the first transistor M1 is connected to the back gate bias circuit 20 via the bias terminal BIAS and the impurity concentration of the N-type well layer 70. Is. Although not shown, the N-type well layer 39 is provided with a contact region for applying the bias voltage VB of the back gate bias circuit 20.

The N-type well layer 70 of the first transistor M1 is formed in the element forming region 34 in which the first transistor M1 is formed in the P-type epitaxial layer 31. The depth and width of the N-type well layer 70 are substantially the same as the depth and width of the N-type well layer 63 of the eighth transistor M8. On the other hand, the concentration of N-type impurities in the N-type well layer 70 is lower than the concentration of N-type impurities in the N-type well layer 63 of the eighth transistor M8. Specifically, the N-type impurity concentration of the N-type well layer 63 of the eighth transistor M8 is the N-type impurity concentration according to the scaling law (proportional reduction law). The concentration of N-type impurities in the N-type well layer 70 of the first transistor M1 is lower than the concentration of N-type impurities according to the scaling law. The concentration of N-type impurities in the N-type well layer 70 is preferably as low as possible within a range in which the element characteristics do not excessively deviate due to the decrease in the concentration of N-type impurities. The range in which the element characteristics do not excessively deviate is, for example, a concentration higher than the upper limit of the N-type impurity concentration at which the threshold voltage deviates and the function of the current mirror circuit 12 does not work. In one example, the concentration of N-type impurities in the N-type well layer 70 is about ½ or less of the concentration of N-type impurities in the N-type well layer 63 of the eighth transistor M8. Preferably, the N-type impurity concentration of the N-type well layer 70 is about 1/10 of the N-type impurity concentration of the N-type well layer 63 of the eighth transistor M8. The concentration of P-type impurities in the N-type well layer 70 of the present embodiment is 1E + 16 to 1E + 17 cm ^-3 .

In the present embodiment, the channel region of the first transistor M1 is arranged below the gate insulating film 42 in the N-type well layer 70 and between the source region 64 and the drain region 65. In the present embodiment, the channel region of the first transistor M1 includes an interface between the N-type well layer 70 and the gate insulating film 42. The impurity concentration in the channel region of the first transistor M1 is the same as the impurity concentration in the N-type well layer 70. Further, the second transistor M2 has the same structure as the first transistor M1.

[Transistor manufacturing method]
A method for manufacturing the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 will be described with reference to FIGS. 6A to 6M. In FIGS. 6A to 6M, for convenience of explanation, it is assumed that the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are formed so as to be adjacent to each other.

Methods for manufacturing these transistors include an epitaxial layer forming step (FIG. 6A), an isolation forming step (FIGS. 6B and 6C), a well forming step (FIGS. 6D to 6G), and a gate forming step (FIGS. 6H and 6I). It has a source / drain forming step (FIG. 6J to FIG. 6L) and a wiring step (FIG. 6M).

As shown in FIG. 6A, a P-shaped silicon substrate 30 is prepared, and a thermal oxide film 71 is formed on the surface of the silicon substrate 30 by, for example, a thermal oxidation method. Next, ion implantation for the N-type embedded layer 40 is performed on the surface of the silicon substrate 30. For example, arsenic ions are injected as N-type impurity ions. After that, a drive treatment (heat treatment) for activating the injected ions is executed. Next, ion implantation for the P-type embedded layer 38 is performed. For example, boron is injected as a P-type impurity ion.

Then, the P-type epitaxial layer 31 is grown on the silicon substrate 30. Specifically, silicon crystals are epitaxially grown while adding P-type impurities (for example, boron). The thickness of the P-type epitaxial layer 31 is, for example, about 5 μm. Due to the heat generated during this epitaxial growth, the N-type impurities and P-type impurities injected into the silicon substrate 30 diffuse into the silicon substrate 30 and the P-type epitaxial layer 31. As a result, the P-type embedded layer 38 and the N-type embedded layer 40 are formed at the boundary between the silicon substrate 30 and the P-type epitaxial layer 31.

As shown in FIG. 6B, the nitride film 72 is formed so as to cover the entire area of the thermal oxide film 71 by, for example, a CVD (Chemical Vapor Deposition) method, and the nitride film 72 is formed by, for example, photolithography and etching. And an opening 73 is selectively formed in the thermal oxide film 71 to expose the region where the trench 32 should be formed. Next, an unnecessary portion of the P-type epitaxial layer 31 is removed by etching using the nitride film 72 and the thermal oxide film 71 as masks, and the trench 32 is formed. Next, for example, a thin liner oxide film (not shown) is formed on the side surface and the bottom surface of the trench 32 by a thermal oxidation method. Next, for example, by a CVD method, an insulating film 74 (silicon oxide film) made of silicon oxide is formed so as to fill the trench 32 and cover the entire area of the nitride film 72.

Next, as shown in FIG. 6C, a silicon oxide film 33 serving as an insulator is embedded in the trench 32. As a result, the element separation region 35 for partitioning the element formation region 34 for forming the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 is formed. Then, the nitride film 72 and the thermal oxide film 71 are sequentially removed by etching.

As shown in FIG. 6D, a high withstand voltage N-type well layer 39 is provided in each of the element forming regions 34 for forming the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8. It is formed. Specifically, N-type impurity ions are injected into each of the device forming regions 34.

As shown in FIG. 6E, a P-type drift layer 37 is formed in each of the element separation regions 35. Specifically, P-type impurity ions are injected into each of the device separation regions 35. For example, boron ion is used as the P-type impurity ion. After that, an annealing treatment is performed as a heat treatment, and the injected N-type impurity ions and P-type impurity ions are activated.

As shown in FIG. 6F, a P-type well layer 41 is formed on the surface layer of the N-type well layer 39 of the element forming region 34 corresponding to the sixth transistor M6, and the element forming region 34 corresponding to the eighth transistor M8 is formed. An N-type well layer 63 is formed on the surface layer portion. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the sixth transistor M6 is the element forming region 34 of the first transistor M1, the third transistor M3, and the eighth transistor M8. It is formed so as to cover the element separation region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. That is, while the impurity ions are implanted into the region where the sixth transistor M6 is formed in the silicon substrate 30 which is a semiconductor substrate, impurities are implanted in the region where the first transistor M1, the third transistor M3, and the eighth transistor M8 are formed. By selectively implanting ions so that ions are not implanted, a channel region is formed in the region where the sixth transistor M6 is formed. For example, boron ion is used as the P-type impurity ion. Next, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the eighth transistor M8 is the element forming region 34 and the element separation of the first transistor M1, the third transistor M3, and the sixth transistor M6. It is formed to cover the region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. That is, while the impurity ion is implanted in the region where the eighth transistor M8 is formed in the silicon substrate 30, the impurity ion is not implanted in the region where the first transistor M1, the third transistor M3, and the sixth transistor M6 are formed. By selectively implanting ions in this way, a channel region is formed in the region where the eighth transistor M8 is formed. For example, arsenic ion and phosphorus ion are used as N-type impurity ions. In the present embodiment, after the P-type well layer 41 of the sixth transistor M6 is formed, the N-type well layer 63 of the eighth transistor M8 is formed, but the N-type well layer 63 of the eighth transistor M8 is formed. After being formed, the P-type well layer 41 of the sixth transistor M6 may be formed.

As shown in FIG. 6G, a P-type well layer 62 is formed on the surface layer portion of the N-type well layer 39 of the third transistor M3, and an N-type well layer is formed on the surface layer portion of the N-type well layer 39 of the first transistor M1. 70 is formed. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 is the element forming region 34 of the first transistor M1, the sixth transistor M6, and the eighth transistor M8. It is formed so as to cover the element separation region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. That is, while the impurity ions are implanted into the region where the third transistor M3 is formed in the silicon substrate 30 which is a semiconductor substrate, impurities are implanted in the region where the first transistor M1, the sixth transistor M6, and the eighth transistor M8 are formed. By selectively implanting ions so that ions are not implanted, a channel region is formed in the region where the third transistor M3 is formed. For example, boron ion is used as the P-type impurity ion. Here, ion implantation is performed so that the P-type impurity concentration of the P-type well layer 41 of the third transistor M3 is lower than the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6. For example, ion implantation is performed so that the P-type impurity concentration of the P-type well layer 62 of the third transistor M3 is about ½ or less of the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6. Preferably, ion implantation is performed so that the P-type impurity concentration of the P-type well layer 62 of the third transistor M3 is about 1/10 of the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6.

Next, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the first transistor M1 is the element forming region 34 and the element separation of the third transistor M3, the sixth transistor M6, and the eighth transistor M8. It is formed to cover the region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. That is, while the impurity ions are implanted into the region where the first transistor M1 is formed in the silicon substrate 30 which is a semiconductor substrate, impurities are implanted in the region where the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are formed. By selectively implanting ions so that ions are not implanted, a channel region is formed in the region where the first transistor M1 is formed. For example, arsenic ion and phosphorus ion are used as N-type impurity ions. Here, ion implantation is performed so that the concentration of N-type impurities in the N-type well layer 70 of the first transistor M1 is lower than the concentration of N-type impurities in the N-type well layer 63 of the eighth transistor M8. For example, ion implantation is performed so that the N-type impurity concentration of the N-type well layer 70 of the first transistor M1 is about ½ or less of the N-type impurity concentration of the N-type well layer 63 of the eighth transistor M8. Preferably, ion implantation is performed so that the N-type impurity concentration of the N-type well layer 70 of the first transistor M1 is about 1/10 of the N-type impurity concentration of the N-type well layer 63 of the eighth transistor M8. In the present embodiment, after the P-type well layer 62 of the third transistor M3 is formed, the N-type well layer 70 of the first transistor M1 is formed, but the N-type well layer 70 of the first transistor M1 is formed. After being formed, the P-type well layer 62 of the third transistor M3 may be formed.

As shown in FIG. 6H, a thermal oxide film 75 is formed on the surface of each element forming region 34 of the P-type epitaxial layer 31 by, for example, a thermal oxidation method. Next, the polysilicon film 76 is formed so as to cover the thermal oxide film 75 and the silicon oxide film 33.

As shown in FIG. 6I, for example, by photolithography and etching, the element forming region 34 of the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 has a thermal oxide film 75 and a polysilicon film. Unnecessary portions of 76 are removed to form a gate insulating film 42 and a gate electrode 43 patterned in a predetermined shape. Then, for example, a nitride film / oxide film laminated film (not shown) is formed on the P-type epitaxial layer 31 by a CVD method, and then selectively etched to form a sidewall 44 on the side surface of each gate electrode 43. To.

As shown in FIG. 6J, a low concentration source region 47 and a low concentration drain region 49 are formed in the element forming region 34 of the third transistor M3 and the sixth transistor M6, and the element forming region of the first transistor M1 and the eighth transistor M8 is formed. A low-concentration source region 66 and a low-concentration drain region 68 are formed in 34. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 and the sixth transistor M6 is the element forming region 34 and the element of the first transistor M1 and the eighth transistor M8. It is formed so as to cover the separation region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 of the first transistor M1 and the eighth transistor M8 is the third transistor M3 and the sixth transistor M6. It is formed so as to cover the element forming region 34 and the element separating region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. For example, BF ₂ ion is used as the P-type impurity ion. In the present embodiment, after the low-concentration source region 47 and the low-concentration drain region 49 are formed, the low-concentration source region 66 and the low-concentration drain region 68 are formed, but the low-concentration source region 66 and the low-concentration drain are formed. After the region 68 is formed, the low concentration source region 47 and the low concentration drain region 49 may be formed.

As shown in FIG. 6K, the high-concentration source region 48 and the high-concentration drain region 50 are formed in the element forming region 34 of the third transistor M3 and the sixth transistor M6, and the element forming region of the first transistor M1 and the eighth transistor M8 is formed. A high-concentration source region 67 and a high-concentration drain region 69 are formed in 34. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 and the sixth transistor M6 is the element forming region 34 and the element of the first transistor M1 and the eighth transistor M8. It is formed so as to cover the separation region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. For example, arsenic ion is used as the N-type impurity ion. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 of the first transistor M1 and the eighth transistor M8 is the third transistor M3 and the sixth transistor M6. It is formed so as to cover the element forming region 34 and the element separating region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. For example, boron ion is used as the P-type impurity ion. In the present embodiment, after the high-concentration source region 48 and the high-concentration drain region 50 are formed, the high-concentration source region 67 and the high-concentration drain region 69 are formed, but the high-concentration source region 67 and the high-concentration drain are formed. After the region 69 is formed, the high concentration source region 48 and the high concentration drain region 50 may be formed.

As shown in FIG. 6L, a silicide layer 77 is formed on the surfaces of the high-concentration source region 48, the high-concentration drain region 50, and the gate electrode 43 formed in the element forming region 34 of the third transistor M3 and the sixth transistor M6. To. Further, a silicide layer 77 is formed on the surfaces of the high-concentration source region 67, the high-concentration drain region 69, and the gate electrode 43 formed in the element forming region 34 of the first transistor M1 and the eighth transistor M8. Specifically, after a cobalt film (not shown) is formed in the direction of the P-type epitaxial layer 31 by, for example, the PVD method, heat treatment is performed. As a result, the cobalt film of the high-concentration source regions 48 and 67, the high-concentration drain regions 50 and 69, and the gate electrode 43 in each element forming region 34 changes to the silicide layer 77, while the silicon oxide film in each element separation region 35. The cobalt film on 33 remains cobalt. Then, for example, cobalt on each silicon oxide film 33 is selectively removed by chemical treatment.

As shown in FIG. 6M, the first insulating layer 51, the second insulating layer 52, the source wiring 58, and the drain wiring 60 are formed. Specifically, for example, a nitride film and an oxide film are continuously laminated on the P-type epitaxial layer 31 by a CVD method to form a film 53 and a first interlayer insulating film 54. Then, for example, the first interlayer insulating film 54 is polished by CMP treatment. Next, the second insulating layer 52 as a silicon oxide film is formed so as to be laminated on the first interlayer insulating film 54. Next, in each element forming region 34 by photolithography and etching, a source contact hole 55 and a drain contact hole 56 are formed in the second insulating layer 52 and the first insulating layer 51, and the source contact plug 57 and the drain contact plug 59 are formed. , Ti / TiN / Al, which is the material of the source wiring 58 and the drain wiring 60, is deposited on the second insulating layer 52. Then, the Ti / TiN / Al laminated film is patterned by photolithography and etching to form the source contact plug 57, the drain contact plug 59, the source wiring 58, and the drain wiring 60. Further, a gate wiring 61 (not shown in FIG. 6M) is formed. As described above, the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are manufactured.

The second transistor M2 is manufactured in the same manner as the first transistor M1, and the fourth transistor M4 is manufactured in the same manner as the third transistor M3. Further, the 7th transistor M7 is manufactured in the same manner as the 6th transistor M6, and the 5th transistor M5, the 9th transistor M9, the transistor of the constant current source 11 and the transistor of the reference current source 13 are manufactured in the same manner as the 8th transistor M8. Will be done. Further, the first transistor M1 and the second transistor M2 are formed at the same time, and the third transistor M3 and the fourth transistor M4 are formed at the same time. Further, the fifth transistor M5, the eighth transistor M8, the ninth transistor M9, the transistor of the constant current source 11, and the transistor of the reference current source 13 are formed at the same time.

The relationship between the impurity concentration of the transistor of the operational amplifier 1 of the present embodiment and the noise of the output signal Sout will be described with reference to FIGS. 7A, 7B, and 8. 7A and 7B are diagrams schematically showing the atomic arrangement at the interface between the gate electrode 43 and the channel region, and FIG. 7A shows an example of the movement of electrons when the impurity concentration in the channel region is low. , FIG. 7B shows an example of electron movement when the impurity concentration in the channel region is high. In other words, FIG. 7B shows an example of the movement of electrons in the channel region of a high-concentration transistor in which the impurity concentration in the channel region is the first concentration, and FIG. 7A shows an example in which the impurity concentration in the channel region is lower than the first concentration. An example of the movement of electrons in the channel region of a low-concentration transistor having two concentrations is shown. The shaded circles in FIGS. 7A and 7B are impurities.

Transistors have been miniaturized in order to improve the logic integration of differential circuits. For example, the size of the minimum dimension of each transistor M1 to M9 is preferably 0.05 to 10 μm, and in this embodiment, for example, 0.13 μm. With the miniaturization of such transistors, 1 / f noise (flicker noise) of the output signal of the differential circuit may increase.

The inventors of the present application have focused on the fact that the 1 / f noise of the output signal is caused by the fluctuation of the drain current, and the fluctuation of the drain current is caused by the fluctuation of the mobility of the transistor. In addition, we focused on the impurity concentration in the channel region as one of the causes of the fluctuation of the mobility.

More specifically, as shown in FIGS. 7A and 7B, the electrons move while being scattered with impurities, so that the electron movement locus (arrow in FIG. 7B) when the impurity concentration in the channel region is high is the channel. It is more complicated than the electron movement locus (arrow in FIG. 7A) when the impurity concentration in the region is low. Therefore, the mobility fluctuation when the impurity concentration in the channel region is high is larger than the mobility fluctuation when the impurity concentration in the channel region is low.

In particular, usually, when miniaturizing a transistor, it is assumed that the impurity concentration in the channel region is increased based on the scaling law in order to suppress the short channel effect of each transistor. Then, scattering with impurities is likely to occur, and the mobility fluctuation is likely to be large.

Therefore, the inventors of the present application set the impurity concentration in the channel region of some of the plurality of transistors constituting the differential circuit lower than the impurity concentration in the channel region of the other transistors to obtain the mobility. It was found that the fluctuation of the That is, the inventors of the present application have a high concentration transistor in which the impurity concentration in the channel region is the first concentration and a low concentration in which the impurity concentration in the channel region is a second concentration lower than the first concentration. It was found that the fluctuation of the mobility is reduced by including the concentration transistor.

Further, in the present embodiment, among the transistors constituting the operational amplifier 1, the plurality of transistors constituting the back gate bias circuit 20 which is not easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1 and the constant current source 11 The impurity concentrations of the P-type well layer 41 and the N-type well layer 63 of the transistor and the transistor of the reference current source 13 were relatively high. On the other hand, in the present embodiment, the P-type well layers 62 and N-type of the first transistor M1 to the fourth transistor M4, which are easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1 among the transistors constituting the operational amplifier 1. The impurity concentration of the well layer 70 was set to a relatively low impurity concentration without relying on the scaling law. Specifically, the impurity concentration (second concentration) of the P-type well layer 62 and the N-type well layer 70 of the first transistor M1 to the fourth transistor M4 is set to the fifth transistor M5 to the ninth transistor M9 and the constant current source 11. , 21 and the impurity concentration (first concentration) of the P-type well layer 41 and the N-type well layer 63 of the reference current source 13 transistor were set to about 1/10. As a result, the fluctuation of the mobility of the transistor, which is easily affected by the 1 / f noise of the output signal Sout, is reduced.

In the graph G3 of the broken line in FIG. 8, the impurity concentrations of the P-type well layer 62 and the N-type well layer 70 of the first transistor M1 to the fourth transistor M4 are the fifth transistor M5 to the ninth transistor M9, the constant current source 11, The input conversion noise voltage when it is equal to the impurity concentration of the P-type well layer 41 and the N-type well layer 63 of the transistor of 21 and the transistor of the reference current source 13 is shown. In the graph G4 of the one-point chain line of FIG. 8, the impurity concentrations of the P-type well layer 62 and the N-type well layer 70 of the first transistor M1 to the fourth transistor M4 are the fifth transistor M5 to the ninth transistor M9, and the constant current source. The input conversion noise voltage in the case of about 1/2 of the impurity concentration of the P-type well layer 41 and the N-type well layer 63 of the transistors 11 and 21 and the transistor of the reference current source 13 is shown. In the solid line graph G5 of FIG. 8, the impurity concentrations of the P-type well layer 62 and the N-type well layer 70 of the first transistor M1 to the fourth transistor M4 are the fifth transistor M5 to the ninth transistor M9, the constant current source 11, The input conversion noise voltage in the case of about 1/10 of the impurity concentration of the P-type well layer 41 and the N-type well layer 63 of the transistor of 21 and the transistor of the reference current source 13 is shown. As can be seen from the graphs G3 to G5 of FIG. 8, as the impurity concentration of the P-type well layer 62 and the N-type well layer 70 of the first transistor M1 to the fourth transistor M4 decreases, the input conversion noise voltage, that is, the output signal Sout 1 / F Noise is reduced.

According to this embodiment, the following effects can be obtained.
(1-1) The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 (the backgate in the N-type well layer 39 of the first transistor M1 and the second transistor M2). A bias voltage VB closer to the first power supply voltage VDD than the source potential of the first transistor M1 and the second transistor M2 is applied to the contact region). As a result, the backgate-source voltage VBS of the first transistor M1 and the second transistor M2 becomes large. As a result, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, so that the output signal Sout of the operational amplifier 1 does not increase the channel length L or the channel width W, that is, without increasing the element area. Noise can be reduced.

In particular, although the backgate bias circuit 20 of the present embodiment is connected to the first power supply wiring 2, the bias voltage VB is slightly lower than the first power supply voltage VDD by the fifth transistor M5. Therefore, it is possible to suppress the noise of the first power supply wiring 2 from affecting the bias voltage VB. Therefore, the noise of the output signal Sout of the operational amplifier 1 can be reduced as compared with the configuration in which the back gates of the first transistor M1 and the second transistor M2 are directly connected to the first power supply wiring 2.

(1-2) In the back gate bias circuit 20, by making the bias voltage VB larger than the first power supply voltage VDD, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes larger, so that the operational amplifier 1 The noise of the output signal Sout can be further reduced.

(1-3) By setting the bias voltage VB to a voltage lower than the voltage at which the parasitic diodes of the first transistor M1 and the second transistor M2 are turned on, the first transistor M1 and the second transistor M2 can operate stably.

(1-4) By setting the bias voltage VB to a voltage other than the same voltage as the first power supply voltage VDD within a predetermined range including the first power supply voltage VDD, the backgate-source voltage VBS becomes large. Therefore, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, and the first transistor M1 and the second transistor M2 can operate stably. In particular, by setting the bias voltage VB to a voltage other than the voltage within ± 20% of the first power supply voltage VDD, which is the same as the first power supply voltage VDD, the backgate source voltage VBS becomes the backgate source. Since the inter-voltage voltage is near VBSH, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, and the first transistor M1 and the second transistor M2 can operate more stably.

(1-5) The impurity concentration of the P-type well layer 62 of the first transistor M1 and the second transistor M2 constituting the differential pair 10 of the operational amplifier 1 constitutes the backgate bias circuit 20, the sixth transistor M6 and the seventh transistor. It is lower than the P-type well layer 41 of M7. According to this configuration, the operational amplifier 1 moves by lowering the impurity concentration of the P-type well layer 62 of each of the transistors M1 and M2 constituting the differential pair 10 which is easily affected by the 1 / f noise of the output signal Sout. Fluctuations in degrees can be suppressed, and fluctuations in drain current can be suppressed. Therefore, the 1 / f noise of the operational amplifier 1 can be effectively reduced.

On the other hand, a stable threshold voltage is required for the plurality of transistors M5 to M9 and the transistors of the constant current source 21 included in the back gate bias circuit 20. If a low-concentration transistor such as each transistor M1 or M2 is used for a transistor that requires such a stable threshold voltage, the operation of the backgate bias circuit 20 may become unstable. There is.

Therefore, the impurity concentration of the N-type well layer 63 of the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 of the back gate bias circuit 20 of the present embodiment, and the P-type well of the sixth transistor M6 and the seventh transistor M7. By relatively increasing the impurity concentration of the layer 41, fluctuations in the threshold voltage of each of the transistors M5 to M9 can be suppressed. Thereby, the operation of the back gate bias circuit 20 can be stabilized.

As described above, in the operational amplifier 1, both low-concentration transistors such as the transistors M1 and M2 and high-concentration transistors such as the transistors M5 to M9 and the constant current source 21 are present. Therefore, it is possible to stabilize the operation of the operational amplifier 1 while effectively reducing the 1 / f noise.

(1-6) The fifth transistor M5 , the eighth transistor M8, in which the impurity concentration in the channel region of the fourth transistor M4 and the third transistor M3 constituting the current mirror circuit 12 of the operational amplifier 1 constitutes the backgate bias circuit 20. And lower than the impurity concentration in the channel region of the ninth transistor M9. According to this configuration, the mobility is increased by lowering the impurity concentration in the channel region of each of the transistors M4 and M3 constituting the current mirror circuit 12 which is easily affected by the 1 / f noise of the output signal Sout in the operational amplifier 1. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, the 1 / f noise of the operational amplifier 1 can be effectively reduced.

(1-7) The transistor of the constant current source 11, the transistor of the reference current source 13, and the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 constituting the back gate bias circuit 20 are of the same conductive type. MOSFET (P channel MOSFET), N-type well layer 63 of the transistor of the constant current source 11, N-type well layer 63 of the transistor of the reference current source 13, and N-type well layer of each transistor M5, M8, M9. 63 is the same impurity concentration. According to this configuration, a step of forming the N-type well layer 63 of the transistor of the constant current source 11, a step of forming the N-type well layer 63 of the transistor of the reference current source 13, and a step of forming the N-type well layer 63 of each transistor M5, M8, M9. Since the step of forming the N-type well layer 63 can be performed collectively, the step of manufacturing the operational amplifier 1 can be simplified.

(1-8) The P-type well layer 41 of the sixth transistor M6 and the seventh transistor M7 constituting the backgate bias circuit 20 and the P-type well layer 41 of the transistor of the constant current source 21 have the same impurity concentration. Therefore, the step of forming the P-type well layer 41 of the sixth transistor M6, the step of forming the P-type well layer 41 of the seventh transistor M7, and the step of forming the P-type well layer 41 of the transistor of the constant current source 21 are formed. Since the processes can be performed collectively, the process of manufacturing the operational amplifier 1 can be simplified.

(Variation example of the first embodiment)
The operational amplifier 1 of the present embodiment can be changed as follows.
The operational amplifier 1 shown in FIG. 1 can be changed like the operational amplifier 1 shown in FIG. The operational amplifier 1 in FIG. 9 is mainly different in the conductive type of each transistor constituting the operational amplifier 1.

The first transistor M1 and the second transistor M2 of the differential pair 10 and the transistor of the constant current source 11 are N-channel MOSFETs. The source of the transistor of the constant current source 11 is connected to the second power supply wiring 3, and the drain of the transistor of the constant current source 11 is connected to the source of the first transistor M1 and the second transistor M2.

The third transistor M 3 and the fourth transistor M 4 of the current mirror circuit 12 are P-channel MOSFETs. The sources of the third transistor M 3 and the fourth transistor M 4 are connected to the first power supply wiring 2, the drain of the third transistor M 3 is connected to the drain of the first transistor M 1, and the drain of the fourth transistor M 4 is connected. Is connected to the drain of the second transistor M2.

The backgate bias circuit 20 is connected to the common backgate of the first transistor M1 and the second transistor M2 and the second power supply wiring 3. The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 so that the bias voltage VB is closer to the second power supply voltage VSS than the source potential of the first transistor M1 and the second transistor M2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the source potential of the first transistor M1 and the second transistor M2 is a voltage on the second power supply voltage VSS side of the intermediate voltage between the second power supply voltage VSS. VB is applied to the back gates of the first transistor M1 and the second transistor M2. That is, the backgate bias circuit 20 applies a bias voltage VB so that the backgate-source voltage VBS becomes large to the backgate of the first transistor M1 and the second transistor M2. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be lower than the second power supply voltage VSS. In this case, the bias voltage VB is preferably lower than the second power supply voltage VSS within a range in which the parasitic diodes of the first transistor M1 and the second transistor M2 do not turn on. The bias voltage VB is preferably a voltage excluding the voltage within a predetermined range including the second power supply voltage VSS, which is the same as the second power supply voltage VSS. In one example, the bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS among the voltages within ± 20% of the second power supply voltage VSS. According to this configuration, since the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, the noise of the output signal Sout of the operational amplifier 1 can be reduced.

Further, in the operational capacitor 1 of FIG. 9, similarly to the operational capacitor 1 of FIG. 1, the impurity concentrations of the P-type well layer 62 and the N-type well layer 70 of the first transistor M1 to the fourth transistor M4 are set to the constant current source 11. It is lower than the impurity concentration of the P-type well layer 41 and the N-type well layer 63 of the transistor, the transistor of the reference current source 13, and the transistors M5 to M9 of the back gate bias circuit 20 and the transistor of the constant current source 21. As a result, the same effect as that of the operational amplifier 1 of FIG. 1 (1-5) to (1-8) can be obtained in the operational amplifier 1 of FIG.

(Second Embodiment)
The operational amplifier 1 of the second embodiment will be described with reference to FIGS. 1 and 10A to 12B. The operational amplifier 1 of the present embodiment has a different transistor structure for reducing 1 / f noise of the output signal Sout of the operational amplifier 1 than the operational amplifier 1 of the first embodiment.

As shown in FIG. 10A, the third transistor M3 of the present embodiment is the third transistor M3 except that the back gate of the third transistor M3 is connected to the source of the third transistor M3 and the third transistor M3 is changed to the embedded channel type. It has the same structure as the sixth transistor M6 (see FIG. 5A) of the first embodiment. That is, the P-type impurity concentration of the P-type well layer 78 in the third transistor M3 of the present embodiment is different from the P-type impurity concentration of the P-type well layer 62 (see FIG. 5B) in the third transistor M3 of the first embodiment. , The P-type impurity concentration of the P-type well layer 41 (see FIG. 5A) of the sixth transistor M6 is the same. Further, a contact region (not shown) for applying a voltage to the back gate is formed in the N-type well layer 39 of the third transistor M3.

An embedded channel layer 79 is formed in a region (channel region) of the P-type well layer 78 facing the gate insulating film 42. The embedded channel layer 79 is the same conductive region (layer) as the source region 45 and the drain region 46. That is, the embedded channel layer 79 is the same N-type region (layer) as the source region 45 and the drain region 46 doped with N-type impurities. The embedded channel layer 79 is formed inside the P-shaped well layer 78. Specifically, the embedded channel layer 79 is formed at a position downwardly separated from the interface between the P-shaped well layer 78 and the gate insulating film 42.

As described above, in the present embodiment, the channel region (embedded channel layer 79) of the third transistor M3 is below the gate insulating film 42 in the P-type well layer 78 and between the source region 45 and the drain region 46. Have been placed. In the present embodiment, the channel region (embedded channel layer 79) of the third transistor M3 does not include the interface between the P-type well layer 78 and the gate insulating film 42. The total impurity concentration in the channel region (embedded channel layer 79) of the third transistor M3 is higher than the impurity concentration in the P-type well layer 78. Further, the fourth transistor M4 has the same configuration as the third transistor M3.

As shown in FIG. 10B, the first transistor M1 is changed to an embedded channel type except that the back gate of the first transistor M1 is connected to the back gate bias circuit 20 via the bias terminal BIAS. It has the same structure as the eighth transistor M8 (see FIG. 5C). That is, the N-type impurity concentration of the N-type well layer 80 in the first transistor M1 of the present embodiment is different from the N-type impurity concentration of the N-type well layer 70 (see FIG. 5D) in the first transistor M1 of the first embodiment. , The same as the N-type impurity concentration of the N-type well layer 63 (see FIG. 5C) of the eighth transistor M8. Although not shown, the N-type well layer 39 is provided with a contact region for applying the bias voltage VB of the back gate bias circuit 20.

An embedded channel layer 81 is formed in a region (channel region) facing the gate insulating film 42 in the N-type well layer 80. The embedded channel layer 81 is the same conductive region (layer) as the source region 64 and the drain region 65. That is, the embedded channel layer 81 is the same P-type region (layer) as the source region 64 and the drain region 65 doped with P-type impurities. The embedded channel layer 81 is formed inside the N-shaped well layer 80. Specifically, the embedded channel layer 81 is formed at a position downwardly separated from the interface between the N-type well layer 80 and the gate insulating film 42.

As described above, in the present embodiment, the channel region (embedded channel layer 81) of the first transistor M1 is below the gate insulating film 42 in the N-type well layer 80 and between the source region 64 and the drain region 65. Have been placed. In the present embodiment, the channel region (embedded channel layer 81) of the first transistor M1 does not include the interface between the N-type well layer 80 and the gate insulating film 42. The total impurity concentration in the channel region (embedded channel layer 81) of the first transistor M1 is higher than the impurity concentration in the N-type well layer 80. Further, the second transistor M2 has the same configuration as the first transistor M1.

[Transistor manufacturing method]
A method for manufacturing the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 will be described with reference to FIGS. 11A and 11B. In FIGS. 11A and 11B, for convenience of explanation, it is assumed that the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are formed so as to be adjacent to each other. The method for manufacturing a transistor of the present embodiment is different from the method for manufacturing a transistor of the first embodiment in a well forming step. In the following description, the well forming step will be mainly described.

In the well forming step, a step of forming a high withstand voltage N-type well layer 39 in the element forming region 34 of the P-type epitaxial layer 31 and a step of forming a P-type drift layer 37 in the element separation region 35 of the P-type epitaxial layer 31. Is the same as in the first embodiment.

As shown in FIG. 11A, a P-type well layer 78 is formed on the surface layer portion of the N-type well layer 39 of the third transistor M3, and a P-type well layer is formed on the surface layer portion of the N-type well layer 39 of the sixth transistor M6. 41 is formed. The N-type well layer 80 is formed on the surface layer portion of the N-type well layer 39 of the first transistor M1, and the N-type well layer 63 is formed on the surface layer portion of the N-type well layer 39 of the eighth transistor M8. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 and the sixth transistor M6 is the element forming region 34 and the element of the first transistor M1 and the eighth transistor M8. It is formed so as to cover the separation region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. For example, boron ion is used as the P-type impurity ion. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 of the first transistor M1 and the eighth transistor M8 is the third transistor M3 and the sixth transistor M6. It is formed so as to cover the element forming region 34 and the element separating region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. For example, arsenic ion and phosphorus ion are used as N-type impurity ions. As described above, the P-type impurity concentration of the P-type well layer 78 of the third transistor M3 and the impurity concentration of the P-type well layer 41 of the sixth transistor M6 are equal to each other, and the impurities of the N-type well layer 80 of the first transistor M1 are equal to each other. The concentration and the impurity concentration of the N-type well layer 63 of the eighth transistor M8 are equal to each other.

In this embodiment, after the P-type well layer 78 of the third transistor M3 and the P-type well layer 41 of the sixth transistor M6 are formed, the N-type well layer 80 of the first transistor M1 and the eighth transistor M8 are formed. The N-type well layer 63 is formed, but the present invention is not limited to this, and after the N-type well layer 80 of the first transistor M1 and the N-type well layer 63 of the eighth transistor M8 are formed, the P-type of the third transistor M3 is formed. The well layer 78 and the P-type well layer 41 of the sixth transistor M6 may be formed.

As shown in FIG. 11B, an embedded channel layer 79 is formed in the P-type well layer 78 of the third transistor M3, and an embedded channel layer 81 is formed in the N-type well layer 80 of the first transistor M1. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 is the element forming region 34 of the first transistor M1, the sixth transistor M6, and the eighth transistor M8. It is formed so as to cover the element separation region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. For example, phosphorus ions are used as N-type impurity ions. As a result, the embedded channel layer 79 is formed. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 of the first transistor M1 is a third transistor M3, a sixth transistor M6, and an eighth transistor M8. It is formed so as to cover the element forming region 34 and the element separating region 35 of the above. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. For example, BF ₂ is used as a P-type impurity ion. As a result, the embedded channel layer 81 is formed. After that, the ion implantation mask is removed. Then, as in the first embodiment, the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are manufactured through the gate forming step, the source / drain forming step, and the wiring step.

In the present embodiment, after the embedded channel layer 79 of the third transistor M3 is formed, the embedded channel layer 81 of the first transistor M1 is formed, but the present invention is not limited to this, and the embedded channel layer of the first transistor M1 is formed. After the 81 is formed, the embedded channel layer 79 of the third transistor M3 may be formed.

Further, the second transistor M2 is manufactured in the same manner as the first transistor M1, and the fourth transistor M4 is manufactured in the same manner as the third transistor M3. The seventh transistor M7 is manufactured in the same manner as the sixth transistor M6, and the fifth transistor M5, the ninth transistor M9, the transistors constituting the constant current sources 11 and 21, and the transistor constituting the reference current source 13 are the eighth. It is manufactured in the same manner as the transistor M8. Further, the first transistor M1 and the second transistor M2 are formed at the same time, and the third transistor M3 and the fourth transistor M4 are formed at the same time. Further, the sixth transistor M6 and the seventh transistor M7 are formed at the same time, and form a fifth transistor M5, an eighth transistor M8, a ninth transistor M9, a transistor constituting a constant current source 11 and 21, and a reference current source 13. Transistors are formed at the same time.

The operation of this embodiment will be described with reference to FIGS. 12A and 12B. The shaded circles in FIGS. 12A and 12B are impurities.
The inventors of the present application focused on the influence of the roughness of the interface as one of the causes of the fluctuation of the mobility of the transistor.

More specifically, as shown in FIGS. 12A and 12B, in the surface channel MOSFET, electrons move near the interface between the P-type well layer and the gate insulating film in the channel region (arrow in FIG. 12B), and the embedded channel. In the type MOSFET, electrons move in a region below the interface between the P-type well layer and the gate insulating film (arrow in FIG. 12A). Here, since the interface between the P-type well layer and the gate insulating film is uneven as shown by the broken line in FIG. 12B, electrons are scattered and moved in the surface-type channel-type MOSFET. It is also susceptible to traps and detraps due to defect levels at the interface between the P-type well layer and the gate insulating film. On the other hand, in the embedded channel type MOSFET, since the electrons move in the region away from the interface between the P-type well layer and the gate insulating film in the channel region, the influence of the interface is less likely to occur when the electrons move. Therefore, the mobility fluctuation of the embedded channel MOSFET is smaller than the mobility fluctuation of the surface channel MOSFET.

Therefore, the inventors of the present application use embedded channel MOSFETs for some of the plurality of transistors constituting the operational amplifier 1 and surface channel MOSFETs for the other transistors, thereby fluctuating the mobility. Was found to be smaller. More specifically, among the plurality of transistors constituting the operational amplifier 1, an embedded channel MOSFET is used in the transistor that is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1, and the output signal Sout 1 of the operational amplifier 1 is used. A surface channel type MOSFET was used for the transistor that is not easily affected by / f noise.

In the present embodiment, the transistor of the constant current source 11 which is not easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1 among the transistors constituting the operational amplifier 1, the transistor of the reference current source 13, and the back gate bias circuit. Surface channel type MOSFETs are used for the plurality of transistors M5 to M9 of 20 and the transistors of the constant current source 21. Further, an embedded channel MOSFET is used in the first transistor M1 to the fourth transistor M4 which are easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1 among the transistors constituting the operational amplifier 1. As a result, the fluctuation of the mobility of the transistor, which is easily affected by the 1 / f noise of the output signal Sout, is reduced, so that the 1 / f noise of the output signal Sout can be reduced.

(Modified example of the second embodiment)
The operational amplifier 1 of the present embodiment can be changed as follows.
-The operational amplifier 1 of this embodiment can also be applied to the operational amplifier 1 of FIG. That is, among the transistors constituting the operational amplifier 1 of FIG. 9, the transistor of the constant current source 11 which is not easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1, the transistor of the reference current source 13, and the backgate bias circuit 20. Surface channel type MOSFETs are used for the plurality of transistors M5 to M9 and the transistors of the constant current source 21. Further, an embedded channel MOSFET is used in the first transistor M1 to the fourth transistor M4 which are easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1 among the transistors constituting the operational amplifier 1.

(Third Embodiment)
The operational amplifier 1 of the third embodiment will be described with reference to FIGS. 1 and 13A to 14C. The operational amplifier 1 of the present embodiment is different from the operational amplifier 1 of the first embodiment in the structure of the transistor devised to reduce the 1 / f noise of the output signal Sout of the operational amplifier 1.

As shown in FIG. 13A, the third transistor M3 of the present embodiment is a combination of the third transistor M3 of the first embodiment and the third transistor M3 of the second embodiment. That is, the third transistor M3 of the present embodiment has an impurity concentration in the channel region lower than the impurity concentration in the channel region (P-type well layer 41: see FIG. 5A) of the sixth transistor M6, and is an embedded channel type MOSFET. has been edited. The back gate of the third transistor M3 is connected to the source of the third transistor M3 (second power supply wiring 3). Other than them, it has the same structure as the sixth transistor M6.

The impurity concentration of the P-type well layer 82 forming the channel region of the third transistor M3 is lower than the impurity concentration of the channel region according to the scaling law. The impurity concentration of the P-type well layer 82 is preferably as low as possible within a range in which the element characteristics do not excessively deviate due to the decrease in the impurity concentration. In one example, the impurity concentration of the P-type well layer 82 is about ½ or less of the P-type impurity concentration of the P-type well layer 41 of the sixth transistor M6. Preferably, the impurity concentration of the P-type well layer 82 is about 1/10 of the impurity concentration of the P-type well layer 41 of the sixth transistor M6.

An embedded channel layer 83 is formed in a region (channel region) of the P-type well layer 82 facing the gate insulating film 42. The embedded channel layer 83 is the same conductive region (layer) as the source region 45 and the drain region 46. That is, the embedded channel layer 83 is the same N-type region (layer) as the source region 45 and the drain region 46 doped with N-type impurities.

As described above, in the present embodiment, the channel region (embedded channel layer 83) of the third transistor M3 is below the gate insulating film 42 in the P-type well layer 82 and is between the source region 45 and the drain region 46. Have been placed. In the present embodiment, the channel region (embedded channel layer 83) of the third transistor M3 does not include the interface between the P-type well layer 82 and the gate insulating film 42. The impurity concentration in the channel region (embedded channel layer 83) of the third transistor M3 is higher than the impurity concentration in the P-type well layer 82. Further, the fourth transistor M4 has the same configuration as the third transistor M3.

As shown in FIG. 13B, the first transistor M1 of the present embodiment is a combination of the first transistor M1 of the first embodiment and the first transistor M1 of the second embodiment. That is, the first transistor M1 of the present embodiment has an impurity concentration in the channel region lower than the impurity concentration in the channel region (N-type well layer 63: see FIG. 5C) of the eighth transistor M8, and is changed to an embedded channel type. ing. Further, the back gate of the first transistor M1 is connected to the back gate bias circuit 20 via the bias terminal BIAS. Other than them, it has the same structure as the eighth transistor M8.

The impurity concentration of the N-type well layer 84 of the first transistor M1 is lower than the N-type impurity concentration according to the scaling law. The impurity concentration of the N-type well layer 84 is preferably as low as possible within a range in which the element characteristics do not excessively deviate due to the decrease in the impurity concentration. The range in which the element characteristics do not excessively deviate is, for example, a concentration higher than the upper limit of the impurity concentration at which the threshold voltage deviates and the function of the current mirror circuit 12 (see FIG. 1) does not work. In one example, the impurity concentration of the N-type well layer 84 is about ½ or less of the impurity concentration of the N-type well layer 63 of the eighth transistor M8. Preferably, the impurity concentration of the N-type well layer 84 is about 1/10 of the impurity concentration of the N-type well layer 63 of the eighth transistor M8.

An embedded channel layer 85 is formed in a region (channel region) of the N-type well layer 84 facing the gate insulating film 42. The embedded channel layer 85 is the same conductive region (layer) as the source region 64 and the drain region 65. That is, the embedded channel layer 85 is the same P-type region (layer) as the source region 64 and the drain region 65 doped with P-type impurities.

As described above, in the present embodiment, the channel region (embedded channel layer 85) of the first transistor M1 is below the gate insulating film 42 in the N-type well layer 84 and is between the source region 64 and the drain region 65. Have been placed. In the present embodiment, the channel region (embedded channel layer 85) of the first transistor M1 does not include the interface between the N-type well layer 84 and the gate insulating film 42. The impurity concentration in the channel region (embedded channel layer 85) of the first transistor M1 is higher than the impurity concentration in the N-type well layer 84. Further, the second transistor M2 has the same configuration as the first transistor M1.

As described above, in the operational amplifier 1 of the present embodiment, the transistors M1 and M2 of the differential pair 10 and the transistors M3 and M4 of the current mirror circuit 12 which is an active load are embedded channel type MOSFETs thereof. The impurity concentration in the channel region is lower than the impurity concentration in the channel region in the transistor of the constant current source 11, the transistor of the reference current source 13, and the transistors M5 to M9 of the back gate bias circuit 20 and the transistors of the constant current source 21. .. On the other hand, the plurality of transistors M5 to M9 of the back gate bias circuit 20 and the transistors of the constant current source 21 are surface channel type MOSFETs.

[Transistor manufacturing method]
A method for manufacturing the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 will be described with reference to FIGS. 14A to 14C. In FIGS. 14A to 14C, for convenience of explanation, it is assumed that the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are formed so as to be adjacent to each other. The method for manufacturing a transistor of the present embodiment is different from the method for manufacturing a transistor of the first embodiment in a well forming step. In the following description, the well forming step will be mainly described.

In the well forming step, a step of forming a high withstand voltage N-type well layer 39 in each of the element forming regions 34 of the P-type epitaxial layer 31 and a P-type drift layer 37 in each of the element separation regions 35 of the P-type epitaxial layer 31. The step of forming the above is the same as that of the first embodiment.

As shown in FIG. 14A, a P-type well layer 41 is formed on the surface layer portion of the N-type well layer 39 of the sixth transistor M6, and an N-type well layer 63 is formed on the surface layer portion of the eighth transistor M8. The method for forming the P-type well layer 41 and the N-type well layer 63 is the same as that in the first embodiment. Specifically, in the silicon substrate 30 which is a semiconductor substrate, while impurity ions are implanted into the region where the sixth transistor M6 is formed, the region where the first transistor M1, the third transistor M3, and the eighth transistor M8 are formed. By selectively implanting ions so that impurity ions are not implanted into the silicon, a channel region is formed in the region where the sixth transistor M6 is formed. Further, while the impurity ions are implanted in the region where the eighth transistor M8 is formed in the silicon substrate 30, the impurity ions are not implanted in the region where the first transistor M1, the third transistor M3, and the sixth transistor M6 are formed. By selectively implanting ions into the region, a channel region is formed in the region where the eighth transistor M8 is formed.

As shown in FIG. 14B, a P-type well layer 82 is formed on the surface layer portion of the N-type well layer 39 of the third transistor M3, and an N-type well layer 84 is formed on the surface layer portion of the first transistor M1. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 is the element forming region 34 of the first transistor M1, the sixth transistor M6, and the eighth transistor M8. It is formed so as to cover the element separation region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. That is, while the impurity ions are implanted into the region where the third transistor M3 is formed in the silicon substrate 30 which is a semiconductor substrate, impurities are implanted in the region where the first transistor M1, the sixth transistor M6, and the eighth transistor M8 are formed. By selectively implanting ions so that ions are not implanted, a channel region is formed in the region where the third transistor M3 is formed. For example, boron ion is used as the P-type impurity ion. Here, ion implantation is performed so that the impurity concentration of the P-type well layer 82 of the third transistor M3 is lower than the impurity concentration of the P-type well layer 41 of the sixth transistor M6. For example, ion implantation is performed so that the impurity concentration of the P-type well layer 82 of the third transistor M3 is about ½ or less of the impurity concentration of the P-type well layer 41 of the sixth transistor M6. Preferably, ion implantation is performed so that the impurity concentration of the P-type well layer 82 of the third transistor M3 is about 1/10 of the impurity concentration of the P-type well layer 41 of the sixth transistor M6.

Next, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the first transistor M1 is the element forming region 34 and the element separation of the third transistor M3, the sixth transistor M6, and the eighth transistor M8. It is formed to cover the region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. That is, while the impurity ions are implanted into the region where the first transistor M1 is formed in the silicon substrate 30 which is a semiconductor substrate, impurities are implanted in the region where the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are formed. By selectively implanting ions so that ions are not implanted, a channel region is formed in the region where the first transistor M1 is formed. For example, arsenic ion and phosphorus ion are used as N-type impurity ions. Here, ion implantation is performed so that the impurity concentration of the N-type well layer 84 of the first transistor M1 is lower than the impurity concentration of the N-type well layer 63 of the eighth transistor M8. For example, ion implantation is performed so that the impurity concentration of the N-type well layer 84 of the first transistor M1 is about ½ or less of the impurity concentration of the N-type well layer 63 of the eighth transistor M8. Preferably, ion implantation is performed so that the impurity concentration of the N-type well layer 84 of the first transistor M1 is about 1/10 of the impurity concentration of the N-type well layer 63 of the eighth transistor M8. In the present embodiment, the N-type well layer 84 is formed after the P-type well layer 82 is formed, but the P-type well layer 82 may be formed after the N-type well layer 84 is formed. good.

As shown in FIG. 14C, the embedded channel layer 83 is formed in the N-type well layer 39 of the third transistor M3, and the embedded channel layer 85 is formed in the N-type well layer 39 of the first transistor M1. Specifically, the ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 is the element forming region 34 of the first transistor M1, the sixth transistor M6, and the eighth transistor M8. It is formed so as to cover the element separation region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. For example, phosphorus ions are used as N-type impurity ions. As a result, the embedded channel layer 83 is formed. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 of the first transistor M1 is a third transistor M3, a sixth transistor M6, and an eighth transistor M8. It is formed so as to cover the element forming region 34 and the element separating region 35 of the above. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. For example, BF ₂ is used as a P-type impurity ion. As a result, the embedded channel layer 85 is formed. In the present embodiment, the embedded channel layer 85 is formed after the embedded channel layer 83 is formed, but the embedded channel layer 83 may be formed after the embedded channel layer 85 is formed.

After that, the ion implantation mask is removed. Then, as in the first embodiment, the first transistor M1, the third transistor M3, the sixth transistor M6, and the eighth transistor M8 are manufactured through the gate forming step, the source / drain forming step, and the wiring step.

The second transistor M2 is manufactured in the same manner as the first transistor M1, and the fourth transistor M4 is manufactured in the same manner as the third transistor M3. The seventh transistor M7 is manufactured in the same manner as the sixth transistor M6, and the constant current source 11 and 21 transistors, the reference current source 13 transistor, the fifth transistor M5, and the ninth transistor M9 are the same as the eighth transistor M8. Manufactured. Further, the first transistor M1 and the second transistor M2 are formed at the same time, and the third transistor M3 and the fourth transistor M4 are formed at the same time. Further, the sixth transistor M6 and the seventh transistor M7 are formed at the same time, and the constant current source 11 and 21 transistors, the reference current source 13 transistor, the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 are formed at the same time. Will be done. According to the present embodiment, the same effects as those of the first embodiment and the second embodiment can be obtained.

(Modified example of the third embodiment)
The operational amplifier 1 of the present embodiment can be changed as follows.
-The operational amplifier 1 of this embodiment can also be applied to the operational amplifier 1 of FIG. That is, among the transistors constituting the operational amplifier 1 of FIG. 9, the transistor of the constant current source 11 which is not easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1, the transistor of the reference current source 13, and the back gate bias circuit. A surface channel type MOSFET is used for each of the transistors M5 to M9 of 20 and the transistor of the constant current source 21. Further, an embedded channel MOSFET is used in the first transistor M1 to the fourth transistor M4 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1 among the transistors constituting the operational amplifier 1 in FIG. Further, the impurity concentration in the channel region in the first transistor M1 to the fourth transistor M4 in each transistor constituting the transistor in FIG. 9 is the transistor of the constant current source 11 in each transistor constituting the transistor 1 in FIG. It is lower than the impurity concentration in the channel region in the transistor of the reference current source 13 and the transistors M5 to M9 of the back gate bias circuit 20 and the transistor of the constant current source 21.

(Fourth Embodiment)
The operational amplifier 1A of the fourth embodiment will be described with reference to FIG.
The operational amplifier 1A of the present embodiment is a two-stage amplifier circuit, and includes a reference current source 13, a backgate bias circuit 20, a differential amplification stage 90, and an output stage 93. The operational amplifier 1A amplifies the potential difference between the inverting input terminal INN and the non-inverting input terminal INP, and outputs the output signal Sout from the output terminal OUT. The operational amplifier 1A is integrally integrated on one semiconductor substrate. The differential amplification stage 90 includes a differential pair 10, a constant current source 11, a cascode current mirror circuit 91, and a bias circuit 92. The differential pair 10, constant current source 11, reference current source 13, and backgate bias circuit 20 are the same as the differential pair 10, constant current source 11, reference current source 13, and backgate bias circuit 20 of the first embodiment. It has a similar configuration. In the present embodiment, the back gate bias circuit 20 is connected to the first power supply wiring 2 and the back gates of the first transistor M1 and the second transistor M2 as in the first embodiment.

The cascode current mirror circuit 91 is an active load connected to the differential pair 10. The cascode current mirror circuit 91 is configured by stacking two transistors of the same type, and includes the tenth transistor M10 to the thirteenth transistor M13. In the present embodiment, the tenth transistor M10 to the thirteenth transistor M13 are composed of N-channel MOSFETs. In particular, the tenth transistor M10 and the eleventh transistor M11 have an enhancement type structure. The tenth transistor M10 corresponds to the "fifth MOS transistor", the eleventh transistor M11 corresponds to the "sixth MOS transistor", the twelfth transistor M12 corresponds to the "seventh MOS transistor", and the thirteenth transistor. M13 corresponds to the "8th MOS transistor".

The tenth transistor M10 is provided in series with the first transistor M1. More specifically, the tenth transistor M10 is provided between the drain of the first transistor M1 and the second power supply wiring 3. The drain of the 10th transistor M10 is connected to the drain of the 1st transistor M1, and the source of the 10th transistor M10 is connected to the second power supply wiring 3. The eleventh transistor M11 is provided in series with the second transistor M2. More specifically, the eleventh transistor M11 is provided between the drain of the second transistor M2 and the second power supply wiring 3. The drain of the 11th transistor M11 is connected to the drain of the 2nd transistor M2, and the source of the 11th transistor M11 is connected to the second power supply wiring 3. The twelfth transistor M12 is vertically stacked on the tenth transistor M10, and the thirteenth transistor M13 is vertically stacked on the eleventh transistor M11. More specifically, the source of the twelfth transistor M12 is connected to the drain of the tenth transistor M10, and the source of the thirteenth transistor M13 is connected to the drain of the eleventh transistor M11. The gates of the twelfth transistor M12 and the thirteenth transistor M13 are appropriately biased by inputting the bias voltage Vbn1 from the first bias circuit (not shown). The gates of the tenth transistor M10 and the eleventh transistor M11 are connected to the drain of the twelfth transistor M12. When the first transistor M1 and the second transistor M2 are of the depletion type, the input full swing (Rail-to-Rail) can be realized by the circuit configuration shown in FIG.

The bias circuit 92 is a constant current circuit that maintains the cascode current mirror circuit 91 in an appropriate bias state. In one example, the bias circuit 92 is configured by stacking two transistors of the same type, and includes the 14th transistor M14 to the 17th transistor M17. In the present embodiment, the 14th transistor M14 to the 17th transistor M17 are composed of P-channel MOSFETs. In particular, the 14th transistor M14 and the 15th transistor M15 have an enhancement type structure.

The 14th transistor M14 and the 15th transistor M15 form a current source that generates a predetermined current. The source of the 14th transistor M14 and the source of the 15th transistor M15 are connected to the first power supply wiring 2, the gate of the 14th transistor M14 and the gate of the 15th transistor M15 are commonly connected, and the second bias circuit (not shown). )It is connected to the. The gates of the 14th transistor M14 and the 15th transistor M15 are appropriately biased by inputting the bias voltage Vbp1 from the second bias circuit. The 16th transistor M16 is vertically stacked on the 14th transistor M14, and the 17th transistor M17 is vertically stacked on the 15th transistor M15. More specifically, the source of the 16th transistor M16 is connected to the drain of the 14th transistor M14, and the source of the 17th transistor M17 is connected to the drain of the 15th transistor M15. The drain of the 16th transistor M16 is connected to the drain of the 12th transistor M12, and the drain of the 17th transistor M17 is connected to the drain of the 13th transistor M13. Further, the drain of the 17th transistor M17 is connected to the output stage 93. The gate of the 16th transistor M16 and the gate of the 17th transistor M17 are commonly connected and connected to a third bias circuit (not shown). The gates of the 16th transistor M16 and the 17th transistor M17 are appropriately biased by inputting the bias voltage Vbp2 from the third bias circuit.

The output stage 93 is connected to the output terminal OUT, inverting and amplifying the output signal Sout of the cascode current mirror circuit 91, and outputting it to the output terminal OUT. An example of the output stage 93 is a grounded-source circuit. More specifically, the output stage 93 includes two transistors connected in series between the first power supply wiring 2 and the second power supply wiring 3. The two transistors are a P-channel MOSFET and an N-channel MOSFET. A capacitor 94 for phase compensation is connected to the output stage 93.

The backgate bias circuit 20 is connected to the first power supply wiring 2 and the common backgate of the first transistor M1 and the second transistor M2 constituting the differential pair 10. The backgate bias circuit 20 of the present embodiment is the same as the backgate bias circuit 20 of the first embodiment (see FIG. 2). Therefore, the same effect as the effect of (1-1) to (1-4) of the first embodiment can be obtained.

Further, in the present embodiment, in order to further reduce the 1 / f noise of the output signal Sout of the output stage 93, the impurity concentration in the channel region of some of the transistors constituting the operational amplifier 1A is set to the operational amplifier 1A. It is lower than the impurity concentration in the channel region in the other transistors among the transistors constituting the above. That is, the plurality of transistors constituting the operational amplifier 1A include a high-concentration transistor having an impurity concentration in the channel region as the first concentration and a low-concentration transistor having an impurity concentration in the channel region having a second concentration lower than the first concentration. include. Specifically, the impurity concentration in the channel region of the transistor that is easily affected by the 1 / f noise of the output signal Sout is lower than the impurity concentration in the channel region of the transistor that is not easily affected by the 1 / f noise of the output signal Sout. is doing. That is, a low-concentration transistor is used for a transistor that is more susceptible to 1 / f noise of the output signal Sout among a plurality of transistors than a high-concentration transistor, and a high-concentration transistor is more than a plurality of low-concentration transistors. It is used for a transistor that is not easily affected by 1 / f noise of the output signal Sout among the transistors. Specifically, in the operational amplifier 1A, the portion susceptible to 1 / f noise of the output signal Sout is the differential pair 10 of the differential amplification stage 90, a part of the bias circuit 92, and the cascode current mirror circuit 91. It is a part. In the operational amplifier 1A, the parts that are not easily affected by the 1 / f noise of the output signal Sout are the constant current source 11, the reference current source 13, the back gate bias circuit 20, the other part of the bias circuit 92, and the cascode current mirror circuit 91. The other part and the output stage 93.

In the present embodiment, the impurity concentration in the channel region in the transistor of the differential pair 10, a part of the bias circuit 92, and a part of the cascode current mirror circuit 91 is set to the constant current source 11, the reference current source 13, and the back gate bias circuit. 20. It is lower than the impurity concentration in the channel region in the other part of the bias circuit 92, the other part of the cascode current mirror circuit 91, and the transistor of the output stage 93. That is, the transistors constituting the differential pair 10, a part of the bias circuit 92, and a part of the cascode current mirror circuit 91 are low-concentration transistors, and are a constant current source 11, a reference current source 13, and a backgate bias circuit 20. , The other part of the bias circuit 92, the other part of the cascode current mirror circuit 91, and the transistor constituting the output stage 93 are high-concentration transistors. Specifically, the impurity concentration in the channel region of the first transistor M1, the second transistor M2, the tenth transistor M10, the eleventh transistor M11, the fourteenth transistor M14, and the fifteenth transistor M15 is set to the constant current sources 11 and 21. Transistor, reference current source 13 transistor, 5th transistor M5, 6th transistor M6, 7th transistor M7, 8th transistor M8, 9th transistor M9, 12th transistor M12, 13th transistor M13, 16th transistor M16, 1st It is lower than the impurity concentration in the channel region of the 17-transistor M17 and the transistor of the output stage 93. That is, each transistor M1, M2, M10, M11, M14, M15 is a low concentration transistor, a constant current source 11 and 21 transistor, a reference current source 13 transistor, an output stage 93 transistor, and each transistor M5, M6. , M7, M8, M9, M12, M13, M16, M17 are high-concentration transistors.

The impurity concentration in the channel region of each transistor M1, M2, M10, M11, M14, M15 is the transistor of the constant current source 11 and 21, the transistor of the reference current source 13, the transistor of the output stage 93, and each transistor M5, M6. It is preferably about 1/2 or less of the impurity concentration in the channel region in M7, M8, M12, M13, M16, and M17. In the present embodiment, the impurity concentration in the channel region of each of the transistors M1, M2, M10, M11, M14, and M15 is the constant current source 11 and 21 transistors, the reference current source 13 transistor, the output stage 93 transistor, and each. It is about 1/10 of the impurity concentration in the channel region in the transistors M5, M6, M7, M8, M12, M13, M16, and M17. Further, the transistors of the constant current sources 11 and 21, the transistor of the reference current source 13, the transistor of the output stage 93, and the transistors M5, M6, M7, M8, M9, M12, M13, M16, and M17 are surface channel type MOSFETs. Is.

The structure and manufacturing method of the N-channel MOSFET and the P-channel MOSFET of each transistor constituting the operational amplifier 1A are the same as those of the N-channel MOSFET and the P-channel MOSFET such as the first transistor M1 of the first embodiment. be.

According to this embodiment, in addition to the effects of (1-1) to (1-4) of the first embodiment, the following effects can be obtained.
(4-1) The impurity concentration in the channel region of the tenth transistor M10 and the eleventh transistor M11 constituting the current source of the cascode current mirror circuit 91 is the sixth transistor M6 and the seventh transistor M7 constituting the backgate bias circuit 20. It is lower than the impurity concentration in the channel region of. According to this configuration, the impurity concentration in the channel region of each of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1A is lowered. Fluctuations in mobility can be suppressed, and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1A can be effectively reduced.

(4-2) The impurity concentration in the channel region of the 14th transistor M14 and the 15th transistor M15 constituting the current source of the bias circuit 92 is the fifth transistor M5, the eighth transistor M8, and the eighth transistor M8 constituting the backgate bias circuit 20. It is lower than the impurity concentration in the channel region of the ninth transistor M9. According to this configuration, by lowering the impurity concentration of the N-type well layer 70 of each of the transistors M14 and M15 constituting the current source of the bias circuit 92 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1A. , Fluctuations in mobility can be suppressed, and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1A can be effectively reduced.

(4-3) The concentration of impurities in the channel region of the first transistor M1 and the second transistor M2, which are P-channel MOSFETs constituting the differential pair 10, and the 14th P-channel MOSFET, which is a current source of the bias circuit 92. The impurity concentrations in the channel region of the transistor M14 and the 15th transistor M15 are equal to each other. According to this configuration, the step of forming the N-type well layer 70 of the transistors M14 and M15 constituting the current source of the bias circuit 92 and the N-type well layer 70 of the transistors M1 and M2 constituting the differential pair 10 Can be performed collectively with the process of forming the above. Therefore, the process of manufacturing the operational amplifier 1A can be simplified.

(4-4) The impurity concentration in the channel region of the transistor of the constant current source 11 and the channel region of the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9, which are P-channel MOSFETs constituting the backgate bias circuit 20. And the impurity concentration in the channel region of the 16th transistor M16 and the 17th transistor M17, which are P-channel MOSFETs of the bias circuit 92, are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the transistor of the constant current source 11, a step of forming the N-type well layer 63 of each transistor M5, M8, M9 of the back gate bias circuit 20, and a bias. The steps of forming the N-type well layer 63 of each of the transistors M16 and M17 of the circuit 92 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1A can be simplified.

(4-5) The impurity concentration in the channel region of the sixth transistor M6, the seventh transistor M7, and the transistor of the constant current source 21, which are N-channel MOSFETs constituting the backgate bias circuit 20, and the N of the cascode current mirror circuit 91. The impurity concentrations in the channel regions of the 12th transistor M12 and the 13th transistor M13, which are channel MOSFETs, are equal to each other. According to this configuration, the steps of forming the P-type well layer 41 of the transistors M6 and M7 of the backgate bias circuit 20 and the transistors of the constant current source 21 and the P of the transistors M12 and M13 of the cascode current mirror circuit 91. The steps of forming the mold well layer 41 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1A can be simplified.

(Modified example of the fourth embodiment)
The operational amplifier 1A of the present embodiment can be changed as follows.
The operational amplifier 1A shown in FIG. 15 can be changed like the operational amplifier 1A having the differential amplification stage 90A shown in FIG. The operational amplifier 1A of FIG. 16 is different from the operational amplifier 1A of FIG. 15 mainly in the conduction type of the channel region and the connection configuration of the back gate bias circuit 20 in each transistor constituting the operational amplifier 1A.

The first transistor M1 and the second transistor M2 of the differential pair 10, the transistor of the constant current source 11, and the transistor of the reference current source 13 are N-channel MOSFETs. The drains of the first transistor M1 and the second transistor M2 are connected to the bias circuit 92. More specifically, the drain of the first transistor M1 is connected to the drain of the fifteenth transistor M15 , and the drain of the second transistor M2 is connected to the drain of the fourteenth transistor M14 . The source of the transistor of the constant current source 11 is connected to the second power supply wiring 3, and the drain of the transistor of the constant current source 11 is connected to the source of the first transistor M1 and the second transistor M2. A bias voltage Vbn2 is input to the transistor of the constant current source 11 from the first bias circuit (not shown). The first transistor M1, the second transistor M2, the transistor of the constant current source 11, and the transistor of the reference current source 13 may have either a depletion type or an enhancement type structure. In FIG. 16, the first transistor M1, the second transistor M2, the transistor of the constant current source 11, and the transistor of the reference current source 13 have an enhancement type structure. When the first transistor M1 and the second transistor M2 are of the depletion type, the input full swing (Rail-to-Rail) can be realized by the circuit configuration shown in FIG.

The backgate bias circuit 20 is connected to a common backgate of the first transistor M1 and the second transistor M2 and to the second power supply wiring 3. The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 so that the bias voltage VB is closer to the second power supply voltage VSS than the source potential of the first transistor M1 and the second transistor M2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the source potential of the first transistor M1 and the second transistor M2 is a voltage on the second power supply voltage VSS side of the intermediate voltage between the second power supply voltage VSS. VB is applied to the back gates of the first transistor M1 and the second transistor M2. That is, the backgate bias circuit 20 applies a bias voltage VB so that the backgate-source voltage VBS becomes large to the backgate of the first transistor M1 and the second transistor M2. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB is preferably lower than the second power supply voltage VSS. The bias voltage VB is preferably a voltage excluding the voltage within a predetermined range including the second power supply voltage VSS, which is the same as the second power supply voltage VSS. In one example, the bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS among the voltages within ± 20% of the second power supply voltage VSS. According to this configuration, since the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, the noise of the output signal Sout of the operational amplifier 1 can be reduced.

Further, in the operational capacitor 1A of FIG. 16, the impurity concentrations of the P-type well layer 62 and the N-type well layer 70 of each of the transistors M1, M2, M10, M11, M14, and M15 are determined in the same manner as in the operational capacitor 1A of FIG. Transistors of current sources 11 and 21, reference current source 13 transistors, output stage 93 transistors, and P-type well layers 41 and N-type of each transistor M5, M6, M7, M8, M9, M12, M13, M16, M17. It is lower than the impurity concentration of the well layer 63. As a result, the same effect as that of the operational amplifier 1A of FIG. 15 (4-1) to (4-4) can be obtained in the operational amplifier 1A of FIG.

For each of the transistors M1, M2, M10, M11, M14, and M15 in the operational amplifier 1A shown in FIGS. 15 and 16, instead of lowering the impurity concentration in the channel region, the transistors M1 to M4 of the second embodiment. Such an embedded channel type MOSFET may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of transistors M1 and M2 constituting the differential pair 10, a set of transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each transistor M14 constituting the current source of the bias circuit 92, Any one or two sets of M15 may be changed to the embedded channel type MOSFET of the second embodiment.

In addition to reducing the impurity concentration in the channel region, an embedded channel MOSFET may be applied to each of the transistors M1, M2, M10, M11, M14, and M15 in the operational amplifier 1A shown in FIGS. 15 and 16. .. That is, the transistors M1, M2, M10, M11, M14, and M15 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1A shown in FIGS. 15 and 16, a set of transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and a bias circuit 92. One or two sets of any one or two sets of the transistors M14 and M15 constituting the current source may be changed to the same structure as the structure of the transistors M1 to M4 of the third embodiment. Further, a set of transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1A shown in FIGS. 15 and 16, a set of transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and a bias circuit 92. The structure of any one or two sets of the transistors M14 and M15 constituting the current source is the same as the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. You may change to the structure of. In short, the operational amplifier 1A shown in FIGS. 15 and 16 has a structure similar to that of the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the transistors M1 to M4 of the third embodiment. May be mixed.

(Fifth Embodiment)
The operational amplifier 1B of the fifth embodiment will be described with reference to FIG. The operational amplifier 1B of the present embodiment is different from the operational amplifier 1 of the first embodiment in that the step-down circuit 100, which is an example of the voltage conversion circuit, the output stage 93 of the fourth embodiment, and the capacitor 94 are added.

As shown in FIG. 17A, the output stage 93 is connected to the node N1 between the drain of the second transistor M2 and the drain of the fourth transistor M4. The output stage 93 is connected to the output terminal OUT, inverting and amplifying the output signal Sout of the node N1 and outputting it to the output terminal OUT. An example of the output stage 93 is a grounded-source circuit. The configuration of the output stage 93 is the same as the configuration of the output stage 93 of the fourth embodiment.

The step-down circuit 100 is provided between the first power supply wiring 2 and the differential pair 10, and more specifically between the first power supply wiring 2 and the constant current source 11. The step-down circuit 100 steps down the first power supply voltage VDD of the first power supply wiring 2 to a predetermined voltage and applies it to the constant current source 11.

As shown in FIG. 17B, the step-down circuit 100 is, for example, a series regulator type semiconductor step-down circuit. The step-down circuit 100 includes a transistor 101 and an operational amplifier 102. The transistor 101 is an N-channel MOSFET. The drain of the transistor 101 is connected to the first power supply wiring 2, and the source of the transistor 101 is connected to the constant current source 11. The gate of the transistor 101 is connected to the output terminal of the operational amplifier 102. The non-inverting input terminal of the operational amplifier 102 is connected to the source of the transistor 101 . A predetermined voltage VF lower than the first power supply voltage VDD is applied to the inverting input terminal of the operational amplifier 102. As a result, the step-down circuit 100 operates so as to apply a voltage VF to the constant current source 11.

The backgate bias circuit 20 is connected to the first power supply wiring 2 and the common backgate of the first transistor M1 and the second transistor M2 constituting the differential pair 10. The backgate bias circuit 20 of the present embodiment is the same as the backgate bias circuit 20 of the first embodiment (see FIG. 2). Therefore, the same effect as (1-1) to (1-4) of the first embodiment can be obtained.

The operation of this embodiment will be described.
The backgate bias circuit 20 applies a bias voltage VB closer to the first power supply voltage VDD than the source potential of the first transistor M1 and the second transistor M2 to the common backgate of each transistor M1 and M2. Further, since the step-down circuit 100 applies a voltage VF lower than the first power supply voltage VDD to the constant current source 11, the first transistor is compared with the case where the first power supply voltage VDD is applied to the constant current source 11. The source potential of M1 and the second transistor M2 becomes low. In this way, the backgate bias circuit 20 and the step-down circuit 100 increase the backgate-source voltage VBS. In this embodiment, the backgate-source voltage VBS is higher than the backgate-source voltage VBSH. As a result, as can be seen from FIG. 3, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large. Therefore, the noise of the output signal Sout becomes small.

The voltage VF of the step-down circuit 100 and the bias voltage VB of the backgate bias circuit 20 have a bias voltage VB higher than that of the first power supply voltage VDD within a range in which the parasitic diodes of the first transistor M1 and the second transistor M2 do not turn on. It is good. That is, the bias voltage VB is preferably less than the voltage at which the parasitic diodes of the first transistor M1 and the second transistor M2 are turned on. An example of the voltage at which the parasitic diode of the first transistor M1 and the second transistor M2 is turned on is a voltage (VDD + 0.5 to 0.6) higher than the first power supply voltage VDD by 0.5 to 0.6 V. Preferably, the voltage VF of the step-down circuit 100 and the bias voltage VB of the backgate bias circuit 20 are controlled so that the backgate source voltage VBS is 20% higher than the backgate source voltage VBSH.

Further, each transistor of the operational amplifier 1B is the same as the configuration and manufacturing method of each transistor of the operational amplifier 1 of the first embodiment. Therefore, the same effect as the effect of (1-5) to (1-8) of the first embodiment can be obtained.

According to this embodiment, the following effects can be obtained.
(5-1) Since the operational amplifier 1B includes the step-down circuit 100 and the backgate bias circuit 20, the backgate-source voltage VBS can be increased by the voltage VF of the step-down circuit 100 and the bias voltage VB of the backgate bias circuit 20. can. Therefore, the noise of the output signal Sout of the operational amplifier 1B can be reduced. In addition, since the magnitude of the backgate-source voltage VBS can be controlled by two voltages, the voltage VF of the step-down circuit 100 and the bias voltage VB of the backgate bias circuit 20, it is easy to increase the backgate-source voltage VBS.

(Variation example of the fifth embodiment)
The operational amplifier 1B of the present embodiment can be changed as follows.
The operational amplifier 1B shown in FIG. 17A can be changed as shown in FIG. 18; The operational amplifier 1B of FIG. 18 is different from the operational amplifier 1B shown in FIG. 17 (a) in the conductive type of each transistor constituting the operational amplifier 1B. Further, the operational amplifier 1B of FIG. 18 is different from the operational amplifier 1B shown in FIG. 17A in that a booster circuit 103, which is an example of a voltage conversion circuit, is provided instead of the step-down circuit 100.

The first transistor M1 and the second transistor M2 of the differential pair 10, the transistor of the constant current source 11, and the transistor of the reference current source 13 are N-channel MOSFETs. The source of the transistor of the constant current source 11 is connected to the second power supply wiring 3, and the drain of the transistor of the constant current source 11 is connected to the source of the first transistor M1 and the second transistor M2.

The third transistor M3 and the fourth transistor M4 of the current mirror circuit 12 are P-channel MOSFETs. The sources of the third transistor M3 and the fourth transistor M4 are connected to the first power supply wiring 2, the drain of the third transistor M3 is connected to the drain of the first transistor M1, and the drain of the fourth transistor M4 is the second transistor. It is connected to the drain of M2.

In the operational amplifier 1B of FIG. 18, similarly to the operational amplifier 1B of FIG. 17A, the impurity concentration in the channel region of the first transistor M1 to the fourth transistor M4 is set to the transistor of the constant current source 11 and the transistor of the reference current source 13. , And the impurity concentration in the channel region of the plurality of transistors of the back gate bias circuit 20. Even in such an operational amplifier 1B of FIG. 18, the same effect as that of the operational amplifier 1B of FIG. 17A can be obtained.

The backgate bias circuit 20 is connected to the common backgate of the first transistor M1 and the second transistor M2 and the second power supply wiring 3. The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 so that the bias voltage VB is closer to the second power supply voltage VSS than the source potential of the first transistor M1 and the second transistor M2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the source potential of the first transistor M1 and the second transistor M2 is a voltage on the second power supply voltage VSS side of the intermediate voltage between the second power supply voltage VSS. VB is applied to the back gates of the first transistor M1 and the second transistor M2. Further, the bias voltage VB may be lower than the second power supply voltage VSS. The bias voltage VB is preferably a voltage excluding the voltage within a predetermined range including the second power supply voltage VSS, which is the same as the second power supply voltage VSS. In one example, the bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS among the voltages within ± 20% of the second power supply voltage VSS. According to this configuration, since the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, the noise of the output signal Sout of the operational amplifier 1 can be reduced.

The booster circuit 103 is provided between the second power supply wiring 3 and the differential pair 10, and more specifically, between the second power supply wiring 3 and the constant current source 11. The booster circuit 103 boosts the second power supply voltage VSS of the second power supply wiring 3 to a predetermined voltage and applies it to the constant current source 11. An example of the booster circuit 103 is a known charge pump type booster circuit.

In the operational amplifier 1B of FIG. 18, the bias voltage VB closer to the second power supply voltage VSS than the source potential of the first transistor M1 and the second transistor M2 by the back gate bias circuit 20 is a common back gate of each transistor M1 and M2. Is applied to. Since a voltage higher than the second power supply voltage VSS is applied to the constant current source 11 by the booster circuit 103, the first transistor M1 and the first transistor M1 and the second are compared with the case where the second power supply voltage VSS is applied to the constant current source 11. The source potential of the two-transistor M2 becomes high. In this way, the backgate bias circuit 20 and the booster circuit 103 increase the backgate-source voltage VBS. In this embodiment, the backgate-source voltage VBS is higher than the backgate-source voltage VBSH. As a result, as can be seen from FIG. 3, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large. Therefore, the noise of the output signal Sout becomes small.

According to the operational amplifier 1B of FIG. 18, the following effects can be further obtained.
Since the operational amplifier 1B includes the booster circuit 103 and the backgate bias circuit 20, the backgate source voltage VBS is increased by the voltage applied to the constant current source 11 by the booster circuit 103 and the bias voltage VB of the backgate bias circuit 20. Can be done. Therefore, the noise of the output signal Sout of the operational amplifier 1B can be reduced. In addition, since the magnitude of the backgate source voltage VBS can be controlled by the voltage applied to the constant current source 11 by the booster circuit 103 and the bias voltage VB of the backgate bias circuit 20, the backgate source voltage VBS Is easy to increase.

For each of the transistors M1 to M4 in the operational amplifier 1B shown in FIGS. 17 and 18, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment is used. May be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 and the sets of the transistors M3 and M4 of the current mirror circuit 12 are used as the embedded channel type MOSFET of the second embodiment. May be changed to.

In addition to reducing the impurity concentration in the channel region, an embedded channel MOSFET may be applied to each of the transistors M1 to M4 in the operational amplifier 1B shown in FIGS. 17 and 18. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1B shown in FIGS. 17 and 18 and the sets of the transistors M3 and M4 of the current mirror circuit 12 May be changed to the same structure as that of the transistors M1 to M4 of the third embodiment. Further, any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1B shown in FIGS. 17 and 18 and the sets of the transistors M3 and M4 of the current mirror circuit 12 May be changed to a structure similar to that of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1B shown in FIGS. 17 and 18 has a structure similar to that of the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the transistors M1 to M4 of the third embodiment. May be mixed.

(Sixth Embodiment)
The operational amplifier 1C of the sixth embodiment will be described with reference to FIG. The operational amplifier 1C of the present embodiment is different from the operational amplifier 1 of the first embodiment in that the input voltage to the back gate bias circuit 20 is different, and the output stage 93 and the capacitor 94 are added. The configuration of the output stage 93 and the capacitor 94 is the same as that of the output stage 93 and the capacitor 94 of the fifth embodiment.

As shown in FIG. 19, the backgate bias circuit 20 is connected to a third power supply wiring 4 to which a third power supply voltage VDD2 higher than the first power supply voltage VDD1 of the first power supply wiring 2 is applied. There is. Specifically, the backgate bias circuit 20 of the present embodiment has the fifth transistor M5 to the ninth transistor M9 and the constant current source 21 (see FIG. 2) like the backgate bias circuit 20 of the first embodiment. .. The sources of the fifth transistor M5, the eighth transistor M8, and the ninth transistor M9 are connected to the third power supply wiring 4.

The backgate bias circuit 20 connected to the third power supply wiring 4 applies a bias voltage VB to the common backgate of the first transistor M1 and the second transistor M2. The bias voltage VB is set by a voltage (VDD2-Vgs) whose voltage drops by the amount of the gate-source voltage Vgs of the fifth transistor M5 from the third power supply voltage VDD2 and the current Ibg flowing through the sixth transistor M6. Therefore, depending on the third power supply voltage VDD2, the bias voltage VB can be controlled to be higher than the first power supply voltage VDD1. The bias voltage VB of this embodiment is higher than the first power supply voltage VDD1. In this case, the bias voltage VB is preferably higher than the first power supply voltage VDD1 within a range in which the parasitic diodes of the first transistor M1 and the second transistor M2 are not turned on. That is, the bias voltage VB is preferably less than the voltage at which the parasitic diodes of the first transistor M1 and the second transistor M2 are turned on. An example of the voltage at which the parasitic diode of the first transistor M1 and the second transistor M2 is turned on is a voltage (ldap + 0.5 to 0.6) higher than the first power supply voltage VDD by 0.5 to 0.6 V. The bias voltage VB of the present embodiment is controlled so that the backgate-source voltage VBS is 20% or less higher than the first power supply voltage VDD1. Since the bias voltage VB is controlled in this way, the backgate-source voltage VBS becomes larger than the backgate-source voltage VBSH. Therefore, as can be seen from FIG. 3, the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large. Therefore, the noise of the output signal Sout becomes small.

Further, according to the present embodiment, since each transistor constituting the operational amplifier 1C has the same configuration and manufacturing method as each transistor constituting the operational amplifier 1 of the first embodiment, (1-5) to (1-5) of the first embodiment The same effect as the effect of (1-8) can be obtained.

(Modified example of the sixth embodiment)
The operational amplifier 1C of this embodiment can be changed as follows.
The operational amplifier 1C shown in FIG. 19 can be changed like the operational amplifier 1C shown in FIG. In the operational amplifier 1C of FIG. 20, the conductive type of each transistor constituting the operational amplifier 1C and the connection configuration of the back gate bias circuit 20 are different. In the operational amplifier 1C of FIG. 20, the reference current source 13, the output stage 93, and the capacitor 94 are omitted for convenience of explanation.

The first transistor M1 and the second transistor M2 of the differential pair 10 and the transistor of the constant current source 11 are N-channel MOSFETs. The source of the transistor of the constant current source 11 is connected to the second power supply wiring 3, and the drain of the transistor of the constant current source 11 is connected to the source of the first transistor M1 and the second transistor M2.

The third transistor M3 and the fourth transistor M4 of the current mirror circuit 12 are P-channel MOSFETs. The sources of the third transistor M3 and the fourth transistor M4 are connected to the first power supply wiring 2, the drain of the third transistor M3 is connected to the drain of the first transistor M1, and the drain of the fourth transistor M4 is the second transistor. It is connected to the drain of M2.

In the operational amplifier 1C of FIG. 20, similarly to the operational amplifier 1C of FIG. 19, the impurity concentration in the channel region of the first transistor M1 to the fourth transistor M4 is set to the channel region of the transistor of the constant current source 11 and the backgate bias circuit 20. It is lower than the impurity concentration. Even in such an operational amplifier 1C of FIG. 20, the same effects as those of (1-5) to (1-8) of the first embodiment can be obtained.

In the backgate bias circuit 20, a common backgate of the first transistor M1 and the second transistor M2 and a fourth power supply voltage VSS2 lower than the second power supply voltage VSS1 of the second power supply wiring 3 are applied. It is connected to the power supply wiring 5 of 4. The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 so that the bias voltage VB is closer to the fourth power supply voltage VSS2 than the source potential of the first transistor M1 and the second transistor M2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the voltage is on the fourth power supply voltage VSS2 side of the intermediate voltage between the source potential of the first transistor M1 and the second transistor M2 and the fourth power supply voltage VSS2. VB is applied to the back gates of the first transistor M1 and the second transistor M2. That is, the backgate bias circuit 20 applies a bias voltage VB so that the backgate-source voltage VBS becomes large to the backgate of the first transistor M1 and the second transistor M2. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. The bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS1 among the voltages within a predetermined range including the second power supply voltage VSS1. In one example, the bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS1 among the voltages within ± 20% of the second power supply voltage VSS1. According to this configuration, since the transconductance gm12 of the first transistor M1 and the second transistor M2 becomes large, the noise of the output signal Sout of the operational amplifier 1 can be reduced.

For each of the transistors M1 to M4 in the operational amplifier 1C of FIGS. 19 and 20, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment is applied. You may. As a result, the same effect as that of the second embodiment can be obtained. Further, one or two sets of one or two sets of the transistors M1 and M2 constituting the differential pair 10 and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are embedded in the second embodiment. It may be changed to a channel type MOSFET.

In addition to reducing the impurity concentration in the channel region, an embedded channel MOSFET may be applied to each of the transistors M1 to M4 in the operational amplifier 1C of FIGS. 19 and 20. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, one or two of the set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1C of FIGS. 19 and 20 and the set of the transistors M3 and M4 constituting the current mirror circuit 12. The set may be changed to a structure similar to the structure of each of the transistors M1 to M4 of the third embodiment. Further, any one or 2 of the set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1C of FIGS. 19 and 20 and the set of the transistors M3 and M4 constituting the current mirror circuit 12. The set may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1C of FIGS. 19 and 20 has a structure similar to that of the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the transistors M1 to M4 of the third embodiment. It may be a mixed configuration.

(7th Embodiment)
The operational amplifier 1D of the seventh embodiment will be described with reference to FIGS. 21 and 22.
As shown in FIG. 21, the operational amplifier 1D of the present embodiment has the third transistor M3 and the third transistor M3 and the second transistor M2 instead of increasing the transconductance gm12 in order to reduce the noise of the output signal Sout. The transconductance gm34 of the fourth transistor M4 is reduced.

Specifically, the operational amplifier 1D omits the back gate bias circuit 20 as compared with the operational amplifier 1 of the first embodiment, and has a first resistance portion between the current mirror circuit 12 and the second power supply wiring 3. The difference is that the first resistor R1 which is an example and the second resistor R2 which is an example of the second resistance section are added.

Specifically, the first resistance R1 is provided between the third transistor M3 and the second power supply wiring 3. The first terminal of the first resistance R1 is connected to the source of the third transistor M3, and the second terminal of the first resistance R1 is connected to the second power supply wiring 3. The second resistance R2 is provided between the fourth transistor M4 and the second power supply wiring 3. The first terminal of the second resistance R2 is connected to the source of the fourth transistor M4, and the second terminal of the second resistance R2 is connected to the second power supply wiring 3. In the present embodiment, the current ratio between the third transistor M3 and the fourth transistor M4 is 1: 1 and the resistance value of the first resistance R1 and the resistance value of the second resistance R2 are equal to each other.

With such a configuration, when a drain current flows through the third transistor M3 and the fourth transistor M4 and the gate-source voltage Vgs of the respective transistors M3 and M4 rises, the first resistance R1 and the second resistance R2 cause each transistor M3. , Since the source potential of M4 rises, it operates so as to prevent an increase in the drain current flowing through each of the transistors M3 and M4. That is, when viewed from the drain side of each transistor M3 and M4 as an effective transconductance gm34, the gate-source voltage Vgs of each transistor M3 and M4 becomes smaller according to the first resistance R1 and the second resistance R2. The transistors M3 and M4 operate in the direction of reducing the drain current. Therefore, the transconductance gm34 on the circuit is lowered.

Further, the transistors M1 to M4 of the operational amplifier 1D and the transistors of the constant current source 11 of the present embodiment have the same configuration and manufacturing method as the transistors M1 to M4 of the operational amplifier 1 of the first embodiment and the transistors of the constant current source 11. be. Therefore, the same effects as those of (1-5) and (1-6) of the first embodiment can be obtained.

The operation and effect of this embodiment will be described. In the following description, an operational amplifier in which the first resistor R1 and the second resistor R2 are omitted from the operational amplifier 1D is referred to as a comparative operational amplifier.
The input conversion noise voltage as the noise of the output signal Sout of the operational amplifier 1D of the present embodiment is represented by (Equation 1) of the first embodiment. As can be seen from (Equation 1), in order to reduce the input conversion noise voltage Vn ² , at least one of the channel width W and the channel length L of the first transistor M1 to the fourth transistor M4 should be increased, and the transconductance gm34 should be increased. At least one of smaller and larger transconductance gm12 is required. Further, as can be seen from (Equation 2) of the first embodiment, in order to reduce the transconductance gm34, at least one of increasing the channel length L and decreasing the channel width W is required, and transconductance is required. In order to increase gm12, it is necessary to increase the channel width W, decrease the channel length L, and increase the drain current ID at least one of them.

When the channel width W of the first transistor M1 and the second transistor M2 is increased, or when the channel length L of the third transistor M3 and the fourth transistor M4 is increased, the element area increases. When the element area increases, it becomes a factor of deterioration of transistor characteristics such as an increase in parasitic capacitance. On the other hand, when the channel length L of the first transistor M1 and the second transistor M2 is reduced, or when the channel width W of the third transistor M3 and the fourth transistor M4 is reduced, the threshold value is set due to the short channel effect or the narrow channel effect. The voltage fluctuates. Further, when the drain currents I (ID1 and ID2) of the first transistor M1 and the second transistor M2 are increased, the current consumption of the operational amplifier 1 increases.

Therefore, in order to reduce the noise of the output signal Sout, it is conceivable to reduce the transconductance gm34 of each of the active load transistors M3 and M4. As can be seen from (Equation 2), in order to reduce the transconductance gm, it is conceivable to reduce the drain current ID. Therefore, in order to reduce the transconductance gm34, it is conceivable to reduce the current flowing through each of the transistors M3 and M4. However, in the comparative operational amplifier, when the current flowing through the transistors M3 and M4 is reduced, the current flowing through the transistors M1 and M2 of the differential pair 10 is also reduced. As a result, in the comparative operational amplifier, the transconductance gm12 of each of the transistors M1 and M2 becomes small, and as can be seen from (Equation 1), it hinders the reduction of noise in the output signal of the comparative operational amplifier.

In that respect, in the operational amplifier 1D of the present embodiment, each transistor M3 is increased by raising the source potential of each transistor M3 and M4 when a current flows through each transistor M3 and M4 by the first resistor R1 and the second resistor R2. , Operates in the direction of reducing the current flowing through M4. Therefore, since the transconductance gm34 of each of the transistors M3 and M4 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1D can be reduced.

FIG. 22 shows the relationship between the input-converted noise voltage of the comparative operational amplifier and the input-converted noise voltage of the operational amplifier 1D, and the frequency. The broken line graph G6 in FIG. 22 shows the input-converted noise voltage of the comparative operational amplifier, and the solid line graph G7 in FIG. 22 shows the input-converted noise voltage of the operational amplifier 1D. As can be seen from the graphs G6 and G7 of FIG. 22, the input conversion noise voltage of the operational amplifier 1D is lower than that of the comparative operational amplifier.

(Variation example of the 7th embodiment)
The operational amplifier 1D of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The operational amplifier 1D may have the cascode current mirror circuit 91 and the bias circuit 92 of the fourth embodiment instead of the current mirror circuit 12. In this case, a first resistance R1 is provided between the tenth transistor M10 of the cascode current mirror circuit 91 and the second power supply wiring 3, and a second resistance is provided between the eleventh transistor M11 and the second power supply wiring 3. R2 is provided.

The resistance value of the first resistance R1 and the resistance value of the second resistance R2 may be changed according to the ratio of the third transistor M3 and the fourth transistor M4.
-For each of the transistors M1 to M4 in the operational amplifier 1D, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, the second implementation is any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1D and the sets of the transistors M3 and M4 constituting the current mirror circuit 12. It may be changed to the embedded channel type MOSFET of the form.

-For each of the transistors M1 to M4 in the operational amplifier 1D, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, one or two sets of any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1D and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are used in the third embodiment. The structure may be changed to the same as the structure of each transistor M1 to M4. Further, one or two sets of one or two sets of the transistors M1 and M2 constituting the differential pair 10 and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are embedded in the second embodiment. The structure may be changed to the same structure as that of the channel type MOSFET or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1D has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(8th Embodiment)
The operational amplifier 1E of the eighth embodiment will be described with reference to FIG. 23. The operational amplifier 1E of the present embodiment is different from the operational amplifier 1D of the seventh embodiment in the method of controlling the source potential of the third transistor M3 and the fourth transistor M4.

The operational amplifier 1E has a configuration in which a first control unit 110A for controlling the source potential of the third transistor M3 and a second control unit 110B for controlling the source potential of the fourth transistor M4 are added to the operational amplifier 1D of the seventh embodiment. Is.

The first control unit 110A controls the source potential of the third transistor M3 by controlling the current supplied to the node NA1 between the source of the third transistor M3 and the first resistance R1. The first control unit 110A includes a first constant current source 111 and a first control transistor MA1. The first control transistor MA1 of this embodiment is an N-channel MOSFET. The first constant current source 111 is provided between the first power supply wiring 2 and the first control transistor MA1. The first constant current source 111 includes a transistor (not shown). The transistor of the first constant current source 111 is a P-channel MOSFET. The drain of the transistor of the first constant current source 111 is connected to the drain of the first control transistor MA1, and the source of the transistor is connected to the first power supply wiring 2. The source of the first control transistor MA1 is connected to the node NA1 between the source of the third transistor M3 and the first resistance R1, and the gate of the first control transistor MA1 is connected to the gate and drain of the third transistor M3. It is connected. With this configuration, in the first control unit 110A, the gate voltage of the first control transistor MA1 is controlled by the gate voltage of the third transistor M3, and the first current Ic1 proportional to the constant current It of the constant current source 11 is a node. It is supplied to NA1. The gate of the first control transistor corresponds to the "control terminal of the first control transistor", and the gate of the second control transistor corresponds to the "control terminal of the second control transistor".

The second control unit 110B controls the source potential of the fourth transistor M4 by controlling the current supplied to the node NA2 between the source of the fourth transistor M4 and the second resistor R2. The second control unit 110B includes a second constant current source 112 and a second control transistor MA2. The second control transistor MA2 of this embodiment is an N-channel MOSFET. The second constant current source 112 is provided between the first power supply wiring 2 and the second control transistor MA2. The second constant current source 112 includes a transistor (not shown). The transistor of the second constant current source 112 is a P-channel MOSFET. The drain of the transistor of the second constant current source 112 is connected to the drain of the second control transistor MA2, and the source of the transistor is connected to the first power supply wiring 2. The source of the second control transistor MA2 is connected to the node NA2 between the source of the fourth transistor M4 and the second resistance R2, and the gate of the second control transistor MA2 is connected to the gate and drain of the third transistor M3. It is connected. With this configuration, in the second control unit 110B, the gate voltage of the second control transistor MA2 is controlled by the gate voltage of the third transistor M3, and the second current Ic2 proportional to the constant current It of the constant current source 11 is a node. It is supplied to NA2.

As described above, the source of the third transistor M3 is supplied with the first current Ic1 from the first control unit 110A, and the source of the fourth transistor M4 is supplied with the second current Ic2 from the second control unit 110B. , The source potential of the third transistor M3 and the source potential of the fourth transistor M4 increase. In addition, as described in the seventh embodiment, the source potentials of the third transistor M3 and the fourth transistor M4 are increased by the first resistance R1 and the second resistance R2. As described above, in the present embodiment, the source potentials of the transistors M3 and M4 are further increased as compared with the seventh embodiment. Therefore, the transconductance gm34 on the circuit is further reduced.

Further, the transistors M1 to M4 of the present embodiment and the transistors of the constant current source 11 have the same configuration and manufacturing method as the transistors of the transistors M1 to M4 and the constant current source 11 of the first embodiment. Therefore, as described in (1-5) and (1-6) of the first embodiment, the noise of the output signal Sout can be effectively reduced.

Since the transistors of the transistors MA1 and MA2 and the constant current sources 111 and 112 are not easily affected by the 1 / f noise of the output signal Sout, the channel region in the transistors of the transistors MA1 and MA2 and the constant current sources 111 and 112 is The impurity concentration of is made higher than the impurity concentration of the channel region in each of the transistors M1 to M4. In other words, the impurity concentration in the channel region of each of the transistors M1 to M4 is lower than the impurity concentration of the channel region of each of the transistors MA1 and MA2 and the constant current sources 111 and 112. That is, the transistors M1 to M4 are low-concentration transistors, and the transistors MA1 and MA2 and the constant current sources 111 and 112 are high-concentration transistors. The impurity concentration in the channel region of each of the transistors M1 to M4 is preferably about 1/2 or less of the impurity concentration in the channel region of each of the transistors MA1 and MA2 and the constant current sources 111 and 112. In the present embodiment, the impurity concentration in the channel region of each of the transistors M1 to M4 is about 1/10 of the impurity concentration of the channel region of each of the transistors MA1 and MA2 and the constant current sources 111 and 112. Further, the transistors MA1 and MA2 and the transistors of the constant current sources 111 and 112 are surface channel type MOSFETs.

According to this embodiment, the following effects can be further obtained.
(8-1) Since the impurity concentration in the channel region of the first control transistor MA1 and the second control transistor MA2 is higher than the impurity concentration in the channel region of each of the transistors M1 to M4, the transistors MA1 and MA2 are used. The variation of the threshold voltage can be suppressed, and the first control unit 110A and the second control unit 110B can operate stably.

(8-2) Since the impurity concentration in the channel region of the transistor of the first constant current source 111 and the transistor of the second constant current source 112 is higher than the impurity concentration in the channel region of each of the transistors M1 to M4, each constant current source 111 It is possible to suppress the variation of the threshold current of the transistor in 112, and the first control unit 110A and the second control unit 110B can operate stably.

(8-3) The impurity concentration in the channel region of the transistor, which is the P-channel MOSFET of the first constant current source 111 of the first control unit 110A and the second constant current source 112 of the second control unit 110B, and the constant current source 11. The impurity concentrations in the channel region of the transistor, which is a P-channel MOSFET, are equal to each other. According to this configuration, the step of forming the N-type well layer 63 of the transistors of the constant current sources 111 and 112 and the step of forming the N-type well layer 63 of the transistor of the constant current source 11 can be collectively performed. can. Therefore, the process of manufacturing the operational amplifier 1E can be simplified.

(Variation example of the eighth embodiment)
The operational amplifier 1E of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

-For each of the transistors M1 to M4 in the operational amplifier 1E, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, the second implementation is any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1E and the sets of the transistors M3 and M4 constituting the current mirror circuit 12. It may be changed to the embedded channel type MOSFET of the form.

-For each of the transistors M1 to M4 in the operational amplifier 1E, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, the third embodiment includes any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1E and the transistors M3 and M4 constituting the current mirror circuit 12. The structure may be changed to the same as the structure of each of the transistors M1 to M4. Further, one or two sets of one or two of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1E and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are secondly implemented. The structure may be changed to the same structure as that of the embedded channel MOSFET of the embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1E has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

The operational amplifier 1E may have the cascode current mirror circuit 91 and the bias circuit 92 of the fourth embodiment instead of the current mirror circuit 12. In this case, a first resistance R1 is provided between the tenth transistor M10 of the cascode current mirror circuit 91 and the second power supply wiring 3, and a second resistance is provided between the eleventh transistor M11 and the second power supply wiring 3. R2 is provided. The source of the first control transistor MA1 of the first control unit 110A is connected to a node (not shown) between the source of the tenth transistor M10 and the first resistance R1 and is connected to a second control unit 110B. The source of the control transistor MA2 is connected to a node (not shown) between the source of the eleventh transistor M11 and the second resistance R2.

Further, the impurity concentration in the channel region of the transistor which is the P channel MOSFET of the first constant current source 111 of the first control unit 110A and the second constant current source 112 of the second control unit 110B and the P channel MOSFET of the bias circuit 92. The impurity concentrations in the channel regions of the 16th transistor M16 and the 17th transistor M17 are equal to each other. According to this configuration, the step of forming the N-type well layer 63 of the transistors of the constant current sources 111 and 112 and the step of forming the N-type well layer 63 of the transistors M16 and M17 can be collectively performed. .. Therefore, the process of manufacturing the operational amplifier 1E can be simplified.

Further, the impurity concentration in the channel region of the first control transistor MA1 of the first control unit 110A and the second control transistor MA2 of the second control unit 110B, and the 12th transistors M12 and 13 of the cascode current mirror circuit 91. The impurity concentrations in the channel region of the transistor M13 are equal to each other. According to this configuration, the step of forming the P-type well layer 41 of each transistor MA1 and MA2 and the step of forming the P-type well layer 41 of each of the transistors M12 and M13 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1E can be simplified.

(9th Embodiment)
The operational amplifier 1F of the ninth embodiment will be described with reference to FIGS. 24 and 25. The operational amplifier 1F of the present embodiment is different from the operational amplifier 1 of the first embodiment in that the back gate bias circuit 20 is omitted and the current adjusting unit 120 is added.

As shown in FIG. 24, the current adjusting unit 120 makes the current flowing through the first transistor M1 and the second transistor M2 larger than the current flowing through the third transistor M3 and the fourth transistor M4. More specifically, the current adjusting unit 120 increases the current flowing through the first transistor M1 and the second transistor M2 more than the constant current It of the constant current source 11, and the current corresponding to the increase of the current flowing through each of the transistors M1 and M2. Is prevented from flowing through the third transistor M3 and the fourth transistor M4. The current adjusting unit 120 includes a current supply unit 121 and a branching unit 122.

The current supply unit 121 supplies a current to the first transistor M1 and the second transistor M2 separately from the constant current It of the constant current source 11. The current supply unit 121 includes a first supply transistor MB1, a second supply transistor MB2, and a third supply transistor MB3. The first supply transistor MB1 and the third supply transistor MB3 of the present embodiment are P-channel MOSFETs, and the second supply transistor MB2 is an N-channel MOSFET.

The first supply transistor MB1 and the second supply transistor MB2 form a series circuit between the first power supply wiring 2 and the second power supply wiring 3. The source of the first supply transistor MB1 is connected to the first power supply wiring 2, the gate of the first supply transistor MB1 is connected to the drain of the first supply transistor MB1, and the first supply transistor MB1 is connected. Is connected to the drain of the second supply transistor MB2. The source of the second supply transistor MB2 is connected to the second power supply wiring 3. The gate of the second supply transistor corresponds to the "control terminal of the second supply transistor".

The third supply transistor MB3 is provided between the first power supply wiring 2 and the differential pair 10. The source of the third supply transistor MB3 is connected to the first power supply wiring 2, the drain of the third supply transistor MB3 is connected to the sources of the first transistor M1 and the second transistor M2, and the third supply transistor M2 is connected. The gate of the transistor MB3 is connected to the gate of the first supply transistor MB1. As a result, the first supply transistor MB1 and the third supply transistor MB3 form a current mirror circuit.

In the present embodiment, the current amount of the first supply transistor MB1 and the current amount of the second supply transistor MB2 are equal to each other. The size ratio (current ratio) of the first supply transistor MB1 and the third supply transistor MB3 is 1: 1.

The branch portion 122 causes each of the increased current of the drain current flowing through the first transistor M1 and the increased current of the drain current flowing through the second transistor M2 to flow through the second power supply wiring 3. The branch portion 122 includes a first branch circuit 123 and a second branch circuit 124.

The first branch circuit 123 includes a first branch transistor MB4 which is an example of a first adjustment transistor connected in parallel with the third transistor M3. The first branch transistor MB4 of this embodiment is an N-channel MOSFET. The drain of the first branch transistor MB4 is connected to the drain of the first transistor M1, the source of the first branch transistor MB4 is connected to the second power supply wiring 3, and the gate of the first branch transistor MB4 is. It is connected to the drain (gate) of the third transistor M3.

The second branch circuit 124 includes a second branch transistor MB5 which is an example of a second adjusting transistor connected in parallel with the fourth transistor M4. The second branch transistor MB5 of this embodiment is an N-channel MOSFET. The drain of the second branch transistor MB5 is connected to the drain of the second transistor M2, the source of the second branch transistor MB5 is connected to the second power supply wiring 3, and the gate of the second branch transistor MB5 is. It is connected to the drain (gate) of the third transistor M3. The drain of the second branching transistor MB5 is connected to the second transistor M2 side of the node N1 to which the output terminal OUT is connected.

Further, the gate of the second supply transistor MB2 is connected to the gate of the second branch transistor MB5. As described above, the branching transistors MB4 and MB5, the second supply transistor MB2, and the third transistor M3 form a current mirror circuit. The gate of the first branch transistor MB4 corresponds to the "control terminal of the first adjustment transistor", and the gate of the second branch transistor MB5 corresponds to the "control terminal of the second adjustment transistor". do.

The electrical characteristics of the first branch transistor MB4 of the first branch circuit 123 and the second branch transistor MB5 of the second branch circuit 124 are equal to each other. In addition, since the gate voltages of the transistors MB2, MB4, and MB5 are common, the current amount of the second supply transistor MB2 is 2 of the current amount of the first branch transistor MB4 (second branch transistor MB5). Since it is doubled, the total current flowing through each of the transistors MB4 and MB5 is generated in the second supply transistor MB2.

In the present embodiment, the electrical characteristics of each of the transistors MB4 and MB5 and the third transistor M3 and the fourth transistor M4 are set to be equal to each other. In addition, since the gates of the transistors MB4 and MB5 are connected to the gate of the third transistor M3, the current flowing through the first branching transistor MB4 and the current flowing through the second branching transistor MB5 are different. It becomes equal to the current flowing through the three transistors M3 (the current flowing through the fourth transistor M4).

Next, the current flowing through the operational amplifier 1F, particularly the current flowing through the current adjusting unit 120 will be described. In this description, the constant current flowing through the constant current source 11 is 2 ID.
In the operational amplifier 1F, the constant current 2ID and the supply current IDB3 from the third supply transistor MB3 are supplied to the differential pair 10. The supply current IDB3 is a current proportional to the current IDB2 flowing through the second supply transistor MB2 by the current mirror circuit including the transistors MB1 and MB3. In the present embodiment, the supply current IDB3 is equal to the current IDB2 because the current ratio between the first supply transistor MB1 and the third supply transistor MB3 is 1: 1. More specifically, the current IDB2 is a current proportional to the current ID3 of the third transistor M3 by the current mirror circuit including each transistor M3, MB4, MB5, MB2. In the present embodiment, the current ratio between the transistors MB4 and MB5 and the transistors M3 and M4 is 1: 1 so that the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5 are equal to the current ID3. In addition, since the second supply transistor MB2 and the respective transistors MB4 and MB5 form a current mirror circuit, the current IDB2 flowing in the second supply transistor MB2 is the current flowing in the respective transistors MB4 and MB5. It becomes the total (IDB4 + IDB5). That is, the supply current IDB3 supplied to the differential pair 10 is the total of the currents flowing through the transistors MB4 and MB5 (IDB4 + IDB5). Further, since the currents flowing through the transistors M3, M4, MB4, and MB5 are equal to each other, the total current (ID3 + ID4), that is, the constant current 2ID and the current flowing through the transistors MB4, MB5 are used. The total current (IDB4 + IDB5) is equal to each other. Therefore, in the present embodiment, the supply current IDB3 and the constant current 2ID are equal to each other.

Further, the current IDx flowing through each of the transistors M1 and M2 is IDx = (2ID + IDB3) / 2 when the inputs of the constant current 2ID and the supply current IDB3 are in phase, that is, when the gate voltage which is an input signal is in phase. Become. In this way, the current IDx flowing through each of the transistors M1 and M2 is larger than the current ID (constant current 2ID / 2) by 1/2 of the current IDB3. On the other hand, the currents IDB4 and IDB5 are pulled out from the drains of the transistors M1 and M2 by the third transistor M3 and the transistors MB4 and MB5 of the branch portion 122 constituting the current mirror circuit, respectively. As a result, the current ID3 flowing through the third transistor M3 becomes IDx-IDB4, and the current ID4 flowing through the fourth transistor M4 becomes IDx-IDB5. Therefore, each of the currents IDB4 and IDB5 of the present embodiment is 1/2 of the current IDB3. That is, the increase in the current flowing through the transistors M1 and M2, that is, the supply current from the current supply unit 121 is passed through the transistors MB4 and MB5. In this way, the current adjusting unit 120 supplies a current equal to the constant current 2ID of the constant current source 11 to the differential pair 10, and causes a current of 1/2 of the constant current 2ID to flow through the transistors MB4 and MB5. , Only the current ID flows through each of the transistors M3 and M4. Therefore, the current adjusting unit 120 does not increase the current flowing through the transistors M3 and M4 even if the current flowing through the transistors M1 and M2 is increased.

The operation of this embodiment will be described. The comparative operational amplifier to be compared with the operational amplifier 1F of the present embodiment has a configuration consisting only of a differential pair 10 and a current mirror circuit 12 as an active load.

The input conversion noise voltage as the noise of the output signal Sout having a configuration such as the operational amplifier 1F of the present embodiment or the comparative operational amplifier is represented by (Equation 1) of the first embodiment. As can be seen from (Equation 1), in order to reduce the input conversion noise voltage Vn ² , at least one of the channel width W and the channel length L of the first transistor M1 to the fourth transistor M4 should be increased, and the transconductance gm34 should be increased. At least one of smaller and larger transconductance gm12 is required. Further, as can be seen from (Equation 2) of the first embodiment, in order to reduce the transconductance gm34, at least one of increasing the channel length L and decreasing the channel width W is required, and transconductance is required. In order to increase gm12, it is necessary to increase the channel width W, decrease the channel length L, and increase the drain current ID at least one of them.

When the channel width W of the first transistor M1 and the second transistor M2 is increased, or when the channel length L of the third transistor M3 and the fourth transistor M4 is increased, the element area increases. When the element area increases, it becomes a factor of deterioration of transistor characteristics such as an increase in parasitic capacitance. On the other hand, when the channel length L of the first transistor M1 and the second transistor M2 is reduced, or when the channel width W of the third transistor M3 and the fourth transistor M4 is reduced, the threshold value is set due to the short channel effect or the narrow channel effect. The voltage fluctuates.

Therefore, as can be seen from (Equation 1), in order to reduce the noise of the output signal Sout, it is conceivable to increase the transconductance gm12 of each transistor M1 and M2 of the differential pair 10. On the other hand, if the transconductance gm34 of each of the transistors M3 and M4 of the current mirror circuit 12 is increased, the noise of the output signal Sout becomes large.

Further, as can be seen from (Equation 2), in order to increase the transconductance gm, it is conceivable to increase the drain current ID. Therefore, in order to increase the transconductance gm12, it is conceivable to increase the current IDx flowing through each of the transistors M1 and M2. Here, in the comparative operational amplifier, when the current IDx flowing through the transistors M1 and M2 is increased, the currents ID3 and ID4 flowing through the transistors M3 and M4 are also increased. As a result, the transconductance gm34 of each of the transistors M3 and M4 becomes large, and as can be seen from (Equation 1), it hinders the reduction of noise in the output signal Sout.

Further, generally, the slew rate SR of the operational amplifier is defined by SR = ID / Cc from the phase compensation capacitance Cc and the drain current ID. Therefore, the slew rate SR increases as the drain current ID increases, and as a result, the operation of the operational amplifier 1F becomes high speed, and problems such as oscillation are likely to occur. On the other hand, if the phase compensation capacity Cc is increased in order to suppress the slew rate SR, the chip area becomes large.

In that respect, in the present embodiment, the current adjusting unit 120 increases the current flowing through the transistors M1 and M2 of the differential pair 10 and does not increase the current flowing through the transistors M3 and M4 of the current mirror circuit 12 which is an active load. I am doing it. As a result, the transconductance gm12 of each transistor M1 and M2 increases, while the transconductance gm34 of each transistor M3 and M4 does not increase. Therefore, the noise of the output signal Sout can be reduced. In addition, the current contributing to the output current to the output terminal OUT by the branch portion 122 has a total current of 2 ID, and therefore does not change even if the current supplied to the differential pair 10 increases. Therefore, it is possible to suppress an increase in the slew rate SR.

FIG. 25 shows the relationship between the input-converted noise voltage of the comparative operational amplifier, the input-converted noise voltage of the operational amplifier 1F, and the frequency. The graph G8 shown by the broken line in FIG. 25 shows the input-converted noise voltage of the comparative operational amplifier, and the graph G9 shown by the solid line in FIG. 25 shows the input-converted noise voltage of the operational amplifier 1F. As can be seen from the graphs G8 and G9 in FIG. 25, the input conversion noise voltage of the operational amplifier 1F is lower than that of the comparative operational amplifier.

Further, the transistors M1 to M4 of the operational amplifier 1F and the transistors of the constant current source 11 of the present embodiment have the same configuration and manufacturing method as the transistors M1 to M4 and the constant current source 11 of the operational amplifier 1 of the first embodiment. be. Therefore, as described in (1-5) and (1-6) of the first embodiment, 1 / f noise of the output signal Sout can be effectively reduced.

Since each of the transistors MB1 to MB5 of the current adjusting unit 120 is not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each of the transistors MB1 to MB5 is set to the impurity concentration of the channel region of each of the transistors M1 to M4. It is higher than the concentration. In other words, the impurity concentration in the channel region of each of the transistors M1 to M4 is lower than the impurity concentration of the channel region of each of the transistors MB1 to MB5. That is, the transistors M1 to M4 are low-concentration transistors, and the transistors MB1 to MB5 are high-concentration transistors. The impurity concentration in the channel region of each of the transistors M1 to M4 is preferably about 1/2 or less of the impurity concentration of the channel region of each of the transistors MB1 to MB5. In the present embodiment, the impurity concentration in the channel region of each of the transistors M1 to M4 is about 1/10 of the impurity concentration of the channel region of each of the transistors MB1 to MB5. Further, each transistor MB1 to MB5 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(9-1) Since the current supplied to the first transistor M1 and the second transistor M2 constituting the differential pair 10 can be increased by the current supply unit 121 as compared with the constant current 2ID, the first transistor M1 and the first transistor M1 and the second transistor M2 can be increased. The transconductance gm12 of the two-transistor M2 can be increased. On the other hand, since a part of the current from the first transistor M1 and the second transistor M2 flows to the branch portion 122 by the branch portion 122, the current flowing through the third transistor M3 and the fourth transistor M4 flows to the first transistor M1 and the second transistor M2. It is smaller than the current flowing through the transistor M2. Therefore, it is possible to suppress an increase in the transconductance gm34 of the third transistor M3 and the fourth transistor M4. Therefore, the noise of the output signal Sout of the operational amplifier 1F can be reduced.

(9-2) Current IDB4 flowing through the first branching transistor MB4 and current IDB5 flowing through the second branching transistor MB5 due to element variation of the first branching transistor MB4 and the second branching transistor MB5. If there is a difference between the two, the currents ID3 and ID4 flowing through the third transistor M3 and the fourth transistor M4 may be affected, and an offset voltage of the third transistor M3 and the fourth transistor M4 may be generated.

In the present embodiment, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 are equal to the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the currents ID3 and ID4 flowing through the three transistors M3 and the fourth transistor M4 can be reduced.

(9-3) Since the impurity concentration in the channel region of each transistor MB1 to MB5 in the current adjusting unit 120 is higher than the impurity concentration in the channel region of each transistor M1 to M4, the threshold voltage of each transistor MB1 to MB5 is increased. The variation can be suppressed, and the current adjusting unit 120 can operate stably.

(9-4) The impurity concentration in the channel region of each transistor MB1 and MB3 in the current adjusting unit 120 and the impurity concentration in the channel region of the transistor of the constant current source 11 are equal to each other. According to this configuration, the step of forming the N-type well layer 63 of each of the transistors MB1 and MB3 and the step of forming the N-type well layer 63 of the transistor of the constant current source 11 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1F can be simplified.

(Variation example of the ninth embodiment)
The operational amplifier 1F of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the current adjusting unit 120 of the operational amplifier 1F, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the currents ID3 and ID4 flowing through the three transistors M3 and the fourth transistor M4 can be further reduced.

-For each of the transistors M1 to M4 in the operational amplifier 1F, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, the second implementation is any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1F and the sets of the transistors M3 and M4 constituting the current mirror circuit 12. It may be changed to the embedded channel type MOSFET of the form.

-For each of the transistors M1 to M4 in the operational amplifier 1F, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, one or two sets of any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1F and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are used in the third embodiment. The structure may be changed to the same as the structure of each transistor M1 to M4. Further, one or two sets of one or two sets of the transistors M1 and M2 constituting the differential pair 10 and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are embedded in the second embodiment. The structure may be changed to the same structure as that of the channel type MOSFET or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1F has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(10th Embodiment)
The operational amplifier 1G of the tenth embodiment will be described with reference to FIG. 26. The operational amplifier 1G of the present embodiment is different from the operational amplifier 1F of the ninth embodiment mainly in that the current mirror circuit is changed to the cascode current mirror circuit and the bias circuit is added as an active load. Since the cascode current mirror circuit and the bias circuit of the present embodiment are the same as the cascode current mirror circuit 91 and the bias circuit 92 of the fourth embodiment, the same reference numerals are used and the description thereof will be omitted.

Since the operational amplifier 1G is changed from the current mirror circuit 12 to the cascode current mirror circuit 91, the connection configurations of the first branch circuit 123 and the second branch circuit 124 of the branch portion 122 in the current adjustment unit 120 are different as follows.

The first branching transistor MB4 of the first branching circuit 123 is connected to the node NB1 between the drain of the first transistor M1 and the drain of the tenth transistor M10. More specifically, the drain of the first branch transistor MB4 is connected to the node NB1, and the source of the first branch transistor MB4 is connected to the second power supply wiring 3. The second branching transistor MB5 of the second branching circuit 124 is connected to the node NB2 between the drain of the second transistor M2 and the drain of the eleventh transistor M11. More specifically, the drain of the second branch transistor MB5 is connected to the node NB2, and the source of the second branch transistor MB5 is connected to the second power supply wiring 3. The gates of the transistors MB4 and MB5 are commonly connected to the gate of the tenth transistor M10. Further, the gate of the second supply transistor MB2 of the current supply unit 121 of the current adjustment unit 120 is connected to the gate of the tenth transistor M10. As described above, each transistor MB2, MB4, MB5 constitutes a current mirror circuit with the tenth transistor M10.

The current flowing through the operational amplifier 1G, particularly the current flowing through the current adjusting unit 120, is the same as that of the ninth embodiment except that the third transistor M3 and the fourth transistor M4 of the ninth embodiment are replaced with the tenth transistor M10 and the eleventh transistor M11. This is the same as the current flowing through the current adjusting unit 120. Therefore, an effect similar to the effects of (9-1) and (9-2) of the ninth embodiment can be obtained.

Further, each transistor constituting the operational amplifier 1G is the same as the structure and manufacturing method of the transistor excluding the transistor of the back gate bias circuit 20 among the transistors constituting the operational amplifier 1A of the fourth embodiment. That is, the impurity concentration in the channel region of each of the transistors M1, M2, M10 to M17 is the same as the impurity concentration of the channel region in each of the transistors M1, M2, M10 to M17 of the fourth embodiment. Further, the impurity concentration in the channel region of the transistor of the constant current source 11 and the transistors M12, M13, M16, and M17 is the same as that of the transistor of the constant current source 11 of the fourth embodiment and the transistors M12, M13, M16, and M17. It is the same as the impurity concentration in the channel region. Therefore, it is possible to obtain an effect similar to the effects of (4-1) to (4-3) of the fourth embodiment.

Further, the structure and manufacturing method of the transistors MB1 to MB5 of the present embodiment are the same as those of the transistors MB1 to MB5 of the ninth embodiment. That is, each transistor MB1 to MB5 has the same impurity concentration in the channel region as the impurity concentration in the channel region in each transistor MB1 to MB5 of the ninth embodiment, and is the same as each transistor MB1 to MB5 of the ninth embodiment. It is a surface channel type MOSFET. Therefore, the same effects as those of (9-3) and (9-4) of the ninth embodiment can be obtained.

According to this embodiment, the following effects can be obtained.
(10-1) The impurity concentration in the channel region of each transistor MB1 and MB3 in the current adjusting unit 120 and the impurity concentration in the channel region of each transistor M16 and M17 of the transistor of the constant current source 11 and the bias circuit 92 are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of each transistor MB1 and MB3, a step of forming the N-type well layer 63 of the transistor of the constant current source 11, and the steps M16 and M17 of the bias circuit 92, respectively. The step of forming the N-type well layer 63 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1G can be simplified.

(10-2) The impurity concentration in the channel region of each transistor MB2, MB4, MB5 in the current adjusting unit 120 and the impurity concentration in the channel region of each transistor M12, M13 of the cascode current mirror circuit 91 are equal to each other. According to this configuration, the step of forming the P-type well layer 41 of each of the transistors MB2, MB4 and MB5 and the step of forming the P-type well layer 41 of each of the transistors M12 and M13 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1G can be simplified.

(Variation example of the tenth embodiment)
The operational amplifier 1G of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the current adjusting unit 120 of the operational amplifier 1G, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the current flowing through the 10-transistor M10 and the 11th transistor M11 can be reduced.

-For each transistor M1, M2, M10, M11, M14, M15 in the operational amplifier 1G, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment. May be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of transistors M1 and M2 constituting the differential pair 10, a set of transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each transistor M14 constituting the current source of the bias circuit 92, Any one or two sets of M15 may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor M1, M2, M10, M11, M14, M15 in the operational amplifier 1G, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1, M2, M10, M11, M14, and M15 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, the set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1G, the pair of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and the current source of the bias circuit 92 are each configured. Any one or two sets of the transistors M14 and M15 may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. Further, each set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1G, the set of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each of the sets constituting the current source of the bias circuit 92. Even if any one or two sets of the transistors M14 and M15 are changed to the same structure as the embedded channel MOSFET of the second embodiment or the structures of the transistors M1 to M4 of the third embodiment. good. In short, the operational amplifier 1G has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(11th Embodiment)
The operational amplifier 1H of the eleventh embodiment will be described with reference to FIG. 27. The operational amplifier 1H of the present embodiment is different from the operational amplifier 1G of the tenth embodiment in that the amount of current of the current adjusting unit 120 is adjusted separately from the transistors M10 and M11 constituting the active load.

The current adjusting unit 120 includes an adjusting current source 125. The adjustment current source 125 adjusts the amount of current supplied to the differential pair 10 by the current supply unit 121 and the amount of current supplied to the second power supply wiring 3 by branching the current from the differential pair 10 by the branch unit 122. do. The regulated current source 125 is provided between the first power supply wiring 2 and the second power supply wiring 3, and includes a constant current source 126 and a transistor MB6.

The constant current source 126 is provided between the first power supply wiring 2 and the transistor MB6. The constant current source 126 includes a transistor. The transistor of this embodiment is a P-channel MOSFET.

The transistor MB6 is connected to the constant current source 126. The transistor of this embodiment is an N-channel MOSFET. The drain of the transistor MB6 is connected to the constant current source 126, the source of the transistor MB6 is connected to the second power supply wiring 3, and the gate of the transistor MB6 is connected to the drain of the transistor MB6.

In the present embodiment, the gate of the second supply transistor MB2 of the current supply unit 121 and the gates of the transistors MB4 and MB5 of the branch unit 122 are commonly connected to the gate of the transistor MB6. That is, each transistor MB2, MB4 to MB6 constitutes a current mirror circuit. Further, the gate voltage of each transistor MB2, MB4 to MB6 is controlled by the gate voltage of the transistor MB6.

Next, the current flowing through the operational amplifier 1H, particularly the current flowing through the current adjusting unit 120 will be described. In this description, the constant current flowing through the constant current source 11 is 2 ID.
In the operational amplifier 1H, the constant current 2 ID and the supply current IDB 3 are supplied to the differential pair 10 from the third supply transistor MB3. Also in this embodiment, since the current ratio between the first supply transistor MB1 and the third supply transistor MB3 is 1: 1, the supply current IDB3 is equal to the current IDB2. More specifically, the supply current IDB3 is a current proportional to the current IDB2 flowing through the second supply transistor MB2 by the current mirror circuit including the transistors MB1 and MB3. In the present embodiment, since the transistors MB4 and MB5 and the second supply transistor MB2 form a current mirror circuit, the current IDB2 flowing through the second supply transistor MB2 flows through the transistors MB4 and MB5. It is the total current (IDB4 + IDB5). Since the gate voltage of each of the transistors MB4 and MB5 is controlled by the gate voltage of the transistor MB6, the magnitude of the current IDB2 is proportional to the current IDB6 flowing through the transistor MB6.

In this case, the current IDx flowing through each of the transistors M1 and M2 is IDx = (2ID + IDB3) / 2 when the inputs of the constant current 2ID and the supply current IDB3 are in phase, that is, when the gate signal which is an input signal is in phase. It becomes. In this way, the current IDx flowing through each of the transistors M1 and M2 is larger than the current ID (constant current 2ID / 2) by 1/2 of the IDB3. On the other hand, the currents IDB4 and IDB5 are drawn from the drains of the transistors M1 and M2 by the 10th transistor M10 and the transistors MB4 and MB5 of the branch portion 122 constituting the current mirror circuit, respectively. As a result, the current ID 10 flowing through the 10th transistor M10 becomes IDx-IDB4, and the current ID 11 flowing through the 11th transistor M11 becomes IDx-IDB5. Therefore, each of the currents IDB4 and IDB5 of the present embodiment is 1/2 of the current IDB3. That is, the increased amount of the current flowing through the transistors M1 and M2 is passed through the transistors MB4 and MB5. As described above, the current adjusting unit 120 does not increase the current flowing through the transistors M10 and M11 even if the current flowing through the transistors M1 and M2 is increased. As a result, the transconductance gm of the transistors M1 and M2 of the differential pair 10 is increased, while the transconductance gm of the transistors M10 and M11 of the active load is not increased, so that the noise of the output signal Sout of the operational amplifier 1H can be reduced. ..

The transistors of the transistors M1, M2, M10 to M17 and the constant current source 11 are the same as the structures and manufacturing methods of the transistors of the transistors M1, M2, M10 to M17 and the constant current source 11 of the fourth embodiment. That is, the impurity concentration in the channel region of the transistors M1, M2, M10 to M17 and the constant current source 11 of the fourth embodiment is the channel region of the transistors M1, M2, M10 to M17 and the constant current source 11 of the fourth embodiment. It is the same as the impurity concentration of.

Further, the structure of each transistor MB1 to MB5 is the same as the structure of each transistor MB1 to MB5 of the ninth and tenth embodiments. That is, the impurity concentration in the channel region of each of the transistors MB1 to MB5 is the same as the impurity concentration of the channel region in each of the transistors MB1 to MB5 of the ninth and tenth embodiments. Therefore, the same effects as the effects of (9-3) and (9-4) of the ninth embodiment and the effects of (10-1) and (10-2) of the tenth embodiment can be obtained.

Further, the impurity concentration in the channel region of the transistor of the constant current source 126 and the transistor MB6 of the regulated current source 125 is the same as the impurity concentration of the channel region in each of the transistors MB1 to MB5. The transistor of the constant current source 126 and the transistor MB6 are surface channel type MOSFETs.

According to this embodiment, the following effects can be obtained.
(11-1) The current flowing from the differential pair 10 to the branch portion 122 by the regulated current source 125 becomes a current proportional to the current flowing from the constant current source 126 of the regulated current source 125 to the transistor MB6. Therefore, the current flowing from the differential pair 10 to the branch portion 122 can be set independently of the current supply portion 121 by the adjusting current source 125.

(11-2) The impurity concentration in the channel region of the transistor of the constant current source 126 and the transistor MB6 of the regulated current source 125 is higher than the impurity concentration of the channel region in each of the transistors M1 to M4, so that each of the transistors MB1 to MB5 has an impurity concentration. The variation in the threshold voltage can be suppressed, and the current adjusting unit 120 can operate stably.

(11-3) The impurity concentration in the channel region of the transistor of the constant current source 126 and the impurity concentration in the channel region of the transistors M16 and M17 of the transistor of the constant current source 11 and the bias circuit 92 are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the transistor of the constant current source 126, a step of forming the N-type well layer 63 of the transistor of the constant current source 11, and each transistor M16 of the bias circuit 92, The steps of forming the N-type well layer 63 of M17 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1H can be simplified.

(11-4) The impurity concentration in the channel region of the transistor MB6 and the impurity concentration in the channel region of each of the transistors M12 and M13 of the cascode current mirror circuit 91 are equal to each other. According to this configuration, the step of forming the P-type well layer 41 of each transistor MB6 and the step of forming the P-type well layer 41 of each of the transistors M12 and M13 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1H can be simplified.

(Modified example of the eleventh embodiment)
The operational amplifier 1H of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the current adjusting unit 120 of the operational amplifier 1H, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the current flowing through the 10-transistor M10 and the 11th transistor M11 can be reduced.

The operational amplifier 1H may have a current mirror circuit 12 instead of the cascode current mirror circuit 91 and the bias circuit 92.
-For each transistor M1, M2, M10, M11, M14, M15 in the operational amplifier 1H, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment. May be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of transistors M1 and M2 constituting the differential pair 10, a set of transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each transistor M14 constituting the current source of the bias circuit 92, Any one or two sets of M15 may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor M1, M2, M10, M11, M14, M15 in the operational amplifier 1H, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1, M2, M10, M11, M14, and M15 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, the set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1H, the pair of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and the current source of the bias circuit 92 are each configured. Any one or two sets of the transistors M14 and M15 may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. Further, each set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1H, the pair of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each of the sets constituting the current source of the bias circuit 92. Even if any one or two sets of the transistors M14 and M15 are changed to the same structure as the embedded channel MOSFET of the second embodiment or the structures of the transistors M1 to M4 of the third embodiment. good. In short, the operational amplifier 1H has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(12th Embodiment)
The operational amplifier 1I of the twelfth embodiment will be described with reference to FIG. 28. The operational amplifier 1I of the present embodiment has a configuration in which the current adjusting unit 120A, the output stage 93 of the fourth embodiment, and the capacitor 94 are added to the operational amplifier 1D of the seventh embodiment.

The current adjusting unit 120A has a point where the third resistor R3 is added to the current supply unit 121 as compared with the current adjusting unit 120 of the tenth embodiment, and the connection configuration of the first branch circuit 123 and the second branch circuit 124. Is different.

The third resistance R3 of the current supply unit 121 is provided between the second supply transistor MB2 and the second power supply wiring 3. The first terminal of the third resistance R3 is connected to the source of the second supply transistor MB2, and the second terminal of the third resistance R3 is connected to the second power supply wiring 3. The third resistance R3 raises the source potential of the second supply transistor MB2. The resistance value of the third resistor R3 is determined according to the ratio of the third transistor M3 and the fourth transistor M4 to the second supply transistor MB2. The resistance value of the third resistance R3 of the present embodiment is equal to the resistance values of the first resistance R1 and the second resistance R2.

The first branch circuit 123 is connected to the drain of the first transistor M1 and the node NC1 between the third transistor M3 and the first resistor R1. More specifically, the drain of the first branch transistor MB4 of the first branch circuit 123 is connected to the drain of the first transistor M1, and the source of the first branch transistor MB4 is connected to the node NC1.

The second branch circuit 124 is connected to the drain of the second transistor M2 and the node NC2 between the fourth transistor M4 and the second resistor R2. More specifically, the drain of the second branch transistor MB5 of the second branch circuit 124 is connected to the drain of the second transistor M2, and the source of the second branch transistor MB5 is connected to the node NC2.

Next, the current flowing through the operational amplifier 1I, particularly the current flowing through the current adjusting unit 120A will be described. In this description, the constant current flowing through the constant current source 11 is 2 ID. The sizes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3, ID4 are the same as the sizes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3, ID4 of the ninth embodiment. Therefore, the description thereof will be omitted.

As described in the ninth embodiment, the supply current IDB3 having the same amount of current as the current IDB2, which is the sum of the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5, is supplied to the differential pair 10. Therefore, the current supplied to the differential pair 10 is the sum of the supply current IDB3 and the constant current 2ID, so that the transconductance gm12 of each transistor M1 and M2 increases. On the other hand, since the currents IDB4 and IDB5 are extracted from the currents IDx flowing through the transistors M1 and M2 by the transistors MB4 and MB5, the increase in the transconductance gm34 of the transistors M3 and M4 is suppressed.

The current IDB4 flowing through the first branching transistor MB4 flows through the node NC1 between the third transistor M3 and the first resistor R1, and the current IDB5 flowing through the second branching transistor MB5 is the fourth transistor M4 and the first. It flows to the node NC2 between the two resistors R2. Therefore, the source potential of the third transistor M3 and the source potential of the fourth transistor M4 increase. In addition, as described in the seventh embodiment, the source potentials of the third transistor M3 and the fourth transistor M4 are increased by the first resistance R1 and the second resistance R2. As described above, in the present embodiment, the source potentials of the transistors M3 and M4 are further increased as compared with the seventh embodiment. Therefore, the transconductance gm34 on the circuit is reduced. In this way, by increasing the transconductance gm12 of each of the transistors M1 and M2 and decreasing the transconductance gm34 of each of the transistors M3 and M4, the noise of the output signal Sout of the operational amplifier 1I can be reduced.

Further, the transistors M1 to M4 of the operational amplifier 1I and the transistors of the constant current source 11 of the present embodiment have the same configuration and manufacturing method as the transistors of the transistors M1 to M4 and the constant current source 11 of the first embodiment. Therefore, as described in (1-5) and (1-6) of the first embodiment, 1 / f noise of the output signal Sout can be effectively reduced. Further, the transistors MB1 to MB5 of the current adjusting unit 120A of the present embodiment have the same configuration and manufacturing method as the transistors MB1 to MB5 of the current adjusting unit 120 of the ninth embodiment. That is, the impurity concentrations in the channel regions of the transistors MB1 to MB5 of the present embodiment are the same as the impurity concentrations in the channel regions of the transistors MB1 to MB5 of the ninth embodiment, and the impurity concentrations of the transistors MB1 to MB5 of the ninth embodiment are the same. Similar to MB5, it is a surface channel type MOSFET.

(Modified example of the twelfth embodiment)
The operational amplifier 1I of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the current adjusting unit 120A of the operational amplifier 1I, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the currents ID3 and ID4 flowing through the three transistors M3 and the fourth transistor M4 can be further reduced.

The resistance value of the first resistance R1, the resistance value of the second resistance R2, and the resistance value of the third resistance R3 depend on the ratio of the third transistor M3, the fourth transistor M4, and the second supply transistor MB2. You may change it.

-For each of the transistors M1 to M4 in the operational amplifier 1I, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, the second implementation is any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1I and the sets of the transistors M3 and M4 constituting the current mirror circuit 12. It may be changed to the embedded channel type MOSFET of the form.

-For each of the transistors M1 to M4 in the operational amplifier 1I, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, the third embodiment includes any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1I and the transistors M3 and M4 constituting the current mirror circuit 12. The structure may be changed to the same as the structure of each of the transistors M1 to M4. Further, one or two sets of one or two of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1I and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are secondly implemented. The structure may be changed to the same structure as that of the embedded channel MOSFET of the embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1I has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(13th Embodiment)
The operational amplifier 1J of the thirteenth embodiment will be described with reference to FIG. 29. The operational amplifier 1J of the present embodiment is different from the operational amplifier 1I of the twelfth embodiment mainly in that the current mirror circuit is changed to the cascode current mirror circuit and the bias circuit is added as an active load. Since the cascode current mirror circuit and the bias circuit of the present embodiment are the same as the cascode current mirror circuit 91 and the bias circuit 92 of the fourth embodiment, the same reference numerals are used and the description thereof will be omitted.

By changing the current mirror circuit 12 to the cascode current mirror circuit 91, the operational amplifier 1J has a connection configuration of the first resistor R1 and the second resistor R2, and the first branch circuit 123 and the first branch circuit 123 of the branch section 122 in the current adjusting section 120A. The connection configuration of the two-branch circuit 124 differs as follows.

The first resistance R1 is provided between the tenth transistor M10 and the second power supply wiring 3, and the second resistance R2 is provided between the eleventh transistor M11 and the second power supply wiring 3. More specifically, the first terminal of the first resistance R1 is connected to the source of the tenth transistor M10, and the second terminal of the first resistance R1 is connected to the second power supply wiring 3. The first terminal of the second resistance R2 is connected to the source of the eleventh transistor M11, and the second terminal of the second resistance R2 is connected to the second power supply wiring 3.

The first branch circuit 123 is connected to the drain of the first transistor M1 and the node ND1 between the tenth transistor M10 and the first resistor R1. More specifically, the drain of the first branch transistor MB4 of the first branch circuit 123 is connected to the drain of the first transistor M1, and the source of the first branch transistor MB4 is connected to the node ND1.

The second branch circuit 124 is connected to the drain of the second transistor M2 and the node ND2 between the eleventh transistor M11 and the second resistor R2. More specifically, the drain of the second branch transistor MB5 of the second branch circuit 124 is connected to the drain of the second transistor M2, and the source of the second branch transistor MB5 is connected to the node ND2.

The gates of the transistors MB4 and MB5 are commonly connected to the gate of the tenth transistor M10. Further, the gate of the second supply transistor MB2 of the current supply unit 121 of the current adjustment unit 120A is connected to the gate of the tenth transistor M10. As described above, each transistor MB2, MB4, MB5 constitutes a current mirror circuit with the tenth transistor M10. In this way, the gate voltage of each transistor MB2, MB4, MB5 is controlled by the gate voltage of the tenth transistor M10.

Next, the current flowing through the operational amplifier 1J, particularly the current flowing through the current adjusting unit 120A will be described. In this description, the constant current flowing through the constant current source 11 is 2 ID. The sizes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID10, ID11 are the same as the sizes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3, ID4 of the ninth embodiment. Therefore, the description thereof will be omitted.

As described in the ninth embodiment, the supply current IDB3 having the same amount of current as the current IDB2, which is the sum of the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5, is supplied to the differential pair 10. Therefore, the current supplied to the differential pair 10 is the sum of the supply current IDB3 and the constant current 2ID, so that the transconductance gm12 of each transistor M1 and M2 increases. On the other hand, since the currents IDB4 and IDB5 are extracted from the currents IDx flowing through the transistors M1 and M2 by the transistors MB4 and MB5, the increase in the transconductance gm34 of the transistors M10 and M11 is suppressed.

In addition, the current IDB4 flowing through the first branching transistor MB4 flows through the node ND1 between the tenth transistor M10 and the first resistor R1, and the current IDB5 flowing through the second branching transistor MB5 is the eleventh transistor. It flows to the node ND2 between M11 and the second resistor R2. Therefore, the source potential of the 10th transistor M10 and the source potential of the 11th transistor M11 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the tenth transistor M10 and the eleventh transistor M11. As described above, in the present embodiment, the source potentials of the transistors M10 and M11 are further increased as in the twelfth embodiment. Therefore, the transconductance gm on the circuit is reduced. In this way, by increasing the transconductance gm12 of each of the transistors M1 and M2 and decreasing the transconductance gm of each of the transistors M10 and M11, the noise of the output signal Sout of the operational amplifier 1J can be reduced.

Further, each transistor constituting the operational amplifier 1J is the same as the structure and manufacturing method of the transistor excluding the transistor of the back gate bias circuit 20 among the transistors constituting the operational amplifier 1A of the fourth embodiment. That is, the impurity concentration in the channel region of each of the transistors M1, M2, M10 to M17 is the same as the impurity concentration of the channel region in each of the transistors M1, M2, M10 to M17 of the fourth embodiment. Therefore, 1 / f noise of the output signal Sout can be effectively reduced. Further, the impurity concentration in the channel region of the transistor of the constant current source 11 and the transistors M12, M13, M16, and M17 is the same as that of the transistor of the constant current source 11 of the fourth embodiment and the transistors M12, M13, M16, and M17. It is the same as the impurity concentration in the channel region. Therefore, an effect similar to the effects of (4-1) to (4-3) of the fourth embodiment can be obtained.

Further, the structure of each transistor MB1 to MB5 is the same as the structure of each transistor MB1 to MB5 of the ninth and tenth embodiments. That is, the impurity concentration in the channel region of each of the transistors MB1 to MB5 is the same as the impurity concentration of the channel region in each of the transistors MB1 to MB5 of the ninth and tenth embodiments. Therefore, the same effects as the effects of (9-3) and (9-4) of the ninth embodiment and the effects of (10-1) and (10-2) of the tenth embodiment can be obtained.

(Modified example of the thirteenth embodiment)
The operational amplifier 1J of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the current adjusting unit 120A of the operational amplifier 1J, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the current flowing through the 10-transistor M10 and the 11th transistor M11 can be reduced.

The resistance value of the first resistance R1, the resistance value of the second resistance R2, and the resistance value of the third resistance R3 depend on the ratio of the tenth transistor M10, the eleventh transistor M11, and the second supply transistor MB2. You may change it.

-For each transistor M1, M2, M10, M11, M14, M15 in the operational amplifier 1J, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment. May be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of transistors M1 and M2 constituting the differential pair 10, a set of transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each transistor M14 constituting the current source of the bias circuit 92, Any one or two sets of M15 may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor M1, M2, M10, M11, M14, M15 in the operational amplifier 1J, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1, M2, M10, M11, M14, and M15 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, the set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1J, the pair of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and the current source of the bias circuit 92 are each configured. Any one or two sets of the transistors M14 and M15 may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. Further, each set of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1J, the pair of the transistors M10 and M11 constituting the current source of the cascode current mirror circuit 91, and each of the sets constituting the current source of the bias circuit 92. Even if any one or two sets of the transistors M14 and M15 are changed to the same structure as the embedded channel MOSFET of the second embodiment or the structures of the transistors M1 to M4 of the third embodiment. good. In short, the operational amplifier 1J has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(14th Embodiment)
The operational amplifier 1K of the 14th embodiment will be described with reference to FIG. 30. The operational amplifier 1K of the present embodiment is different from the operational amplifier 1I of the twelfth embodiment mainly in the control method of the source potentials of the third transistor M3 and the fourth transistor M4 as active loads and the configuration of the current adjusting unit. ..

In the operational amplifier 1K, the constant current source 11 includes the transistor MC1. The transistor MC1 of this embodiment is a P-channel MOSFET. The source of the transistor MC1 is connected to the first power supply wiring 2, the drain of the transistor MC1 is connected to the sources of the first transistor M1 and the second transistor M2, and the gate of the transistor MC1 is connected to the bias terminal BIAS.

The operational amplifier 1K further includes a current adjusting unit 120B having a configuration different from that of the current adjusting unit 120A (see FIG. 28) of the operational amplifier 1I of the twelfth embodiment, a current control unit 130, and an output stage 140. A capacitor 141 for phase compensation is connected to the output stage 140.

The current adjusting unit 120B is an operational amplifier in that the connection configuration of the first branch circuit 123 and the second branch circuit 124, and the addition of the fourth resistor R4 and the fifth resistor R5 to the first branch circuit 123 and the second branch circuit 124. It is different from the current adjusting unit 120A of 1I.

The first branch circuit 123 is connected to the drain of the first transistor M1 and the second power supply wiring 3, and includes the first branch transistor MB4 and the fourth resistor R4. The first branch transistor MB4 and the fourth resistor R4 form a series circuit. The drain of the first branching transistor MB4 is connected to the drain of the first transistor M1, and the source of the first branching transistor MB4 is connected to the first terminal of the fourth resistance R4. The second terminal of the fourth resistance R4 is connected to the second power supply wiring 3. The resistance value of the fourth resistor R4 of the present embodiment is equal to the resistance values of the first resistor R1 and the second resistor R2.

The second branch circuit 124 is connected to the drain of the second transistor M2 and the second power supply wiring 3, and includes the second branch transistor MB5 and the fifth resistance R5. The second branch transistor MB5 and the fifth resistor R5 form a series circuit. The drain of the second branching transistor MB5 is connected to the drain of the second transistor M2, and the source of the second branching transistor MB5 is connected to the first terminal of the fifth resistance R5. The second terminal of the fifth resistance R5 is connected to the second power supply wiring 3. The resistance value of the fifth resistor R5 of the present embodiment is equal to the resistance value of the fourth resistor R4. That is, the resistance value of the fifth resistance R5 is equal to the resistance values of the first resistance R1 and the second resistance R2.

The current control unit 130 supplies current to each of the node NE1 between the source of the third transistor M3 and the first resistor R1 and the node NE2 between the source of the fourth transistor M4 and the second resistor R2. , The source potential of the third transistor M3 and the fourth transistor M4 is raised. The current control unit 130 includes a first control unit 131 that controls the source potential of the third transistor M3, and a second control unit 132 that controls the source potential of the fourth transistor M4.

The first control unit 131 is a series circuit provided between the first power supply wiring 2 and the node NE1 and composed of the transistor MC2 and the transistor MC3. In this embodiment, the transistor MC2 is a P-channel MOSFET and the transistor MC3 is an N-channel MOSFET. The transistor MC2 is provided between the first power supply wiring 2 and the transistor MC3. The source of the transistor MC2 is connected to the first power supply wiring 2, the drain of the transistor MC2 is connected to the drain of the transistor MC3, the gate of the transistor MC2 is commonly connected to the gate of the transistor MC1, and is connected to the bias terminal BIAS. There is. The source of the transistor MC3 is connected to the node NE1.

The second control unit 132 is provided between the first power supply wiring 2 and the node NE2, and is a series circuit including the transistor MC4 and the transistor MC5. In this embodiment, the transistor MC4 is a P-channel MOSFET and the transistor MC5 is an N-channel MOSFET. The transistor MC4 is provided between the first power supply wiring 2 and the transistor MC5. The source of the transistor MC4 is connected to the first power supply wiring 2, the drain of the transistor MC4 is connected to the drain of the transistor MC5, the gate of the transistor MC4 is connected to the gate of the transistor MC1, and it is connected to the bias terminal BIAS. The source of the transistor MC5 is connected to the node NE2. The gate of the transistor MC5 is connected to the gate of the transistor MC3 and is connected to the gate of the third transistor M3 of the current mirror circuit 12. That is, each of the transistors MC3 and MC5 constitutes a current mirror circuit with the third transistor M3, similarly to the transistors MB2, MB4 and MB5.

The output stage 140 is a grounded-source circuit, and is a series circuit including the transistor MC6 and the transistor MC7. In this embodiment, the transistor MC6 is a P-channel MOSFET and the transistor MC7 is an N-channel MOSFET. The transistor MC6 is provided between the first power supply wiring 2 and the transistor MC7. The source of the transistor MC6 is connected to the first power supply wiring 2, the drain of the transistor MC6 is connected to the drain of the transistor MC7, the gate of the transistor MC6 is connected in common with the gate of the transistor MC1, and is connected to the bias terminal BIAS. There is. The source of the transistor MC7 is connected to the second power supply wiring 3, and the gate of the transistor MC7 is connected to the node NE3 between the drain of the second transistor M2 and the drain of the fourth transistor M4. Further, an output terminal OUT is connected to the node NE4 between the drain of the transistor MC6 and the drain of the transistor MC7.

Next, the current flowing through the operational amplifier 1K, particularly the current flowing through the current adjusting unit 120B and the current control unit 130 will be described. In this description, the constant current flowing through the constant current source 11 is 2 ID. Regarding the magnitudes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3, ID4 in the current adjustment unit 120B, the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3, ID4 of the ninth embodiment. Since it is the same as the size of, the description thereof will be omitted.

As described in the ninth embodiment, the supply current IDB3 having the same amount of current as the current IDB2, which is the sum of the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5, is supplied to the differential pair 10. Therefore, the current supplied to the differential pair 10 is the sum of the supply current IDB3 and the constant current 2ID, so that the transconductance gm12 of each transistor M1 and M2 increases. On the other hand, since the currents IDB4 and IDB5 are extracted from the currents IDx flowing through the transistors M1 and M2 by the transistors MB4 and MB5, the increase in the transconductance gm34 of the transistors M3 and M4 is suppressed.

When the transistor MC3 and the transistor MC5 of the current control unit 130 form a current mirror circuit with the third transistor M3 of the active load, a current IDC3 proportional to the current ID3 flowing through the third transistor M3 flows through the transistor MC3, and the transistor MC5 A current IDC5 proportional to the current ID3 flows through the current. The current IDC3 flows to the node NE1 between the third transistor M3 and the first resistance R1, and the current IDC5 flows to the node NE2 between the fourth transistor M4 and the second resistance R2. As a result, the source potential of each transistor M3 and M4 rises. Therefore, the transconductance gm34 on the circuit is further reduced.

Further, since the transistors M1 to M4 of the present embodiment and the transistors MC1 of the constant current source 11 have the same configuration and manufacturing method as the transistors M1 to M4 and the constant current source 11 of the first embodiment, the first embodiment is performed. As described in the embodiments (1-5) and (1-6), the 1 / f noise of the output signal Sout can be effectively reduced.

Further, the structure of the transistors MB1 to MB5 of the present embodiment is the same as the structure of the transistors MB1 to MB5 of the ninth embodiment. That is, the impurity concentration in the channel region of each of the transistors MB1 to MB5 is the same as the impurity concentration of the channel region in each of the transistors MB1 to MB5 of the ninth embodiment. Therefore, the same effects as (9-3) and (9-4) of the ninth embodiment can be obtained.

Further, since the transistors MC1 of the constant current source 11, the transistors MC2 to MC5 of the current control unit 130, and the transistors MC6 and MC7 of the output stage 140 are not easily affected by the 1 / f noise of the output signal Sout, each of the transistors MC1 to MC1 to The impurity concentration in the channel region in MC7 is made higher than the impurity concentration in the channel region in each of the transistors M1 to M4. In other words, the impurity concentration in the channel region of each of the transistors M1 to M4 is lower than the impurity concentration of the channel region of each of the transistors MC1 to MC7. That is, each transistor MC1 to MC7 is a high-concentration transistor. The impurity concentration in the channel region of each of the transistors M1 to M4 is preferably about 1/2 or less of the impurity concentration of the channel region of each of the transistors MC1 to MC7. In the present embodiment, the impurity concentration in the channel region of each of the transistors M1 to M4 is about 1/10 of the impurity concentration of the channel region of each of the transistors MC1 to MC7. In the present embodiment, the impurity concentration in the channel region of each of the transistors MC1 to MC7 is substantially equal to the impurity concentration of the channel region of each of the transistors MB1 to MB5. Further, each of the transistors MC1 to MC7 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(14-1) Impurity concentration in the channel region of the transistor MC1 of the constant current source 11, impurity concentration in the channel region of each transistor MC2, MC4, MC6 of the current control unit 130, and each transistor MB1, MB3 of the current adjustment unit 120B. The impurity concentrations in the channel regions of are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the transistor MC1, a step of forming the N-type well layer 63 of each transistor MC2, MC4, MC6, and a step of forming the N-type well layer 63 of each transistor MB1, MB3. Can be performed collectively with the process of forming. Therefore, the process of manufacturing the operational amplifier 1K can be simplified.

(14-2) The impurity concentration in the channel region of each of the transistors MC3 and MC5 of the current control unit 130 and the impurity concentration in the channel region of the second supply transistor MB2 of the current adjustment unit 120B are equal to each other. According to this configuration, the step of forming the P-type well layer 41 of each of the transistors MC3 and MC5 and the step of forming the P-type well layer 41 of the second supply transistor MB2 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1K can be simplified.

(Modified example of the 14th embodiment)
The operational amplifier 1K of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the current adjusting unit 120B of the operational amplifier 1K, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the currents ID3 and ID4 flowing through the three transistors M3 and the fourth transistor M4 can be further reduced.

The resistance value of the first resistance R1, the resistance value of the second resistance R2, the resistance value of the third resistance R3, the resistance value of the fourth resistance R4, and the resistance value of the fifth resistance R5 are the third transistors M3 and the fourth. It may be changed according to the ratio of the transistor M4, the second supply transistor MB2, the first branch transistor MB4, and the second branch transistor MB5.

-For each of the transistors M1 to M4 in the operational amplifier 1K, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, the second implementation is any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1K and the sets of the transistors M3 and M4 constituting the current mirror circuit 12. It may be changed to the embedded channel type MOSFET of the form.

-For each of the transistors M1 to M4 in the operational amplifier 1K, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, in the third embodiment, any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1K and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are used. The structure may be changed to the same as the structure of each of the transistors M1 to M4. Further, one or two sets of one or two of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1K and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are secondly implemented. The structure may be changed to the same structure as that of the embedded channel MOSFET of the embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1K has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(15th Embodiment)
The operational amplifier 1L of the fifteenth embodiment will be described with reference to FIG. 31.
The operational amplifier 1L amplifies the potential difference between the inverting input terminal INN and the non-inverting input terminal INP, and outputs the output signal Sout from the output terminal OUT. The operational amplifier 1L includes a differential amplification stage 150, an output stage 155, a backgate bias circuit 20, and a correction circuit 156, and is integrally integrated on one semiconductor substrate.

The differential amplification stage 150 includes a differential pair 151, a constant current source 152, a phase compensation circuit 153, and a constant current circuit 154.
The differential pair 151 has a first transistor MD1 and a second transistor MD2. In this embodiment, the first transistor MD1 and the second transistor MD2 are P-channel MOSFETs. The first transistor MD1 and the second transistor MD2 may have either a depletion type structure or an enhancement type structure. In the present embodiment, the first transistor MD1 and the second transistor MD2 have an enhancement type structure. The gate of the first transistor MD1 is connected to the inverting input terminal INN, and the gate of the second transistor MD2 is connected to the non-inverting input terminal INP. The differential pair 151 generates differential currents Imb1 and Imb2 corresponding to the input voltages Vinn and Vinp of the inverting input terminal INN and the non-inverting input terminal INP, respectively.

The constant current source 152 supplies the constant current It to the differential pair 151. The constant current source 152 has a third transistor MD3 which is a P-channel MOSFET. The gate of the third transistor MD3 is connected to the first bias terminal BIAS1. The source of the third transistor MD3 is connected to the first power supply wiring 2. The drain of the third transistor MD3 is connected to the phase compensation circuit 153.

The phase compensation circuit 153 is provided between the differential pair 151 and the constant current source 152. The phase compensation circuit 153 includes a first compensation resistor RD1, a second compensation resistor RD2, and a compensation capacitor CD1. The first compensation resistor RD1 is provided between the source of the first transistor MD1 and the constant current source 152, and the second compensation resistor RD2 is provided between the source of the second transistor MD2 and the constant current source 152. There is. The compensation capacitor CD1 is connected between the source of the first transistor MD1 and the source of the second transistor MD2.

The constant current circuit 154 is connected to the drain of the first transistor MD1 and the drain of the second transistor MD2 to generate constant currents Imb4 and Imb5. The constant current circuit 154 has a fourth transistor MD4 and a fifth transistor MD5. In this embodiment, the fourth transistor MD4 and the fifth transistor MD5 are N-channel MOSFETs. In particular, the fourth transistor MD4 and the fifth transistor MD5 have an enhancement type structure. The gate of the 4th transistor MD4 and the gate of the 5th transistor MD5 are commonly connected. The drain of the fourth transistor MD4 is connected to the drain of the first transistor MD1, and the source of the fourth transistor MD4 is connected to the second power supply wiring 3. The drain of the fifth transistor MD5 is connected to the drain of the second transistor MD2, and the source of the fifth transistor MD5 is connected to the second power supply wiring 3. The fourth transistor MD4 and the fifth transistor MD5 are biased by a voltage corresponding to the voltage Vbias1 of the first bias terminal BIAS1 so that the currents Imb4 and Imb5 proportional to the constant current It generated by the constant current source 152 flow.

As a specific configuration, the operational amplifier 1L has an 11th transistor MD11 and a 12th transistor MD12. The twelfth transistor MD12 is a P-channel MOSFET, and the eleventh transistor MD11 is an N-channel MOSFET. The source of the twelfth transistor MD12 is connected to the first power supply wiring 2, and the drain of the twelfth transistor MD12 is connected to the drain of the eleventh transistor MD11. The gate of the twelfth transistor MD12 is connected to the first bias terminal BIAS1. The source of the 11th transistor MD11 is connected to the second power supply wiring 3, the gate of the 11th transistor MD11 is connected to the gates of the 4th transistor MD4 and the 5th transistor MD5, and the gate of the 11th transistor MD11 is connected to the drain of the 11th transistor MD11. There is. That is, the 11th transistor MD11 forms a current mirror circuit together with the 4th transistor MD4 and the 5th transistor MD5. Since the current Imb12 proportional to the constant current It flows in the 12th transistor MD12, the currents Imb4 and Imb5 flowing in the 4th transistor MD4 and the 5th transistor MD5 forming the current mirror circuit together with the 11th transistor MD11 are constant current It. Is in proportion to.

The output stage 155 is connected to the drain of the first transistor MD1 and the drain of the second transistor MD2 to generate an output signal Sout. The output stage 155 has four transistors, a sixth transistor MD6 to a ninth transistor MD9. In the present embodiment, the 6th transistor MD6 and the 7th transistor MD7 are N-channel MOSFETs, and the 8th transistor MD8 and the 9th transistor MD9 are P-channel MOSFETs. In particular, the 8th transistor MD8 and the 9th transistor MD9 have an enhancement type structure.

The gates of the sixth transistor MD6 and the seventh transistor MD7 are connected to the second bias terminal BIAS2, and a predetermined bias voltage Vbias2 is applied. The source of the sixth transistor MD6 is connected to the drain of the first transistor MD1, and the source of the seventh transistor MD7 is connected to the drain of the second transistor MD2. The drain of the 6th transistor MD6 is connected to the drain of the 8th transistor MD8, and the drain of the 7th transistor MD7 is connected to the drain of the 9th transistor MD9. Further, the drain of the sixth transistor MD6 is connected to the output terminal OUT.

The eighth transistor MD8 and the ninth transistor MD9 form a current mirror circuit. Specifically, the gate of the 8th transistor MD8 and the gate of the 9th transistor MD9 are connected in common, and the gate of the 9th transistor MD9 is connected to the drain of the 9th transistor MD9. The source of the eighth transistor MD8 and the source of the ninth transistor MD9 are connected to the first power supply wiring 2.

The correction circuit 156 corrects the current flowing through the constant current circuit 154 based on the source voltage Vs1 of the first transistor MD1 and the source voltage Vs2 of the second transistor MD2. The two outputs of the correction circuit 156 are connected to the drain of the first transistor MD1 and the drain of the second transistor MD2, and the difference according to the potential difference between the source voltage Vs1 of the first transistor MD1 and the source voltage Vs2 of the second transistor MD2. Dynamic correction currents Icmp1 and Icmp2 are generated.

The correction circuit 156 has a correction differential pair 157 and a correction current source 158.
The correction differential pair 157 includes a PNP type first correction transistor Q1 and a second correction transistor Q2. The PNP type bipolar transistor has the same polarity as the P channel MOSFET of the differential pair 151. The source voltage Vs1 of the first transistor MD1 is input to the base of the first correction transistor Q1, and the source voltage Vs2 of the second transistor MD2 is input to the base of the second correction transistor Q2. The collector of the first correction transistor Q1 is connected to the drain of the first transistor MD1, and the collector of the second correction transistor Q2 is connected to the drain of the second transistor MD2. The emitters of the first correction transistor Q1 and the second correction transistor Q2 are connected to the correction current source 158.

The correction current source 158 has a tenth transistor MD10 which is a P-channel MOSFET. The source of the tenth transistor MD10 is connected to the first power supply wiring 2, and the drain of the tenth transistor MD10 is connected to the correction differential pair 157. The gate of the tenth transistor MD10 is connected to the first bias terminal BIAS1. Therefore, the constant current I2 generated by the correction current source 158 is proportional to the constant current It of the constant current source 152.

Next, the operation of the operational amplifier 1L will be described.
It is assumed that a mismatch occurs between the resistance value of the first compensation resistor RD1 and the resistance value of the second compensation resistor RD2, and RD1 = R and RD2 = R + ΔR. In this case, the differential current Imb1 of the first transistor MD1 increases by ΔI (Imb1 = I / 2 + ΔI), and the differential current Imb2 of the second transistor MD2 decreases by ΔI (Imb2 = I / 2-ΔI). Therefore, when the source voltage Vs2 of the second transistor MD2 becomes lower than the source voltage Vs1 of the first transistor MD1, the correction current Icmp2 flowing through the second correction transistor Q2 of the correction differential pair 157 increases (Icmp2 = I2). / 2 + ΔI'), the correction current Icmp1 flowing through the first correction transistor Q1 decreases (Icmp1 = I2 / 2-ΔI').

The correction current of the correction circuit 156 is superimposed on the differential current flowing from the differential pair 151 into the constant current circuit 154. Therefore, the corrected differential currents are Imb1 + Icmp1 and Imb2 + Icmp2. That is, the increase ΔI of the current Imb1 of the first transistor MD1 cancels out the decrease ΔI ′ of the current Icmp1 of the first correction transistor Q1, and the decrease ΔI of the current Imb2 of the second transistor MD2 cancels out the decrease ΔI of the second correction transistor Q2. It cancels out with the increase ΔI'of the current Icmp2. As described above, the correction circuit 156 directly corrects the difference between the source voltages Vs1 and Vs2 caused by the mismatch between the first compensation resistor RD1 and the second compensation resistor RD2, in other words, the input offset voltage Vos of the operational amplifier 1L. Feedback is applied so that the drain currents Imb1 + Icmp1, Imb2 + Icmp2 that are converted into the currents Icmp1 and Icmp2 and flow into the constant current circuit 154 become constant.

The backgate bias circuit 20 is connected to the common backgate of the first transistor MD1 and the second transistor MD2 and the first power supply wiring 2. The backgate bias circuit 20 is connected to the backgate of the first transistor MD1 and the second transistor MD2 via the third bias terminal BIAS3. The configuration of the backgate bias circuit 20 is the same as the configuration of the backgate bias circuit 20 of the first embodiment (see FIG. 2). The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor MD1 and the second transistor MD2 so that the bias voltage VB is closer to the first power supply voltage VDD than the source potential of the first transistor MD1 and the second transistor MD2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the voltage is on the first power supply voltage VDD side of the intermediate voltage between the source potential of the first transistor MD1 and the second transistor MD2 and the first power supply voltage VDD. VB is applied to the back gates of the first transistor MD1 and the second transistor MD2. That is, the backgate bias circuit 20 applies a bias voltage VB to the first transistor MD1 and the second transistor MD2 so that the backgate source voltage VBS becomes large. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be higher than the first power supply voltage VDD. In this case, the bias voltage VB is preferably higher than the first power supply voltage VDD within a range in which the parasitic diodes of the first transistor MD1 and the second transistor MD2 are not turned on. That is, the bias voltage VB is preferably less than the voltage at which the parasitic diodes of the first transistor MD1 and the second transistor MD2 are turned on. An example of the voltage at which the parasitic diode of the first transistor MD1 and the second transistor MD2 is turned on is a voltage (VDD + 0.5 to 0.6) higher than the first power supply voltage VDD by 0.5 to 0.6 V. The bias voltage VB is preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within a predetermined range including the first power supply voltage VDD. More specifically, the bias voltage VB is more preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within ± 20% of the first power supply voltage VDD. As a result, the backgate-source voltage VBS becomes a voltage excluding the backgate-source voltage VBSH among the voltages within ± 20% of the backgate-source voltage VBSH.

Further, in the present embodiment, in order to further reduce the 1 / f noise of the output signal Sout of the output stage 155, the impurity concentration in the channel region in some of the plurality of transistors of the operational amplifier 1L is set in other transistors. It is lower than the impurity concentration in the channel region. That is, the plurality of transistors of the operational amplifier 1L include a high-concentration transistor in which the impurity concentration in the channel region is the first concentration and a low-concentration transistor in which the impurity concentration in the channel region is a second concentration lower than the first concentration. Specifically, the impurity concentration in the channel region of the transistor that is easily affected by the 1 / f noise of the output signal Sout is lower than the impurity concentration in the channel region of the transistor that is not easily affected by the 1 / f noise of the output signal Sout. is doing. That is, a low-concentration transistor is used as a transistor that is more susceptible to 1 / f noise of the output signal Sout among a plurality of transistors than a high-concentration transistor, and a high-concentration transistor is a plurality of transistors rather than a low-concentration transistor. Of these, it is used for transistors that are not easily affected by 1 / f noise of the operational amplifier 1L. Specifically, in the operational amplifier 1L, the portion susceptible to 1 / f noise of the output signal Sout is a part of the differential pair 151, the constant current circuit 154, and the output stage 155, and 1 / f of the output signal Sout. The parts that are not easily affected by noise are the constant current source 152, the other part of the output stage 155, the correction circuit 156, and the back gate bias circuit 20.

In the present embodiment, the impurity concentration in the channel region in some transistors of the differential pair 151, the constant current circuit 154, and the output stage 155 is set to the constant current source 152, the back gate bias circuit 20, and the other one of the output stage 155. The concentration is lower than the impurity concentration in the channel region of the transistor and the transistor of the correction circuit 156. That is, the transistors constituting a part of the differential pair 151, the constant current circuit 154, and the output stage 155 are low-concentration transistors, and are other parts of the constant current source 152, the backgate bias circuit 20, and the output stage 155. , And the transistor constituting the correction circuit 156 is a high-concentration transistor. Specifically, the impurity concentration in the channel region of the first transistor MD1, the second transistor MD2, the fourth transistor MD4, the fifth transistor MD5, the eighth transistor MD8, the ninth transistor MD9, and the eleventh transistor MD11 is backgated. More than the impurity concentration in the channel region of the transistors M5 to M9 of the bias circuit 20, the transistors of the constant current source 21, the third transistor MD3, the sixth transistor MD6, the seventh transistor MD7, the tenth transistor MD10, and the twelfth transistor MD12. It is low. That is, the first transistor MD1, the second transistor MD2, the fourth transistor MD4, the fifth transistor MD5, the eighth transistor MD8, the ninth transistor MD9, and the eleventh transistor MD11 are low-concentration transistors, and the backgate bias circuit 20 . The transistors M5 to M9 and the transistors of the constant current source 21, the third transistor MD3, the sixth transistor MD6, the seventh transistor MD7, the tenth transistor MD10, and the twelfth transistor MD12 are high-concentration transistors.

The impurity concentration in the channel region of each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 is the impurity concentration in the channel region of each transistor M5 to M9, MD3, MD6, MD7, MD10, MD12 and the constant current source 21. It is preferably about 1/2 or less of the concentration. In the present embodiment, the impurity concentration in the channel region of each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 is the transistor of each transistor M5 to M9, MD3, MD6, MD7, MD10, MD12 and the constant current source 21. It is about 1/10 of the impurity concentration in the channel region in.

The structures and manufacturing methods of the N-channel MOSFETs and P-channel MOSFETs of the transistors MD1 to MD12 are the same as those of the N-channel MOSFETs and P-channel MOSFETs such as the first transistor M1 of the first embodiment.

According to this embodiment, the following effects can be obtained.
(15-1) The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor MD1 and the second transistor MD2 (the backgate in the N-type well layer 39 of the first transistor MD1 and the second transistor MD2). A bias voltage VB closer to the first power supply voltage VDD than the source potential of the first transistor MD1 and the second transistor MD2 is applied to the contact region). As a result, the backgate-source voltage VBS of the first transistor MD1 and the second transistor MD2 becomes large, so that the transconductance gm12 of the first transistor MD1 and the second transistor MD2 becomes large. Therefore, the noise of the output signal Sout of the operational amplifier 1L can be reduced.

(15-2) In the back gate bias circuit 20, by making the bias voltage VB larger than the first power supply voltage VDD, the transconductance gm12 of the first transistor MD1 and the second transistor MD2 becomes larger, so that the operational amplifier 1L The noise of the output signal Sout can be further reduced.

(15-3) By setting the bias voltage VB to a voltage lower than the voltage at which the parasitic diodes of the first transistor MD1 and the second transistor MD2 are turned on, the first transistor MD1 and the second transistor MD2 can operate stably.

(15-4) By setting the bias voltage VB to a voltage other than the same voltage as the first power supply voltage VDD within a predetermined range including the first power supply voltage VDD, the backgate-source voltage VBS becomes large. Therefore, the transconductance gm12 of the first transistor MD1 and the second transistor MD2 becomes large, and the first transistor MD1 and the second transistor MD2 can operate stably. In particular, by setting the bias voltage VB to a voltage other than the voltage within ± 20% of the first power supply voltage VDD, which is the same as the first power supply voltage VDD, the backgate source voltage VBS becomes the backgate source. Since the inter-voltage voltage is near VBSH, the transconductance gm12 of the first transistor MD1 and the second transistor MD2 becomes large, and the first transistor MD1 and the second transistor MD2 can operate more stably.

(15-5) The operational amplifier 1L has a correction circuit 156. According to this configuration, since the correction current flows in the differential current flowing from the differential pair 151 to the constant current circuit 154 by the correction circuit 156, the mismatch between the first compensation resistor RD1 and the second compensation resistor RD2 for phase compensation The input offset voltage Vos of the operational amplifier 1L due to the above can be reduced.

(15-6) The impurity concentration in the channel region of the first transistor MD1 and the second transistor MD2 constituting the differential pair 151 is the impurity concentration in the channel region of the sixth transistor MD6 and the plurality of transistors of the backgate bias circuit 20. It is lower than the impurity concentration in the channel region. According to this configuration, the mobility fluctuates by lowering the impurity concentration in the channel region of each transistor MD1 and MD2 constituting the differential pair 151 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1L. Can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1L can be effectively suppressed.

(15-7) The impurity concentration in the channel region of the fourth transistor MD4 and the fifth transistor MD5 constituting the current source of the constant current circuit 154 and the impurity concentration in the channel region of the eleventh transistor MD11 are the channels of the sixth transistor MD6. It is lower than the impurity concentration in the region and the impurity concentration in the channel region in the plurality of transistors of the backgate bias circuit 20. According to this configuration, the impurity concentration in the channel region of each transistor MD4 and MD5 constituting the current source of the constant current circuit 154 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1L and the channel of the eleventh transistor MD11. By lowering the impurity concentration in the region, fluctuations in mobility can be suppressed and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1L can be effectively suppressed.

(15-8) The impurity concentration in the channel region of the 8th transistor MD8 and the 9th transistor MD9 constituting the current mirror circuit is the impurity concentration in the channel region of the 6th transistor MD6 and the channels in the plurality of transistors of the backgate bias circuit 20. It is lower than the impurity concentration in the region. According to this configuration, the fluctuation of mobility can be suppressed by lowering the impurity concentration of each transistor MD8 and MD9 of the current mirror circuit which is easily affected by 1 / f noise of the output signal Sout of the operational amplifier 1L, and the drain current can be suppressed. Fluctuation can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1L can be effectively suppressed.

(15-9) Impurity concentration in the channel region of the first transistor MD1 and the second transistor MD2 constituting the differential pair 151, and the impurity concentration in the channel region of the eighth transistor MD8 and the ninth transistor MD9 constituting the current mirror circuit. Are equal to each other. According to this configuration, the step of forming the N-type well layer 70 of each transistor MD1 and MD2 and the step of forming the N-type well layer 70 of each transistor MD8 and MD9 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1L can be simplified.

(15-10) Impurity concentration in the channel region of the third transistor MD3 in the constant current source 152, impurity concentration in the channel region of the tenth transistor MD10 in the correction current source 158, and impurity concentration in the channel region of the twelfth transistor MD12. , The impurity concentrations in the channel regions of the transistors M5, M8, and M9 in the backgate bias circuit 20 are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the third transistor MD3, a step of forming the N-type well layer 63 of the tenth transistor MD10, and a step of forming the N-type well layer 63 of the twelfth transistor MD12 are formed. The step of forming the N-type well layer 63 of each of the transistors M6 and M7 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1L can be simplified.

(15-11) Impurity concentration in the channel region of the 6th transistor MD6 and 7th transistor MD7 in the output stage 155, and the impurity concentration in the channel region of each transistor M6, M7 and the constant current source 21 in the backgate bias circuit 20. Are equal to each other. According to this configuration, the steps of forming the P-type well layer 41 of the transistors MD6 and MD7 and the steps of forming the P-type well layer 41 of the transistors M6 and M7 and the constant current source 21 are collectively performed. be able to. Therefore, the process of manufacturing the operational amplifier 1L can be simplified.

(Variation example of the fifteenth embodiment)
The operational amplifier 1L of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the operational amplifier 1L, the step-down circuit 100 of the fifth embodiment is added between the first power supply wiring 2 and the differential pair 151, more specifically between the first power supply wiring 2 and the constant current source 152. You can also do it. According to this configuration, the same effect as that of the fifth embodiment can be obtained. Further, the back gate bias circuit 20 can also be connected to the third power supply wiring 4 like the back gate bias circuit 20 of the sixth embodiment. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

The operational amplifier 1L shown in FIG. 31 can be changed like the operational amplifier 1L shown in FIG. 32. The operational amplifier 1L of FIG. 32 is different from the operational amplifier 1L of FIG. 31 mainly in the conductive type of the channel region in the MOSFET of the differential amplification stage 150 and the output stage 155. In FIG. 32, the correction circuit 156 is shown in a simplified manner for convenience of explanation.

As shown in FIG. 32, the first transistor MD1 and the second transistor MD2 of the differential pair 151 and the third transistor MD3 of the constant current source 152 are N-channel MOSFETs, and the fourth transistor MD4 and the fifth transistor MD4 of the constant current circuit 154. The transistor MD5 is a P-channel MOSFET. The sixth transistor MD6 and the seventh transistor MD7 of the output stage 155 are P-channel MOSFETs, and the eighth transistor MD8 and the ninth transistor MD9 are N-channel MOSFETs. The eleventh transistor MD11 is a P-channel MOSFET, and the twelfth transistor MD12 is an N-channel MOSFET.

The drain of the first transistor MD1 is connected to the drain of the fourth transistor MD4, and the drain of the second transistor MD2 is connected to the drain of the fifth transistor MD5. The source of the first transistor MD1 is connected to the first compensating resistor RD1, and the source of the second transistor MD2 is connected to the second compensating resistor RD2. The drain of the third transistor MD3 is connected to the first compensating resistor RD1 and the second compensating resistor RD2, and the source of the third transistor MD3 is connected to the second power supply wiring 3. The sources of the fourth transistor MD4, the fifth transistor MD5, and the eleventh transistor MD11 are connected to the first power supply wiring 2. The sources of the eighth transistor MD8, the ninth transistor MD9, and the twelfth transistor MD12 are connected to the second power supply wiring 3. The drain of the 8th transistor MD8 is connected to the drain of the 6th transistor MD6, the drain of the 9th transistor MD9 is connected to the drain of the 7th transistor MD7, and the drain of the 12th transistor MD12 is connected to the drain of the 11th transistor MD11. ing.

The backgate bias circuit 20 is connected to the common backgate of the first transistor MD1 and the second transistor MD2 and the second power supply wiring 3. The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor MD1 and the second transistor MD2 so that the bias voltage VB is closer to the second power supply voltage VSS than the source potential of the first transistor MD1 and the second transistor MD2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the source potential of the first transistor MD1 and the second transistor MD2 is a voltage on the second power supply voltage VSS side of the intermediate voltage between the second power supply voltage VSS. VB is applied to the back gates of the first transistor MD1 and the second transistor MD2. That is, the backgate bias circuit 20 applies a bias voltage VB so that the backgate-source voltage VBS becomes large to the backgate of the first transistor MD1 and the second transistor MD2. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be lower than the second power supply voltage VSS. The bias voltage VB is preferably a voltage excluding the voltage within a predetermined range including the second power supply voltage VSS, which is the same as the second power supply voltage VSS. In one example, the bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS among the voltages within ± 20% of the second power supply voltage VSS. According to this configuration, since the transconductance gm12 of the first transistor MD1 and the second transistor MD2 becomes large, the noise of the output signal Sout of the operational amplifier 1 can be reduced. Even in such an operational amplifier 1L of FIG. 32, the same effect as that of the operational amplifier 1L of the present embodiment can be obtained.

-In the operational amplifier 1L of FIG. 32, the booster circuit 103 of the operational amplifier 1B of FIG. 18 can be added. According to this configuration, the same effect as that of the operational amplifier 1B of FIG. 18 can be obtained. Further, the back gate bias circuit 20 of the operational amplifier 1L of FIG. 32 can also be connected to the fourth power supply wiring 5 as in the operational amplifier 1C of FIG. According to this configuration, the same effect as that of the operational amplifier 1C of FIG. 20 can be obtained.

In the operational amplifier 1L of FIGS. 31 and 32, for each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11, instead of lowering the impurity concentration in the channel region, each transistor M1 to M4 of the second embodiment. An embedded channel type MOSFET such as the above may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, in the operational amplifier 1L of FIGS. 31 and 32, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and each transistor MD4 constituting the current mirror circuit. , MD5, MD11 may be changed to any one or two sets of the embedded channel type MOSFET of the second embodiment.

In addition to reducing the impurity concentration in the channel region for each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 in the operational amplifier 1L of FIGS. 31 and 32, even if an embedded channel MOSFET is applied. good. That is, the transistors MD1, MD2, MD4, MD5, MD8, MD9, and MD11 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, in the operational amplifier 1L of FIGS. 31 and 32, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and each transistor MD4 constituting the current mirror circuit. , MD5, one or two sets of MD11 may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, in the operational amplifier 1L of FIGS. 31 and 32, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and each transistor MD4 constituting the current mirror circuit. , MD5, MD11 may be changed to the same structure as the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. good. In short, the operational amplifier 1L of FIGS. 31 and 32 has a structure similar to that of the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the transistors M1 to M4 of the third embodiment. It may be a mixed configuration.

(16th Embodiment)
The operational amplifier 1M of the 16th embodiment will be described with reference to FIG. 33. In the operational amplifier 1M of the present embodiment, the back gate bias circuit 20 is omitted as compared with the operational amplifier 1L of the fifteenth embodiment, and the first control unit 110A, the second control unit 110B, and the first resistor R1 of the eighth embodiment are omitted. , The second resistance R2, and the third resistance R3 are added.

The first resistance R1 is provided between the second power supply wiring 3 and the fourth transistor MD4. The first terminal of the first resistance R1 is connected to the source of the fourth transistor MD4, and the second terminal of the first resistance R1 is connected to the second power supply wiring 3.

The second resistance R2 is provided between the second power supply wiring 3 and the fifth transistor MD5. The first terminal of the second resistance R2 is connected to the source of the fifth transistor MD5, and the second terminal of the second resistance R2 is connected to the second power supply wiring 3.

The third resistance R3 is provided between the second power supply wiring 3 and the eleventh transistor MD11. The first terminal of the third resistance R3 is connected to the source of the eleventh transistor MD11, and the second terminal of the third resistance R3 is connected to the second power supply wiring 3.

The first control unit 110A is connected to the first power supply wiring 2 and the node NF1 between the fourth transistor MD4 and the first resistance R1. The first control unit 110A controls the source potential of the fourth transistor MD4 by controlling the current supplied to the node NF1 between the source of the fourth transistor MD4 and the first resistance R1. The first control transistor MA1 of the first control unit 110A of the present embodiment is an N-channel MOSFET. The first constant current source 111 includes a transistor (not shown). The transistor of the first constant current source 111 is a P-channel MOSFET. The drain of the transistor of the first constant current source 111 is connected to the drain of the first control transistor MA1, and the source of the transistor is connected to the first power supply wiring 2. The source of the first control transistor MA1 is connected to the node NF1 between the source of the fourth transistor MD4 and the first resistance R1, and the gate of the first control transistor MA1 is connected to the gate of the fourth transistor MD4. Has been done. With this configuration, the first control unit 110A supplies the node NF1 with a first current Ic1 proportional to the constant current It of the constant current source 152.

The second control unit 110B is connected to the first power supply wiring 2 and the node NF2 between the fifth transistor MD5 and the second resistance R2. The second control unit 110B controls the source potential of the fifth transistor MD5 by controlling the current supplied to the node NF2 between the source of the fifth transistor MD5 and the second resistor R2. The second control transistor MA2 of the second control unit 110B of the present embodiment is an N-channel MOSFET. The second constant current source 112 includes a transistor (not shown). The transistor of the second constant current source 112 is a P-channel MOSFET. The drain of the transistor of the second constant current source 112 is connected to the drain of the second control transistor MA2, and the source of the transistor is connected to the first power supply wiring 2. The source of the second control transistor MA2 is connected to the node NF2 between the source of the fifth transistor MD5 and the second resistance R2, and the gate of the second control transistor MA2 is connected to the gate of the fourth transistor MD4. Has been done. With this configuration, the second control unit 110B supplies the node NF2 with a second current Ic2 proportional to the constant current It of the constant current source 152.

As described above, the source of the fourth transistor MD4 is supplied with the first current Ic1 from the first control unit 110A, and the source of the fifth transistor MD5 is supplied with the second current Ic2 from the second control unit 110B. , The source potential of the 4th transistor MD4 and the source potential of the 5th transistor MD5 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the fourth transistor MD4 and the fifth transistor MD5. As described above, in the present embodiment, the source potentials of the transistors MD4 and MD5 are further increased. Therefore, the transconductance gm34 on the circuit is reduced.

Further, the transistors MD1 to MD12 of the operational amplifier 1M of the present embodiment have the same configuration as the transistors MD1 to MD12 of the fifteenth embodiment. Therefore, an effect similar to the effects of (15-6) to (15-11) of the fifteenth embodiment can be obtained.

Further, since the first control transistor MA1 and the second control transistor MA2 are not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MA1 and MA2 is set to each transistor MD1. , MD2, MD4, MD5, MD8, MD9, MD11 are higher than the impurity concentration in the channel region. In other words, the impurity concentration in the channel region in each of the transistors M1 to M4 is lower than the impurity concentration in the channel region in each of the transistors MA1 and MA2. That is, the transistors MD1, MD2, MD4, MD5, MD8, MD9, and MD11 are low-concentration transistors, and the transistors MA1 and MA2 are high-concentration transistors. The impurity concentration in the channel region of each of the transistors MD1, MD2, MD4, MD5, MD8, MD9, and MD11 is preferably about 1/2 or less of the impurity concentration in the channel region of each of the transistors MA1 and MA2. In the present embodiment, the impurity concentration in the channel region of each of the transistors MD1, MD2, MD4, MD5, MD8, MD9, and MD11 is about 1/10 of the impurity concentration in the channel region of each of the transistors MA1 and MA2. Further, each transistor MA1 and MA2 is a surface channel type MOSFET.

According to this embodiment, in addition to the effect of (15-5) of the fifteenth embodiment, the following effects can be obtained.
(16-1) By controlling the source potentials of the active load transistors MD4 and MD5 to increase by the control units 110A and 110B, the currents flowing through the transistors MD4 and MD5 are reduced. Therefore, since the transconductance gm of each of the transistors MD4 and MD5 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1M can be reduced.

(16-2) The impurity concentration in the channel region of the third transistor MD3 in the constant current source 152, the impurity concentration in the channel region of the tenth transistor MD10 in the correction current source 158, and the impurity concentration in the channel region of the twelfth transistor MD12. , The impurity concentrations in the channel region of the transistor of the constant current source 111 of the first control unit 110A and the transistor of the constant current source 112 of the second control unit 110B are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the third transistor MD3, a step of forming the N-type well layer 63 of the tenth transistor MD10, and a step of forming the N-type well layer 63 of the twelfth transistor MD12 are formed. The step of forming the N-type well layer 63 of the transistors of the constant current sources 111 and 112 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1M can be simplified.

(16-3) The impurity concentration in the channel region of the sixth transistor MD6 and the seventh transistor MD7 in the output stage 155 and the impurity concentration in the channel region of the first control transistor MA1 and the second control transistor MA2 are Equal to each other. According to this configuration, the step of forming the P-type well layer 41 of each of the transistors MD6 and MD7 and the step of forming the P-type well layer 41 of each of the transistors MA1 and MA2 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1M can be simplified.

(Variation example of the 16th embodiment)
The operational amplifier 1M of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The first control unit 110A and the second control unit 110B may be omitted from the operational amplifier 1M. In this case, the source potentials of the transistors MD4 and MD5 are increased by the first resistance R1 and the second resistance R2.

The resistance value of the first resistance R1, the resistance value of the second resistance R2, and the resistance value of the third resistance R3 are changed according to the ratio of the fourth transistor MD4, the fifth transistor MD5, and the eleventh transistor MD11. May be good.

-For each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 of the operational amplifier 1M, instead of lowering the impurity concentration in the channel region, an embedded channel type such as the transistors M1 to M4 of the second embodiment. MOSFET may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, in the operational amplifier 1M, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and a set of the transistors MD4, MD5 and MD11 constituting the current mirror circuit. Any one or a set of two of them may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 of the operational amplifier 1M, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors MD1, MD2, MD4, MD5, MD8, MD9, and MD11 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, in the operational amplifier 1M, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and a set of the transistors MD4, MD5 and MD11 constituting the current mirror circuit. One or two sets of any one of them may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, in the operational amplifier 1M, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and a set of the transistors MD4, MD5 and MD11 constituting the current mirror circuit. Any one or a set of two of them may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1M has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(17th Embodiment)
The operational amplifier 1N of the 17th embodiment will be described with reference to FIG. 34. The operational amplifier 1N of the present embodiment is different from the operational amplifier 1M of the 16th embodiment in that the first control unit 110A and the second control unit 110B are omitted and the current adjustment unit 120C is added.

The current adjusting unit 120C has a current supply unit 121 that supplies a current to the differential pair 151, and a branching unit 122 that draws out a part of the current from the differential pair 151.
The current supply unit 121 includes a transistor MB7, an eleventh transistor MD11, and a twelfth transistor MD12. The transistor MB7 of this embodiment is a P-channel MOSFET. The transistor MB7 is provided between the differential pair 151 and the first power supply wiring 2. The source of the transistor MB7 is connected to the first power supply wiring 2, the drain of the transistor MB7 is connected to the source of each transistor MD1 and MD2 of the differential pair 151, and the gate of the transistor MB7 is connected to the first bias terminal BIAS1. ..

In the present embodiment, the amount of current of the 12th transistor MD12 and the amount of current of the 11th transistor MD11 are equal to each other. The size ratio (current ratio) between the 12th transistor MD12 and the transistor MB7 is 1: 1.

The branch portion 122 of the current adjusting unit 120C has the same configuration as the branch portion 122 of the current adjusting unit 120B of the 14th embodiment.
The first branch circuit 123 includes a first branch transistor MB4 which is an example of a first adjusting transistor connected in parallel with a fourth transistor MD4 corresponding to a third transistor of an active load. The first branch circuit 123 is connected to the drain of the first transistor MD1 and the node NG1 between the fourth transistor MD4 and the first resistor R1. More specifically, the drain of the first branch transistor MB4 is connected to the drain of the first transistor MD1, and the source of the first branch transistor MB4 is connected to the node NG1.

The second branch circuit 124 includes a second branch transistor MB5 which is an example of a second adjusting transistor connected in parallel with the fifth transistor MD5 corresponding to the fourth transistor of the active load. The second branch circuit 124 is connected to the drain of the second transistor MD2 and the node NG2 between the fifth transistor MD5 and the second resistor R2. More specifically, the drain of the second branch transistor MB5 is connected to the drain of the second transistor MD2, and the source of the second branch transistor MB5 is connected to the node NG2.

The gates of the transistors MB4 and MB5 are commonly connected to the gates of the fourth transistor MD4 and the eleventh transistor MD11. As described above, each transistor MD4, MB4, MB5 constitutes a current mirror circuit with the eleventh transistor MD11. That is, the gate voltage of each transistor MD4, MB4, MB5 is controlled by the gate voltage of the eleventh transistor MD11.

The electrical characteristics of the first branch transistor MB4 of the first branch circuit 123 and the second branch transistor MB5 of the second branch circuit 124 are equal to each other. In addition, since the gate voltage of each transistor MD11, MB4, MB5 is common, the current amount of the 11th transistor MD11 is twice the current amount of the first branching transistor MB4 (second branching transistor MB5). Therefore, the total current flowing through each of the transistors MB4 and MB5 is generated in the eleventh transistor MD11.

In the present embodiment, the electrical characteristics of each of the transistors MB4 and MB5 and the fourth transistor MD4 and the fifth transistor MD5 are set to be equal to each other. In addition, since the gates of the transistors MB4 and MB5 are connected to the gate of the fourth transistor MD4, the current flowing through the first branching transistor MB4 and the current flowing through the second branching transistor MB5 are different. It is equal to the current flowing through the 4 -transistor M D4 (current flowing through the fifth transistor M D5 ).

Next, the current flowing through the operational amplifier 1N, particularly the current flowing through the current adjusting unit 120C, will be described.
In the operational amplifier 1N, the constant current It and the supply current IDB7 are supplied to the differential pair 151 from the transistor MB7. The supply current IDB7 is a current proportional to the current Imb12. In this embodiment, since the current ratio between the 11th transistor MD11 and the 12th transistor MD12 is 1: 1, a current Imb12 flows through the 11th transistor MD11. The supply current IDB7 is a current proportional to the current Imb12 flowing through the 11th transistor MD11 by the current mirror circuit composed of the transistors MD12 and MB7. In the present embodiment, the current ratio between the 12th transistor MD12 and the transistor MB7 is 1: 1 so that the supply current IDB7 is equal to the current Imb12. More specifically, the current Imb12 is a current proportional to the current Imb4 by the current mirror circuit including the transistors MD4, MD11, MB4, and MB5. In the present embodiment, the current ratio between the transistors MB4 and MB5 and the transistors MD4 and MD5 is 1: 1 so that the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5 are equal to the current Imb4. In addition, since the 11th transistor MD11 and the respective transistors MB4 and MB5 form a current mirror circuit, the current Imb12 flowing through the 11th transistor MD11 is the total current flowing through the respective transistors MB4 and MB5 (IDB4 + IDB5). .. That is, the supply current IDB7 supplied to the differential pair 151 is the total of the currents flowing through the transistors MB4 and MB5 (IDB4 + IDB5). Further, since the currents flowing through the transistors M D 4, M D 5, MB 4, and MB 5 are equal to each other, the total current (I mb4 + I mb5 ), that is, the constant current It, is the sum of the currents flowing through the transistors M D 4, M D 5. And the total current (IDB4 + IDB5) of the currents flowing through the transistors MB4 and MB5 are equal to each other. Therefore, in the present embodiment, the supply current IDB7 and the constant current It are equal to each other.

Further, the currents Imb1 and Imb2 flowing through the transistors MD1 and MD2 are Imb1 and Imb2 = (It + IDB7) when the inputs of the constant current It and the supply current IDB7 are in phase, that is, when the gate voltage which is an input signal is in phase. ) / 2. As described above, the currents Imb1 and Imb2 flowing through the transistors MD1 and MD2 are larger than 1/2 of the constant current It by 1/2 of the supply current IDB7. On the other hand, the currents IDB4 and IDB5 are pulled out from the drains of the transistors MD1 and MD2 by the fourth transistor MD4 and the transistors MB4 and MB5 of the branch portion 122 constituting the current mirror circuit, respectively. As a result, when the correction currents Icmp1 and Icmp2 are not taken into consideration, the current Imb4 flowing through the fourth transistor MD4 becomes Imb1-IDB4, and the current Imb5 flowing through the fifth transistor MD5 becomes Imb2-IDB5. Therefore, each of the currents IDB4 and IDB5 of the present embodiment is 1/2 of the supply current IDB7. That is, the increased amount of the current flowing through the transistors MD1 and MD2 is passed through the transistors MB4 and MB5. As described above, the current adjusting unit 120C does not increase the current flowing through the active load transistors MD4 and MD5 even if the current flowing through the transistors MD1 and MD2 of the differential pair 151 is increased.

In addition, the current IDB4 flowing through the first branching transistor MB4 flows through the node NG1 between the fourth transistor MD4 and the first resistor R1, and the current IDB5 flowing through the second branching transistor MB5 is the second. It flows through the node NG2 between the 5-transistor MD5 and the second resistor R2. Therefore, the source potential of the 4th transistor MD4 and the source potential of the 5th transistor MD5 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the fourth transistor MD4 and the fifth transistor MD5. As described above, in the present embodiment, the source potentials of the transistors MD4 and MD5 are further increased as in the 16th embodiment. Therefore, the transconductance gm34 on the circuit is further reduced.

Further, the transistors MD1 to MD12 of the operational amplifier 1M of the present embodiment have the same configuration as the transistors MD1 to MD12 of the fifteenth embodiment. Therefore, an effect similar to the effects of (15-6) to (15-11) of the fifteenth embodiment can be obtained.

Further, the transistors MB4, MB5, and MB7 have the same configuration as the transistors MB1 to MB5 of the ninth embodiment. That is, since each transistor MB4, MB5, MB7 is not easily affected by 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MB4, MB5, MB7 is set to each transistor MD1, MD2, MD4, MD5. , MD8, MD9, and MD11 are higher than the impurity concentration in the channel region. In other words, the impurity concentration in the channel region of each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 is lower than the impurity concentration in the channel region of each transistor MB4, MB5, MB7. That is, each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 is a low concentration transistor, and each transistor MB4, MB5, MB7 is a high concentration transistor. The impurity concentration in the channel region of each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 is preferably about 1/2 or less of the impurity concentration in the channel region of each transistor MB4, MB5, MB7. In the present embodiment, the impurity concentration in the channel region of each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 is about 1/10 of the impurity concentration in the channel region of each transistor MB4, MB5, MB7. Further, each transistor MB4, MB5, MB7 is a surface channel type MOSFET.

According to this embodiment, in addition to the effect of (15-5) of the fifteenth embodiment, the following effects can be obtained.
(17-1) While the current supplied to the differential pair 151 by the current adjusting unit 120C is increased, the current supplied to the active load is not increased, so that the transconductance of each transistor MD1 and MD2 of the differential pair 151 increases. , The increase in the transconductance of each transistor MD4 and MD5 of the active load is suppressed. Therefore, the noise of the output signal Sout of the operational amplifier 1N can be reduced.

(17-2) Since the source potential of each transistor MD4 and MD5 of the active load can be increased by the first resistance R1 and the second resistance R2 connected to the active load, the current flowing through each transistor MD4 and MD5 is reduced. Move in the direction. Therefore, since the transconductance gm of each of the transistors MD4 and MD5 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1N can be reduced.

(17-3) Impurity concentration in the channel region of the third transistor MD3 in the constant current source 152, impurity concentration in the channel region of the tenth transistor MD10 in the correction current source 158, and impurity concentration in the channel region of the twelfth transistor MD12. , The impurity concentrations in the channel region of the transistor MB6 of the current supply unit 121 are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the third transistor MD3, a step of forming the N-type well layer 63 of the tenth transistor MD10, and a step of forming the N-type well layer 63 of the twelfth transistor MD12 are formed. The step of forming the N-type well layer 63 of the transistor MB6 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1N can be simplified.

(17-4) The impurity concentration in the channel region of the sixth transistor MD6 and the seventh transistor MD7 in the output stage 155 and the impurity concentration in the channel region of the first branch transistor MB4 and the second branch transistor MB5 are Equal to each other. According to this configuration, the step of forming the P-type well layer 41 of each transistor MD6 and MD7 and the step of forming the P-type well layer 41 of each of the transistors MB4 and MB5 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1N can be simplified.

(Variation example of the 17th embodiment)
The operational amplifier 1N of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The resistance value of the first resistance R1, the resistance value of the second resistance R2, and the resistance value of the third resistance R3 are changed according to the ratio of the fourth transistor MD4, the fifth transistor MD5, and the eleventh transistor MD11. May be good.

The first resistor R1, the second resistor R2, and the third resistor R3 are omitted from the operational amplifier 1N, and the source of the first branch transistor MB4 of the first branch circuit 123 and the second branch of the second branch circuit 124 are used. The source of the transistor MB5 may be connected to the second power supply wiring 3. In this case, the regulated current source 125 may be added to the operational amplifier 1N as in the operational amplifier 1H of the eleventh embodiment. The connection configuration of the transistor MB6 of the adjustment current source 125 and the transistors MD11, MB4, MB5 is the same as that of the eleventh embodiment.

The current control unit 130 of the 14th embodiment may be added to the operational amplifier 1N. The first control unit 131 of the current control unit 130 is connected to the node NG1, and the second control unit 132 is connected to the node NG2. In this case, the source of the first branch transistor MB4 of the first branch circuit 123 of the branch portion 122 and the source of the second branch transistor MB5 of the second branch circuit 124 are connected to the second power supply wiring 3. ..

-For each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 of the operational amplifier 1N, instead of lowering the impurity concentration in the channel region, an embedded channel type such as the transistors M1 to M4 of the second embodiment. MOSFET may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, in the operational amplifier 1N, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and a set of the transistors MD4, MD5 and MD11 constituting the current mirror circuit. Any one or a set of two of them may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor MD1, MD2, MD4, MD5, MD8, MD9, MD11 of the operational amplifier 1N, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors MD1, MD2, MD4, MD5, MD8, MD9, and MD11 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, in the operational amplifier 1N, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and a set of the transistors MD4, MD5 and MD11 constituting the current mirror circuit. One or two sets of any one of them may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, in the operational amplifier 1N, a set of the transistors MD1 and MD2 constituting the differential pair 151, a set of the transistors MD8 and MD9 constituting the current mirror circuit, and a set of the transistors MD4, MD5 and MD11 constituting the current mirror circuit. Any one or a set of two of them may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1N has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(18th Embodiment)
The operational amplifier 1P of the eighteenth embodiment will be described with reference to FIG. 35.
The operational amplifier 1P amplifies the potential difference between the inverting input terminal INN and the non-inverting input terminal INP, and outputs an output signal Sout from the output terminal OUT. The operational amplifier 1P includes a differential amplification stage 160, a class AB bias circuit 165, a backgate bias circuit 20, and an output stage 166. The differential amplification stage 160 includes a differential pair 161, a constant current source 162, a cascode current mirror circuit 163, and a bias circuit 164. The operational amplifier 1P is integrally integrated on one semiconductor substrate.

The differential pair 161 includes a first transistor ME1 connected to the non-inverting input terminal INP and a second transistor ME2 connected to the inverting input terminal INN. The differential pair 161 of the present embodiment is composed of a P-channel MOSFET. The first transistor ME1 and the second transistor ME2 may have either a depletion type structure or an enhancement type structure. In the present embodiment, the first transistor ME1 and the second transistor ME2 have an enhancement type structure. The gate of the first transistor ME1 is connected to the non-inverting input terminal INP, and the gate of the second transistor ME2 is connected to the inverting input terminal INN. The source of the first transistor ME1 and the source of the second transistor ME2 are commonly connected.

The constant current source 162 includes a third transistor ME3 connected to the differential pair 161. The third transistor ME3 of this embodiment is a P-channel MOSFET. The drain of the third transistor ME3 is connected to the source of each transistor ME1 and ME2, and the source of the third transistor ME3 is connected to the first power supply wiring 2. A bias voltage Vbp1 from a first bias circuit (not shown) is input to the gate of the third transistor ME3. The constant current source 162 supplies a constant current It based on the bias voltage Vbp1.

The cascode current mirror circuit 163 is an active load connected to the differential pair 161. The cascode current mirror circuit 163 is configured by stacking two transistors of the same type, and includes the fourth transistor ME4 to the seventh transistor ME7. In the present embodiment, the 4th transistor ME4 to the 7th transistor ME7 are composed of N-channel MOSFETs. In particular, the fourth transistor ME4 and the fifth transistor ME5 have an enhancement type structure.

The fourth transistor ME4 is provided in series with the second transistor ME2. More specifically, the fourth transistor ME4 is provided between the drain of the second transistor ME2 and the second power supply wiring 3. The fifth transistor ME5 is provided in series with the first transistor ME1. More specifically, the fifth transistor ME5 is provided between the drain of the first transistor ME1 and the second power supply wiring 3. The sixth transistor ME6 is vertically stacked on the fourth transistor ME4, and the seventh transistor ME7 is vertically stacked on the fifth transistor ME5. More specifically, the source of the 6th transistor ME6 is connected to the drain of the 4th transistor ME4, and the source of the 7th transistor ME7 is connected to the drain of the 5th transistor ME5. The gates of the 6th transistor ME6 and the 7th transistor ME7 are commonly connected and connected to a second bias circuit (not shown). The gates of the sixth transistor ME6 and the seventh transistor ME7 are appropriately biased by the bias voltage Vbn1 from the second bias circuit. The gates of the 4th transistor ME4 and the 5th transistor ME5 are connected to the drain of the 6th transistor ME6. When the first transistor ME1 and the second transistor ME2 are of the depletion type, the input full swing (Rail-to-Rail) can be realized by the circuit configuration shown in FIG.

Further, the 4th transistor ME4 to the 7th transistor ME7 are connected to the first comparator 167. Specifically, the drain of the 6th transistor ME6 is connected to the non-inverting input terminal of the 1st comparator 167, the drain of the 7th transistor ME7 is connected to the inverting input terminal of the 1st comparator 167, and the 4th transistor ME4 and The gate of the fifth transistor ME5 is connected to the output terminal of the first comparator 167. As a result, the first comparator 167 outputs an output signal to the gates of the fourth transistor ME4 and the fifth transistor ME5 so that the drain voltage of the sixth transistor ME6 and the drain voltage of the seventh transistor ME7 match.

The bias circuit 164 is a constant current circuit that maintains the cascode current mirror circuit 163 in an appropriate bias state. In one example, the bias circuit 164 is configured by stacking two transistors of the same type, and includes the eighth transistor ME8 to the eleventh transistor ME11. In the present embodiment, the 8th transistor ME8 to the 11th transistor ME11 are P-channel MOSFETs. In particular, the 8th transistor ME8 and the 9th transistor ME9 have an enhancement type structure. The eighth transistor ME8 and the ninth transistor ME9 form a current source that generates a predetermined current. The gates of the 8th transistor ME8 and the 9th transistor ME9 are appropriately biased by the first bias circuit. The gate of the tenth transistor ME10 is connected to a third bias circuit (not shown). The gate of the tenth transistor ME10 is appropriately biased by the bias voltage Vbp2 from the third bias circuit. Further, the 8th transistor ME8, the 9th transistor ME9, and the 11th transistor ME11 are connected to the second comparator 168. Specifically, the drain of the 8th transistor ME8 is connected to the non-inverting input terminal of the 2nd comparator 168, the drain of the 9th transistor ME9 is connected to the inverting input terminal of the 2nd comparator 168, and the 11th transistor ME11 The gate is connected to the output terminal of the second comparator 168. As a result, the second comparator 168 turns on the eleventh transistor ME11 when the difference between the drain voltage of the eighth transistor ME8 and the drain voltage of the ninth transistor ME9 is equal to or more than a predetermined value, thereby turning on the eleventh transistor ME11. The supply of current to the class AB bias circuit 165 and the output stage 166 is stopped via the circuit.

The class AB bias circuit 165 is an output buffer circuit that includes the 12th transistor ME12 to the 19th transistor ME19 and draws a large drive current during operation from a small bias current during bias.

The 12th transistor ME12 to the 14th transistor ME14 are connected in series between the first power supply wiring 2 and the second power supply wiring 3. The twelfth transistor ME12 is a P-channel MOSFET, and the thirteenth transistor ME13 and the fourteenth transistor ME14 are N-channel MOSFETs. The source of the twelfth transistor ME12 is connected to the first power supply wiring 2, and the bias voltage Vbp1 is input to the gate of the twelfth transistor ME12 from the first bias circuit. The drain of the 13th transistor ME13 is connected to the drain of the 12th transistor ME12, the source of the 13th transistor ME13 is connected to the drain of the 14th transistor ME14, and the gate of the 13th transistor ME13 is connected to the drain of the 13th transistor ME13. ing. The gate of the 14th transistor ME14 is connected to the drain of the 14th transistor ME14, and the source of the 14th transistor ME14 is connected to the second power supply wiring 3.

The 15th transistor ME15 to the 17th transistor ME17 are connected in series between the first power supply wiring 2 and the second power supply wiring 3. The 15th transistor ME15 to the 17th transistor ME17 are provided on the output stage 166 side with respect to the 12th transistor ME12 to the 14th transistor ME14. The 15th transistor ME15 is an N-channel MOSFET, and the 16th transistor ME16 and the 17th transistor ME17 are P-channel MOSFETs. The source of the 15th transistor ME15 is connected to the second power supply wiring 3, and the gate of the 15th transistor ME15 is connected to a fourth bias circuit (not shown). The gate of the 15th transistor ME15 is appropriately biased by inputting the bias voltage Vbn2 from the 4th bias circuit. The source of the 16th transistor ME16 is connected to the first power supply wiring 2, the drain of the 16th transistor ME16 is connected to the source of the 17th transistor ME17, and the gate of the 16th transistor ME16 is connected to the drain of the 16th transistor ME16. ing. The gate of the 17th transistor ME17 is connected to the drain of the 17th transistor ME17, and the drain of the 17th transistor ME17 is connected to the drain of the 15th transistor ME15.

The 18th transistor ME18 and the 19th transistor ME19 are connected to a bias circuit 164, a cascode current mirror circuit 163, and an output stage 166. The 18th transistor ME18 is an N-channel MOSFET, and the 19th transistor ME19 is a P-channel MOSFET. The drain of the 18th transistor ME18 is connected to the node NH1 between the drain of the 11th transistor ME11 and the output stage 166, and the source of the 18th transistor ME18 is the node NH2 between the drain of the 7th transistor ME7 and the output stage 166. It is connected to the. The gate of the 18th transistor ME18 is connected to the node NH3 between the drain of the 12th transistor ME12 and the drain of the 13th transistor ME13. The source of the 19th transistor ME19 is connected to the node NH4 between the drain of the 11th transistor ME11 and the output stage 166, and the drain of the 19th transistor ME19 is the node NH5 between the drain of the 7th transistor ME7 and the output stage 166. It is connected to the. The gate of the 19th transistor ME19 is connected to the node NH6 between the drain of the 15th transistor ME15 and the drain of the 17th transistor ME17. The node NH4 is closer to the output stage 166 than the node NH1, and the node NH5 is closer to the output stage 166 than the node NH2.

The output stage 166 is a source grounding circuit using the 20th transistor ME20 and the 21st transistor ME21, amplifies the output signal of the cascode current mirror circuit 163 which is an active load, and outputs the output signal Sout from the output terminal OUT.

In the present embodiment, the 20th transistor ME20 is a P-channel MOSFET, and the 21st transistor ME21 is an N-channel MOSFET. The source of the 20th transistor ME20 is connected to the first power supply wiring 2, and the drain of the 20th transistor ME20 is connected to the output terminal OUT. The gate of the 20th transistor ME20 is connected to the drain of the 11th transistor ME11. The source of the 21st transistor ME21 is connected to the second power supply wiring 3, and the drain of the 21st transistor ME21 is connected to the output terminal OUT. The gate of the 21st transistor ME21 is connected to the drain of the 7th transistor ME7.

The output stage 166 further includes a phase compensation circuit 169. The phase compensation circuit 169 includes a first compensation resistor RC1, a second compensation resistor RC2, a first compensation capacitor CC1, and a second compensation capacitor CC2. The first compensating resistor RC1 and the first compensating capacitor CC1 are connected in series. The first terminal of the first compensating resistor RC1 is connected to the node NH7 between the drain of the 11th transistor ME11 and the gate of the 20th transistor ME20, and the second terminal of the first compensating resistor RC1 is the first compensating capacitor. It is connected to the first terminal of CC1. The second terminal of the first compensation capacitor CC1 is connected to the output terminal OUT. The second compensating resistor RC2 and the second compensating capacitor CC2 are connected in series. The first terminal of the second compensating resistor RC2 is connected to the node NH8 between the drain of the seventh transistor ME7 and the gate of the 21st transistor ME21, and the second terminal of the second compensating resistor RC2 is the second compensating capacitor. It is connected to the first terminal of CC2. The second terminal of the second compensation capacitor CC2 is connected to the output terminal OUT.

The backgate bias circuit 20 is connected to the common backgate of the first transistor ME1 and the second transistor ME2 of the differential pair 161 and the first power supply wiring 2. The configuration of the backgate bias circuit 20 is the same as the configuration of the backgate bias circuit 20 of the first embodiment (see FIG. 2). The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor ME1 and the second transistor ME2 so that the bias voltage VB is closer to the first power supply voltage VDD than the source potential of the first transistor ME1 and the second transistor ME2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the voltage is on the first power supply voltage VDD side of the intermediate voltage between the source potential of the first transistor ME1 and the second transistor ME2 and the first power supply voltage VDD. VB is applied to the back gates of the first transistor ME1 and the second transistor ME2. That is, the backgate bias circuit 20 applies a bias voltage VB to the first transistor ME1 and the second transistor ME2 so that the backgate source voltage VBS becomes large. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be higher than the first power supply voltage VDD. In this case, the bias voltage VB is preferably higher than the first power supply voltage VDD within a range in which the parasitic diodes of the first transistor ME1 and the second transistor ME2 are not turned on. That is, the bias voltage VB is preferably less than the voltage at which the parasitic diodes of the first transistor ME1 and the second transistor ME2 are turned on. An example of the voltage at which the parasitic diode of the first transistor ME1 and the second transistor ME2 is turned on is a voltage (ldap + 0.5 to 0.6) higher than the first power supply voltage VDD by 0.5 to 0.6 V. The bias voltage VB is preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within a predetermined range including the first power supply voltage VDD. More specifically, the bias voltage VB is more preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within ± 20% of the first power supply voltage VDD. As a result, the backgate-source voltage VBS becomes a voltage excluding the backgate-source voltage VBSH among the voltages within ± 20% of the backgate-source voltage VBSH.

Further, in the present embodiment, in order to further reduce the 1 / f noise of the output signal Sout of the output stage 166, the impurity concentration in the channel region in some of the transistors of the operational amplifier 1P is set to the channel in the other transistors. It is lower than the impurity concentration in the region. That is, the plurality of transistors of the operational amplifier 1P include a high-concentration transistor in which the impurity concentration in the channel region is the first concentration and a low-concentration transistor in which the impurity concentration in the channel region is a second concentration lower than the first concentration. Specifically, the impurity concentration in the channel region of the transistor that is easily affected by the 1 / f noise of the output signal Sout is lower than the impurity concentration in the channel region of the transistor that is not easily affected by the 1 / f noise of the output signal Sout. is doing. That is, a low-concentration transistor is used as a transistor that is more susceptible to 1 / f noise of the output signal Sout among a plurality of transistors than a high-concentration transistor, and a high-concentration transistor is a plurality of transistors rather than a low-concentration transistor. Of these, it is used for transistors that are not easily affected by 1 / f noise of the output signal Sout. Specifically, in the operational amplifier 1P, the portion susceptible to 1 / f noise of the output signal Sout is a differential pair 161, a part of the cascode current mirror circuit 163, and a part of the bias circuit 164. On the other hand, the part of the output signal Sout that is not easily affected by the 1 / f noise is the constant current source 162, the other part of the cascode current mirror circuit 163, the other part of the bias circuit 164, the AB class bias circuit 165, and the back gate. The bias circuit 20 and the output stage 166.

In the present embodiment, the impurity concentration in the channel region in the transistor of the differential pair 161 and a part of the cascode current mirror circuit 163 and a part of the bias circuit 164 is set to the constant current source 162 and the other one of the cascode current mirror circuit 163. It is lower than the impurity concentration in the channel region in the transistor of the unit, the other part of the bias circuit 164, the class AB bias circuit 165, the back gate bias circuit 20, and the output stage 166. That is, the differential pair 161 and a part of the cascode current mirror circuit 163 and a part of the bias circuit 164 are low-concentration transistors, and the constant current source 162, the other part of the cascode current mirror circuit 163, and the bias. The other part of the circuit 164, the class AB bias circuit 165, the backgate bias circuit 20, and the transistor of the output stage 166 are high-concentration transistors. Specifically, the impurity concentration in the channel region of the first transistor ME1, the second transistor ME2, the fourth transistor ME4, the fifth transistor ME5, the eighth transistor ME8, and the ninth transistor ME9 is determined by the third transistor ME3 and the sixth. It is lower than the impurity concentration in the channel region of the transistors ME6, the 7th transistor ME7, the transistors M5 to M9 of the backgate bias circuit 20, the transistors of the constant current source 21, and the 10th transistor ME10 to the 21st transistor ME21.

The impurity concentration in the channel region of each transistor ME1, ME2, ME4, ME5, ME8, ME9 is the impurity concentration of the channel region in the transistors of each transistor ME3, ME6, ME7, M5 to M9, ME10 to ME21 and the constant current source 21. It is preferably about 1/2 or less. In the present embodiment, the impurity concentration in the channel region of each transistor ME1, ME2, ME4, ME5, ME8, ME9 is the channel in each transistor ME3, ME6, ME7, M5 to M9, ME10 to ME21, and the constant current source 21. It is about 1/10 of the impurity concentration in the region.

Further, the structure and manufacturing method of the N-channel MOSFET and the P-channel MOSFET of each transistor of the operational amplifier 1P are the same structure and manufacturing method as those of the N-channel MOSFET and the P-channel MOSFET such as the first transistor M1 of the first embodiment.

According to this embodiment, the following effects can be obtained.
(18-1) In the backgate bias circuit 20, the backgate bias circuit 20 has a bias voltage VB in the backgate of the first transistor ME1 and the second transistor ME2 (in the N-type well layer 39 of the first transistor ME4 and the second transistor ME2). A bias voltage VB closer to the first power supply voltage VDD than the source potential of the first transistor ME1 and the second transistor ME2 is applied to the contact region for applying the first transistor ME1 and the second transistor ME2. As a result, the backgate-source voltage VBS of the first transistor ME1 and the second transistor ME2 becomes large. As a result, the transconductance gm12 of the first transistor ME1 and the second transistor ME2 becomes large, so that the noise of the output signal Sout of the operational amplifier 1P can be reduced.

(18-2) In the back gate bias circuit 20, by making the bias voltage VB larger than the first power supply voltage VDD, the transconductance gm12 of the first transistor ME1 and the second transistor ME2 becomes larger, so that the operational amplifier 1P The noise of the output signal Sout can be further reduced.

(18-3) By setting the bias voltage VB to a voltage lower than the voltage at which the parasitic diodes of the first transistor ME1 and the second transistor ME2 are turned on, the first transistor ME1 and the second transistor ME2 can operate stably.

(18-4) By setting the bias voltage VB to a voltage other than the same voltage as the first power supply voltage VDD within a predetermined range including the first power supply voltage VDD, the backgate-source voltage VBS becomes large. Therefore, the transconductance gm12 of the first transistor ME1 and the second transistor ME2 becomes large, and the first transistor ME1 and the second transistor ME2 can operate stably. In particular, by setting the bias voltage VB to a voltage other than the voltage within ± 20% of the first power supply voltage VDD, which is the same as the first power supply voltage VDD, the backgate source voltage VBS becomes the backgate source. Since the inter-voltage voltage is near VBSH, the transconductance gm12 of the first transistor ME1 and the second transistor ME2 becomes large, and the first transistor ME1 and the second transistor ME2 can operate more stably.

(18-5) The impurity concentration in the channel region of the first transistor ME1 and the second transistor ME2 constituting the differential pair 161 is the respective transistors M5 of the 20th transistor ME20 and the backgate bias circuit 20 constituting the output stage 166. It is lower than the impurity concentration in the channel region in M8 and M9. According to this configuration, the mobility fluctuation is caused by lowering the impurity concentration in the channel region of each transistor ME1 and ME2 constituting the differential pair 161 which is easily affected by 1 / f noise of the output signal Sout of the operational amplifier 1P. Can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1P can be effectively suppressed.

(18-6) The impurity concentration in the channel region of the fourth transistor ME4 and the fifth transistor ME5 constituting the current source of the cascode current mirror circuit 163 is the concentration of impurities in the 21st transistor ME21 and the backgate bias circuit 20 constituting the output stage 166. It is lower than the impurity concentration in the channel region in the transistors of each of the transistors M6 and M7 and the constant current source 21. According to this configuration, the impurity concentration in the channel region of each of the transistors ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1P, is lowered. Fluctuations in mobility can be suppressed, and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1P can be effectively suppressed.

(18-7) The impurity concentration in the channel region of the 8th transistor ME8 and the 9th transistor ME9 constituting the current source of the bias circuit 164 is the respective transistors of the 20th transistor ME20 and the backgate bias circuit 20 constituting the output stage 166. It is lower than the impurity concentration in the channel region in M5, M8, and M9. According to this configuration, the mobility is reduced by lowering the impurity concentration in the channel region of each of the transistors ME8 and ME9 constituting the current source of the bias circuit 164 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1P. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1P can be effectively suppressed.

(18-8) Impurity concentration in the channel region of the 8th transistor ME8 and 9th transistor ME9 constituting the current source of the bias circuit 164, and the channel region of the 1st transistor ME1 and the 2nd transistor ME2 constituting the differential pair 161. Impurity concentration is equal to each other. According to this configuration, the step of forming the N-type well layer 70 of each transistor ME1 and ME2 constituting the differential pair 161 and the N-type well layer 70 of each transistor ME8 and ME9 constituting the current source of the bias circuit 164 Can be performed collectively with the process of forming the above. Therefore, the process of manufacturing the operational amplifier 1P can be simplified.

(18-9) The impurity concentration in the channel region of the third transistor ME3 of the constant current source 162, the impurity concentration in the channel region of the transistors ME10 and ME11 of the bias circuit 164, and the transistors ME12 and ME16 of the class AB bias circuit 165. , The impurity concentration in the channel region of ME17 and ME19, the impurity concentration in the channel region of the 20th transistor ME20 of the output stage 166, and the impurity concentration in the channel region of each transistor M5, M8, M9 of the back gate bias circuit 20. Equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the third transistor ME3, a step of forming the N-type well layer 63 of each transistor ME10, ME11, and an N-type well of each transistor ME12, ME16, ME17, ME19. The step of forming the layer 63, the step of forming the N-type well layer 63 of the 20th transistor ME20, and the step of forming the N-type well layer 63 of each of the transistors M5, M8, and M9 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1P can be simplified.

(18-10) The impurity concentration in the channel region of each transistor ME6 and ME7 of the cascode current mirror circuit 163, the impurity concentration in the channel region of each transistor ME13 to ME15 of the class AB bias circuit 165, and the 21st transistor of the output stage 166. The impurity concentration in the channel region of ME21 and the impurity concentration in the channel region of each transistor M6, M7 of the backgate bias circuit 20 and the transistor of the constant current source 21 are equal to each other. According to this configuration, a step of forming the P-type well layer 41 of each transistor ME6 and ME7, a step of forming the P-type well layer 41 of each transistor ME13 to ME15, and a step of forming the P-type well layer 41 of the 21st transistor ME21 are formed. The steps of forming the P-type well layer 41 of the transistors M6 and M7 and the constant current source 21 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1P can be simplified.

(Variation example of the 18th embodiment)
The operational amplifier 1P of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the operational amplifier 1P, the step-down circuit 100 of the fifth embodiment is added between the first power supply wiring 2 and the differential pair 161 and more specifically between the first power supply wiring 2 and the constant current source 162. You can also do it. According to this configuration, the same effect as that of the fifth embodiment can be obtained. Further, the back gate bias circuit 20 can also be connected to the third power supply wiring 4 like the back gate bias circuit 20 of the sixth embodiment. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

-For each transistor ME1, ME2, ME4, ME5, ME8, ME9, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as each transistor M1 to M4 of the second embodiment is applied. You may. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two of the sets of ME9 may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor ME1, ME2, ME4, ME5, ME8, ME9, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors ME1, ME2, ME4, ME5, ME8, and ME9 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two sets of ME9 may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two sets of ME9 may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1P has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(19th Embodiment)
The operational amplifier 1Q of the 19th embodiment will be described with reference to FIG. 36. The operational amplifier 1Q of the present embodiment omits the back gate bias circuit 20 as compared with the operational amplifier 1P of the 18th embodiment, and has the first control unit 110A, the second control unit 110B, and the first resistor R1 of the eighth embodiment. , And the point that the second resistor R2 is added is different.

The first resistance R1 is provided between the second power supply wiring 3 and the fourth transistor ME4. The first terminal of the first resistance R1 is connected to the source of the fourth transistor ME4, and the second terminal of the first resistance R1 is connected to the second power supply wiring 3.

The second resistance R2 is provided between the second power supply wiring 3 and the fifth transistor ME5. The first terminal of the second resistance R2 is connected to the source of the fifth transistor ME5, and the second terminal of the second resistance R2 is connected to the second power supply wiring 3.

The first control unit 110A controls the source potential of the fourth transistor ME4 by controlling the current supplied to the node NH9 between the source of the fourth transistor ME4 and the first resistor R1. The first control transistor MA1 of the first control unit 110A of the present embodiment is an N-channel MOSFET. The first constant current source 111 includes a transistor (not shown). The transistor of the first constant current source 111 is a P-channel MOSFET. The drain of the transistor of the first constant current source 111 is connected to the drain of the first control transistor MA1, and the source of the transistor is connected to the first power supply wiring 2. The source of the first control transistor MA1 is connected to the node NH9 between the source of the fourth transistor ME4 and the first resistance R1, and the gate of the first control transistor MA1 is connected to the gate of the fourth transistor ME4. Has been done. With this configuration, the first control unit 110A supplies the node NH9 with a first current Ic1 proportional to the constant current It of the constant current source 162.

The second control unit 110B controls the source potential of the fifth transistor ME5 by controlling the current supplied to the node NH10 between the source of the fifth transistor ME5 and the second resistor R2. The second control transistor MA2 of the second control unit 110B of the present embodiment is an N-channel MOSFET. The second constant current source 112 includes a transistor (not shown). The transistor of the second constant current source 112 is a P-channel MOSFET. The drain of the transistor of the second constant current source 112 is connected to the drain of the second control transistor MA2, and the source of the transistor is connected to the first power supply wiring 2. The source of the second control transistor MA2 is connected to the node NH10 between the source of the fifth transistor ME5 and the second resistance R2, and the gate of the second control transistor MA2 is connected to the gate of the fourth transistor ME4. Has been done. With this configuration, the second control unit 110B supplies the node NH10 with a second current Ic2 proportional to the constant current It of the constant current source 162.

As described above, the source of the fourth transistor ME4 is supplied with the first current Ic1 from the first control unit 110A, and the source of the fifth transistor ME5 is supplied with the second current Ic2 from the second control unit 110B. , The source potential of the 4th transistor ME4 and the source potential of the 5th transistor ME5 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the fourth transistor ME4 and the fifth transistor ME5. As described above, in the present embodiment, the source potentials of the transistors ME4 and ME5 are further increased. Therefore, the transconductance gm on the circuit is reduced.

Further, the transistors ME1 to ME21 of the operational amplifier 1Q of the present embodiment have the same configuration and manufacturing method as the transistors ME1 to ME21 of the eighteenth embodiment. Therefore, an effect similar to the effects of (18-5) to (18-8) of the 18th embodiment can be obtained.

Further, since the first control transistor MA1 and the second control transistor MA2 are not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MA1 and MA2 is set to each transistor ME1. , ME2, ME4, ME5, ME8, ME9 are higher than the impurity concentration in the channel region. In other words, the impurity concentration in the channel region in each of the transistors M1 to M4 is lower than the impurity concentration in the channel region in each of the transistors MA1 and MA2. That is, the transistors ME1, ME2, ME4, ME5, ME8, and ME9 are low-concentration transistors, and the transistors MA1 and MA2 are high-concentration transistors. The impurity concentration in the channel region of each transistor ME1, ME2, ME4, ME5, ME8, ME9 is preferably about 1/2 or less of the impurity concentration in the channel region of each transistor MA1, MA2. In the present embodiment, the impurity concentration in the channel region of each transistor ME1, ME2, ME4, ME5, ME8, ME9 is about 1/10 of the impurity concentration in the channel region of each transistor MA1, MA2.

According to this embodiment, the following effects can be obtained.
(19-1) By controlling the source potentials of the active load transistors ME4 and ME5 to increase by the control units 110A and 110B, the currents flowing through the transistors ME4 and ME5 are reduced. Therefore, since the transconductance gm of each of the transistors ME4 and ME5 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1Q can be reduced.

(19-2) The impurity concentration in the channel region of the third transistor ME3 of the constant current source 162, the impurity concentration in the channel region of the transistors ME10 and ME11 of the bias circuit 164, and the transistors ME12 and ME16 of the class AB bias circuit 165. , The impurity concentration in the channel region of ME17 and ME19, the impurity concentration in the channel region of the 20th transistor ME20 of the output stage 166, the transistor of the constant current source 111 of the first control unit 110A, and the constant current source of the second control unit 110B. The impurity concentrations in the channel region of the 112 transistors are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the third transistor ME3, a step of forming the N-type well layer 63 of each transistor ME10, ME11, and an N-type well of each transistor ME12, ME16, ME17, ME19. The step of forming the layer 63, the step of forming the N-type well layer 63 of the 20th transistor ME20, and the step of forming the N-type well layer 63 of the transistors of the constant current sources 111 and 112 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1Q can be simplified.

(19-3) The impurity concentration in the channel region of each transistor ME6 and ME7 of the cascode current mirror circuit 163, the impurity concentration in the channel region of each transistor ME13 to ME15 of the class AB bias circuit 165, and the 21st transistor of the output stage 166. The impurity concentration in the channel region of ME21 and the impurity concentration in the channel region of the transistors MA1 and MA2 of the control units 110A and 110B are equal to each other. According to this configuration, a step of forming the P-type well layer 41 of each transistor ME6 and ME7, a step of forming the P-type well layer 41 of each transistor ME13 to ME15, and a step of forming the P-type well layer 41 of the 21st transistor ME21 are formed. And the step of forming the P-type well layer 41 of each transistor MA1 and MA2 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1Q can be simplified.

(Variation example of the 19th embodiment)
The operational amplifier 1Q of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The first control unit 110A and the second control unit 110B may be omitted from the operational amplifier 1Q. In this case, the source potentials of the transistors ME4 and ME5 are increased by the first resistance R1 and the second resistance R2.

In the operational amplifier 1Q, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 may be changed according to the ratio of the fourth transistor ME4 and the fifth transistor ME5.
-For each transistor ME1, ME2, ME4, ME5, ME8, ME9, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as each transistor M1 to M4 of the second embodiment is applied. You may. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two of the sets of ME9 may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor ME1, ME2, ME4, ME5, ME8, ME9, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors ME1, ME2, ME4, ME5, ME8, and ME9 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two sets of ME9 may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two sets of ME9 may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1Q has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(20th Embodiment)
The operational amplifier 1R of the twentieth embodiment will be described with reference to FIG. 37. The operational amplifier 1R of the present embodiment is different from the operational amplifier 1P of the 18th embodiment in that the back gate bias circuit 20 is omitted and the current adjusting unit 120D is added.

The current adjusting unit 120D has the same configuration as the current adjusting unit 120 of the tenth embodiment.
The first branch circuit 123 of the current adjusting unit 120D is connected to the drain of the first transistor ME1 and the second power supply wiring 3. More specifically, the drain of the first branch transistor MB4 of the first branch circuit 123 is connected to the drain of the first transistor ME1, and the source of the first branch transistor MB4 is connected to the second power supply wiring 3. ing.

The second branch circuit 124 of the current adjusting unit 120D is connected to the drain of the second transistor ME2 and the second power supply wiring 3. More specifically, the drain of the second branch transistor MB5 of the second branch circuit 124 is connected to the drain of the second transistor ME2, and the source of the second branch transistor MB5 is connected to the second power supply wiring 3. ing.

The gates of the transistors MB4 and MB5 are commonly connected to the gates of the fourth transistor ME4. Further, the gate of the second supply transistor MB2 is connected to the gate of the fourth transistor ME4. As described above, each transistor MB2, MB4, MB5 constitutes a current mirror circuit with the fourth transistor ME4. That is, the gate voltage of each transistor MB2, MB4, MB5 of the current adjusting unit 120D is controlled by the gate voltage of the fourth transistor ME4.

The electrical characteristics of the first branch transistor MB4 of the first branch circuit 123 and the second branch transistor MB5 of the second branch circuit 124 are equal to each other. In addition, since the gate voltages of the transistors MB2, MB4, and MB5 are common, the current amount of the second supply transistor MB2 is 2 of the current amount of the first branch transistor MB4 (second branch transistor MB5). Since it is doubled, the total current flowing through each of the transistors MB4 and MB5 is generated in the second supply transistor MB2.

In the present embodiment, the electrical characteristics of each of the transistors MB4 and MB5 and the fourth transistor ME4 and the fifth transistor ME5 are set to be equal to each other. In addition, since the gates of the transistors MB4 and MB5 are connected to the gate of the fourth transistor ME4, the current flowing through the first branching transistor MB4 and the current flowing through the second branching transistor MB5 are the first. It is equal to the current flowing through the 4-transistor ME4 (current flowing through the fifth transistor ME5).

Next, the current flowing through the operational amplifier 1R, particularly the current flowing through the current adjusting unit 120D will be described. In this description, the constant current flowing through the constant current source 11 is 2 ID. The sizes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID4, ID5 are the same as the sizes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3, ID4 of the ninth embodiment. Therefore, the description thereof will be omitted.

As described in the ninth embodiment, the supply current IDB3 having the same amount of current as the current IDB2, which is the sum of the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5, is supplied to the differential pair 10. Therefore, since the current supplied to the differential pair 10 is the sum of the supply current IDB3 and the constant current 2ID, the transconductance gm of each transistor ME1 and ME2 of the differential pair 161 increases. On the other hand, since the currents IDB4 and IDB5 are extracted from the currents IDx flowing through the transistors M1 and M2 by the transistors MB4 and MB5, the increase in the transconductance gm of the active load transistors ME4 and ME5 is suppressed. As described above, the current adjusting unit 120D does not increase the current flowing through the transistors ME4 and ME5 even if the current flowing through the transistors ME1 and ME2 is increased. As a result, the transconductance gm of each transistor ME1 and ME2 of the differential pair 161 increases, while the transconductance gm of each transistor ME4 and ME5 of the cascode current mirror circuit 163 that becomes an active load does not increase. As a result, the noise of the output signal Sout of the operational amplifier 1R can be reduced.

Further, the transistors ME1 to ME21 of the operational amplifier 1R of the present embodiment have the same configuration and manufacturing method as the transistors ME1 to ME21 of the eighteenth embodiment. Therefore, an effect similar to the effects of (18-5) to (18-8) of the 18th embodiment can be obtained.

Further, the transistors MB1 to MB5 of the present embodiment have the same configuration as the transistors MB1 to MB5 of the tenth embodiment. That is, since the transistors MB1 to MB5 are not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MB1 to MB5 is set to the impurity concentration of each transistor ME1, ME2, ME4, ME5, ME8, ME9. It is higher than the impurity concentration in the channel region in. In other words, the impurity concentration in the channel region of each transistor ME1, ME2, ME4, ME5, ME8, ME9 is lower than the impurity concentration in the channel region of each transistor MB1 to MB5. That is, each transistor ME1, ME2, ME4, ME5, ME8, ME9 is a low-concentration transistor, and each transistor MB1 to MB5 is a high-concentration transistor. The impurity concentration in the channel region of each of the transistors ME1, ME2, ME4, ME5, ME8, and ME9 is preferably about 1/2 or less of the impurity concentration in the channel region of each of the transistors MB1 to MB5. In the present embodiment, the impurity concentration in the channel region of each transistor ME1, ME2, ME4, ME5, ME8, ME9 is about 1/10 of the impurity concentration in the channel region of each transistor MB1 to MB5. Further, each of the transistors MB1 to MB5 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(20-1) While the current supplied to the differential pair 161 is increased by the current adjusting unit 120D, the current supplied to the active load is not increased, so that the transconductance of the transistors ME1 and ME2 of the differential pair 161 increases. , The increase in the transconductance of each transistor ME4 and ME5 of the active load is suppressed. Therefore, the noise of the output signal Sout of the operational amplifier 1R can be reduced.

(20-2) The impurity concentration in the channel region of the third transistor ME3 of the constant current source 162, the impurity concentration in the channel region of the transistors ME10 and ME11 of the bias circuit 164, and the transistors ME12 and ME16 of the class AB bias circuit 165. , The impurity concentration in the channel region of ME17 and ME19, the impurity concentration in the channel region of the 20th transistor ME20 of the output stage 166, and the impurity concentration in the channel region in each of the transistors MB1 and MB3 of the current adjusting unit 120D are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the third transistor ME3, a step of forming the N-type well layer 63 of each transistor ME10, ME11, and an N-type well of each transistor ME12, ME16, ME17, ME19. The step of forming the layer 63, the step of forming the N-type well layer 63 of the 20th transistor ME20, and the step of forming the N-type well layer 63 of each of the transistors MB1 and MB3 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1R can be simplified.

(20-3) The impurity concentration in the channel region of each transistor ME6 and ME7 of the cascode current mirror circuit 163, the impurity concentration in the channel region of each transistor ME13 to ME15 of the class AB bias circuit 165, and the 21st transistor of the output stage 166. The impurity concentration in the channel region of ME21 and the impurity concentration in the channel region of each transistor MB2, MB4, MB5 of the current adjusting unit 120D are equal to each other. According to this configuration, a step of forming the P-type well layer 41 of each transistor ME6 and ME7, a step of forming the P-type well layer 41 of each transistor ME13 to ME15, and a step of forming the P-type well layer 41 of the 21st transistor ME21 are formed. And the steps of forming the P-type well layer 41 of each transistor MB2, MB4, MB5 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1R can be simplified.

(Variation example of the 20th embodiment)
The operational amplifier 1R of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

-A regulated current source 125 may be added to the operational amplifier 1R as in the operational amplifier 1H of the eleventh embodiment. The connection configuration of the transistor MB6 of the adjustment current source 125 and each of the transistors MB2, MB4, MB5 is the same as that of the eleventh embodiment.

A first resistor R1, a second resistor R2, and a third resistor R3 may be added to the operational amplifier 1R. In this case, a connection configuration such as the current adjusting unit 120A of the twelfth embodiment may be used. That is, the first resistance R1 is provided between the fourth transistor ME4 and the second power supply wiring 3, and the second resistance R2 is provided between the fifth transistor ME5 and the second power supply wiring 3. The resistor R3 is provided between the second supply transistor MB2 and the second power supply wiring 3. The drain of the first branching transistor MB4 is connected to the drain of the first transistor ME1, the source of the first branching transistor MB4 is connected between the source of the fourth transistor ME4 and the first resistor R1, and the first The gate of the branching transistor MB4 is connected to the gate of the fourth transistor ME4. The drain of the second branching transistor MB5 is connected to the drain of the second transistor ME2, the source of the second branching transistor MB5 is connected between the source of the fifth transistor ME5 and the second resistor R2, and the second The gate of the branching transistor MB5 is connected to the gate of the fourth transistor ME4. According to this configuration, the source potentials of the active load transistors ME4 and ME5 can be increased by the first resistance R1 and the second resistance R2 connected to the active load, so that the current flowing through the transistors ME4 and ME5 can be increased. It works in the direction of reducing. Therefore, since the transconductance gm of each of the transistors ME4 and ME5 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1R can be reduced.

When the first resistor R1, the second resistor R2, and the third resistor R3 are added to the operational amplifier 1R, the connection configuration may be such that the current adjusting unit 120B of the 14th embodiment. In this case, a fourth resistor R4 and a fifth resistor R5 are further added to the operational amplifier 1R. The fourth resistance R4 is provided between the source of the first branch transistor MB4 and the second power supply wiring 3, and the fifth resistance R5 is the source of the second branch transistor MB5 and the second power supply wiring 3. It is provided between.

-For each transistor ME1, ME2, ME4, ME5, ME8, ME9, instead of lowering the impurity concentration in the channel region, an embedded channel type MOSFET such as each transistor M1 to M4 of the second embodiment is applied. You may. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two of the sets of ME9 may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor ME1, ME2, ME4, ME5, ME8, ME9, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors ME1, ME2, ME4, ME5, ME8, and ME9 may have the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two sets of ME9 may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, a set of each transistor ME1 and ME2 constituting the differential pair 161, a set of each transistor ME4 and ME5 constituting the current source of the cascode current mirror circuit 163, and each transistor ME8 constituting the current source of the bias circuit 164, Any one or two sets of ME9 may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1R has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(21st Embodiment)
The operational amplifier 1S of the 21st embodiment will be described with reference to FIG. 38.
The operational amplifier 1S amplifies the potential difference between the inverting input terminal INN and the non-inverting input terminal INP, and outputs an output signal Sout from the output terminal (not shown). The operational amplifier 1S includes a constant current generation unit 170A, a differential amplification stage 170B, a first backgate bias circuit 20A, and a second backgate bias circuit 20B. The operational amplifier 1S is integrally integrated on one semiconductor substrate.

The constant current generation unit 170A has a first transistor MF1 to a third transistor MF3. In the present embodiment, the first transistor MF1 and the second transistor MF2 are P-channel MOSFETs, and the third transistor MF3 is an N-channel MOSFET. The source of the first transistor MF1 and the source of the second transistor MF2 are connected to the first power supply wiring 2. The drain of the first transistor MF1 is connected to the bias terminal BIAS. The drain of the second transistor MF2 is connected to the drain of the third transistor MF3. The source of the third transistor MF3 is connected to the second power supply wiring 3, and the gate of the third transistor MF3 is connected to the drain of the third transistor MF3. The bias voltage Vbp1 is input to the source and gate of the first transistor MF1 and the gate of the second transistor MF2 by the first bias circuit (not shown) connected to the bias terminal BIAS.

The differential amplification stage 170B includes a first differential pair 171 and a second differential pair 172, a first constant current source 173, a second constant current source 174, a current switching unit 175, and a cascode current mirror circuit 176. A bias circuit 177 and a class AB bias circuit 178 are provided.

The first differential pair 171 has a fourth transistor MF4 and a fifth transistor MF5. The fourth transistor MF4 and the fifth transistor MF5 of this embodiment are N-channel MOSFETs. The fourth transistor MF4 and the fifth transistor MF5 may have either a depletion type structure or an enhancement type structure. In the present embodiment, the fourth transistor MF4 and the fifth transistor MF5 have an enhancement type structure. The source of the fourth transistor MF4 and the source of the fifth transistor MF5 are commonly connected. The drain of the fourth transistor MF4 and the drain of the fifth transistor MF5 are connected to the bias circuit 177. The gate of the 4th transistor MF4 is connected to the non-inverting input terminal INP, and the gate of the 5th transistor MF5 is connected to the inverting input terminal INN.

The first constant current source 173 has a sixth transistor MF6 connected to the first differential pair 171. The sixth transistor MF6 of this embodiment is an N-channel MOSFET. The drain of the sixth transistor MF6 is connected to the source of the fourth transistor MF4 and the fifth transistor MF5, and the source of the sixth transistor MF6 is connected to the second power supply wiring 3. The gate of the sixth transistor MF6 is connected to the gate of the third transistor MF3. As a result, the current mirror circuit is formed by the third transistor MF3 and the sixth transistor MF6.

The second differential pair 172 has a seventh transistor MF7 and an eighth transistor MF8. The seventh transistor MF7 and the eighth transistor MF8 of this embodiment are P-channel MOSFETs. The 7th transistor MF7 and the 8th transistor MF8 may have either a depletion type structure or an enhancement type structure. In the present embodiment, the 7th transistor MF7 and the 8th transistor MF8 have an enhancement type structure. The source of the 7th transistor MF7 and the source of the 8th transistor MF8 are commonly connected. The drains of the 7th transistor MF7 and the 8th transistor MF8 are connected to the cascode current mirror circuit 176. The gate of the 7th transistor MF7 is connected to the non-inverting input terminal INP, and the gate of the 8th transistor MF8 is connected to the inverting input terminal INN.

The second constant current source 174 has a ninth transistor MF9 connected to a second differential pair 172. The ninth transistor MF9 of this embodiment is a P-channel MOSFET. The drain of the 9th transistor MF9 is connected to the source of the 7th transistor MF7 and the 8th transistor MF8, and the source of the 9th transistor MF9 is connected to the first power supply wiring 2. The gate of the 9th transistor MF9 is connected to the gate of the 2nd transistor MF2. As a result, the current mirror circuit is formed by the second transistor MF2 and the ninth transistor MF9. Further, a bias voltage Vbp1 is input from the first bias circuit to the gate of the second transistor MF2.

The cascode current mirror circuit 176 is connected to a second differential pair 172. The cascode current mirror circuit 176 is configured by stacking two transistors of the same type, and includes the tenth transistor MF10 to the thirteenth transistor MF13. In the present embodiment, the 10th transistor MF10 to the 13th transistor MF13 are composed of N-channel MOSFETs. In particular, the tenth transistor MF10 and the eleventh transistor MF11 have an enhancement type structure.

The tenth transistor MF10 is provided in series with the seventh transistor MF7. More specifically, the tenth transistor MF10 is provided between the drain of the seventh transistor MF7 and the second power supply wiring 3. The eleventh transistor MF11 is provided in series with the eighth transistor MF8. More specifically, the eleventh transistor MF 11 is provided between the drain of the eighth transistor MF 8 and the second power supply wiring 3. The twelfth transistor MF12 is vertically stacked on the tenth transistor MF10, and the thirteenth transistor MF13 is vertically stacked on the eleventh transistor MF11. More specifically, the source of the 10th transistor MF10 and the source of the 11th transistor MF11 are connected to the second power supply wiring 3. The drain of the 10th transistor MF10 is connected to the source of the 12th transistor MF12, and the drain of the 11th transistor MF11 is connected to the source of the 13th transistor MF13. The gates of the 12th transistor MF12 and the 13th transistor MF13 are connected to a second bias circuit (not shown). The gates of the twelfth transistor MF12 and the thirteenth transistor MF13 are appropriately biased by inputting the bias voltage Vbn1 from the second bias circuit. The gate of the 10th transistor MF10 and the gate of the 11th transistor MF11 are connected to the drain of the 13th transistor MF13. With this connection, even if the 4th transistor MF4, the 5th transistor MF5, the 7th transistor MF7, and the 8th transistor MF8 are enhancement type, low voltage and input full swing (Rail-to-Rail) can be realized.

The bias circuit 177 is a constant current circuit that maintains the cascode current mirror circuit 176 in an appropriate bias state. In one example, the bias circuit 177 is configured by stacking two transistors of the same type, and includes the 14th transistor MF14 to the 17th transistor MF17. In the present embodiment, the 14th transistor MF14 to the 17th transistor MF17 are P-channel MOSFETs. In particular, the 14th transistor MF14 and the 15th transistor MF15 are enhancement type.

The 14th transistor MF14 and the 15th transistor MF15 form a current source that generates a predetermined current. The 14th transistor MF14 is provided in series with the 4th transistor MF4. More specifically, the 14th transistor MF 14 is provided between the drain of the 4th transistor MF 4 and the first power supply wiring 2. The fifteenth transistor MF15 is provided in series with the fifth transistor MF5. More specifically, the fifteenth transistor MF15 is provided between the drain of the fifth transistor MF5 and the first power supply wiring 2. The gates of the 14th transistor MF14 and the 15th transistor MF15 are connected to a second bias circuit (not shown). The gates of the 14th transistor MF14 and the 15th transistor MF15 are appropriately biased by inputting a bias voltage Vbp2 from the third bias circuit. The 16th transistor MF16 is vertically stacked on the 14th transistor MF14, and the 17th transistor MF17 is vertically stacked on the 15th transistor MF15. More specifically, the drain of the 16th transistor MF16 is connected to the source of the 14th transistor MF14, and the drain of the 17th transistor MF17 is connected to the source of the 15th transistor MF15. The gates of the 16th transistor MF16 and the 17th transistor MF17 are connected to a fourth bias circuit (not shown). The gates of the 16th transistor MF16 and the 17th transistor MF17 are appropriately biased by inputting a bias voltage Vbp3 from the third bias circuit.

The current switching unit 175 has a first resistance RF1, a second resistance RF2, and a third resistance RF3, which are three resistances connected in series between the first power supply wiring 2 and the second power supply wiring 3. .. The first terminal of the first resistance RF1 is connected to the first power supply wiring 2, and the second terminal of the first resistance RF1 is connected to the first terminal of the second resistance RF2. The second terminal of the second resistance RF2 is connected to the first terminal of the third resistance RF3, and the second terminal of the third resistance RF3 is connected to the second power supply wiring 3.

Further, the current switching unit 175 has a first switching unit 175A connected to the first differential pair 171 and a second switching unit 175B connected to the second differential pair 172.
The first switching unit 175A has an 18th transistor MF18 and a 19th transistor MF19. In the present embodiment, the 18th transistor MF18 and the 19th transistor MF19 are enhancement type N-channel MOSFETs. The drain of the 18th transistor MF18 is connected to the drain of the 4th transistor MF4, and the drain of the 19th transistor MF19 is connected to the drain of the 5th transistor MF5. The source of the 18th transistor MF18 and the source of the 19th transistor MF19 are commonly connected and connected to the node NI1 between the source of the 4th transistor MF4 and the 5th transistor MF5 and the drain of the 6th transistor MF6. The gate of the 18th transistor MF18 and the gate of the 19th transistor MF19 are commonly connected and connected to the node NI2 between the second resistance RF2 and the third resistance RF3.

The second switching unit 175B has a 20th transistor MF20 and a 21st transistor MF21. In the present embodiment, the 20th transistor MF20 and the 21st transistor MF21 are enhancement type P-channel MOSFETs. The drain of the 20th transistor MF20 is connected to the drain of the 7th transistor MF7, and the drain of the 21st transistor MF21 is connected to the drain of the 8th transistor MF8. The source of the 20th transistor MF20 and the source of the 21st transistor MF21 are commonly connected and connected to the node NI3 between the drain of the 9th transistor MF9 and the source of the 7th transistor MF7 and the 8th transistor MF8. The gate of the 20th transistor MF20 and the gate of the 21st transistor MF21 are commonly connected and connected to the node NI4 between the first resistance RF1 and the second resistance RF2. Further, the drain of the 20th transistor MF 20 is connected to the second switching terminal Gm N , and the drain of the 21st transistor MF 21 is connected to the first switching terminal Gm P. The second switching terminal Gm N is connected to the drain of the seventh transistor MF7, and the first switching terminal Gm P is connected to the drain of the eighth transistor MF8.

The class AB bias circuit 178 is provided between the cascode current mirror circuit 176 and the bias circuit 177. More specifically, the class AB bias circuit 178 is provided between the drain of the 16th transistor MF16 of the bias circuit 177 and the drain of the 12th transistor MF12 of the cascode current mirror circuit 176. The class AB bias circuit 178 is an output buffer circuit that includes a plurality of transistors and draws a large drive current during operation from a small bias current during bias. The class AB bias circuit 178 is connected to the output stage (not shown) of the operational amplifier 1S.

The first backgate bias circuit 20A is connected to the common backgate of the fourth transistor MF4 and the fifth transistor MF5 of the first differential pair 171 and the second power supply wiring 3. The first backgate bias circuit 20A of the present embodiment has a configuration in which the conductive type of each transistor of the backgate bias circuit 20 (see FIG. 2) of the first embodiment is changed. The first backgate bias circuit 20A sets a bias voltage VB such that the backgate source voltage VBS is closer to the second power supply voltage VSS than the source potentials of the fourth transistor MF4 and the fifth transistor MF5, and the fourth transistor MF4 and the fourth transistor MF4. It is applied to the back gate of the fifth transistor MF5. In other words, the first backgate bias circuit 20A has a voltage on the second power supply voltage VSS side of the intermediate voltage between the source potential of the fourth transistor MF4 and the fifth transistor MF5 and the second power supply voltage VSS. A bias voltage VB is applied to the back gates of the fourth transistor MF4 and the fifth transistor MF5. That is, the first backgate bias circuit 20A applies a bias voltage VB such that the backgate-source voltage VBS becomes large to the back gates of the fourth transistor MF4 and the fifth transistor MF5. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be lower than the second power supply voltage VSS. In this case, the bias voltage VB is preferably lower than the second power supply voltage VSS within a range in which the parasitic diodes of the fourth transistor MF4 and the fifth transistor MF5 are not turned on. The bias voltage VB is preferably a voltage excluding the voltage within a predetermined range including the second power supply voltage VSS, which is the same as the second power supply voltage VSS. In one example, the bias voltage VB is preferably a voltage excluding the same voltage as the second power supply voltage VSS among the voltages within ± 20% of the second power supply voltage VSS. As a result, the backgate-source voltage VBS becomes a voltage excluding the backgate-source voltage VBSH among the voltages within ± 20% of the backgate-source voltage VBSH.

The second backgate bias circuit 20B is connected to the common backgate of the seventh transistor MF7 and the eighth transistor MF8 of the second differential pair 172 and the first power supply wiring 2. The second backgate bias circuit 20B of the present embodiment has the same configuration as the backgate bias circuit 20 of the first embodiment (see FIG. 2). The second backgate bias circuit 20B sets the bias voltage VB so that the bias voltage VB is closer to the first power supply voltage VDD than the source potential of the seventh transistor MF7 and the eighth transistor MF8, and the backgate of the seventh transistor MF7 and the eighth transistor MF8. Apply to. In other words, the second backgate bias circuit 20B has a voltage on the first power supply voltage VDD side of the intermediate voltage between the source potential of the seventh transistor MF7 and the eighth transistor MF8 and the first power supply voltage VDD. A bias voltage VB is applied to the back gates of the 7th transistor MF7 and the 8th transistor MF8. That is, the second backgate bias circuit 20B applies a bias voltage VB such that the backgate-source voltage VBS becomes large to the back gates of the seventh transistor MF7 and the eighth transistor MF8. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be higher than the first power supply voltage VDD. In this case, the bias voltage VB is preferably higher than the first power supply voltage VDD within a range in which the parasitic diodes of the 7th transistor MF7 and the 8th transistor MF8 are not turned on. An example of the voltage at which the parasitic diode of the seventh transistor MF7 and the eighth transistor MF8 is turned on is a voltage 0.5 to 0.6 V higher than the first power supply voltage VDD (VDD + 0.5 to 0.6). The backgate-source voltage VBS is preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within a predetermined range including the first power supply voltage VDD. More specifically, the bias voltage VB is more preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within ± 20% of the first power supply voltage VDD. As a result, the backgate-source voltage VBS becomes a voltage excluding the backgate-source voltage VBSH among the voltages within ± 20% of the backgate-source voltage VBSH.

Further, in the present embodiment, in order to further reduce the 1 / f noise of the output signal Sout of the operational amplifier 1S, the impurity concentration in the channel region of some of the transistors of the operational amplifier 1S is set to the channel region of the other transistors. It is lower than the impurity concentration. That is, the plurality of transistors of the operational amplifier 1S include a high-concentration transistor in which the impurity concentration in the channel region is the first concentration and a low-concentration transistor in which the impurity concentration in the channel region is a second concentration lower than the first concentration. Specifically, among the transistors of the operational amplifier 1S, the impurity concentration in the channel region in the transistor that is easily affected by the 1 / f noise of the output signal Sout is measured in the transistor that is not easily affected by the 1 / f noise of the output signal Sout. It is lower than the impurity concentration in the channel region. That is, a low-concentration transistor is used for a transistor that is more susceptible to 1 / f noise of the output signal Sout among a plurality of transistors than a high-concentration transistor, and a high-concentration transistor is more than a plurality of low-concentration transistors. It is used for a transistor that is not easily affected by 1 / f noise of the output signal Sout among the transistors. More specifically, in the operational amplifier 1S, the parts susceptible to 1 / f noise of the output signal Sout are the first differential pair 171 and the second differential pair 172, the current switching unit 175, and the cascode current mirror circuit. It is a part of 176 and a part of a bias circuit 177. On the other hand, in the operational amplifier 1S, the parts that are not easily affected by the 1 / f noise of the output signal Sout are the constant current generator 170A, the first constant current source 173, the second constant current source 174, and the class AB bias circuit 178. And each back gate bias circuit 20A, 20B.

In the present embodiment, the channel region of the transistor constituting the first differential pair 171 and the second differential pair 172, the current switching unit 175, a part of the cascode current mirror circuit 176, and a part of the bias circuit 177. The impurity concentration is determined from the impurity concentration in the channel region constituting the constant current generator 170A, the first constant current source 173, the second constant current source 174, the AB class bias circuit 178, and the back gate bias circuits 20A and 20B. Is also low. That is, the first differential pair 171 and the second differential pair 172, the current switching unit 175, a part of the cascode current mirror circuit 176, and a part of the bias circuit 177 are low-concentration transistors, and are constant. The transistors of the current generator 170A, the first constant current source 173, the second constant current source 174, the class AB bias circuit 178, and the backgate bias circuits 20A and 20B are high-concentration transistors. Specifically, the 4th transistor MF4, the 5th transistor MF5, the 7th transistor MF7, the 8th transistor MF8, the 10th transistor MF10, the 11th transistor MF11, the 14th transistor MF14, the 15th transistor MF15, and the 18th transistor MF18. The impurity concentration in the channel region of the 21st transistor MF21 is adjusted to the 1st transistor MF1 to the 3rd transistor MF3, the 6th transistor MF6, the 9th transistor MF9, the 12th transistor MF12, the 13th transistor MF13, the 16th transistor MF16, and the 17th. It is lower than the impurity concentration in the channel region of the transistor MF17 and the transistors of the back gate bias circuits 20A and 20B. That is, the 4th transistor MF4, the 5th transistor MF5, the 7th transistor MF7, the 8th transistor MF8, the 10th transistor MF10, the 11th transistor MF11, the 14th transistor MF14, the 15th transistor MF15, and the 18th transistor MF18-21. The transistor MF21 is a low concentration transistor. On the other hand, the first transistor MF1 to the third transistor MF3, the sixth transistor MF6, the ninth transistor MF9, the twelfth transistor MF12, the thirteenth transistor MF13, the sixteenth transistor MF16, the seventeenth transistor MF17, and each backgate bias circuit 20A, The 20B transistor is a high concentration transistor.

The impurity concentrations in the channel region of each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 are the respective transistors MF1 to MF3, MF6, MF9, MF12, MF13, MF16, MF17 and each backgate. It is preferable that the impurity concentration in the channel region of the transistors of the bias circuits 20A and 20B is about 1/2 or less. In the present embodiment, the impurity concentration in the channel region in each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 is the impurity concentration of each transistor MF1 to MF3, MF6, MF9, MF12, MF13, MF16, It is about 1/10 of the impurity concentration in the channel region in the transistor of the MF17 and the back gate bias circuits 20A and 20B. The plurality of transistors of the back gate bias circuits 20A and 20B are surface channel type MOSFETs.

The structures and manufacturing methods of the N-channel MOSFETs and P-channel MOSFETs of the transistors MF1 to MF21 are the same structures and manufacturing methods as those of the N-channel MOSFETs and P-channel MOSFETs such as the first transistor M1 of the first embodiment.

According to this embodiment, the following effects can be obtained.
(21-1) The first backgate bias circuit 20A is a backgate of the fourth transistor MF4 and the fifth transistor MF5 of the first differential pair 171 (N-type well layer 39 of the fourth transistor MF4 and the fifth transistor MF5). In the contact region for applying the bias voltage VB by the first backgate bias circuit 20A), a bias voltage VB closer to the second power supply voltage VSS than the source potential of the fourth transistor MF4 and the fifth transistor MF5 is applied. do. As a result, the backgate-source voltage VBS of the fourth transistor MF4 and the fifth transistor MF5 becomes large. As a result, the transconductance gm of the fourth transistor MF4 and the fifth transistor MF5 becomes large, so that the noise of the output signal Sout of the operational amplifier 1S can be reduced.

Further, the second backgate bias circuit 20B is the second in the back gate of the seventh transistor MF7 and the eighth transistor MF8 of the second differential pair 172 (the N-type well layer 39 of the seventh transistor MF7 and the eighth transistor MF8). The backgate bias circuit 20B applies a bias voltage VB closer to the first power supply voltage VDD than the source potential of the seventh transistor MF7 and the eighth transistor MF8 to the contact region for applying the bias voltage VB). As a result, the transconductance gm of the 7th transistor MF7 and the 8th transistor MF8 becomes large, so that the noise of the output signal Sout of the operational amplifier 1S can be reduced.

(21-2) In the first backgate bias circuit 20A, the bias voltage VB is made lower than the second power supply voltage VSS, so that the transconductance gm of the fourth transistor MF4 and the fifth transistor MF5 becomes larger. The noise of the output signal Sout of the operational amplifier 1S can be further reduced.

Further, in the second backgate bias circuit 20B, by making the bias voltage VB larger than the first power supply voltage VDD, the transconductance gm of the seventh transistor MF7 and the eighth transistor MF8 becomes larger, so that the operational amplifier 1S has a larger transconductance gm. The noise of the output signal Sout can be further reduced.

(21-3) By setting the bias voltage VB to a voltage lower than the voltage at which the parasitic diode of the 7th transistor MF7 and the 8th transistor MF8 is turned on, the 7th transistor MF7 and the 8th transistor MF8 can operate stably.

(21-4) By setting the bias voltage VB to a voltage other than the same voltage as the first power supply voltage VDD within a predetermined range including the first power supply voltage VDD, the backgate-source voltage VBS becomes large. Therefore, the transconductance gm of the 7th transistor MF7 and the 8th transistor MF8 becomes large, and the 7th transistor MF7 and the 8th transistor MF8 can operate stably. In particular, by setting the bias voltage VB to a voltage other than the voltage within ± 20% of the first power supply voltage VDD, which is the same as the first power supply voltage VDD, the backgate source voltage VBS becomes the backgate source. Since the voltage is near the VFSH, the transconductance gm of the 7th transistor MF7 and the 8th transistor MF8 becomes large, and the 7th transistor MF7 and the 8th transistor MF8 can operate more stably.

(21-5) The impurity concentration in the channel region in the fourth transistor MF4 and the fifth transistor MF5 constituting the first differential pair 171 is the sixth transistor MF6 and the first back constituting the first constant current source 173. It is lower than the impurity concentration in the channel region in the transistor of the gate bias circuit 20A. Further, the impurity concentration in the channel region in the seventh transistor MF7 and the eighth transistor MF8 constituting the second differential pair 172 is the ninth transistor MF9 and the second backgate bias circuit constituting the second constant current source 174. It is lower than the impurity concentration in the channel region in the 20B transistor. According to such a configuration, the impurity concentration in the channel region of each transistor MF4, MF5, MF7, MF8 constituting each differential pair 171 and 172 which is easily affected by 1 / f noise of the output signal Sout of the operational amplifier 1S can be determined. By lowering the value, fluctuations in mobility can be suppressed and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1S can be effectively suppressed.

(21-6) The impurity concentration in the channel region of the tenth transistor MF10 and the eleventh transistor MF11 constituting the current source of the cascode current mirror circuit 176 is the sixth transistor MF6 and the first transistor constituting the first constant current source 173. It is lower than the impurity concentration in the channel region in the transistor of the backgate bias circuit 20A. According to this configuration, the impurity concentration in the channel region of each of the transistors MF10 and MF11 constituting the current source of the cascode current mirror circuit 176, which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1S, is lowered. Fluctuations in mobility can be suppressed, and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1S can be effectively suppressed.

(21-7) The impurity concentration in the channel region of the 14th transistor MF14 and the 15th transistor MF15 constituting the current source of the bias circuit 177 is the 9th transistor MF9 and the 2nd backgate constituting the second constant current source 174. It is lower than the impurity concentration in the channel region in the transistor of the bias circuit 20B. According to this configuration, the mobility is reduced by lowering the impurity concentration in the channel region of each of the transistors MF14 and MF15 constituting the current source of the bias circuit 177 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1S. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1S can be effectively suppressed.

(21-8) The impurity concentration in the channel region of the 18th transistor MF18 and the 19th transistor MF19 constituting the first switching unit 175A of the current switching unit 175 is the sixth transistor MF6 constituting the first constant current source 173. And lower than the impurity concentration in the channel region in the transistor of the first backgate bias circuit 20A. Further, the impurity concentration in the channel region of the 20th transistor MF20 and the 21st transistor MF21 constituting the second switching unit 175B is the ninth transistor MF9 and the second backgate bias circuit 20B constituting the second constant current source 174. It is lower than the impurity concentration in the channel region of the transistor. According to such a configuration, the mobility is reduced by lowering the impurity concentration in the channel region of each of the transistors MF18 to MF21 constituting the current switching unit 175 which is easily affected by the 1 / f noise of the output signal Sout of the operational amplifier 1S. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the operational amplifier 1S can be effectively suppressed.

(21-9) The impurity concentration in the channel region of each transistor MF10 and MF11 constituting the current source of the cascode current mirror circuit 176, and the impurity concentration in the channel region of each transistor MF1 and MF2 constituting the first differential pair 171. And the impurity concentrations in the channel regions of the transistors MF18 and MF19 constituting the first switching unit 175A are equal to each other. According to this configuration, a step of forming a P-type well layer 62 of each transistor MF1 and MF2, a step of forming a P-type well layer 62 of each transistor MF10 and MF11, and a step of forming a P-type well layer 62 of each transistor MF18 and MF19. The process of forming 62 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1S can be simplified.

(21-10) Impurity concentration in the channel region of each transistor MF14 and MF15 constituting the current source of the bias circuit 177, and impurity concentration in the channel region of each transistor MF7 and MF8 constituting the second differential pair 172. The impurity concentrations in the channel regions of the transistors MF20 and MF21 constituting the second switching unit 175B are equal to each other. According to this configuration, a step of forming an N-type well layer 70 of each transistor MF14 and MF15, a step of forming an N-type well layer 70 of each transistor MF7 and MF8, and a step of forming an N-type well layer 70 of each transistor MF20 and MF21. The steps of forming the 70 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1S can be simplified.

(Modified example of the 21st embodiment)
The operational amplifier 1S of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

-Any one of the first backgate bias circuit 20A and the second backgate bias circuit 20B may be omitted.
In the operational amplifier 1S, in the fifth embodiment, between the first power supply wiring 2 and the first differential pair 171 and more specifically between the first power supply wiring 2 and the first constant current source 173. It is also possible to add a booster circuit 103 (see FIG. 18) of the operational amplifier 1B of FIG. 18, which is a modification. According to this configuration, the same effect as that of the operational amplifier 1B of FIG. 18 can be obtained. Further, in the operational amplifier 1S, in the fifth embodiment, between the first power supply wiring 2 and the second differential pair 172, more specifically, between the first power supply wiring 2 and the second constant current source 174. A step-down circuit 100 (see FIG. 17) can also be added. According to this configuration, the same effect as that of the fifth embodiment can be obtained.

The first backgate bias circuit 20A can also be connected to the fourth power supply wiring 5 like the backgate bias circuit 20 of the operational amplifier 1C of FIG. 20, which is a modification of the sixth embodiment. According to this configuration, the same effect as that of the operational amplifier 1C of FIG. 20 can be obtained. Further, the second backgate bias circuit 20B can also be connected to the third power supply wiring 4 as in the backgate bias circuit 20 of the sixth embodiment shown in FIG. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

The specific circuit configuration of the current switching unit 175 is arbitrary as long as its function can be realized, and is not limited to the circuit configuration of the present embodiment.
-For each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21, instead of lowering the impurity concentration in the channel region, like each transistor M1 to M4 of the second embodiment. Embedded channel MOSFETs may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, each transistor MF4, MF5 constituting the first differential pair 171, each transistor MF7, MF8 constituting the second differential pair 172, and each transistor MF10, MF11 constituting the current source of the cascode current mirror circuit 176. First implementation of each transistor MF14, MF15 constituting the current source of the bias circuit 177, each transistor MF18, MF19 constituting the first switching unit 175A, and each transistor MF20, MF21 constituting the second switching unit 175B. The low-concentration transistor of the embodiment and the embedded channel MOSFET of the second embodiment may be mixed.

-For each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 may have the same structure as the structure of each transistor M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor MF4 and MF5 constituting the first differential pair 171, a set of each transistor MF7 and MF8 constituting the second differential pair 172, and each constituting a current source of the cascode current mirror circuit 176. A set of transistors MF10 and MF11, a set of transistors MF14 and MF15 constituting the current source of the bias circuit 177, a set of transistors MF18 and MF19 constituting the first switching unit 175A, and a second switching unit 175B. The set of the transistors MF20 and MF21 may be changed so that the same structures as those of the low-concentration transistor of the first embodiment and the transistors M1 to M4 of the third embodiment are mixed. Further, a set of each transistor MF4 and MF5 constituting the first differential pair 171, a set of each transistor MF7 and MF8 constituting the second differential pair 172, and each constituting a current source of the cascode current mirror circuit 176. A set of transistors MF10 and MF11, a set of transistors MF14 and MF15 constituting the current source of the bias circuit 177, a set of transistors MF18 and MF19 constituting the first switching unit 175A, and a second switching unit 175B. The set of each transistor MF20 and MF21 is mixed with the low concentration transistor of the first embodiment, the embedded channel type MOSFET of the second embodiment, and the structure similar to the structure of each of the transistors M1 to M4 of the third embodiment. May be changed to. In short, the operational amplifier 1S has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(22nd Embodiment)
The operational amplifier 1T of the 22nd embodiment will be described with reference to FIG. 39. In the operational amplifier 1T of the present embodiment, the back gate bias circuits 20A and 20B are omitted as compared with the operational amplifier 1S of the 21st embodiment, and the first control unit 110A, the second control unit 110B, and the second control unit 110B of the eighth embodiment are omitted. The difference is that the 1st resistance R1, the 2nd resistance R2, and the 3rd resistance R3 are added.

The first control unit 110A controls the source potential of the 11th transistor MF 11 by controlling the current supplied to the node NI 5 between the source of the 11th transistor MF 11 and the first resistor R1. The first control transistor MA1 of the first control unit 110A of the present embodiment is an N-channel MOSFET. The first constant current source 111 includes a transistor (not shown). The transistor of the first constant current source 111 is a P-channel MOSFET. The drain of the transistor of the first constant current source 111 is connected to the drain of the first control transistor MA1, and the source of the transistor is connected to the first power supply wiring 2. The source of the first control transistor MA1 is connected to the node NI5 between the source of the eleventh transistor MF11 and the first resistance R1, and the gate of the first control transistor MA1 is connected to the gate and drain of the eleventh transistor MF11. It is connected. With this configuration, the first control unit 110A supplies the node NI 5 with a first current Ic1 proportional to the constant current It of the constant current source 174.

The second control unit 110B controls the source potential of the tenth transistor MF10 by controlling the current supplied to the node NI6 between the source of the tenth transistor MF10 and the second resistor R2. The second control transistor MA2 of the second control unit 110B of the present embodiment is an N-channel MOSFET. The second constant current source 112 includes a transistor (not shown). The transistor of the second constant current source 112 is a P-channel MOSFET. The drain of the transistor of the second constant current source 112 is connected to the drain of the second control transistor MA2, and the source of the transistor is connected to the first power supply wiring 2. The source of the second control transistor MA2 is connected to the node NI6 between the source of the tenth transistor MF10 and the second resistance R2, and the gate of the second control transistor MA2 is connected to the gate of the eleventh transistor MF11. Has been done. With this configuration, the second control unit 110B supplies the node NI 6 with a second current Ic2 proportional to the constant current It of the constant current source 174.

As described above, the source of the 11th transistor MF11 is supplied with the first current Ic1 from the first control unit 110A, and the source of the tenth transistor MF10 is supplied with the second current Ic2 from the second control unit 110B. , The source potential of the 11th transistor MF11 and the source potential of the 10th transistor MF10 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the 11th transistor MF11 and the 10th transistor MF10. As described above, in the present embodiment, the source potentials of the transistors MF10 and MF11 are further increased. Therefore, the transconductance gm on the circuit is reduced.

Further, the transistors MF1 to MF21 of the operational amplifier 1T of the present embodiment have the same configuration and manufacturing method as the transistors MF1 to MF21 of the 21st embodiment. Therefore, an effect similar to the effects of (21-5) to (21-10) of the 21st embodiment can be obtained.

Further, since the first control transistor MA1 and the second control transistor MA2 are not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MA1 and MA2 is set to each transistor MF4. , MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 are higher than the impurity concentration in the channel region. In other words, the impurity concentration in the channel region in each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 is lower than the impurity concentration in the channel region in each transistor MA1 and MA2. That is, each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 are low-concentration transistors, and each transistor MA1 and MA2 are high-concentration transistors. The impurity concentration in the channel region of each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 may be about 1/2 or less of the impurity concentration in the channel region of each transistor MA1 and MA2. preferable. In the present embodiment, the impurity concentration in the channel region of each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 is about 1/10 of the impurity concentration in the channel region of each transistor MA1 and MA2. Is. Further, each transistor MA1 and MA2 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(22-1) By controlling the source potentials of the active load transistors MF10 and MF11 to increase by the control units 110A and 110B, the currents flowing through the transistors MF10 and MF11 are reduced. Therefore, since the transconductance gm of each of the transistors MF10 and MF11 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1T can be reduced.

(22-2) The impurity concentration in the channel region of the first transistor MF1 and the second transistor MF2, the impurity concentration in the channel region of the ninth transistor MF9 of the second constant current source 174, and each transistor MF16 of the bias circuit 177. The impurity concentration in the channel region of the MF 17 and the impurity concentration in the channel region of the transistor of the constant current source 111 of the first control unit 110A and the transistor of the constant current source 112 of the second control unit 110B are equal to each other. According to this configuration, the step of forming the N-type well layer 63 of each transistor MF1 and MF2, the step of forming the N-type well layer 63 of the ninth transistor MF9, and the step of forming the N-type well layer 63 of each transistor MF16 and MF17 are formed. And the steps of forming the N-type well layer 63 of the transistors of the constant current sources 111 and 112 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1T can be simplified.

(22-3) Impurity concentration in the channel region of the third transistor MF3, impurity concentration in the channel region of the sixth transistor MF6 of the first constant current source 173, and channels of the transistors MF12 and MF13 of the cascode current mirror circuit 176. The impurity concentration in the region and the impurity concentration in the channel region of each of the control transistors MA1 and MA2 are equal to each other. According to this configuration, a step of forming the P-type well layer 41 of the third transistor MF3, a step of forming the P-type well layer 41 of the sixth transistor MF6, and forming the P-type well layer 41 of each of the transistors MF12 and MF13. The steps and the steps of forming the P-type well layer 41 of the transistors MA1 and MA2 can be collectively performed. Therefore, the process of manufacturing the operational amplifier 1T can be simplified.

(Variation example of the 22nd embodiment)
The operational amplifier 1T of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The first control unit 110A and the second control unit 110B may be omitted from the operational amplifier 1T. In this case, the source potentials of the transistors MF11 and MF10 are increased by the first resistance R1 and the second resistance R2.

In the operational amplifier 1T, the resistance value of the first resistor R1 and the resistance value of the second resistor R2 may be changed according to the ratio of the tenth transistor MF10 and the eleventh transistor MF11.
-For each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21, instead of lowering the impurity concentration in the channel region, like each transistor M1 to M4 of the second embodiment. Embedded channel MOSFETs may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, each transistor MF4, MF5 constituting the first differential pair 171, each transistor MF7, MF8 constituting the second differential pair 172, and each transistor MF10, MF11 constituting the current source of the cascode current mirror circuit 176. First implementation of each transistor MF14, MF15 constituting the current source of the bias circuit 177, each transistor MF18, MF19 constituting the first switching unit 175A, and each transistor MF20, MF21 constituting the second switching unit 175B. The low-concentration transistor of the embodiment and the embedded channel MOSFET of the second embodiment may be mixed.

-For each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 may have the same structure as the structure of each transistor M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor MF4 and MF5 constituting the first differential pair 171, a set of each transistor MF7 and MF8 constituting the second differential pair 172, and each constituting a current source of the cascode current mirror circuit 176. A set of transistors MF10 and MF11, a set of transistors MF14 and MF15 constituting the current source of the bias circuit 177, a set of transistors MF18 and MF19 constituting the first switching unit 175A, and a second switching unit 175B. The set of the transistors MF20 and MF21 may be changed so that the same structures as those of the low-concentration transistor of the first embodiment and the transistors M1 to M4 of the third embodiment are mixed. Further, a set of each transistor MF4 and MF5 constituting the first differential pair 171, a set of each transistor MF7 and MF8 constituting the second differential pair 172, and each constituting a current source of the cascode current mirror circuit 176. A set of transistors MF10 and MF11, a set of transistors MF14 and MF15 constituting the current source of the bias circuit 177, a set of transistors MF18 and MF19 constituting the first switching unit 175A, and a second switching unit 175B. The set of each transistor MF20 and MF21 is mixed with the low concentration transistor of the first embodiment, the embedded channel type MOSFET of the second embodiment, and the structure similar to the structure of each of the transistors M1 to M4 of the third embodiment. May be changed to. In short, the operational amplifier 1T has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(23rd Embodiment)
The operational amplifier 1U of the 23rd embodiment will be described with reference to FIG. 40. The operational amplifier 1U of the present embodiment is different from the operational amplifier 1T of the 22nd embodiment in that the control units 110A and 110B are omitted and the current adjustment unit 120E is added.

The current adjusting unit 120E makes the current flowing through the 7th transistor MF7 and the 8th transistor MF8 of the second differential pair 172 larger than the current flowing through the 10th transistor MF10 and the 11th transistor MF11 which are active loads. More specifically, the current adjusting unit 120E increases the current flowing through the 7th transistor MF7 and the 8th transistor MF8 more than the constant current It of the constant current source 174, and the current corresponding to the increase of the current flowing through the respective transistors MF7 and MF8. Is prevented from flowing through the 10th transistor MF10 and the 11th transistor MF11. The current adjusting unit 120E has the same configuration as the current adjusting unit 120B of the 14th embodiment, and has a current supply unit 121, a branching unit 122, a third resistance R3, a fourth resistance R4, and a fifth resistance R5.

The current supply unit 121 of the current adjustment unit 120E is a current source provided separately from the constant current source 174, and supplies current to the seventh transistor MF7 and the eighth transistor MF8. The source of the second supply transistor MB2 is connected to the first terminal of the third resistor R3, and the gate of the second supply transistor MB2 is connected to the gate of the eleventh transistor MF11. The second terminal of the third resistance R3 is connected to the second power supply wiring 3.

The branch portion 122 causes each of the increased current of the drain current flowing through the 7th transistor MF 7 and the increased current of the drain current flowing through the 8th transistor MF 8 to the second power supply wiring 3. The branch portion 122 includes a first branch circuit 123 and a second branch circuit 124.

The first branch circuit 123 is connected to the drain of the seventh transistor MF7 and the second power supply wiring 3, and includes the first branch transistor MB4 and the fourth resistor R4. The first branch transistor MB4 and the fourth resistor R4 form a series circuit. The drain of the first branching transistor MB4 is connected to the drain of the seventh transistor MF7, and the source of the first branching transistor MB4 is connected to the first terminal of the fourth resistance R4. The second terminal of the fourth resistance R4 is connected to the second power supply wiring 3. The resistance value of the fourth resistor R4 of the present embodiment is equal to the resistance values of the first resistor R1 and the second resistor R2.

The second branch circuit 124 is connected to the drain of the eighth transistor MF8 and the second power supply wiring 3, and includes the second branch transistor MB5 and the fifth resistor R5. The second branch transistor MB5 and the fifth resistor R5 form a series circuit. The drain of the second branching transistor MB5 is connected to the drain of the eighth transistor MF8, and the source of the second branching transistor MB5 is connected to the first terminal of the fifth resistance R5. The second terminal of the fifth resistance R5 is connected to the second power supply wiring 3. The resistance value of the fifth resistor R5 of the present embodiment is equal to the resistance value of the fourth resistor R4. That is, the resistance value of the fifth resistance R5 is equal to the resistance values of the first resistance R1 and the second resistance R2.

The electrical characteristics of the first branch transistor MB4 of the first branch circuit 123 and the second branch transistor MB5 of the second branch circuit 124 are equal to each other. In addition, since the gate voltages of the transistors MB2, MB4, and MB5 are common, the current amount of the second supply transistor MB2 is 2 of the current amount of the first branch transistor MB4 (second branch transistor MB5). Since it is doubled, the total current flowing through each of the transistors MB4 and MB5 is generated in the second supply transistor MB2.

In the present embodiment, the electrical characteristics of each of the transistors MB4 and MB5 and the tenth transistor MF10 and the eleventh transistor MF11 are set to be equal to each other. In addition, since the gates of the transistors MB4 and MB5 are connected to the gate of the eleventh transistor MF11, the current flowing through the first branching transistor MB4 and the current flowing through the second branching transistor MB5 are different. It is equal to the current flowing through the 11th transistor MF11 (the current flowing through the 10th transistor MF10).

Next, the current flowing through the operational amplifier 1U, particularly the current flowing through the current adjusting unit 120E will be described. In this description, the constant current flowing through the second constant current source 174 is 2 ID. Regarding the magnitudes of the supply current IDB3, current IDB2, IDB4, IDB5, and current ID10, ID11, the supply current IDB3, current IDB2, IDB4, IDB5, and current ID3 of the 14th embodiment (9th embodiment). Since it is the same as the size of ID4, the description thereof will be omitted.

As described in the ninth embodiment, the supply current IDB3 having the same amount of current as the current IDB2, which is the sum of the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5, is supplied to the differential pair 10. Therefore, the current supplied to the differential pair 10 is the sum of the supply current IDB3 and the constant current 2ID, so that the transconductance gm of each transistor MF7 and MF8 increases. On the other hand, since the currents IDB4 and IDB5 are extracted from the currents IDx flowing through the transistors MF7 and MF8 by the transistors MB4 and MB5, the increase in the transconductance gm of the transistors MF10 and MF11 is suppressed. Therefore, the noise of the output signal Sout of the operational amplifier 1U can be reduced.

In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the tenth transistor MF10 and the eleventh transistor MF11. As described above, in the present embodiment, the source potentials of the transistors MF10 and MF11 are further increased. Therefore, the transconductance gm on the circuit of the active load is reduced. As a result, the noise of the output signal Sout of the operational amplifier 1U can be further reduced.

Further, the transistors MF1 to MF21 of the operational amplifier 1U of the present embodiment have the same configuration and manufacturing method as the transistors MF1 to MF21 of the 21st embodiment. Therefore, an effect similar to the effects of (21-5) to (21-10) of the 21st embodiment can be obtained.

Further, since each of the transistors MB1 to MB5 of the current adjusting unit 120E is not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each of the transistors MB1 to MB5 is set to the impurity concentration of each transistor MF4 and MF5 . , MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 are higher than the impurity concentration in the channel region. In other words, the impurity concentration in the channel region in each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 is lower than the impurity concentration in the channel region in each transistor MB1 to MB5. That is, each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 are low concentration transistors, and each transistor MB1 to MB5 is a high concentration transistor. The impurity concentration in the channel region of each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 may be about 1/2 or less of the impurity concentration in the channel region of each transistor MB1 to MB5. preferable. In the present embodiment, the impurity concentration in the channel region of each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 is about 1/10 of the impurity concentration in the channel region of each transistor MB1 to MB5. Is. Further, each transistor MB1 to MB5 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(23-1) Since the current supplied to the second differential pair 172 is increased by the current adjusting unit 120E but the current supplied to the active load is not increased, the transistors MF7 and MF8 of the second differential pair 172 are increased. The transconductance of the active load is increased, and the increase in the transconductance of each of the active load transistors MF10 and MF11 is suppressed. Therefore, the noise of the output signal Sout of the operational amplifier 1U can be reduced.

(23-2) Since the source potentials of the active load transistors MF10 and MF11 can be increased by the first resistance R1 and the second resistance R2 connected to the active load, the current flowing through the transistors MF10 and MF11 is reduced. Move in the direction. Therefore, since the transconductance gm of each of the transistors MF10 and MF11 on the circuit is reduced, the noise of the output signal Sout of the operational amplifier 1U can be reduced.

(23-3) Impurity concentration in the channel region of the first transistor MF1 and the second transistor MF2, the impurity concentration in the channel region of the ninth transistor MF9 of the second constant current source 174, and each transistor MF16 of the bias circuit 177. The impurity concentration in the channel region of the MF 17 and the impurity concentration in the channel region of each of the transistors MB1 and MB3 of the current adjusting unit 120E are equal to each other. According to this configuration, the step of forming the N-type well layer 63 of each transistor MF1 and MF2, the step of forming the N-type well layer 63 of the ninth transistor MF9, and the step of forming the N-type well layer 63 of each transistor MF16 and MF17 are formed. And the steps of forming the N-type well layer 63 of each of the transistors MB1 and MB3 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1U can be simplified.

(23-4) The impurity concentration in the channel region of the third transistor MF3, the impurity concentration in the channel region of the sixth transistor MF6 of the first constant current source 173, and the channels of the transistors MF12 and MF13 of the cascode current mirror circuit 176. The impurity concentration in the region and the impurity concentration in the channel region of each of the transistors MB2, MB4, MB5 of the current adjusting unit 120E are equal to each other. According to this configuration, a step of forming the P-type well layer 41 of the third transistor MF3, a step of forming the P-type well layer 41 of the sixth transistor MF6, and forming the P-type well layer 41 of each of the transistors MF12 and MF13. The step and the step of forming the P-type well layer 41 of each transistor MB2, MB4, MB5 can be performed collectively. Therefore, the process of manufacturing the operational amplifier 1U can be simplified.

(Modified example of the 23rd embodiment)
The operational amplifier 1U of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the operational capacitor 1U, the resistance value of the first resistance R1, the resistance value of the second resistance R2, the resistance value of the third resistance R3, the resistance value of the fourth resistance R4, and the resistance value of the fifth resistance R5 are set to the 11th transistor MF11. , The tenth transistor MF10, the second supply transistor MB2, the first branch transistor MB4, and the second branch transistor MB5 may be changed according to the ratio.

The fourth resistor R4 and the fifth resistor R5 are omitted from the operational amplifier 1U, the source of the first branch transistor MB4 is connected between the source of the eleventh transistor MF11 and the first resistor R1, and the second branch is used. The source of the transistor MB5 may be connected between the source of the tenth transistor MF10 and the second resistor R2.

The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are omitted from the operational amplifier 1U, and the source and the first branch transistor MB4 of the first branch circuit 123 are omitted. The source of the second branch transistor MB5 of the two-branch circuit 124 may be connected to the second power supply wiring 3. In this case, the regulated current source 125 may be added to the operational amplifier 1U as in the operational amplifier 1H of the eleventh embodiment. The connection configuration of the transistor MB6 of the adjustment current source 125 and each of the transistors MB2, MB4, MB5 is the same as that of the eleventh embodiment.

-For each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21, instead of lowering the impurity concentration in the channel region, like each transistor M1 to M4 of the second embodiment. Embedded channel MOSFETs may be applied. As a result, the same effect as that of the second embodiment can be obtained. Further, each transistor MF4, MF5 constituting the first differential pair 171, each transistor MF7, MF8 constituting the second differential pair 172, and each transistor MF10, MF11 constituting the current source of the cascode current mirror circuit 176. First implementation of the transistors MF14, MF15 constituting the current source of the bias circuit 177, the transistors MF18, MF19 constituting the first switching unit 175A, and the transistors MF20, MF21 constituting the second switching unit 175B. The low-concentration transistor of the embodiment and the embedded channel MOSFET of the second embodiment may be mixed.

-For each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, each transistor MF4, MF5, MF7, MF8, MF10, MF11, MF14, MF15, MF18 to MF21 may have the same structure as the structure of each transistor M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor MF4 and MF5 constituting the first differential pair 171, a set of each transistor MF7 and MF8 constituting the second differential pair 172, and each constituting a current source of the cascode current mirror circuit 176. A set of transistors MF10 and MF11, a set of transistors MF14 and MF15 constituting the current source of the bias circuit 177, a set of transistors MF18 and MF19 constituting the first switching unit 175A, and a second switching unit 175B. The set of the transistors MF20 and MF21 may be changed so that the same structures as those of the low-concentration transistor of the first embodiment and the transistors M1 to M4 of the third embodiment are mixed. Further, a set of each transistor MF4 and MF5 constituting the first differential pair 171, a set of each transistor MF7 and MF8 constituting the second differential pair 172, and each constituting a current source of the cascode current mirror circuit 176. A set of transistors MF10 and MF11, a set of transistors MF14 and MF15 constituting the current source of the bias circuit 177, a set of transistors MF18 and MF19 constituting the first switching unit 175A, and a second switching unit 175B. The set of each transistor MF20 and MF21 is mixed with the low concentration transistor of the first embodiment, the embedded channel type MOSFET of the second embodiment, and the structure similar to the structure of each of the transistors M1 to M4 of the third embodiment. May be changed to. In short, the operational amplifier 1U has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(24th Embodiment)
The integrating circuit 180, which is an example of the differential circuit of the 24th embodiment, will be described with reference to FIG. 41. The integrating circuit 180 of the present embodiment integrates the differential input currents input to the non-inverting input terminal INP and the inverting input terminal INN, samples and holds them in a predetermined cycle, and generates a differential voltage signal.

The integrator circuit 180 includes a differential pair 181, a constant current source 182, a constant current source 183, 184, a first selector 185, a second selector 186, an integrator 187, a sample hold circuit (not shown), a common feedback circuit 188, and a current. It has a mirror circuit 189 and a backgate bias circuit 20.

The differential pair 181 includes a first transistor MG1 and a second transistor MG2. In the present embodiment, the first transistor MG1 and the second transistor MG2 are composed of P-channel MOSFETs. The first transistor MG1 and the second transistor MG2 may have either a depletion type structure or an enhancement type structure. In the present embodiment, the first transistor MG1 and the second transistor MG2 have an enhancement type structure. The source of the first transistor MG1 and the source of the second transistor MG2 are commonly connected.

The constant current source 182 includes a transistor (not shown) connected to the differential pair 181. The transistor of this embodiment is a P-channel MOSFET. The drain of the transistor is connected to the source of each transistor MG1 and MG2, and the source of the transistor is connected to the first power supply wiring 2. A bias voltage from a first bias circuit (not shown) is input to the gate of the transistor. The constant current source 182 supplies a constant current It based on the bias voltage.

The constant current source 183 includes the third transistor MG3, and the constant current source 184 includes the fourth transistor MG4. The third transistor MG3 and the fourth transistor MG4 of the present embodiment are enhancement type P-channel MOSFETs. The source of the third transistor MG3 and the source of the fourth transistor MG4 are connected to the first power supply wiring 2, and the gate of the third transistor MG3 and the gate of the fourth transistor MG4 are commonly connected. A bias voltage from, for example, a first bias circuit may be input to the gates of the third transistor MG3 and the fourth transistor MG4.

The first selector 185 is provided in front of the differential pair 181. The first selector 185 is a first state in which the gate of the first transistor MG1 of the differential pair 181 and the non-inverting input terminal INP are connected, and the gate of the second transistor MG2 and the inverting input terminal INN are connected. The gate of the first transistor MG1 and the inverting input terminal INN are connected, and the gate of the second transistor MG2 and the non-inverting input terminal INP are connected to the second state. FIG. 41 shows the first state. The first selector 185 includes a first switch SW1 to a fourth switch SW4, a first capacitor CG1, and a second capacitor CG2. The first capacitor CG1 and the second capacitor CG2 are capacitors for DC blocks. The first capacitor CG1 is provided between the first switch SW1 and the first transistor MG1, and the second capacitor CG2 is provided between the second switch SW2 and the second transistor MG2. Each switch SW1 to SW4 may be a CMOS switch (CMOS transfer gate). The first terminal of the first switch SW1 and the first terminal of the third switch SW3 are connected to the non-inverting input terminal INP, and the first terminal of the second switch SW2 and the first terminal of the fourth switch SW4 are connected to the inverting input terminal INN. It is connected. The second terminal of the first switch SW1 is connected to the node NJ1 between the first switch SW1 and the first capacitor CG1. The second terminal of the second switch SW2 is connected to the node NJ2 between the second switch SW2 and the second capacitor CG2. The second terminal of the third switch SW3 is connected to the node NJ2, and the second terminal of the fourth switch SW4 is connected to the node NJ1. The first selector 185 is in the first state when the first switch SW1 and the second switch SW2 are on and the third switch SW3 and the fourth switch SW4 are off, and the first switch SW1 and the second switch SW2 are off. The second state is set when the third switch SW3 and the fourth switch SW4 are on.

The second selector 186 is provided after the differential pair 181. The second selector 186 is the first state in which the drain of the first transistor MG1 is connected to the first circuit 187A of the integrator 187 and the drain of the second transistor MG2 is connected to the second circuit 187B of the integrator 187. , The second state in which the drain of the first transistor MG1 is connected to the second circuit 187B and the drain of the second transistor MG2 is connected to the first circuit 187A is switched. The second selector 186 includes the fifth to eighth switches SW5 to SW8. Each switch SW5 to SW8 may be a CMOS switch (CMOS transfer gate). The first terminal of the fifth switch SW5 and the first terminal of the seventh switch SW7 are connected to the drain of the first transistor MG1, and the first terminal of the sixth switch SW6 and the first terminal of the eighth switch SW8 are the second transistor MG2. It is connected to the drain of. The second terminal of the fifth switch SW5 is connected to the node NJ3 between the first transistor MG1 and the first circuit 187A. The second terminal of the sixth switch SW6 is connected to the node NJ4 between the second transistor MG2 and the second circuit 187B. The second terminal of the seventh switch SW7 is connected to the node NJ4, and the second terminal of the eighth switch SW8 is connected to the node NJ3. The second selector 186 is in the first state when the fifth switch SW5 and the sixth switch SW6 are on and the seventh switch SW7 and the eighth switch SW8 are off, and the fifth switch SW5 and the sixth switch SW6 are off. The second state is set when the 7th switch SW7 and the 8th switch SW8 are on.

The integrator 187 has a first circuit 187A and a second circuit 187B. The integrator 187 integrates the first differential input current flowing from the differential pair 181 to the first circuit 187A to generate the first differential voltage signal. The integrator 187 integrates the second differential input current flowing from the differential pair 181 to the second circuit 187B to generate a second differential voltage signal.

The first circuit 187A includes a fifth transistor MG5, a resistor RG1 and a capacitor CG3. The fifth transistor MG5 of this embodiment is an enhancement type N-channel MOSFET. The drain of the fifth transistor MG5 is connected to the drain of the fourth transistor MG4, the source of the fifth transistor MG5 is connected to the second power supply wiring 3, and the gate of the fifth transistor MG5 is connected to the node NJ3. The resistor RG1 and the capacitor CG3 are connected in series to form an RC circuit. The first terminal of the resistor RG1 is connected to the node NJ5 between the node NJ3 and the gate of the fifth transistor MG5. The second terminal of the resistor RG1 is connected to the first terminal of the capacitor CG3. The second terminal of the capacitor CG3 is connected to the drain of the fifth transistor MG5.

The second circuit 187B includes a sixth transistor MG6, a resistor RG2, and a capacitor CG4. The sixth transistor MG6 of this embodiment is an enhancement type N-channel MOSFET. The drain of the sixth transistor MG6 is connected to the drain of the third transistor MG3, the source of the sixth transistor MG6 is connected to the second power supply wiring 3, and the gate of the sixth transistor MG6 is connected to the node NJ4. The resistor RG2 and the capacitor CG4 are connected in series to form an RC circuit. The first terminal of the resistor RG2 is connected to the node NJ6 between the node NJ4 and the gate of the sixth transistor MG6. The second terminal of the resistor RG2 is connected to the first terminal of the capacitor CG4. The second terminal of the capacitor CG4 is connected to the drain of the sixth transistor MG6.

The common feedback circuit 188 adjusts the bias state of the differential pair 181 so that the midpoint voltage of the first differential output voltage and the second differential output voltage of the integrator 187 approaches the target voltage. The common feedback circuit 188 has a differential pair 188A, a constant current source 188B, six resistors RG3 to RG8, and two capacitors CG5 and CG6.

The differential pair 188A has a seventh transistor MG7 and an eighth transistor MG8. The seventh transistor MG7 and the eighth transistor MG8 of the present embodiment are P-channel MOSFETs. The source of the 7th transistor MG7 and the source of the 8th transistor MG8 are commonly connected. The common feedback circuit 188 further includes a ninth transistor MG9 and a tenth transistor MG10. The 9th transistor MG9 and the 10th transistor MG10 are enhancement type N-channel MOSFETs. The drain of the 9th transistor MG9 is connected to the drain of the 7th transistor MG7, and the drain of the 10th transistor MG10 is connected to the drain of the 8th transistor MG8. The source of the 9th transistor MG9 and the source of the 10th transistor MG10 are connected to the second power supply wiring 3. The gate of the 9th transistor MG9 is connected to the drain of the 9th transistor MG9. The gate of the tenth transistor MG10 is connected to the drain of the tenth transistor MG10.

The constant current source 188B includes a transistor connected to a differential pair 188A. The transistor of this embodiment is a P-channel MOSFET. The drain of the transistor is connected to the source of each of the transistors MG7 and MG8, and the source of the transistor is connected to the first power supply wiring 2. A bias voltage from a first bias circuit (not shown) is input to the gate of the transistor. The constant current source 188B supplies a constant current based on the bias voltage.

The resistor RG3 and the resistor RG4 are connected in series. The first terminal of the resistor RG3 is connected to the node NJ7 between the capacitor CG1 and the gate of the first transistor MG1. The second terminal of the resistor RG3 is connected to the first terminal of the resistor RG4. The second terminal of the resistor RG4 is connected to the node NJ8 between the capacitor CG2 and the gate of the second transistor MG2. The resistance RG5 and the resistance RG6 are connected in series between the first power supply wiring 2 and the second power supply wiring 3. The first terminal of the resistor RG5 is connected to the first power supply wiring 2, and the second terminal of the resistor RG5 is connected to the first terminal of the resistor RG6. The second terminal of the resistor RG6 is connected to the second power supply wiring 3. The gate of the seventh transistor MG7 is a node NJ9 between the second terminal of the resistor RG3 and the first terminal of the resistor RG4, and a node NJ10 between the second terminal of the resistor RG5 and the first terminal of the resistor RG6. It is connected.

The resistor RG7 and the resistor RG8 are connected in series. The first terminal of the resistor RG7 is connected to the non-inverting input terminal SHIP of the sample hold circuit, and the second terminal of the resistor RG7 is connected to the first terminal of the resistor RG8. The second terminal of the resistor RG8 is connected to the inverting input terminal SHIN of the sample hold circuit. The capacitor CG5 is connected in parallel with the resistor RG7, and the capacitor CG6 is connected in parallel with the resistor RG8. The non-inverting input terminal SHIP is connected to the node NJ11 between the drain of the third transistor MG3 and the drain of the sixth transistor MG6. The inverting input terminal SHIN is connected to the node NJ12 between the drain of the fourth transistor MG4 and the drain of the fifth transistor MG5. The gate of the eighth transistor MG8 is connected to the node NJ13 between the second terminal of the resistor RG7 and the first terminal of the resistor RG8.

The current mirror circuit 189 includes the 11th transistor MG11 and the 12th transistor MG12. The eleventh transistor MG11 and the twelfth transistor MG12 of the present embodiment are enhancement type N-channel MOSFETs. The source of the 11th transistor MG11 and the source of the 12th transistor MG12 are connected to the second power supply wiring 3, and the gate of the 11th transistor MG11 and the gate of the 12th transistor MG12 are commonly connected to the gate of the 10th transistor MG10. ing. The drain of the eleventh transistor MG11 is connected to the node NJ14 between the drain of the first transistor MG1 and the fifth switch SW5. The drain of the 12th transistor MG12 is connected to the node NJ15 between the drain of the 2nd transistor MG2 and the 6th switch SW6.

The backgate bias circuit 20 is connected to a common backgate of the differential pair 181 and the first power supply wiring 2. The configuration of the backgate bias circuit 20 is the same as the configuration of the backgate bias circuit 20 of the first embodiment (see FIG. 2). The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor MG1 and the second transistor MG2 so as to be closer to the first power supply voltage VDD than the source potential of the first transistor MG1 and the second transistor MG2. do. In other words, the backgate bias circuit 20 has a bias voltage such that the voltage is on the first power supply voltage VDD side of the intermediate voltage between the source potential of the first transistor MG1 and the second transistor MG2 and the first power supply voltage VDD. VB is applied to the back gates of the first transistor MG1 and the second transistor MG2. That is, the backgate bias circuit 20 applies a bias voltage VB to the first transistor MG1 and the second transistor MG2 so that the backgate source voltage VBS becomes large. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Further, the bias voltage VB may be higher than the first power supply voltage VDD. In this case, the bias voltage VB is preferably higher than the first power supply voltage VDD within a range in which the parasitic diodes of the first transistor MG1 and the second transistor MG2 are not turned on. That is, the bias voltage VB is preferably less than the voltage at which the parasitic diodes of the first transistor MG1 and the second transistor MG2 are turned on. An example of the voltage at which the parasitic diode of the first transistor MG1 and the second transistor MG2 is turned on is a voltage 0.5 to 0.6 V higher than the first power supply voltage VDD (VDD + 0.5 to 0.6). The bias voltage VB is preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within a predetermined range including the first power supply voltage VDD. More specifically, the bias voltage VB is more preferably a voltage excluding the same voltage as the first power supply voltage VDD among the voltages within ± 20% of the first power supply voltage VDD. As a result, the backgate-source voltage VBS becomes a voltage excluding the backgate-source voltage VBSH among the voltages within ± 20% of the backgate-source voltage VBSH.

Further, in the present embodiment, in order to further reduce the 1 / f noise of the output signal Sout of the integrating circuit 180, the impurity concentration in the channel region in some of the transistors of the integrating circuit 180 is set in the other transistors. It is lower than the impurity concentration in the channel region. That is, the plurality of transistors of the integrator circuit 180 include a high-concentration transistor having an impurity concentration in the channel region as the first concentration and a low-concentration transistor having an impurity concentration in the channel region having a second concentration lower than the first concentration. .. Specifically, the impurity concentration in the channel region of the transistor susceptible to 1 / f noise of the output signal Sout of each transistor of the integrator circuit 180 is set to 1 of the output signal Sout of each transistor of the integrator circuit 180. It is lower than the impurity concentration in the channel region of the transistor that is not easily affected by / f noise. That is, a low-concentration transistor is used for a transistor that is more susceptible to 1 / f noise of the output signal Sout among a plurality of transistors than a high-concentration transistor, and a high-concentration transistor is more than a plurality of low-concentration transistors. It is used for a transistor that is not easily affected by 1 / f noise of the output signal Sout among the transistors. Specifically, the parts susceptible to 1 / f noise of the output signal Sout are the differential pair 181, the constant current source 183, 184, the integrator 187, a part of the common feedback circuit 188, and the current mirror circuit 189. The parts that are not easily affected by the 1 / f noise characteristics of the output signal Sout are the differential pair 188A of the common feedback circuit 188 and the backgate bias circuit 20.

In this embodiment, the difference between the differential pair 181 and the constant current source 183 and 184, the integrator 187, a part of the common feedback circuit 188, and the impurity concentration in the channel region of the transistor of the current mirror circuit 189 is the difference between the common feedback circuit 188. It is lower than the impurity concentration in the channel region in the transistor of the dynamic pair 188A and the backgate bias circuit 20. That is, the transistors constituting the differential pair 181, the constant current source 183, 184, the integrator 187, a part of the common feedback circuit 188, and the current mirror circuit 189 are low-concentration transistors, and the differential pair of the common feedback circuit 188. The transistors constituting the 188A and the backgate bias circuit 20 are high-concentration transistors. Specifically, the impurity concentration in the channel region of the first transistor MG1 to the sixth transistor MG6 and the ninth transistor MG9 to the twelfth transistor MG12 is measured by the seventh transistor MG7, the eighth transistor MG8, and the backgate bias circuit 20. It is lower than the impurity concentration in the channel region of the transistor. That is, the first transistor MG1 to the sixth transistor MG6 and the ninth transistor MG9 to the twelfth transistor MG12 are low-concentration transistors, and the seventh transistor MG7, the eighth transistor MG8, and the backgate bias circuit 20 have high concentrations. It is a transistor.

The impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is preferably about 1/2 or less of the impurity concentration in the channel region of the transistors of each of the transistors MG7, MG8 and the backgate bias circuit 20. In the present embodiment, the impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is about 1/10 of the impurity concentration in the channel region of each of the transistors MG7, MG8 and the backgate bias circuit 20. Each transistor of the back gate bias circuit 20 is a surface channel type MOSFET.

The structures and manufacturing methods of the N-channel MOSFETs and P-channel MOSFETs of the transistors MG1 to MG12 are the same structures and manufacturing methods as those of the N-channel MOSFETs and P-channel MOSFETs such as the first transistor M1 of the first embodiment.

According to this embodiment, the following effects can be obtained.
(24-1) In the backgate bias circuit 20, the backgate bias circuit 20 has a bias voltage VB in the backgate of the first transistor MG1 and the second transistor MG2 (in the N-type well layer 39 of the first transistor MG1 and the second transistor MG2). A bias voltage VB closer to the first power supply voltage VDD than the source potential of the first transistor MG1 and the second transistor MG2 is applied to the contact region for applying the first transistor MG1 and the second transistor MG2. As a result, the backgate-source voltage VBS of the first transistor MG1 and the second transistor MG2 becomes large. As a result, the transconductance gm12 of the first transistor MG1 and the second transistor MG2 becomes large, so that the noise of the output signal Sout of the integrator circuit 180 can be reduced.

(24-2) The backgate bias circuit 20 is an integrator circuit because the transconductance gm12 of the first transistor MG1 and the second transistor MG2 becomes larger by making the bias voltage VB larger than the first power supply voltage VDD. The noise of the output signal Sout of 180 can be further reduced.

(24-3) By setting the bias voltage VB to a voltage lower than the voltage at which the parasitic diodes of the first transistor MG1 and the second transistor MG2 are turned on, the first transistor MG1 and the second transistor MG2 can operate stably.

(24-4) By setting the bias voltage VB to a voltage other than the same voltage as the first power supply voltage VDD within a predetermined range including the first power supply voltage VDD, the backgate-source voltage VBS becomes large. Therefore, the transconductance gm12 of the first transistor MG1 and the second transistor MG2 becomes large, and the first transistor MG1 and the second transistor MG2 can operate stably. In particular, by setting the bias voltage VB to a voltage other than the voltage within ± 20% of the first power supply voltage VDD, which is the same as the first power supply voltage VDD, the backgate source voltage VBS becomes the backgate source. Since the inter-voltage voltage is near VBSH, the transconductance gm12 of the first transistor MG1 and the second transistor MG2 becomes large, and the first transistor MG1 and the second transistor MG2 can operate more stably.

(24-5) The impurity concentration in the channel region in the first transistor MG1 and the second transistor MG2 constituting the differential pair 181 is the seventh transistor MG7 and the eighth transistor MG8 constituting the differential pair 188A of the common feedback circuit 188. Further, it is lower than the impurity concentration in the channel region in the transistor constituting the back gate bias circuit 20. According to this configuration, the mobility is increased by lowering the impurity concentration in the channel region of each transistor MG1 and MG2 constituting the differential pair 181 which is easily affected by 1 / f noise of the output signal Sout of the integrating circuit 180. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the integrating circuit 180 can be effectively reduced.

(24-6) The impurity concentration in the channel region in the third transistor MG3 and the fourth transistor MG4 constituting the constant current sources 183 and 184 is the seventh transistor MG7 and the eighth transistor constituting the differential pair 188A of the common feedback circuit 188. It is lower than the impurity concentration in the channel region of the transistor constituting the transistor MG8 and the backgate bias circuit 20. According to this configuration, the transfer is performed by lowering the impurity concentration in the channel region of each of the transistors MG3 and MG4 constituting the constant current sources 183 and 184 which are easily affected by the 1 / f noise of the output signal Sout of the integrating circuit 180. Fluctuations in degree can be suppressed, and fluctuations in drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the integrating circuit 180 can be effectively reduced.

(24-7) The impurity concentration in the channel region in the 11th transistor MG11 and the 12th transistor MG12 constituting the current mirror circuit 189 is the 7th transistor MG7 and the 8th transistor MG8 constituting the differential pair 188A of the common feedback circuit 188. Further, it is lower than the impurity concentration in the channel region in the transistor constituting the back gate bias circuit 20. According to this configuration, the mobility is reduced by lowering the impurity concentration in the channel region of each of the transistors MG11 and MG12 constituting the current mirror circuit 189 which is easily affected by the 1 / f noise of the output signal Sout of the integrating circuit 180. Fluctuations can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the integrating circuit 180 can be effectively reduced.

(24-8) The impurity concentration in the channel region in the 5th transistor MG5 and the 6th transistor MG6 constituting the integrator 187 is the same as that of the 7th transistor MG7 and the 8th transistor MG8 constituting the differential pair 188A of the common feedback circuit 188. It is lower than the impurity concentration in the channel region of the transistor constituting the back gate bias circuit 20. According to this configuration, the mobility fluctuates by lowering the impurity concentration in the channel region of each of the transistors MG5 and MG6 constituting the integrator 187 which is easily affected by the 1 / f noise of the output signal Sout of the integrator circuit 180. Can be suppressed, and fluctuations in the drain current can be suppressed. Therefore, 1 / f noise of the output signal Sout of the integrating circuit 180 can be effectively reduced.

(24-9) Impurity concentration in the channel region of each transistor MG3 and MG4 constituting the constant current sources 183 and 184, and impurity concentration in the channel region of the first transistor MG1 and the second transistor MG2 constituting the differential pair 181. Are equal to each other. According to this configuration, the step of forming the N-type well layer 70 of each transistor MG3 and MG4 and the step of forming the N-type well layer 70 of each transistor MG1 and MG2 can be performed collectively, so that the integrator circuit can be performed. The process of manufacturing the 180 can be simplified.

(24-10) The impurity concentration in the channel region of each of the transistors MG11 and MG12 constituting the current mirror circuit 189, the impurity concentration in the channel region of each of the transistors MG5 and MG6 constituting the integrator 187, and the current of the common feedback circuit 188. The impurity concentrations in the channel regions of the transistors MG9 and MG10 constituting the source are equal to each other. According to this configuration, a step of forming a P-type well layer 62 of each transistor MG11 and MG12, a step of forming a P-type well layer 62 of each transistor MG5 and MG6, and a step of forming a P-type well layer 62 of each transistor MG9 and MG10. Since the process of forming the 62 can be performed collectively, the process of manufacturing the integrating circuit 180 can be simplified.

(24-11) The impurity concentration in the channel region of the transistor of the constant current source 182, the impurity concentration in the channel region of each of the transistors MG7 and MG8 of the differential pair 188A, and the impurity concentration in the channel region of the transistor of the constant current source 188B. , The impurity concentrations in the channel region of the transistors M5, M8, and M9 of the backgate bias circuit 20 are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the transistor of the constant current source 182, a step of forming the N-type well layer 63 of each of the transistors MG7 and MG8, and an N-type of the transistor of the constant current source 188B. The step of forming the well layer 63 and the step of forming the N-type well layer 63 of each of the transistors M5, M8, and M9 of the backgate bias circuit 20 can be performed collectively. Therefore, the process of manufacturing the integrator circuit 180A can be simplified.

(Modified example of the 24th embodiment)
The integrating circuit 180 of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

In the integrator circuit 180, the step-down circuit 100 of the fifth embodiment is added between the first power supply wiring 2 and the differential pair 181 and more specifically between the first power supply wiring 2 and the constant current source 182. You can also do it. According to this configuration, the same effect as that of the fifth embodiment can be obtained. Further, the back gate bias circuit 20 can also be connected to the third power supply wiring 4 like the back gate bias circuit 20 of the sixth embodiment. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

-For each of the transistors MG1 to MG6 and MG9 to MG12, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current sources 183 and 184. Any one or a set of two of them may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor MG1 to MG6 and MG9 to MG12, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors MG1 to MG6 and MG9 to MG12 may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current sources 183 and 184. One or two sets of any one of them may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current source 183 and 184. Any one or a set of two of them may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the integrator circuit 180 has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. You may.

(25th Embodiment)
The integrating circuit 180A, which is an example of the differential circuit of the 25th embodiment, will be described with reference to FIG. 42. In the integrating circuit 180A of the present embodiment, the back gate bias circuit 20 is omitted as compared with the integrating circuit 180 of the 24th embodiment, and the first control unit 110A, the second control unit 110B, the first resistance R1, and the first resistor R1 are omitted. The main difference is that the two resistors R2 are added.

The first resistance R1 is provided between the second power supply wiring 3 and the eleventh transistor MG11. The first terminal of the first resistance R1 is connected to the source of the eleventh transistor MG11, and the second terminal of the first resistance R1 is connected to the second power supply wiring 3.

The second resistance R2 is provided between the second power supply wiring 3 and the twelfth transistor MG12. The first terminal of the second resistance R2 is connected to the source of the twelfth transistor MG12, and the second terminal of the second resistance R2 is connected to the second power supply wiring 3.

With the addition of the first resistor R1 and the second resistor R2, a resistor R9 is provided between the source of the ninth transistor MG9 of the differential pair 188A of the common feedback circuit 188 and the second power supply wiring 3. A resistor R10 is provided between the source of the tenth transistor MG10 and the second power supply wiring 3. The first terminal of the resistor R9 is connected to the source of the ninth transistor MG9, and the second terminal of the resistor R9 is connected to the second power supply wiring 3. The first terminal of the resistor R10 is connected to the source of the tenth transistor MG10, and the second terminal of the resistor R10 is connected to the second power supply wiring 3.

The first control unit 110A controls the source potential of the eleventh transistor MG11 by controlling the current supplied to the node NJ16 between the source of the eleventh transistor MG11 and the first resistor R1. The first control transistor MA1 of the first control unit 110A of the present embodiment is an N-channel MOSFET. The first constant current source 111 includes a transistor (not shown). The transistor of the first constant current source 111 is a P-channel MOSFET. The drain of the transistor of the first constant current source 111 is connected to the drain of the first control transistor MA1, and the source of the transistor is connected to the first power supply wiring 2. The source of the first control transistor MA1 is connected to the node NJ16 between the source of the eleventh transistor MG11 and the first resistance R1, and the gate of the first control transistor MA1 is connected to the gate and drain of the eleventh transistor MG11. It is connected. With this configuration, the first control unit 110A supplies the node NJ16 with a first current Ic1 proportional to the constant current It of the constant current source 182.

The second control unit 110B controls the source potential of the twelfth transistor MG12 by controlling the current supplied to the node NJ17 between the source of the twelfth transistor MG12 and the second resistor R2. The second control transistor MA2 of the second control unit 110B of the present embodiment is an N-channel MOSFET. The second constant current source 112 includes a transistor (not shown). The transistor of the second constant current source 112 is a P-channel MOSFET. The drain of the transistor of the second constant current source 112 is connected to the drain of the second control transistor MA2, and the source of the transistor is connected to the first power supply wiring 2. The source of the second control transistor MA2 is connected to the node NJ17 between the source of the twelfth transistor MG12 and the second resistance R2, and the gate of the second control transistor MA2 is connected to the gate of the eleventh transistor MG11. ing. With this configuration, the second control unit 110B supplies the node NJ17 with a second current Ic2 proportional to the constant current It of the constant current source 182.

As described above, the source of the fourth transistor ME4 is supplied with the first current Ic1 from the first control unit 110A, and the source of the fifth transistor ME5 is supplied with the second current Ic2 from the second control unit 110B. , The source potential of the 4th transistor ME4 and the source potential of the 5th transistor ME5 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the fourth transistor ME4 and the fifth transistor ME5. As described above, in the present embodiment, the source potentials of the transistors ME4 and ME5 are further increased. Therefore, the transconductance gm on the circuit is reduced.

Further, the structure and manufacturing method of the N-channel MOSFET and the P-channel MOSFET of each transistor of the integrating circuit 180A are the structure and manufacturing method of the N-channel MOSFET and the P-channel MOSFET of the transistors MG1 to MG12 of the integrating circuit 180 of the 24th embodiment. Is the same as. Therefore, an effect similar to the effect of (24-5) to (24-10) of the 24th embodiment can be obtained.

Further, since the first control transistor MA1 and the second control transistor MA2 are not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MA1 and MA2 is set to each transistor MG1. It is higher than the impurity concentration in the channel region in ~ MG6, MG9 ~ MG12. In other words, the impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is lower than the impurity concentration of the channel region in each of the transistors MA1 and MA2. That is, the transistors MG1 to MG6 and MG9 to MG12 are low-concentration transistors, and the transistors MA1 and MA2 are high-concentration transistors. The impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is preferably about 1/2 or less of the impurity concentration in the channel region of each of the transistors MA1 and MA2. In the present embodiment, the impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is about 1/10 of the impurity concentration of the channel region of each of the transistors MA1 and MA2. Further, each transistor MA1 and MA2 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(25-1) By controlling the source potentials of the active load transistors MG11 and MG12 to increase by the control units 110A and 110B, the currents flowing through the transistors MG11 and MG12 are reduced. Therefore, since the transconductance gm of each of the transistors MG11 and MG12 on the circuit is reduced, the noise of the output signal Sout of the integrating circuit 180A can be reduced.

(25-2) The impurity concentration in the channel region of the transistor of the constant current source 182, the impurity concentration in the channel region of each of the transistors MG7 and MG8 of the differential pair 188A, and the impurity concentration in the channel region of the transistor of the constant current source 188B. , The impurity concentrations in the channel region of the transistor of the constant current source 111 of the first control unit 110A and the transistor of the constant current source 112 of the second control unit 110B are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the transistor of the constant current source 182, a step of forming the N-type well layer 63 of each of the transistors MG7 and MG8, and an N-type of the transistor of the constant current source 188B. The step of forming the well layer 63 and the step of forming the N-type well layer 63 of the transistors of the constant current sources 111 and 112 can be performed collectively. Therefore, the process of manufacturing the integrator circuit 180A can be simplified.

(Modified example of the 25th embodiment)
The integrating circuit 180A of the present embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The resistance value of the first resistance R1, the resistance value of the second resistance R2, the resistance value of the resistance R9, and the resistance value of the resistance R10 are the 11th transistor MG11, the 12th transistor MG12, the 9th transistor MG9, and the 10th transistor. It may be changed according to the ratio of MG10.

The first control unit 110A and the second control unit 110B may be omitted from the integrator circuit 180A. In this case, the source potentials of the transistors MG11 and MG12 are increased by the first resistance R1 and the second resistance R2.

-For each of the transistors MG1 to MG6 and MG9 to MG12, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current sources 183 and 184. Any one or a set of two of them may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor MG1 to MG6 and MG9 to MG12, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors MG1 to MG6 and MG9 to MG12 may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current sources 183 and 184. Any one or two sets may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current source 183 and 184. Any one or a set of two of them may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the integrator circuit 180A has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. You may.

(26th Embodiment)
The integrating circuit 180B, which is an example of the differential circuit of the 26th embodiment, will be described with reference to FIG. 43. The integrator circuit 180B of the present embodiment is different from the integrator circuit 180A of the 25th embodiment in that the control units 110A and 110B are omitted and the current adjustment unit 120F is added.

The current adjusting unit 120F makes the current flowing through the first transistor MG1 and the second transistor MG2 of the differential pair 181 larger than the current flowing through the 11th transistor MG11 and the 12th transistor MG12 which are active loads. More specifically, the current adjusting unit 120F increases the current flowing through the first transistor MG1 and the second transistor MG2 more than the constant current It of the constant current source 182, and the current corresponding to the increase of the current flowing through each of the transistors MG1 and MG2. Is prevented from flowing through the 11th transistor MG11 and the 12th transistor MG12. The current adjusting unit 120F has the same configuration as the current adjusting unit 120A of the twelfth embodiment, and has a current supply unit 121, a branching unit 122, and a third resistance R3.

The current supply unit 121 is a current source provided separately from the constant current source 182, and supplies current to the first transistor MG1 and the second transistor MG2. The current supply unit 121 includes a first supply transistor MB1, a second supply transistor MB2, and a third supply transistor MB3. The first supply transistor MB1 and the third supply transistor MB3 of the present embodiment are P-channel MOSFETs, and the second supply transistor MB2 is an N-channel MOSFET.

The first supply transistor MB1 and the second supply transistor MB2 form a series circuit between the first power supply wiring 2 and the second power supply wiring 3. The source of the first supply transistor MB1 is connected to the first power supply wiring 2, the gate of the first supply transistor MB1 is connected to the drain of the first supply transistor MB1, and the first supply transistor MB1 is connected. Is connected to the drain of the second supply transistor MB2. The source of the second supply transistor MB2 is connected to the second power supply wiring 3.

The third supply transistor MB3 is provided between the first power supply wiring 2 and the differential pair 181. The source of the third supply transistor MB3 is connected to the first power supply wiring 2, the drain of the third supply transistor MB3 is connected to the sources of the first transistor MG1 and the second transistor MG2, and the third supply transistor MB3 is connected to the source. The gate of the transistor MB3 is commonly connected to the gate of the first supply transistor MB1. As a result, the first supply transistor MB1 and the third supply transistor MB3 form a current mirror circuit.

The branch portion 122 does not allow the increased current of the drain current flowing through the first transistor MG1 and the increased current of the drain current flowing through the second transistor MG2 to flow to the drains of the 11th transistor MG11 and the 12th transistor MG12, respectively. The branch portion 122 includes a first branch circuit 123 and a second branch circuit 124.

The first branch circuit 123 includes a first branch transistor MB4. The first branch transistor MB4 of this embodiment is an N-channel MOSFET. The drain of the first branching transistor MB4 is connected to the drain of the first transistor MG1, and the source of the first branching transistor MB4 is connected to the node NJ18 between the twelfth transistor MG12 and the first resistance R1. The gate of the branching transistor MB4 of 1 is commonly connected to the gate of the 11th transistor MG11 and the gate of the 10th transistor MG10.

The second branch circuit 124 includes a second branch transistor MB5. The second branch transistor MB5 of this embodiment is an N-channel MOSFET. The drain of the second branch transistor MB5 is connected to the drain of the second transistor MG2, and the source of the second branch transistor MB5 is connected to the node NJ19 between the 11th transistor MG11 and the second resistance R2. The gate of the branching transistor MB5 of 2 is commonly connected to the gate of the 12th transistor MG12 and the gate of the 10th transistor MG10.

Further, the gate of the second supply transistor MB2 is connected to the gate of the second branch transistor MB5. As described above, the branching transistors MB4 and MB5, the second supply transistor MB2, and the tenth transistor MG10 form a current mirror circuit. Further, the gate voltage of each transistor MB2, MB4, MB5 is controlled by the gate voltage of the tenth transistor MG10.

The electrical characteristics of the first branch transistor MB4 of the first branch circuit 123 and the second branch transistor MB5 of the second branch circuit 124 are equal to each other. In addition, since the gate voltages of the transistors MB2, MB4, and MB5 are common, the current amount of the second supply transistor MB2 is 2 of the current amount of the first branch transistor MB4 (second branch transistor MB5). Since it is doubled, the total current flowing through each of the transistors MB4 and MB5 is generated in the second supply transistor MB2.

In the present embodiment, the electrical characteristics of each of the transistors MB4 and MB5 and the eleventh transistor MG11 and the twelfth transistor MG12 are set to be equal to each other. In addition, since the gates of the transistors MB4 and MB5 are connected to the gate of the eleventh transistor MG11, the current flowing through the first branching transistor MB4 and the current flowing through the second branching transistor MB5 are the first. It is equal to the current flowing through the 11th transistor MG11 (the current flowing through the 12th transistor MG12).

Next, the current flowing through the integrating circuit 180B, particularly the current flowing through the current adjusting unit 120F will be described. In this description, the constant current flowing through the constant current source 182 is 2 ID.
In the integrator circuit 180B, the differential pair 181 is supplied with the constant current 2 ID and the supply current IDB 3 from the third supply transistor MB3. The supply current IDB3 is a current proportional to the current IDB2 flowing through the second supply transistor MB2 by the current mirror circuit including the transistors MB1 and MB3. In the present embodiment, the supply current IDB3 is equal to the current IDB2 because the current ratio between the first supply transistor MB1 and the third supply transistor MB3 is 1: 1. More specifically, the current IDB2 is a current proportional to the current ID11 of the eleventh transistor MG11 by the current mirror circuit including the transistors MG11, MB4, MB5, and MB2. In the present embodiment, the current ratio between the transistors MB4 and MB5 and the transistor MG11 is 1: 1. Therefore, the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5 are equal to the current ID11. In addition, since the second supply transistor MB2 and the respective transistors MB4 and MB5 form a current mirror circuit, the current IDB2 flowing in the second supply transistor MB2 is the current flowing in the respective transistors MB4 and MB5. It becomes the total (IDB4 + IDB5). That is, the supply current IDB3 supplied to the differential pair 181 is the total of the currents flowing through the transistors MB4 and MB5 (IDB4 + IDB5). Further, since the currents flowing through the transistors MG11, MG12, MB4 and MB5 are equal to each other, the total current (ID3 + ID4) of the currents flowing through the transistors MG11 and MG12, that is, the constant current 2ID and the current flowing through the transistors MB4 and MB5 are used. The total current (IDB4 + IDB5) is equal to each other. Therefore, in the present embodiment, the supply current IDB3 and the constant current 2ID are equal to each other.

Further, the current IDx flowing through each of the transistors MG1 and MG2 of the differential pair 181 is IDx = (when the inputs of the constant current 2ID and the supply current IDB3 are in phase, that is, when the gate voltage which is an input signal is in phase. It becomes 2ID + IDB3) / 2. In this way, the current IDx flowing through each of the transistors MG1 and MG2 is larger than the current ID (constant current 2ID / 2) by 1/2 of the IDB3. On the other hand, the currents IDB4 and IDB5 are drawn from the drains of the transistors MG1 and MG2 by the 11th transistor MG11 and the transistors MB4 and MB5 of the branch portion 122 constituting the current mirror circuit, respectively. As a result, the current ID 11 flowing through the 11th transistor MG 11 becomes IDx-IDB 4, and the current ID 12 flowing through the 12th transistor MG 12 becomes IDx-IDB 5. Therefore, each of the currents IDB4 and IDB5 of the present embodiment is 1/2 of the current IDB3. That is, the increase in the current flowing through the transistors MG1 and MG2, that is, the amount of the current supplied from the current supply unit 121 is passed through the transistors MB4 and MB5. In this way, the current adjusting unit 120F supplies a current equal to the constant current 2ID of the constant current source 11 to the differential pair 181 and causes a current of 1/2 of the constant current 2ID to flow through the transistors MB4 and MB5. , Only the current ID flows through each of the transistors MG11 and MG12. Therefore, the current adjusting unit 120F does not increase the current flowing through the transistors MG11 and MG12 even if the current flowing through the transistors MG1 and MG2 is increased. As a result, the transconductance gm of each transistor MG1 and MG2 of the differential pair 181 increases, but the transconductance of each of the transistors MG11 and MG12 which are active loads does not increase.

In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the 11th transistor MG11 and the 12th transistor MG12. As described above, in the present embodiment, the source potentials of the transistors MG11 and MG12 are further increased. Therefore, the transconductance gm on the circuit of the active load is reduced.

Further, the structure and manufacturing method of the N-channel MOSFET and the P-channel MOSFET of each transistor of the integrating circuit 180B are the structure and manufacturing method of the N-channel MOSFET and the P-channel MOSFET of the transistors MG1 to MG12 of the integrating circuit 180 of the 24th embodiment. Is the same as. Therefore, an effect similar to the effect of (24-5) to (24-10) of the 24th embodiment can be obtained.

Further, since the transistors MB1 to MB5 of the current adjusting unit 120F are not easily affected by the 1 / f noise of the output signal Sout, the impurity concentration in the channel region of each transistor MB1 to MB5 is set to the impurity concentration of each transistor MG1 to MG6, MG9 to. It is higher than the impurity concentration in the channel region in MG12. In other words, the impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is lower than the impurity concentration of the channel region in each of the transistors MB1 to MB5. That is, the transistors MG1 to MG6 and MG9 to MG12 are low-concentration transistors, and the transistors MB1 to MB5 are high-concentration transistors. The impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is preferably about 1/2 or less of the impurity concentration of the channel region of each of the transistors MB1 to MB5. In the present embodiment, the impurity concentration in the channel region of each of the transistors MG1 to MG6 and MG9 to MG12 is about 1/10 of the impurity concentration of the channel region of each of the transistors MB1 to MB5. Further, each transistor MB1 to MB5 is a surface channel type MOSFET.

According to this embodiment, the following effects can be obtained.
(26-1) While the current supplied to the differential pair 181 is increased by the current adjusting unit 120F, the current supplied to the active load is not increased, so that the transconductance of each transistor MG1 and MG2 of the differential pair 181 increases. , The increase in the transconductance of each of the active load transistors MG11 and MG12 is suppressed. Therefore, the noise of the output signal Sout of the integrating circuit 180B can be reduced.

(26-2) Since the source potentials of the active load transistors MG11 and MG12 can be increased by the first resistance R1 and the second resistance R2 connected to the active load, the current flowing through the transistors MG11 and MG12 is reduced. Move in the direction. Therefore, since the transconductance gm of each of the transistors MG11 and MG12 on the circuit is reduced, the noise of the output signal Sout of the integrating circuit 180B can be reduced.

(26-3) The impurity concentration in the channel region of the transistor of the constant current source 182, the impurity concentration in the channel region of each of the transistors MG7 and MG8 of the differential pair 188A, and the impurity concentration in the channel region of the transistor of the constant current source 188B. , The impurity concentrations in the channel region of each of the transistors MB1 and MB3 of the current adjusting unit 120F are equal to each other. According to this configuration, a step of forming the N-type well layer 63 of the transistor of the constant current source 182, a step of forming the N-type well layer 63 of each of the transistors MG7 and MG8, and an N-type of the transistor of the constant current source 188B. The step of forming the well layer 63 and the step of forming the N-type well layer 63 of each of the transistors MB1 and MB3 can be performed collectively. Therefore, the process of manufacturing the integrator circuit 180B can be simplified.

(Modified example of the 26th embodiment)
The integrating circuit 180B of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The first resistance R1, the second resistance R2, the third resistance R3, the resistance R9, and the resistance R10 are omitted from the integrator circuit 180B, and the source and the second branch circuit of the first branch transistor MB4 of the first branch circuit 123. The source of the second branch transistor MB5 of 124 may be connected to the second power supply wiring 3. In this case, the regulated current source 125 may be added to the integrating circuit 180B as in the operational amplifier 1H of the eleventh embodiment. The connection configuration of the transistor MB6 of the adjustment current source 125 and each of the transistors MB2, MB4, MB5 is the same as that of the eleventh embodiment.

For each of the transistors MG1 to MG6 and MG9 to MG12, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current sources 183 and 184. Any one or a set of two of them may be changed to the embedded channel type MOSFET of the second embodiment.

-For each transistor MG1 to MG6 and MG9 to MG12, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors MG1 to MG6 and MG9 to MG12 may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current sources 183 and 184. Any one or two sets may be changed to the same structure as the structure of each transistor M1 to M4 of the third embodiment. Further, a set of each transistor MG1 and MG2 constituting the differential pair 181, a set of each transistor MG11 and MG12 constituting the current mirror circuit 189, and a set of each transistor MG3 and MG4 constituting the constant current source 183 and 184. Any one or a set of two of them may be changed to a structure similar to the structure of the embedded channel MOSFET of the second embodiment or the transistors M1 to M4 of the third embodiment. In short, the integrator circuit 180B has a structure in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. You may.

(27th Embodiment)
The operational amplifier 1V of the 27th embodiment will be described with reference to FIG. 44. The operational amplifier 1V of the present embodiment has the operational amplifier 1 of the first embodiment, the first control unit 110A, the second control unit 110B, the first resistance R1, the second resistance R2, and the output of the fourth embodiment of the eighth embodiment. This is a configuration in which a step 93 is added.

The operational amplifier 1V includes a differential pair 10, a constant current source 11, a current mirror circuit 12 as an active load, a reference current source 13, a backgate bias circuit 20, an output stage 93, a first control unit 110A, and a second control unit 110B. The first resistor R1 and the second resistor R2 are included.

The differential pair 10 of the operational amplifier 1V, the constant current source 11, the current mirror circuit 12, the reference current source 13, and the back gate bias circuit 20 are the differential pair 10 of the operational amplifier 1 of the first embodiment, the constant current source 11, and the current. It has the same configuration as the mirror circuit 12, the reference current source 13, and the back gate bias circuit 20. The connection configuration of the differential pair 10 of the operational amplifier 1V, the constant current source 11, the current mirror circuit 12, the reference current source 13, and the backgate bias circuit 20 is the differential pair 10 of the operational amplifier 1 of the first embodiment, the constant current source. 11. The connection configuration is the same as that of the current mirror circuit 12, the reference current source 13, and the back gate bias circuit 20.

The output stage 93 of the operational amplifier 1V is connected to the node NK1 between the drain of the second transistor M2 and the drain of the fourth transistor M4. The configuration of the output stage 93 of the operational amplifier 1V is the same as that of the output stage 93 of the fourth embodiment.

The first control unit 110A and the second control unit 110B of the operational amplifier 1V have the same configuration as the first control unit 110A and the second control unit 110B of the eighth embodiment. The resistance values of the first resistance R1 and the second resistance R2 of the operational amplifier 1V are the same as the resistance values of the first resistance R1 and the second resistance R2 of the eighth embodiment.

The connection configuration of the first control unit 110A, the second control unit 110B, the first resistance R1, and the second resistance R2 of the operational amplifier 1V is the first control unit 110A, the second control unit 110B, and the first resistance of the eighth embodiment. The connection configuration is the same as that of R1 and the second resistor R2. That is, the source of the first control transistor MA1 of the first control unit 110A is connected to the node NK2 between the third transistor M3 and the first resistance R1, and the second control transistor MA2 of the second control unit 110B is connected. The source of is connected to the node NK3 between the fourth transistor M4 and the second resistance R2.

The operation of this embodiment will be described.
The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 so as to be closer to the first power supply voltage VDD than the source potential of the first transistor M1 and the second transistor M2. do. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Therefore, as shown in FIG. 3, the backgates of the first transistor M1 and the second transistor M2 are the sources of the respective transistors M1 and M2. The transistor conductance gm12 is larger than that in the case of being connected to.

Further, the source of the third transistor M3 is supplied with the first current Ic1 from the first control unit 110A, and the source of the fourth transistor M4 is supplied with the second current Ic2 from the second control unit 110B. The source potential of the three-transistor M3 and the source potential of the fourth transistor M4 increase. In addition, the first resistance R1 and the second resistance R2 raise the source potentials of the third transistor M3 and the fourth transistor M4. As described above, in the present embodiment, the source potentials of the transistors M3 and M4 are further increased as compared with the seventh embodiment. Therefore, the transconductance gm34 on the circuit is further reduced.

As described above, since the transconductance gm12 becomes large and the transconductance gm34 becomes small, the noise of the operational amplifier 1V can be effectively reduced.
According to the present embodiment, the same effect as the effect of (1-1) to (1-4) of the first embodiment and the same effect as the effect of (8-1) of the tenth embodiment can be obtained. ..

Further, the transistors M1 to M4 of the operational amplifier 1V of the present embodiment have the same configuration and manufacturing method as the transistors M1 to M4 of the first embodiment. Therefore, the same effect as the effect of (1-5) to (1-8) of the first embodiment can be obtained. Further, the transistors MA1 and MA2 of the operational amplifier 1V of the present embodiment have the same configuration and manufacturing method as the transistors MA1 and MA2 of the eighth embodiment. Therefore, the same effects as those of (8-2) and (8-3) of the eighth embodiment can be obtained.

(Modified example of the 27th embodiment)
The operational amplifier 1V of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The operational amplifier 1V may include the cascode current mirror circuit 91 and the bias circuit 92 of the fourth embodiment instead of the current mirror circuit 12.
In the operational amplifier 1V, the resistance value of the first resistance R1 and the resistance value of the second resistance R2 may be changed according to the ratio of the third transistor M3 and the fourth transistor M4.

The operational amplifier 1V adds the step-down circuit 100 of the fifth embodiment between the first power supply wiring 2 and the differential pair 10, and more specifically between the first power supply wiring 2 and the constant current source 11. You can also do it. According to this configuration, the same effect as that of the fifth embodiment can be obtained. Further, the back gate bias circuit 20 of the operational amplifier 1V can also be connected to the third power supply wiring 4 like the back gate bias circuit 20 of the sixth embodiment. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

The first control unit 110A and the second control unit 110B may be omitted from the operational amplifier 1V. In this case, the source potentials of the third transistor M3 and the fourth transistor M4 are increased by the first resistance R1 and the second resistance R2.

-For each of the transistors M1 to M4 in the operational amplifier 1V, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, one or two sets of one or two sets of the transistors M1 and M2 constituting the differential pair 10 and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are embedded in the second embodiment. It may be changed to a channel type MOSFET.

-For each of the transistors M1 to M4 in the operational amplifier 1V, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, in the third embodiment, any one or two sets of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1V and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are used. The structure may be changed to the same as the structure of each of the transistors M1 to M4. Further, one or two sets of one or two of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1V and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are secondly implemented. The structure may be changed to the same structure as that of the embedded channel MOSFET of the embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1V has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(28th Embodiment)
The operational amplifier 1W of the 28th embodiment will be described with reference to FIG. 45. The operational amplifier 1W of the present embodiment has a configuration in which the current adjusting unit 120A of the twelfth embodiment, the first resistance R1, the second resistance R2, the third resistance R3, and the output stage 93 are added to the operational amplifier 1 of the first embodiment. be.

The current adjusting unit 120A and the output stage 93 of the operational amplifier 1W have the same configuration as the current adjusting unit 120A and the output stage 93 of the twelfth embodiment. The output stage 93 is connected to the node NL1 between the drain of the second transistor M2 and the drain of the fourth transistor M4. The resistance values of the first resistance R1, the second resistance R2, and the third resistance R3 of the operational amplifier 1W are the resistance values of the first resistance R1, the second resistance R2, and the third resistance R3 of the twelfth embodiment, respectively. Is the same as. The connection configuration of the current adjusting unit 120A, the first resistance R1, the second resistance R2, the third resistance R3, and the output stage 93 of the operational amplifier 1W is the current adjusting unit 120A, the first resistance R1, and the second resistance of the twelfth embodiment. The connection configuration is the same as that of R2, the third resistor R3, and the output stage 93. That is, the source of the first branch transistor MB4 of the branch portion 122 is connected to the node NL2 between the third transistor M3 and the first resistance R1, and the source of the second branch transistor MB5 is the fourth transistor M4. It is connected to the node NL3 between the second resistance R2 and the second resistor R2.

The electrical characteristics of the first branch transistor MB4 of the first branch circuit 123 and the second branch transistor MB5 of the second branch circuit 124 are equal to each other. In addition, since the gate voltages of the transistors MB2, MB4, and MB5 are common, the current amount of the second supply transistor MB2 is 2 of the current amount of the first branch transistor MB4 (second branch transistor MB5). Since it is doubled, the total current flowing through each of the transistors MB4 and MB5 is generated in the second supply transistor MB2.

In the present embodiment, the electrical characteristics of each of the transistors MB4 and MB5 and the third transistor M3 and the fourth transistor M4 are set to be equal to each other. In addition, since the gates of the transistors MB4 and MB5 are connected to the gate of the third transistor M3, the current flowing through the first branching transistor MB4 and the current flowing through the second branching transistor MB5 are the first. It becomes equal to the current flowing through the three transistors M3 (the current flowing through the fourth transistor M4).

The operation of this embodiment will be described. In the following description, the constant current flowing through the constant current source 11 is 2 ID.
The backgate bias circuit 20 applies a bias voltage VB to the backgate of the first transistor M1 and the second transistor M2 so as to be closer to the first power supply voltage VDD than the source potential of the first transistor M1 and the second transistor M2. do. As a result, the backgate-source voltage VBS becomes a voltage near the backgate-source voltage VBSH. Therefore, as shown in FIG. 3, the backgates of the first transistor M1 and the second transistor M2 are the sources of the respective transistors M1 and M2. The transistor conductance gm12 is larger than that in the case of being connected to.

The current flow in the current adjusting unit 120A is the same as the current flow in the current adjusting unit 120A of the twelfth embodiment. That is, the sizes of the supply current IDB3, the current IDB2, IDB4, IDB5, and the current ID3, ID4 are the same as the sizes of the supply current IDB3, the current IDB2, IDB4, IDB5, and the current ID3, ID4 of the ninth embodiment. be. Further, as described in the ninth embodiment, the supply current IDB3 having the same amount of current as the current IDB2, which is the sum of the currents IDB4 and IDB5 flowing through the transistors MB4 and MB5, is supplied to the differential pair 10. Therefore, the current supplied to the differential pair 10 is the sum of the supply current IDB3 and the constant current 2ID, so that the transconductance gm12 of each transistor M1 and M2 increases. On the other hand, since the currents IDB4 and IDB5 are extracted from the currents IDx flowing through the transistors M1 and M2 by the transistors MB4 and MB5, the increase in the transconductance gm34 of the transistors M3 and M4 is suppressed.

The current IDB4 flowing through the first branching transistor MB4 flows through the node NL2 between the third transistor M3 and the first resistor R1, and the current IDB5 flowing through the second branching transistor MB5 is the fourth transistor M4 and the first. It flows to the node NL3 between the two resistors R2. Therefore, the source potential of the third transistor M3 and the source potential of the fourth transistor M4 increase. In addition, as described in the seventh embodiment, the source potentials of the third transistor M3 and the fourth transistor M4 are increased by the first resistance R1 and the second resistance R2. As described above, in the present embodiment, the source potentials of the transistors M3 and M4 are further increased as compared with the seventh embodiment. Therefore, the transconductance gm34 on the circuit is reduced.

As described above, since the transconductance gm12 becomes large and the transconductance gm34 becomes small, the noise of the operational amplifier 1W can be effectively reduced.
According to this embodiment, the same effect as the effect of (1-1) to (1-4) of the first embodiment and the same effect as the effect of the twelfth embodiment can be obtained.

Further, the transistors M1 to M4 of the operational amplifier 1W of the present embodiment have the same configuration and manufacturing method as the transistors M1 to M4 of the first embodiment. Therefore, the same effect as the effect of (1-5) to (1-8) of the first embodiment can be obtained. Further, the transistors MB1 to MB5 of the operational amplifier 1W of the present embodiment have the same configuration and manufacturing method as the transistors MB1 to MB5 of the twelfth embodiment.

(Variation example of the 28th embodiment)
The operational amplifier 1W of this embodiment can be changed as follows. The following modifications can be combined with each other as long as there is no technical contradiction.

The operational amplifier 1W may include the cascode current mirror circuit 91 and the bias circuit 92 of the fourth embodiment instead of the current mirror circuit 12.
In the current adjusting unit 120A of the operational amplifier 1W, the size of the supply current IDB3 from the current supply unit 121 can be arbitrarily changed within a range not exceeding the constant current 2ID. For example, the current ratio between the first supply transistor MB1 and the third supply transistor MB3 may be 2: 1. In this case, the supply current IDB3 of the third supply transistor MB3 is 1/2 of the supply current IDB2. In this way, the supply current IDB3 can be made smaller than the constant current 2ID. As a result, the current IDB4 flowing through the first branching transistor MB4 and the current IDB5 flowing through the second branching transistor MB5 become smaller than the current ID, which is caused by the element variation of the branching transistors MB4 and MB5. The influence on the currents ID3 and ID4 flowing through the three transistors M3 and the fourth transistor M4 can be further reduced.

In the operational amplifier 1W, the resistance value of the first resistance R1, the resistance value of the second resistance R2, and the resistance value of the third resistance R3 are determined by the third transistor M3, the fourth transistor M4, and the second supply transistor MB2. It may be changed according to the ratio.

The operational amplifier 1W adds the step-down circuit 100 of the fifth embodiment between the first power supply wiring 2 and the differential pair 10, and more specifically between the first power supply wiring 2 and the constant current source 11. You can also do it. According to this configuration, the same effect as that of the fifth embodiment can be obtained. Further, the back gate bias circuit 20 of the operational amplifier 1W can also be connected to the third power supply wiring 4 like the back gate bias circuit 20 of the sixth embodiment. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

In the operational amplifier 1W, the fourth resistance R4 and the fifth resistance R5 may be connected to the source of the first branch transistor MB4 and the source of the second branch transistor MB5. In this case, the fourth resistance R4 and the fifth resistance R5 are connected to the second power supply wiring 3 instead of the nodes NL2 and NL3. That is, the current adjusting unit 120A of the operational amplifier 1W may be changed like the current adjusting unit 120B of the operational amplifier 1K of the 14th embodiment. Further, in this case, the current control unit 130 may be added as in the operational amplifier 1K of the 14th embodiment.

The first resistor R1, the second resistor R2, and the third resistor R3 may be omitted from the operational amplifier 1W, and the current adjusting unit 120A of the operational amplifier 1W may be changed as in the current adjusting unit 120 of the ninth embodiment. That is, the source of the second supply transistor MB2, the source of the first branch transistor MB4, and the source of the second branch transistor MB5 may be connected to the second power supply wiring 3. ..

-For each of the transistors M1 to M4 in the operational amplifier 1W, an embedded channel type MOSFET such as the transistors M1 to M4 of the second embodiment may be applied instead of lowering the impurity concentration in the channel region. As a result, the same effect as that of the second embodiment can be obtained. Further, one or two sets of one or two sets of the transistors M1 and M2 constituting the differential pair 10 and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are embedded in the second embodiment. It may be changed to a channel type MOSFET.

-For each of the transistors M1 to M4 in the operational amplifier 1W, in addition to lowering the impurity concentration in the channel region, an embedded channel type MOSFET may be applied. That is, the transistors M1 to M4 may have the same structure as the transistors M1 to M4 of the third embodiment. As a result, the same effect as that of the third embodiment can be obtained. Further, the third embodiment includes any one or two sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1W and the transistors M3 and M4 constituting the current mirror circuit 12. The structure may be changed to the same as the structure of each of the transistors M1 to M4. Further, one or two sets of one or two of the sets of the transistors M1 and M2 constituting the differential pair 10 in the operational amplifier 1W and the sets of the transistors M3 and M4 constituting the current mirror circuit 12 are secondly implemented. The structure may be changed to the same structure as that of the embedded channel MOSFET of the embodiment or the transistors M1 to M4 of the third embodiment. In short, the operational amplifier 1W has a configuration in which the low-concentration transistor of the first embodiment, the embedded channel MOSFET of the second embodiment, and the structures similar to the structures of the transistors M1 to M4 of the third embodiment are mixed. May be good.

(Modification example)
The description of each of the above embodiments is an example of possible embodiments of the differential circuit of the present invention and is not intended to limit the embodiments. The differential circuit of the present invention may take, for example, a modification of each of the above embodiments shown below, and a combination of at least two modifications that do not contradict each other.

In each of the above embodiments, the element separation region 35 in the silicon substrate 30 has an STI structure, but the structure is not limited to this, and a LOCOS (local oxidation of silicon) structure may be used.

In each of the above embodiments, the source region 45 of the N-channel MOSFET among the plurality of transistors of the differential circuit is composed of the low concentration source region 47 and the high concentration source region 48, and the drain region 46 is the low concentration drain region 49 and the high concentration region 49. It was a so-called DDD (Double Diffused Drain) type MOSFET consisting of a concentration drain region 50, but the structure of the N-channel MOSFET is not limited to this. For example, the source region 45 of the N-channel MOSFET may be composed of only the high-concentration source region 48, and the drain region 46 may be composed of only the high-concentration drain region 50. Similarly, in the source region 64 and the drain region 65 of the P-channel MOSFET among the plurality of transistors of the differential circuit, the source region 64 is composed of only the high-concentration source region 67, and the drain region 65 is only the high-concentration drain region 69. It may consist of.

The gate insulating film 42 is not limited to the silicon oxide film, and may be made of a high dielectric constant material (High—K material). Examples of the high dielectric constant material include HfO ₂ , HfSiON, SiON, Si ₃ N ₄ , Al ₂ O ₃ , Ta ₂ O ₅ , TiO ₂ , La ₂ O ₃ , CeO ₂ , ZrO ₂ , HfO ₂ , and SrTIO ₃ . , Pr ₂ O ₃ and the like are conceivable.

When a high dielectric constant material is adopted as the gate insulating film 42, scattering at the interface between the channel region and the gate insulating film 42 tends to occur depending on the high dielectric constant material, and the 1 / f noise characteristics deteriorate. There may be concerns. In this respect, for example, by adopting an embedded channel type MOSFET as in the second embodiment, deterioration of 1 / f noise characteristics due to scattering at the interface can be suppressed, so that the gate insulating film 42 is highly dielectric. The above concerns caused by the adoption of the ratio material can be suppressed.

In the first embodiment, the impurity concentration of the P-type well layer 62 (N-type well layer 70) of some of the plurality of transistors of the differential circuit is set to the P-type well layer 41 (N) of another transistor. Although it is lower than the impurity concentration of the mold well layer 63), the structure of the plurality of transistors is not limited to this. For example, as shown in FIG. 46, a P-type epitaxial layer 31 is used as a conductive region forming a channel region of the third transistor M3 (N-channel MOSFET) as an example of the above-mentioned some transistors, and the above-mentioned some transistors. As an example, an N-type well layer 39 having a high withstand voltage may be used as a conductive region forming a channel region of the first transistor M1 (P channel MOSFET).

In the third transistor M3 of FIG. 46, a source region 45 and a drain region 46 are formed on the surface layer portion of the P-type epitaxial layer 31. That is, a channel region is formed in the P-type epitaxial layer 31. The channel region of the third transistor M3 in FIG. 46 is located below the gate insulating film 42 of the P-type epitaxial layer 31 and is arranged between the source region 45 and the drain region 46. The channel region of the third transistor M3 in FIG. 46 includes an interface between the P-type epitaxial layer 31 and the gate insulating film 42. The impurity concentration in the channel region of the third transistor M3 is the same as the impurity concentration in the P-type epitaxial layer 31.

The impurity concentration of the P-type epitaxial layer 31 in the third transistor M3 of FIG. 46 is lower than, for example, the impurity concentration of the P-type well layer 41 (see FIG. 5A) of the sixth transistor M6. In one example, the impurity concentration of the P-type epitaxial layer 31 is about ½ or less of the impurity concentration of the P-type well layer 41 of the sixth transistor M6. Preferably, the impurity concentration of the P-type epitaxial layer 31 is about 1/10 of the impurity concentration of the P-type well layer 41 of the sixth transistor M6.

In the first transistor M1 of FIG. 46, a source region 64 and a drain region 65 are formed on the surface layer portion of the N-type well layer 39. That is, a channel region is formed in the N-type well layer 39. The channel region of the first transistor M1 in FIG. 46 is located below the gate insulating film 42 in the N-type well layer 39 and is arranged between the source region 64 and the drain region 65. The channel region of the first transistor M1 in FIG. 46 includes an interface between the N-type well layer 39 and the gate insulating film 42. The impurity concentration in the channel region of the first transistor M1 is the same as the impurity concentration in the N-type well layer 39.

The impurity concentration of the N-type well layer 39 in the first transistor M1 of FIG. 46 is lower than, for example, the impurity concentration of the N-type well layer 63 (see FIG. 5C) of the eighth transistor M8. In one example, the impurity concentration of the N-type well layer 39 is about ½ or less of the impurity concentration of the N-type well layer 63 of the eighth transistor M8. Preferably, the impurity concentration of the N-type well layer 39 is about 1/10 of the impurity concentration of the N-type well layer 63 of the eighth transistor M8.

[Transistor manufacturing method]
Next, a method of manufacturing the first transistor M1 and the third transistor M3 of FIG. 46 will be described with reference to FIGS. 47A to 47H. In the method for manufacturing these transistors, the epitaxial layer forming step, the isolation forming step, and the wiring step are the same as those in the first embodiment, so the description thereof will be omitted, and the well forming step, the gate forming step, and the source. The part different from the first embodiment in the drain forming step will be mainly described.

As shown in FIG. 47A, in the well forming step, the N-type well layer 39 is formed in the element forming region 34 corresponding to the first transistor M1, while the N-type well is formed in the element forming region 34 corresponding to the third transistor M3. Layer 39 is not formed. Specifically, an ion implantation mask 86 that covers the element forming region 34 and the element separation region 35 corresponding to the third transistor M3 while opening the element forming region 34 corresponding to the first transistor M1 is formed, and the first transistor is formed. N-type impurity ions are implanted into the device forming region 34 corresponding to M1. For example, phosphorus ion is used as the N-type impurity ion. After that, the ion implantation mask 86 is removed.

Next, as shown in FIGS. 47B and 47C, a P-type well layer 36 is formed in each of the element separation regions 35 after the P-type drift layer 37 is formed as in the first embodiment (see FIG. 6F). Will be done. Then, as shown in FIG. 47D, a thermal oxide film 75 is formed on the surface of each element forming region 34 of the P-type epitaxial layer 31 by, for example, a thermal oxidation method. Next, the polysilicon film 76 is formed so as to cover the thermal oxide film 75 and the silicon oxide film 33. Then, as shown in FIG. 47E, unnecessary portions of the thermal oxide film 75 and the polysilicon film 76 are removed from the element forming region 34 corresponding to the first transistor M1 and the third transistor M3 by, for example, photolithography and etching. The gate insulating film 42 and the gate electrode 43 patterned in a predetermined shape are formed. Then, for example, after a nitride film (not shown) is formed on the P-type epitaxial layer 31 by a CVD method, the nitride film is selectively etched to form a sidewall 44 on the side surface of each gate electrode 43.

As shown in FIG. 47F, a low-concentration source region 47 and a low-concentration drain region 49 are formed in the element forming region 34 (P-type epitaxial layer 31) of the third transistor M3, and the element forming region 34 (N) of the first transistor M1 is formed. A low-concentration source region 66 and a low-concentration drain region 68 are formed in the mold well layer 39). Specifically, an ion implantation mask (not shown) having an opening that exposes the element forming region 34 of the third transistor M3 is formed so as to cover the element forming region 34 and the element separation region 35 of the first transistor M1. To. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 (N-type well layer 39) of the first transistor M1 is the element forming region of the third transistor M3. It is formed so as to cover the 34 and the element separation region 35. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. In this modification, the low-concentration source region 47 and the low-concentration drain region 49 were formed, and then the low-concentration source region 66 and the low-concentration drain region 68 were formed, but the low-concentration source region 66 and the low-concentration drain were formed. After the region 68 is formed, the low concentration source region 47 and the low concentration drain region 49 may be formed.

As shown in FIG. 47G, the high-concentration source region 48 and the high-concentration drain region 50 are formed in the element forming region 34 (P-type epitaxial layer 31) of the third transistor M3, and the element forming region 34 (N) of the first transistor M1 is formed. A high-concentration source region 67 and a high-concentration drain region 69 are formed in the mold well layer 39). Specifically, an ion implantation mask (not shown) having an opening for exposing the P-type epitaxial layer 31 in the element forming region 34 of the third transistor M3 is an N-type well layer 39 in the element forming region 34 of the first transistor M1. And is formed so as to cover the element separation region 35. Then, N-type impurity ions are implanted through the opening of this ion implantation mask. For example, arsenic ion is used as the N-type impurity ion. Next, the ion implantation mask (not shown) having an opening for removing the ion implantation mask and exposing the element forming region 34 of the first transistor M1 forms the element forming region 34 and the element separation region 35 of the third transistor M3. Formed to cover. Then, P-type impurity ions are implanted through the opening of this ion implantation mask. For example, boron ion is used as the P-type impurity ion. In this modification, after the high-concentration source region 48 and the high-concentration drain region 50 were formed, the high-concentration source region 67 and the high-concentration drain region 69 were formed, but the high-concentration source region 67 and the high-concentration drain were formed. After the region 69 is formed, the high concentration source region 48 and the high concentration drain region 50 may be formed.

As shown in FIG. 47H, the high-concentration source region 48, the high-concentration drain region 50, and the silicide layer 77 formed on the surface of the element forming region 34 (P-type epitaxial layer 31) of the third transistor M3 are formed on the surface of the gate electrode 43. It is formed. Further, a silicide layer 77 is formed on the surfaces of the high-concentration source region 67, the high-concentration drain region 69, and the gate electrode 43 formed in the element forming region 34 (N-type well layer 39) of the first transistor M1. Specifically, a cobalt film (not shown) is formed in the direction of the P-type epitaxial layer 31 by, for example, the PVD method, and then heat treatment is performed. As a result, the cobalt film of the high-concentration source regions 48 and 67, the high-concentration drain regions 50 and 69, and the gate electrode 43 in each element forming region 34 changes to the silicide layer 77, while the silicon oxide film in each element separation region 35. The cobalt film on 33 remains cobalt. Then, for example, cobalt on each silicon oxide film 33 is selectively removed by chemical treatment.

In the modified example of FIG. 46, the structure may be changed to the same structure as the structures of the transistors M1 to M4 of the third embodiment. That is, in the third transistor M3 of FIG. 46, an embedded channel layer (not shown) may be formed in the P-type epitaxial layer 31. The embedded channel layer is the same conductive region (layer) as the source region 45 and the drain region 46. That is, the embedded channel layer is the same N-type region (layer) as the source region 45 and the drain region 46 doped with N-type impurities. The channel region (embedded channel layer) of the third transistor M3 does not include the interface between the P-type epitaxial layer 31 and the gate insulating film 42. The impurity concentration in the channel region (embedded channel layer) of the third transistor M3 is higher than the impurity concentration in the P-type epitaxial layer 31. Further, the fourth transistor M4 has the same configuration as the third transistor M3.

Further, in the first transistor M1 of FIG. 46, an embedded channel layer (not shown) may be formed in the N-type well layer 39. The embedded channel layer is the same conductive region (layer) as the source region 64 and the drain region 65. That is, the embedded channel layer is the same P-type region (layer) as the source region 64 and the drain region 65 doped with P-type impurities. The channel region (embedded channel layer) of the first transistor M1 does not include the interface between the N-type well layer 39 and the gate insulating film 42. The impurity concentration in the channel region (embedded channel layer) of the first transistor M1 is higher than the impurity concentration in the N-type well layer 39. Further, the second transistor M2 has the same configuration as the first transistor M1.

-In each of the above embodiments, each transistor constituting the operational amplifier may be a high-concentration transistor. That is, the transistor that is easily affected by 1 / f noise in the operational amplifier may be a high-concentration transistor.

-In each of the above embodiments, each transistor constituting the operational amplifier may be a low-concentration transistor. That is, the transistor that is not easily affected by 1 / f noise in the operational amplifier may be a low-concentration transistor.

-In each of the above embodiments, each transistor constituting the operational amplifier may be a surface channel type MOSFET. That is, the transistor that is easily affected by 1 / f noise in the operational amplifier may be a surface channel type MOSFET.

-In each of the above embodiments, each transistor constituting the operational amplifier may be an embedded channel type MOSFET. That is, the transistor that is not easily affected by 1 / f noise in the operational amplifier may be an embedded channel type MOSFET.

The transistors MA1 and MA2 constituting the first control unit 110A and the second control unit 110B may be bipolar transistors instead of MOSFETs. In this case, the base of the bipolar transistor corresponds to the "control terminal of the first control transistor" and the "control terminal of the second control transistor".

The transistors MB1 to MB5 constituting the current adjusting units 120 to 120F may be bipolar transistors instead of MOSFETs. In this case, the base of the bipolar transistor as the first branching transistor corresponds to the "control terminal of the first adjusting transistor". The base of the bipolar transistor as the second branching transistor corresponds to the "control terminal of the second adjusting transistor". The base of the bipolar transistor as the second supply transistor corresponds to the "control terminal of the second supply transistor".

The operational amplifier or the integrating circuit of the 7th to 14th, 16th, 17th, 19th, 20th, 22nd, and 23rd embodiments or the integrating circuit of the 25th and 26th embodiments, that is, the operational amplifier or the integrating circuit not provided with the backgate bias circuit 20 is configured. Each transistor may be a bipolar transistor instead of the MOSFET.

A backgate bias circuit 20 may be added to the operational amplifier of the 16th, 17th, 19th, 20th, 22nd, and 23rd embodiments or the integrating circuit of the 25th and 26th embodiments. In this case, a step-down circuit 100 can be added between the first power supply wiring 2 and the differential pair. According to this configuration, the same effect as that of the fifth embodiment can be obtained. Further, the back gate bias circuit 20 can also be connected to the third power supply wiring 4 like the back gate bias circuit 20 of the sixth embodiment. According to this configuration, the same effect as that of the sixth embodiment can be obtained.

The backgate bias circuit 20 (20A, 20B) may be manufactured on a semiconductor substrate different from the operational amplifier.
In each of the above embodiments, the channel lengths of the transistors constituting the differential pair 10,151,161,171,172,181 are set to active loads (current mirror circuits 12,189 and cascode current mirror circuits 91,163,176). It may be shorter than the channel length of the transistor constituting the above. Although the element area increases due to such a relationship of channel length, the fluctuation of mobility can be suppressed, so that the noise of the output signal Sout can be further reduced.

(Additional note)
Next, the technical ideas that can be grasped from the above embodiments and the above modifications will be described.
(Appendix A1)
The differential pair includes a first differential pair and a second differential pair, and the differential circuit supplies current to the first differential pair and to the second differential pair. The difference according to any one of claims 24 to 26, further comprising a current switching unit for switching between current supply and the plurality of transistors, wherein the transistor constituting the current switching unit is the low concentration transistor. Dynamic circuit.

(Appendix A2)
The differential circuit according to Appendix A1, wherein the low-concentration transistor constituting the current switching unit is an enhancement type MOS transistor.

(Appendix A3)
Note that any of the transistor constituting the current switching unit, the transistor constituting the first differential pair, and the transistor constituting the second differential pair is the low-concentration transistor of the same conductive type. The differential circuit according to A1 or A2.

(Appendix B1)
The backgate bias circuit includes a plurality of MOS transistors, the plurality of MOS transistors are surface channel type MOS transistors, and the first MOS transistor and the second MOS transistor are embedded channel type MOS transistors. The differential circuit according to any one of claims 1 to 23.

(Appendix B2)
The differential circuit according to Appendix B1, wherein the first MOS transistor and the second MOS transistor are enhancement type MOS transistors.

(Appendix B3)
The differential circuit has an active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor, and constitutes the active load among the plurality of transistors. The differential circuit according to Supplementary note B1 or B2, wherein the transistor is an embedded channel type MOS transistor.

(Appendix B4)
The differential circuit according to Appendix B3, wherein the transistor constituting the active load is an enhancement type MOS transistor.

(Appendix B5)
The differential pair includes a first differential pair and a second differential pair, and the differential circuit supplies current to the first differential pair and to the second differential pair. The transistor further including a current switching unit for switching the current supply and constituting the current switching unit among the plurality of transistors is described in any one of the appendices B1 to B4, which is an embedded channel type MOS transistor. Differential circuit.

(Appendix B6)
The differential circuit according to Appendix B5, wherein the transistor constituting the current switching unit is an enhancement type MOS transistor.

(Appendix C1)
The backgate bias circuit includes a plurality of MOS transistors, the plurality of MOS transistors are surface channel type MOS transistors, and the first MOS transistor and the second MOS transistor are embedded channel type MOS transistors. The differential circuit according to any one of claims 1 to 23, wherein the impurity concentration in the channel region of the embedded channel type MOS transistor is lower than the impurity concentration in the channel region of the surface channel type MOS transistor.

(Appendix C2)
The differential circuit according to Appendix C1, wherein the first MOS transistor and the second MOS transistor are enhancement type MOS transistors.

(Appendix C3)
The differential circuit has an active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor, and constitutes the active load among the plurality of transistors. The transistor is the differential circuit according to Supplementary note C1 or C2, which is the embedded channel type MOSFET.

(Appendix C4)
The differential circuit according to Appendix C3, wherein the transistor constituting the active load is an enhancement type MOSFET.

(Appendix C5)
The differential pair includes a first differential pair and a second differential pair, and the operational amplifier has a current supply to the first differential pair and a current to the second differential pair. The transistor further including a current switching unit for switching between supply and the plurality of transistors constituting the current switching unit is described in any one of the appendices C1 to C4, which is an embedded channel type MOS transistor. Differential circuit.

(Appendix C6)
The differential circuit according to Appendix C5, wherein the transistor constituting the current switching unit is an enhancement type MOS transistor.

(Appendix C7)
The transistor constituting the current switching unit, the transistor constituting the first differential pair, and the transistor constituting the second differential pair are the same conductive type embedded channel type MOS transistors. A differential circuit according to Supplementary note C5 or C6.

(Appendix C8)
The differential according to any one of Supplementary note C1 to C7, wherein the impurity concentration in the channel region of the embedded channel type MOS transistor is about ½ of the impurity concentration in the channel region of the surface channel type MOS transistor. circuit.

1,1A to 1W operational amplifier (differential circuit)
2 First power supply wiring 3 Second power supply wiring 4 Third power supply wiring 10,151,161,181 Differential pair 12 Current mirror circuit (active load)
20, 20A, 20B Backgate bias circuit 91,163,176 Cascode current mirror circuit 92,164,177 Bias circuit 100 Step-down circuit (voltage conversion circuit)
103 Booster circuit (voltage conversion circuit)
110A 1st control unit 110B 2nd control unit 111 1st constant current source 112 2nd constant current source 120, 120A to 120F Current adjustment unit 121 Current supply unit 125 Adjusting current source (current source)
131 1st control unit 132 2nd control unit 171 1st differential pair (differential pair)
172 Second differential pair (differential pair)
180 Integrator circuit (differential circuit)
M1, MD1, ME1 1st transistor (1st MOS transistor)
M2, MD2, ME2 2nd transistor (2nd MOS transistor)
M3 3rd transistor (3rd MOS transistor)
M4 4th transistor (4th MOS transistor)
M5 to M9 Multiple MOS Transistors in Backgate Bias Circuit M10, MF10 10th Transistor (5th MOS Transistor)
M11, MF11 11th transistor (6th MOS transistor)
M12, MF12 12th transistor (7th MOS transistor)
M13, MF13 13th transistor (8th MOS transistor)
MD4 4th transistor (3rd MOS transistor)
MD5 5th transistor (4th MOS transistor)
ME4 4th transistor (5th MOS transistor)
ME5 5th transistor (6th MOS transistor)
ME6 6th transistor (7th MOS transistor)
ME7 7th transistor (8th MOS transistor)
MF4 4th transistor (1st MOS transistor)
MF5 5th transistor (2nd MOS transistor)
MF7 7th transistor (1st MOS transistor)
MF8 8th transistor (2nd MOS transistor)
MA1 1st control transistor MA2 2nd control transistor MB1 1st supply transistor MB2 2nd supply transistor MB3 3rd supply transistor MB4 1st branch transistor (1st adjustment transistor)
MB5 Second branch transistor (second adjustment transistor)
R1 1st resistance (1st resistance part)
R2 2nd resistance (2nd resistance part)
R3 3rd resistance (3rd resistance part)
VB bias voltage VDD, VDD1 first power supply voltage VSS, VSS1 second power supply voltage VDD2 third power supply voltage

Claims (42)

A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor.
A first resistance portion provided between the third MOS transistor and the second power supply wiring,
A second resistance portion provided between the fourth MOS transistor and the second power supply wiring, and
A first control unit that controls the source potential of the third MOS transistor by supplying a current between the source of the third MOS transistor and the first resistance unit.
A second control unit that controls the source potential of the fourth MOS transistor by supplying a current between the source of the fourth MOS transistor and the second resistance unit.
A differential circuit with . A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
Equipped with
The backgate bias circuit includes a plurality of MOS transistors and includes a plurality of MOS transistors.
The plurality of MOS transistors are high-concentration transistors in which the impurity concentration in the channel region is the first concentration.
The first MOS transistor and the second MOS transistor are low-concentration transistors having a second concentration in which the impurity concentration in the channel region is lower than the first concentration.
Differential circuit. The differential circuit includes a cascode current mirror circuit as an active load.
The cascode current mirror circuit includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor.
The drain of the 5th MOS transistor is connected to the drain of the 1st MOS transistor, and the source of the 5th MOS transistor is connected to the 2nd power supply wiring.
The drain of the 6th MOS transistor is connected to the drain of the 2nd MOS transistor, and the source of the 6th MOS transistor is connected to the 2nd power supply wiring.
The source of the 7th MOS transistor is connected to the drain of the 5th MOS transistor.
The source of the 8th MOS transistor is connected to the drain of the 6th MOS transistor.
The gates of the 7th MOS transistor and the 8th MOS transistor are commonly connected, and a predetermined bias voltage is applied.
The fifth MOS transistor and the sixth MOS transistor are the low concentration transistors.
The differential circuit according to claim 2 , wherein the 7th MOS transistor and the 8th MOS transistor are high-concentration transistors. The first power supply voltage provided between the first power supply wiring and the differential pair is set to a voltage closer to the source potential of the first MOS transistor and the second MOS transistor than the first power supply voltage. The differential circuit according to any one of claims 1 to 3, which includes a voltage conversion circuit to be converted. The backgate bias circuit generates the bias voltage by a third power supply voltage different from the first power supply voltage.
The differential circuit according to any one of claims 1 to 4, wherein the first power supply voltage is a voltage closer to the source potential of the first MOS transistor and the second MOS transistor than the third power supply voltage. The differential according to any one of claims 1 to 5 , wherein the bias voltage is a voltage excluding the voltage within a predetermined range including the first power supply voltage, which is the same as the first power supply voltage. circuit. The first power supply voltage is higher than the second power supply voltage.
The first MOS transistor and the second MOS transistor are P-channel MOS transistors, and the first MOS transistor and the second MOS transistor are P-channel MOS transistors.
The differential circuit according to claim 6 , wherein the bias voltage is higher than the first power supply voltage. The differential circuit according to claim 7 , wherein the bias voltage is lower than the voltage at which the parasitic diodes of the first MOS transistor and the second MOS transistor are turned on. The differential circuit according to any one of claims 6 to 8 , wherein the bias voltage is a voltage within ± 20% of the first power supply voltage. The second power supply voltage is higher than the first power supply voltage.
The first MOS transistor and the second MOS transistor are N-channel MOS transistors, and the first MOS transistor and the second MOS transistor are N-channel MOS transistors.
The differential circuit according to any one of claims 1 to 6 , wherein the bias voltage is lower than the first power supply voltage. The differential circuit according to claim 2, wherein the second concentration is about ½ or less of the first concentration, or any one of claims 3 to 10 quoting claim 2 . The differential circuit according to claim 11 , wherein the second concentration is about 1/10 of the first concentration. A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor.
A first resistance portion provided between the third MOS transistor and the second power supply wiring,
A second resistance portion provided between the fourth MOS transistor and the second power supply wiring, and
A first control unit that controls the source potential of the third MOS transistor by supplying a current between the source of the third MOS transistor and the first resistance unit.
A second control unit that controls the source potential of the fourth MOS transistor by supplying a current between the source of the fourth MOS transistor and the second resistance unit.
Equipped with
The backgate bias circuit includes a plurality of MOS transistors and includes a plurality of MOS transistors.
The plurality of MOS transistors are high-concentration transistors in which the impurity concentration in the channel region is the first concentration.
The first MOS transistor and the second MOS transistor are low-concentration transistors having a second concentration in which the impurity concentration in the channel region is lower than the first concentration.
Differential circuit. The first control unit includes a first control transistor connected between the source of the third MOS transistor and the first resistance unit.
The second control unit includes a second control transistor connected between the source of the fourth MOS transistor and the second resistance unit.
The differential circuit according to claim 1 or 13 , wherein the voltage of the control terminal of the first control transistor and the second control transistor is controlled by the gate voltage of the third MOS transistor and the fourth MOS transistor. .. The first control unit further includes a first power supply wiring and a first current source connected to the first control transistor.
The differential circuit according to claim 14 , wherein the second control unit further includes a second power supply wiring and a second current source connected to the second control transistor. The differential circuit according to claim 1 or 13, further comprising a current adjusting unit for increasing the current flowing through the first MOS transistor and the second MOS transistor to be larger than the current flowing through the third MOS transistor and the fourth MOS transistor. The current adjusting unit is
A first adjusting transistor connected in parallel with the third MOS transistor,
The differential circuit according to claim 16 , further comprising a second adjusting transistor connected in parallel with the fourth MOS transistor and having a control terminal connected to the control terminal of the first adjusting transistor. The current adjusting unit supplies a current for adjusting the amount of current, which is the sum of the amount of current flowing through the first adjusting transistor and the amount of current flowing through the second adjusting transistor, to the differential pair. The differential circuit according to claim 17 , which has a part. The current supply unit includes a first supply transistor and a second supply transistor connected in series between the first power supply wiring and the second power supply wiring, and the first power supply wiring. It includes a third supply transistor provided between the differential pair and a third resistance portion provided between the second supply transistor and the second power supply wiring.
The first supply transistor is provided between the second supply transistor and the first power supply wiring.
The control terminal of the second supply transistor is connected to the control terminal of the first adjustment transistor and the control terminal of the second adjustment transistor.
The differential circuit according to claim 18 , wherein the third supply transistor constitutes a current mirror circuit with the first supply transistor, and supplies the adjustment current to the differential pair. The differential circuit according to any one of claims 17 to 19 , wherein the first adjusting transistor and the second adjusting transistor flow a current equal to or less than the current flowing through the third MOS transistor. An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor and having a gate connected to the gate of the third MOS transistor.
The differential circuit according to claim 2, further comprising a current adjusting unit for increasing the current flowing through the first MOS transistor and the second MOS transistor to be larger than the current flowing through the third MOS transistor and the fourth MOS transistor. The current adjusting unit is
A first adjusting transistor connected in parallel with the third MOS transistor,
21. The differential circuit of claim 21 , wherein the differential circuit is connected in parallel with the fourth MOS transistor and has a second adjusting transistor whose control terminal is connected to the control terminal of the first adjusting transistor. The current adjusting unit supplies a current for adjusting the amount of current, which is the sum of the amount of current flowing through the first adjusting transistor and the amount of current flowing through the second adjusting transistor, to the differential pair. 22. The differential circuit according to claim 22 having a unit. The current supply unit includes a first supply transistor and a second supply transistor connected in series between the first power supply wiring and the second power supply wiring, and the first power supply wiring. Including a third supply transistor provided between the differential pair and
The first supply transistor is provided between the second supply transistor and the first power supply wiring.
The control terminal of the second supply transistor is connected to the control terminal of the first adjustment transistor and the control terminal of the second adjustment transistor.
The differential circuit according to claim 23 , wherein the third supply transistor constitutes a current mirror circuit with the first supply transistor, and supplies the adjustment current to the differential pair. The differential circuit according to claim 23 or 24 , wherein the first adjusting transistor and the second adjusting transistor flow a current equal to or less than the current flowing through the third MOS transistor. The current supply unit biases the first adjusting transistor and the second adjusting transistor by a current source so that a current equal to or less than the current flowing through the third MOS transistor flows. The differential circuit according to one item. An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor.
A first resistance portion provided between the third MOS transistor and the second power supply wiring,
A second resistance portion provided between the fourth MOS transistor and the second power supply wiring
Equipped with
The differential circuit according to any one of claims 2, 11, and 12 , wherein the third MOS transistor and the fourth MOS transistor of the active load are the low concentration transistors. An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor and having a gate connected to the gate of the third MOS transistor.
With a current adjusting unit that makes the current flowing through the first MOS transistor and the second MOS transistor larger than the current flowing through the third MOS transistor and the fourth MOS transistor.
Equipped with
The differential circuit according to any one of claims 2, 11, and 12 , wherein the third MOS transistor and the fourth MOS transistor of the active load are the low concentration transistors. A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor.
A first resistance portion provided between the third MOS transistor and the second power supply wiring,
A second resistance portion provided between the fourth MOS transistor and the second power supply wiring
Equipped with
The third MOS transistor and the fourth MOS transistor are embedded channel type MOS transistors.
Differential circuit. A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor and having a gate connected to the gate of the third MOS transistor.
With a current adjusting unit that makes the current flowing through the first MOS transistor and the second MOS transistor larger than the current flowing through the third MOS transistor and the fourth MOS transistor.
Equipped with
The third MOS transistor and the fourth MOS transistor are embedded channel type MOS transistors.
Differential circuit. The differential circuit according to claim 27 or 28 , wherein the third MOS transistor and the fourth MOS transistor are embedded channel type MOS transistors. The fifth MOS transistor and the sixth MOS transistor are embedded channel type MOS transistors.
The differential circuit according to any one of claims 3 or 4 to 10, wherein the 7th MOS transistor and the 8th MOS transistor are surface channel type MOS transistors. The differential circuit according to any one of claims 2, 11 to 13, 27, 28 , 31 , and 32 , wherein the plurality of MOS transistors are surface channel type MOS transistors. The differential circuit according to any one of claims 2, 11 to 13, and 27 to 33 , wherein the first MOS transistor and the second MOS transistor are embedded channel type MOS transistors. The difference according to claim 14 or 15 , wherein the impurity concentration in the channel region of the first control transistor and the second control transistor is higher than the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor. Dynamic circuit. The differential circuit according to any one of claims 14 , 15 , and 35 , wherein the first control transistor and the second control transistor are surface channel type MOS transistors. Any one of claims 17 to 20 , wherein the impurity concentration in the channel region of the first adjusting transistor and the second adjusting transistor is higher than the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor. The differential circuit described in the section. The differential circuit according to any one of claims 17 to 20 and 37 , wherein the first adjusting transistor and the second adjusting transistor are surface channel type MOS transistors. A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor.
A first resistance portion provided between the third MOS transistor and the second power supply wiring,
A second resistance portion provided between the fourth MOS transistor and the second power supply wiring, and
With a current adjusting unit that makes the current flowing through the first MOS transistor and the second MOS transistor larger than the current flowing through the third MOS transistor and the fourth MOS transistor.
Equipped with
The current adjusting unit is
The first adjusting transistor connected in parallel with the third MOS transistor,
A second adjusting transistor connected in parallel with the fourth MOS transistor and having a control terminal connected to the control terminal of the first adjusting transistor.
With the current supply unit that supplies the adjusting current of the total amount of the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor to the differential pair.
Have,
The current supply unit includes a first supply transistor and a second supply transistor connected in series between the first power supply wiring and the second power supply wiring, and the first power supply wiring. It includes a third supply transistor provided between the differential pair and a third resistance portion provided between the second supply transistor and the second power supply wiring.
The first supply transistor is provided between the second supply transistor and the first power supply wiring.
The control terminal of the second supply transistor is connected to the control terminal of the first adjustment transistor and the control terminal of the second adjustment transistor.
The third supply transistor constitutes a current mirror circuit with the first supply transistor, and supplies the adjustment current to the differential pair.
The impurity concentration in the channel region of the first supply transistor, the second supply transistor, and the third supply transistor is higher than the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor.
Differential circuit. A first MOS transistor and a first MOS transistor provided between a first power supply wiring to which a first power supply voltage is applied and a second power supply wiring to which a second power supply voltage different from the first power supply voltage is applied. With a differential pair containing a 2MOS transistor,
A backgate bias circuit that applies a bias voltage closer to the first power supply voltage than the source potential of the first MOS transistor and the second MOS transistor to the backgate of the first MOS transistor and the second MOS transistor.
An active load including a third MOS transistor connected to the first MOS transistor and a fourth MOS transistor connected to the second MOS transistor and having a gate connected to the gate of the third MOS transistor.
With a current adjusting unit that makes the current flowing through the first MOS transistor and the second MOS transistor larger than the current flowing through the third MOS transistor and the fourth MOS transistor.
Equipped with
The current adjusting unit is
A first adjusting transistor connected in parallel with the third MOS transistor,
A second adjusting transistor connected in parallel with the fourth MOS transistor and having a control terminal connected to the control terminal of the first adjusting transistor.
With the current supply unit that supplies the adjusting current of the total amount of the current flowing through the first adjusting transistor and the current flowing through the second adjusting transistor to the differential pair.
Have,
The current supply unit includes a first supply transistor and a second supply transistor connected in series between the first power supply wiring and the second power supply wiring, and the first power supply wiring. Including a third supply transistor provided between the differential pair and
The first supply transistor is provided between the second supply transistor and the first power supply wiring.
The control terminal of the second supply transistor is connected to the control terminal of the first adjustment transistor and the control terminal of the second adjustment transistor.
The third supply transistor constitutes a current mirror circuit with the first supply transistor, and supplies the adjustment current to the differential pair.
The impurity concentration in the channel region of the first supply transistor, the second supply transistor, and the third supply transistor is higher than the impurity concentration in the channel region of the first MOS transistor and the second MOS transistor.
Differential circuit. The differential circuit according to claim 39 or 40 , wherein the first supply transistor, the second supply transistor, and the third supply transistor are surface channel type MOS transistors. The differential circuit according to any one of claims 1 to 41 used as an operational amplifier.

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