JP7041285B2 - Hosts that communicate with the FPGA, methods of communicating with the FPGA, and communication systems - Google Patents

Description

The present invention relates to the field of programmable logic devices. Specifically, the present invention relates to a host that communicates with the FPGA, a method of communicating with the FPGA, and an FPGA interface chip.

FPGA (Field-Programmable Gate Array) is a programmable logic device. FPGA chips typically integrate with an on-chip control system. In the on-chip control system, the user places and debugs the FPGA via an interface such as JTAG (Joint Test Action Group) or SPI (Serial Peripheral Interface). It is also permitted to read and write soft-core data and hard-core data. In the communication process, the host computer can use different channels to communicate with the FPGA. The receiving side is usually provided with an interface chip used to send and receive host messages and directly communicate with the FPGA. The subsystem composed of the interface chip is generally called a downloader (cable).

The host communicating with the FPGA, the method of communicating with the FPGA, and the FPGA interface chip provided by the embodiment of the present invention have low scalability mainly in the design of the interface software, and use a plurality of types of communication resources in parallel. The purpose is to solve the conventional problem of not being able to communicate with the FPGA interface chip.

According to an aspect of the present invention, a software interface module for defining a call interface exposed to a higher layer application so as to specify transmission data, the transmission data is acquired by the call interface, and the transmission data is obtained. A resource management module that manages the host interface chip cable object to be transmitted to the protocol packet module and allows at least two cable objects to be accessed in parallel at the same time, and the FPGA interface protocol and the cable object that receive the transmission data. Based on the channel protocol corresponding to, the protocol packet module that encapsulates the transmission data to acquire the data packet and transmits the data packet to the host channel interface module, and the protocol packet module that receives the data packet and transmits the data packet to the FPGA. A host that communicates with the FPGA is provided, including the host channel interface module, which is packaged and transmitted by channel based on a preset data format agreed with the interface chip.

According to another aspect of the present invention, the FPGA interface chip receives a data packet transmitted from the host, converts the data packet into a communication signal required for the FPGA, and directly communicates with the FPGA. Chips are provided.

According to another aspect of the invention, the software interface module of the host communicating with the FPGA defines a call interface that exposes the transmitted data to a higher layer application so that the transmitted data can be identified, and the resource of the host communicating with the FPGA. A step that allows the management module to manage the host interface chip cable object that acquires the transmission data by the calling interface and transmits the transmission data to the protocol packet module, and allows at least two cable objects to be accessed in parallel at the same time. Then, the protocol packet module receives the transmission data, encapsulates the transmission data and acquires a data packet based on the interface protocol of the FPGA and the channel protocol corresponding to the cable object, and obtains the data packet from the data packet by the FPGA. The step of transmitting to the host channel interface module of the host communicating with the host channel interface module receives the data packet, packages the data packet based on the preset data format agreed with the FPGA interface chip, and channels. Includes a step of transmitting to the FPGA interface chip via the above, and a step of receiving the data packet, converting the data packet into a communication signal required for the FPGA, and directly communicating with the FPGA. A method of communicating with the FPGA is provided.

Aspects of the present invention have the following beneficial effects.
Hosts and FPGA interface chips that communicate with FPGAs are provided to solve the problem of poor scalability and inability to communicate with FPGA interface chips using multiple types of communication resources in parallel in traditional interface software designs. .. The software interface module according to the present invention defines a call interface exposed to a higher layer application, and the resource management module manages a host interface chip cable object and permits at least two cable objects to be accessed in parallel at the same time. The cable object shares the call interface, the protocol packet module encapsulates the transmission data and acquires the data packet based on the FPGA interface protocol and the channel protocol corresponding to the cable object, and the host channel interface module , The data packet is packaged according to the preset data format agreed with the FPGA interface chip and transmitted by channel. That is, the host communicating with the FPGA of the present invention aims to access a plurality of interface resources in parallel by layering the interface software. Moreover, since the software interfaces used are the same, it is suitable for FPGA cluster resource management. Further, since the host communicating with the FPGA of the present invention has good portability, even if it is completely layered and ported to a different platform, only the host channel interface is different and there is no need to change the operation process. Improves scalability and maintainability. Also, by completely abstracting each operation of the FPGA communication interface, the upper layer code of the calling interface software does not have to consider details such as channels, receiver cables, and interface protocols, and identifies a specific FPGA. You only need to pay attention to the communication process of the interface of.

It is a structural schematic diagram of the host which communicates with FPGA which concerns on Example 1 of this invention. FIG. 5 is a schematic diagram in which a host communicating with the FPGA according to the first embodiment of the present invention is connected to the FPGA interface chip via Ethernet. FIG. 5 is a schematic diagram in which a host communicating with the FPGA according to the first embodiment of the present invention is connected to the FPGA interface chip via a wireless net. FIG. 5 is a schematic diagram in which a host communicating with the FPGA according to the first embodiment of the present invention is connected to the FPGA interface chip via a cable such as USB or LPT. FIG. 5 is a schematic diagram in which a host communicating with the FPGA according to the first embodiment of the present invention communicates with the FPGA interface chip via Ethernet. It is a schematic diagram of the preset data format which concerns on Example 1 of this invention. It is a schematic diagram that the FPGA interface chip which concerns on Example 2 of this invention is connected to FPGA. It is a software hierarchy structure diagram which concerns on Example 2 of this invention. FIG. 3 is a process diagram in which a host communicating with the FPGA according to the third embodiment of the present invention communicates with the FPGA. It is a process diagram of the method of communicating with FPGA which concerns on Example 3 of this invention.

Hereinafter, the present invention will be described in detail with reference to the drawings and examples.

In order to more clearly explain the object, technical solution, and advantage of the present invention, embodiments of the present invention will be described in more detail with reference to the drawings. Here, the specific examples described are merely for explaining the present invention, and do not limit the present invention.

Communication interface software developed by conventional FPGA manufacturers has certain restrictions. For example, since it is not possible to communicate with the FPGA without using the USB interface cable of the host, it is not possible to use multiple resources in parallel. As a result, only one user can use the resource at a time, which has a drawback such as low scalability. Some FPGA manufacturers allow users to locally virtualize a cable (actually one that accesses an FPGA on a circuit board via an Ethernet interface) and use it as a regular USB cable. I proposed the concept of virtual cable like Cable). However, in fact, because the software to realize this concept is independent of each other, when writing the communication process code of a particular on-chip interface of the FPGA, it is necessary to write it separately for different channels. This wastes development resources and increases maintenance costs. In view of the above circumstances, the present invention presents the following countermeasures.

Example 1
In this embodiment, by completely abstracting each operation of the FPGA communication interface, the upper layer code of the calling interface software does not have to consider details such as channels, receiver cables, and interface protocols, and is specific. We only need to focus on the communication process of a particular interface of the FPGA. This improves the scalability and maintainability of the software as a whole. As shown in FIG. 1, the host according to this embodiment communicates with the FPGA. The host may be a computer, a laptop computer, or the like, but this is not the case. The host includes a software interface module 101, a resource management module 102, a protocol packet module 103, and a host channel interface module 104.

The software interface module 101 is for defining a call interface exposed to a higher layer application. The call interface is for identifying transmission data.

The resource management module 102 manages the host interface chip cable object and allows at least two cable objects to be accessed in parallel at the same time. The cable object acquires transmission data by the calling interface and transmits the transmission data to the protocol packet module 103.

The protocol packet module 103 receives transmission data, encapsulates the transmission data to acquire a data packet based on the FPGA interface protocol and the channel protocol corresponding to the cable object, and transfers the data packet to the host channel interface module 104. Send.

The host channel interface module 104 receives the data packet, packages the data packet based on the preset data format agreed with the FPGA interface chip, and transmits it by channel.

In such an embodiment, the calling interface exposed to the user by the software interface module 101 can specify transmission data. The resource management module 102 determines the cable object that communicates with the FPGA interface chip. The cable object acquires transmission data by the calling interface and transmits the transmission data to the protocol packet module 103. The protocol packet module 103 encapsulates transmission data to acquire a data packet and transmits the data packet to the host channel interface module 104 based on the FPGA interface protocol and the channel protocol corresponding to the cable object.

Here, if the cable object is different, the corresponding channel is different. The cable object is via a cable to which a USB (Universal Serial Bus) cable is connected, a circuit board cable connected via an Ethernet port, and a PCIE (peripheral component interconnect express, high-speed serial computer expansion bus standard). Includes at least one of the PCIE card cables connected to and the cable connected to the printer parallel port. The channels corresponding to the cable object are USB, Ethernet port, PCIe, and printer parallel port, respectively. The host channel interface module 104 only performs processing related to the channel and packages the data. Then, when transmitting, the host channel interface module 104 needs to agree on a necessary data packet format with the FPGA interface chip and transmit the data packet based on the protocol rule used for the channel. The agreed data packet format is different for different FPGA interface chips.

In such an embodiment, the software interface module 101 includes an interface exposed to the user as an interface software library of the host communicating with the FPGA. The calling interface includes a basic software interface that communicates with the FPGA. As shown in FIGS. 2A, 2B, and 2C, the host communicating with the FPGA is connected to the FPGA interface chip via a cable such as Ethernet, USB, LPT, or Wi-Fi (wireless net). As you can see, different types of FPGA interface chips, such as USB, Ethernet, WIFI, etc., have almost the same communication process, the necessary processes are to initialize and then connect, read and write data to each other, The last to be released. As shown in FIG. 3, the host communicating with the FPGA is a process of communicating with the FPGA interface chip via Ethernet, specifically, the FPGA interface chip monitors a specific port and listens for a connection. Then, the host communicating with the FPGA initializes the socket connection based on the IP (Internet Protocol) address, and after the connection is successful, the host communicating with the FPGA reads data by the socket / After writing, the FPGA interface chip decapsulates the data in the socket and converts the data into the signal required for FPGA. After that, the host communicating with the FPGA releases, the socket connection is cut off, and the FPGA interface chip monitors the specific port again.

Therefore, in this embodiment, a fixed basic software interface is formed by integrating and abstracting the software interface module 101 so that the host communicating with the FPGA can communicate with a different type of FPGA interface chip. That is, the upper layer software can use the same basic software interface when communicating with each FPGA interface chip. Therefore, the basic software interface according to the present embodiment includes an initialization (Init) interface, a data write (Write) interface, a data read (Read) interface, and a release (Relase) interface. For example, when a host communicating with an FPGA communicates with an FPGA interface chip using Ethernet, initialization is a remote FPGA via a system socket using TCP (Transmission Control Protocol) / IP protocol. It tries to connect to the interface chip, and after the connection is successful, it sends a data packet, performs a specific initialization operation, and the FPGA interface chip returns the signal corresponding to the data packet to the host. Is to break the connection, write is to write binary data to the socket, and read is to read the data from the socket. When a host communicating with the FPGA uses USB to communicate with the FPGA interface chip, initialization means calling the system interface, applying for a USB device, and performing an initialization operation, and release means releasing resources. It is released to the system, and read / write is to read and write data using the system interface. Of course, all the data transmitted between the host communicating with the FPGA and the FPGA interface chip is packaged based on the agreed preset data format.

In such an embodiment, it is necessary to define a request object in the process of transmitting transmission data to the basic software interface. Since the request object is a structure, the structure of the transmission data includes the request object. The request object contains at least one of a predefined operation code, data, object, callback function, and extended void (untyped) pointer, and is a basic software interface in a unified format with higher layer code. Is allowed access to.

In such an embodiment, the resource management module 102 manages all available cable objects. The cable object may be an actual one such as a cable connected to a USB cable, and may be an interface chip of a circuit board connected via an Ethernet port or an interface chip of a PCIE card connected via PCIE. It may be a virtual one such as. The resource management module 102 specifically manages the specific number of each type of cable object and the occupied situation, and allows at least two cable objects to be accessed in parallel at the same time. Of course, the at least two cable objects do not interfere. In this embodiment, in order to easily manage each cable object, each cable object is assigned a unique MAC address and identifier so as to be easily distinguished. As a result, the resource management module 102 can uniquely identify the cable object.

In such an embodiment, the identifier assigned to the cable object is used to define the type attribute of the cable object. The identifier is custom set by the host communicating with the FPGA. For example, if the cable object is a USB cable, the identifier corresponding to the cable object is USB, and if the cable object is an Ethernet virtual cable, the identifier corresponding to the cable object is Ethernet. In such an embodiment, the identifier may be a custom number or the like, provided the cable type is specified.

Here, the only MAC address is assigned to the cable as the only resource identifier, regardless of whether the cable itself has a real MAC. Specifically, when the cable object is a USB cable, the MAC address is a serial number recorded in the EEPROM of the USB, and when the cable object is an Ethernet virtual cable, the MAC address is an Ethernet virtual cable. IP address or FPGA interface chip When the cable object is a cable of a PCIE board, the MAC address is an address of the PCIE bus or a serial number in the interface chip on the PCIE bus, and the cable is If the object is a printer parallel port, the MAC address is the parallel port address.

Here, the user may select any cable object connected to the FPGA interface chip. Specifically, the resource management module 102 scans an accessible table object list, creates a list, and then provides the list to the user.

In such an embodiment, the calling interface includes a probe (Probe) interface for acquiring an accessible cable object, and the probe interface can detect the usage status of the currently accessible cable object. In order to identify the access cable object that the upper layer application communicates with the FPGA, the resource management module 102 creates the list and then returns the list to the upper layer application by the probe interface.

In such an embodiment, the protocol packet module 103 encapsulates the received transmission data, primarily based on the FPGA's interface and channel protocols. Here, the hardcore and soft core of FPGA are usually JTAG (Joint Test Action Group, Joint Test Action Group), I2C (Inter-Integrated Circuit, 2-wire serial bus), SPI (Serial Peripheral Interface), and serial peripheral interface. , And interfaces such as parallel interfaces. These interface protocols may require special processing at the application layer based on the protocol's relevant information.

For example, for the JTAG protocol, if there is a JTAG chain, in fact, there are many devices in this chain, some of which may or may not be FPGAs. As described above, the JTAG protocol software may perform certain processing as necessary. For example, when writing a JTAG command, it is necessary to write a necessary bypass command first according to the chain situation, and when writing JTAG data, it is necessary to add 1 or the like appropriately. When the transmission data is transmitted, the protocol packet module 103 reencapsulates the transmission data based on the protocol used for the channel. For example, when using a channel corresponding to Ethernet, the transmission data is re-encapsulated based on the TCP / IP protocol to acquire a data packet to be transmitted to the host channel interface module 104. Then, by analyzing the TCP / IP data with the FPGA interface information, the content to be extracted is the agreed preset data packet format.

In such an embodiment, it is necessary to agree on data in a specific format in order to communicate between the host channel interface module 104 and the FPGA interface chip. To facilitate the FPGA interface chip to receive the data packet and parse the data packet, the agreed preset data format is related to the FPGA interface chip implementation scheme. Therefore, the host channel interface module 104 agrees with the FPGA interface chip on the preset data format based on the mounting method of the FPGA interface chip. In the communication of digital signals between electronic components, a specific format is agreed for binary data, and the binary data is transmitted in that format.

Here, the FPGA interface chip includes a USB interface chip of FT2232H. The preset data format includes a packet header and data. The packet header is composed of a command code and a data length. As shown in FIG. 4, the 32-bit command code determines the operations that the FPGA interface chip needs to perform, such as JTAG protocol state transitions, attribute settings, and JTAG data read / write. The 32-bit data length indicates the amount of data behind.

In such an embodiment, the FPGA interface chip is realized by combining an MCU (Microcontroller Unit) with an Ethernet port chip. Since the FPGA interface chip is programmable, it is possible to agree on the content format of the net data packet received by the FPGA interface chip. Both can then decapsulate the data packet based on the agreed content.

The host communicating with the FPGA provided by this embodiment includes a layered interface software design mode, and the FPGA communication is performed by the software interface module 101, the resource management module 102, the protocol packet module 103, and the host channel interface module 104. Each operation of the interface is completely abstracted. As a result, the higher layer code of the calling interface software does not have to consider details such as channels, receiver cables, and interface protocols, and only needs to focus on the communication process of a particular interface of a particular FPGA. This improves the scalability and maintainability of the software as a whole.

Example 2
As shown in FIG. 5, the FPGA interface chip provided by this embodiment includes an FPGA side channel interface module. The FPGA side channel interface module receives the data packet transmitted from the host communicating with the FPGA. Then, the FPGA interface chip analyzes the data packet based on the preset data format agreed with the host channel interface module 104 of the host communicating with the FPGA, converts the data packet into a communication signal required for the FPGA, and converts the data packet into a communication signal required for the FPGA. Communicate directly with.

Here, the analysis of the data by the FPGA side channel interface module is a chip level operation, that is, the data is read directly from the channel, the data is analyzed, and then the communication signals such as JTAG and SPI required for the FPGA are directly processed. Converts and communicates directly with the FPGA.

For example, when the interface chip is a USB cable, the data of the host communicating with the FPGA is acquired by the USB cable, converted into a protocol signal such as JTAG, and communicated with the FPGA. Here, the FPGA interface chip includes a USB interface chip of FT2232H. The preset data format includes a packet header and data. The packet header is composed of a command code and a data length. The command code determines the operations that the FPGA interface chip needs to perform, such as JTAG protocol state transitions, attribute settings, and reading / writing of JTAG data. The data length indicates the amount of data behind.

According to this embodiment, an interface design for communicating with the FPGA is provided. Interface software is planned by layering. As shown in FIG. 6, the interface design includes a software interface, resource management, cable object, protocol packet, host channel interface, and FPGA side channel interface.

The software interface defines the interface exposed to the upper layer application, and includes the interface for releasing and applying for resources, the probe interface for acquiring the resource list, the read / write interface for each protocol directly related to FPGA, the initialization interface, and so on. .. By defining these basic interfaces, the interface of the host that communicates with the FPGA is abstracted to the operation unit (operator). Each type of operator has a corresponding function. These operators only read / write data directly, or convert, initialize and release interfaces, and collect resource status. Different operators offer custom features depending on their unique characteristics, but higher layer features only assume these basic interfaces.

Resource management is to manage resources, manage cable resources, and allow a plurality of communication resources to be accessed in parallel at the same time. Resource management manages all available cable resources such as the number of resources of each type, the situation in which the resources are occupied, and so on. A mechanism for releasing and applying for resources is established at the resource management layer. When the user applies for an object, the handle object is acquired and an operation is performed using these handle objects. Resource management automatically scans for available resources and provides the list to the user. In the probe function interface, what is returned is a list of related resources. After selecting, the user can access the cable resource corresponding to the list in parallel. Each cable resource is uniquely distinguished by MAC, type, etc. For the process, the resource management object is just one example.

The cable object may be an actual one such as a cable connected to a USB cable, and may be an interface chip of a circuit board connected via an Ethernet port or an interface chip of a PCIE card connected via PCIE. It may be a virtual one such as. At the software design level, it is necessary to abstract these cable objects into one cable object. The cable object aims to integrate each type of operator supported by the current type of cable to provide a unified handle software interface. As a result, the upper layer can read / write data only by transmitting the operation code. The cable object needs to provide a basic interface such as an initialization interface and a release interface. These interface methods are to call the associated operator to fill in and release the resource.

The protocol packet layer creates data related to protocols such as JTAG and SPI used by FPGA in a data packet based on a specific rule, and transmits the data packet to an operator object in a lower layer in order to process the data packet. Lower layer operators handle only channel issues, and FPGA-related protocol operations are accomplished by implementing some protocol operators and packaging operators located in lower layers. The process at the layer where the protocol operator is located is the process of dividing or reorganizing the data packet related to the protocol transmitted from the user and calling the basic read / write interface. Protocol operators require lower layer operators, and basically all lower layer operators share operators for the same protocol.

The host channel interface layer mainly realizes a lower layer operator that calls the drive interface of the system, and re-encapsulates and transmits the data transmitted from the upper layer based on the channel request. Different channels require different encoding methods. This is also related to the FPGA side interface. After the data is transmitted based on the channel request, it is received by the FPGA side channel interface. Different receivers have different data packet requests, but higher layer software may agree on each receiving platform without considering specific packet conditions. Then, based on these agreements, an independent operator is planned.

The FPGA side channel interface is one in which an interface chip is provided on the FPGA side. If the FPGA side channel interface is, for example, a USB cable, it is a cable having an interface chip. The cable acquires the data of the host communicating with the FPGA via the USB cable, converts it into a protocol signal such as JTAG, and communicates with the FPGA. If the interface chip is different, the required processing is also different, so the cooperation of the host side that communicates with the FPGA is required. However, in most cases this is just a difference in how the encapsulated data is combined. Since the receiving side can select the interface hardware more flexibly, the host side communicating with the FPGA encapsulates the data at the request of the receiving side hardware itself. In this case, the interface hardware chip needs to support data decapsulation, convert the communication signals required for the FPGA, and communicate directly with the FPGA.

In this embodiment, the layered interface software design mode has the following advantages. Higher layer applications do not have to consider special processing details such as the interface chip, the FPGA's own interface protocol, and so on. This improves scalability and maintainability. It has been decided that interface resources will be exposed to higher layer applications regardless of the channel. In addition, interface resources that do not interfere are accessed in parallel, so they are used as server processes. If interconnection structures such as Ethernet can be introduced, specific distribution characteristics can also be achieved. Higher layer software is suitable for FPGA cluster resources because it can utilize the same software interface when communicating with each FPGA resource in the network. Further, since the host communicating with the FPGA of the present invention has good portability, even if it is completely layered and ported to a different platform, only the host channel interface is different. Therefore, by replacing each operator at this layer, Code migration is realized and there is no need to change the operation process of the upper layer. Furthermore, the interface software can be applied to various environments and can communicate with the FPGA by wireless, wired or the like.

Example 3
This embodiment describes a communication process with the FPGA of the host communicating with the FPGA. As shown in FIG. 7, in S701, the host side communicating with the FPGA identifies a cable resource communicating with the FPGA based on the probe interface.

In this embodiment, the probe interface mainly detects the total number of accessible resources of the current type, creates a list, and returns it to the upper layer software. As a result, the user determines which cable resource is used to communicate with the FPA G. Here, in order to distinguish each cable resource, a MAC address and an identifier are assigned to the cable resource. When it is decided to communicate with the FPGA using the cable connected to the USB cable and the cable simulated by Ethernet, in S702, the host side communicating with the FPGA is the FPGA interface chip of the FPGA via the initialization interface. Connected to.

When using Ethernet, initialization means connecting to the receiving side remotely using the TCP / IP protocol and the socket of the system, and when using USB, initialization means calling the system interface. Applying for a USB device and performing the initialization operation.

In S703, when writing binary data using the write data interface, the host side communicating with the FPGA creates a data packet by combining data related to the interface protocol used for the FPGA based on a specific rule.

When using Ethernet, write binary data to the socket, and when using USB, write binary data using the system interface. After that, data packets are created by combining binary data based on specific rules using data related to protocols such as JTAG and SPI.

In S704, the host side communicating with the FPGA creates a data packet by combining them based on the preset data format, and transmits the data packet to the FPGA interface chip via the channel corresponding to the cable resource.

In this embodiment, the FPA G interface chip includes a USB interface chip of FT2232H. The preset data format includes a packet header and data. The packet header consists of a command code and data length. The command code determines the operations that the FPGA interface chip needs to perform, such as JTAG protocol state transitions, attribute settings, and reading / writing of JTAG data. The data length indicates the amount of data behind. The FMAG interface chip is realized by combining the MCU with the Ethernet port chip. Since the FPGA interface chip is programmable, it is possible to agree on the content format of the net data packet received by the FPGA interface chip. When Ethernet is used, when the data packet is transmitted, the TCP / IP protocol used reencapsulates the data packet and sends it to the Ethernet port chip.

In S705, the FPGA interface chip reads a data packet from the channel, analyzes it, converts it into a communication signal required for the FPGA, and directly communicates with the FPGA.

The FPA G interface chip analyzes data packets based on a preset data format. The FPGA interface chip also packages the data based on the preset data format when transmitting the data to the host side communicating with the FPGA.

In S706, the host side communicating with the FPGA cuts off the connection with the FPGA interface chip by releasing the interface.

The embodiments of the present invention provide a method of communicating with an FPGA. As shown in FIG. 8, the method is realized by the following steps.

In S11, the software interface module 101 of the host that communicates with the FPGA defines a call interface that is exposed to higher layer applications to identify transmission data.

In S12, the resource management module 102 of the host communicating with the FPGA manages a host interface chip cable object that acquires transmission data by the call interface and transmits the transmission data to the protocol packet module 103, and simultaneously to at least two cable objects. Allow access in parallel.

In S13, the protocol packet module 103 receives the transmission data, encapsulates the transmission data to acquire the data packet, and communicates the data packet with the FPGA based on the interface protocol of the FPGA and the channel protocol corresponding to the cable object. Send to the host channel interface module 104 of the host.

In S14, the host channel interface module 104 receives the data packet, packages the data packet based on the preset data format agreed with the FPGA interface chip, and transmits it to the FPGA interface chip via the channel.

In S15, the FPGA interface chip receives the data packet, converts the data packet into a communication signal required for the FPGA, and directly communicates with the FPGA.

Further, the method of communicating with the FPGA after the FPGA interface chip receives the data packet further includes the following steps. The host communicating with the FPGA cuts off the connection with the FPGA interface chip by releasing the interface.

In the embodiments of the present invention, the description of the method of communicating with the FPGA and the beneficial effects of the method are the same as the description and beneficial effects of the host communicating with the FPGA according to the above-described embodiment. Omit. It should be noted that "includes", "has", or other variants are intended to include non-exclusively, so a process, method, article, or device that includes a set of elements will only include those elements. It may contain other elements not listed, or elements specific to a process, method, article, or device.

The above-mentioned numbers of the examples of the present invention are for the purpose of explanation only and do not indicate the superiority or inferiority of the examples.

Through the description of the above embodiment, those skilled in the art can clearly understand that the method according to the above embodiment is realized by the software and the required hardware platform. Of course, it can be realized by hardware, but in most cases, the former is preferable. Based on this understanding, the special technical features of the invention, or features that contribute to the prior art, are expressed in the form of software products. Computer software products are stored on storage media (ROM / RAM, magnetic disks, optical disks) and some for causing devices (mobile phones, computers, servers, air conditioners, network devices, etc.) to perform the methods according to each embodiment. Includes instructions for.

The above-mentioned contents explain the embodiment of the present invention in more detail based on the specific embodiment, and it cannot be considered that the specific implementation of the present invention is limited to these explanations. Those skilled in the art may make minor improvements and modifications as long as they do not deviate from the spirit of the present invention. These improvements and modifications are also considered to be the scope of protection of the present invention.

This application is the priority of a Chinese patent application submitted to the China Bureau of Interest on June 28, 2019, with an application number of 201910580649.9 and the title of the invention is "a host and FPGA interface chip that communicates with FPGA". And incorporates all the contents of the previous application.

Claims (20)

A host that communicates with the FPGA
A software interface module for defining call interfaces that are exposed to higher layer applications to identify transmission data, and
A resource management module that manages a host interface chip cable object that acquires the transmission data by the call interface and transmits the transmission data to the protocol packet module, and allows access to at least two cable objects in parallel at the same time.
The protocol packet that receives the transmission data, encapsulates the transmission data and acquires a data packet based on the FPGA interface protocol and the channel protocol corresponding to the cable object, and transmits the data packet to the host channel interface module. Module and
A host that communicates with an FPGA, comprising: .. A host that communicates with the FPGA according to claim 1.
A host that communicates with an FPGA, further comprising an interface release module that blocks the connection between the host and the FPGA interface chip after the host channel interface module has transmitted the data packet. A host that communicates with the FPGA according to claim 1.
The call interface is a host that communicates with the FPGA, including an initialization interface, a data write interface, a data read interface, and a release interface, including a basic software interface that communicates with the FPGA. A host that communicates with the FPGA according to claim 1.
The cable object includes at least one of a cable to which a USB cable is connected, a circuit board cable connected via an Ethernet port, a PCIe card cable connected via PCIE, and a printer parallel port. A host that communicates with the FPGA. A host that communicates with the FPGA according to claim 4.
The cable object is a host that communicates with an FPGA, characterized in that it is assigned a unique MAC address and type indicator identifier to distinguish it. A host that communicates with the FPGA according to claim 5.
When the cable object is a USB cable, the MAC address is a serial number recorded in the EEPROM of the USB.
When the cable object is an Ethernet virtual cable, the MAC address is the IP address of the Ethernet virtual cable or the FPGA interface chip real MAC address.
When the cable object is a PCIe board cable, the MAC address is the address of the PCIe bus or the serial number of the interface chip of the PCIe bus.
When the cable object is a printer parallel port, the MAC address is a host that communicates with the FPGA, characterized in that it is a parallel port address. A host that communicates with the FPGA according to claim 4.
The resource management module is a host that communicates with an FPGA, characterized in that it scans and creates a list of accessible cable objects. A host that communicates with the FPGA according to claim 7.
The call interface further includes a probe interface to obtain an accessible cable object.
The resource management module scans the access cable object to create a list so that the upper layer application identifies the access cable object that communicates with the FPGA, and then displays the list via the probe interface to the upper layer. A host that communicates with an FPGA, characterized by replying to an application. A host that communicates with the FPGA according to any one of claims 1 to 8.
The host channel interface module is a host that communicates with the FPGA, which is characterized by agreeing the preset data format with the FPGA interface chip based on the mounting method of the FPGA interface chip. A host that communicates with the FPGA according to claim 9.
When the FPGA interface chip includes a USB interface chip of FT2232H, the preset data format is a host that communicates with the FPGA, comprising a packet header composed of a command code and a data length, and data. It ’s a communication system ,
A host that communicates with the FPGA according to any one of claims 1 to 10.
It comprises an FPGA interface chip that receives a data packet transmitted from the host, converts the data packet into a communication signal required for the FPGA, and directly communicates with the FPGA.
A communication system characterized by that. The communication system according to claim 11.
The FPGA interface chip is a communication system including Ethernet, USB, LTP, and a wireless net. The communication system according to claim 12.
When the FPGA interface chip includes a USB interface chip of FT2232H, the preset data format is a communication system including a packet header composed of a command code and a data length, and data. The communication system according to claim 11.
The FPGA interface chip is a communication system characterized in that it is connected to a host that communicates with the FPGA via an initialization interface. The communication system according to claim 11.
The interface protocol supported by the FPGA is a communication system including JTAG, I2C, SPI, and a parallel interface. The communication system according to claim 11.
The FPGA interface chip is a communication system including a channel interface module that receives a data packet transmitted from a host communicating with the FPGA according to any one of claims 1 to 9. It ’s a way to communicate with FPGA.
A step in which the software interface module of the host communicating with the FPGA defines a call interface that is exposed to higher layer applications so that the transmitted data can be identified.
The resource management module of the host communicating with the FPGA manages a host interface chip cable object that acquires the transmission data by the call interface and transmits the transmission data to the protocol packet module, and is parallel to at least two cable objects at the same time. And the steps to allow access to
The protocol packet module receives the transmission data, encapsulates the transmission data and acquires a data packet based on the interface protocol of the FPGA and the channel protocol corresponding to the cable object, and communicates the data packet with the FPGA. And the steps to send to the host channel interface module of the host
A step in which the host channel interface module receives the data packet, packages the data packet based on a preset data format agreed with the FPGA interface chip, and transmits the data packet to the FPGA interface chip via the channel.
A method of communicating with an FPGA, wherein the FPGA interface chip includes a step of receiving the data packet, converting the data packet into a communication signal required for the FPGA, and directly communicating with the FPGA. The method of communicating with the FPGA according to claim 17.
After the FPGA interface chip receives the data packet,
A method of communicating with an FPGA, wherein the host communicating with the FPGA further comprises a step of disconnecting the connection with the FPGA interface chip by releasing the interface. A method of communicating with the FPGA according to claim 17 or 18.
The step in which the resource management module manages the host interface chip cable object is
A method of communicating with an FPGA, wherein the resource management module comprises a step of scanning a cable object to which access is granted and creating a list. The method of communicating with the FPGA according to claim 19.
The call interface further includes a probe interface to obtain an accessible cable object.
The step in which the resource management module manages the host interface chip cable object is
The resource management module scans the access cable object to create a list so that the higher layer application identifies the access cable object that communicates with the FPGA, and then the list is displayed on the upper layer via the probe interface. A method of communicating with an FPGA, characterized by further including a step of replying to the application.

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