JP7040162B2 - Semiconductor devices and their manufacturing methods - Google Patents

Description

The present invention relates to a structure and a manufacturing method of a semiconductor device that operates by applying a high voltage in the in-plane direction of a semiconductor substrate.

In power MOSFETs, which are a type of power semiconductor device, vertical elements that flow current (large current) in the thickness direction of the semiconductor substrate and horizontal elements that flow current in the in-plane direction of the semiconductor substrate when turned on are known. Has been done. Of these, LDMOS (Laterally Diffused MOSFET), which is one of the horizontal elements, is particularly preferably used because it has excellent high frequency characteristics.

A general LDMOS structure is described in, for example, Patent Document 1. A cross-sectional view of this LDMOS (semiconductor device 200) is shown in FIG. Here, only the structure near the surface is described. Here, the semiconductor substrate 80 provided with the n-type layer 81 is used, and the p-type layer 82 serving as an island-shaped base region is formed on a part of the surface thereof. In the p-type layer 82, a high impurity concentration p ⁺ layer 83 and a high impurity concentration n ⁺ layer 84 connected to the source electrode 91 are formed. On the upper side of the semiconductor substrate 80, a gate electrode 92 is provided via a thin gate oxide film 90 in a region including the n ⁺ layer 84 and the n-type layer 81 exposed on the surface. The drain electrode 93 is connected to the surface of the semiconductor substrate 80 at a position separated from the gate electrode 92 via an n ⁺ layer 85 having a high impurity concentration. Since the carrier concentration of the n-type layer 81 is sufficiently lower than that of the p-type layer 82, when the potential of the source electrode 91 (source potential) is the ground potential and the potential of the drain electrode 93 (drain potential) is a positive high potential. The depleted layer extending from the interface between the n-type layer 81 and the p-type layer 82 spreads mainly on the n-type layer 81 side.

In this semiconductor device 200, when it is turned on (when a voltage that turns on is applied to the gate electrode 92), a current is applied from the n ⁺ layer 84 to the n-type layer 81 via a channel formed directly under the gate electrode 92. Then, a current flows in the horizontal direction in the n-type layer 81, so that a current flows between the source electrode 91 and the drain electrode 93.

On the other hand, when off, no current flows between the n ⁺ layer 84 and the n-type layer 81, the depleted layer spreads in the n-type layer 81, and the source electrode 91, which is the ground potential, has a low potential close to the ground potential. Since the potential difference between the gate electrode 92 and the drain electrode 93 having a high potential is large, the maximum electric field strength inside the depleted layer is high. That is, in the n-type layer 91, a current flows in the in-plane direction (left-right direction in FIG. 5) when it is on, and no current flows when it is off, forming a depletion layer, and the electric field strength inside the depletion layer is formed. Will be higher.

When this maximum electric field strength exceeds the breakdown electric field strength, a current flows between the source electrode 91 and the drain electrode 93 even though it is originally off. Therefore, the withstand voltage of the semiconductor device 200 is such that the maximum electric field strength is the breakdown electric field strength. It becomes the drain voltage at the time of. In order to reduce the maximum electric field strength and increase the withstand voltage, it is preferable to widen the distance between the n ⁺ layer 85 and the p-type layer 82 or the like in FIG. On the other hand, since the space between these layers is the path of the current at the time of turning on as described above, it is preferable that the space between them is narrow in order to reduce the resistance at the time of turning on and allow a large current to flow. .. In consideration of these points, a thick oxide film (field oxide film 94) is provided between the p-type layer 82 and the n ⁺ layer 85 in order to reduce the resistance at the time of turning on and secure the withstand voltage. .. Further, the maximum electric field strength can be lowered by providing a region where the field oxide film 94 and the gate electrode 92 overlap.

The field oxide film 94 is formed to be significantly thicker than the gate oxide film 90. On the other hand, in order to secure the withstand voltage as described above, the length in the lateral direction in FIG. 5 becomes long, so that the field oxide film 94 becomes thick and long, and the field oxide film is formed by a forming method capable of realizing such a shape. 94 is formed. As such a forming method, Si is locally used by using a silicon nitride film as a mask, which is also used when forming an oxide film for element separation of a CMOS integrated circuit in which a thick oxide film is also used. There is a LOCOS (Local Oxidation of Silicon) method for oxidizing the surface. Although shown in a simplified manner in the figure, in reality, the thickness of the field oxide film 94 by the LOCOS method is not uniform, and the shape protrudes upward from the surface of the n-type layer 81.

On the other hand, the LDMOS as described above is often used as a mixed mounting device formed on the same semiconductor substrate as the CMOS integrated circuit. In this case, since the oxide film for element separation in the CMOS integrated circuit and the above-mentioned field oxide film 94 in LDMOS can be formed at the same time, the manufacturing process can be simplified, thereby reducing the cost of the consolidated device. be able to.

Japanese Unexamined Patent Publication No. 2011-129701

With the recent miniaturization of CMOS integrated circuits for higher performance, the oxide film for device separation has also been miniaturized, and its width has been miniaturized. Along with this, the oxide film for separating the elements is not based on the LOCOS method as described above, but is STI (Shallow Trench Isolation). In STI, after forming a fine groove corresponding to the shape of the oxide film for element separation on the surface of the semiconductor substrate, an oxide film is formed on the entire surface, this groove is embedded, and this groove is removed by removing the oxide film on the surface. The oxide film (embedded insulating layer) remaining only inside is used as an oxide film for element separation. On the other hand, it has been difficult to form an oxide film for element separation having the same shape and dimensions by the LOCOS method.

As described above, when manufacturing the mixed mounting device of the semiconductor device 200 and the CMOS integrated circuit of FIG. 5, it is preferable to form the above-mentioned field oxide film 94 and the element separation oxide film at the same time. Here, while the width of the oxide film for element separation in the CMOS integrated circuit is made finer as described above, the width of the field oxide film 94 is widened in order to secure the withstand voltage of LDMOS. do not have. Therefore, the difference between the width of the field oxide film 94 and the width of the element separation oxide film becomes large.

Here, the manufacturing process for forming the STI as described above is performed under the conditions optimized according to the dimensions of the STI. Therefore, it was difficult to form the field oxide film 94 having a width significantly wider than that of STI at the same time as STI. That is, it was difficult to form the field oxide film 94 and the element separation oxide film in the same process. Therefore, a structure that can obtain a high withstand voltage by using an embedded insulating layer having a narrow width is desired.

The present invention has been made in view of such problems, and an object of the present invention is to provide an invention for solving the above problems.

The present invention has the following configurations in order to solve the above problems.
The semiconductor device of the present invention is a semiconductor device using a semiconductor substrate in which a semiconductor element is formed so that a potential difference is generated in the in-plane direction on the surface side and a current flows in the in-plane direction, and the first conductive type. A first semiconductor layer in which the current flows in the in-plane direction is provided on the surface side of the semiconductor substrate, and in the first semiconductor layer, the surface side without penetrating the first semiconductor layer. A plurality of grooves from which the first semiconductor layer is dug are formed along the direction in which the potential difference is generated, and the width of the groove is in the range of 3 to 10 μm along the direction in which the potential difference is generated. The spacing between the two is in the range of 0.3 to 0.8 μm, the grooves are embedded in an insulating layer, and a second conductive type opposite to the first conductive type is formed on the surface between the adjacent grooves. It is characterized in that a surface conductive layer having a surface conductive layer is formed.
In the semiconductor device of the present invention, a second semiconductor layer having a second conductive type opposite to the first conductive type is locally formed on the surface of the first semiconductor layer, and the first semiconductor is formed. The main electrode is connected to a position on the surface of the layer separated from the second semiconductor layer, and the plurality of grooves are formed between the main electrode and the second semiconductor layer in a plan view. And.
In the semiconductor device of the present invention, the semiconductor element is a MOSFET, and the main electrode is a drain electrode in the MOSFET.
The semiconductor device of the present invention is characterized in that an electrode is connected to the surface conductive layer.
The method for manufacturing a semiconductor device of the present invention is the method for manufacturing the semiconductor device, which is a groove forming step for forming the groove in the first semiconductor layer and a groove forming step on the surface of the semiconductor substrate so as to embed the groove. It is characterized by comprising an insulating layer forming step for forming the insulating layer and an insulating layer removing step for removing the insulating layer on the surface other than the inside of the groove.
The semiconductor device of the present invention is characterized in that, in the insulating layer forming step, a thermal oxide film is first formed on the inner surface of the groove by thermal oxidation, and then the insulating layer is formed by a CVD method.

Since the present invention is configured as described above, a high withstand voltage can be obtained by using an embedded insulating layer having a narrow width.

It is sectional drawing which shows the structure of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows typically the electric field distribution in the semiconductor substrate in the conventional semiconductor device. It is a figure which shows typically the electric field distribution in the semiconductor substrate in the semiconductor device which concerns on embodiment of this invention. It is a process sectional view which shows the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Hereinafter, the semiconductor device according to the embodiment of the present invention will be described. During operation of this semiconductor device, a high potential difference is generated in the in-plane direction of the semiconductor substrate, or a large current flows in the in-plane direction. Specifically, this semiconductor device 1 is a MOSFET in which the on / off of the current between the source electrode and the drain electrode is controlled by the potential of the gate electrode, and in particular, all of the source electrode, the drain electrode, and the gate electrode. Is an LDMOS provided on the surface side of the semiconductor substrate.

FIG. 1 is a cross-sectional view showing the structure of the semiconductor device 1. In the semiconductor device 1, an LDMOS is configured by using a semiconductor substrate 10 made of Si, and FIG. 1 shows a portion corresponding to the LDMOS. Actually, a CMOS integrated circuit is also formed on the semiconductor substrate 10 in a region other than this portion.

An n-type layer (first semiconductor layer) 11 having a low concentration of n-type is provided on the surface side of the semiconductor substrate 10 by epitaxial growth. Actually, another layer is provided below the n-type layer 11, but since the other layer is irrelevant to the present invention, the description thereof is omitted here. The n-type layer 11 is the same as the n-type layer 81 in the semiconductor device 200. That is, a current flows through the n-type layer 11 in the in-plane direction (left-right direction in FIG. 1) when it is on, and no current flows when it is off, forming a depletion layer, and the electric field strength inside the depletion layer is formed. Will be higher.

Further, the p-type layer (base region: second semiconductor layer) 12, p ⁺ layer 13, n ⁺ layers 14, 15, gate oxide film 20, source electrode (main electrode) 21, gate electrode 22, drain electrode (main). The electrode) 23 is the same as the p-type layer 82, p ⁺ layer 83, n ⁺ layer 84, 85, gate oxide film 90, source electrode 91, gate electrode 92, and drain electrode 93 in the semiconductor device 200, respectively. .. That is, LDMOS is similarly formed by these components.

However, here, instead of the wide field oxide film 94, a narrow embedded oxide layer (embedded insulating layer) 25 is stretched in a direction perpendicular to the paper surface to provide a plurality of rows (three rows in the figure). .. The embedded oxide layer 25 is formed by embedding a groove formed at a depth that does not penetrate the n-type layer 11 with SiO ₂ which is an insulating layer. Further, a p ⁺ layer (surface conductive layer) 16 is formed on the surface of the semiconductor substrate 10 between the adjacent embedded oxide layers 25.

In FIG. 1, the region in which the p ⁺ layers 16 sandwiched between the three embedded oxide layers 25 and the adjacent embedded oxide layers 25 are arranged in the horizontal direction corresponds to the field oxide film 94 in FIG. 5, and as will be described later. Therefore, the withstand voltage between the source electrode 21 and the drain electrode 23 at the time of off can be increased. On the other hand, the width of each embedded oxide layer 25 can be set to be significantly smaller than that of the field oxide film 94. Specifically, the width of the embedded oxide layer 25 is about 3 to 10 μm, and the interval (width of p ⁺ layer 16) is about 0.3 to 0.8 μm. Therefore, the STI of the CMOS integrated circuit formed at the same time and the embedded oxide layer 25 can be formed at the same time.

Next, the point that a high withstand voltage can be obtained in this semiconductor device 1 will be described. First, for comparison, in the semiconductor device 200 of FIG. 5, the distribution of the electric field strength E in the n-type layer 91 when the voltage (drain voltage Vd) of the drain electrode 93 is raised in three stages when off is schematically shown. Is shown in FIG. Here, the drain voltage Vd corresponds to the integral value of E in this graph, and it is shown that the electric field generated by the application of Vd is thus generated in the n-type layer 91.

In FIG. 2, the electric field E is shown as a calculated value of the one-dimensional distribution as the one at the lateral position x in the structure of the semiconductor device 200 shown at the uppermost portion, and the horizontal axis x in the distribution of the electric field strength E is the maximum. Corresponds to the position in the semiconductor device 200 shown at the top. Here, the distribution of the electric field strength E from the vicinity of the interface between the p-type layer 92 and the n-type layer 91 to the drain side end (n ⁺ layer 85 side) on the source side in the horizontal direction is shown. The place where the electric field strength E is not zero is the place where the depletion layer is formed. Further, in the graphs (a), (b) and (c) of the distribution of the electric field strength E shown here, the lower part is shown. Vd is increased toward the side.

As described above, as Vd is increased, the width of the depletion layer widens especially on the n-type layer 91 side (right side of the pn junction), and the electric field strength E takes a maximum value at the pn junction interface. At this time, the electric field strength distribution changes in a similar figure proportional to Vd, and the rate of change dE / dx (slope) of the electric field strength E in the n-type layer 91 is constant regardless of x and Vd. Therefore, ideally, Vd when the electric field strength E at the pn junction interface becomes the breakdown electric field strength (about 3 × 105 ^V / cm in the case of Si) is the withstand voltage of the semiconductor device 200.

On the other hand, FIG. 3 shows the result of calculating the distribution of the electric field strength E when Vd is gradually increased in the above-mentioned semiconductor device 1 as in FIG. 2. Here, the point that the depletion layer expands as Vd rises is the same as in the case of FIG. 2, but the distribution shape of the electric field strength E is greatly influenced by the p ⁺ layer 16. First, when the Vd is the smallest and the depletion layer does not reach the leftmost p ⁺ layer 16 (a), the distribution is the same as in FIG. 2 (a).

Next, (b) is a case where the depletion layer spreads because Vd becomes larger than this, and the depletion layer is formed beyond the p ⁺ layer 16 on the left side. Here, in the figure, the position of the left end of the left p ⁺ layer 16 is A, and the position of the right end is B. When the depletion layer reaches the p ⁺ layer 16, a large number of holes are injected from the p ⁺ layer 16 into the depletion layer (or due to the influence of negative ions formed on the p ⁺ layer 16 side). , The electric field strength E is greatly reduced in the portion where x is larger than A. Therefore, the electric field strength E greatly decreases at A as shown in (b). On the other hand, assuming that Vd in this case is the same as in FIG. 2B, for example, x is smaller than A because Vd is the integrated value of the electric field strength E in this graph (more than A in FIG. 3). The electric field strength E in the region (on the left side) becomes larger by the decrease of the electric field strength E on the right side than A. Alternatively, the holes injected from the p ⁺ layer 16 as described above act so that x lowers the electric field strength E in the region on the right side of A and increases the electric field strength E in the region on the left side of A. It acts to make you. Therefore, in the case of FIG. 2, dE / dx was constant in the n-type layer 91, whereas in FIG. 3B, E is greatly reduced at the point where x is larger than A. By (| dE / dx | becomes larger), | dE / dx | becomes smaller at the point where x is smaller than A.

(C) is a case where the depletion layer exceeds p ⁺ layer 16 (the position at the left end is C and the position at the right end is D) on the right side by further increasing Vd than (b) in FIG. In this case, the situation in the region on the left side of A is the same as in (b), so that the region on the right side of B is (b). Therefore, in (c), the electric field strength E on the right side of C is greatly reduced, and the electric field strength E on the left side of C is large. After that, (d) is a case where Vd is further increased as compared with (c) in FIG.

In the case of FIG. 2, the electric field strength E has a single peak distribution and its maximum value is obtained at the pn junction interface, whereas in the case of FIG. 3 (d), the electric field strength E is the pn junction interface. It may be the maximum value in places other than. Further, since Vd is an integral value of the distribution of the electric field strength E in FIGS. 2 and 3, in the case of FIG. 3 in which a region where | dE / dx | is small (a region where the electric field strength E is maintained high) is widely provided. Can lower the maximum value of the electric field strength as compared with the case of FIG. 2 if Vd is equivalent. That is, by providing the p ⁺ layer as shown in FIG. 1, | dE / dx | can be made small, and even when Vd is large, the maximum electric field strength can be made lower than that of the conventional semiconductor device 200. , The pressure resistance can be increased.

The shape of the distribution of the electric field strength E in the case of FIG. 3 (d) where Vd is increased and the depletion layer is the widest and the electric field strength is the highest is the number of the embedded oxide layers 25, the width of the embedded oxide layer 25, and the width of the p ⁺ layer 16. , P ⁺ layer 16 can be adjusted by setting the impurity concentration. Therefore, the widths of the embedded oxide layer 25 and the p ⁺ layer 16 do not have to be the same in all cases. In this case, these widths can be set to gradually change from one side to the other in the lateral direction in FIG. 1. The same applies to the impurity concentration of the p ⁺ layer 16.

Further, the potential of each p ⁺ layer 16 can be adjusted by appropriately connecting electrodes to a plurality of existing p ⁺ layers 16, which also adjusts the distribution of the electric field strength E in the case of FIG. 3D. However, this can reduce the maximum electric field strength. That is, with such a configuration, the withstand voltage can be further increased.

Next, a manufacturing method for manufacturing the above-mentioned semiconductor device 1 will be described. Here, since the structure other than the structure around the embedded oxide layer 25 is the same as that of the conventionally known semiconductor device 200, only the step of forming the structure around the embedded oxide layer 25 will be described. FIG. 4 is a process sectional view showing this manufacturing method.

First, as shown in FIG. 4A, the p ⁺ layer 16 is formed on a part of the surface of the flat semiconductor substrate 10 (n-type layer 11) by ion implantation or the like. The p ⁺ layer 16 does not need to be divided as in the state of FIG. 1, and at this point, the p ⁺ layer 16 in the state of FIG. 1 can be widely formed so as to be in a connected state.

Next, as shown in FIG. 4B, a groove T having a depth not penetrating the n-type layer 11 corresponding to the shape of the embedded oxide layer 25 in FIG. 1 is formed in the n-type layer 11 by dry etching. (Groove formation step). After that, thermal oxidation is performed to form a thin thermal oxide film 31 composed of SiO ₂ on the entire surface as shown in FIG. 4 (c). The thermal oxide film 31 is uniformly formed on the surface of the n-type layer 11 including the inner surface of the groove T, but its thickness is several hundred nm or less and is sufficiently thin compared to the width and depth of the groove T. As shown in FIG. 4 (c), the shape of the surface at this time is almost the same as the shape before thermal oxidation in FIG. 4 (b), and the shape of the groove T is reflected.

After that, as shown in FIG. 4D, for example, a CVD oxide film 32 composed of SiO ₂ is thickly formed by a CVD method using TEOS (tetraethoxysilane) as a raw material, and a groove T is embedded in the film. (Insulation layer forming step). Then, by removing the exposed SiO ₂ surface by a method such as CMP (chemical mechanical polishing) and flattening it, as shown in FIG. 4 (e), the CVD oxide film 32 and thermal oxidation are performed only in the groove T. The film 31 can be left, and the remaining portion can be used as the embedded oxide layer 25 (insulating layer removing step). The thermal oxide film 31 may be left in the portion where the gate electrode 22 is formed, and this may be used as the gate oxide film 20 in FIG.

The manufacturing process for forming the embedded oxide layer 25 shown in FIG. 4 is the same as the manufacturing process for forming the STI for element separation in a normal CMOS integrated circuit. At this time, for example, in the steps shown in FIGS. 4 (b) to 4 (e), optimization is performed according to the width of the groove T (width of the embedded oxide layer 25). In the above-mentioned semiconductor device 1, since the width of the embedded oxide layer 25 and the above-mentioned STI width can be made equal to each other, when manufacturing a semiconductor device in which the LDMOS and CMOS integrated circuit shown in FIG. 1 are mixedly mounted. , The above manufacturing process can be commonly used. Therefore, the above-mentioned semiconductor device 1 can be manufactured at low cost.

Further, in the above example, the first semiconductor layer (n-type layer 11) to which one of the main electrodes (drain electrode 23) is connected is an n-type (first conductive type) due to a high electric field inside. It is assumed that the second semiconductor layer (p-type layer 12) locally formed on the surface and to which the other of the main electrodes (source electrode 91) is connected is p-type (second conductive type). However, it is clear that the same effect can be obtained by reversing the conductive type of the first semiconductor layer and the second semiconductor layer and reversing the conductive type of the surface conductive layer (p ⁺ layer 16).

Although the above-mentioned semiconductor device 1 is LDMOS, if it is a semiconductor device in which a high potential difference is generated in the in-plane direction of the semiconductor substrate and a current is passed in the in-plane direction to operate, the above-mentioned field oxide film 94 is used. In many cases, an insulating layer similar to the above is used to secure the withstand voltage. It is clear that the above configuration can replace the structure of such an insulating layer in such cases, thereby achieving a similar effect. That is, the above configuration is not limited to LDMOS.

1,200 Semiconductor device 10,80 Semiconductor substrate 11,81 n-type layer (first semiconductor layer)
12, 82 p-type layer (second semiconductor layer)
13,83 p ⁺ layer 14, 15, 84, 85 n ⁺ layer 16 p ⁺ layer (surface conductive layer)
20, 90 Gate oxide film 21, 91 Source electrode (main electrode)
22, 92 Gate electrode 23, 93 Drain electrode (main electrode)
25 Embedded oxide layer ((embedded insulating layer))
31 Thermal oxide film 32 CVD oxide film 94 Field oxide film T groove

Claims (6)

A semiconductor device using a semiconductor substrate in which a semiconductor element is formed so that a potential difference is generated in the in-plane direction on the surface side and a current flows in the in-plane direction.
A first semiconductor layer having a first conductive type and having the current flowing in the in-plane direction is provided on the surface side of the semiconductor substrate.
In the first semiconductor layer,
A plurality of grooves in which the first semiconductor layer is dug from the surface side without penetrating the first semiconductor layer are formed along the direction in which the potential difference is generated.
The width of the groove is in the range of 3 to 10 μm, and the distance between the grooves is in the range of 0.3 to 0.8 μm along the direction in which the potential difference is generated.
The groove is embedded with an insulating layer,
A semiconductor device characterized in that a surface conductive layer having a second conductive type opposite to the first conductive type is formed on the surface between adjacent grooves. A second semiconductor layer having a second conductive type opposite to the first conductive type is locally formed on the surface of the first semiconductor layer, and the second semiconductor layer is formed on the surface of the first semiconductor layer. The main electrode is connected to a location separated from the semiconductor layer of
The semiconductor device according to claim 1, wherein the plurality of grooves are formed between the main electrode and the second semiconductor layer in a plan view. The semiconductor device according to claim 2, wherein the semiconductor element is a MOSFET, and the main electrode is a drain electrode in the MOSFET. The semiconductor device according to any one of claims 1 to 3, wherein the electrode is connected to the surface conductive layer. The method for manufacturing a semiconductor device according to any one of claims 1 to 4.
A groove forming step of forming the groove in the first semiconductor layer,
An insulating layer forming step of forming the insulating layer on the surface of the semiconductor substrate so as to embed the groove.
An insulating layer removing step for removing the insulating layer on the surface other than the inside of the groove,
A method for manufacturing a semiconductor device, which comprises the above. In the insulating layer forming step,
The method for manufacturing a semiconductor device according to claim 5, wherein a thermal oxide film is first formed on the inner surface of the groove by thermal oxidation, and then the insulating layer is formed by a CVD method.

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