JP7037538B2 - Gate drive circuit - Google Patents

Description

The present invention relates to a gate drive circuit having a short circuit detection function (circuit) of a semiconductor device for detecting a short circuit of a semiconductor device such as an IGBT (Insulated Gate Bipolar Transistor). Further, the present invention relates to a gate drive circuit having a function (circuit) for detecting an overcurrent of a semiconductor device.

When an IGBT that switches between high voltage and large current is destroyed, it causes a great damage to peripheral devices, so it is necessary to avoid destruction as much as possible. Therefore, it is important that the gate driver circuit that drives the IGBT has a function of protecting the IGBT in preparation for such a situation. The present invention relates to a function of protecting an IGBT when the load of the IGBT is in a short-circuited state or a state close to it.
Usually, as a method of detecting an abnormality such as a short circuit of a load, a method of detecting an increase value of Vce (collector voltage) when the IGBT is in the ON state is adopted.
In the conventional method, a certain time may be provided from the detection of the abnormality to the transmission of the abnormality signal. This fixed time is a time for holding and waiting for transmission of an abnormal signal, and may be called a mask time. This mask time is required to have a certain accuracy from the viewpoint of preventing malfunction and preventing the overload of the IGBT.

<Details of the conventional method>
<Problem 1 of the conventional method>
FIG. 17 is a circuit diagram adopting a conventional method. FIG. 17 shows a circuit in which the gate driver 10 drives the IGBT 12. The gate driver 10 is in the form of a drive IC, and is described as a Drive IC in FIG.

The operation when the IGBT 12 normally repeats the ON operation and the OFF operation will be described. During the OFF operation of the IGBT 12, the output value of the OUT terminal 14 of the gate driver 10 (Drive IC) is LOW, and the transistor Q1 of the gate driver 10 is turned ON to discharge the charge of the capacitor Cdesat to 0.
When the IGBT 12 is turned on, the value of the OUT terminal 14 is High, so a Low signal is input to the base of the transistor Q1 via the inverter 16. As a result, the transistor Q1 is turned off, but the collector-emitter voltage of the IGBT 12 becomes the saturation voltage, so that the current of the current source _Ideat flows to the collector terminal of the IGBT 12 via the diode Ddesat.

ここで、Ｖ_{Ｃｄｅｓａｔ}（０）は、ＩＧＢＴ１２が正常動作時におけるコンデンサＣｄｅｓａｔの端子間電圧である。ＶＦ_{Ｄｄｅｓａｔ}は、ダイオードＤｄｅｓａｔの順方向電圧である。ＶＣＥ_ｓａｔは、ＩＧＢＴ１２が正常にＯＮ動作している場合の、コレクタ－エミッタ間の飽和電圧とする。 As a result, the capacitor Cdesat is charged to a voltage obtained by adding the forward voltage of the diode _Ddesat by the current source Ideat and the saturation voltage between the collector and the emitter of the IGBT 12. That is, the voltage between the terminals of the capacitor Cdesat is the saturation voltage + the forward voltage of the diode Ddesat.
Since the voltage of the _DESAT terminal of the gate driver 10 maintains a voltage lower than the reference voltage V desert, the comparator 18 in the gate driver 10 does not invert the value of the output signal, so that no abnormal signal is output. If the voltage between the terminals of the capacitor Cdesat is expressed by an equation, it is expressed by the following equation (1).

Here, _VCdesat (0) is a voltage between terminals of the capacitor Cdesat when the IGBT 12 is operating normally. The VF _Ddesat is a forward voltage of the diode Ddesat. The VCE _sat is the saturation voltage between the collector and the emitter when the IGBT 12 is operating normally.

In the above state, when an abnormality occurs in the load of the IGBT 12, the collector-emitter voltage VCE of the IGBT 12 rises and reaches the positive side power supply VCS level, the diode Ddesat is in a cutoff state, and the capacitor Cdesat is a current source. The current of the emitter flows in, the voltage between the terminals of the capacitor _Cdesat rises, and the reference voltage Vdesat built in the gate driver 10 is reached. As a result, the comparator 18 in the gate driver 10 is inverted and sends an abnormal signal.

ここで、Ｖ_{Ｃｄｅｓａｔ}（０）は、コンデンサＣｄｅｓａｔの初期電圧である。
また、Ｃ_{ｄｅｓａｔ}は、コンデンサＣｄｅｓａｔの静電容量を表し、Ｉ_{ｄｅｓａｔ}は、電流Ｉ_{ｄｅｓａｔ}の電流値を表す。 The output signal of the comparator 18 becomes High when the voltage between the terminals of the capacitor Cdesat is higher than the reference voltage _Vdesat , which represents an abnormal signal.
At this time, a mask time T _mask from the occurrence of an abnormality in the load of the IGBT 12 until the gate driver 10 sends an abnormal signal is set, and this mask time T _mask is expressed by the equation (2). ..

Here, _VCdesat (0) is the initial voltage of the capacitor Cdesat.
Further, C _desat represents the capacitance of the capacitor C desat, and I _desat represents the current value of the current I _desat .

このように、マスク時間Ｔ_ｍａｓｋはＩＧＢＴ１２の異常の発生するタイミングにより、式（４）で与えるΔｔだけ変動することになる。

このようにして、マスク時間Ｔ_ｍａｓｋは異常が発生するタイミングにより変動してしまうという課題がある。 On the other hand, when the abnormality of the IGBT 12 occurs immediately after the IGBT 12 shifts from the OFF operation to the ON operation, the capacitor Cdesat does not have time to be charged by the _Idestat current, so that _VCdesat (0) = 0. In such a case, the mask time T _mask is expressed by the equation (3).

In this way, the mask time T _mask fluctuates by Δt given by the equation (4) depending on the timing at which the abnormality of the IGBT 12 occurs.

In this way, there is a problem that the mask time T _mask fluctuates depending on the timing at which an abnormality occurs.

<Problem 2 of the conventional method>
Further, since the low reference voltage Vdesat shown in FIG. 17 means that there is little margin for malfunction, it may be necessary to increase the voltage value of the reference voltage Vdesat as necessary. However, since the voltage is built into the gate driver 10, there is a problem that it is generally difficult to change this voltage value.

Prior Patented Technology For example, Patent Document 1 (Japanese Unexamined Patent Publication No. 2004-140891), which will be described later, discloses a power conversion device capable of reliably detecting that a failure has occurred in some elements constituting an overvoltage protection circuit. There is. Specifically, the time when the voltage of the overvoltage protection circuit changes when the semiconductor element to be protected is turned off is measured, and when the time exceeds the set time length, the overvoltage protection circuit A circuit for determining that a failure has occurred in a part of the elements constituting the above is described.

Japanese Unexamined Patent Publication No. 2004-140891

As described above, the above-mentioned conventional method has the following problems.
Problem 1: Change in mask time due to short-circuit conditions As described above, when the IGBT load is short-circuited, a large current flows and the IGBT Vce rises and is damaged, but detection is detected for several microseconds. A delayed mask time is required. This mask time needs to have a certain accuracy, and it is necessary to keep it as stable as possible even when the load short-circuit condition changes variously.
Here, the change in the load short-circuit condition includes, for example, a change in the magnitude of the inductance connected to the IGBT at the time of short-circuit. For example, it is desirable that the mask time described above does not fluctuate depending on whether the load inductance is very small (for example, 200 nH) or the load inductance is relatively large (for example, 2 μH).
However, when a general-purpose control IC is used as a gate driver and the IGBT is driven, the mask time varies exclusively due to the change in the load short-circuit condition as described above.

Problem 2: Margin for malfunction Further, the gate driver arranged in the vicinity of the IGBT under a large current and high voltage is required to have a large margin for malfunction. However, some gate drivers using general-purpose control ICs have a low threshold voltage, and may not have a sufficient malfunction margin.

The present invention has been made in view of these above problems, and an object of the present invention is to provide a gate drive circuit that realizes an improvement in the accuracy of masking time and an improvement in a margin for malfunction.

First, to improve the accuracy of the mask time, we adopted a method to reduce the fluctuation of the mask time by controlling the initial charge of the capacitor that determines the time constant. The inventor of the present application has made diligent research on methods such as controlling the initial charge of a capacitor to 0 or controlling the initial charge to a constant value, and has come to the present invention.
In addition, to improve the margin against malfunction, we adopted a method of configuring the circuit so that the threshold voltage can be set separately. The inventor of the present application has come up with the present invention as a result of studying various circuits for separately setting the threshold voltage and proceeding with diligent research.
Specifically, the present invention employs the following means.

(1) The present invention is a gate drive circuit for driving a power semiconductor switch in order to solve the above problems, and is a comparison circuit for comparing a collector-emitter voltage of the power semiconductor switch with a predetermined threshold voltage. The comparison circuit includes a time measurement circuit that starts time measurement after detecting that the collector-emitter voltage exceeds the threshold voltage, and the time measurement circuit measures the standby hold time. Later, it is a gate drive circuit including an output circuit for outputting an abnormal signal, which means that the power semiconductor switch is in an abnormal state.

(2) Further, the present invention is the gate drive circuit according to (1), wherein the comparison circuit is immediately after the power semiconductor switch shifts from an OFF operation to an ON operation, or the power semiconductor switch is in a saturation state. In the above situation, when the collector current increases due to a predetermined failure or abnormality and the power semiconductor switch is in a desaturation state, the collector-emitter voltage and the predetermined threshold voltage can be compared. It is a characteristic gate drive circuit.

(3) Further, the present invention is the gate drive circuit according to (1) or (2), and the abnormal signal is generated by the power semiconductor switch when a predetermined output signal changes to a predetermined value. It is a gate drive circuit characterized by being a signal meaning that it is in a saturation state.

(4) Further, the present invention is the gate drive circuit according to any one of (1) to (3), wherein the time measurement circuit is a capacitor to which a charging current having a constant current value is applied. Therefore, the charging capacitor for setting the time until the voltage between the terminals of the capacitor rises with charging and reaching a predetermined voltage value as the standby hold time, and the power semiconductor switch are in the saturation state, and the collector. -When the value of the emitter voltage is equal to or less than the threshold voltage of the comparator, the current of the constant charging current value is bypassed so that the charging current does not flow into the charging capacitor. The comparison circuit includes a charging current detour circuit in which the initial charge of the comparison circuit is set to 0, and the comparison circuit detects that the power semiconductor switch is in a desaturated state and the collector-emitter voltage exceeds the threshold voltage of the comparison circuit. In this case, the gate drive circuit is characterized in that the charging current detour is cut off and the constant charging current value flows into the capacitor from the state where the initial charge of the capacitor is 0.

(5) Further, the present invention is the gate drive circuit according to (4), in which the power semiconductor switch outputs a signal for shifting the power semiconductor switch to be driven from the OFF state to the ON state, and then the power semiconductor switch. When a delay time occurs before the actual ON operation, the initial charge remains in the charging capacitor, and the first initial charge that generates the standby hold time shorter by the time for charging the initial charge is generated. The output circuit comprises a charging circuit, wherein the time measuring circuit outputs an abnormal signal, which means that the power semiconductor switch is in a desaturation state, after measuring the short standby hold time. It is a gate drive circuit.

(6) Further, the present invention is the gate drive circuit according to (4), in which the power semiconductor switch outputs a signal for shifting the power semiconductor switch to be driven from the OFF state to the ON state, and then the power semiconductor switch. When a delay time occurs before the actual ON operation, the charging current bypass circuit includes a series circuit of a bypass switch for bypassing the charging current and a resistor directly connected to the bypass switch. Even when the charging current is bypassed by the charging current bypass circuit, the initial charge remains in the charging capacitor by the amount of the initial charge resistance, and the standby hold time shorter by the time of charging the initial charge is generated. The output circuit is a gate drive circuit, characterized in that the time measurement circuit outputs an abnormal signal meaning that the power semiconductor switch is in a desaturation state after measuring the short standby hold time. ..

(7) Further, in the gate drive circuit according to any one of (1) to (6), the present invention has a cathode terminal connected to the comparison circuit and an anode terminal to a collector terminal of the power semiconductor switch. The comparison circuit includes a diode to be connected, and the comparison circuit is a gate drive circuit characterized in that the collector voltage of the power semiconductor switch is detected via the diode.

According to the present invention, it is possible to provide a gate drive circuit for driving a power semiconductor switch, which improves the accuracy of the standby hold time (mask time) and improves the margin for malfunction.

It is a circuit diagram of the gate drive circuit 100 in Embodiment 1. It is a functional block diagram of the circuit shown in FIG. It is a circuit diagram of the gate drive circuit 200 in Embodiment 2. It is a circuit diagram of the equivalent circuit in the transition state from the OFF operation to the ON operation of the IGBT. It is a graph which shows the voltage waveform of the non-inverting input terminal of the comparator CMP1 of a gate driver 110 when there is no diode D1. It is a graph which shows the voltage waveform of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 when the diode D1 is inserted. It is a time chart which showed the situation which the mask time fluctuates when the transition operation to the ON operation of the IGBT 12 is delayed, and when the load abnormality occurs after the ON operation of the IGBT 12 is completed. It is a time chart showing the situation where the mask time fluctuates when the transition operation to the ON operation of the IGBT 12 is delayed and the load abnormality occurs before the ON operation of the IGBT 12 is completed. It is a circuit diagram of the gate drive circuit 300 in Embodiment 3. 6 is a time chart showing a situation in which the mask time fluctuates when a load abnormality occurs after the IGBT 12 is turned on in the circuit shown in the third embodiment. It is a figure which shows the example of another constituent circuit which makes the initial charge, and is the circuit diagram of the gate drive circuit 400. It is a circuit diagram of the gate drive circuit 500 which concerns on the specific Example 1. FIG. It is a graph which shows the mask time when an abnormality occurs 20 μsec after ON operation of the IGBT 12. It is a graph which shows the mask time when the IGBT 12 is turned on and an abnormality occurs immediately after that. It is a circuit diagram of the gate drive circuit 600 which concerns on the specific Example 2. FIG. It is a circuit diagram of the gate drive circuit 700 which concerns on the specific Example 3. FIG. It is a circuit diagram which shows the circuit structure when the conventional gate driver 10 drives an IGBT 12.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
1. 1. Embodiment 1
FIG. 1 shows a circuit diagram showing a gate drive circuit 100 according to the present embodiment. In FIG. 1, the portion excluding the IGBT 12 is a characteristic portion of the gate drive circuit 100.
As shown in FIG. 1, it is a circuit using the gate driver 110 like the conventional circuit shown in FIG. 17, and the configuration / operation of the gate driver 110 is the configuration of the gate driver 10 shown in FIG.・ It is the same as the operation. The gate driver 110 may also be configured by a predetermined IC or the like like the gate driver 10 shown in FIG.
The OUT terminal 114 of the gate driver 110 is connected to the gate terminal of the IGBT 12 via the buffer 120 and drives the IGBT 12. A capacitor Cdesat is connected between the GND terminal of the gate driver 110 and the DESAT terminal. As will be described later, this capacitor Cdesat is an element that plays an important role in determining the mask time by its charging operation.
Here, the IGBT 12 corresponds to a suitable example of a power semiconductor switch in the claims.
The gate drive circuit 100 corresponds to a preferred example of a gate drive circuit in the claims. The gate drive circuits 200, 300, 400, 500, 600, and 700, which will be described later, also correspond to suitable examples of the gate drive circuits in the claims.

The collector terminal of the transistor Q2 is connected to the DESAT terminal, and the emitter terminal is connected to the GND terminal. The base terminal of the transistor Q2 is connected to the output terminal of the comparator CMP2. As will be described later, the transistor Q2 plays a role of discharging the electric charge of the capacitor Cdesat. The inverting input terminal of the comparator CMP2 is connected to the positive power supply VCS via the resistor Rdesat. Further, the inverting input terminal is connected to the anode terminal of the diode Ddesat.
The anode terminal of the diode Ddesat is connected to the inverting input terminal of the comparator CMP2, and the cathode terminal is connected to the collector terminal of the IGBT 12.
The non-inverting input terminal of the comparator CMP2 is connected to the positive terminal of the second reference voltage Vdesat-2. The other (minus side) terminal of the second reference voltage Vdedsat-2 is connected to the GND terminal.
Further, the emitter terminal of the IGBT 12 is connected to the GND terminal.
The transistor Q2 corresponds to a suitable example of the charge current detour circuit in the claims.

When the IGBT 12 is in the OFF operation state, the collector voltage of the IGBT 12 becomes a high voltage, so that the positive power supply VCS is applied to the inverting input terminal of the comparator CMP2. The output signal of the comparator CMP2 is Low, and the transistor Q2 is in the OFF state.
At this time, the output signal of the OUT terminal of the gate driver 110 (applied to the gate terminal of the IGBT 12) is Low, and this output signal is inverted by the inverter 116 to become High and applied to the base terminal of the transistor Q1. .. Therefore, the transistor Q1 of the gate driver 110 maintains the ON operating state to discharge the electric charge of the capacitor Cdesat. Therefore, the initial voltage of the capacitor Cdesat is 0V.
The capacitor Cdesat corresponds to a suitable example of a charging capacitor in the claims. The capacitor C3 shown in FIG. 12, which will be described later, also corresponds to a suitable example of the charging capacitor in the claims.

When the output signal of the OUT terminal 114 becomes High, the IGBT 12 is turned on. At this time, since the output signal of the OUT terminal 114 is inverted by the inverter 116 and applied to the base terminal of the transistor A1, the transistor Q1 is turned off.
Since the collector-emitter voltage (collector voltage) of the IGBT 12 is the saturation voltage, the voltage applied to the inverting input terminal of the comparator CMP2 is the forward voltage of the diode Ddesat and the saturation voltage between the collector and the emitter of the IGBT 12. The sum, that is, VF _Diode + VCE _sat , which is lower than the second reference voltage Vdesat-2, so that the transistor Q2 is in the ON state.

What is characteristic of this embodiment is that even if the IGBT 12 is turned on, the transistor Q2 is turned on so that the capacitor Cdesat is not charged. As a result, the voltage between the terminals of the capacitor Cdesat can be maintained at 0V. That is, the initial voltage of the capacitor Cdesat could be fixed to 0.
Here, when the load of the IGBT 12 becomes abnormal and the collector-emitter voltage of the IGBT 12 rises and exceeds the second reference voltage V _desert-2- VF _Ddesat , the voltage of the inverting input terminal of the comparator CMP2 becomes the second reference. The voltage exceeds V _desat-2 . Therefore, the comparator CMP2 output signal becomes Low, the transistor Q2 is turned off, and the capacitor Cdesat is started to be charged by the current source _Ideat in the gate driver 110.

このように、式（５）には従来技術の場合の式（２）のようにコンデンサＣｄｅｓａｔの初期電荷に伴うＶ_{Ｃｄｅｓａｔ}（０）項が関係しないので、異常の発生するタイミングに依存しないで、常に一定のマスク時間を実現することができる。
また、第２の基準電圧Ｖ_{ｄｅｓａｔ－２}は、プラス側電圧ＶＣＣ以下の電圧であれば任意に選定できるので、ノイズ等に対する誤動作マージンをより大きくとることが可能である。したがって、従来方式のノイズに対するマージンを確保しにくい欠点を解消することができる。第２の基準電圧Ｖ_{ｄｅｓａｔ－２}は、請求の範囲の所定の閾値電圧の好適な一例に相当する。 When the voltage between terminals V _Cdesat of the capacitor Cdesat exceeds the first reference voltage _Vdestat-1 due to this charging, the output signal of the comparator CMP1 in the gate driver 110 is inverted and becomes High, and an abnormal signal is transmitted.
The mask time from when the load of the IGBT 12 becomes abnormal and the collector-emitter voltage of the IGBT 12 exceeds V _desert-2 -VF _Ddesat until the abnormal signal is transmitted is expressed by the following equation (5).

As described above, since the _VCdesat (0) term associated with the initial charge of the capacitor Cdesat is not related to the equation (5) as in the equation (2) in the case of the prior art, it does not depend on the timing at which the abnormality occurs. A constant mask time can always be achieved.
Further, since the second reference voltage V _desert-2 can be arbitrarily selected as long as it is a voltage equal to or lower than the positive side voltage VCS, it is possible to take a larger malfunction margin against noise and the like. Therefore, it is possible to eliminate the drawback that it is difficult to secure a margin for noise in the conventional method. The second reference voltage V _desat-2 corresponds to a suitable example of a predetermined threshold voltage in the claims.

Functional block diagram A functional block diagram of the circuit in FIG. 1 of the first embodiment is shown in FIG.
In the functional block diagram of FIG. 2, in addition to the gate driver 110, a time measurement circuit 130 and a comparison circuit 132 are shown.
The comparison circuit 132 is a circuit corresponding to the comparator CMP2 and the second reference voltage V _desert-2 in FIG. 1, and corresponds to a suitable example of the comparison circuit in the claims. Therefore, the comparison circuit 132 compares the collector-emitter voltage of the IGBT 12 with the second reference voltage V _desert-2 , and outputs the comparison result.
Further, the second reference voltage corresponds to a suitable example of a predetermined threshold voltage in the claims.
The time measurement circuit 130 is a circuit corresponding to the capacitor Cdesat and the transistor Q2 in FIG. 1, and corresponds to a suitable example of the time measurement circuit in the claims.
This transistor Q2 constitutes a charge current bypass circuit within the range of the claim, and bypasses the charge current of the capacitor Cdesat based on the output signal of the comparison circuit 132, or charges the capacitor Cdesat without bypassing. It is possible to perform the operation of making.
One of the characteristic matters in this embodiment is that a charging current open circuit (transistor Q2) is provided. As a result, the charge of the capacitor Cdesat at the start of charging can be set to 0 in advance, so that the measurement of the mask time can be made more accurate.
The gate driver 110 corresponds to a preferred example of an output circuit in the claims. In particular, the output signal of the comparator CMP1 corresponds to a suitable example of the abnormal signal in the claims.

2. 2. Embodiment 2
A circuit diagram of the gate drive circuit 200 according to the second embodiment is shown in FIG. FIG. 3 is a circuit in which a diode D1 is inserted between the inverting input terminal of the comparator CMP2 of FIG. 1 and the anode of the diode Ddesat, and a capacitor C1 is added. The capacitor C1 represents a parasitic capacitance of the inverting input terminal of the comparator CMP2 or a capacitor inserted to absorb noise that causes a malfunction. The configurations other than these added configurations are the same as those in FIG.
The diode D1 corresponds to a suitable example of the diode in the claims.

In this way, when the capacitor C1 is present, due to the transient phenomenon in which the IGBT 12 shifts from the OFF operation to the ON operation, the electric charge of the capacitance existing between the terminals of the diode Ddesat charges the capacitor C1 in the negative direction, and the mask time fluctuates. May be done. The diode D1 is a diode for preventing such a phenomenon.
When the IGBT 12 is in the OFF operation state, the diode Ddesat is reverse-biased, so that it can be considered equivalently as a capacitor. A voltage close to the collector voltage when the IGBT 12 is in the OFF state is applied to this equivalent capacitor, and when the IGBT 12 shifts from the OFF state to the ON state, immediately after that, as shown in the equivalent circuit of FIG. 4, the capacitor C1 Is charged in the negative direction, and the detection operation of the comparator CMP2 is delayed by the time until it recovers. FIG. 4 shows an equivalent circuit in a transition state in which the IGBT 12 is in a transition state from an OFF operation to an ON operation.

この式（６）から、ＩＧＢＴ１２がＯＮ動作した瞬間にコンデンサＣ１の端子間電圧は
－Ｖｈｉ×（Ｃ_{Ｄｄｅｓａｔ}／（Ｃ_１＋Ｃ_{Ｄｄｅｓａｔ}））までマイナス電圧に充電される。その後、時定数Ｒ_{ｄｅｓａｔ}（Ｃ_１＋Ｃ_{Ｄｄｅｓａｔ}）で０Ｖに復帰する。この復帰時間は、負荷異常がＩＧＢＴ１２のＯＮ動作直後に発生した場合と、復帰時間の終了後に負荷異常が発生した場合とで、マスク時間が異なる結果となる。
なお、Ｃ_{Ｄｄｅｓａｔ}は、ダイオードＤｄｅｓａｔの等価コンデンサの容量を表し、Ｃ_１は、コンデンサＣ１の容量を表し、Ｒ_{ｄｅｓａｔ}１は、抵抗Ｒｄｅｓａｔの抵抗値を表す。 Here, in FIG. 4, Vhi is the collector voltage when the IGBT 12 is in the OFF operation, and is assumed to be a sufficiently high voltage with respect to the positive side power supply VCS. Therefore, assuming that Vhi-V CC≈Vhi, the transient waveform of the voltage between the capacitors C1 terminals when the IGBT 12 operates from the OFF operation to the ON operation can be expressed by the equation (6).

From this equation (6), the voltage between the terminals of the capacitor C1 is charged to a negative voltage up to −Vhi × (C _Ddesat / (C ₁ + C _Ddesat )) at the moment when the IGBT 12 is turned on. After that, it returns to 0V with the time constant R _desat (C ₁ + C _{D desat} ). This recovery time has different mask times depending on whether the load abnormality occurs immediately after the ON operation of the IGBT 12 or the load abnormality occurs after the recovery time ends.
Note that C _Ddesat represents the capacity of the equivalent capacitor of the diode Ddesat, C ₁ represents the capacity of the capacitor C1, and R _desat 1 represents the resistance value of the resistor Rdesat.

That is, if a load abnormality occurs immediately after the IGBT 12 is turned on, the detection of an increase in the collector-emitter voltage Vce of the IGBT 12 is delayed by the recovery time, so that the mask time is finally lengthened by the recovery time. Therefore, as shown in FIG. 3 of the second embodiment, this phenomenon can be suppressed by inserting the diode D1.
The voltage waveforms of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode D1 is not provided and the case where the diode D1 is inserted are shown in the graphs of FIGS. 5 and 6, respectively. In each graph, the horizontal axis shows the passage of time, and the vertical axis shows the voltage waveform of the non-inverting input terminal and various other signal waveforms.

When there is no diode D1 (FIG. 5), the potential of the non-inverting input terminal of the gate driver 110 comparator CMP1 drops in the negative direction at the moment when the IGBT 12 is turned on, and then the potential value gradually recovers. ing. In the example of FIG. 5, it takes about 1 μsec, and is labeled as “increased time” in FIG. Therefore, the mask time becomes longer by that amount, which causes fluctuations in the mask time. That is, the masking time is the time until the charging voltage of the capacitor Cdesat exceeds the first reference voltage Vdesat-1, but as is clear from FIG. 5, the masking time is longer by the above-mentioned "increased time". (Fluctuating).
On the other hand, when the diode D1 is inserted, it is clear that the voltage change of the non-inverting input terminal of the gate driver 110 comparator CMP1 is eliminated and there is no factor of fluctuation in the mask time (see FIG. 6).

As described above, according to the present embodiment, it is possible to suppress fluctuations in the mask time while effectively removing noise that causes malfunction.

3. 3. Embodiment 3
Delay time from the generation of the ON signal from the control circuit that outputs the control signal of the IGBT 12 to the actual ON operation of the IGBT 12 due to the characteristics of the IGBT 12 or the request of the target set side for power control by the IGBT 12. May be long. The characteristics of the IGBT 12 are, for example, when the gate resistance is very large.
Under such circumstances, even in the load circuit shown in the first embodiment (FIG. 1), the mask time may fluctuate depending on the timing of occurrence of an abnormality.
7 and 8 show a situation in which the mask time fluctuates depending on the timing of occurrence of a load abnormality when the transition operation of the IGBT 12 to the ON operation is delayed in the circuit including the gate drive circuit 100 described with reference to FIG. The time chart is shown.

FIG. 7 is an example in which a load abnormality occurs after the IGBT 12 completes the ON operation. In other words, it is a time chart when a load abnormality occurs after the delay time of the ON operation of the IGBT 12. In FIG. 7, the horizontal axis represents the passage of time, and the vertical axis represents various signals. Specifically, the voltage across the capacitor Cdesat, the ON / OFF state of the IGBT 12, the gate-source voltage of the IGBT 12, and the control signal from the control circuit that controls the IGBT 12 are shown.

First, when the control signal from the control circuit changes to a value that turns on the IGBT 12, the gate-source voltage of the IGBT 12 starts to rise, and the voltage across the capacitor Cdesat also starts to rise.
In the example of FIG. 7, the response speed of the IGBT 12 is slow, and the IGBT 12 shifts to the ON operation after the delay time td elapses. Then, the voltage across the capacitor Cdesat is reset to 0. After that, when a failure, for example, a short circuit failure of the load occurs, charging of the capacitor Cdesat is started, and the mask time is started to be timed.
The mask time at this time is t1 (see FIG. 7), and the charging capacitor Cdesat starts charging from 0 when the initial charge is 0, and the charging time from 0V to Vdesat across the voltage of the capacitor Cdesat is the masking time.

On the other hand, FIG. 8 shows an example in which a load abnormality occurs before the IGBT 12 is turned on. In other words, it is a time chart when a load abnormality occurs within the ON operation delay time of the IGBT 12.
In FIG. 8, as in FIG. 7, the horizontal axis represents the passage of time, and the vertical axis represents the same type of signal as in FIG.

As a normal operation of the gate driver 110, when a predetermined control circuit sets the value of the control signal to a value for turning on the IGBT 12 (when an ON operation command is issued), a detour circuit for the charging current inside the gate driver 110 almost at the same time. Is cut off (transistor Q1 is turned off).
That is, the output signal of the OUT terminal in FIG. 1 becomes High, and this signal is applied to the base terminal of the transistor Q1 via the inverter 116, so that the transistor Q1 which is a detour circuit of the charging current is turned off.

In the example of FIG. 8, since the ON operation of the IGBT 12 is delayed, the voltage of the inverting input terminal of the comparator CMP2 of FIG. 1 is higher than that of Vdesat-2, so that the transistor Q2 also maintains the OFF state. Therefore, charging of the charging capacitor Cdesat is started almost at the same time when the control signal gives a command to turn on the IGBT 12. This situation is shown in the time chart of FIG. At this time, the gate-source voltage of the IGBT 12 also rises, but since the ON operation of the IGBT 12 is delayed, the IGBT 12 remains OFF for a certain period of time (see FIG. 8).
Specifically, the OFF state of the IGBT 12 continues for the period of the delay time td.
In the example described with reference to FIG. 8, a failure such as a short circuit has occurred before the IGBT 12 is turned on.

Then, after the delay time td in FIG. 8 has elapsed, the IGBT 12 is delayed and shifts to the ON operation. However, when the IGBT 12 shifts to the ON operation (when the delay time td has elapsed), the load abnormality has already occurred, so even if the IGBT 12 shifts to the ON operation, the inverting input terminal voltage of the comparator CMP2 remains unchanged. , Since the voltage higher than Vdesat-2 is maintained, the transistor Q2 also keeps the OFF state, and the capacitor Cdesat keeps charging. Therefore, the time from 0V to Vdesat-1 for the voltage between the terminals of the capacitor Cdesat is t2 (see FIG. 8).

This time t2 is the same as the mask time t1 in FIG. However, the time measurement in the unsaturated state (Desaturation state: desaturation state) (hereinafter referred to as the Desat state) must be started after the IGBT 12 is actually in the Desat state. That is, in this case, immediately after the IGBT 12 shifts to the ON operation (the time when the delay time td in FIG. 8 has elapsed), that time must be the starting point of the time measurement. This is because the protection of Desat detection (detection of unsaturated state) must protect the IGBT 12 and at the same time determine the mask time from the viewpoint of preventing the protection circuit from malfunctioning, so the mutual balance must be considered as much as possible. Because.
When the mask time is defined in this way, the mask time in the situation described in FIG. 8 is t3 shown in FIG. 8, and there is a problem that the delay time td of the IGBT 12 is shorter than the mask time t1 in FIG.

In such a case, as shown in FIG. 9, for the discharge of the capacitor Cdesat by the transistor Q2, it is preferable to take a method of intentionally giving the initial charge to the capacitor Cdesat at the start of the discharge of the capacitor Cdesat. Vb in FIG. 9 discharges the capacitor Cdesat by the transistor Q2 when the IGBT 12 completes the ON operation transition, but does not discharge all the charges of the capacitor Cdesat, and serves to leave only the voltage between the terminals of the capacitor Cdesat as Vb. That is, even if the transistor Q2 is turned on, the voltage between the terminals of the capacitor Cdesat does not become 0V but becomes Vb. The value of Vb is set to a voltage equal to the inter-terminal voltage Vd of the capacitor Cdesat shown in FIG. 7 when the IGBT 12 shifts to the ON operation with a delay of its own delay time.
As a result of setting Vb (FIG. 9) = Vd (FIG. 7) in this way, the mask time can be constant regardless of the timing at which the load abnormality occurs, as shown in FIG.
The circuit shown in FIG. 9 is the same as that of FIG. 1 except that a new voltage source Vb is provided. That is, the gate drive circuit 300 shown in FIG. 9 is the same circuit as the gate drive circuit 100 of FIG. 1, except for the voltage source Vb.
Further, Vb corresponds to a suitable example of the first initial charge charging circuit.

A time chart for explaining the operation of the circuit (gate drive circuit 300) shown in FIG. 9 is shown in FIG. In FIG. 10, a time chart similar to that in FIGS. 7 and 8 is shown, the horizontal axis represents the passage of time, and the vertical axis shows signals of the same type as those in FIGS. 7 and 8. There is. Comparing this FIG. 10 with the time chart of FIG. 7, the signal waveforms are the same until the time when the IGBT 12 starts the ON operation.
At the time when the IGBT 12 starts the ON operation, the voltage between the terminals of the capacitor Cdesat is reset to 0 in FIG. 7, but in the time chart of FIG. 10, the voltage Vd at that time is maintained. This is due to the voltage source Vb, which is a new configuration shown in FIG. 9, and since Vb = Vd is set, such a time chart is obtained.
FIG. 10 describes an example in which a short-circuit failure occurs after the IGBT 12 is turned on, as in FIG. 7. FIG. 10 is the same as FIG. 7 in that charging of the capacitor Cdesat is started after the short circuit failure occurs. However, in the example shown in FIG. 10, since the capacitor Cdesat is already charged to the voltage Vb (= Vd) at the start of charging, the initial voltage at the start of charging is different. As a result, the mask time in the example of FIG. 10 is t4, and this time is the same as the mask time t3 in FIG. 8, as explained above.

Other Examples of Setting Initial Charges Another circuit configuration for creating initial charges is shown in FIG. As shown in this figure, it is a method of inserting a resistor Rb in series with the collector of the transistor Q2. In this case, the initial charge Vd is Vd = IdeasatRb. Rb in this equation is the resistance value of the resistor Rb, and uses the voltage generated in the resistor Rb by the current of the current source Idesat.
Therefore, Rb corresponds to a suitable example of the initial charge resistance in the claims. Further, the transistor Q2 corresponds to a suitable example of a detour switch in the claims.
As described above, according to the second embodiment, since the voltage value at the start of charging the capacitor Cdesat is set to a predetermined value, is the time when the load abnormality occurs before the IGBT 12 is turned on? It is possible to maintain the mask time at a constant value regardless of whether or not the mask time is turned on.

4. Specific examples
4.1 Specific Example 1
FIG. 12 shows a circuit diagram of the gate drive circuit 500, which is a specific embodiment of the invention. The gate driver 110 is the gate driver for driving the IGBT used in FIGS. 1, 2, 8 and 10, and may be configured by an IC or the like. The comparator IC1 is a comparator whose output is an open collector output. The voltage dividing value of the VCS by the resistors R1 and R2 and the capacitor C2 constitute the second reference voltage V _desat-2 of FIGS. 1, 3, 9, and 11. The resistance R4 and the capacitor C1 are a resistance and a capacitor for lowering the impedance of the input terminal of the comparator IC1 in order to increase the margin of malfunction. The capacitor C3 is a charging capacitor that creates a mask time. The diode D1 corresponds to the diode D1 in FIG. Also, R5 is. It is a resistance corresponding to Rb of FIG. 11 of the third embodiment.
The comparator IC1 has a configuration corresponding to the comparator CMP2 in FIG. 1 and the like and the transistor Q2. That is, the output transistor of the comparator IC1 is an open collector and plays the role of the transistor Q2 as shown in FIG. Therefore, in FIG. 12, the configuration corresponding to the transistor Q2 is not directly drawn.

ここで、ＩＧＢＴ１２が正常の範囲でＯＮ動作をしている場合の比較器ＩＣ１の非反転入力端子の電圧の最大値をＶ_ＳＯＮとすると、Ｖ_{ｄｅｓａｔ－２}は、Ｖ_ＳＯＮより高く設定する。Ｖ_ＳＯＮ
と、Ｖ_{ｄｅｓａｔ－２}とは下記の式（８）の関係である。 The diodes D2, D3, and D4 correspond to the diodes Ddesat of FIGS. 1, 3, 9, and 11. Here, the second reference voltage V _desat-2 of FIGS. 1, 3, 9, and 11 can be represented by the following equation (7) in FIG.

Here, assuming that the maximum value of the voltage of the non-inverting input terminal of the comparator IC1 when the IGBT 12 is operating in the normal range is V _SON , V _desert-2 is set higher than V _SON . V _SON
And V _desert-2 are related to the following equation (8).

ゲートドライバ１１０のＯＵＴ端子１１４の出力信号がＬｏｗのとき、ＩＧＢＴ１２はＯＦＦ動作している。このとき、ダイオードＤ２、Ｄ３、Ｄ４は逆バイアスされ、カットオフ状態である。従って、ダイオードＤ１は順バイアス状態で、比較器ＩＣ１の非反転入力端子の電圧は、第２の基準電圧_{Ｖｄｅｓａｔ－２}より高くなる。 However, VF _D1 is the total value of the forward voltage drop of the diode D1, and VF _D2-4 is the total value of the forward voltage drop of the diodes D2, D3, and D4. Further, the maximum value of the collector-emitter voltage when the IGBT 12 is in the ON operation in the normal range is defined as VCE _SAT .

When the output signal of the OUT terminal 114 of the gate driver 110 is Low, the IGBT 12 is in the OFF operation. At this time, the diodes D2, D3, and D4 are reverse-biased and are in a cutoff state. Therefore, the diode D1 is in the forward bias state, and the voltage of the non-inverting input terminal of the comparator IC1 is higher than the second reference voltage _Vdesat-2 .

Therefore, the output transistor of the comparator IC1 is turned off, but the transistor Q1 of the gate driver 110 is turned on, so that the current source Idea flows to the VEE via the transistor Q1 without charging the capacitor C3. .. As a result, in this state, the DESAT terminal voltage of the gate driver 110 does not rise and always maintains a voltage lower than the first reference voltage _Vdesat-1 , so that the comparator CMP1 does not output an abnormal signal (the output signal is High). Does not).
When the IGBT 12 is turned on and continues to operate normally, the collector-emitter voltage of the IGBT 12 is maintained below the saturation voltage V _SAT . Therefore, since the voltage of the non-inverting input terminal of the comparator _IC1 is lower than the voltage given by the above equation (8), the output transistor of the comparator IC1 is turned on. Therefore, the current source Idea of the gate driver 110 flows to the VEE via the output transistor of the comparator IC1 and does not charge the capacitor C3. Therefore, if the IGBT 12 maintains this state (ON state), no abnormal signal is output (the output signal does not become High).

Ｖ_{ＳＯＮＤＥＳＡＴ}が第２の基準電圧Ｖ_{ｄｅｓａｔ－２}を超えると、比較器ＩＣ１の出力トランジスタがＯＦＦ動作して、電流源ＩｄｅｓａｔがコンデンサＣ３に流れて、コンデンサＣ３の充電を開始する。充電によってコンデンサＣ３の端子間電圧が第１の基準電圧Ｖ_{ｄｅｓａｔ－１}に達すると比較器ＣＭＰ１が反転して異常信号を送出する（出力信号がＨｉｇｈとなる）。 When the IGBT 12 is in the ON operation and an abnormality occurs in the load and the IGBT 12 is in the Desert state (desaturation state), the collector-emitter voltage of the IGBT 12 rises. When the collector-emitter voltage of the IGBT 12 at this time is expressed as VCE _DESAT , the voltage V _SONDESAT of the non-inverting input terminal of the comparator IC1 is given by the following equation (9).

When V _SONDESAT exceeds the second reference voltage V _desert-2 , the output transistor of the comparator IC1 is turned off, the current source Idea flows to the capacitor C3, and charging of the capacitor C3 is started. When the voltage between the terminals of the capacitor C3 reaches the first reference voltage V _{desert-1 due} to charging, the comparator CMP1 is inverted and sends an abnormal signal (the output signal becomes High).

ＩＧＢＴ１２が、ＯＦＦ動作からＯＮ 動作に移行した直後に負荷異常等によりＩＧＢＴ１２のコレクタ－エミッタ間電圧が上記式（１０）のＶＣＥＤＥＴに達した場合には、ダイオードＤ２～Ｄ４の端子間の等価コンデンサ（図４のＤｄｅｓａｔ）に充電された高電圧（図４のＶｈｉ）によってコンデンサＣ１をマイナス方向に充電しようとするが、ダイオードＤ１が逆バイアスとなりマイナス方向への充電を阻止する。
従って、本発明の好適な実施例である図１２の回路は、ＩＧＢＴ１２のＤｅｓａｔ状態の検出から異常信号を送出するまでの遅延時間であるマスク時間を常に一定に保つことができる。 Therefore, the collector-emitter voltage VCE _DET for determining that the IGBT 12 is in the Desert state due to the load abnormality can be expressed by the following equation (10). The mask time Tmask from the determination that the IGBT 12 is in the Desert state due to the load abnormality until the abnormality signal is transmitted is expressed by the equation (5) already described.

If the collector-emitter voltage of the IGBT 12 reaches the VCEDET of the above equation (10) immediately after the IGBT 12 shifts from the OFF operation to the ON operation due to a load abnormality or the like, the equivalent capacitor between the terminals of the diodes D2 to D4 ( The capacitor C1 is attempted to be charged in the negative direction by the high voltage (Vhi in FIG. 4) charged in the Ddesat of FIG. 4, but the diode D1 becomes a reverse bias and prevents the charging in the negative direction.
Therefore, the circuit of FIG. 12, which is a preferred embodiment of the present invention, can always keep the mask time, which is the delay time from the detection of the Desert state of the IGBT 12 to the transmission of the abnormal signal, constant.

FIG. 13, shows experimental data of the mask time in the case of the Desat state about 20 μsec after the IGBT 12 is turned on and the mask time in the case of the Desat state immediately after the IGBT 12 is turned on. It is shown in FIG. The masking time was about 4.6 μsec, and there was almost no difference in the masking time between the two, and it was confirmed that a constant masking time was obtained. In both FIGS. 13 and 14, the horizontal axis represents the passage of time, and the vertical axis represents the voltage value or the current value.
In FIG. 13, a graph of each signal of the gate voltage, the collector current, and the collector-emitter voltage is drawn, and when the IGBT 12 shifts to the ON state, the gate voltage momentarily rises and the collector- The voltage between the emitters is dropping momentarily. Further, the collector current gradually increases from the time when the IGBT 12 shifts to the ON state.
In the graph of FIG. 13, an abnormality occurs 20 μsec after the IGBT 12 is turned on, and transmission of an abnormal signal is started 20 μsec after the mask time.
The graph of FIG. 14 is also a graph of the same type as the graph of FIG. 13, although the time scale is different, and the types of signals shown are also the same.
If the delay time from when the IGBT 12 receives the ON signal to when the IGBT actually turns ON is long, the mask time can be obtained by inserting the resistor Rd into the output of the comparator IC1 of FIG. 12 according to the delay time. Can be kept constant.

4.2 Specific Example 2
FIG. 15 shows a circuit diagram of the gate drive circuit 600, which is a specific embodiment of the invention. The difference from the gate drive circuit 500 in FIG. 14 is the connection position of the resistor R3.
In the gate drive circuit 500 of FIG. 14, the resistor R3 is provided so as to connect the positive power supply VCS and the anode side of the diode D1. On the other hand, in the gate drive circuit 600 of FIG. 15, the resistor R3 is provided so as to connect the output signal of the OUT terminal 114 and the anode side of the diode D1. Actually, as shown in FIG. 15, it is connected to the output signal of the buffer 120, not directly to the output signal of the OUT terminal 114. This is because the output signal of the buffer 120 has a larger output current, and it is considered that the drive of the IGBT 12 is hardly affected even if the resistor R3 is connected.
According to such a connection, when the IGBT 12 is in the OFF state, the non-inverting input terminal of the comparator IC1 can be maintained at Low, and it is considered that a circuit resistant to noise can be configured.
4.3 Specific Example 3

FIG. 16 shows a circuit diagram of the gate drive circuit 700, which is a specific embodiment of the invention. The difference from the gate drive circuit 600 of FIG. 15 is that the resistor R6 is provided. Due to the presence of the resistance R6, it is possible to construct a circuit having improved resistance to noise.

5. Effects, Modifications, etc. As described above, according to the present embodiment, it is possible to maintain the mask time after the occurrence of an abnormality at a constant value, and the resistance to noise is improved and stable. It is possible to provide a gate drive circuit capable of performing failure occurrence detection.

Further, the embodiment described above is an example as a means for realizing the present invention, and should be appropriately modified or changed depending on the configuration of the apparatus to which the present invention is applied and various conditions, and the present invention is the present embodiment. Is not limited to the above aspect. For example, in the above-described embodiment, the IGBT is mainly described as the power semiconductor switch to be driven, but it can also be applied to a gate drive circuit for driving another power semiconductor switch (for example, MOSFET). Further, in the embodiments and examples described above, the gate driver 110, the individual elements associated with the gate driver 110, and the circuit configuration have been described, but the gate driver 110 may be configured by using an IC, an LSI, or the like.

10, 110 Gate driver 12 IGBT
14, 114 OUT terminal 16, 116 Inverter 18, 118 Comparator 100, 200, 300, 400, 500, 600, 700 Gate drive circuit 120 Buffer 130, Time measurement circuit 132 Comparator C1, C2, C3 Capacitor CMP1, CMP2, IC1 Comparator D1, D2, D3, D4 Diode Rb, R1, R2, R3, R4, R5, R6 Resistance Q1, Q2 Transistor

Claims (6)

It is a gate drive circuit that drives a power semiconductor switch.
A comparison circuit that compares the collector-emitter voltage of the power semiconductor switch with a predetermined threshold voltage.
A time measurement circuit that starts time measurement after the power semiconductor switch is in the ON operation state and the comparison circuit detects that the collector-emitter voltage exceeds the threshold voltage.
Have,
An output circuit that outputs an abnormal signal indicating that the power semiconductor switch is in a desaturation state after the time measurement circuit measures the standby hold time.
A gate drive circuit characterized by being equipped with. The gate drive circuit according to claim 1.
In the comparison circuit, the collector current increases due to a predetermined failure or abnormality immediately after the power semiconductor switch shifts from the OFF operation to the ON operation, or under the condition that the power semiconductor switch is in a saturation state, and the power semiconductor switch A gate drive circuit, characterized in that the collector-emitter voltage is compared with a predetermined threshold voltage when the is in a desaturation state. The gate drive circuit according to claim 1 or 2 .
The time measurement circuit
A capacitor to which a charging current of a constant current value is applied, and a charging capacitor for setting the time until the terminal voltage of the capacitor rises with charging and reaches a predetermined voltage value as the standby hold time. ,
When the power semiconductor switch is in the saturation state and the collector-emitter voltage value is equal to or lower than the threshold voltage of the comparator, the current of the constant charging current value is bypassed and the charging capacitor is charged. A charging current bypass circuit that prevents current from flowing and sets the initial charge of the charging capacitor to 0,
Equipped with
When the comparison circuit detects that the power semiconductor switch is in the desaturation state and the collector-emitter voltage exceeds the threshold voltage of the comparison circuit, the charging current bypass circuit is interrupted and the initial charge of the capacitor is detected. A gate drive circuit characterized in that a constant charging current value flows into a capacitor from a state where is 0. The gate drive circuit according to claim 3 , which delays from outputting a signal for shifting the power semiconductor switch to be driven from the OFF state to the ON state until the power semiconductor switch actually turns ON. In the event of time
A first initial charge charging circuit that retains an initial charge in the charging capacitor and generates the standby hold time that is shorter by the time for charging the initial charge.
Equipped with
The output circuit is a gate drive circuit, characterized in that the time measuring circuit outputs an abnormal signal meaning that the power semiconductor switch is in a desaturation state after measuring the short standby hold time. The gate drive circuit according to claim 3 , which delays from outputting a signal for shifting the power semiconductor switch to be driven from the OFF state to the ON state until the power semiconductor switch actually turns ON. In the event of time
The charge current detour circuit is
A detour switch that bypasses the charging current,
The initial charge resistance directly connected to the detour switch,
Equipped with a series circuit of
Even when the charging current is bypassed by the charging current bypass circuit, the initial charge remains in the charging capacitor by the amount of the initial charge resistance, and the standby hold time shorter by the time of charging the initial charge is generated. ,
The output circuit is a gate drive circuit, characterized in that the time measuring circuit outputs an abnormal signal meaning that the power semiconductor switch is in a desaturation state after measuring the short standby hold time. The gate drive circuit according to any one of claims 1 to 5 .
A diode whose cathode terminal is connected to the comparison circuit and whose anode terminal is connected to the collector terminal of the power semiconductor switch.
Equipped with
The comparison circuit is a gate drive circuit characterized in that the collector voltage of the power semiconductor switch is detected via the diode.

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