JP7001463B2 - Load drive device, semiconductor device and motor driver device - Google Patents

Description

The present invention relates to a load drive device, and a semiconductor device and a motor driver device related thereto.

The hard disk device is provided with a spindle motor (SPM) for rotationally driving a magnetic disk and a voice coil motor (VCM) used for moving the magnetic head. The SPM is generally PWM (pulse width modulation) driven, and the VCM is also PWM driven. Often.

FIG. 21 shows the connection relationship between the SPM 910 as a three-phase DC motor and the SPM driver 920 provided in the hard disk device. The SPM910 includes U-phase, V-phase and W-phase coils 910u, 910v and 910w, and the SPM driver 920 includes half-bridge circuits 921u, 921v and 921w for U-phase, V-phase and W-phase, and a drive circuit 922. Be prepared. Then, one end of each coil is connected to the corresponding half-bridge circuit via the corresponding output terminals (930u, 930v, 930w). The drive circuit 922 can PWM drive the SPM910 by turning on and off each output transistor of the corresponding half-bridge circuit according to the PWM signals of the U phase, the V phase and the W phase provided from the control circuit (not shown). At this time, a technique for preventing the pair of output transistors in each half bridge from being turned on at the same time is also used.

WO2009 / 150794

It is known that when the voltage at the output terminals (930u, 930v, 930w) connected to the SPM910 is suddenly changed when the SPM910 is PWM-driven, the high frequency component in the steep voltage change increases the noise of the entire hard disk device. Has been done. Therefore, in order to reduce such noise as much as possible, in a hard disk device, generally, the voltage of the output terminal is gently changed at a desired slew rate (for example, several tens of V / μsec) in the turn-on operation and the turn-off operation of the output transistor. Slew rate control is required.

In addition, not only for hard disk devices, but also for any load drive device, if the voltage at the output terminal connected to any load is suddenly changed, the high frequency component in the sudden voltage change becomes noise in other circuit operations. It may have an adverse effect, and in consideration of this, the above-mentioned slew rate control may be required.

However, in the turn-off operation in the conventional configuration, the slew rate control may not work accurately depending on the load current supplied to the load (the reason will be described in detail later).

An object of the present invention is to provide a load drive device that contributes to suppressing a steep voltage change at an output terminal connected to a load, and a semiconductor device and a motor driver device related to the load drive device.

The load drive device according to the present invention includes a first output transistor and a second output transistor connected in series to each other, and a drive unit for turning each output transistor on and off, and the first output transistor and the said A load drive device that supplies a load current to a load via an output terminal provided between the second output transistor and a target output transistor that is either one of the first output transistor and the second output transistor. A monitoring circuit that is connected to the control electrode of the above and can output a forced off signal based on the voltage level in the control electrode of the target output transistor, and when the forced off signal is received from the monitoring circuit, the target output transistor is forced. The monitoring circuit includes a sense transistor, and the control electrode of the target output transistor has a sense transistor so that the target output transistor is turned from an on state to an off state by the drive unit. When the voltage is controlled, the sense transistor is also configured to go from the on state to the off state, receives the turn-off of the sense transistor, outputs the forced off signal, and the drive unit receives the forced off signal. Upon receiving the output, the first output transistor and the other output transistor of the second output transistor are allowed to be turned on, and the monitoring circuit has the control electrode of the sense transistor and the control electrode of the target output transistor. It further has an adjustment resistance inserted between them, and when the drive unit controls the voltage at the control electrode of the target output transistor in the direction from the on state to the off state of the target output transistor, the adjustment resistance is used. By supplying a predetermined current, the turn-off timing of the sense transistor is delayed by the voltage drop of the adjusting resistor as compared with the case where there is no adjusting resistor.

Specifically, for example, when the target output transistor is switched from the on state to the off state, the drive unit includes the off current source and the target output transistor in the direction in which the target output transistor moves from the on state to the off state. A predetermined off-current current may be passed between the control electrodes and the target output transistor, and the target output transistor may be directed from the on-state to the off-state over a period of time corresponding to the magnitude of the off-current.

Specifically, for example, each of the target output transistor and the sense transistor is an electric field effect transistor having a gate as the control electrode, and the target output transistor and the source of the sense transistor are commonly connected to each other. In the process of reducing the gate-source voltage of the target output transistor from the on state to the off state by the drive unit, the gate-source voltage of the target output transistor becomes the gate threshold of the sense transistor. When the sense transistor is kept on even when it is reduced to a voltage, and then the sense transistor is turned off when the gate-source voltage of the target output transistor is further reduced by the voltage drop of the adjustment resistor. good.

Alternatively, for example, each of the target output transistor and the sense transistor is an IGBT having a gate as the control electrode, and the target output transistor and the emitters of the sense transistor are commonly connected to each other, and the target output is provided by the drive unit. Even if the gate-emitter voltage of the target output transistor is reduced to the gate threshold voltage of the sense transistor in the process of reducing the gate-emitter voltage of the target output transistor from the on state to the off state of the transistor. The sense transistor may be turned off when the on state of the sense transistor is maintained and then the gate-emitter voltage of the target output transistor is further reduced by the voltage drop of the adjustment resistor.

Further, for example, the target output transistor and the sense transistor may have a gate threshold voltage common to each other.

Further, for example, the monitoring circuit may output the forced off signal after a predetermined time has elapsed from the turn-off of the sense transistor.

Further, for example, it is preferable to further provide a control circuit for controlling the drive unit so that the target output transistor is repeatedly turned on and off in the load drive device.

Further, for example, in the load drive device, the first output transistor and the second output transistor are each set as the target output transistor, and the monitoring circuit and the monitoring circuit are used for each of the first output transistor and the second output transistor. A forced off circuit may be provided.

The semiconductor device according to the present invention is a semiconductor device that forms the load drive device, and the load drive device is characterized by being formed by using an integrated circuit.

The first motor driver device according to the present invention is provided with the load driving device, and is characterized in that the load current is supplied to the motor as the load.

The second motor driver device according to the present invention includes the load drive device, and the load drive device is an SPM driver that drives a spindle motor that rotates a magnetic disk of the magnetic disk device as the load. ..

The third motor driver device according to the present invention includes the load drive device, and the load drive device is a VCM that drives a voice coil motor that moves the magnetic head of the magnetic disk device in the radial direction of the magnetic disk as the load. It is characterized by being a driver.

According to the present invention, it is possible to provide a load drive device that contributes to suppressing a steep voltage change at an output terminal connected to a load, and a semiconductor device and a motor driver device related to the load drive device. ..

It is a block diagram of the block of the load drive device which concerns on embodiment of this invention. It is a partial block diagram of the load drive device according to the reference embodiment which concerns on this invention. It is explanatory drawing of the turn-on operation of the output transistor on the low-side side with respect to the reference embodiment concerning this invention. It is explanatory drawing of the turn-off operation of the output transistor on the low-side side with respect to the reference embodiment concerning this invention. It is a figure which shows the input / output signal relation of a dead time circuit. FIG. 3 is an explanatory diagram of a turn-off operation of an output transistor when a load is driven by a constant current according to a reference embodiment according to the present invention. It is a figure which shows the waveform of each part at the time of the turn-off operation of an output transistor at the time of driving a load by a constant current according to the reference embodiment which concerns on this invention (simplification model). FIG. 3 is an explanatory diagram of a turn-off operation of an output transistor when a load is driven by a constant current according to a reference embodiment according to the present invention. It is a figure which shows the waveform of each part at the time of the turn-off operation of an output transistor at the time of driving a load by a constant current according to the reference embodiment which concerns on this invention (load current: large). It is a figure which shows the waveform of each part at the time of the turn-off operation of an output transistor at the time of driving a load by a constant current according to the reference embodiment which concerns on this invention (load current: small). It is a partial block diagram of the load drive device which concerns on 1st Embodiment of this invention. According to the first embodiment of the present invention, it is a figure which shows the waveform of each part at the time of the turn-off operation of an output transistor at the time of driving a load by a constant current (load current: large). According to the first embodiment of the present invention, it is a figure which shows the waveform of each part at the time of the turn-off operation of an output transistor at the time of driving a load by a constant current (load current: small). It is a partial block diagram of the load drive device which concerns on 2nd Embodiment of this invention. It is an internal circuit diagram of the constant current circuit which concerns on 4th Embodiment of this invention. It is a schematic block diagram which concerns on the mechanism of the hard disk apparatus which concerns on 6th Embodiment of this invention. It is an electric schematic block diagram of the hard disk apparatus which concerns on 6th Embodiment of this invention, and the external perspective view of the driver IC mounted on the hard disk apparatus. It is a figure which shows the internal structure of the SPM (spindle motor) and the SPM driver, and the connection relationship between them, according to the 6th Embodiment of this invention. It is a figure which shows the internal structure of the VCM (voice coil motor) and the VCM driver, and the connection relationship between them, according to the 6th Embodiment of this invention. It is a partial block diagram of the load drive device which concerns on 7th Embodiment of this invention. It is a figure which shows the connection relation of SPM (spindle motor) and SPM driver which concerns on the prior art.

Hereinafter, examples of embodiments of the present invention will be specifically described with reference to the drawings. In each of the referenced figures, the same parts are designated by the same reference numerals, and duplicate explanations regarding the same parts will be omitted in principle. In this specification, for the sake of simplification of description, by describing a symbol or a code that refers to an information, a signal, a physical quantity, a member, etc., the name of the information, a signal, a physical quantity, a member, etc. corresponding to the symbol or the code is given. May be omitted or abbreviated.

FIG. 1 shows a block diagram of a load drive device 1 according to an embodiment of the present invention. The load drive device 1 includes a high-side side output transistor TrH and a low-side side output transistor TrL connected in series with each other, and also includes a control circuit 20, an output terminal OUT, and an output block 10 provided for each output transistor. , Equipped with. Each component of the load drive device 1 can be formed in the form of a semiconductor integrated circuit, and the semiconductor integrated circuit is enclosed in a housing (package) made of resin to form a semiconductor device. good.

A half-bridge circuit is composed of output transistors TrH and TrL. In the half-bridge circuit, the output transistors TrH and TrL are configured as N-channel MOSFETs (metal-oxide-semiconductor field-effect transistors), and the drain of the output transistor TrH has a predetermined positive DC voltage value. The power supply voltage line VPWR is connected to the power supply voltage line LN_VPWR to which the power supply voltage VPWR is applied, and the source of the output transistor TrL is connected to the ground. The source of the output transistor TrH and the drain of the output transistor TrL are commonly connected to the output terminal OUT. The ground refers to a reference potential point having a reference potential of 0 V (zero volt). In the present embodiment, the potential refers to the potential with reference to the ground, and the voltage described without particularly indicating the reference refers to the potential difference from the ground. The ground may be read as the ground line. In the present embodiment, the line means a wiring composed of a conducting wire or a conductor having a predetermined pattern shape.

Each output block 10 includes a drive circuit 11, a condition monitoring circuit 12, and a forced off circuit 13. The output block 10 for the output transistor TrH is particularly referred to by reference numeral 10H, and the output block 10 for the output transistor TrL is particularly referred to by reference numeral 10L.

The drive circuit 11 in the output block 10H controls the on / off of the output transistor TrH by controlling the gate voltage (gate potential) of the output transistor TrH according to the control signal supplied from the control circuit 20. The control of the gate voltage of the output transistor TrH is also the control of the gate-source voltage of the output transistor TrH.

For any FET including the output transistors TrH and TrL, the gate-source voltage refers to the potential of the gate of the FET as seen from the potential of the source of the FET. Hereinafter, for any FET including the output transistors TrH and TrL, the gate-source voltage may be abbreviated as voltage _VGS , or may be simply referred to as _VGS .

The state monitoring circuit 12 in the output block 10H detects the state of the output transistor TrH by monitoring the voltage level of the gate voltage of the output transistor TrH, and the voltage _VGS of the output transistor TrH is the gate threshold voltage V of the output transistor TrH. When the voltage is less than _TH (gate cutoff voltage) or less than the gate threshold voltage _VTH (gate cutoff voltage) of the output transistor TTH (gate cutoff voltage) or less, wait for the _elapse of the predetermined time _tDT for the dead time and then high. The level status detection signal is output, and if not, the low level status detection signal is output. The gate threshold voltage VTH of the output transistor _TrH and the predetermined voltage _VTH'have a positive predetermined voltage value (for example, 1V). In the present embodiment, of the high level and the low level, the high level has a higher potential than the low level.

The state detection signal output from the state monitoring circuit 12 of the output block 10H is transmitted to the forced off circuit 13 of the output block 10H. When the forced off circuit 13 of the output block 10H receives a high-level state detection signal, the output transistor TrH is forcibly turned off by short-circuiting the gate and the source of the output transistor TrH.

The transistor to be controlled and the state monitoring of the output block 10H is the transistor TrH, whereas the transistor to be controlled and the state monitoring of the output block 10L is the transistor TrL. Except for this point, the operation of the output block 10L is the same as the operation of the output block 10H. That is, the drive circuit 11 in the output block 10L controls the on / off of the output transistor TrL by controlling the gate voltage (gate potential) of the output transistor TrL according to the control signal supplied from the control circuit 20. The control of the gate voltage of the output transistor TrL is also the control of the gate-source voltage of the output transistor TrL.

The state monitoring circuit 12 in the output block 10L detects the state of the output transistor TrL by monitoring the voltage level of the gate voltage of the output transistor TrL, and the voltage _VGS of the output transistor TrL is the gate threshold voltage V of the output transistor TrL. When the voltage is less than _TH (gate cutoff voltage) or less than the gate threshold voltage _VTH (gate cutoff voltage) of the output transistor TTH (gate cutoff voltage) or less, wait for the _{elapse of the predetermined time tDT for} the dead time and then high. The level status detection signal is output, and if not, the low level status detection signal is output. The gate threshold voltage _VTH of the output transistor TrL and the predetermined voltage _VTH'have a positive predetermined voltage value (for example, 1V).

The state detection signal output from the state monitoring circuit 12 of the output block 10L is transmitted to the forced off circuit 13 of the output block 10L. When the forced off circuit 13 of the output block 10L receives a high level state detection signal, the output transistor TrL is forcibly turned off by short-circuiting the gate and the source of the output transistor TrL.

The control circuit 20 outputs a control signal specifying a period during which the output transistor TrH is turned on and a period during which the output transistor TrH is turned off to the drive circuit 11 of the output block 10H, and also sets a period during which the output transistor TrL is turned on and a period during which the output transistor TrL is turned off. By outputting the designated control signal to the drive circuit 11 of the output block 10L, the on / off of the output transistors TrH and TrL is specified.

The control circuit 20 does not create and output a control signal that overlaps the period in which the output transistor TrH is turned on and the period in which the output transistor TrL is turned on, but the output transistors TrH and TrL are turned on at the same time. The output signal of the state monitoring circuit 12 of one output block is transmitted to the drive circuit 11 of the other output block in order to surely prevent the above. It should be noted that this transmission may be performed through the control circuit 20.

That is, in detail, the drive circuit 11 of the output block 10H controls the on / off of the output transistor TrH based on the control signal from the control circuit 20 and the state detection signal from the state monitoring circuit 12 of the output block 10L. In principle, the control signal from the control circuit 20 is followed, but the output transistor TrH is kept off while the low-level state detection signal is output from the state monitoring circuit 12 of the output block 10L, and the output block 10L The output transistor TrH is allowed to be turned on only when a high-level state detection signal is output from the state monitoring circuit 12 (that is, only when a reliable off of the output transistor TrL is guaranteed). Works like this. This ensures that the output transistors TrH and TrL are not turned on at the same time.

Similarly, the drive circuit 11 of the output block 10L controls the on / off of the output transistor TrL based on the control signal from the control circuit 20 and the state detection signal from the state monitoring circuit 12 of the output block 10H. In principle, the control signal from the control circuit 20 is followed, but the output transistor TrL is kept off while the low-level state detection signal is output from the state monitoring circuit 12 of the output block 10H, and the state monitoring of the output block 10H is performed. Operates to allow the output transistor TrL to be turned on only when a high-level state detection signal is output from the circuit 12 (that is, only when the output transistor TrH is guaranteed to be surely turned off). do.

When a control signal instructing to turn on the turned-off output transistor TrH is output from the control circuit 20, a high-level state detection signal is output from the state monitoring circuit 12 of the output block 10L. On the condition that (that is, on the condition that the output transistor TrL is surely turned off), the state detection signal output from the state monitoring circuit 12 is forcibly set to a low level in the output block 10H. The low level of the state detection signal shall be maintained at least until the voltage _VGS of the output transistor _TrH is sufficiently high above the gate threshold voltage VTH of the output transistor TrH. In the output block 10H, when the state detection signal output from the state monitoring circuit 12 is low level, the short circuit between the gate and the source of the output transistor TrH by the forced off circuit 13 is eliminated, and the output transistor TrH is turned by the drive circuit 11. It is possible to turn it on.

Similarly, when a control signal instructing to turn on the turned-off output transistor TrL is output from the control circuit 20, a high-level state detection signal is output from the state monitoring circuit 12 of the output block 10H. On condition that the output transistor TrH is surely turned off (that is, on condition that the output transistor TrH is surely turned off), the state detection signal output from the state monitoring circuit 12 is forcibly set to a low level in the output block 10L. The low level of this state detection signal shall be maintained at least until the voltage _VGS of the output transistor TrL is sufficiently high above the gate threshold voltage _VTH of the output transistor TrL. In the output block 10L, when the state detection signal output from the state monitoring circuit 12 is low level, the short circuit between the gate and the source of the output transistor TrL by the forced off circuit 13 is eliminated, and the output transistor TrL is turned by the drive circuit 11. It is possible to turn it on.

The output terminal OUT is connected to one end of the load LD. The current supplied to the load LD via the output terminal OUT is represented by I _OUT . When the output transistor TrH is on, the current I OUT flows from the power supply voltage line LN_VPWR toward the load LD via the output transistor TrH and the output terminal OUT, and when the output transistor TrL is on, the current I _OUT flows from the load LD toward the ground. The current I _OUT flows through the terminal OUT and the output transistor TrL. To achieve this, it is assumed that the other end of the load LD is connected to a circuit not shown in FIG.

For example, a half-bridge circuit (TrH, TrL) shown in FIG. 1 and a half-bridge circuit (not shown) are provided in the load drive device 1, and a load LD is connected between the two half-bridge circuits to make the load LD full. A bridge circuit may be configured. At this time, for example, the control circuit 20 may switch drive each output transistor of the full bridge circuit including the output transistors TrH and TrL so that a desired current is supplied to the load LD. This switching drive may be PWM (pulse width modulation) drive.

Hereinafter, the details, applications, deformation techniques, etc. of the above-mentioned devices and circuits will be described in the plurality of examples. The above-mentioned matters in the present embodiment are applied to the respective examples described later as long as there is no contradiction. Further, as long as there is no contradiction, the matters described in any of the plurality of examples described below may be applied to any other example (that is, any 2 of the plurality of examples). It is also possible to combine the above examples). In the following, specific numerical values such as resistance value and current value are given for the purpose of embodying the explanation, but these numerical values are merely examples and can be changed in various ways as a matter of course.

[Reference Example]
First, a reference embodiment will be described. FIG. 2 is a partial configuration diagram of the load drive device 1A, which is the load drive device 1 of the reference embodiment. The load drive device 1A is provided with an output block 10LA as an output block 10L for the output transistor TrL. The output block 10LA is provided with a drive circuit 11A, a condition monitoring circuit 12A, and a forced off circuit 13A as the drive circuit 11, the condition monitoring circuit 12, and the forced off circuit 13 of FIG.

The drive circuit 11A includes constant current circuits 31 and 32. FIG. 2 shows an equivalent circuit of the drive circuit 11A. The condition monitoring circuit 12A includes a resistor 33, a dead time circuit 34, and a sense transistor Trs formed as an N-channel MOSFET. The forced off circuit 13A includes a forced off transistor Trfo formed as an N-channel type MOSFET.

The line connected to the gate of the output transistor TrL is referred to as a gate line LG. The parasitic capacitance between the gate and drain of the output transistor TrL is represented by Cgd, and the parasitic capacitance between the gate and source of the output transistor TrL is represented by Cgs.

The configuration and operation of the output block 10LA, the connection relationship between the output block 10LA and the output transistor TrL, and the like will be described.

The constant current circuit 31 directs the constant current I1 toward the gate line LG as shown in FIG. 3 in the turn-on operation of transitioning the state of the output transistor TrL from the off state to the on state based on the control signal from the control circuit 20. It is a circuit to supply. The constant current circuit 32 draws the constant current I2 from the gate line LG as shown in FIG. 4 in the turn-off operation of transitioning the state of the output transistor TrL from the on state to the off state based on the control signal from the control circuit 20. It is a circuit. Therefore, in the turn-on operation, the state of the output transistor TrL changes from the off state to the on state over a time corresponding to the magnitude of the constant current I1, and in the turn-off operation, the time corresponding to the magnitude of the constant current I2. The state of the output transistor TrL changes from the on state to the off state.

The gate of the sense transistor Trs and the drain of the forced off transistor Trfo are connected to the gate line LG, and each source of the sense transistor Trs and the forced off transistor Trfo is connected to the source (and thus ground) of the output transistor TrL. A positive DC voltage VA is applied to one end of the resistor 33, and the other end of the resistor 33 is connected to the drain of the sense transistor Trs. Therefore, the drain voltage level (drain potential) of the sense transistor Trs becomes a high level having a DC voltage VA when the sense transistor Trs is off, and is sufficiently higher than the DC voltage VA when the sense transistor Trs is on. It becomes a low level.

The dead time circuit 34 has an input terminal D1 and an output terminal D2. The drain voltage of the sense transistor Trs is input to the input terminal D1 of the dead time circuit 34, and the dead time circuit 34 outputs a state detection signal from the output terminal D2 based on the voltage level of the input terminal D1. As shown in FIG. 5, the dead time circuit 34 outputs a low level state detection signal when the input voltage level of the input terminal D1 is low level, and the input voltage level of the input terminal D1 switches from low level to high level. Then, when a predetermined time t _DT called a dead time elapses from the switching timing, the voltage level of the state detection signal is switched from the low level to the high level.

The output terminal D2 of the dead time circuit 34 is connected to the gate of the forced off transistor Trfo. That is, the state detection signal from the dead time circuit 34 is supplied to the gate of the forced off transistor Trfo. The forced off transistor Transo is turned on when the state detection signal is high level and turned off when the state detection signal is low level. Therefore, when the state detection signal becomes high level, the forced off transistor Trfo is turned on, short-circuiting the gate and source of the output transistor TrL, and the output transistor TrL is forcibly turned off. The forced off transistor Trfo may be any switching element that is turned on only when the state detection signal is at a high level to short-circuit between the gate and the source of the output transistor TrL.

The dead time circuit 34 returns the voltage level of the state detection signal to the low level after a certain period of time has elapsed after switching the voltage level of the state detection signal from the low level to the high level, regardless of the input voltage level of the input terminal D1. It may be a circuit, or it may be a circuit that maintains the voltage level of the state detection signal at a high level until the next turn-on operation of the output transistor TrL is performed. At least, the dead time circuit 34 turns off the forced off transistor Trfo by setting the voltage level of the state detection signal to a low level regardless of the input voltage level of the input terminal D1 when the next turn-on operation of the output transistor TrL is performed. To maintain.

The sense transistor Trs and the output transistor TrL are semiconductor elements formed with the same structure in order to accurately detect whether the gate-source voltage of the output transistor TrL is equal to or lower than the gate threshold voltage _VTH of the output transistor TrL. It is assumed that the gate threshold voltage VTH of the sense transistor Trs and the gate threshold voltage _VTH of the output transistor _TrL are in agreement with each other. However, the match here is a concept including an error.

With reference to FIG. 6, a detailed description of the behavior of the load drive device 1A in the turn-off operation will be added. Here, it is assumed that a constant current drive of the load LD is performed in which a constant current is supplied to the load LD as a current I _OUT in the direction toward the output terminal OUT via the load LD. Then, the output is output starting from a state in which the output transistor TrH is turned off and the output transistor TrL is turned on and the current I _OUT , which is a constant current, flows from the load LD to the ground via the output terminal OUT and the output transistor TrL. Consider that the turn-off operation of the transistor TrL is performed.

See FIG. 7. FIG. 7 shows the voltage waveform 310 of the output terminal OUT, the voltage waveform 320 of the gate line LG, the voltage waveform 331 at the input terminal D1 of the dead time circuit 34, and the dead time circuit 34 when the turn-off operation is performed. It represents the voltage waveform 332 at the output terminal D2 of. In the simplified model, the presence of parasitic capacitance Cgd is ignored. In the following, the drain-source resistance of any FET including the output transistor _TrL may be referred to by the reference numeral RDS. It is assumed that each timing comes in the order of timing t0, t1, t2, t3, and t4 along with the progress of time.

The timing t0 is the timing before the start of the turn-off operation for the output transistor TrL. At the timing t0, a voltage V _ON at which the drain-source resistance RDS of the output transistor _TrL becomes sufficiently low is applied to the gate line LG as a gate voltage, and here, the voltage V _ON is 5 V (volt). do. The voltage V _ON is sufficiently higher than the gate threshold voltage _VTH of the output transistor TrL and the sense transistor Trs. At the timing t0, the resistance R _DS is sufficiently low, so that the voltage of the output terminal OUT is approximately 0 V.

The turn-off operation for the output transistor TrL is started from the timing t1. That is, the current I2 flows from the gate line LG toward the constant current circuit 32 so that the accumulated charge of the parasitic capacitance Cgs decreases from the timing t1, the voltage of the gate line LG gradually decreases, and the gate line LG reaches the timing t3. The voltage matches the gate threshold voltage _VTH of the sense transistor Trs. Then, at the timing t3, the sense transistor Trs functioning as a switch is switched from on to off, and the voltage level of the input terminal D1 of the dead time circuit 34 is switched from the low level to the high level. After that, the voltage level of the output terminal D2 of the dead time circuit 34 is switched from the low level to the high level at the timing t4 when the predetermined time _tDT has elapsed from the timing t3, and the voltage of the gate line LG is turned on by the turn-on of the forced off transistor Trfo. The level is forcibly lowered to substantially 0V.

From timing t1 to timing t3 via timing t2, the drain-source resistance RDS of the output transistor _TrL gradually increases as the voltage level of the gate line LG decreases, resulting in a gradual increase. , The voltage level of the output terminal OUT is also gradual, but gradually increases. Then, at the timing t3 at which the voltage of the gate line LG coincides with the gate threshold voltage _VTH , the resistance _RDS rapidly increases, and the voltage of the output terminal OUT goes toward (VPWR + Vf). When the resistance R _DS becomes sufficiently large, substantially all of the current I _OUT as a constant current flows into the power supply voltage line LN_VPWR through the diode DI connected in parallel to the output transistor TrH on the high side side, as shown in FIG. .. Vf represents the forward voltage of the diode DI. The diode DI has a forward direction from the source of the output transistor TrH toward the drain. The diode DI may be a parasitic diode of the output transistor TrH.

In the simplified model corresponding to FIG. 7, the existence of the parasitic capacitance Cgd is ignored as described above, but the actual voltage change of the gate line LG is affected by the existence of the parasitic capacitance Cgd.

With reference to FIG. 9, each signal waveform in the turn-off operation in consideration of the presence of the parasitic capacitance Cgd will be described. In each of the following simulations, it is assumed that the existence of the parasitic capacitance Cgd is taken into consideration unless otherwise specified. The solid line waveform 410, the solid line waveform 420, the solid line waveform 431, and the broken line waveform 432 in FIG. 9 are the voltage waveform of the output terminal OUT, the voltage waveform of the gate line LG, and the input terminal D1 of the dead time circuit 34, respectively, in the first simulation. The voltage waveform and the voltage waveform at the output terminal D2 of the dead time circuit 34 are shown.

In the first simulation and each simulation described later, it is assumed that the load LD is driven by a constant current, and the output transistor TrH is turned off and the output transistor TrL is turned on, and the current I _OUT , which is a constant current, is loaded. The behavior when the turn-off operation of the output transistor TrL is performed is simulated starting from the state of flowing from the LD to the ground via the output terminal OUT and the output transistor TrL. In the first simulation and each simulation described later, the power supply voltage VPWR is 12V, the forward voltage of the diode DI described above is 0.6V, the voltage V _ON described above is 5V, and the gate threshold voltage of the sense transistor Trs. It was assumed that the VTH was _0.87V . Further, in the first simulation and each simulation described later, it is assumed that the drain-source resistance RDS of the output transistor TrL is _60Ω when the voltage of the gate line LG is 0.97V. Then, in the first simulation, it was assumed that the current I _OUT was 100 mA.

In the first simulation, the timing t0 is the timing before the start of the turn-off operation with respect to the output transistor TrL. At the timing t0, the voltage VON at which the drain-source resistance RDS of the output transistor _TrL becomes sufficiently low (for example, 0.2Ω) is applied to the gate line LG as the gate voltage, and the voltage of the _output terminal OUT is It is approximately 0V.

In the first simulation, the turn-off operation for the output transistor TrL is started from the timing t1. That is, in the first simulation, the current I2 flows from the gate line LG toward the constant current circuit 32 so that the accumulated charge of the parasitic capacitance Cgs decreases from the timing t1, the voltage of the gate line LG gradually decreases, and the timing t2 At timing t3, the voltage of the gate line LG coincides with the gate threshold voltage _VTH of the sense transistor Trs. Then, at the timing t3, the sense transistor Trs functioning as a switch is switched from on to off, and the voltage level of the input terminal D1 of the dead time circuit 34 is switched from the low level to the high level. After that, the voltage level of the output terminal D2 of the dead time circuit 34 is switched from the low level to the high level at the timing t4 when the predetermined time _tDT has elapsed from the timing t3, and the voltage of the gate line LG is turned on by the turn-on of the forced off transistor Trfo. The level is forcibly lowered to substantially 0V.

In the first simulation, the drain-source resistance RDS of the output transistor _TrL gradually increases as the voltage level of the gate line LG decreases from the timing t1 to the timing t3 via the timing t2. As a result, the voltage level of the output terminal OUT also gradually rises. At this time, when the voltage of the gate line LG drops to near the gate threshold voltage of the output transistor _TrL , the degree of increase in the resistance RDS with respect to the voltage drop of the gate line LG increases. Since the current flowing through the parasitic capacitance Cgd when the voltage level of the output terminal OUT rises acts to prevent the voltage drop of the gate line LG due to the flow of the current I2, the gate line LG in the process of raising the voltage level of the output terminal OUT The voltage drop rate of is correspondingly small. In the first simulation, at a certain timing t2 between the timings t1 and t3, the voltage of the gate line LG is 0.97V, and at this time, the drain-source resistance RDS of the output transistor TrL is _60Ω , and the result is , The voltage of the output terminal OUT is 6V.

Then, after the timing t3, the resistance R _DS of the output transistor TrL becomes sufficiently large, and substantially all of the current I _OUT as a constant current passes through the diode DI connected in parallel to the output transistor TrH on the high side side. It will flow into the power supply voltage line LN_VPWR.

As described above, under I _OUT = 100 mA assumed in the first simulation, the slew rate control that raises the voltage of the output terminal OUT at the slew rate according to the magnitude of the constant current I2 in the turn-off operation is as desired. It will be realized.

However, the slew rate control may not work as desired depending on the magnitude of the current I _OUT . This will be described with reference to FIG. The solid line waveform 460, the solid line waveform 470, the solid line waveform 481, and the broken line waveform 482 in FIG. 10 are the voltage waveform of the output terminal OUT, the voltage waveform of the gate line LG, and the input terminal D1 of the dead time circuit 34, respectively, in the second simulation. The voltage waveform and the voltage waveform at the output terminal D2 of the dead time circuit 34 are shown. In the second simulation, it was assumed that the current I _OUT was 10 mA.

In the second simulation, the timing t0 is the timing before the start of the turn-off operation with respect to the output transistor TrL. At the timing t0, the voltage VON at which the drain-source resistance RDS of the output transistor _TrL becomes sufficiently low (for example, 0.2Ω) is applied to the gate line LG as the gate voltage, and the voltage of the _output terminal OUT is It is approximately 0V.

In the second simulation, the turn-off operation for the output transistor TrL is started from the timing t1. That is, in the second simulation, the current I2 flows from the gate line LG toward the constant current circuit 32 so that the accumulated charge of the parasitic capacitance Cgs decreases from the timing t1, the voltage of the gate line LG gradually decreases, and the timing t3 In', the voltage of the gate line LG matches the gate threshold voltage _VTH of the sense transistor Trs. Then, at the timing t3', the sense transistor Trs functioning as a switch is switched from on to off, and the voltage level of the input terminal D1 of the dead time circuit 34 is switched from the low level to the high level. After that, the voltage level of the output terminal D2 of the dead time circuit 34 switches from low level to high level at the timing _t4'when the predetermined time tDT has elapsed from the timing t3', and the gate line LG is turned on by the forced off transistor Trfo. The voltage level of is forcibly lowered to substantially 0V.

In the second simulation, the voltage of the gate line LG drops to the gate threshold voltage _VTH (here 0.87 V) of the sense transistor Trs at the timing t3', but the current I _OUT is 10 mA, which is smaller than that of the first simulation. Therefore, the voltage level of the output terminal OUT at the timing t3'is much smaller than the voltage level of the output terminal OUT at the timing t3 of the first simulation. For example, if the drain-source resistance RDS of the output transistor TrL when the voltage of the gate line LG is _0.87V is 100Ω, the turn-off timing (t3') of the sense transistor Trs in the second simulation. The voltage of the output terminal OUT at is only 1V.

As a result, the voltage of the output terminal OUT is not so large even at the timing _t4'after the predetermined time tDT has passed from the turn-off timing (t3') of the sense transistor Trs, and the voltage of the gate line LG is 0V at the timing t4'. When the voltage is sharply lowered, the voltage of the output terminal OUT rises sharply from a relatively low voltage (for example, 2V) to the vicinity of the power supply voltage VPWR, and the desired slew rate control cannot be realized.

[First Example]
Next, the first embodiment will be described. FIG. 11 is a partial configuration diagram of the load drive device 1B, which is the load drive device 1 of the first embodiment. The load drive device 1B is provided with an output block 10LB as an output block 10L for the output transistor TrL. The output block 10LB is provided with a drive circuit 11B, a condition monitoring circuit 12B, and a forced off circuit 13B as the drive circuit 11, the condition monitoring circuit 12, and the forced off circuit 13 of FIG.

As described above, the line connected to the gate of the output transistor TrL is referred to as a gate line LG, and the parasitic capacitance between the gate and drain of the output transistor TrL is represented by Cgd and the parasitic capacitance between the gate and source of the output transistor TrL. The capacitance is expressed in Cgs.

The configuration and operation of the output block 10LB, the connection relationship between the output block 10LB and the output transistor TrL, and the like will be described.

The drive circuit 11B is the same as the drive circuit 11A in the reference embodiment, and includes constant current circuits 31 and 32 (the equivalent circuit of the drive circuit 11B is shown in FIG. 11). That is, in the turn-on operation of transitioning the state of the output transistor TrL from the off state to the on state based on the control signal from the control circuit 20, the constant current circuit 31 has the same constant current I1 as that shown in FIG. Is supplied toward the gate line LG. The constant current circuit 32 is constant from the gate line LG in the turn-off operation of transitioning the state of the output transistor TrL from the on state to the off state based on the control signal from the control circuit 20 in the same manner as that shown in FIG. The current I2 is drawn. Therefore, in the turn-on operation, the state of the output transistor TrL changes from the off state to the on state over a time corresponding to the magnitude of the constant current I1, and in the turn-off operation, the time corresponding to the magnitude of the constant current I2. The state of the output transistor TrL changes from the on state to the off state.

The condition monitoring circuit 12B includes a sense transistor Trs formed as an N-channel type MOSFET and a dead time circuit 34, and their operations are the same as those described in the reference embodiment. However, the condition monitoring circuit 12B is provided with a resistor 41 and constant current circuits 42 and 43. Specifically, in the state monitoring circuit 12B, one end of the resistor 41 is connected to the gate line LG, while the other end of the resistor 41 is connected to the gate of the sense transistor Trs, and the source of the sense transistor Trs is an output transistor. It is connected to the source (and therefore ground) of the TrL. The connection node (connection point) Ns between the gate of the sense transistor Trs and the resistor 41 is connected to the constant current circuit 42, and the drain of the sense transistor Trs is connected to the input terminal D1 of the dead time circuit 34 and to the constant current circuit 43. Be connected.

The constant current circuit 42 is a circuit that supplies the constant current I3 to the resistance 41 at least when the turn-off operation of the output transistor TrL is performed (when the constant current I2 flows from the gate line LG toward the constant current circuit 32). be. At this time, the constant current I3 flows from the connection node Ns between the gate of the sense transistor Trs and the resistor 41 to the gate line LG via the resistor 41, and is drawn (or forced) into the drive circuit 11B as a part of the current I2. When the off-transistor Trfo is on, it flows to ground via the forced off-transistor Trfo). Therefore, when the constant current I3 is flowing through the resistance 41, the gate voltage of the sense transistor Trs is higher than the voltage of the gate line LG by the voltage drop of the resistance 41 due to the constant current I3.

More specifically, the constant current circuit 42 includes a constant current source 42a and transistors 42b and 42c configured as P-channel MOSFETs. A positive DC voltage VB is applied to each source of the transistors 42b and 42c, the gates of the transistors 42b and 42c and the drain of the transistor 42b are commonly connected to each other, and the drain of the transistor 43c is between the gate of the sense transistor Trs and the resistance 41. It is connected to the connection node Ns of. Then, the drain of the transistor 42b is connected to the constant current source 42a, and the constant current from the constant current source 42a is passed as the drain current of the transistor 42b, so that the constant current I3 as the drain current of the transistor 42c is required when the resistor 41 is required. It is possible to supply to.

The constant current circuit 43 is a circuit that supplies the constant current I4 as the drain current of the sense transistor Trs when the sense transistor Trs is on. More specifically, the constant current circuit 43 includes a constant current source 43a and transistors 43b and 43c configured as P-channel MOSFETs. A positive DC voltage VA is applied to each source of the transistors 43b and 43c, the gates of the transistors 43b and 43c and the drain of the transistor 43b are commonly connected to each other, and the drain of the transistor 43c is the drain of the sense transistor Trs and the dead time circuit. It is commonly connected to the input terminal D1 of 34. Then, the drain of the transistor 43b is connected to the constant current source 43a, and the constant current from the constant current source 43a is passed as the drain current of the transistor 43b, so that the constant current I4 as the drain current of the transistor 43c is turned on by the sense transistor Trs. When it is, it will flow as the drain current of the sense transistor Trs. The drain voltage level (drain potential) of the sense transistor Trs becomes a high level having a voltage comparable to that of the DC voltage VA when the sense transistor Trs is off, and the DC voltage VA when the sense transistor Trs is on. The low level is much lower than.

The operation of the dead time circuit 34 is the same as that described in the reference embodiment. The forced off circuit 13B is the same as the forced off circuit 13A in the reference embodiment, and includes a forced off transistor Trfo formed as an N-channel type MOSFET. Similar to the reference embodiment, the output terminal D2 of the dead time circuit 34 is connected to the gate of the forced off transistor Trfo, the drain of the forced off transistor Trfo is connected to the gate line LG, and the source of the forced off transistor Trfo is the output transistor TrL. Connected to the source (and therefore ground) of. Therefore, the state detection signal output from the output terminal D2 of the dead time circuit 34 is supplied to the gate of the forced off transistor Trfo, the forced off transistor Trfo is turned on when the state detection signal is at a high level, and the state detection signal is output. Turns off at low levels. When the state detection signal is at a high level, the forced off transistor Trfo is turned on to short-circuit the gate and source of the output transistor TrL and force the output transistor TrL to be turned off. That is, by forming an electric circuit for discharging the accumulated charge of the parasitic capacitance Ggs through the forced off transistor Trfo, the gate-source voltage _VGS of the output transistor TrL is reduced to substantially zero, and the current via the output transistor TrL is reduced to substantially zero. Block the flow of I _OUT .

As described in the reference embodiment, the dead time circuit 34 is in a state regardless of the input voltage level of the input terminal D1 after a certain period of time has elapsed after switching the voltage level of the state detection signal from the low level to the high level. The circuit may be a circuit that returns the voltage level of the detection signal to a low level, or may be a circuit that maintains the voltage level of the state detection signal at a high level until the next turn-on operation of the output transistor TrL is performed. At least, the dead time circuit 34 turns off the forced off transistor Trfo by setting the voltage level of the state detection signal to a low level regardless of the input voltage level of the input terminal D1 when the next turn-on operation of the output transistor TrL is performed. To maintain.

The sense transistor Trs and the output transistor TrL are semiconductor elements formed in the same structure as each other, whereby the gate threshold voltage VTH of the sense transistor Trs and the gate threshold voltage _VTH of the output transistor _TrL are in agreement with each other. It shall be. However, the match here is a concept including an error. With respect to any FET including a sense transistor Trs and an output transistor TrL, the gate threshold voltage _VTH is when a predetermined voltage (for example, 10V) is applied between the drain and the source of the FET in a predetermined ambient temperature environment. It is defined as the gate-source voltage required to pass a drain current of a predetermined magnitude (eg, 1 mA). By setting the transistors Trs and TrL as semiconductor elements formed with the same structure as each other, not only the _VTH value but also the temperature dependence of _VTH and the temperature dependence of the drain current and the voltage _VGS relationship, etc., are FETs. The electrical characteristics of the transistors are equivalent (expected to be equivalent) between the transistors Trs and TrL. As a result, it is possible to realize the desired operation in a wide temperature range.

The results of the third and fourth simulations performed on the load drive device 1B of the first embodiment will be described with reference to FIGS. 12 and 13. In the third simulation, the current I _OUT was assumed to be 100 mA, and in the fourth simulation, the current I _OUT was assumed to be 10 mA.

The solid line waveform 510, the solid line waveform 520, the broken line waveform 521, the solid line waveform 531 and the broken line waveform 532 in FIG. 12 are the voltage waveform of the output terminal OUT, the voltage waveform of the gate line LG, and the voltage waveform at the node Ns, respectively, in the third simulation. , The voltage waveform at the input terminal D1 of the dead time circuit 34 and the voltage waveform at the output terminal D2 of the dead time circuit 34 are shown.
The solid line waveform 560, the solid line waveform 570, the broken line waveform 571, the solid line waveform 581, and the broken line waveform 582 in FIG. 13 are the voltage waveform of the output terminal OUT, the voltage waveform of the gate line LG, and the voltage waveform at the node Ns in the fourth simulation, respectively. , The voltage waveform at the input terminal D1 of the dead time circuit 34 and the voltage waveform at the output terminal D2 of the dead time circuit 34 are shown.

In the third and fourth simulations, the timing T0 is the timing before the start of the turn-off operation with respect to the output transistor TrL. At the timing T0, a voltage V _ON at which the drain-source resistance RDS of the output transistor _TrL becomes sufficiently low (for example, 0.2Ω) is applied to the gate line LG as a gate voltage, and the voltage of the output terminal OUT is It is approximately 0V.

In the third and fourth simulations, the turn-off operation for the output transistor TrL is started from the timing T1. That is, in the third and fourth simulations, the constant current I2 flows from the gate line LG toward the constant current circuit 32 so that the accumulated charge of the parasitic capacitance Cgs decreases from the timing T1, and the voltage of the gate line LG gradually decreases. go. At this time, it is assumed that a constant current I3 flows through the resistor 41 to generate a voltage of 0.15 V at the resistor 41. That is, in the turn-off operation of the output transistor TrL, the gate voltage (voltage at the node Ns) of the sense transistor Trs is higher than the gate voltage of the output transistor TrL at least before the forced off transistor Trfo is turned on at the timing T4 described later. Is also higher by 0.15V. In FIG. 12, the deviation between the waveforms 520 and 521 corresponding to 0.15 V is slightly exaggerated so that the waveforms 520 and 521 can be easily distinguished (also for the waveforms 570 and 571 in FIG. 13). Similarly).

In the third and fourth simulations, the timing T2, which is the timing between the timings T1 and T3, is a timing at which the voltage of the output terminal OUT becomes 6V. In the third simulation of FIG. 12, the timing when the voltage of the gate line LG is 0.97V corresponds to the timing T2, and in the fourth simulation of FIG. 13, the timing when the voltage of the gate line LG is 0.78V corresponds to the timing T2. Corresponds to. This is because, in the output transistor TrL, when the gate-source voltage V _GS is 0.97 V, the drain-source resistance is 60 Ω (= 6 V / 100 mA), and the gate-source voltage V _GS is 0.78 V. When is, it indicates that the drain-source resistance is 600Ω (= 6V / 10mA).

In the turn-off operation of the output block 10LB, the voltage of the node Ns is 0.93V (= 0.78V + 0.15V) even if the voltage of the gate line LG drops to 0.78V, and the gate threshold voltage of the sense transistor Trs. Since it is higher than the VTH of _0.87V , the sense transistor Trs is kept on.

In the third and fourth simulations, the voltage of the node Ns drops to 0.87V when the timing T2 is exceeded and the timing T3 is reached. At this timing T3, the voltage of the gate line LG is 0.72V from "0.87-0.15 = 0.72". In the third and fourth simulations, the sense transistor Trs functioning as a switch is switched from on to off at the timing T3, the voltage level of the input terminal D1 of the dead time circuit 34 is switched from the low level to the high level, and then. At the timing T4 when the predetermined time _tDT has elapsed from the timing T3, the voltage level of the output terminal D2 of the dead time circuit 34 is switched from the low level to the high level. Then, the voltage level of the gate line LG is forcibly lowered to 0V by the turn-on of the forced off transistor Trfo.

Further, in the third and fourth simulations, after the timing T3, the drain-source resistance RDS of the output transistor _TrL becomes sufficiently large, and the current I _OUT as a constant current is substantially all on the high side side. Since the current flows into the power supply voltage line LN_VPWR through the diode DI connected in parallel to the output transistor TrH, the voltage of the output terminal OUT is 12V or more.

In this way, in the turn-off operation of the output transistor TrL, the sense transistor Trs is controlled at a gate voltage higher than the gate voltage of the output transistor TrL, so that the drain-source resistance of the output transistor TrL is sufficiently increased. The sense transistor Trs will turn off at. As a result, slew rate control that raises the voltage of the output terminal OUT at a slew rate according to the magnitude of the constant current I2 in the turn-off operation of the output transistor TrL is realized as desired regardless of whether the load LD is relatively heavy or light. It becomes possible to do.

Further, in the method of pulling up the drain of the sense transistor Trs with the resistor 33 as in the reference embodiment (FIG. 2), the manufacturing variation of the resistance value of the resistor 33 and the temperature change of the resistance value are correspondingly large. , When the voltage level at the input terminal D1 of the dead time circuit 34 transitions between the low level and the high level, the gate voltage of the sense transistor Trs is varied. By replacing the resistance 33 with the constant current circuit 43 as in the first embodiment, such variation can be suppressed.

[Second Example]
The second embodiment will be described. In the first embodiment, for the sake of clarification, only the output block 10LB for the output transistor TrL on the low side side is shown, and the configuration and operation of the output block are described only for the output block 10LB. However, as shown in FIG. 14, the load drive device 1B described above is provided with an output block 10HB similar to the output block 10LB for the output transistor TrH on the high side side. That is, the load drive device 1B is provided with an output block 10HB as an output block 10H for the output transistor TrH. The configuration and operation of the output block 10HB are the same as those of the output block 10LB described in the first embodiment.

However, when considering the configuration and operation of the output block 10HB, the output transistor TrL in the description of the reference embodiment and the first embodiment is read as the output transistor TrH, and each source of the sense transistor Trs and the forced off transistor Trfo in the output block 10HB. Will be connected to the source of the output transistor TrH (hence the output terminal OUT). The circuits 12B and 13B in the output block 10LB for the low side function beneficially in the turn-off operation of the output transistor TrL, whereas the circuits 12B and 13B in the output block 10HB for the high side function beneficially in the turn-off operation of the output transistor TrH. Will work.

[Third Example]
A third embodiment will be described. In the third embodiment, supplementary explanations will be provided regarding the configuration and operation of the devices and circuits according to the first and second embodiments.

As described above, each output block controls on / off of the target output transistor connected to itself, monitors the state of the target output transistor, and the like. The target output transistor for the output block 10L (10LB in the first embodiment) is the output transistor TrL, and the target output transistor for the output block 10H (10HB in the second embodiment) is the output transistor TrH.

The output block (10LB or 10HB) for the target output transistor includes a condition monitoring circuit 12B that outputs a forced off signal based on the voltage level at the gate of the target output transistor. In the first and second embodiments, the high-level state detection signal corresponds to the forced off signal, and the low-level state detection signal is not the forced off signal, but it is possible to reverse these relationships. ..

Further, the output block (10LB or 10HB) for the target output transistor includes a forced off circuit 13B that forcibly turns off the target output transistor when a forced off signal is received from the state monitoring circuit 12B in the output block. There is. That is, when the forced off circuit 13B receives the forced off signal, the forced off circuit 13B forms an electric circuit for discharging the accumulated charge of the parasitic capacitance between the gate and the source of the target output transistor through the forced off transistor Trfo, thereby forming the target output transistor. The gate voltage of the target output transistor is controlled in the direction in which the drain and the source are non-conducting, in other words, the gate voltage and the gate-source of the target output transistor are controlled in the direction in which the resistance value between the drain and the source of the target output transistor increases. Control the voltage between.

Both the output transistors TrL and TrH can be the target output transistors, but for the sake of clarification, when one of the output transistors TrL and TrH is regarded as the target output transistor and the other is referred to as the non-target output transistor, it is the target. The drive unit is composed of the drive circuit 11B for the output transistor and the drive circuit 11B for the non-target output transistor. This drive unit operates so as to allow the non-target output transistor to turn on when a forced off signal is received from the state monitoring circuit 12B for the target output transistor, whereby the target output transistor and the non-target output transistor simultaneously operate. Suppresses the generation of through current due to the ON state.

The condition monitoring circuit 12B for the target output transistor has sense transistors Trs arranged so as to be turned on and off in conjunction with the on and off of the target output transistor. That is, in the state monitoring circuit 12B for the target output transistor, the gate voltage of the target output transistor is directed from the off state to the on state by the turn-on operation of the drive unit (specifically, the drive circuit 11B for the target output transistor). Is controlled, the sense transistor Trs is also configured to go from the off state to the on state, and the target output transistor is turned from the on state by the turn-off operation of the drive unit (specifically, the drive circuit 11B for the target output transistor). When the gate voltage of the target output transistor is controlled in the direction toward the off state, the sense transistor Trs is also configured to move from the on state to the off state. Then, the state monitoring circuit 12B for the target output transistor receives the turn-off of the sense transistor Trs and outputs a forced off signal (here, a high-level state detection signal). More specifically, the condition monitoring circuit 12B outputs a forced off signal after a predetermined time _tDT has elapsed from the timing at which the sense transistor Trs functioning as a switch is turned off.

However, the state monitoring circuit 12B for the target output transistor includes a resistor (adjustment resistance) 41 between the gate of the sense transistor Trs and the gate of the target output transistor, and the target output transistor is turned off from the on state by the turn-off operation of the drive unit. When the gate voltage of the target output transistor is controlled in the direction toward the state (when the gate-source voltage of the target output transistor is reduced), a predetermined current (here, constant current I2) is supplied to the resistor 41. .. As a result, the turn-off timing of the sense transistor Trs is delayed by the voltage drop of the resistance 41 due to the predetermined current in comparison with the case where the resistance 41 is not provided.

That is, in the process in which the gate-source voltage of the target output transistor is reduced due to the turn-off operation of the drive unit with respect to the target output transistor, the date voltage and the gate-source voltage of the target output transistor reach the gate threshold voltage of the sense transistor Trs. The sense transistor Trs remains on even when reduced, and then the sense transistor Trs turns off (functions as a switch) when the gate-source voltage of the target output transistor is further reduced by the voltage drop of the resistor 41. The state of the sense transistor Trs is switched from the on state to the off state).

Further, as will be described later, when the target output transistor and the sense transistor Trs are replaced with IGBTs (Insulated Gate Bipolar Transistor) (see FIG. 20), the source is replaced with the emitter, so that the target output transistor and the emitter of the sense transistor Trs are replaced. They are connected in common. Then, in the process in which the gate-emitter voltage of the target output transistor is reduced due to the turn-off operation of the drive portion with respect to the target output transistor, the gate voltage and the gate-emitter voltage of the target output transistor reach the gate threshold voltage of the sense transistor Trs. The on state of the sense transistor Trs is maintained even if it is reduced, and then, when the gate-emitter voltage of the target output transistor is further reduced by the voltage drop of the resistor 41, the sense transistor Trs is turned off.

The driver unit can be controlled through the output of a control signal so that the target output transistor is repeatedly turned on and off (for example, periodically turned on and off). That is, the control circuit 20 can control the driver unit through the output of the control signal so that the period in which the target output transistor is in the on state and the period in which the target output transistor is in the off state are alternately and repeatedly visited. Through the configuration and operation as described above, it is possible to satisfactorily realize slew rate control that changes the voltage of the output terminal OUT at a desired slew rate regardless of the magnitude of the load current in the turn-off operation of the target output transistor. It will be possible.

The output block 10 for the output transistor TrH is the output block 10HB (see FIG. 14) including the resistor 41 and the like, while the output block 10 for the output transistor TrL is the output block 10LA (see FIG. 2) not including the resistor 41 and the like. It may be possible to do. On the contrary, it is possible that the output block 10 for the output transistor TrL is the output block 10LB (see FIG. 11) including the resistor 41 and the like, but the output block 10 for the output transistor TrH is the output block not including the resistor 41 and the like. Is also good.

[Fourth Example]
A fourth embodiment will be described. FIG. 15 shows a configuration example of the above-mentioned constant current circuit 32. The constant current circuit 32 includes a constant current source 32a and transistors 32b, 32c, and 32d configured as N-channel MOSFETs.

The sources of the transistors 32b, 32c and 32d are connected to the ground, and the gates of the transistors 32b and 32c and the drains of the transistors 32b and 32d are commonly connected to each other. The drain of the transistor 32c is connected to the corresponding gate line LG. Then, the drain of the transistor 32b is connected to the constant current source 32a, and the constant current from the constant current source 32a is passed as the drain current of the transistor 32b. It can be pulled in from the gate line LG. The control circuit 20 can control the presence or absence of a constant current I1 by turning the transistor 32d on and off through the control of the gate voltage of the transistor 32d.

The constant current circuit 31 for supplying the constant current I1 to the gate line LG can also be the same circuit as the constant current circuit 32 (provided that it is modified to reverse the flow of the constant current). ..

Further, in the load drive device (1, 1A, 1B), the magnitudes of the constant currents I1 and I2 may be variably set.

In the present invention, it is not essential that the current I2 is a constant current, and the current I2 may change with the passage of time during the execution period of the turn-off operation. Similarly, in the present invention, it is not essential that the current I1 is a constant current, and the current I1 may change over time during the execution period of the turn-on operation.

[Fifth Example]
A fifth embodiment will be described. The load LD is arbitrary as long as it is a load that is driven by receiving the supply of the current I _OUT via the output terminal OUT. When the load LD is a motor, it can be said that the load drive device (1, 1A, 1B) functions as a motor driver device. Further, in the first embodiment and the like, in order to facilitate understanding of the operation of the output block according to the present invention, it is assumed that the current I _OUT supplied to the load LD is a constant current, but the current I _OUT is constant. It does not have to be an electric current.

[Sixth Example]
The sixth embodiment will be described. FIG. 16 is a schematic configuration diagram relating to the mechanism of the hard disk device (hereinafter referred to as HDD device) 100 as the magnetic disk device according to the sixth embodiment. FIG. 17A is a schematic electrical block diagram of the HDD device 100.

The HDD device 100 can move the magnetic disk 110 as a recording medium, the head 111 which is a magnetic head for writing and reading information to and from the magnetic disk 110, and the head 111 in the radial direction of the magnetic disk 110. The arm 112 that supports the arm 112, the spindle motor 113 that supports and rotates the magnetic disk 110 (hereinafter referred to as SPM 113), and the arm 112 are rotationally driven and positioned to move the head 111 in the radial direction of the magnetic disk 110. A voice coil motor 114 for positioning (hereinafter referred to as VCM 114), a lamp unit 115 for holding the head 111 in a predetermined retracted position away from the magnetic disk 110 when the head 111 moves to the outside of the outer periphery of the magnetic disk 110, and a lamp unit 115. To prepare for. The magnetic disk 110, the head 111, the arm 112, the SPM 113, the VCM 114, and the lamp unit 115 are housed in the housing of the HDD device 100. The movement in the radial direction of the magnetic disk 110 means the movement in the direction connecting the outer periphery and the center of the magnetic disk 110 having a disk shape, but the movement in the radial direction of the magnetic disk 110 is the outer circumference of the magnetic disk 110. In addition to the component of movement in the direction connecting the center and the center, the component of movement in other directions (for example, the tangential direction of the outer periphery of the magnetic disk) may be included.

The HDD device 100 is provided with a driver IC 200, a signal processing circuit 120, an MPU (micro-processing unit) 130, and a power supply circuit 140 as electrical components. The power supply circuit 140 supplies the driver IC 200, the signal processing circuit 120, and the power supply voltage for driving the MPU 130 to them.

When writing information to the magnetic disk 110, the signal processing circuit 120 outputs a recording signal for writing the information to the head 111, and when reading information from the magnetic disk 110, the signal is read from the magnetic disk 110. On the other hand, necessary signal processing is performed, and the signal obtained by this is sent to the MPU 130. The MPU 130 controls the information writing operation and reading operation by the head 111 through the control of the signal processing circuit 120.

The driver IC 200 is an electronic component (motor driver device) formed by enclosing a semiconductor integrated circuit in a housing (package) made of resin, as shown in FIG. 17 (b). The number of pins (number of external terminals) of the driver IC 200 shown in FIG. 17B is merely an example. The driver IC 200 is provided with an SPM driver 210 for driving the SPM 113 and a VCM driver 220 for driving the VCM 114, and an IF circuit (interface circuit) for enabling bidirectional communication between the MPU 130 and the driver IC 200. The 230 and the control circuit 240 that controls the operation of the SPM driver 210 and the VCM driver 220 based on the control data received from the MPU 130 in the IF circuit 230 are provided.

The MPU 130 controls the rotation of the magnetic disk 110 through the drive control of the SPM 113 by controlling the SPM driver 210 of the driver IC 200, and controls the movement of the head 111 through the drive control of the VCM 114 by controlling the VCM driver 220 of the driver IC 200. Perform positioning. Positional information indicating each position on the magnetic disk 110 is recorded at each location of the magnetic disk 110, and when the head 111 is located on the magnetic disk 110, this position information is read by the head 111. , Is transmitted to the MPU 130 through the signal processing circuit 120. The MPU 130 can control the VCM driver 220 based on the position information, and the VCM driver 220 supplies the required drive current to the VCM 114 through this control to realize the movement and positioning of the head 111. The fact that the head 111 is located on the magnetic disk 110 means that the head 111 is located above the magnetic disk 110 with a minute space in between.

FIG. 18 shows the internal configurations of the SPM 113 and the SPM driver 210 and their connection relationships. The SPM 113 is a three-phase DC motor including a star-connected U-phase coil 113u, a V-phase coil 113v, and a W-phase coil 113w. One end of the coil 113u, one end of the coil 113v, and one end of the coil 113w are connected to the external terminals OUTu, OUTv, and OUTw provided in the driver IC 200, respectively, and the other ends of the coils 113u, 113v, and 113w are neutral points 113n. It is commonly connected at.

The SPM driver 210 is via a half-bridge circuit 211u connected to one end of the coil 113u via the external terminal OUTu, a half-bridge circuit 211v connected to one end of the coil 113v via the external terminal OUTv, and an external terminal OUTw. A half-bridge circuit 211w connected to one end of the coil 113w, an output stage circuit 212 for turning on and off each transistor in each half-bridge circuit, and a control circuit 213 for controlling the operation of the output stage circuit 212 are provided. ..

The half-bridge circuits 211u, 211v and 211w are each of the high-side output transistor TrH and the low-side side connected in series between the line to which the power supply voltage VPWR is applied (that is, the power supply line LN_VPWR; see FIG. 1) and the ground. It consists of an output transistor TrL. The output transistors TrH and TrL in each half-bridge circuit in the SPM driver 210 correspond to the output transistors TrH and TrL in each of the above-described embodiments, and the connection relationship between the output transistors TrH and TrL and the output terminal OUTu of the half-bridge circuit 211u. The connection relationship between the output transistors TrH and TrL and the output terminal OUTv of the half-bridge circuit 211v and the connection relationship between the output transistors TrH and TrL and the output terminal OUTw of the half-bridge circuit 211w are the output transistors in each of the above-described embodiments. The connection relationship between the TrH and TrL and the output terminal OUT is the same.

The control circuit 213 has, for example, the potential of the connection point between one end of the coil 113u and the half bridge circuit 211u, the potential of the connection point between one end of the coil 113v and the half bridge circuit 211v, and one end of the coil 113w and the half bridge circuit 211w. A PWM signal for the U phase, a PWM signal for the V phase, and a PWM signal for the W phase are generated based on the potential of the connection point, the potential of the neutral point 113n, and the like. Then, the output stage circuit 212 obtains the power supply voltage VPWR by pulse width modulation by turning on / off each output transistor of the corresponding half bridge circuit (211u, 211v, 211w) according to each PWM signal from the control circuit 213. The switching voltages for U-phase, V-phase, and W-phase, which are the voltages to be generated, are generated, and the switching voltages for U-phase, V-phase, and W-phase are supplied to the coils 113u, 113v, and 113w, respectively. At this time, for example, the PWM signal of each phase may be generated so that the currents flowing through the coils 113u, 113v and 113w each have a sinusoidal shape.

The output stage circuit 212 includes a total of six output blocks 10 for individually turning on and on each output transistor in the SPM driver 210, and these six output blocks 10 are used in the first embodiment or the second embodiment. The indicated output block 10LB or 10HB (see FIGS. 11 and 14) may be used. That is, the output stage circuit 212 may include an output block 10HB for each output transistor TrH in the SPM driver 210, and an output block 10LB for each output transistor TrL in the SPM driver 210. At this time, the operations of the output blocks 10HB and 10LB provided for the half-bridge circuit 211u, the operations of the output blocks 10HB and 10LB provided for the half-bridge circuit 211v, and the output blocks provided for the half-bridge circuit 211w. The operation of 10HB and 10LB may be the same as the operation of the output blocks 10HB and 10LB described in each of the above-described embodiments, respectively. In the SPM driver 210, the control circuit 213 includes the function of the control circuit 20 (see FIG. 1 and the like), and the SPM 113 (coils 113u, 113v, 113w) corresponds to the load LD. Therefore, it can be said that the SPM driver 210 includes the above-mentioned load driving device 1B.

When the PWM signal of each phase is generated so that the currents flowing through the coils 113u, 113v and 113w are sinusoidal, the magnitude of the current flowing through the output terminals OUTu, OUTv and OUTw is time. It changes over time. By using the output blocks 10HB and 10LB for the output stage circuit 212, the target output transistors (U phase, V phase, It is possible to satisfactorily realize slew rate control in which the voltage of the output terminals (OUTu, OUTv, OUTw) is changed at a desired slew rate in the turn-off operation of the W phase TrH or TrL).

FIG. 19 shows the internal configurations of the VCM 114 and the VCM driver 220 and their connection relationships. The external terminals provided in the driver IC 200 include external terminals OUTa and OUTb, the external terminal OUTa is connected to one end of the VCM 114 via the sense resistor Rs, and the external terminal OUTb is directly connected to the other end of the VCM 114. ..

The VCM driver 220 turns on and off the half-bridge circuit 221a connected to the external terminal OUTa, the half-bridge circuit 221b connected to the external terminal OUTb, and each transistor in each half-bridge circuit (221a, 221b). The output stage circuit 222 and the control circuit 223 for controlling the operation of the output stage circuit 222 are provided.

The half-bridge circuits 221a and 221b each have a high-side output transistor TrH and a low-side output transistor connected in series between the line to which the power supply voltage VPWR is applied (that is, the power supply line LN_VPWR; see FIG. 1) and the ground. It consists of TrL. The output transistors TrH and TrL in each half bridge circuit in the VCM driver 220 correspond to the output transistors TrH and TrL in each of the above embodiments, and the connection relationship between the output transistors TrH and TrL and the output terminal OUTa of the half bridge circuit 221a. The connection relationship between the output transistors TrH and TrL and the output terminal OUTb of the half-bridge circuit 221b is the same as the connection relationship between the output transistors TrH and TrL and the output terminal OUT in each of the above-described embodiments.

The control circuit 223 specifies, for example, a voltage drop signal of the resistors Rs indicating the magnitude and direction of the current flowing through the VCM 114 via the output terminals OUTa and OUTb, and the magnitude and direction of the current to be supplied to the VCM 114. Based on the current command signal, a PWM signal for each half-bridge circuit in the VCM driver 220 is generated and output so that the current flowing through the VCM 114 follows the current command signal. The current command signal is supplied to the driver IC 200 from, for example, the MPU 130. Then, the output stage circuit 222 turns on and off each output transistor of the corresponding half-bridge circuit (221a, 221b) according to each PWM signal from the control circuit 223, so that the current flowing through the VCM 114 while utilizing the pulse width modulation. Is controlled according to the current command signal. If the magnitude and direction of the current specified by the current command signal are constant, the VCM 114 will operate at a constant current by PWM drive. At this time, by supplying the current flowing from the output terminal OUTa toward the output terminal OUTb to the VCM 114, the head 111 moves from the outer peripheral side of the magnetic disk 110 toward the center of the magnetic disk 110, and from the output terminal OUTb to the output terminal OUTa. By supplying the current flowing toward the VCM 114 to the VCM 114, the head 111 moves from the center of the magnetic disk 110 toward the outer peripheral side of the magnetic disk 110.

The output stage circuit 222 includes a total of four output blocks 10 for individually turning on and on each output transistor in the VCM driver 220, and these four output blocks 10 are used in the first embodiment or the second embodiment. The indicated output block 10LB or 10HB (see FIGS. 11 and 14) may be used. That is, it is preferable that the output stage circuit 222 includes an output block 10HB for each output transistor TrH in the VCM driver 220 and an output block 10LB for each output transistor TrL in the VCM driver 220. At this time, the operations of the output blocks 10HB and 10LB provided for the half-bridge circuit 221a and the operations of the output blocks 10HB and 10LB provided for the half-bridge circuit 221b are described in each of the above-described embodiments. It may be the same as the operation of the output blocks 10HB and 10LB. In the VCM driver 220, the control circuit 223 includes the functions of the control circuit 20 (see FIG. 1 and the like), and the VCM 114 corresponds to the load LD. Therefore, it can be said that the VCM driver 220 includes the above-mentioned load driving device 1B.

The supply current to the VCM 114 changes variously through changes in the current command signal (changes in the required torque). By using the output blocks 10HB and 10LB for the output stage circuit 222, the turn-off operation of the target output transistor (TrH or TrL) is performed while suppressing the generation of a slew rate regardless of whether the supply current to the VCM 114 is large or small. It is possible to satisfactorily realize slew rate control in which the voltage of the output terminals (OUTa, OUTb) is changed at a desired slew rate.

Regarding the VCM driver 220, the drive method of the VCM 114 described above belongs to the PWM drive method of intermittently supplying power to the VCM 114 by supplying a pulse width modulated voltage to the VCM 114, but the VCM driver 220 has a pulse width. It may be possible to operate in a linear drive system that constantly supplies electric power to the VCM 114 by supplying an unmodulated continuous voltage as the drive voltage of the VCM 114. The VCM driver 220 may be provided with a circuit for the PWM drive method and a circuit for the linear drive method. In this case, by switching and using those circuits, the VCM 114 can be used in either the PWM drive method or the linear drive method. Is driven. At this time, of the circuit for the PWM drive system and the circuit for the linear drive system, a part of one circuit may be shared as a part of the other circuit.

When the SPM 113 or VCM 114 is PWM-driven, if the voltage at the output terminal (OUTu, OUTa, etc.) connected to the SPM 113 or VCM 114 is suddenly changed, the high frequency component in the steep voltage change increases the noise of the entire HDD device 100. It is known to make it. Therefore, in order to reduce such noise as much as possible, in HDD devices, generally, a through that gently changes the voltage of the output terminal at a desired slew rate in the turn-on operation and turn-off operation of the target output transistor (TrH or TrL). Rate control is required. By using the output blocks shown in the first and second embodiments, it is possible to meet the demand regardless of the magnitude of the current to the load.

Each component of the driver IC 200 is formed in the form of a semiconductor integrated circuit, and the semiconductor device is configured by enclosing the semiconductor integrated circuit in a housing (package) made of resin. , A circuit equivalent to the circuit in the driver IC 200 may be configured by using a plurality of discrete components. Further, it can be said that the driver IC 200 functions as a motor driver device. However, it can be considered that the motor driver device is configured by the combination of the driver IC 200 and the MPU 130.

[7th Example]
A seventh embodiment will be described.

Since the load drive device (1, 1A, 1B) employs a method of sensing the gate-source voltage of the transistor, the dead time may not be provided (that is, the predetermined time _tDT may be set. (It may be zero), and the generation of through current can be suppressed in principle without setting a dead time.

The slew rate control has been described above for reducing noise in HDD devices, but if the voltage at the output terminal (OUT) is changed sharply, the high frequency components in the steep voltage change will adversely affect other circuit operations as noise. In consideration of this, the above-mentioned slew rate control may be required. The present invention is applicable to any application requiring the above-mentioned slew rate control.

The type of channel of the FET (field effect transistor) shown in the above embodiment is an example, so that the P-channel type FET is changed to the N-channel type FET, or the N-channel type FET is P. The configuration of the circuit including the FET can be modified so as to be changed to a channel type FET.

However, when the target output transistor (TrH, TrL) is changed to a P-channel type FET, the sense transistor Trs and the forced off-transistor Trfo provided corresponding to the target output transistor are also changed to the P-channel type FET. ..

When changing the target output transistors (TrH, TrL) and sense transistors Trs to P-channel type FETs, considering that their gate threshold voltage becomes a negative voltage, each circuit described above is in line with the above-mentioned purpose. The configuration and operation of the above may be changed. For example, when the output transistor TrH is changed to a P-channel type FET, the direction of the current I1 flow in the turn-on operation of the output transistor TrH is opposite to that when it is an N-channel type (that is, the output transistor TrH). The direction of the current I2 flow in the turn-off operation of the output transistor TrH is also opposite to that of the N-channel type (that is, the direction of increasing the gate voltage of the output transistor TrH). Become).

Further, each transistor exemplified in the above-described embodiment may be any kind of transistor. For example, the transistor shown as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor) or a bipolar transistor. Any transistor has a first electrode, a second electrode and a control electrode. In the FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In the IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

In particular, for example, the above-mentioned output transistor (TrH, TrL) is a voltage-controlled output transistor such as a FET including a MOSFET or an IGBT (that is, the current flowing between the first and second electrodes is controlled according to the voltage at the control electrode. It is good to be a transistor).

FIG. 20 shows a partial configuration diagram of a load drive device 1B in which output transistors TrL and TrH and sense transistors Trs are formed as N-channel type IGBTs. When the transistors TrL, TrH and Trs are referred to as IGBTs, it is sufficient to read the drains and sources in the above description regarding the transistors TrL, TrH and Trs as collectors and emitters, respectively. Even when the output transistor TrL and the sense transistor Trs are formed as IGBTs in the output block 10LB on the low side side, the output transistor TrL and the sense transistor Trs have the same structure as when they are formed as FETs. It is preferable that the gate threshold voltage VTH of the sense transistor Trs and the gate threshold voltage _VTH of the output transistor _TrL are in agreement with each other. The same applies to the output block 10HB on the high side.

<< Consideration of the present invention >>
The present invention embodied in the above-described embodiment will be considered.

The load drive device W (see FIG. 11 and the like) according to the present invention includes a first output transistor and a second output transistor connected in series to each other, and a drive unit for turning on and off each output transistor (for example, FIG. 1-2). A load drive device that has (a combination of two drive circuits 11) and supplies a load current to a load via an output terminal provided between the first output transistor and the second output transistor. It is connected to the control electrode of the target output transistor (for example, TrL) which is one of the first output transistor and the second output transistor, and a forced off signal can be output based on the voltage level in the control electrode of the target output transistor. The monitoring circuit includes a monitoring circuit (12B) and a forced off circuit (13B) that forcibly turns off the target output transistor when the forced off signal is received from the monitoring circuit. The monitoring circuit is a sense transistor. It has (Trs), and when the voltage at the control electrode of the target output transistor is controlled by the drive unit in the direction from the on state to the off state, the sense transistor is also in the off state. The drive unit receives the output of the forced off signal and outputs the forced off signal in response to the turn-off of the sense transistor of the first output transistor and the second output transistor. Allowing the other output transistor (eg, TrH) to be turned on, the monitoring circuit further has an adjustment resistor (41) inserted between the control electrode of the sense transistor and the control electrode of the target output transistor. Then, when the voltage at the control electrode of the target output transistor is controlled by the drive unit in the direction from the on state to the off state of the target output transistor, the adjustment is performed by supplying a predetermined current to the adjustment resistor. It is characterized in that the turn-off timing of the sense transistor is delayed by the voltage drop of the adjustment resistor as compared with the case where there is no resistance.

The function of the forced off circuit and the drive unit can suppress the generation of through current due to the simultaneous on of the first and second output transistors. Then, according to the load drive device W including the adjustment resistor, the resistance value at the place where the load current of the target output transistor flows (in the case of FET, the resistance value of the drain-source resistance) is sufficiently increased, and then the sense transistor is used. Since the target output transistor is forcibly turned off through the turn-off, the voltage change of the output terminal in the process from the on state to the off state of the target output transistor is gentle regardless of whether the load current is large or small. Can be.

In the load drive device W, for example, when the target output transistor is switched from the on state to the off state, the drive unit has the off current source and the target in the direction in which the target output transistor moves from the on state to the off state. A predetermined off current (I2) is passed between the control electrode of the output transistor and the target output transistor is turned from the on state to the off state over a period of time corresponding to the magnitude of the off current. Is good.

As a result, the voltage change of the output terminal in the process from the on state to the off state of the target output transistor can be made into a voltage change at a speed corresponding to the off current (slew rate control becomes possible), and the voltage can be controlled. It is possible to reduce the high frequency component in the change. By reducing the high frequency component in the voltage change of the output terminal, it is possible to reduce the noise in the device incorporating the load drive device and suppress the generation of noise. Then, by configuring the load drive device W as described above using the adjustment resistor, it is possible to make the voltage change of the output terminal gentle without depending on the magnitude of the load current.

The embodiments of the present invention can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present invention, and the meanings of the terms of the present invention or each constituent requirement are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values.

1, 1A, 1B Load drive device 10, 10L, 10H, 10LA, 10LB, 10HB Output block 11, 11A, 11B Drive circuit 12, 12A, 12B Status monitoring circuit 13, 13A, 13B Forced off circuit TrL, TrH Output transistor Trs Sense transistor Trfo Forced off transistor 100 HDD device 110 Magnetic disk 111 Head 112 Arm 113 SPM
114 VCM
210 SPM driver 220 VCM driver

Claims (11)

The first output transistor and the second output transistor are provided with a first output transistor and a second output transistor connected in series with each other, and the first output transistor and the second output transistor are controlled by controlling the on / off of the first output transistor and the second output transistor. It is a load drive device that supplies a load current to a load via an output terminal provided between the two.
It is connected to the control electrode of the target output transistor, which is one of the first output transistor and the second output transistor, and controls the voltage between the control electrode of the target output transistor and the other electrodes based on the supplied control signal. By doing so, the drive circuit for turning on / off the target output transistor and
A control circuit that supplies the control signal to the drive circuit,
It is connected to the control electrode of the target output transistor , monitors the voltage level in the control electrode of the target output transistor, and the potential of the control electrode seen from other electrodes in the target output transistor is less than the threshold voltage of the target output transistor. A monitoring circuit that can output a forced off signal when the voltage is below the specified voltage ,
A forced-off circuit that forcibly turns off the target output transistor when the forced-off signal is received from the monitoring circuit is provided.
When the target output transistor is switched from the on state to the off state based on the control signal, the drive circuit has a predetermined off position on the control electrode of the target output transistor in the direction in which the target output transistor moves from the on state to the off state. An off current source that causes the target output transistor to move from the on state to the off state over a period of time according to the magnitude of the off current, and the target output transistor based on the control signal. When switching from the off state to the on state, a predetermined on current is passed through the control electrode of the target output transistor in the direction from the off state to the on state, whereby the magnitude of the on current is large. It is equipped with an on-current source for turning the target output transistor from the off state to the on state over a period of time according to the above.
The monitoring circuit has a sense transistor, and when the drive circuit controls the voltage at the control electrode of the target output transistor in the direction from the on state to the off state of the target output transistor, the sense transistor is also turned on. It is configured to go from the state to the off state, receives the turn-off of the sense transistor, outputs the forced off signal, and outputs the forced off signal.
In the load drive device, the first output transistor and the first output transistor are allowed to turn on by receiving the output of the forced off signal and allowing the other output transistor of the first output transistor and the second output transistor to turn on . Prevents two output transistors from turning on at the same time,
The monitoring circuit further has an adjustment resistor inserted between the control electrode of the sense transistor and the control electrode of the target output transistor, and the direction in which the target output transistor is turned from the on state to the off state by the drive circuit . By supplying a predetermined current to the adjustment resistor when the voltage at the control electrode of the target output transistor is controlled, the sense transistor is equal to the voltage drop of the adjustment resistor as compared with the case where there is no adjustment resistor. Delay the timing of the turn-off
, Load drive. Each of the target output transistor and the sense transistor is a field effect transistor having a gate as the control electrode, and the target output transistor and the source of the sense transistor are commonly connected to each other.
In the process of reducing the gate-source voltage of the target output transistor from the on state to the off state by the drive circuit, the gate-source voltage of the target output transistor becomes the gate of the sense transistor. The on state of the sense transistor is maintained even when the voltage is reduced to the threshold voltage, and then the sense transistor is turned off when the gate-source voltage of the target output transistor is further reduced by the voltage drop of the adjustment resistor. do
, The load drive device according to claim 1. Each of the target output transistor and the sense transistor is an IGBT having a gate as the control electrode, and the target output transistor and the emitter of the sense transistor are commonly connected to each other.
In the process of reducing the gate-emitter voltage of the target output transistor from the on state to the off state by the drive circuit, the gate-emitter voltage of the target output transistor becomes the gate of the sense transistor. The on state of the sense transistor is maintained even when the voltage is reduced to the threshold voltage, and then the sense transistor is turned off when the gate-emitter voltage of the target output transistor is further reduced by the voltage drop of the adjustment resistor. do
, The load drive device according to claim 1. The target output transistor and the sense transistor have a gate threshold voltage common to each other.
, The load drive device according to claim 2 or 3. The monitoring circuit outputs the forced off signal after a predetermined time has elapsed from the turn-off of the sense transistor.
, The load drive device according to any one of claims 1 to 4. The control circuit controls the drive circuit so that the target output transistor is repeatedly turned on and off.
, The load drive device according to any one of claims 1 to 5. Each of the first output transistor and the second output transistor is defined as the target output transistor.
The drive circuit, the monitoring circuit, and the forced off circuit are provided for each of the first output transistor and the second output transistor.
, The load drive device according to any one of claims 1 to 6. A semiconductor device that forms the load drive device according to any one of claims 1 to 7.
The load drive device is formed by using an integrated circuit.
, Semiconductor device. The load drive device according to any one of claims 1 to 7 is provided, and the load current is supplied to the motor as the load.
, Motor driver device. A motor driver device including the load drive device according to any one of claims 1 to 7.
The load drive device is an SPM driver that drives a spindle motor that rotates a magnetic disk of a magnetic disk device as the load.
, Motor driver device. A motor driver device including the load drive device according to any one of claims 1 to 7.
The load drive device is a VCM driver that drives a voice coil motor that moves the magnetic head of the magnetic disk device in the radial direction of the magnetic disk as the load.
, Motor driver device.

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