JP6995644B2 - Electronic control device - Google Patents

Description

The present invention relates to an electronic control device capable of controlling access to a shared resource of a multi-core microcomputer (also referred to as a many-core microcomputer).

With the miniaturization of semiconductor processes, highly integrated and highly functional embedded microcomputers are rapidly advancing. One of the important applications of the embedded microcomputer is an in-vehicle electronic control unit (Electronic Control Unit, ECU) in the automobile field. Against the background of the demand for system cost reduction, there is a demand for a technology that enables functions realized by a plurality of ECUs to be integrated into one ECU. Expected technologies include, for example, an integrated ECU equipped with a high-performance embedded microcomputer utilizing multi-core, and an application execution platform for appropriately executing an application that realizes each function integrated in the integrated ECU.

The in-vehicle ECU, which is greatly related to the safety of the final product, relies on ISO26262, which is an international standard for in-vehicle embedded systems, as a functional safety framework that guarantees the mounting quality and safety. ISO 26262 is standardized with the goal of achieving both high safety and reliability in in-vehicle embedded systems and efficient software development, and introduces an index called the Automotive Safety Risk (ASIL), which is derived from ASIL. Three factors (exposure, avoidance, and degree of harm) for this purpose and hazard analysis and risk assessment methods using them are defined. ASIL expresses the level of safety that must be realized in order to avoid possible obstacles (hazard) in an in-vehicle embedded system in five stages.

Of particular importance in ISO 26262 compliance is the assurance of Freedom From Interference (FFI) between applications. The idea of FFI is that when multiple applications with different ASILs are mixed and executed on one ECU, the malfunction that occurs in the application with the lower ASIL becomes the application with the higher ASIL. It is required to prevent it from propagating. There are three types of interference that can occur between applications defined by ISO 26262: timing and execution (time domain), memory, and information exchange.

Non-interfering in the time domain means that failures that occur during the execution of one application or unexpected interrupt handling do not interfere with the execution of other safety-related applications. As a typical implementation means for that purpose, as a part of the elements that make up the real-time OS that is the execution platform, the application execution is static or dynamic by combining time management hardware (watchdog timer, etc.) and software. Some have a target scheduling function and an execution time monitoring function. When determining the execution schedule of multiple applications (or tasks that are components of the application) that run simultaneously on the in-vehicle ECU, applications related to access to shared resources such as internal or external memory and peripheral modules of the microcomputer. It is required that there is no contradiction in the dependencies between them.

When there are relatively few applications that are executed at the same time or arithmetic elements that execute the applications, the following technologies that realize resource sharing and exclusive control of access are used.
(1) Time-driven scheduling that allocates fixed time slots to each application in an appropriate order while maintaining the dependency between applications in units of time (Tick) managed by the real-time OS scheduler.
(2) Exclusive access control by lock / unlock operation using the means supported by the architecture of the microcomputer for the lock variable set for each shared resource.

Tsutomu Sawada (2006) "Easy-to-understand embedded system construction technique-software edition-" Kyoritsu Shuppan

However, in time-driven scheduling, the utilization efficiency of shared resources decreases when the time for occupying shared resources is less than Tick or when there is a large difference between applications. In addition, the interval for allocating usage rights for shared resources to a specific application increases in proportion to the number of applications, which reduces the real-time performance of processing.

In the access exclusive control, the utilization efficiency of the arithmetic element is lowered due to the spinlock processing and the arithmetic processing bottleneck occurs, and strict schedule management based on the priority required for the realization of FFI is also impossible.

Therefore, regardless of which of the above technologies are applied, the software execution platform is integrated in the in-vehicle multi-core microcomputer mounted on the integrated ECU, and a large number of applications running on the software share resources inside and outside the microcomputer. In order to achieve both hard real-time performance, which is a requirement peculiar to in-vehicle embedded systems, and the realization of scalable resource sharing control that can continue to adapt to the increasing trend of the number of applications (or arithmetic elements) operating in parallel on a microcomputer. It was difficult to get it done.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an electronic control device capable of improving the utilization efficiency of shared resources while maintaining the real-time performance of processing in a multi-core microcomputer. be.

In order to achieve the above object, the electronic control device according to the first aspect stores the policy information regarding the allocation of the shared resource, and the first arithmetic unit that executes the allocation process of the shared resource based on the policy information. Be prepared.

According to the present invention, it is possible to improve the utilization efficiency of shared resources while maintaining the real-time performance of processing in a multi-core microcomputer.

FIG. 1 is a block diagram showing a configuration example of a microcomputer applied to the electronic control device according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the usage authority control device of FIG. FIG. 3 is a block diagram showing a modified example of the usage authority control device of FIG. FIG. 4 is a diagram showing a modification of the microcomputer of FIG. 1. FIG. 5 is a diagram showing a configuration example of the control table of FIG. FIG. 6 is a diagram showing a configuration example of the usage request register of FIG. FIG. 7 is a diagram showing a configuration example of the inter-PE interrupt control device of FIG. 8 (a) and 8 (b) are timing charts showing the relationship between the control cycle of the microcomputer of FIG. 1 and the shared resource usage request time window. FIG. 9 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the first embodiment. FIG. 10 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the first embodiment. FIG. 11 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the first embodiment. FIG. 12 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the second embodiment. FIG. 13 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the second embodiment. FIG. 14 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the second embodiment. FIG. 15 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the third embodiment. FIG. 16 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the third embodiment. FIG. 17 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the third embodiment. FIG. 18 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the third embodiment. FIG. 19 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the fourth embodiment. FIG. 20 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the fourth embodiment. FIG. 21 is a flowchart showing the operation of granting the shared resource use authority of the microcomputer according to the fourth embodiment. FIG. 22 is a flowchart showing a process of determining the order of granting usage authority in the microcomputer of FIG. FIG. 23 is a flowchart showing a process of determining the grantee of the usage authority in the microcomputer of FIG. FIG. 24 is a diagram showing an example of a time change in power consumption during the operation of the microcomputer of FIG. 1 or FIG. 4 (a). FIG. 25 is a diagram showing an example of time-dependent changes in power consumption during operation of the microcomputer of FIG. 1 or FIG. 4 (b). FIG. 26 is a block diagram showing a configuration example of a microcomputer according to a comparative example of the present embodiment. FIG. 27 is a timing chart showing an access exclusive control method using a lock variable in the microcomputer of FIG. 26. FIG. 28 is a diagram showing an example of time change of power consumption in the microcomputer of FIG. 26.

The embodiments will be described with reference to the drawings. It should be noted that the embodiments described below do not limit the invention according to the claims, and all of the elements and combinations thereof described in the embodiments are indispensable for the means for solving the invention. Is not always.

Further, in the following description, the "memory" is one or more entities for storing a program or data, and each memory is one or more non-volatile memory, volatile memory, ROM, RAM, First-In-First-. It can consist of an Out (FIFO) type buffer memory, a ring type buffer memory, an interleaved type buffer memory, an instruction cache, a data cache or a register. A part or all of the memory may be formed on the same silicon chip as the microcomputer (also referred to as a microcomputer), or may be formed on a different silicon chip. The memory may further include a non-volatile external storage device (eg, a hard disk drive or solid state drive, a recording medium such as a memory card) accessible via the memory address space of the microcomputer.

Further, in the following description, the microcomputer is a multi-core microcomputer including a plurality of arithmetic elements (processor elements, PE). The implementation of one or more CPU cores constituting the PE may be a non-superscalar system including one instruction execution unit, or a superscalar system including two or more instruction execution units. For the purpose of detecting a failure or malfunction of a PE or a CPU core, a lock step configuration may be adopted in which one PE is configured and the same program is physically executed simultaneously on a plurality of CPU cores. The microcomputer may include a hardware circuit (for example, Direct Memory Access Controller, DMAC) that executes memory access independently of the CPU core or based on an instruction from the CPU core.

Further, in the following description, the function may be described by the expression of "kkk part", but the function may be realized by executing one or more programs in the instruction execution unit, or one or more. It may be realized by a hardware circuit (for example, Field Programmable Gate Array (FPGA) or Application Special Integrated Circuit (ASIC)). When the function is realized by the instruction execution unit, the function may be at least a part of the instruction execution unit because the defined processing is appropriately performed by using the memory and / or the external interface for communication. The process described with the function as the subject may be a process performed by an instruction execution unit or a CPU core having the instruction execution unit. Further, the instruction execution unit may include a hardware circuit that performs a part or all of the processing. The program may be installed from the program source in one or more memories accessible to the microcomputer. The program source may be, for example, a specific area on the non-volatile memory or a recording medium (for example, a memory card) readable by the microcomputer. The description of each function is an example, and a plurality of functions may be combined into one function, or one function may be divided into a plurality of functions.

Further, in the following description, when the same type of element is not distinguished, the reference code or the common number in the reference code is used, and when the same type of element is described separately, the reference code of the element is used. Alternatively, the ID assigned to the element may be used instead of the reference code.

FIG. 1 is a block diagram showing a configuration example of a microcomputer applied to the electronic control device according to the first embodiment.
In FIG. 1, the microcomputer 1 includes a plurality of PE10, 20-1, 20-2, 20-3, a shared resource 30, a usage request register 50, and a usage authority control device 60 as built-in function modules. PE10, 20-1, 20-2, 20-3 can be used as arithmetic elements. The PE 10, 20-1, 20-2, 20-3, the shared resource 30, the usage request register 50, and the usage authority control device 60 are interconnected via the PE-to-PE connection bus 40. The PE 10 and the usage authority control device 60 may be mounted on the same silicon chip or may be mounted on different silicon chips. The usage authority control device 60 may be the usage authority control device 60A shown in FIG. PE10 operates as a master PE that executes a shared resource management program. PE20-1, 20-2, and 20-3 operate as satellite PEs that execute user programs (hereinafter also referred to as applications) other than the shared resource management program. The application may be operated by the master PE. By executing the shared resource management program by PE10, it is possible to realize the allocation process of the shared resource 30 based on the policy information regarding the allocation of the shared resource 30 among PE20-1, 20-2, and 20-3. .. Each PE20-1, 20-2, 20-3 requests the use of the shared resource 30, and is based on the usage authority of the shared resource 30 allocated in a time-division manner in response to the request for the use of the shared resource 30. The shared resource 30 can be used exclusively.

At this time, PE20-1, 20-2, and 20-3 store the usage request of the shared resource 30 in the usage request register 50. The PE 10 accepts a request for use of the shared resource 30 from PE 20-1, 20-2, 20-3 based on the request state held in the usage request register 50. Then, the PE 10 executes scheduling of the use of the shared resource 30 between PE 20-1, 20-2, and 20-3 that have received the usage request, based on the policy information regarding the allocation of the shared resource 30. The usage authority control device 60 grants the usage authority of the shared resource 30 to PE20-1, 20-2, and 20-3 based on the scheduling result of the use of the shared resource 30. PE20-1, 20-2, and 20-3 exclusively use the shared resource 30 based on the usage authority granted by the usage authority control device 60.

Here, the policy information regarding the allocation of the shared resource 30 can be set individually on the software or firmware for each of PE20-1, 20-2, and 20-3. Therefore, the shared resource 30 is used for PE20-1, 20-2, 20-3 according to the processing content of PE20-1, 20-2, 20-3 and the degree of harm when the processing is delayed. The priority and usage time can be set flexibly, and even when the number of PE20-1, 20-2, 20-3 using the shared resource 30 increases, PE20-1, 20-2, 20- It becomes possible to maintain the real-time property of the processing of 3.

Further, PE10 executes scheduling of use of the shared resource 30, and the use authority control device 60 grants the use authority of the shared resource 30 to PE20-1, 20-2, 20-3, whereby PE20-1, 20. It is no longer necessary for PE10, 20-1, 20-2, 20-3 to manage the occupied state and released state of the shared resource 30 by -2, 20-3, and PE10, 20-1, 20-2, 20-3. It is possible to reduce the load on the.

Further, the usage authority control device 60 manages the usage authority of the shared resource 30, so that the shared resource 30 is used between PE20-1, 20-2, and 20-3 in synchronization with the control cycle managed by the real-time OS. It is not necessary to switch the authority, and the particle size of the usage time of the shared resource 30 of PE20-1, 20-2, 20-3 can be made finer. Therefore, PE20-1, 20-2, while allowing the shared resource 30 to be used at least once for PE20-1, 20-2, 20-3 that have issued a usage request within one control cycle, The occupancy time of the shared resource 30 can be made different according to the priority of 20-3, and it is possible to improve the utilization efficiency of the shared resource 30 while maintaining the real-time performance of the processing in the multi-core microcomputer.

Further, PE20-1, 20-2, and 20-3 store the usage request of the shared resource 30 in the usage request register 50, and PE10 stores the usage request of the shared resource 30 in the usage request register 50. By accepting the request for use of the shared resource 30 from 20-2, 20-3, PE20-1, 20-2, 20-3 request the use of the shared resource 30 until the right to use the shared resource 30 is granted. It is not necessary to issue the number of times, and it is possible to suppress the decrease in calculation efficiency due to the spinlock.

Hereinafter, the configuration of the microcomputer 1 of FIG. 1 will be specifically described.
PE10 is executed by one or more CPU cores 100-0 that execute a program created according to a predetermined instruction set architecture, interrupt controllers 110-0 that control interrupt requests related to PE10, and CPU cores 100-0. A bus interface 120-0 that controls access between the PE 10 and the PE-to-PE connection bus 40 in response to an access request from the program, and a cache memory and / or RAM memory that stores the program and / or data necessary for program execution. It includes a PE internal memory 130-0 including a control table 140 for storing policy information necessary for access control of the shared resource 30.

The interrupt controller 110-0 uses the interrupt controller connection interface 111-0, the bus interface 120-0 uses the bus interface connection interface 121-0, and the PE internal memory 130 uses the PE internal memory-CPU core connection interface 132-0. It is interconnected with the CPU core 100-0. Further, the PE internal memory 130-0 is interconnected with the PE internal memory-bus interface connection interface 131-0, and the control table 140 is interconnected with the bus interface 120-0 by the control table connection interface 141. At least the usage authority control interrupt signal 61 output by the usage authority control device 60 is input to the interrupt controller 110-0 as a signal indicating an interrupt request to the PE 10. The control table 140 is either a memory independent of the PE internal memory 130-0, a part of the PE internal memory 130-0, or a memory outside the PE 10 (not shown) connected to the PE-to-PE connection bus 40. It may be configured as a table.

The PE20-1 is one or more CPU cores 100-1 that execute a program created according to a predetermined instruction set architecture common to the PE10, an interrupt controller 110-1 that controls interrupt requests related to the PE20-1, and a CPU. Necessary for bus interface 120-1, program, and / or program execution that controls access between PE20-1 and PE-to-PE connection bus 40 in response to an access request from a program executed on core 100-1. A PE internal memory 130-1 including a cache memory for storing data and / or a RAM memory is included. The interrupt controller 110-1 uses the interrupt controller connection interface 111-1, the bus interface 120-1 uses the bus interface connection interface 121-1, and the PE internal memory 130-1 uses the PE internal memory-CPU core connection interface 132-1. , Each are interconnected with the CPU core 100-1. Further, the PE internal memory 130-1 is interconnected with the bus interface 120-1 by the PE internal memory-bus interface connection interface 131-1. At least the usage authority control interrupt signal 62-1 output by the usage authority control device 60 is input to the interrupt controller 110-1 as a signal indicating an interrupt request to PE20-1.

PE20-2 and 20-3 can be configured in the same manner as PE20-1. To the interrupt controller of PE20-2, 20-3, at least the usage authority control interrupt signal 62-2, 62-3 output by the usage authority control device 60 as a signal indicating an interrupt request for the PE20-2, 20-3. Is entered. The usage authority control interrupt signals 62-1, 62-2, and 62-3 are independent signals for each of PE20-1, 20-2, and 20-3.

The shared resource 30 is a resource shared by a plurality of applications operating on PE20-1, 20-2, 20-3 in a time-division manner under the control of a shared resource management program. The shared resource 30 includes one or more microcomputer built-in peripheral modules such as a communication module that controls communication with hardware connected to the outside of the microcomputer 1, and PE10, 20-1, 20-2, 20. -3 It may be at least a part of one or more memories connected to the inside or the outside. For the sake of simplicity, only one shared resource 30 is shown, but two or more shared resources 30 may be used.

FIG. 2 is a block diagram showing a configuration example of the usage authority control device of FIG.
In FIG. 2, the usage authority control device 60 is a bus interface 600 that controls access to a control register inside the usage authority control device 60 via the PE-to-PE connection bus 40, and four hardware timer channels 610-1 and 610-2. , 610-3, 610-4, generate trigger control signals 612-1, 612-2, 612-3, 612-4 for each hardware timer channel 610-1, 610-2, 610-3, 610-4. Includes a trigger control unit 620 to generate an interrupt request control unit 630 that generates use authority control interrupt signals 61, 62-1, 62-2, 62-3 to PE10, 20-1, 20-2, 20-3, respectively. .. The trigger control unit 620 outputs the trigger control signals 612-1, 612-2, 612-3, 612-4 independently for each hardware timer channel 610-1, 610-2, 610-3, 610-4. do. The number of hardware timer channels 610-1, 610-2, 610-3, 610-4 is equal to or greater than the number of satellite PEs in which the application using the shared resource 30 operates. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 is interrupted by the hardware timer channel connection interface 611, the trigger control unit 620 is interrupted by the trigger control unit connection interface 621, and the interrupt request control unit 630 is interrupted. Each is interconnected with the bus interface 600 by the request control unit connection interface 631.

The hardware timer channels 610-1, 610-2, 610-3, and 610-4 have a channel status register 615 indicating the operating state of the channel, a current count value register 616 holding the current count value, and a current count value register 616 at the start of counting. An initial count value register 617 for holding an initial count value to be loaded into the count value register 616 is independently provided for each channel. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 requests access from the hardware timer channel connection interface 611 to the channel status register 615, the current count value register 616, and the initial count value register 617. In response to, read / write to / from the specified channel status register 615, current count value register 616, and initial count value register 617 is executed. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 has at least two states, which can be identified by the contents of the channel status register 615, that is, counting is in operation and counting is stopped. It has the function of.

(1) When the trigger control signals 612-1, 612-2, 612-3, and 612-4 instruct the start of the counting operation of the own channel, the contents of the initial count value register 617 are changed to the current count value register 616. And update the contents of the channel status register 615 to a value indicating that the count is in progress. At this time, when the content of the current count value register 616 is larger than the lower limit value (for example, zero) defined in advance by a means (not shown), the content of the current count value register 616 is decremented every time a predetermined time elapses. ..

(2) When the trigger control signals 612-1, 612-2, 612-3, and 612-4 instruct the stop of the counting operation of the own channel, the content of the channel status register 615 indicates that the counting is stopped. Is updated to, and the contents of the current count value register 616 are retained.

(3) While the hardware timer channels 610-1, 610-2, 610-3, and 610-4 are counting, the contents of the current count value register 616 of the channel are not equal to or less than the lower limit. The comparison results that are true / false respectively are output as the timer value comparison result signal of the own channel among the timer value comparison result signals 613-1, 613-2, 613-3, and 613-4.

Note that the count stop instruction for the hardware timer channels 610-1, 610-2, 610-3, and 610-4 during which the count is stopped is ignored as an invalid instruction. Further, the count start instruction for the hardware timer channels 610-1, 610-2, 610-3, and 610-4 during the count operation is interpreted as a valid instruction to continue the count operation. However, it may be possible to select whether or not to copy the contents of the initial count value register 617 to the current count value register 616 according to the count start instruction by means (not shown).

The trigger control unit 620 simultaneously instructs one or more hardware timer channels 610-1, 610-2, 610-3, 610-4 to start counting in a bitmap format start trigger register 625, and stops counting at the same time. It is provided with a bitmap type stop trigger register 626 for instructing. The trigger control unit 620 responds to an access request to the start trigger register 625 and the stop trigger register 626 from the trigger control unit connection interface 621 so that writing to the specified start trigger register 625 and the stop trigger register 626 is executed. Configure. At the time of writing to the start trigger register 625, one or more of the trigger control signals 612-1, 612-2, 612-3, 612-4 in which the field value (for example, the value 1) indicating the start of counting is set. As the trigger control signals 612-1, 612-2, 612-3, 612-4 that output the trigger to the hardware timer channels 610-1, 610-2, 610-3, 610-4 of the above. A predetermined signal instructing the start of counting is output at the same time. For hardware timer channels 610-1, 610-2, 610-3, 610-4 for which other field values (for example, value 0) are set, the trigger control signal to the channel 612-1, As 612-2, 612-3, and 612-4, predetermined signals instructing the maintenance of the channel state are simultaneously output.

Further, at the time of writing to the stop trigger register 626, among the trigger control signals 612-1, 612-2, 612-3, and 612-4, the field value (for example, value 1) instructing the count stop is set 1. Trigger control signals 612-1, 612-2, 612-3, 612-that output a trigger to one or more hardware timer channels 610-1, 610-2, 610-3, 610-4. As No. 4, a predetermined signal instructing the stop of counting is output at the same time. For hardware timer channels 610-1, 610-2, 610-3, 610-4 for which other field values (for example, value 0) are set, the trigger control signal to the channel 612-1, As 612-2, 612-3, and 612-4, predetermined signals instructing the maintenance of the channel state are simultaneously output.

The interrupt request control unit 630 includes hardware timer channels 610-1, 610-2, 610-3, 610-4 and PE10, 20-1, 20-2, 20-3 (that is, each PE10) to be interrupted. , 20-1, 20-2, 20-3, channel mapping register 637, which defines the association with the usage authority control interrupt signal 61, 62-1, 62-2, 62-3), and the target of the interrupt request. Interrupt factor register 635, interrupt request target that holds the occurrence status of the event (hereinafter referred to as the interrupt request target event) for each of the interrupt destinations PE10, 20-1, 20-2, 20-3, and for each factor. It includes an interrupt enable register 636 that sets whether to allow an interrupt request when an event occurs for each of the interrupt destinations PE10, 20-1, 20-2, 20-3, and for each factor. The interrupt request control unit 630 responds to an access request from the interrupt request control unit connection interface 631 to the interrupt factor register 635, the interrupt enable register 636, and the channel mapping register 637, and the designated interrupt factor register 635, the interrupt enable register 636, and the interrupt enable register 636. It is configured to read and write to the channel mapping register 637.

Timer value comparison result signals 613-1, 613-2, 613-3, 613-4 output by each hardware timer channel 610-1, 610-2, 610-3, 610-4 are interrupt request target events. A true transition from false, that is, a detection that the current count value is equal to or less than a predetermined lower limit value in the hardware timer channels 610-1, 610-2, 610-3, 610-4 during the counting operation. do. At this time, the interrupt request control unit 630 identifies the PE10, 20-1, 20-2, 20-3 to be associated with the channel mapping register 637, and the PE10, 20-1, 20-2, In the interrupt factor register 635 that holds the occurrence state of the interrupt request target event to 20-3, a predetermined value (for example, value 1) is set in the field indicating the end event of the usage authority grant period.

If the interrupt enable register 636 is set to enable the interrupt request when the usage authority grant period end event occurs in the PE10, 20-1, 20-2, 20-3, the usage authority control interrupt signal is further set. An interrupt to the PE10, 20-1, 20-2, 20-3 is requested via 61, 62-1, 62-2, 62-3. In PE10, 20-1, 20-2, and 20-3 that have detected an interrupt request from the usage authority control device 60, the processing main body is used as a part of the processing of the interrupt handler operating in any CPU core in the own PE. After the execution of, the field value indicating the occurrence of the usage authority grant period end event is updated to an invalid value (for example, the value 0) by writing to the interrupt cause register 635, and the interrupt request by the event is invalidated.

Here, PE20-1, 20-2, and 20-3 can release the shared resource 30 based on the interrupt from the usage authority control device 60. Therefore, even when the usage time of the shared resource 30 is set individually for each of PE20-1, 20-2, and 20-3, PE20-1, 20-2, and 20-3 use the shared resource 30. The shared resource 30 can be released without monitoring the time, and the load on PE20-1, 20-2, and 20-3 can be reduced.

FIG. 3 is a block diagram showing a modified example of the usage authority control device of FIG. Of the usage authority control device 60A, the elements having the same reference numerals as the usage authority control device 60 of FIG. 2 are common, so a part of the description will be omitted.
In FIG. 3, the usage authority control device 60A is a bus interface 600 that controls access to a control register inside the usage authority control device 60A via the PE-to-PE connection bus 40, and four hardware timer channels 610-1 and 610-2. , 610-3, 610-4, hardware timer channels 610-1, 610-2, 610-3, 610-4 to generate trigger control signals 612-1, 612-2, 612-3, 612-4. It includes a trigger control unit 620 and an interrupt request control unit 630A that generates use authority control interrupt signals 61, 62-1, 62-2, 62-3 to PE10, 20-1, 20-2, 20-3, respectively. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 is interrupted by the hardware timer channel connection interface 611, the trigger control unit 620 is interrupted by the trigger control unit connection interface 621, and the interrupt request control unit 630A is interrupted. Each is interconnected with the bus interface 600 by the request control unit connection interface 631.

The configurations and functions of the hardware timer channels 610-1, 610-2, 610-3, 610-4 and the trigger control unit 620 of the usage authority control device 60A are the same as those of the usage authority control device 60.

The interrupt request control unit 630A includes hardware timer channels 610-1, 610-2, 610-3, 610-4 and PE10, 20-1, 20-2, 20-3 (that is, each PE10, which is an interrupt destination). Channel mapping register 637, which defines the association with the usage authority control interrupt signal 61, 62-1, 62-2, 62-3) connected to 20-1, 20-2, 20-3, interrupt request target event. Interrupt factor register 635A that holds the occurrence status for each of PE10, 20-1, 20-2, 20-3, which is the interrupt destination, and for each factor, whether to allow interrupt request when an interrupt request target event occurs. It includes an interrupt enable register 636A that is set for each of PE10, 20-1, 20-2, 20-3, which is an interrupt destination, and for each factor. The interrupt request control unit 630A responds to an access request from the interrupt request control unit connection interface 631 to the interrupt factor register 635A, the interrupt enable register 636A, and the channel mapping register 637, and the designated interrupt factor register 635A, the interrupt enable register 636A, and the interrupt enable register 636A. It is configured to read and write to the channel mapping register 637.

In this modification, in addition to the timer value comparison result signals 613-1, 613-2, 613-3, 613-4 output by each hardware timer channel 610-1, 610-2, 610-3, 610-4. Of the trigger control signals 621-1, 612-2, 612-3, and 612-4 output by the trigger control unit 620, at least the trigger control signal capable of identifying the count start instruction is also an interrupt request target event. As an interrupt request target event, the timer value comparison result signals 613-1, 613-2, 613-3, 613-4 truly transition from false to true, that is, the hardware timer channels 610-1, 610-2 during the counting operation. , 610-3, 610-4, it is assumed that it is detected that the current count value is equal to or less than a predetermined lower limit value. At this time, the interrupt request control unit 630A identifies the PE10, 20-1, 20-2, 20-3 to be associated with the channel mapping register 637, and the PE10, 20-1, 20-2, In the interrupt factor register 635A that holds the occurrence state of the interrupt request target event to 20-3, a predetermined value (for example, value 1) is set in the field value indicating the event for which the usage authority grant period ends. If the interrupt enable register 636A is set to enable the interrupt request when the usage authority grant period end event occurs in the PE10, 20-1, 20-2, 20-3, the usage authority control interrupt signal is further set. An interrupt to the PE10, 20-1, 20-2, 20-3 is requested via 61, 62-1, 62-2, 62-3.

In addition, when the trigger control signals 612-1, 612-2, 612-3, and 612-4 instruct the start of counting as the interrupt request target event, the interrupt request control unit 630A is set in the channel mapping register 637. An interrupt factor register that identifies the PE10, 20-1, 20-2, 20-3 to be associated, and holds the occurrence state of the event for which an interrupt request is made to the PE10, 20-1, 20-2, 20-3. In 635A, a predetermined value (for example, value 1) is set in the field value indicating the usage authority grant period start event. If the interrupt enable register 636A is set to enable the interrupt request when the usage authority grant period start event occurs in the PE10, 20-1, 20-2, 20-3, the usage authority control interrupt signal is further set. An interrupt to the PE10, 20-1, 20-2, 20-3 is requested via 61, 62-1, 62-2, 62-3.

In PE10, 20-1, 20-2, and 20-3 that have detected an interrupt request from the usage authority control device 60A, the processing main body is used as a part of the processing of the interrupt handler operating in any CPU core in the own PE. The contents of the interrupt factor register 635A are read out prior to the execution of, and the interrupt factor (use permission grant period start or end event) is specified. After the processing body is executed, the field value indicating the occurrence of the event specified above is updated to an invalid value (for example, value 0) by writing to the interrupt factor register 635A, and the interrupt request due to the event is invalidated. ..

Here, PE20-1, 20-2, and 20-3 can start using the shared resource 30 or release the shared resource 30 based on an interrupt from the usage authority control device 60A. Therefore, even when the usage start timing and usage time of the shared resource 30 are individually set for each of PE20-1, 20-2, and 20-3, PE20-1, 20-2, and 20-3 are shared. The shared resource 30 can be used exclusively without monitoring the usage status of the resource 30. Therefore, when it is necessary to use the shared resource 30, each PE 20-1, 20-2, 20-3 does not have to keep issuing a request to use the shared resource 30 until the authority to use the shared resource 30 is obtained. , PE20-1, 20-2, 20-3 can be reduced.

Normally, two interrupt factors, that is, the start and end events of the usage authority grant period are not detected at the same time, and the interrupt factor can be identified by referring to the contents of the interrupt factor register 635A. The usage authority control interrupt signals 61, 62-1, 62-2, 62-3 to be output to 20-1, 20-2, 20-3 may be shared among a plurality of events. Further, the usage authority control device 60A may be configured so that the count start request for the hardware timer channels 610-1, 610-2, 610-3, and 610-4 during the counting operation can be masked by means (not shown). ..

FIG. 4 is a diagram showing a modification of the microcomputer of FIG. 1. Since the elements of the microcomputer 1B having the same reference numerals as those of the microcomputer 1 shown in FIG. 1 are common, a part of the description thereof will be omitted.
In FIG. 4, the microcomputer 1B further includes an inter-PE interrupt control device 70 as a built-in function module. The inter-PE interrupt control device 70 is interconnected with PE 10, 20-1, 20-2, and 20-3 via the inter-PE connection bus 40. The inter-PE interrupt control device 70 includes a control register accessible from each PE 10, 20-1, 20-2, 20-3. The interrupt requesting source PE requests an interrupt to its own PE or another PE, and the interrupt requesting destination PE is provided with means for specifying the interrupt requesting source PE. Further, the inter-PE interrupt control device 70 uses the inter-PE interrupt signals 71-0, 71-1, 71-2, and 71-3 as independent signals, which indicate the inter-PE interrupt request status for the PE for each interrupt destination PE. It is output and input to the interrupt controller in PE10, 20-1, 20-2, 20-3, respectively.

Here, when the inter-PE interrupt control device 70 receives the release notification of the shared resource 30 from PE20-1, 20-2, 20-3, the PE 10 can be notified of the occurrence of the resource release event. Upon receiving the notification of the occurrence of the resource release event, the PE 10 can rescheduling the use of the shared resource 30 among the PE 20-1, 20-2, and 20-3 that are requesting the use of the shared resource 30. .. Therefore, in PE20-1, 20-2, 20-3 to which the usage authority of the shared resource 30 is granted, the shared resource is used before the usage time given to PE20-1, 20-2, 20-3 is used up. Even when 30 is released, PE20-1, 20- requesting the use of the shared resource 30 without waiting for the elapse of the usage time given to PE20-1, 20-2, 20-3. It becomes possible for 2, 20-3 to use the shared resource 30, and it becomes possible to improve the utilization efficiency of the shared resource 30.

FIG. 5 is a diagram showing a configuration example of the control table of FIG.
In FIG. 5, the control table 140 can store the control policy regarding the shared resource 30 among PE10, 20-1, 20-2, 20-3. The PE 10 can schedule the use of the shared resource 30 among the PE 20-1, 20-2, and 20-3 that have received the usage request by referring to the control table 140 when the shared resource management program is executed. can.

The control table 140 stores a control policy to be referenced and updated when the order of granting the usage authority of the shared resource 30 to each PE10, 20-1, 20-2, and 20-3 is controlled by executing the shared resource management program. It is an area. The control table 140 includes the following fields for each of the PE10, 20-1, 20-2, and 20-3 to be shared control.
For the sake of simplicity of the following description, unless otherwise specified, PE10 having the smallest PE identifier among the plurality of PE10s, 20-1, 20-2, and 20-3 provided in the microcomputers 1 and 1B, that is, PE0 is used as PE10. In the ascending order of the PE identifier, PE1, PE2, and PE3 are designated as PE20-1, 20-2, and 20-3, respectively.

(1) Enable (EN) field: A field indicating whether or not the settings of the following fields related to the PE10, 20-1, 20-2, and 20-3 are valid. If an application running on the PE10, 20-1, 20-2, 20-3 can request the use of the shared resource 30, it must be enabled.

(2) Priority, PR field: Zero or a positive integer indicating the priority when granting the right to use the shared resource 30 to the PE10, 20-1, 20-2, 20-3. Is. The smaller the value, the higher the priority, and the earlier the order of granting the usage authority of the shared resource 30.

(3) Upper limit time within the control cycle (Permitted Time, PT) field: An upper limit of the shared resource usage time that can be assigned to the PE10, 20-1, 20-2, 20-3 for each control cycle. Set a value based on either an absolute value or a percentage of the control cycle time. At any time, the result of adding the set values of this field for all PE10, 20-1, 20-2, 20-3 for which the EN field is valid is the control cycle time (when the absolute value is used as an index) or 100. Do not exceed% (when the percentage is used as an index). This constraint may be imposed on the user as a constraint necessary for the normal operation of the microcomputers 1 and 1B, or as a part of the function provided by the shared resource management program, the presence or absence of a constraint violation is detected during operation, and the constraint violation is detected. If this is the case, a predetermined error process such as log acquisition may be executed. In addition, in order to compensate for control errors due to variations in processing time related to shared resource management, control cycle time (when using an absolute value as an index) or 100% (when using a ratio as an index) when checking for violations of the above constraints. It may be compared with the value obtained by subtracting the predetermined grace time or the grace rate from.

(4) Re-grant of authority within control cycle (Re-Grant, RG) field: In one control cycle, PE10, 20-1, 20-2, 20-3 are shared resources up to the set value of the PT field. Specifies whether to allow 30 to be divided into a plurality of times and used. This field may be an option, in which case it is interpreted that the prohibition of split use is specified.

(5) Order for granting authority within the control cycle (Order, OR) field: This field is updated every control cycle by the shared resource management program based on a predetermined order determination algorithm. The set value is a zero or a positive integer indicating the order of granting the authority to use the shared resource in the current control cycle, and each PE10, 20-1, 20- so that the value set in this field is in ascending order from zero. The right to use is granted to 2, 20-3 in a timely manner. Depending on the order determination algorithm to be used, this field may be an option. For example, when there is a request to use one or more shared resources 30 at the time of switching the use permission destination PE, the PE with the highest priority is set. If there is no request to use the shared resource 30, the permission may be dynamically granted to the user, and the request to use the shared resource 30 may be polled at a predetermined cycle until the request is generated.

(6) Remaining time in control cycle (Remaining Time, RT) field: Holds the remaining time of the usage time of the shared resource 30 that can be assigned to the PE10, 20-1, 20-2, 20-3 in the current control cycle. It is a field to do. The absolute value of time divided by the decrement operation cycle of the hardware timer channels 610-1, 610-2, 610-3, 610-4, that is, the hardware timer channels 610-1, 610-2, 610-3, It can be written directly to the initial count value register 617 or the current count value register 616 of 610-4, or can be a positive integer value obtained by converting the magnitude of the value into a value that can be directly compared. This field value is reset by the value obtained by converting the value of the PT field according to the above procedure for each control cycle, and the period for granting the right to use the shared resource 30 to a certain PE10, 20-1, 20-2, 20-3 is set. This field value for PE10, 20-1, 20-2, 20-3 is updated every time the end or the end of use of the shared resource 30 is notified from PE10, 20-1, 20-2, 20-3. Is controlled to do. The update value newly set in this field may be zero, or a count value corresponding to the remaining time obtained by subtracting the actual usage time of the shared resource 30 from the current setting value.

(7) Flag for granting usage authority (In-Use, IU) field: Flag indicating whether the usage authority for the shared resource 30 is being granted to the PE10, 20-1, 20-2, 20-3. Is. The number of PEs to which the shared resource management program grants the usage authority at the same time is at most 1, and only 0 or 1 of the fields corresponding to the number of PEs is true.

FIG. 6 is a diagram showing a configuration example of the usage request register of FIG. Note that FIG. 6 shows the internal configuration of the usage request register 50, the flag that holds the presence / absence of the usage request of the shared resource 30 for each request source PE, and the register-to-register mapping related to the flag setting / clearing means.
In FIG. 6, the use request register 50 is accessible from PE10, 20-1, 20-2, and 20-3 via the PE-to-PE connection bus 40, and is one of the address spaces of the microcomputers 1 and 1B. It can be placed in a local area. The usage request register 50 is composed of two usage request register banks having different addresses, that is, a usage request register bank 50-0 (Bank-0) and a usage request register bank 50-1 (Bank-1).

The functions of the usage request register banks 50-0 and 50-1 are common among the banks except for the difference in the address assigned to the control register which is a component. Of the two usage request register banks 50-0 and 50-1, for example, one of the banks is referred to by the common resource management program operating on the PE 10 for controlling the granting of the usage authority of the shared resource 30 in the current control cycle. A bank (hereinafter referred to as a front bank), and the other is a bank (hereinafter referred to as a back bank) that accumulates requests for allocation of usage authority of the shared resource 30 in the next control cycle from an application running on PE20-1, 20-2, 20-3. It may be assigned as a bank), and the front and back banks may be switched and used for each control cycle. For the purpose of simplifying the address generation procedure of the back bank to be accessed by the application, a register (not shown) that stores a flag that identifies the allocation state of the front and back banks and the address area of the front and back banks are determined by the state of the flag. By further providing a replacement address translation unit (not shown) in the usage request register 50, it may be provided with a function of fixing the addresses of the front and back banks regardless of the bank allocation status. A part or all of the usage request register 50 may be implemented as a specially designed hardware module, or at least a part may be allocated to the memory connected to the inside or the outside of the microcomputers 1 and 1B. Further, due to implementation restrictions, the usage request register 50 may be configured as one bank having only the usage request register banks 50-0. The method of using the usage request register banks 50-0 and 50-1 in the configuration of one bank or two banks will be described later together with the detailed control flow of granting the usage authority of the shared resource 30.

The usage request register banks 50-0 and 50-1 have a usage request flag register that holds the presence / absence of a usage request of the shared resource 30 in a bitmap format for each request source PE, and a usage request flag stored in the usage request flag register. Is provided individually for each PE10, 20-1, 20-2, 20-3, or as a means for collectively setting / clearing a plurality of PEs, the following control registers are provided.

(1) Shared resource usage request set register 520-0, 520-1, 520-2, 520-3: PE10, 20-1, 20-2, 20-3 set the usage request flag of the shared resource 30, respectively. It is a 32-bit wide register that serves as an interface. From the registers SET_REF_REG0 (for requests from PE10), SET_RQ_REG1 (for requests from PE20-1), SET_RQ_REG2 (for requests from PE20-2), and SET_RQ_REG3 (for requests from PE20-3) that are independent for each requesting PE. It is composed. An application that operates on each PE10, 20-1, 20-2, 20-3 and requests the permission to use the shared resource 30 uses the shared resource for its own PE within a predetermined time window in the control cycle. The value 1 is written to the flag set request fields SR0, SR1, SR2, SR3 in the request set register 520-0, 520-1, 520-2, 520-3. Each flag set request field SR0, SR1, SR2, SR3 is mapped to the flag fields RQ0, RQ1, RQ2, RQ3 independent for each request source PE in the shared resource use request flag register 510, and the set request is made. The flag RQn (n = 0, 1, 2, 3) is set to the value 1 in response to the writing of the value 1 to SRn (n = 0, 1, 2, 3). It is assumed that the zero value is always read when reading this register.

(2) Shared resource use request flag register 510: Flag fields RQ0, RQ1, RQ2, RQ3 that hold in bitmap format whether or not there is a request to use the shared resource 30 by PE10, 20-1, 20-2, 20-3, respectively. Is a 32-bit wide read-only register FLG_REF_REG that aggregates the above into one register. Read by the shared resource management program running on PE10.

(3) Shared resource usage request clear register 530: A 32-bit wide register CLR_RQ_REG in which PE10, 20-1, 20-2, and 20-3 serve as an interface for clearing the usage request flag of the shared resource 30, respectively. The shared resource management program running on PE10 writes. The flag fields CR0, CR1, CR2, and CR3 independently mapped for each of the flag fields RQ0, RQ1, RQ2, and RQ3 of the shared resource usage request flag register 510 to be cleared are aggregated in one register and cleared. The flag field RQn (n = 0, 1, 2, 3) is cleared to the value 0 in response to the writing of the value 1 to the request field CRn (n = 0, 1, 2, 3). At the time of reading, a zero value is always read.

FIG. 7 is a diagram showing a configuration example of the inter-PE interrupt control device of FIG. Note that FIG. 7 shows the internal configuration of the PE-to-PE interrupt control device 70, the flag that holds the presence / absence of the PE-to-PE interrupt request for each combination of the request source / request destination PE, and the register-to-register mapping related to the flag setting / clearing means. rice field.
In FIG. 7, the inter-PE interrupt control device 70 is accessible from each of PEs 10, 20-1, 20-2, and 20-3 via the inter-PE connection bus 40, and is one on the address space of the microcomputer 1B. Includes multiple control registers located in the area. Part or all of the control registers may be implemented as a dedicatedly designed hardware module, or at least a part may be allocated to the memory connected to the inside or the outside of the microcomputer 1B. The inter-PE interrupt control device 70 collects the presence or absence of an inter-PE interrupt in an independent register for each request destination PE, and holds the presence or absence of the inter-PE interrupt in a bitmap format regarding the request source PE from a specific request source PE. For interrupt requests, individually for each request destination PE, or as a means to collectively set multiple request destination PEs, and for the inter-PE interrupt request flag targeting a specific request destination PE, individually for each request source PE. Or, as a means for clearing a plurality of request source PEs at once, the following control registers are provided.

(1) PE-to-PE interrupt request set register 720-n (n = 0, 1, 2, 3): Set the PE-to-PE interrupt request flag with PE10, 20-1, 20-2, 20-3 as the request source PE, respectively. It is a 32-bit wide register that serves as an interface when setting. From the registers SET_IPIR_REG0 (for requests from PE10), SET_IPIR_REG1 (for requests from PE20-1), SET_IPIR_REG2 (for requests from PE20-2), and SET_IPIR_REG3 (for requests from PE20-3) that are independent for each requesting PE. It is composed. An application that operates on each PE10, 20-1, 20-2, 20-3 and requests the transmission of a message based on a predetermined format from the own PE or another PE is an interrupt request between PEs for the own PE (Pen). Of the flag set request fields SRn0, SRn1, SRn2, SRn3 in the set register 720-n (n = 0, 1, 2, 3), one or more fields corresponding to the PE that is the interrupt request destination from the own PE. Write the value 1 to.

The flag set request field SRnm (m = 0, 1, 2, 3) of the inter-PE interrupt request set register SET_IPIR_REGn (n = 0, 1, 2, 3) is an inter-PE interrupt request aggregated for each interrupt request destination PE. It is mapped to the field RQnm (n = 0, 1, 2, 3) of the flag register FLG_IPIR_REGm (m = 0, 1, 2, 3), and the field RQnm corresponds to the writing of the value 1 to the flag set request field SRnm. Is set to the value 1. It is assumed that the zero value is always read when reading this register.

(2) Inter-PE interrupt request flag register 710-m (m = 0, 1, 2, 3): About the inter-PE interrupt request flag whose request destination PEs are PE10, 20-1, 20-2, and 20-3, respectively. , A 32-bit wide read-only register that provides an interface that can acquire the requesting PE in an identifiable bitmap format. From the registers FLG_IPIR_REG0 (for request to master PE10), FLG_IPIR_REG1 (for request to PE20-1), FLG_IPIR_REG2 (for request to PE20-2), FLG_IPIR_REG3 (for request to PE20-3) independent for each request destination. It is composed. Normally, the application on the side where the inter-PE interrupt is requested identifies the request source of the inter-PE interrupt with its own PE (PEm) as the request destination, and the inter-PE interrupt request flag register 710-m (m = 0, Read from 1, 2, 3). Further, the interrupt signal 71-m (m = 0, 1, 2, 3) between PEs can be defined as the logical sum of the fields RQ0m, RQ1m, RQ2m, and RQ3m.

(3) PE-to-PE interrupt request clear register 730-m (m = 0, 1, 2, 3): Set the PE-to-PE interrupt request flag with PE10, 20-1, 20-2, 20-3 as the request destination PE, respectively. It is a 32-bit wide register that serves as an interface for clearing. From the independent registers CLR_IPIR_REG0 (for request to PE10), CLR_IPIR_REG1 (for request to PE20-1), CLR_IPIR_REG2 (for request to PE20-2), and CLR_IPIR_REG3 (for request to PE20-3) that are independent for each request destination PE. It is composed. Normally, the purpose of the application on the side where the PE-to-PE interrupt is requested clears the interrupt request from one or more PEs (PEn) that have completed processing among the PE-to-PE interrupts whose request destination is its own PE (PEm). Then, write to the PE-to-PE interrupt request clear register 730-m (m = 0, 1, 2, 3). The field CRnm (n = 0, 1, 2, 3) of the inter-PE interrupt request clear register CLR_IPIR_REGm (m = 0, 1, 2, 3) is the inter-PE interrupt request flag register FLG_IPIR_REGm (m = 0, 1, 2, 3). It is mapped to the field RQnm (n = 0, 1, 2, 3) of 3), and the field RQnm is cleared to the value 0 according to the writing of the value 1 to the field CRnm. It is assumed that the zero value is always read when reading this register.

Below, two main control models focusing on the relationship between the control cycle, which is the time unit of control, and the time window that accepts the usage request of the shared resource 30, in order to realize the control of granting the authority to use the shared resource based on the control policy. To explain.

8 (a) and 8 (b) are timing charts showing the relationship between the control cycle of the microcomputer of FIG. 1 and the shared resource usage request time window.
In FIGS. 8 (a) and 8 (b), the control cycle (Control Period) is an application running on the microcomputers 1 and 1B, or a system clock used as a reference for time management by a real-time OS that provides an execution environment of the application. It is a fixed time cycle generated based on (Tick). In principle, the operation of the application or / and the real-time OS is controlled in units of control cycles. In order to realize resource sharing control with a smaller time particle size than the control cycle, at least a part of the control state and control parameters related to the granting of usage authority of the shared resource 30 must be reset (initialized) for each control cycle, and shared. The grant period of the usage authority of the resource 30 is completed within a single control cycle, the permission is not granted across multiple control cycles, and one or more requests for granting the usage permission of the shared resource 30 in a specific control cycle. As a constraint, PE10, 20-1, 20-2, and 20-3 of PE10, 20-1, 20-2, and 20-3 may be subject to shared control so that the usage authority is granted at least once within the control cycle. In the following description, it is assumed that the application executed on the PE 10 does not request the use of the shared resource 30, but the generality of the usage authority grant control based on the control policy is not lost.

FIG. 8A is a control model in which the usage request register 50 has a one-bank configuration of only the usage request register banks 50-0. In this control model, one usage request register is used between the accumulation of usage authority allocation requests for the shared resource 30 from PE20-1, 20-2, and 20-3 and the reference of the request status from the shared resource management program. Share banks 50-0 in a time division manner. Therefore, the usage request acceptance window period W for accepting the shared resource usage request R in the control cycle is set only for the period specified from the beginning of each control cycle. PE20-1, 20-2, and 20-3, which require the assignment of usage authority, are the shared resource usage request set registers 520-1 and 520-2 of the usage request register bank 50-0 within the usage request acceptance window period W. The request flag of the shared resource usage request flag register 510 is set via 520-3. When one or more usage authority allocation requests are made within the usage request acceptance window period W, the shared resource management program operating on PE10 is based on the control policy specified in the control table 140, and the usage authority in the current control cycle is used. The granting order is determined A.

Subsequently, according to the determined granting order, PE20-1, 20-2, 20-3 to be granted the usage authority next are specified, and the hardware in the usage authority control device 60, 60A required for managing the authorization grant time is specified. Set and start S of the wear timer channels 610-2, 610-3, 610-4. PE20-1, 20-2, 20-3 to which the authority is granted can be used for polling the operating status of the hardware timer channels 610-2, 610-3, 610-4 associated with the own PE, or for the own PE. By detecting the permission grant start interrupt via the output usage authority control interrupt signals 62-1, 62-2, 62-3, it is recognized that the usage authority of the shared resource 30 has been granted to the own PE, and the shared resource is used. Execution U of the application using 30 is performed. Under the control of the shared resource management program, PE20-1, 20-2, and 20-3 to which the usage authority is granted can occupy the shared resource 30 until the interrupt for the end of authorization to the own PE is detected. ..

For example, in the control cycle (n-1), assuming that there is a shared resource usage request R from two PE20-1 and 20-3 within the usage request acceptance window period W, it is assumed that the shared resource usage request R is within the control cycle (n-1). The right to use the shared resource 30 is assigned to PE20-1 and 20-3 in a time-division manner. Then, PE20-1 and 20-3 execute the application by exclusively using the shared resource 30 within the control cycle (n-1). Further, in the control cycle (n), assuming that there are shared resource usage requests R from the three PE20-1, 20-2, and 20-3 within the usage request acceptance window period W, it is assumed that the shared resource usage request R is within the control cycle (n). The right to use the shared resource 30 is assigned to PE20-1, 20-2, and 20-3 in a time-division manner. Then, PE20-1, 20-2, and 20-3 execute the application by exclusively using the shared resource 30 within the control cycle (n).

As a result, resource sharing control with a smaller time particle size than each control cycle (n-1) and (n) can be realized, and the time particle size of the resource sharing control for each control cycle (n-1) and (n). Can be changed. Therefore, for example, in PE20-1 and 20-3 that issued the shared resource use request R in the control cycle (n-1), the shared resource 30 is used in PE20-1 within the control cycle (n-1). Even when the authority is assigned, the PE20-3 can acquire the authority to use the shared resource 30 within the control cycle (n-1), and the control cycle (n-1) after the control cycle (n-1). Since it is not necessary to wait for the execution U of the application until n) and (n + 1), it is possible to improve the calculation efficiency of PE20-3. A more detailed control flow will be described again with a separate figure.

FIG. 8B is a control model in which the usage request register 50 has a two-bank configuration of usage request register banks 50-0 and 50-1. In this control model, the usage request register banks 50-0, which are different for accumulating usage authority allocation requests for shared resources 30 from PE20-1, 20-2, and 20-3, and for referencing the request status from the shared resource management program, respectively. 50-1 can be assigned, and the time division sharing of the usage request register bank 50-0 described with reference to FIG. 8A becomes unnecessary. Therefore, for a specific control cycle (Control Period (n)), the whole is set as a usage request acceptance window period W (n + 1) for accepting the shared resource usage request R in the next control cycle (Control Period (n + 1)). can do. PE20-1, 20-2, and 20-3, which require the assignment of usage authority, are on the back bank side of the usage request register banks 50-0, 50-1 within the usage request acceptance window period W (n + 1). The request flag of the shared resource usage request flag register 510 is set via the shared resource usage request set register 520-1, 520-2, 520-3. A shared resource that operates on PE10 when there is one or more usage permission allocation requests on the front bank side as a result of switching the front / back banks of the usage request registers 50-0 and 50-1 at the beginning of each control cycle. The management program determines the order of granting the usage authority in the control cycle (n + 1) based on the control policy specified in the control table 140.

Subsequently, according to the determined granting order, PE20-1, 20-2, 20-3 to be granted the usage authority next are specified, and the hardware in the usage authority control device 60, 60A required for managing the authorization grant time is specified. Set and start S of the wear timer channels 610-2, 610-3, 610-4. PE20-1, 20-2, 20-3 to which the authority is granted are polled of the operating status of the hard-wet timer channels 610-2, 610-3, 610-4 associated with the own PE, or connected to the own PE. By detecting the permission grant start interrupt via the usage authority control interrupt signals 62-1, 62-2, 62-3, it is recognized that the usage authority of the shared resource 30 has been granted to the own PE, and the shared resource 30 is recognized. Execute the application that uses. Under the control of the shared resource management program, PE20-1, 20-2, and 20-3 to which the usage authority is granted can monopolize the shared resource 30 until the interrupt for the end of authorization to the own PE is detected. ..

In this control model, the application can be executed in the form of a software pipeline whose unit is the control cycle. Therefore, the porting work required to adapt the existing application to the control model in comparison with the control model of FIG. 8 (a). Can be reduced. A more detailed control flow will be described again with a separate figure.

Hereinafter, four typical control flows will be described in detail regarding the control of granting the authority to use shared resources based on the control policy.

<First shared resource usage permission grant control flow>
9 to 11 are flowcharts showing the operation of granting the authority to use the shared resource of the microcomputer according to the first embodiment.

In the first shared resource use authority grant control flow, the following cases are illustrated.
(1) The usage request register 50 has a configuration of one bank (only the usage request register bank 50-0), and is the usage request register bank S30.

(2) The usage authority control device is configured to be either 60 or 60A, and the interrupt request when the usage authority grant period end event occurs is set to permission for all PEs.

(3) Regarding the setting of the control table 140, the basic priority (PR) field of the master PE (PE0) can be converted to zero (highest priority), and the upper limit time (PT) field within the control cycle can be converted into the usage request acceptance window period. Set to a value, and disable the intra-control cycle reauthorization (RG) field for each of the master PE (PE0) and all satellite PEs (PE1, PE2, PE3).

(4) Only a predetermined time from the beginning of each control cycle is set as the usage request acceptance window period W, and the shared resource usage request from the satellite PE that needs to grant the usage authority of the shared resource 30 is accepted within the control cycle. ..

(5) Notification of the start timing of granting usage authority is to poll the operating status of the hardware timer channel associated with the own PE of the usage authority control devices 60 and 60A from the application running on each satellite PE. Realize with.

(6) The notification of the end timing of granting the usage authority is realized by requesting the application running on each satellite PE from the usage authority control devices 60 and 60A to interrupt with the occurrence of the usage authority grant period end event.

The hardware timer channel S41 provided in the usage authority control devices 60 and 60A is associated with the PEN which is the first satellite PE, and controls the end timing of granting the shared resource usage authority to at least the PEN and the application S40 running on the Pen. do. Similarly, for the master PE (PE0), a hardware timer channel S11 independent of the hardware timer channel S41 is associated with the master PE (PE0), and a usage request is accepted as a part of the shared control process by the shared resource management program S10 operating on the PE0. For the purpose of measuring the window period W, more preferably, it is used as a replica of the state and operation of the hardware timer channel associated with the satellite PE holding the usage authority.

The application S40 running on the Pen sets the request flag in the use request register bank S30 of the one-bank configuration. The shared resource management program S10 determines the order of granting usage authority and controls the usage authority while referring / updating the shared resource usage request stored in the usage request register bank S30 and the control information set in the control table S20, respectively. 60, 60A is controlled. It is assumed that the control table S20 is appropriately set prior to the start of the shared control.

In FIG. 9, when the shared resource management program S10 detects the start timing of the control cycle by using hardware or software means (not shown), the following initialization process S1001 is sequentially executed.

(1) Simultaneous stop of all hardware timer channels S11 and S41 is requested (T1001 and T1002) by writing to the stop trigger register 626 provided in the usage authority control devices 60 and 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request are in the stopped state (S1101, S4101), respectively.

(2) The usage request flag of all PEs is cleared by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30, and the usage request flag of PE0 is cleared by writing to the shared resource usage request set register 520-0. By setting, the contents of the shared resource usage request flag register 510 are updated (T1003) so that only the usage request flag of PE0 is in a valid state (S3001).

(3) For all PEs in the control table S20, the usage authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. (PT) Control at the start of the control cycle by updating (T1005) to a value converted from the field value to a value that can be set in the count register in the hardware timer channels S11 and S41 (hereinafter referred to as a converted value). The initial state (S2001) of the table S20 is used.

(4) The remaining time (RT) field value in the control cycle of the control table S20 is set (T1006, T1007) for the initial count value register 617 of the hardware timer channels S11 and S41 associated with each PE, respectively. At this point in time, a value corresponding to the usage request acceptance window period W is set in the hardware timer channel S11 for PE0.

(5) At the beginning of the control cycle, in order to operate the hardware timer channel S11 for PE0 for the purpose of realizing the usage request acceptance window period W in the mode of granting the permission to use the shared resource to PE0, the flag for granting the permission to use PE0. (IU) The field value is set (true set) (T1008), and the state of the control table S20 is updated to the state S2002 in which PE0 holds the usage authority. By combining this process with the highest basic priority setting of PE0, the process related to granting the authority to use shared resources to PE0 and other PENs is standardized, and other than PE0 before the usage request acceptance window period W. This is an effective optional process for suppressing the granting of usage authority to PEn.

(6) The activation of the hardware timer channel S11 for PE0 is requested (T1009) by writing to the start trigger register 625 included in the usage authority control devices 60 and 60A. The hardware timer channel S11 that has received the start request transitions to the operation state S1102, and starts the decrement operation based on a predetermined condition with the value of the initial count value register 617 copied to the current count value register 616 as the initial value. ..

The application S40 running on PEn, which has detected the start timing of the control cycle by the same means as the shared resource management program S10, executes predetermined preprocessing such as initialization of the processing to be executed within the control cycle (S4001). do. When the process to be executed requires the granting of the shared resource use authority, it is used within the usage request acceptance window period W, that is, during the counting operation of the hardware timer channel S11 for PE0, as at least a part of the preprocessing. The PEn usage request flag is set (T4001) by writing to the PEN shared resource usage request set register in the request register bank S30.

Further, although not shown, an application running on a satellite PE (referred to as PEm) different from Pen within the same usage request acceptance window period W shall also set the usage request flag of PEm by the same procedure. .. As a result, at the end of the usage request acceptance window period W, the usage request register bank S30 is in a state S3002 in which the usage request flags of PE0, Pen, and Pem are set.

As shown in FIGS. 9 and 10, the application S40 on the PEN that has completed the preprocessing is a channel state of the hardware timer channel S41 for the Pen as at least a part of the process S4002 waiting for the permission to use the shared resource to be granted to the Pen. The register 615 is polled (T4002, T4003, T4004) at a predetermined cycle. The application S40 polls until the PEn has been granted usage authority, that is, the hardware timer channel S41 is started by the instruction of the shared resource management program S10, and the channel status register 615 reaches a value indicating that the counting operation is in progress. Repeat the operation.

On the other hand, the hardware timer channel S11 for PE0 in the counting operation state decrements the contents of the current count value register 616 every time the usage request acceptance window period W and a predetermined time elapse. When it is detected that the content of the current count value register 616 is equal to or less than the predetermined lower limit value, the usage authority control devices 60 and 60A are in the interrupt factor registers 635 and 635A provided in the interrupt request control units 630 and 630A. , The field value that holds the occurrence state of the usage authority grant period end event for PE0 from the hardware timer channel S11 is truly set. In this control flow, since the interrupt caused by the event is set to allow, the use authority control interrupt signal 61 requests the PE0 for the interrupt caused by the event (T1101).

The shared resource management program S10 that has detected an interrupt request caused by the usage authority grant period end event by the hardware timer channel S11 for PE0 sequentially executes a series of processes S1002 related to the end of the usage request acceptance window period W.

(1) In the interrupt factor registers 635 and 635A provided in the interrupt request control units 630 and 630A of the usage authority control devices 60 and 60A, the generation state of the usage authority grant period end event for PE0 is held from the hardware timer channel S11 for PE0. The field value is falsely cleared, and more preferably, when the channel S11 continues the counting operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1010). As a result, the hardware timer channel S11 transitions to the count stop state S1103.

(2) With the end of the usage request acceptance window period W implemented in the mode of granting the shared resource usage authority to PE0, the PE0 usage authority granting flag (IU) field value is cleared (set to false) (T1011). The state of the control table S20 is updated to the state S2003 in which none of PE0, Pen, and Pem holds the usage authority. The process T1011 is paired with the process T1008, and when the process T1008 is omitted, the process T1011 may be omitted as well.

(3) Subsequently, the remaining time (RT) field value in the control cycle of PE0 is updated according to the setting of the authority reassignment (RG) field in the control cycle of PE0. In this control flow, the RG field is set to invalid (reassignment prohibited), and in that case, the RT field value is converted to zero remaining time so that the usage authority is not granted to PE0 again by mistake. Update to the value (T1012).

(4) When the remaining time in the control cycle of PE0 becomes zero, the usage request flag of PE0 is cleared (T1013) by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30. As a result, the usage request register bank S30 is in the state S3003 in which the usage request flags of Pen and Pem are set.

Subsequently, as shown in FIG. 10, the shared resource management program S10 reads out the shared resource usage request flag register 510 included in the usage request register bank S30 (T1014), and uses the shared resources accumulated in the usage request acceptance window period W. Check for the presence or absence of a request (S1003). When there is one or more usage requests, the order of granting the shared resource usage authority is collectively determined (S1004) based on the flow shown in FIG. 22, and at least the shared resource 30 of the control table S20 is used. For all the requested PEs, a value specifying the determined grant order is set in the authority grant order (OR) field within the control cycle (T1015). More preferably, PEs that are not subject to the grant of the shared resource use authority in the current control cycle due to a predetermined reason such as no request to use the shared resource 30 or invalidation of the control policy setting in the control table S20 are subject to grant. A specific value indicating that it is outside may be set in the OR field of the PE.

After that, the shared resource management program S10 grants the usage authority of the shared resource 30 to the satellite PE to be granted according to the order of granting the shared resource usage authority determined in the process S1004. The specific procedure is as follows.

(1) With reference to the authority granting order (OR) field within the control cycle of the control table S20, the satellite PE to which the usage authority should be granted next (or first) is specified (S1005). The flag (IU) field value for granting the usage authority of the specified PE (referred to as PEn) is set (true set) (T1016), and the state of the control table S20 is changed to the state S2004 in which the PEN holds the usage authority. Update.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S41 for Pen to which the next usage authority is granted, the remaining time in the control cycle of PEn in the setting of the control table S20 (2) The RT) field value is set in the initial count value register 617 of the hardware timer channel S11 (T1017).

(3) Simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 is requested (T1018, T1019) by writing to the start trigger register 625 included in the usage authority control devices 60 and 60A. The hardware timer channels S11 and S41 that received the start request transition to the operating states (S1104 and S4102), respectively, and both of them are the initial count value registers 617 copied to the current count value registers 616 of the hardware timer channels S11 and S41. The decrement operation based on a predetermined condition is started with the value of. Here, it is equivalent that the hardware timer channel S41 is in the counting operation state and the shared resource use authority is being granted to the PEN, and the two hardware timer channels S11 and S41 are synchronously decrementing. I do.

The application S40, which polls (T4004) the channel status register 615 of the hardware timer channel S41 for Pen at a predetermined cycle as at least a part of the process S4002 waiting for the permission to use the shared resource to be granted to the Pen, is the hardware timer channel. When the count operation state of S41, that is, the state indicating that the usage authority to PEn has been granted is detected, the process S4003 accompanied by the use of the shared resource 30 is executed. In the application S40, while the hardware timer channel S41 can be used by occupying the shared resource 30 during the counting operation state, an interrupt request caused by an authorization period end event for notifying the use authority grant end timing is received. It is assumed that the process S4003 must be completed by the time it occurs.

After the hardware timer channels S11 and S41 for PE0 and PEn transition to the count operation state by the simultaneous start request (T1018, T1019), the time set in the initial count value register 617 of each hardware timer channel S11, S41, that is, When the time specified in the remaining time (RT) field in the control cycle that can be assigned to PEn in the control table S20 elapses, the interrupt factor registers 635 provided by the interrupt request control units 630 and 630A of the usage authority control devices 60 and 60A, In 635A, the field values that hold the occurrence state of the usage authority granting period end event for PE0 from the hardware timer channel S11 and the usage authority granting period end event for PEN from the hardware timer channel S41 are truly set. In this control flow, since the interrupt caused by the event is set to allow, the hardware channels S11 and S41 send an interrupt notifying the end of the usage authority granting period due to the event as a usage authority interrupt signal. At the same time, PE0 (T1102) and Pen (T4101) are requested at the same time.

As shown in FIG. 11, the application S40 that has detected the interrupt request caused by the usage authority grant period end event by the hardware timer channel S41 for Pen executes the process S4004 related to the end of the usage permission grant period.

(1) In the interrupt factor registers 635 and 635A provided in the interrupt request control units 630 and 630A of the usage authority control devices 60 and 60A, the generation state of the usage authority grant period end event for the PEN from the hardware timer channel S41 for Pen is held. The field value is falsely cleared, and more preferably, when the channel S41 continues the counting operation state, the hardware timer channel S41 is requested to be stopped by writing to the stop trigger register 626 (T4005). As a result, the hardware timer channel S41 transitions to the count stop state S4103.

(2) If necessary, the application S40 executes predetermined post-processing S4005, such as recovery processing from interrupts, processing that does not require shared resource use authority and should be executed within the control cycle.

The shared resource management program S10 that has detected an interrupt request caused by the usage authority grant period end event by the hardware timer channel S11 for PE0 sequentially executes the following processes as the process S1006 related to the end of the usage permission grant period.

(1) In the interrupt factor registers 635 and 635A provided in the interrupt request control units 630 and 630A of the usage authority control devices 60 and 60A, the generation state of the usage authority grant period end event for PE0 is held from the hardware timer channel S11 for PE0. If the field value is falsely cleared, and more preferably, the hardware timer channel S11 continues to be in the counting operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626. T1020). As a result, the hardware timer channel S11 transitions to the count stop state S1105.

(2) As an optional process for safety, the field value that holds the occurrence status of all events targeting PEn is falsely cleared in the interrupt factor registers 635 and 635A, and the field value is written to the stop trigger register 626 for PEn. Request the stop of the hardware timer channel S41 (T1021).

(3) Regarding the control table S20, the flag (IU) field value for which the usage authority of Pen is granted is cleared (set to false) (T1022), and none of PE0, Pen, and Pem holds the usage authority in S2005. Update.

(4) Subsequently, the remaining time (RT) field value in the control cycle of the PEN is updated according to the setting of the authority reassignment (RG) field in the control cycle of the PEN. In this control flow, the RG field is set to invalid (reassignment prohibited), and in that case, the RT field value is converted to zero remaining time so that the usage authority is not granted to PEn again by mistake. Update to the value (T1023).

(5) When the remaining time in the control cycle of PEn becomes zero, the usage request flag of Pen is cleared (T1024) by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30. As a result, the usage request register bank S30 is in the state S3004 in which the usage request flag of PEm is set.

The shared resource management program S10 subsequently executes a series of processes S1007 relating to the identification of the PE to which the usage authority is granted next to the PEn and the authorization of the shared resource 30 to the identified PE. The specific procedure is as follows.

(1) With reference to the authority granting order (OR) field within the control cycle of the control table S20, the satellite PE to which the usage authority should be granted is specified next. Set (true set) (T1025) the flag (IU) field value for granting the usage authority of the specified PE (referred to as PEm), and change the state of the control table S20 to the state S2006 in which the PEm holds the usage authority. Update.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S11 for PEm (not shown) to which the next usage authority is granted, the control cycle of PEm among the settings of the control table S20 The remaining time (RT) field value is set in the initial count value register 617 of the hardware timer channel S11 (T1026).

(3) By writing to the start trigger register 625 provided in the usage authority control devices 60 and 60A, simultaneous activation of the hardware timer channel S11 for PE0 and the hardware timer channel for PEm (not shown) is requested (T1027, T1028). do. The hardware timer channel S11 that has received the start request transitions to the operating state (S1106), and a predetermined value is set as the initial value of the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11. Start the condition-based decrement operation. The hardware timer channel for PEm (not shown) also starts the decrement operation by the same procedure, and becomes a count operation state indicating that the shared resource use authority is being granted to the PEm.

According to this control flow, the allocation of usage authority is requested within the usage request acceptance window period W by sequentially executing the above-mentioned usage authority granting process by utilizing the limited functions installed in the microcomputers 1 and 1B. For all PEs, it is possible to realize resource sharing control that grants usage authority at least once in each control cycle based on strict priority setting and in the finest particle time unit allowed by the hardware timer channels S11 and S41.

<Second shared resource usage permission grant control flow>
12 to 14 are flowcharts showing the operation of granting the authority to use the shared resource of the microcomputer according to the second embodiment.
In the second shared resource use authority grant control flow, the conditions (2) and (5) are different from the example of the first shared resource use authority grant control flow.

(2) The usage authority control device is configured to be 60A, the interrupt request when the usage authority grant period end event occurs is set to allow for all PEs, and the interrupt request when the usage authority grant period start event occurs for all PEs except PE0. Is set to allow.

(5) Notification of the start timing of granting usage authority is realized by requesting an interrupt accompanying the occurrence of the usage permission grant period start event from the usage authority control device 60A to the application running on each satellite PE.

A hardware timer channel S41 included in the usage authority control device 60A is associated with the PEn which is the first satellite PE, and controls the start / end timing of granting the shared resource usage authority to the application S40 running on the Pen and the Pen. .. Similarly, for the master PE (PE0), a hardware timer channel S11 independent of the hardware timer channel S41 is associated with the master PE (PE0), and a usage request is accepted as a part of the shared control process by the shared resource management program S10 operating on the PE0. For the purpose of measuring the window period W, more preferably, it is used as a replica of the state and operation of the hardware timer channel S41 associated with the satellite PE holding the usage authority. The application S40 running on the Pen sets the request flag in the usage request register bank S30 of the one-bank configuration, and the shared resource management program S10 sets the shared resource usage request stored in the usage request register bank S30 and the control table. While referring / updating the control information set in S20, the order of granting usage authority is determined and the usage authority control device 60A is controlled. It is assumed that the control table S20 is appropriately set prior to the start of the shared control.

In FIG. 12, when the shared resource management program S10 detects the start timing of the control cycle by using hardware or software means (not shown), the following initialization process S1001 is sequentially executed.

(1) Simultaneous stop of all hardware timer channels S11 and S41 is requested (T1001 and T1002) by writing to the stop trigger register 626 included in the usage authority control device 60A. The PE0 and the hardware timer channels S11 and S41 for PEn that have received the stop request are in the stopped state (S1101, S4101), respectively.

(2) The usage request flag of all PEs is cleared by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30, and the usage request flag of PE0 is cleared by writing to the shared resource usage request set register 520-0. By setting, the contents of the shared resource usage request flag register 510 are updated (T1003) so that only the usage request flag of PE0 is in a valid state (S3001).

(3) For all PEs in the control table S20, the usage authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. (PT) The control table at the start of the control cycle by updating (T1005) to the value converted from the field value to the value that can be set in the count register in the hardware timer channels S11 and S41 (hereinafter referred to as the converted value). The initial state of S20 (S2001) is used.

(4) The remaining time (RT) field value in the control cycle of the control table S20 is set (T1006, T1007) for the initial count value register 617 of the hardware timer channels S11 and S41 associated with each PE, respectively. At this point in time, a value corresponding to the usage request acceptance window period W is set in the hardware timer channel S11 for PE0.

(5) At the beginning of the control cycle, in order to operate the hardware timer channel S11 for PE0 for the purpose of realizing the usage request acceptance window period W in the mode of granting the permission to use the shared resource to PE0, the flag for granting the permission to use PE0. (IU) The field value is set (true set) (T1008), and the state of the control table S20 is updated to the state S2002 in which PE0 holds the usage authority. By combining this process with the highest basic priority setting of PE0, the process related to granting the authority to use shared resources to PE0 and other PENs is standardized, and other than PE0 before the usage request acceptance window period W. This is an effective optional process for suppressing the granting of usage authority to PEn.

(6) The activation of the hardware timer channel S11 for PE0 is requested (T1009) by writing to the start trigger register 625 included in the usage authority control device 60A. The hardware timer channel S11 that has received the start request transitions to the operation state S1102, and starts the decrement operation based on a predetermined condition with the value of the initial count value register 617 copied to the current count value register 616 as the initial value. ..

The application S40 running on PEn, which has detected the start timing of the control cycle by the same means as the shared resource management program S10, executes predetermined preprocessing such as initialization of the processing to be executed within the control cycle (S4001). do. When the process to be executed requires the granting of the shared resource use authority, it is used within the usage request acceptance window period W, that is, during the counting operation of the hardware timer channel S11 for PE0, as at least a part of the preprocessing. The PEN usage request flag is set (T4001) by writing to the PEN shared resource usage request set register in the request register bank S30.

Further, although not shown, an application operating on a satellite PE (referred to as PEm) different from Pen within the same usage request acceptance window period W also sets the usage request flag of PEm by the same procedure. As a result, at the end of the usage request acceptance window period W, the usage request register bank S30 is in a state S3002 in which the usage request flags of PE0, Pen, and Pem are set.

Unlike the first shared resource use permission grant control flow, the application S40 on the PEN that has completed the preprocessing is a hardware timer channel S41 for Pen as at least a part of the process of waiting for the grant of the shared resource use right to the Pen. There is no need to poll the channel status register 615 of. In response to the start request of the hardware timer channel S41 by the shared resource management program S10, it is sufficient to wait for an interrupt caused by the usage authority grant period start event from the usage authority control device 60A, until the interrupt request is made. The period may be devoted to the execution of another task process.

On the other hand, the hardware timer channel S11 for PE0 in the counting operation state decrements the contents of the current count value register 616 every time the usage request acceptance window period W and a predetermined time elapse. When it is detected that the content of the current count value register 616 is equal to or less than the predetermined lower limit value, the usage authority control device 60A sets the hardware timer channel S11 in the interrupt factor register 635A included in the interrupt request control unit 630A. True sets the field value that holds the occurrence state of the usage authority grant period end event for PE0. In this control flow, since the interrupt caused by the event is set to allow, the use authority control interrupt signal 61 requests the PE0 for the interrupt caused by the event (T1101).

The shared resource management program S10 that has detected the interrupt request T1001 caused by the usage permission grant period end event by the hardware timer channel S11 for PE0 sequentially executes a series of processes S1002 related to the end of the usage request acceptance window period W. ..

(1) In the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence state of the usage authority grant period end event for PE0 from the hardware timer channel S11 for PE0 is falsely cleared. Further, more preferably, when the hardware timer channel S11 continues the counting operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1010). As a result, the hardware timer channel S11 transitions to the count stop state S1103.

(2) With the end of the usage request acceptance window period W implemented in the mode of granting the shared resource usage authority to PE0, the PE0 usage authority granting flag (IU) field value is cleared (set to false) (T1011). The state of the control table S20 is updated to the state S2003 in which none of PE0, Pen, and Pem holds the usage authority. The process T1011 is paired with the process T1008, and when the process T1008 is omitted, the process T1011 may be omitted as well.

(3) Subsequently, the remaining time (RT) field value in the control cycle of PE0 is updated according to the setting of the authority reassignment (RG) field in the control cycle of PE0. In this control flow, the RG field is set to invalid (reassignment prohibited), and in that case, the RT field value is converted to zero remaining time so that the usage authority is not granted to PE0 again by mistake. Update to the value (T1012).

(4) When the remaining time in the control cycle of PE0 becomes zero, the usage request flag of PE0 is cleared (T1013) by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30. As a result, the usage request register bank S30 is in the state S3003 in which the usage request flags of Pen and Pem are set.

Subsequently, as shown in FIG. 13, the shared resource management program S10 reads out the shared resource usage request flag register 510 included in the usage request register bank S30 (T1014), and uses the shared resources accumulated in the usage request acceptance window period W. Check for the presence or absence of a request (S1003). When there is one or more usage requests, the order of granting the shared resource usage authority is collectively determined (S1004) based on the flow shown in FIG. 22, and at least the shared resource 30 of the control table S20 is used. For all the requested PEs, a value specifying the determined grant order is set in the authority grant order (OR) field within the control cycle (T1015). More preferably, PEs that are not subject to the grant of the shared resource use authority in the current control cycle due to a predetermined reason such as no request to use the shared resource 30 or invalidation of the control policy setting in the control table S20 are subject to grant. A predetermined value indicating that it is outside may be set in the OR field of the PE.

After that, the shared resource management program S10 grants the usage authority of the shared resource 30 to the satellite PE to be granted according to the order of granting the shared resource usage authority determined in the process S1004. The specific procedure is as follows.

(1) With reference to the authority granting order (OR) field within the control cycle of the control table S20, the satellite PE to which the usage authority should be granted next (or first) is specified (S1005). The flag (IU) field value for granting the usage authority of the specified PE (referred to as PEn) is set (true set) (T1016), and the state of the control table S20 is changed to the state S2004 in which the PEN holds the usage authority. Update.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S41 for Pen to which the next usage authority is granted, the remaining time in the control cycle of PEn in the setting of the control table S20 (2) The RT) field value is set in the initial count value register 617 of the channel S11 (T1017).

(3) By writing to the start trigger register 625 included in the usage authority control device 60A, simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 is requested (T1018, T1019). The hardware timer channels S11 and S41 that received the start request transition to the operating states (S1104 and S4102), respectively, and both of them are the initial count value registers 617 copied to the current count value registers 616 of the hardware timer channels S11 and S41. The decrement operation based on a predetermined condition is started with the value of. Here, it is equivalent that the hardware timer channel S41 is in the counting operation state and the shared resource use authority is being granted to the PEN, and the two hardware timer channels S11 and S41 are synchronously decrementing. I do.

When the start request T1018 for the hardware timer channel S41 for Pen is received from the shared resource management program S10, the hardware timer channel S11 is used for PE0 in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A. The field values that hold the occurrence status of the authorization period start event and the usage authorization period start event for PEn from the hardware timer channel S41 are set to true. In this control flow, only the interrupt caused by the latter event is set to be permitted, so that the hardware timer channel S41 sends an interrupt notifying the start of the usage authority granting period due to the event, and a usage authority interrupt signal. Request (T4121) to PEn via.

The application S40 that has detected the interrupt request T4121 caused by the usage permission grant period start event by the hardware timer channel S41 for Pen executes the process S4021 related to the start of the usage permission grant period. That is, in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence state of the usage authority grant period start event for the PEN from the hardware timer channel S41 for Pen is falsely cleared ( T4021), and subsequently, the process S4003 accompanied by the use of the shared resource 30 is executed. Similar to the first control flow, the application S40 can be used by occupying the shared resource 30 during the period in which the hardware timer channel S41 is in the counting operation state, while the permission granting period for notifying the timing of the granting end of the usage permission ends. It is assumed that the process S4003 must be terminated before the interrupt request caused by the occurrence of the event is generated.

After the hardware timer channels S11 and S41 for PE0 and PEn transition to the count operation state by the simultaneous start request (T1018, T1019), the time set in the initial count value register 617 of each hardware timer channel S11, S41, that is, When the time specified in the remaining time (RT) field in the control cycle that can be assigned to PEn in the control table S20 elapses, the hardware timer is set in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A. The field values that hold the occurrence status of the usage authority granting period end event from the channel S11 to PE0 and the usage authority granting period end event from the hardware timer channel S41 to PEn are set to true. In this control flow, since the interrupt caused by the event is set to allow, the hardware timer channels S11 and S41 notify the end of the usage authority granting period due to the event as shown in FIG. The interrupt to be executed is simultaneously requested to PE0 (T1102) and PEn (T4101), respectively, via the usage authority interrupt signal.

The application S40 that has detected an interrupt request caused by the usage authority grant period end event by the hardware timer channel S41 for Pen executes the process S4004 related to the end of the usage permission grant period.

(1) In the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence of all events targeting PEn is falsely cleared, and more preferably, the hardware timer channel. When S41 continues the counting operation state, the hardware timer channel S41 is requested to be stopped by writing to the stop trigger register 626 (T4005). As a result, the hardware timer channel S41 transitions to the count stop state S4103.

(2) If necessary, the application S40 executes predetermined post-processing S4005, such as recovery processing from an interrupt, processing that does not require shared resource use authority and should be executed within the control cycle.

The shared resource management program S10 that has detected an interrupt request caused by the usage authority grant period end event by the hardware timer channel S11 for PE0 sequentially executes the following processes as the process S1006 related to the end of the usage permission grant period.

(1) In the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value holding the occurrence state of all events targeting PE0 is falsely cleared, and more preferably, the hardware timer. When the channel S11 continues the counting operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1020). As a result, the hardware timer channel S11 transitions to the count stop state S1105.

(2) As an optional process for safety, the field value that holds the occurrence status of all events targeting PEn in the interrupt factor register 635A is falsely cleared, and the hardware for Pen is written by writing to the stop trigger register 626. Request the stop of the timer channel S41 (T1021).

(3) Regarding the control table S20, the flag (IU) field value for which the usage authority of Pen is granted is cleared (set to false) (T1022), and none of PE0, Pen, and Pem holds the usage authority in S2005. Update.

(4) Subsequently, the remaining time (RT) field value in the control cycle of the PEN is updated according to the setting of the authority reassignment (RG) field in the control cycle of the PEN. In this control flow, the RG field is set to invalid (reassignment prohibited), and in that case, the RT field value is converted to zero remaining time so that the usage authority is not granted to PEn again by mistake. Update to the value (T1023).

(5) When the remaining time in the control cycle of PEn becomes zero, the usage request flag of Pen is cleared (T1024) by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30. As a result, the usage request register bank S30 is in the state S3004 in which the usage request flag of PEm is set.

The shared resource management program S10 subsequently executes a series of processes S1007 relating to the identification of the PE to which the usage authority is granted next to the PEn and the authorization of the shared resource 30 to the identified PE. The specific procedure is as follows.

(1) With reference to the authority granting order (OR) field within the control cycle of the control table S20, the satellite PE to which the usage authority should be granted is specified next. Set (true set) (T1025) the flag (IU) field value for granting the usage authority of the specified PE (referred to as PEm), and change the state of the control table S20 to the state S2006 in which the PEm holds the usage authority. Update.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel (not shown) for PEm to which the next usage authority is granted, the control cycle of PEm among the settings of the control table S20 The remaining time (RT) field value is set in the initial count value register 617 of the channel S11 (T1026).

(3) By writing to the start trigger register 625 included in the usage authority control device 60A, simultaneous activation of the hardware timer channel S11 for PE0 and the hardware timer channel for PEm (not shown) is requested (T1027, T1028). The hardware timer channel S11 that has received the start request transitions to the operating state (S1106), and a predetermined value is set as the initial value of the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11. Start the condition-based decrement operation. The hardware timer channel for PEm (not shown) also starts the decrement operation by the same procedure, and becomes a count operation state indicating that the shared resource use authority is being granted to the PEm.

Compared with the first control flow, according to this control flow, the polling process for acquiring the shared resource use authority grant status to the satellite PE becomes unnecessary, and the CPU in the satellite PE that supports the simultaneous execution of a plurality of tasks in particular. It is possible to improve the utilization efficiency of computational resources such as cores.

<Third shared resource usage permission grant control flow>
15 to 18 are flowcharts showing the operation of granting the authority to use the shared resource of the microcomputer according to the third embodiment.
In the third shared resource use authority grant control flow, the conditions (3) and (6) are further different from the example of the second shared resource use authority grant control flow.

(3) Regarding the setting of the control table 140, the basic priority (PR) field of the master PE (PE0) can be converted to zero (highest priority), and the upper limit time (PT) field within the control cycle can be converted to the usage request acceptance window period W. In addition, enable the reauthorization (RG) field within the control cycle of at least one satellite PE (referred to as PEN), and disable the RG field for satellite PE and master PE (PE0) excluding PEN. To each.

(6) Instead of detecting the interrupt request due to the occurrence of the usage authority grant period end event from the usage authority control device 60A that notifies the usage authority grant end timing, the application S40 has completed the process involving the use of the shared resource 30. At this point, the application S40 proactively notifies the shared resource management program S10 of the return of the usage authority by the PE-to-PE interrupt request via the PE-to-PE interrupt control device 70.

A hardware timer channel S41 included in the usage authority control device 60A is associated with the PEn which is the first satellite PE, and controls the start / end timing of granting the shared resource usage authority to the application S40 running on the Pen and the Pen. .. Similarly, for the master PE (PE0), a hardware timer channel S11 independent of the hardware timer channel S41 is associated with the master PE (PE0), and a usage request is accepted as a part of the shared control process by the shared resource management program S10 operating on the PE0. For the purpose of measuring the window period W, more preferably, it is used as a replica of the state and operation of the hardware timer channel S41 associated with the satellite PE holding the usage authority. The application S40 running on the Pen sets the request flag in the usage request register bank S30 of the one-bank configuration, and the shared resource management program S10 sets the shared resource usage request stored in the usage request register bank S30 and the control table. While referring / updating the control information set in S20, the order of granting usage authority is determined and the usage authority control device 60A is controlled. In this control flow, at least the PE-to-PE interrupt request via the PE-to-PE interrupt control device 70 is used as a means for notifying the shared resource management program S10 of the return of the independent shared resource use authority from the application S40. .. It is assumed that the control table S20 is appropriately set prior to the start of the shared control.

In FIG. 15, when the shared resource management program S10 detects the start timing of the control cycle by using hardware or software means (not shown), the following initialization process S1001 is sequentially executed.

(1) Simultaneous stop of all hardware timer channels S11 and S41 is requested (T1001 and T1002) by writing to the stop trigger register 626 included in the usage authority control device 60A. The PE0 and the hardware timer channels S11 and S41 for PEn that have received the stop request are in the stopped state (S1101, S4101), respectively.

(2) The usage request flag of all PEs is cleared by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30, and the usage request flag of PE0 is cleared by writing to the shared resource usage request set register 520-0. By setting, the contents of the shared resource usage request flag register 510 are updated (T1003) so that only the usage request flag of PE0 is in a valid state (S3001).

(3) For all PEs in the control table S20, the usage authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. (PT) The control table at the start of the control cycle by updating (T1005) to the value converted from the field value to the value that can be set in the count register in the hardware timer channels S11 and S41 (hereinafter referred to as the converted value). The initial state of S20 (S2001) is used.

(4) The remaining time (RT) field value in the control cycle of the control table S20 is set (T1006, T1007) for the initial count value register 617 of the hardware timer channels S11 and S41 associated with each PE, respectively. At this point in time, a value corresponding to the usage request acceptance window period W is set in the hardware timer channel S11 for PE0.

(5) At the beginning of the control cycle, in order to operate the hardware timer channel S11 for PE0 for the purpose of realizing the usage request acceptance window period W in the mode of granting the permission to use the shared resource to PE0, the flag for granting the permission to use PE0. (IU) The field value is set (true set) (T1008), and the state of the control table S20 is updated to the state S2002 in which PE0 holds the usage authority. By combining this process with the highest basic priority setting of PE0, the process related to granting the authority to use shared resources to PE0 and other PENs is standardized, and other than PE0 before the usage request acceptance window period W. This is an effective optional process for suppressing the granting of usage authority to PEn.

(6) The activation of the hardware timer channel S11 for PE0 is requested (T1009) by writing to the start trigger register 625 included in the usage authority control device 60A. The hardware timer channel S11 that has received the start request transitions to the operation state S1102, and starts the decrement operation based on a predetermined condition with the value of the initial count value register 617 copied to the current count value register 616 as the initial value. ..

The application S40 running on PEn, which has detected the start timing of the control cycle by the same means as the shared resource management program S10, executes predetermined preprocessing such as initialization of the processing to be executed within the control cycle (S4001). do. When the process to be executed requires the granting of the shared resource use authority, it is used within the usage request acceptance window period W, that is, during the counting operation of the hardware timer channel S11 for PE0, as at least a part of the preprocessing. The PEN usage request flag is set (T4001) by writing to the PEN shared resource usage request set register in the request register bank S30.

Further, although not shown, an application running on a satellite PE (referred to as PEm) different from Pen within the same usage request acceptance window period W shall also set the usage request flag of PEm by the same procedure. .. As a result, at the end of the usage request acceptance window period W, the usage request register bank S30 is in a state S3002 in which the usage request flags of PE0, Pen, and Pem are set.

Similar to the second shared resource use permission grant control flow, the application S40 on the PEN that has completed the preprocessing is the hardware timer channel S41 for Pen as at least a part of the process of waiting for the grant of the shared resource use permission to the Pen. There is no need to poll the channel state register 615. In response to the start request of the hardware timer channel S41 by the shared resource management program S10, it is sufficient to wait for an interrupt caused by the usage authority grant period start event from the usage authority control device 60A, until the interrupt request is made. The period may be devoted to the execution of another task process.

On the other hand, the hardware timer channel S11 for PE0 in the counting operation state decrements the contents of the current count value register 616 every time the usage request acceptance window period W and a predetermined time elapse. When it is detected that the content of the current count value register 616 is equal to or less than the predetermined lower limit value, the usage authority control device 60A sets the hardware timer channel S11 in the interrupt factor register 635A included in the interrupt request control unit 630A. True sets the field value that holds the occurrence state of the usage authority grant period end event for PE0. In this control flow, since the interrupt caused by the event is set to allow, the use authority control interrupt signal 61 requests the PE0 for the interrupt caused by the event (T1101).

The shared resource management program S10 that has detected the interrupt request T1101 caused by the usage permission grant period end event by the hardware timer channel S11 for PE0 sequentially executes a series of processes S1002 related to the end of the usage request acceptance window period.

(1) In the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence state of the usage authority grant period end event for PE0 from the hardware timer channel S11 for PE0 is falsely cleared. Further, more preferably, when the hardware timer channel S11 continues the counting operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1010). As a result, the hardware timer channel S11 transitions to the count stop state S1103.

(2) With the end of the usage request acceptance window period W implemented in the mode of granting the shared resource usage authority to PE0, the PE0 usage authority granting flag (IU) field value is cleared (set to false) (T1011). The state of the control table S20 is updated to the state S2003 in which none of PE0, Pen, and Pem holds the usage authority. The process T1011 is paired with the process T1008, and when the process T1008 is omitted, the process T1011 may be omitted as well.

(3) Subsequently, the remaining time (RT) field value in the control cycle of PE0 is updated according to the setting of the authority reassignment (RG) field in the control cycle of PE0. In this control flow, the RG field is set to invalid (reassignment prohibited), and in that case, the RT field value is converted to zero remaining time so that the usage authority is not granted to PE0 again by mistake. Update to the value (T1012).

(4) When the remaining time in the control cycle of PE0 becomes zero, the usage request flag of PE0 is cleared (T1013) by writing to the shared resource usage request clear register 530 provided in the usage request register bank S30. As a result, the usage request register bank S30 is in the state S3003 in which the usage request flags of Pen and Pem are set.

Subsequently, as shown in FIG. 16, the shared resource management program S10 reads out the shared resource usage request flag register 510 included in the usage request register bank S30 (T1014), and uses the shared resources accumulated in the usage request acceptance window period W. Check for the presence or absence of a request (S1003). When there is one or more usage requests, one PE with the highest priority at the time of execution of this process is dynamically determined as the first shared resource usage authority grant destination based on the flow shown in FIG. 23 (S1041). )do. In the shared control policy in this control flow, since the authority granting order (OR) field within the control cycle in the control table S20 is not referred to, the set value of the OR field may be arbitrary.

After that, the shared resource management program S10 executes the process S1042 for granting the use authority of the shared resource 30 to the satellite PE to which the shared resource use authority is dynamically determined in the process S1041. The specific procedure is as follows.

(1) Set (true set) (T1041) the flag (IU) field value for granting the usage authority of the PE (referred to as PEN) to which the usage authority should be granted, and PEn assigns the usage authority to the status of the control table S20. Update to the held state S2004.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S41 for Pen which is the first permission to use, among the settings of the control table S20, the remaining time in the control cycle of PEn (2) The RT) field value is set in the initial count value register 617 of the channel S11 (T1017).

(3) By writing to the start trigger register 625 included in the usage authority control device 60A, simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 is requested (T1018, T1019). The hardware timer channels S11 and S41 that received the start request transition to the operating states (S1104 and S4102), respectively, and both of them are the initial count value registers 617 copied to the current count value registers 616 of the hardware timer channels S11 and S41. The decrement operation based on a predetermined condition is started with the value of. Here, it is equivalent that the hardware timer channel S41 is in the counting operation state and the shared resource use authority is being granted to the PEN, and the two hardware timer channels S11 and S41 are synchronously decrementing. I do.

When the start request T1018 for the hardware timer channel S41 for Pen is received from the shared resource management program S10, the hardware timer channel S11 is used for PE0 in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A. The field values that hold the occurrence status of the authorization period start event and the usage authorization period start event for PEn from the hardware timer channel S41 are set to true. In this control flow, only the interrupt caused by the latter event is set to be permitted, so that the hardware timer channel S41 sends an interrupt notifying the start of the usage authority granting period due to the event, and a usage authority interrupt signal. Request (T4121) to PEn via.

The application S40 that has detected the interrupt request T4121 caused by the usage permission grant period start event by the hardware timer channel S41 for Pen executes the process S4021 related to the start of the usage permission grant period. That is, in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence state of the usage authority grant period start event for the PEN from the hardware timer channel S41 for Pen is falsely cleared ( T4021), and subsequently, the process S4003 accompanied by the use of the shared resource 30 is executed. Similar to the second control flow, the application S40 can be used by occupying the shared resource 30 during the period in which the hardware timer channel S41 is in the counting operation state, while the permission granting period for notifying the timing of the granting end of the usage permission ends. It is assumed that the process S4003 must be terminated before the interrupt request caused by the occurrence of the event is generated.

In the second control flow, regardless of whether or not the process S4003 using the shared resource 30 is completed in the application S40, the shared resource is used until the usage authority grant period end event and the interrupt request that is the cause of the event are detected. PEn continues to retain the usage authority of 30. On the other hand, in this control flow, when the usage authority of the shared resource 30 is no longer required, the following usage authority is as shown in FIG. 17 without waiting for the interrupt request caused by the usage authority grant period end event. The return process S4041 is independently executed.

(1) In order to safely stop the operating hardware timer channel S41 for PEn, all events targeting PEn are sent by writing to the interrupt enable register 636A provided in the interrupt request control unit 630A of the usage authority control device 60A. Temporarily disable the interrupt request as a factor (T4041).

(2) In the interrupt factor register 635A, the field value holding the occurrence state of all events targeting PEn is falsely cleared, and the hardware timer channel S41 for Pen is stopped by writing to the stop trigger register 626. Request (T4042). As a result, the hardware timer channel S41 transitions to the count stop state S4103.

(3) The PE-interruption request flag with PE0 as the request destination PE is set by writing to the PE-interruption request set register 720-n having the PEn as the request source PE provided in the PE-interruption control device 70, and the PEN is set. Requests an interrupt between PEs from PE0 (T4043). When it is necessary to transmit a message different from the release of the shared resource 30 by returning the usage authority regarding the interrupt between PEs, a means for notifying the interrupt factor accompanying the interrupt signal between PEs (not shown). May be provided separately.

(4) By writing to the interrupt enable register 636A, the interrupt request temporarily disabled by the process T4041 is re-allowed (T4044).

(5) If necessary, the application S40 executes predetermined post-processing S4005, such as processing that does not require the shared resource use authority and should be executed within the control cycle.

The shared resource management program S10 that has detected the PE-to-PE interrupt request T4043 from PEn to PE0 via the PE-to-PE interrupt signal sequentially executes the following processes as the process S1043 related to the return of usage authority.

(1) In order to safely stop the operating hardware timer channel S11 for PE0, all events targeting PE0 are sent by writing to the interrupt enable register 636A provided in the interrupt request control unit 630A of the usage authority control device 60A. Temporarily disable the interrupt request as a factor (T1042).

(2) In the interrupt factor register 635A, the field value holding the occurrence state of all events targeting PE0 is falsely cleared, and the hardware timer channel S11 for PEn is stopped by writing to the stop trigger register 626. Request (T1043). As a result, the hardware timer channel S41 transitions to the count stop state S1105.

(3) As an optional process for safety, in the interrupt factor register 635A, the field value that holds the occurrence state of all events targeting PEn is falsely cleared, and the hardware for Pen is written by writing to the stop trigger register 626. Request the stop of the wear timer channel S41 (T1021).

(4) By writing to the interrupt enable register 636A, the interrupt request temporarily disabled by the process T1042 is re-allowed (T1044).

(5) Regarding the control table S20, the flag (IU) field value for which the usage authority of Pen is granted is cleared (set to false) (T1022), and none of PE0, Pen, and Pem holds the usage authority in S2005. Update.

(6) Subsequently, the remaining time (RT) field value in the control cycle of the PEN is updated according to the setting of the authority reassignment (RG) field in the control cycle of the PEN. In this control flow, the RG field is set to valid (re-grant permission), and in that case, the current count value register 616 of the hardware timer channel S41 for Pen and / and the hardware timer channel S11 for PE0 are set. The contents of the current count value register 616 of the above are read out (T1045, T1046), respectively, and the converted value of the remaining time in the control cycle that can be assigned to the PEN is calculated by subtracting the time when the Pen actually occupies the shared resource 30. As the calculation method, the conversion value acquired by the processing T1045, the average of the two conversion values acquired by the processing T1045 and the processing T1046, or the smaller value among the two conversion values may be used.

(7) For PEn in the control table S20, the value of the RT field is updated to the converted value calculated in (6) (T1047).

(8) Similarly, the initial count value register 617 of the hardware timer channel S41 for Pen is updated to the converted value calculated in (7) in preparation for reassigning the authority to use the shared resource to PEN (T1048).

(9) When the remaining time in the control cycle of the PEN calculated in (6) becomes zero, reassignment of authority to the Pen in the current control cycle is prohibited regardless of the setting of the RG field, and the use request register bank S30 is set. By writing to the shared resource usage request clear register 530 provided, the usage request flag of PEn is cleared (T1049). As a result, the usage request register bank S30 is in a state S3041 in which the usage request flags of Pen and Pem are set or only the usage request of Pem is set. In this control flow, the following description will be continued assuming that the usage request flags of PEn and Pem are set.

Then, as shown in FIG. 18, the shared resource management program S10 executes a series of processes related to the identification of the PE to which the usage authority is granted next to the PE and the authorization of the shared resource 30 to the identified PE. do. Specifically, the shared resource usage including the re-granting of the usage authority by the PE having a positive value as the remaining time in the control cycle by reading the shared resource usage request flag register 510 provided in the usage request register bank S30 (T1050) again. Check for the presence or absence of a request (S1044). When there is one or more usage requests, one PE with the highest priority at the time of execution of this process is dynamically determined as the next shared resource usage authority grant destination based on the flow shown in FIG. 23 (S1045). )do.

After that, the shared resource management program S10 executes the process S1046 for granting the use authority of the shared resource 30 to the satellite PE to which the shared resource use authority is dynamically determined in the process S1045. The specific procedure is as follows.

(1) Set (true set) the usage authority granting flag (IU) field value of the PE (PEn, assuming the case where the usage authority is granted twice in a row to the same PE) to which the usage authority is granted next. ) (T1051), and the state of the control table S20 is updated to the state S2006 in which PEn holds the usage authority again.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S41 for Pen to which the next usage authority is granted, the remaining time in the control cycle of PEn in the setting of the control table S20 (2) The RT) field value is set in the initial count value register 617 of the hardware timer channel S11 (T1017). The value set here is a value obtained by subtracting the value corresponding to the time when Pen actually occupies the shared resource 30 at the time of the first grant of the usage authority.

(3) By writing to the start trigger register 625 included in the usage authority control device 60A, simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 is requested (T1018, T1019). As in the case of the first grant of authority to PEn, the hardware timer channels S11 and S41 that received the start request transition to the operating states (S1106, S4141), respectively, and both of them are the current counts of the hardware timer channels S11 and S41. The decrement operation based on a predetermined condition is started with the value of the initial count value register 617 copied to the value register 616 as the initial value.

Compared with the second control flow, according to this control flow, when the time when the satellite PE actually uses the shared resource 30 is shorter than the setting of the upper limit time in the control cycle in the control table S20, for example, it is unsteady. By allocating the surplus time to the shared resource usage request due to the interrupt processing, it is possible to reduce the wasted time when the shared resource 30 is unused and improve the utilization efficiency of the shared resource 30.

<Fourth shared resource usage permission grant control flow>
19 to 21 are flowcharts showing the operation of granting the authority to use the shared resource of the microcomputer according to the fourth embodiment.
In the fourth shared resource use authority grant control flow, the conditions (1), (3), and (4) are further different from the example of the second shared resource use authority grant control flow.

(1) The usage request register 50 has a configuration of two banks (use request register banks 50-0, 50-1), and the usage request register banks S31 and S32 (Bank-0, Bank-1).

(3) Regarding the setting of the control table 140, the enable (EN) field of the master PE (PE0) is set to invalid, and the privilege reassignment (RG) field within the control cycle is disabled for all satellite PEs. ..

(4) As conceptually shown with reference to FIG. 8B, the entire control cycle is set as the usage request acceptance window period for accepting the shared resource usage request in the next control cycle.

A hardware timer channel S41 included in the usage authority control device 60A is associated with PEN, which is the first satellite PE, and controls the start / end timing of granting the shared resource usage authority to the application S40 running on Pen and Pen. do. Similarly, for the master PE (PE0), the hardware timer channel S11 independent of the hardware timer channel S41 is associated with the master PE (PE0), and preferably, as a part of the shared control process by the shared resource management program S10 operating on the PE0. The state and operation of the hardware timer channel S41 associated with the satellite PE holding the usage authority are used as a replicated replica.

The application S40 running on Pen sets the request flag in the usage request register bank on the back bank side of the usage request register banks S31 and S32 having a two-bank configuration, and the shared resource management program S10 is on the front bank side. Refer to / update the shared resource usage request stored in the usage request register bank and the control information set in the control table S20, and determine and use the usage authority granting order while switching the front and back of the bank for each control cycle. It controls the authority control device 60A. It is assumed that the control table S20 is appropriately set prior to the start of the shared control. Further, at the time of starting control, of the two usage request register banks S31 and S32, the usage request register bank S32 is the front bank (also referred to as the current bank), and the usage request register bank S31 is the back bank.

In FIG. 19, when the shared resource management program S10 detects the start timing of the control cycle by using hardware or software means (not shown), the following initialization process S1061 is sequentially executed.

(1) Simultaneous stop of all hardware timer channels S11 and S41 is requested (T1001 and T1002) by writing to the stop trigger register 626 included in the usage authority control device 60A. The PE0 and the hardware timer channels S11 and S41 for Pen that have received the stop request are in the stopped state (S1101, S4101), respectively.

(2) At this point, the usage request flag of all PEs is invalidated by clearing the usage request flag of all PEs by writing to the shared resource usage request clear register 530 provided in the usage request register bank S32, which corresponds to the table bank. The contents of the shared resource use request flag register 510 are updated (T1061) so that the state (S3261) is reached.

(3) The front and back banks of the usage request register banks S31 and S32 are switched (T1062) according to a predetermined procedure, and the usage request register bank S31 is used as the front bank (S3161).

(4) For all PEs in the control table S20, the usage authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. (PT) The control table at the start of the control cycle by updating (T1005) to the value converted from the field value to the value that can be set in the count register in the hardware timer channels S11 and S41 (hereinafter referred to as the converted value). The initial state of S20 (S2001) is used.

(5) The remaining time (RT) field value in the control cycle of the control table S20 is set (T1006) for the initial count value register 617 of the hardware timer channel associated with each satellite PE. In this control flow, it is not necessary to measure the usage request acceptance window period using the hardware timer channel S11 for PE0. Therefore, it is not necessary to set or start the hardware timer channel S11 at this point.

The application S40 running on PEn, which has detected the start timing of the control cycle by the same means as the shared resource management program S10, determines the initialization of the processing to be executed in the current and / or next control cycle. (S4061) is executed. When the process to be executed in the next control cycle requires the granting of the shared resource use authority, as at least a part of the pre-process, the PEN shared resource use request in the use request register bank S32 on the back bank side. By writing to the set register, the PEn usage request flag is set (T4061).

Further, although not shown, an application operating on a satellite PE (referred to as PEm) different from Pen also sets the usage request flag of PEm in the usage request register bank S32 by the same procedure. As a result, at the end of the current control cycle, the usage request register bank S32 is in a state S3622 in which the usage request flags of PEn and Pem are set.

Similar to the second shared resource usage authority grant control flow, the application S40 on the PEN that has completed the preprocessing is used from the usage authority control device 60A in response to the start request of the hardware timer channel S41 by the shared resource management program S10. Wait for an interrupt due to the authorization period start event to be requested. The period until the interrupt request may be devoted to the execution of another task process. Whether or not the application S40 is requested to grant the usage authority of the shared resource 30 in the previous control cycle as an internal resource that maintains the correspondence between the interrupt caused by the usage permission grant period start event and the control cycle. A flag indicating the above may be provided.

Following the initial setting of the control table S20, the shared resource management program S10 reads out the shared resource usage request flag register 510 included in the usage request register bank S31 on the table bank side (T1063), and the shared resource accumulated in the previous control cycle. Check for the presence or absence of a usage request (S1062). For the sake of simplicity, it is assumed that there is no usage request from any satellite Pen or Pem at this point, and the process related to the granting of usage authority in the current control cycle is terminated.

When the shared resource management program S10 detects the start timing of the control cycle again, the following initialization process S1061A is sequentially executed again.

(1) Simultaneous stop of all hardware timer channels S11 and S41 is requested (T1001A, T1002A) by writing to the stop trigger register 626 included in the usage authority control device 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request transition to the stopped state (S1101A, S4101A), respectively, or maintain the stopped state.

(2) At this point, the usage request flag of all PEs is invalidated by clearing the usage request flag of all PEs by writing to the shared resource usage request clear register 530 provided in the usage request register bank S31 corresponding to the table bank. The contents of the shared resource use request flag register 510 are updated (T1064) so that the state (S3162) is reached.

(3) The front and back banks of the usage request register banks S31 and S32 are switched (T1065) according to a predetermined procedure, and the usage request register bank S32 is used as the front bank (S3263).

(4) For all PEs in the control table S20, the usage authority granting flag (IU) field value is cleared (set to false) (T1004A), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. (PT) The control table at the start of the control cycle by updating (T1005A) to the value converted from the field value to the value that can be set in the count register in the hardware timer channels S11 and S41 (hereinafter referred to as the converted value). The initial state of S20 (S2001A) is used.

(5) The remaining time (RT) field value in the control cycle of the control table S20 is set (T1006A) for the initial count value register 617 of the hardware timer channel associated with each satellite PE. As in the case of the pre-control cycle, it is not necessary to set or start the hardware timer channel S11 for PE0 at this point.

Subsequently, as shown in FIG. 20, the shared resource management program S10 reads out the shared resource usage request flag register 510 included in the usage request register bank S32 on the table bank side (T1066), and shares the shares accumulated in the pre-control cycle. Check whether there is a resource usage request (S1062A). When there is one or more usage requests, the order of granting the shared resource usage authority is collectively determined (S1004A) based on the flow shown in FIG. 22, and at least the shared resource 30 of the control table S20 is used. For all the requested PEs, a value specifying the determined granting order is set in the authority granting order (OR) field within the control cycle (T1015A). More preferably, PEs that are not subject to the grant of the shared resource use authority in the current control cycle due to a predetermined reason such as no request to use the shared resource 30 or invalidation of the control policy setting in the control table S20 are subject to grant. A predetermined value indicating that it is outside may be set in the OR field of the PE.

After that, the shared resource management program S10 grants the usage authority of the shared resource 30 to the satellite PE to be granted according to the order of granting the shared resource usage authority determined in the process S1004A. The specific procedure is as follows.

(1) With reference to the authority granting order (OR) field within the control cycle of the control table S20, the satellite PE to which the usage authority should be granted next (or first) is specified (S1005A). Set (true set) (T1016A) the flag (IU) field value for granting the usage authority of the specified PE (referred to as PEn), and change the state of the control table S20 to the state S2004A in which the PEN holds the usage authority. Update.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S41 for Pen to which the next usage authority is granted, the remaining time in the control cycle of PEn in the setting of the control table S20 (2) The RT) field value is set in the initial count value register of channel S11 (T1017A).

(3) Simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 is requested (T1018A, T1019A) by writing to the start trigger register 625 included in the usage authority control device 60A. The hardware timer channels S11 and S41 that received the start request transition to the operating states (S1104A, S4102A), respectively, and both of them are the initial count value registers 617 copied to the current count value registers 616 of the hardware timer channels S11 and S41. The decrement operation based on a predetermined condition is started with the value of. Here, it is equivalent that the hardware timer channel S41 is in the counting operation state and the shared resource use authority is being granted to the PEN, and the two hardware timer channels S11 and S41 are synchronously decrementing. I do.

When the start request T1018A for the hardware timer channel S41 for Pen is received from the shared resource management program S10, the use for the PEN from the hardware timer channel S11 in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A. The field values that hold the occurrence status of the authorization period start event and the usage authorization period start event for PEn from the hardware timer channel S41 are set to true. In this control flow, only the interrupt caused by the latter event is set to be permitted, so that the hardware timer channel S41 sends an interrupt notifying the start of the usage authority granting period due to the event as a usage authority interrupt signal. Request (T4121A) to PEn via.

The application S40 that has detected the interrupt request T4121A caused by the usage authorization period start event by the hardware timer channel S41 for Pen executes the process S4021A related to the start of the usage authorization period. That is, in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence state of the usage authority grant period start event for the PEN from the hardware timer channel S41 for Pen is falsely cleared ( T1021A), and subsequently, the process S4003A accompanied by the use of the shared resource 30 is executed. Similar to the second and second control flows, in the application S40, while the hardware timer channel S41 can occupy and use the shared resource 30 during the counting operation state, the application S40 grants the permission to notify the end timing of granting the usage permission. It is assumed that the process S4003A must be terminated before the interrupt request caused by the occurrence of the period end event is generated.

After the hardware timer channels S11 and S41 for PE0 and PEn transition to the counting operation state by the simultaneous start request (T1018A, T1019A), the time set in the initial count value register 617 of each hardware timer channel S11, S41, that is, When the time specified in the remaining time (RT) field in the control cycle that can be assigned to PEn in the control table S20 elapses, the hardware timer is set in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A. The field values that hold the occurrence status of the usage authority granting period end event from the channel S11 to PE0 and the usage authority granting period end event from the hardware timer channel S41 to PEn are set to true. In this control flow, since the interrupt caused by the event is set to allow, the hardware timer channels S11 and S41 terminate the usage authority granting period caused by the event, as shown in FIG. 21. The interrupt to be notified is simultaneously requested to PE0 (T1102A) and PEn (T4101A), respectively, via the usage authority interrupt signal.

The application S40 that has detected an interrupt request caused by the usage authority granting period end event by the hardware timer channel S41 for Pen executes the process S4004A related to the end of the usage permission granting period.

(1) In the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value for holding the occurrence of all events targeting PEn is falsely cleared, and more preferably, the hardware timer channel. When S41 continues the counting operation state, the hardware timer channel S41 is requested to be stopped by writing to the stop trigger register 626 (T4005A). As a result, the hardware timer channel S41 transitions to the count stop state S4103A.

(2) If necessary, the application S40 executes predetermined post-processing S4005A, such as recovery processing from an interrupt, processing that does not require shared resource use authority and should be executed within the control cycle.

The shared resource management program S10 that has detected an interrupt request caused by the usage authority grant period end event by the hardware timer channel S11 for PE0 sequentially executes the following processes as the process S1063A related to the end of the usage permission grant period.

(1) In the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage authority control device 60A, the field value holding the occurrence state of all events targeting PE0 is falsely cleared, and more preferably, the hardware timer. When the channel S11 continues the counting operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1020A). As a result, the hardware timer channel S11 transitions to the count stop state S1105A.

(2) As an optional process for safety, in the interrupt factor register 635A, the field value that holds the occurrence state of all events targeting PEn is falsely cleared, and the hardware for Pen is written by writing to the stop trigger register 626. Request the stop of the wear timer channel S41 (T1021A).

(3) Regarding the control table S20, the flag (IU) field value for which the usage authority of Pen is granted is cleared (set to false) (T1022A), and no PE0, Pen, or Pem holds the usage authority in S2005A. Update.

(4) Subsequently, the remaining time (RT) field value in the control cycle of the PEN is updated according to the setting of the authority reassignment (RG) field in the control cycle of the PEN. In this control flow, the RG field is set to invalid (reassignment prohibited), and in that case, the RT field value is converted to zero remaining time so that the usage authority is not granted to PEn again by mistake. Update to the value (T1023A).

(5) When the remaining time in the control cycle of PEn becomes zero, the usage request flag of PEn is cleared by writing to the shared resource usage request clear register 530 provided in the usage request register bank S32 on the table bank side (T1067). )do. As a result, the usage request register bank S32 is in the state S3264 in which the usage request flag of PEm is set.

The shared resource management program S10 subsequently executes a series of processes S1007A relating to the identification of the PE to which the usage authority is granted next to the PEn and the authorization of the shared resource 30 to the identified PE. The specific procedure is as follows.

(1) With reference to the authority granting order (OR) field within the control cycle of the control table S20, the satellite PE to which the usage authority should be granted is specified next. Set (true set) (T1025A) the flag (IU) field value for granting the usage authority of the specified PE (referred to as PEm), and change the state of the control table S20 to the state S2006A in which the PEm holds the usage authority. Update.

(2) In order to operate the hardware timer channel S11 for PE0 as a replica of the hardware timer channel S11 for PEm (not shown) to which the next usage authority is granted, the control cycle of PEm among the settings of the control table S20 The remaining time (RT) field value is set in the initial count value register 617 of the hardware timer channel S11 (T1026A).

(3) By writing to the start trigger register 625 included in the usage authority control device 60A, simultaneous activation of the hardware timer channel S11 for PE0 and the hardware timer channel for PEm (not shown) is requested (T1027A, T1028A). The hardware timer channel S11 that has received the start request transitions to the operating state (S1106A), and a predetermined value is set as the initial value of the initial count value register 67 copied to the current count value register 616 of the hardware timer channel S11. Start the condition-based decrement operation. The hardware timer channel for PEm (not shown) also starts the decrement operation by the same procedure, and becomes a count operation state indicating that the shared resource use authority is being granted to the PEm.

Compared with the first control flow, according to this control flow, it is not necessary to set a part of the control cycle as the usage request acceptance window period, and the time corresponding to the usage request acceptance window period can be set in various satellite PEs. It can be allocated to processing and use of the shared resource 30, and the utilization efficiency of the computational resource such as the CPU core and the shared resource 30 can be further improved. In addition, the time constraint regarding the timing of the shared resource usage request from the satellite PE is greatly relaxed, and it has a high affinity with the implementation of software pipeline processing in units of control cycles, facilitating application porting. Can be done.

FIG. 22 is a flowchart showing a process of determining the order of granting usage authority in the microcomputer of FIG. In FIG. 22, among the four typical shared resource usage authority grant control flows exemplified so far, all of the one or more shared resource usage requests accumulated in the shared resource usage request flag register 510 at the start of this process. The detailed flow of the process S1004 and S1004A which collectively determines the order of granting the use authority in the current control cycle for the use request is shown.

Here, each of the plurality of PE10, 20-1, 20-2, and 20-3 included in the microcomputers 1 and 1B has a PE identifier having a unique value (zero or positive integer value, where zero indicates PE0). Is assigned. The value that can be set in the basic priority (PR) field in the control table 140 is zero (highest priority, but can be set only for PE0) or a positive integer value less than or equal to the predetermined maximum value (lowest priority). Either. Among PEs with the same priority, the smaller the value of the PE identifier, the higher the priority. In addition, the value indicating the order of granting the authority to use the shared resource set in the authority grant order (OR) field within the control cycle is zero or a positive integer value less than the number of PEs for the PE to be granted within the control cycle. Any PE that is not subject to grant has a negative integer value (for example, -1), and the authority is granted in ascending order from the PE for which the value zero is set.

In FIG. 22, the order counter N and the priority counter P, which are internal parameters, are initialized to zero (S901), respectively. Subsequently, the presence / absence of a usage request for the shared resource 30 is checked (S902) from the contents of the shared resource usage request flag register 510 read before the start of this process, and if there is no usage request (S902: No). , The OR field value is set to -1 (S910) for all PEs that are not subject to the grant of usage authority, and this process is terminated.

When there is a usage request from one or more PEs (S902: Yes), the PE counter C is initialized to zero (S903) as an internal parameter for scanning the control table 140 for each PE. Subsequently, as a process of determining whether or not the PE whose PE identifier matches the value of the PE counter C can be the target of granting the usage authority, the enable (EN) field value of the PE is true (valid) and the basic priority (basic priority). PR) Check in the control table whether the field value matches the value of the priority counter P and the remaining time (RT) field value in the control cycle is a non-zero conversion value, and in addition, the usage request from the PE. Check if there is (S904). When it is determined that the PE is a grant target PE (S904: Yes), the value of the order counter N is set in the OR field of the PE, and then the order counter N is incremented (S905). If it is determined that the PE is not the grant target PE (S904: No), the process S905 is skipped.

Subsequently, the PE counter C is incremented (S906), and it is checked (S907) whether or not the value of the PE counter C is the maximum value, that is, ((the number of PEs included in the microcomputers 1 and 1B) -1) or more. If the result of the process S907 is unsuccessful (S907: No), the process returns to the process S904.

When the result of the process S907 is established (S907: Yes), the same process is performed for the PE having the next lowest priority, that is, the setting scan for each PE in the control table 140 and the order of granting the usage authority to the PE to be granted. In order to execute the setting, the priority counter P is incremented (S908), and it is checked whether the value of the priority counter P is equal to or greater than a predetermined maximum value (S909). If the result of process S909 is unsuccessful (S909: No), the process returns to process S903, and if it is established (S909: Yes), the OR field value is set to -1 for all PEs that are not subject to use permission. Set (S910) and end this process.

FIG. 23 is a flowchart showing a process of determining the grantee of the usage authority in the microcomputer of FIG. In FIG. 23, among the four typical shared resource usage authority grant control flows exemplified so far, the highest priority is given to one or more shared resource usage requests stored in the shared resource usage request flag register 510 at the start of this process. The detailed flow of the process S1041 and S1045 which determines one PE with a high degree as the next use authority grant destination is shown.

Here, each of the plurality of PE10, 20-1, 20-2, and 20-3 included in the microcomputers 1 and 1B has a PE identifier (zero or a positive integer value, where zero indicates PE0) having a unique value. Assigned. The value that can be set in the basic priority (PR) field in the control table 140 is zero (highest priority, but can be set only for PE0) or a positive integer value less than or equal to the predetermined maximum value (lowest priority). Either. Among PEs with the same priority, the smaller the value of the PE identifier, the higher the priority. Unlike the process of FIG. 22, the authority granting order (OR) field within the control cycle is not updated.

In FIG. 23, the priority counter P, which is an internal parameter, is initialized to zero (S921). Subsequently, the presence / absence of a usage request is checked (S922) from the contents of the shared resource usage request flag register 510 read before the start of this processing, and if there is no usage request (S922: No), the following authority is given. After executing the predetermined process S930 when there is no grant destination PE, this process ends.

When there is a usage request from one or more PEs (S922: Yes), the PE counter C is initialized to zero (S923) as an internal parameter for scanning the control table 140 for each PE. Subsequently, as a process of determining whether or not the PE whose PE identifier matches the value of the PE counter C can be the target of granting usage authority, the enable (EN) field value of the PE is true (valid) and the basic priority (PR). ) Check with the control table 140 whether the field value matches the value of the priority counter P and the remaining time in the control cycle (RT) field value is a non-zero conversion value, and in addition, the usage request from the PE. Check if there is (S924). When it is determined that the PE is to be granted (S924: Yes), the PE is determined as the next grant destination (S925), and this process is terminated.

When the result of the process S924 is unsuccessful (S924: No), the PE counter C is incremented (S926), and the value of the PE counter C is the maximum value, that is, ((the number of PEs of the microcomputers 1 and 1B) -1) or more. Check if there is (S927). If the result of the process S927 is unsuccessful (S927: No), the process returns to the process S924.

When the result of the process S927 is satisfied (S927: Yes), the priority counter P is incremented in order to execute the same process for the PE having the next lowest priority, that is, the setting scan for each PE in the control table 140. (S928), and it is checked whether or not the value of the priority counter P is equal to or greater than a predetermined maximum value (S929). If the result of the process S929 is unsuccessful (S929: No), the process returns to the process S923, and if the result is established (S929: Yes), after executing the predetermined process S930 when there is no next authorization destination PE, This process ends.

As described above, according to the above-described embodiment, it is possible to improve the utilization efficiency of arithmetic elements and shared resources as compared with the access exclusive control using the spinlock process, and the control specified by the user. It is possible to realize resource sharing control with a small time particle size suitable for applications that require strict scheduling control based on policies and hard real-time performance. In addition, it is possible to reduce the power consumption related to the resource sharing control by reducing the processing that is not involved in the calculation.

FIG. 24 is a diagram showing an example of a time change in power consumption during the operation of the microcomputer of FIG. 1 or FIG. 4 (a).
In FIG. 24, not only the overall power consumption of the microcomputers 1 and 1B is averaged, but also the upper limit of the power consumption itself required for the shared control is almost determined by one PE in which the shared resource management program operates. It contributes to the reduction of power consumption.

FIG. 25 is a diagram showing an example of time-dependent changes in power consumption during operation of the microcomputer of FIG. 1 or FIG. 4 (b).
In FIG. 25, in the method of FIG. 8A, the shared resource usage request R, the determination A of the granting order of the usage authority, the setting and starting S of the hardware timer channel, and the execution U of the application are executed in chronological order. .. On the other hand, in the method of FIG. 8A, the shared resource usage request R is executed in parallel with the determination A of the granting order of the usage authority, the setting and starting S of the hardware timer channel, or the execution U of the application. To.
Therefore, in the method of FIG. 8B, when there is a shared resource usage request R, the power consumption required for the processing is added to the power consumption of the method of FIG. 8A.

FIG. 26 is a block diagram showing a configuration example of a microcomputer according to a comparative example of the present embodiment.
In FIG. 26, the microcomputer 1001 includes, as a built-in function module, a lock variable register 1080 that holds a lock state of a plurality of PE1010-0, 1010-1, 1010-2, 1010-3, a shared resource 1030, and a shared resource 1030. .. PE1010-0, 1010-1, 1010-2, 1010-3 can be used as an arithmetic element. PE1010-0, 1010-1, 1010-2, 1010-3, shared resource 1030 and lock variable register 1080 are interconnected via the PE-to-PE connection bus 1040.

Each PE 1010-0, 1010-1, 1010-2, 1010-3 is accessed by one or more CPU cores 1100, a program executed by the CPU core 1100, which executes a program created according to a predetermined instruction set architecture. Inside the PE, which consists of a bus interface 1120 that controls access between the PE and the connection bus 1040 between PEs, a program, and / or a cache memory and / or a RAM memory that stores data necessary for program execution, upon request. Includes memory 1130. The bus interface 1120 is interconnected with the CPU core 1100 by the bus interface connection interface 1121 and the PE internal memory 1130 is interconnected with the CPU core 1100 by the PE internal memory-CPU core connection interface 1132. Further, the PE internal memory 1130 is interconnected with the bus interface 1120 by the PE internal memory-bus interface connection interface 1131.

The shared resource 1030 is a resource shared by applications operating on a plurality of PEs 1010-0, 1010-1, 1010-2, and 1010-3 in a time-division manner. The shared resource 1030 may be one or more peripheral modules with built-in microcomputers such as a communication module that controls communication with hardware connected to the outside of the microcomputer 1001, or one or more connected to the inside or outside of the PE. It may be at least a part of the memory of. For the sake of simplicity, only one shared resource 1030 is shown, but there may be two or more.

The lock variable register 1080 is accessible from each PE 1010-0, 1010-1, 1010-2, 1010-3 via the PE-to-PE connection bus 1040, and is arranged in a part of the address space of the microcomputer 1001. Will be done. The lock variable register 1080 is provided for each shared resource 1030, and holds a flag indicating whether or not the shared resource 1030 is in use (locked state).

FIG. 27 is a timing chart showing an access exclusive control method using a lock variable in the microcomputer of FIG. 26.
In FIG. 27, the lock variable held in the lock variable register 1080 has either an unlocked state (OFF) or a locked state (ON). If the application running on each PE 1010-0, 1010-1, 1010-2, 1010-3 uses the shared resource 1030, the application checks the state of the lock variable prior to actual use, and if it is in the unlocked state. , The lock is acquired by setting the lock variable to the locked state (P). The PE that has acquired the lock executes (U) a process that uses the shared resource 1030. When the processing is completed, the PE that has acquired the lock releases the shared resource 1030 by setting the lock variable to the unlocked state (V).

Here, when a plurality of PEs 1010-0, 1010-1, 1010-2, and 1010-3 simultaneously request the use of the shared resource 1030, the PEs that fail to acquire the lock are locked until the lock variable is in the unlocked state. Perform a spinlock (SL) process that keeps checking variables. Then, the PE that fails to acquire the lock can realize exclusive access to the shared resource 1030 by acquiring the lock when the lock variable is in the unlocked state.

FIG. 28 is a diagram showing an example of time change of power consumption in the microcomputer of FIG. 26.
In FIG. 28, in order to compare with the power consumption of FIGS. 24 and 25 under the same conditions, in each PE1010-1, 1010-2, 1010-3, when only one task for which the shared resource use authority needs to be granted is executed. Is assumed. In the comparative example, in particular, a plurality of PE1010-1, 1010-2, and 1010-3 have large power consumption during a long period of waiting for the granting of usage authority while spinlocking, and the peak and average consumption of the entire microcomputer 1001. It is pushing up the power.

The power consumption of the spinlock (SL) process increases in proportion to the number of PEs that require the use of the shared resource 1030 at the same time. Therefore, as the number of PEs mounted on the microcomputer 1001 increases, the peak power consumption of the entire microcomputer 1001 increases.

On the other hand, in the microcomputers 1 and 1B of FIGS. 1 and 4, exclusive access to the shared resource 1030 can be realized without executing the spinlock (SL) process, and the power consumption corresponding to that amount can be realized. Can be reduced. Therefore, even when the number of PEs mounted on the microcomputers 1 and 1B increases, it is possible to prevent an increase in the peak power consumption of the entire microcomputers 1 and 1B.

1, 1B: Microcomputer, 10, 20-1, 20-2, 20-3: Arithmetic element (processor element, PE), 30: Shared resource, 40: PE connection bus, 50: Usage request register, 50-0 , 50-1: Usage request register bank, 60, 60A: Usage authority control device, 61, 62-1, 62-2, 62-3: Usage authority control interrupt signal, 70: PE-to-PE interrupt control device, 71-0 , 71-1, 71-2, 71-3: Interrupt signal between PEs, 100: CPU core, 110: interrupt controller, 111: interrupt controller connection interface, 120: bus interface, 121: bus interface connection interface, 130: PE Internal memory, 131: PE internal memory-bus interface connection interface, 132: PE internal memory-CPU core connection interface, 140: control table, 141: control table connection interface, 510: shared resource usage request flag register, 520- 0,520-1,520-2,520-3: Shared resource usage request set register, 530: Shared resource usage request clear register, 600: Bus interface, 610-1, 610-2, 610-3, 610-4 : Hardware timer channel, 611: Hardware timer channel connection interface, 612-1, 612-2, 612-3, 612-4: Trigger control signal, 613-1, 613-2, 613-3, 613-4 : Timer value comparison result signal, 615: Channel status register, 616: Current count value register, 617: Initial count value register, 620: Trigger control unit, 621: Trigger control unit connection interface, 625: Start trigger register, 626: Stop Trigger register, 630, 630A: Interrupt request control unit, 631: Interrupt request control unit connection interface, 635, 635A: Interrupt factor register, 636, 636A: Interrupt enable register, 637: Channel mapping register, 710-m ,: Between PE Interrupt request flag register, 720-n :: PE-to-PE interrupt request set register, 730-m ,: PE-to-PE interrupt request clear register

Claims (10)

A first arithmetic unit that stores policy information regarding the allocation of shared resources and executes the allocation process of the shared resources based on the policy information .
A usage authority management device that holds at least one of the presence / absence of usage authority and the usage permission amount of the shared resource set based on the policy information.
A plurality of second arithmetic units that exclusively use the shared resource based on the operating state of the usage authority management device, and
A storage device for holding a request for use of the shared resource by the plurality of second arithmetic units is provided.
The first arithmetic unit is
Based on the request state held in the storage device and the policy information, the plurality of second arithmetic units are assigned the right to use the shared resource.
The operation of the usage authority management device so that the shared resource usage authority of one second arithmetic unit selected from the plurality of second arithmetic units becomes valid based on the request state held in the storage device and the policy information. Update the status,
Based on the comparison result between the usage permission amount and the predetermined value, the operating state of the usage permission management device is updated so that the shared resource usage permission of the selected second arithmetic unit becomes invalid.
Operates with a predetermined control cycle as a unit of time,
The license amount is reset during a predetermined period within the control cycle, and the license amount is reset.
An electronic control device that controls so that only the usage requests made within a predetermined period within the control cycle are valid among the usage requests of the shared resource notified from the plurality of second arithmetic units to the storage device. The electronic control device according to claim 1 , wherein the usage authority management device and the first arithmetic unit are mounted on the same or different silicon chips. The usage authority management device includes one or more counters.
The electronic control device according to claim 1 , wherein the count value of the counter is updated according to the lapse of a predetermined time or access to the shared resource. The usage authority management device is in a state in which the usage authority of the shared resource is granted to the second arithmetic unit by requesting the second arithmetic unit for an operation start interrupt indicating the start of counting operation of the counter. The electronic control device according to claim 3 , which notifies that. The usage authority management device requests the second arithmetic unit for an underflow interrupt indicating that the count value of the counter is equal to or less than a predetermined value, so that the usage authority of the shared resource is the second arithmetic unit. The electronic control device according to claim 3 , which notifies that the state is no longer given to the device. The usage authority management device requests the second arithmetic unit and the first arithmetic unit for an underflow interrupt indicating that the count value of the counter is equal to or less than a predetermined value, thereby causing the first arithmetic unit. The electronic control device according to claim 3 , which activates the predetermined processing of the above. A plurality of second arithmetic units that use the shared resource, and
A storage device that stores the usage request from the second arithmetic unit, and
Further, a usage authority control device for granting the usage authority of the shared resource to the second arithmetic unit based on the scheduling result of the use of the shared resource is provided.
The first arithmetic unit is
Accepting the usage request from the second arithmetic unit,
Scheduling the use of the shared resource is executed based on the policy information between the second arithmetic units that have received the usage request.
The electronic control device according to claim 1, wherein the second arithmetic unit exclusively uses the shared resource based on the usage authority granted by the usage authority control unit. Accepting the usage request, scheduling the use of the shared resource, and granting the permission to use the shared resource are repeatedly executed within the control cycle, or
The scheduling of the use of the shared resource and the granting of the permission to use the shared resource are repeatedly executed within the control cycle, and the acceptance of the usage request is before the control cycle in which the scheduling of the use of the shared resource is executed. The electronic control device according to claim 7 , which is executed within the control cycle. The usage authority control device includes a counter associated with each of the second arithmetic units on a one-to-one basis.
The electronic control unit according to claim 7 , wherein the second arithmetic unit exclusively uses the shared resource based on the operation of a counter associated with the second arithmetic unit. It is equipped with multiple arithmetic units that use shared resources, usage authority management units, and storage devices .
The plurality of arithmetic units are
Request the use of the shared resource
The shared resource is exclusively used based on the usage authority of the shared resource allocated to each of the plurality of arithmetic units in a time-division manner in response to the request for the use of the shared resource .
The plurality of arithmetic units include a first arithmetic unit that stores policy information regarding the allocation of the shared resource and executes the allocation process of the shared resource based on the policy information.
The usage authority management device holds at least one of the presence / absence of the usage authority and the usage permission amount of the shared resource set based on the policy information.
The plurality of arithmetic units include a plurality of second arithmetic units that exclusively use the shared resource based on the operating state of the usage authority management unit.
The storage device holds the presence / absence of a request for use of the shared resource by the plurality of second arithmetic units.
The first arithmetic unit is
Based on the request state held in the storage device and the policy information, the plurality of second arithmetic units are assigned the right to use the shared resource.
The operation of the usage authority management device so that the shared resource usage authority of one second arithmetic unit selected from the plurality of second arithmetic units becomes valid based on the request state held in the storage device and the policy information. Update the status,
Based on the comparison result between the usage permission amount and the predetermined value, the operating state of the usage permission management device is updated so that the shared resource usage permission of the selected second arithmetic unit becomes invalid.
Operates with a predetermined control cycle as a unit of time,
The license amount is reset during a predetermined period within the control cycle, and the license amount is reset.
An electronic control device that controls so that only the usage requests made within a predetermined period within the control cycle are valid among the usage requests of the shared resource notified from the plurality of second arithmetic units to the storage device.

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