JP2019128711A - Electronic control device - Google Patents

Abstract

To improve a utilization efficiency of a shared resource while maintaining a real-time characteristic of a process in a multi-core microcomputer.SOLUTION: PEs 20-1, 20-2, and 20-3 stores, in a usage request register 50, a usage request for a shared resource 30. A PE 10 receives the usage request for the shared resource 30 from the PEs 20-1, 20-2, and 20-3 on the basis of a request state held by the usage request register 50. Among the PEs 20-1, 20-2, and 20-3 that have the usage request received, a scheduling for usage of the shared resource 30 is executed on the basis of policy information on an allocation of the shared resource 30. A usage authority control device 60 gives a usage authority for the shared resource 30 to the PEs 20-1, 20-2, and 20-3 on the basis of a scheduling result for the usage of the shared resource 30. The PEs 20-1, 20-2, and 20-3 exclusively utilize the shared resource 30 on the basis of the usage authority given by the usage authority control device 60.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an electronic control unit capable of controlling access to shared resources of a multi-core microcomputer (also referred to as a many-core microcomputer).

  With the miniaturization of semiconductor processes, high integration and high functionality of embedded microcomputers are rapidly advancing. One of the important application destinations of embedded microcomputers is an in-vehicle electronic control unit (ECU) in the automobile field. With the background of the demand for system cost reduction, there is a need for a technology that enables the functions realized by multiple ECUs to be integrated into one ECU. Expected technologies include, for example, an integrated ECU equipped with a high-performance embedded microcomputer utilizing a multi-core, and an application execution base for appropriately executing an application for realizing each function integrated in the integrated ECU.

  The in-vehicle ECU that is largely related to the safety of the final product relies on ISO 26262, which is an international standard for in-vehicle embedded systems, as a functional safety framework that ensures its mounting quality and safety. ISO 26 262 is standardized with the goal of achieving both high safety and reliability in in-vehicle embedded systems and efficient software development, and introduces an indicator called Automotive Safety Integrity Level (ASIL), and derives ASIL derived Three factors (exposure, avoidance, hazard) and hazard analysis and risk assessment methods using them. The ASIL is a five-level representation of the level of safety that must be achieved to avoid possible hazards in the in-vehicle embedded system.

  When complying with ISO26262, the emphasis is on ensuring no interference between applications (Freedom From Interference, FFI). According to the FFI concept, when multiple applications with different ASILs are mixedly executed on one ECU, a malfunction generated in an application with lower ASIL will be for an application with higher ASIL. It is required to prevent propagation. There are three types of interference that can occur between applications defined by ISO26262: timing and execution (time domain), memory, and exchange of information.

  Incoherence in the time domain means that a failure that occurs during execution of an application or unexpected interrupt processing does not prevent the execution of another application related to safety. As a typical implementation means for that purpose, static or dynamic execution of application execution by combination of hardware for time management (such as watchdog timer) and software as a part of elements constituting real-time OS as execution basis Dynamic scheduling function and execution time monitoring function. When determining the execution schedule of multiple applications (or tasks that are components of the application) operating simultaneously on the in-vehicle ECU, applications related to access to shared resources such as microcomputer internal or external memory and peripheral modules It is required that there is no contradiction in the dependency between

In the case where there are relatively few applications executing simultaneously or computing elements executing the applications, the following techniques for realizing exclusive control of resource sharing and access are used.
(1) Time-driven scheduling in which fixed time slots are allocated to each application in an appropriate order while maintaining the dependency between applications in units of time (Tick) managed by the scheduler of the real-time OS.
(2) Exclusive control of access to lock variables set for each shared resource by means of lock / unlock operations using means supported by the microcomputer architecture.

Tsutomu Sawada (2006) "Easy-to-understand embedded system construction techniques-software" Kyoritsu Publishing

  However, in the time-driven scheduling, when the time dedicated to the shared resource is less than Tick or greatly differs between applications, the use efficiency of the shared resource decreases. In addition, since the usage resource assignment interval of the shared resource for a specific application increases in proportion to the number of applications, the real-time property of processing is degraded.

  In the access exclusive control, the use efficiency of computing elements is reduced due to the spin lock process, and an operation processing bottleneck occurs, and strict schedule management based on the priority necessary for realizing FFI is impossible.

  For this reason, even if any of the above-mentioned technologies is applied, the software execution base is integrated into the in-vehicle multi-core microcomputer mounted on the integrated ECU, and a large number of applications operating on the same share resources inside and outside the microcomputer. In both, real-time performance, which is a unique requirement for in-vehicle embedded systems, and realization of scalable resource sharing control that can continue to adapt to the increasing trend of the number of applications (or computing elements) that run in parallel on a microcomputer It was difficult to let

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an electronic control device capable of improving the utilization efficiency of shared resources while maintaining the real-time processing of the multi-core microcomputer. is there.

  In order to achieve the above object, an electronic control device according to a first aspect includes a first arithmetic device that stores policy information related to shared resource allocation and executes the shared resource allocation processing based on the policy information. Prepare.

  ADVANTAGE OF THE INVENTION According to this invention, the utilization efficiency of a shared resource can be improved, maintaining the real-time property of the process in a multi-core microcomputer.

FIG. 1 is a block diagram showing a configuration example of a microcomputer applied to the electronic control unit according to the first embodiment. FIG. 2 is a block diagram showing a configuration example of the usage right control apparatus of FIG. FIG. 3 is a block diagram showing a modification of the usage right control device of FIG. FIG. 4 is a view showing a modification of the microcomputer of FIG. FIG. 5 is a view showing a configuration example of the control table of FIG. FIG. 6 is a diagram showing a configuration example of the use request register of FIG. FIG. 7 is a view showing a configuration example of the inter-PE interrupt control device of FIG. FIGS. 8A and 8B are timing charts showing the relationship between the control cycle of the microcomputer shown in FIG. 1 and the shared resource use request time window. FIG. 9 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the first embodiment. FIG. 10 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the first embodiment. FIG. 11 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the first embodiment. FIG. 12 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the second embodiment. FIG. 13 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the second embodiment. FIG. 14 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the second embodiment. FIG. 15 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the third embodiment. FIG. 16 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the third embodiment. FIG. 17 is a flowchart showing the operation of giving the shared resource use right of the microcomputer according to the third embodiment. FIG. 18 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the third embodiment. FIG. 19 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the fourth embodiment. FIG. 20 is a flowchart showing an operation of giving shared resource use authority of the microcomputer according to the fourth embodiment. FIG. 21 is a flow chart showing an operation of giving shared resource use authority of the microcomputer according to the fourth embodiment. FIG. 22 is a flow chart showing a process of determining the order of granting use authority in the microcomputer of FIG. FIG. 23 is a flow chart showing a process of determining a grant destination of use authority in the microcomputer of FIG. FIG. 24 is a diagram showing an example of a time change of power consumption at the time of operation of FIG. 8A of the microcomputer of FIG. 1 or FIG. FIG. 25 is a diagram showing an example of the time change of the power consumption at the time of the operation of FIG. 8 (b) of the microcomputer of FIG. 1 or FIG. FIG. 26 is a block diagram showing a configuration example of a microcomputer according to a comparative example of the present embodiment. FIG. 27 is a timing chart showing an access exclusion control method using a lock variable in the microcomputer of FIG. FIG. 28 is a diagram showing an example of a time change of power consumption in the microcomputer of FIG.

  Embodiments will be described with reference to the drawings. The embodiments described below do not limit the invention according to the claims, and all of the elements described in the embodiments and their combinations are essential to the solution means of the invention. There is no limit.

  In the following description, “memory” is one or more entities that store programs and data, and each memory includes one or more nonvolatile memories, volatile memories, ROM, RAM, First-In-First- An Out (FIFO) type buffer memory, a ring type buffer memory, an interleave type buffer memory, an instruction cache, a data cache, or a register can be used. Part or all of the memory may be formed on the same silicon chip as the microcomputer (also referred to as a microcomputer) or may be formed on a different silicon chip. The memory may further include a non-volatile external storage device (eg, a hard disk drive or a solid state drive, a recording medium such as a memory card) accessible via the memory address space of the microcomputer.

  Further, in the following description, the microcomputer is a multi-core microcomputer including a plurality of arithmetic elements (processor elements, PEs). The implementation of one or more CPU cores constituting a PE may be a non-superscalar system having one instruction execution unit or a superscalar system having two or more instruction execution units. In order to detect a failure or a malfunction of the PE or CPU core, a lockstep configuration may be employed in which one PE is configured and the same program is simultaneously executed physically on a plurality of CPU cores. The microcomputer may include a hardware circuit (for example, Direct Memory Access Controller, DMAC) that executes memory access independently of the CPU core or based on an instruction from the CPU core.

  In the following description, the function may be described using the expression “kkk part”. However, the function may be realized by executing one or more programs in the instruction execution unit, or one or more functions. It may be realized by a hardware circuit (for example, Field Programmable Gate Array (FPGA) or Application Specific Integrated Circuit (ASIC)). When the function is implemented by the instruction execution unit, the function may be at least a part of the instruction execution unit, since the defined processing is appropriately performed using the memory and / or the communication external interface. The processing described with the function as the subject may be processing performed by an instruction execution unit or a CPU core having the instruction execution unit. Also, the instruction execution unit may include hardware circuitry that performs some or all of the processing. The program may be installed from one or more program sources to one or more memories accessible by the microcomputer. The program source may be located, for example, in a specific area on a non-volatile memory or in a recording medium readable by a microcomputer (for example, a memory card). The description of each function is an example, and a plurality of functions may be combined into one function, or one function may be divided into a plurality of functions.

  In the following description, when a description is made without distinguishing the same type of element, a reference number or a common number in the reference number is used, and when a description is made by distinguishing the same type of element, the reference number of the element is used. Or, instead of the reference code, an ID assigned to the element may be used.

FIG. 1 is a block diagram showing a configuration example of a microcomputer applied to the electronic control unit according to the first embodiment.
In FIG. 1, the microcomputer 1 includes a plurality of PEs 10, 20-1, 20-2 and 20-3, a shared resource 30, a use request register 50 and a use authority control device 60 as built-in function modules. PE10, 20-1, 20-2, 20-3 can be used as a calculation element. The PEs 10, 20-1, 20-2, 20-3, the shared resource 30, the use request register 50 and the use authority control device 60 are interconnected via the inter-PE connection bus 40. The PE 10 and the usage right control device 60 may be mounted on the same silicon chip, or may be mounted on different silicon chips. The usage right control device 60 may be the usage right control device 60A of FIG. The PE 10 operates as a master PE that executes a shared resource management program. The PEs 20-1, 20-2, and 20-3 operate as satellite PEs that execute user programs (hereinafter also referred to as applications) other than the shared resource management program. The application may be operated by the master PE. When the PE 10 executes the shared resource management program, the shared resource 30 allocation process can be realized based on the policy information regarding the allocation of the shared resource 30 between the PEs 20-1, 20-2, and 20-3. . Each PE 20-1, 20-2, 20-3 requests the use of the shared resource 30, and based on the authority to use the shared resource 30 allocated in a time-sharing manner in response to the request for use of the shared resource 30. The shared resource 30 can be used exclusively.

  At this time, the PEs 20-1, 20-2, and 20-3 store the use request of the shared resource 30 in the use request register 50. The PE 10 receives a use request for the shared resource 30 from the PEs 20-1, 20-2, and 20-3 based on the request state held in the use request register 50. Then, the PE 10 executes the scheduling of the use of the shared resource 30 based on the policy information on the assignment of the shared resource 30 among the PEs 20-1, 20-2, and 20-3 that have received the use request. The usage authority control device 60 grants the usage authority of the shared resource 30 to the PEs 20-1, 20-2, and 20-3 based on the scheduling result of the usage of the shared resource 30. The PEs 20-1, 20-2, and 20-3 exclusively use the shared resource 30 based on the usage authority given from the usage authority control device 60.

  Here, the policy information related to the allocation of the shared resource 30 can be individually set on the software or firmware for each of the PEs 20-1, 20-2, and 20-3. For this reason, depending on the processing content in charge of the PEs 20-1, 20-2, 20-3 and the degree of harm when the processing is delayed, the use of the shared resource 30 for the PEs 20-1, 20-2, 20-3. Even when the number of PEs 20-1, 20-2 and 20-3 that use the shared resource 30 increases, the priority and the usage time can be set flexibly, and the PEs 20-1, 20-2 and 20- can be set. It is possible to maintain the real-time property of the third processing.

  Also, the PE 10 executes scheduling of use of the shared resource 30, and the use authority control device 60 grants the use authority of the shared resource 30 to the PEs 20-1, 20-2, and 20-3. It is no longer necessary for the PEs 10, 20-1, 20-2, 20-3 to manage the occupied state and released state of the shared resource 30 by -2, 20-3, and the PEs 10, 20-1, 20-2, 20-3 It is possible to reduce the load.

  Furthermore, use of the shared resource 30 among the PEs 20-1, 20-2, 20-3 in synchronization with the control cycle managed by the real-time OS by the use authority control device 60 managing the use authority of the shared resource 30 It is not necessary to switch the authority, and the granularity of the usage time of the shared resource 30 of the PEs 20-1, 20-2, and 20-3 can be reduced. Therefore, within one control period, the PEs 20-1, 20-2, 20-2, 20-2, 20-3 can be used at least once with respect to the PEs 20-1, 20-2, 20-3 that have made use requests. The occupation time of the shared resource 30 can be varied according to the priority of 20-3, and the utilization efficiency of the shared resource 30 can be improved while maintaining the real-time processing of the multicore microcomputer.

  Furthermore, the PEs 20-1, 20-2, 20-3 store the use request of the shared resource 30 in the use request register 50, and the PE 10 makes the PE 20-1 based on the request state held in the use request register 50, By accepting the use request of the shared resource 30 from 20-2 and 20-3, the PEs 20-1, 20-2, and 20-3 use the shared resource 30 until the right to use the shared resource 30 is granted. Can be eliminated, and the decrease in computational efficiency due to spinlock can be suppressed.

Hereinafter, the configuration of the microcomputer 1 of FIG. 1 will be specifically described.
The PE 10 is executed by one or more CPU cores 100-0 that execute a program created according to a predetermined instruction set architecture, an interrupt controller 110-0 that controls interrupt requests related to the PE 10, and a CPU core 100-0. A bus interface 120-0 for controlling access between the PE 10 and the inter-PE connection bus 40 in response to an access request from the program, a cache memory and / or a RAM memory for storing a program and / or data necessary for program execution And a control table 140 storing policy information required for access control of the shared resource 30.

  The interrupt controller 110-0 is provided by the interrupt controller connection interface 111-0, the bus interface 120-0 is provided by the bus interface connection interface 121-0, and the PE internal memory 130 is provided by the PE internal memory-CPU core connection interface 132-0. Interconnected with the CPU core 100-0. Further, the PE internal memory 130-0 is interconnected with the bus interface 120-0 by the PE internal memory-bus interface connection interface 131-0 and the control table 140 by the control table connection interface 141, respectively. At least the usage authority control interrupt signal 61 output from the usage authority control device 60 is input to the interrupt controller 110-0 as a signal indicating an interrupt request to the PE 10. The control table 140 may be either a memory independent of the PE internal memory 130-0, a part of the PE internal memory 130-0, or a memory (not shown) outside the PE 10 connected to the inter-PE connection bus 40. It may be configured as an elevator.

  The PE 20-1 includes one or more CPU cores 100-1 that execute a program created according to a predetermined instruction set architecture common to the PE 10, an interrupt controller 110-1 that controls interrupt requests related to the PE 20-1, and a CPU. Necessary for execution of the bus interface 120-1, the program, and / or the program that controls access between the PE 20-1 and the inter-PE connection bus 40 in response to an access request from the program executed by the core 100-1. A PE internal memory 130-1 including a cache memory for storing data and / or a RAM memory is included. The interrupt controller 110-1 is provided by the interrupt controller connection interface 111-1, the bus interface 120-1 is provided by the bus interface connection interface 121-1, and the PE internal memory 130-1 is provided by the PE internal memory-CPU core connection interface 132-1. Are mutually connected with the CPU core 100-1. Further, the PE internal memory 130-1 is interconnected with the bus interface 120-1 by a PE internal memory-bus interface connection interface 131-1. At least the usage authority control interrupt signal 62-1 output from the usage authority control device 60 is input to the interrupt controller 110-1 as a signal indicating an interrupt request to the PE 20-1.

  The PEs 20-2 and 20-3 can be configured similarly to the PE 20-1. At least the use authority control interrupt signal 62-2 and 62-3 output by the use authority control device 60 as a signal indicating an interrupt request for the PE 20-2 and 20-3 to the interrupt controller of the PE 20-2 and 20-3. Is entered. The use authority control interrupt signals 62-1, 62-2, and 62-3 are independent signals for the PEs 20-1, 20-2, and 20-3.

  The shared resource 30 is a resource that is shared in a time-sharing manner by applications operating on the plurality of PEs 20-1, 20-2, and 20-3 according to the control of the shared resource management program. The shared resource 30 is, for example, one or more built-in peripheral modules such as a communication module that controls communication with hardware connected to the outside of the microcomputer 1, or PEs 10, 20-1, 20-2, 20. -3 It may be at least a partial area of one or more memories connected inside or outside. Although only one shared resource 30 is illustrated for simplification of the description, it may be two or more.

FIG. 2 is a block diagram showing a configuration example of the usage right control apparatus of FIG.
In FIG. 2, the usage authority control device 60 includes a bus interface 600 that controls access to a control register in the usage authority control device 60 via the inter-PE connection bus 40, and four hardware timer channels 610-1 and 610-2. 610-3, 610-4, and trigger control signals 612-1, 612-2, 612-3, 612-4 for the hardware timer channels 610-1, 610-2, 610-3, 610-4 are generated. A trigger control unit 620 for generating, and an interrupt request control unit 630 for generating use authority control interrupt signals 61, 62-1, 62-2, and 62-3 for the PEs 10, 20-1, 20-2, and 20-3. . The trigger control unit 620 outputs the trigger control signals 612-1, 612-2, 612-3, and 612-4 independently for each hardware timer channel 610-1, 610-2, 610-3, and 610-4. To do. The number of hardware timer channels 610-1, 610-2, 610-3, and 610-4 is equal to or greater than the number of satellite PEs in which an application using the shared resource 30 operates. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 is interrupted by the hardware timer channel connection interface 611, the trigger controller 620 is triggered by the trigger controller connection interface 621, and the interrupt request controller 630 is interrupted. The request control unit connection interface 631 interconnects the bus interface 600.

  The hardware timer channels 610-1, 610-2, 610-3 and 610-4 are provided with a channel status register 615 indicating the operating status of the channel, a current count value register 616 for holding the current count value, and a current value at the start of counting. An initial count value register 617 for holding an initial count value to be loaded into the count value register 616 is provided independently for each channel. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 requests access from the hardware timer channel connection interface 611 to the channel state register 615, the current count value register 616 and the initial count value register 617. In response to this, the reading / writing to the designated channel state register 615, the current count value register 616 and the initial count value register 617 is executed. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 has at least two states during count operation and count stop, which can be identified by the contents of channel state register 615, and Equipped with

  (1) When the trigger control signals 612-1, 612-2, 612-3, 612-4 instruct the start of the count operation of the own channel, the contents of the initial count value register 617 are compared with the current count value register 616. And the contents of the channel status register 615 are updated so as to be a value indicating that the count operation is being performed. At this time, when the content of the current count value register 616 is larger than a lower limit (for example, zero) previously defined by means not shown, the content of the current count value register 616 is decremented each time a predetermined time elapses. .

  (2) When trigger control signals 612-1, 612-2, 612-3, 612-4 instruct the termination of the count operation of the own channel, the value of the content of channel state register 615 indicates that the count is stopped. And the contents of the current count value register 616 are held.

  (3) While the hardware timer channel 610-1, 610-2, 610-3, 610-4 is counting, depending on whether the content of the current count value register 616 of the channel is equal to or less than the lower limit value. The comparison results that are true / false are output as timer value comparison result signals of the own channel among the timer value comparison result signals 613-1, 613-2, 613-3, and 613-4.

  It should be noted that the count stop instruction for the hardware timer channels 610-1, 610-2, 610-3, and 610-4 whose count is stopped is ignored as an invalid instruction. Further, the count start instruction for the hardware timer channels 610-1, 610-2, 610-3, and 610-4 during the counting operation is interpreted as a valid instruction for continuing the counting operation. However, whether to copy the contents of the initial count value register 617 to the current count value register 616 again according to the count start instruction may be selectable by means not shown.

  The trigger control unit 620 is a bitmap format start trigger register 625 that simultaneously instructs the start of counting to one or more hardware timer channels 610-1, 610-2, 610-3, and 610-4, and stops counting simultaneously. Is provided with a stop trigger register 626 in a bitmap format. The trigger control unit 620 responds to an access request from the trigger control unit connection interface 621 to the start trigger register 625 and the stop trigger register 626 so that writing to the designated start trigger register 625 and the stop trigger register 626 is performed. Configure. At the time of writing to the start trigger register 625, one or more of the trigger control signals 612-1, 612-2, 612-3, 612-4 in which the field value (for example, the value 1) instructing the start of counting is set Trigger control signals 612-1, 612-2, 612-3, and 612-4 for performing trigger output to the corresponding hardware timer channels 610-1, 610-2, 610-3, and 610-4 A predetermined signal instructing the start of counting is simultaneously output. For hardware timer channels 610-1, 610-2, 610-3, 610-4 set with other field values (for example, value 0), the trigger control signal 612-1 to the channel, Predetermined signals instructing maintenance of the channel state are simultaneously output as 612-2, 612-3, and 612-4.

  In addition, when writing to the stop trigger register 626, one of the trigger control signals 612-1, 612-2, 612-3, and 612-4 is set to a field value (for example, a value of 1) instructing a count stop. For one or more hardware timer channels 610-1, 610-2, 610-3, 610-4, trigger control signals 612-1, 612-2, 612-3, 612 for performing trigger output to the channels. 4, a predetermined signal for instructing to stop counting is simultaneously output. For hardware timer channels 610-1, 610-2, 610-3, 610-4 set with other field values (for example, value 0), the trigger control signal 612-1 to the channel, Predetermined signals instructing maintenance of the channel state are simultaneously output as 612-2, 612-3, and 612-4.

  The interrupt request control unit 630 includes hardware timer channels 610-1, 610-2, 610-3, and 610-4, and PEs 10, 20-1, 20-2, and 20-3 as interrupt destinations (ie, each PE 10). , 20-1, 20-2 and 20-3, the channel mapping register 637 defining the association with the authority control interrupt signal 61, 62-1, 62-2 and 62-3), the target of the interrupt request An interrupt factor register 635 that holds the state of occurrence of an event (hereinafter referred to as an interrupt request target event) for each PE10, 20-1, 20-2, 20-3 that is an interrupt destination and for each factor, and an interrupt request target Whether or not an interrupt request is permitted when an event occurs is determined for each of PEs 10, 20-1, 20-2, and 20-3 that are interrupt destinations. Comprising an interrupt enable register 636 to be set for each factor. The interrupt request control unit 630 responds to an access request from the interrupt request control unit connection interface 631 to the interrupt source register 635, the interrupt enable register 636 and the channel mapping register 637, and designates the specified interrupt source register 635, the interrupt enable register 636 and The channel mapping register 637 is configured to be read and written.

  As interrupt request target events, timer value comparison result signals 613-1, 613-2, 613-3, and 613-4 output from the hardware timer channels 610-1, 610-2, 610-3, and 610-4 are displayed. Transition from false to true, ie, detection of the current count value falling below a predetermined lower limit value in the hardware timer channels 610-1, 610-2, 610-3, and 610-4 in counting operation. Do. At this time, the interrupt request control unit 630 identifies the PEs 10, 20-1, 20-2, and 20-3 that are association destinations set in the channel mapping register 637, and the PEs 10, 20-1, 20-2, In the interrupt factor register 635 that holds the generation state of the interrupt request target event to 20-3, a predetermined value (for example, value 1) is set in the field indicating the use authority grant period end event.

  When the PE 10, 20-1, 20-2, and 20-3 are set in the interrupt enable register 636 so as to permit an interrupt request when a use authority grant period end event occurs, the use authority control interrupt signal is further set. An interrupt is requested to the PEs 10, 20-1, 20-2, and 20-3 via the 61, 62-1, 62-2, and 62-3. In the PEs 10, 20-1, 20-2, and 20-3 that have detected the interrupt request from the usage authority control device 60, as a part of the processing of the interrupt handler that operates in any of the CPU cores in the own PE, the processing body After the execution of, the field value indicating the occurrence of the use authority grant period end event is updated to an invalid value (for example, value 0) by writing to the interrupt factor register 635, and the interrupt request due to the event is invalidated.

  Here, the PEs 20-1, 20-2, and 20-3 can release the shared resource 30 based on an interrupt from the usage authority control device 60. Therefore, even when the usage time of the shared resource 30 is individually set for each of the PEs 20-1, 20-2, and 20-3, the PEs 20-1, 20-2, and 20-3 use the shared resource 30. The shared resource 30 can be released without monitoring the time, and the load on the PEs 20-1, 20-2, and 20-3 can be reduced.

FIG. 3 is a block diagram showing a modification of the usage right control device of FIG. Among the usage right control devices 60A, elements having the same reference numerals as the usage rights control device 60 in FIG. 2 are common, and thus part of the description will be omitted.
In FIG. 3, the usage authority control device 60A is a bus interface 600 that controls access to the control registers in the usage authority control device 60A via the inter-PE connection bus 40, and four hardware timer channels 610-1 and 610-2. , 610-3, 610-4, and trigger control signals 612-1, 612-2, 612-3, 612-4 for the hardware timer channels 610-1, 610-2, 610-3, 610-4 are generated. The trigger control unit 620 includes an interrupt request control unit 630A that generates use authority control interrupt signals 61, 62-1, 62-2, and 62-3 for the PEs 10, 20-1, 20-2, and 20-3. Each hardware timer channel 610-1, 610-2, 610-3, 610-4 is interrupted by the hardware timer channel connection interface 611, the trigger controller 620 is triggered by the trigger controller connection interface 621, and the interrupt request controller 630A is interrupted. The request control unit connection interface 631 interconnects the bus interface 600.

  The configurations and functions of hardware timer channels 610-1, 610-2, 610-3, 610-4 and trigger control unit 620 of usage right control device 60A are the same as those of usage right control device 60.

  The interrupt request control unit 630A includes hardware timer channels 610-1, 610-2, 610-3, and 610-4 and PEs 10, 20-1, 20-2, and 20-3 as interrupt destinations (ie, each PE 10, 20-1, 20-2, 20-3, channel mapping register 637 that defines the association with use authority control interrupt signals 61, 62-1, 62-2, 62-3) connected to the interrupt request target event. An interrupt factor register 635A that holds the generation state for each PE10, 20-1, 20-2, and 20-3 that is an interrupt destination and for each factor, and whether or not an interrupt request is permitted when an interrupt request target event occurs. Interrupt enable register set for each interrupt source PE 10, 20-1, 20-2, 20-3 and for each factor Equipped with a 36A. The interrupt request control unit 630A responds to an access request from the interrupt request control unit connection interface 631 to the interrupt factor register 635A, the interrupt enable register 636A and the channel mapping register 637, and designates the designated interrupt factor register 635A, the interrupt enable register 636A and The channel mapping register 637 is configured to be read and written.

  In this modification, in addition to the timer value comparison result signals 613-1, 613-2, 613-3, and 613-4 output by the hardware timer channels 610-1, 610-2, 610-3, and 610-4 Of the trigger control signals 612-1, 612-2, 612-3, and 612-4 output from the trigger control unit 620, at least a trigger control signal capable of identifying a count start instruction is also an interrupt request target event. As an interrupt request target event, the timer value comparison result signals 613-1, 613-2, 613-3, 613-4 transition from false to true, that is, the hardware timer channels 610-1, 610-2 during the counting operation. , 610-3, and 610-4, it is detected that the current count value has become equal to or less than a predetermined lower limit value. At this time, the interrupt request control unit 630A identifies the PEs 10, 20-1, 20-2, and 20-3 that are the association destinations set in the channel mapping register 637, and the PEs 10, 20-1, 20-2, In the interrupt factor register 635A that holds the state of occurrence of the interrupt request target event to 20-3, a predetermined value (for example, value 1) is set to the field value indicating the use authority grant period end event. If the PE10, 20-1, 20-2, 20-3 is set in the interrupt enable register 636A to permit an interrupt request when a use authority grant period end event occurs, a use authority control interrupt signal is further set. An interrupt is requested to the PEs 10, 20-1, 20-2, and 20-3 via the 61, 62-1, 62-2, and 62-3.

  In addition, when the trigger control signals 612-1, 612-2, 612-3, and 612-4 are instructed to start counting as an interrupt request target event, the interrupt request control unit 630A is set in the channel mapping register 637. An interrupt factor register that specifies PEs 10, 20-1, 20-2, and 20-3 as association destinations and holds the occurrence state of an interrupt request target event for the PEs 10, 20-1, 20-2, and 20-3 In 635A, a predetermined value (for example, value 1) is set in the field value indicating the usage authorization period start event. If the PE 10, 20-1, 20-2, 20-3 is set in the interrupt enable register 636 A to permit an interrupt request when a use authority grant period start event occurs, the use authority control interrupt signal is further set. An interrupt is requested to the PEs 10, 20-1, 20-2, and 20-3 via the 61, 62-1, 62-2, and 62-3.

  In the PEs 10, 20-1, 20-2, and 20-3 that have detected the interrupt request from the use authority control device 60A, as a part of the processing of the interrupt handler that operates in any of the CPU cores in the own PE, the processing body Prior to execution, the contents of the interrupt factor register 635A are read to identify the interrupt factor (use authority grant period start or end event). After execution of the processing body, the field value indicating the occurrence of the above-identified event is updated to an invalid value (for example, the value 0) by writing to the interrupt factor register 635A, and the interrupt request due to the event is invalidated. .

  Here, the PEs 20-1, 20-2, and 20-3 can start using the shared resource 30 or release the shared resource 30 based on an interrupt from the usage right control device 60A. For this reason, even when the use start timing and use time of the shared resource 30 are individually set for each of the PEs 20-1, 20-2, and 20-3, the PEs 20-1, 20-2, and 20-3 are shared. The shared resource 30 can be used exclusively without monitoring the usage state of the resource 30. For this reason, when it is necessary to use the shared resource 30, each PE 20-1, 20-2, 20-3 does not need to keep issuing a use request for the shared resource 30 until the right to use the shared resource 30 is obtained. , PE20-1, 20-2, 20-3 can be reduced.

  Normally, two interrupt factors, that is, the start and end events of the usage right grant period are not detected at the same time, and the interrupt factor can be identified by referring to the contents of the interrupt factor register 635A. The use authority control interrupt signals 61, 62-1, 62-2, and 62-3 to be output to 20-1, 20-2, and 20-3 may be shared among a plurality of events. Further, the usage authority control device 60A may be configured to be able to mask the count start request for the hardware timer channel 610-1, 610-2, 610-3, 610-4 during the counting operation by means not shown. .

FIG. 4 is a view showing a modification of the microcomputer of FIG. Elements of the microcomputer 1B that have the same reference numerals as those of the microcomputer 1 shown in FIG. 1 are the same, so a part of the description will be omitted.
In FIG. 4, the microcomputer 1B further includes an inter-PE interrupt control device 70 as a built-in function module. The inter-PE interrupt control device 70 is interconnected with the PEs 10, 20-1, 20-2, and 20-3 via the inter-PE connection bus 40. The inter-PE interrupt controller 70 includes control registers accessible from each of the PEs 10, 20-1, 20-2, and 20-3. The interrupt request source PE requests an interrupt to the own PE or another PE, and the interrupt request destination PE includes means for specifying the interrupt request source PE. Further, the inter-PE interrupt control device 70 uses inter-PE interrupt signals 71-0, 71-1, 71-2, 71-3 as independent signals indicating the inter-PE interrupt request status for the PE for each interrupt destination PE. It outputs and is input into the interrupt controller in PE10, 20-1, 20-2, and 20-3, respectively.

  Here, when receiving the release notification of the shared resource 30 from the PEs 20-1, 20-2, and 20-3, the inter-PE interrupt control device 70 can notify the PE 10 of the occurrence of the resource release event. When the PE 10 receives the resource release event occurrence notification, the PE 10 can perform rescheduling of the use of the shared resource 30 between the PEs 20-1, 20-2, and 20-3 that have issued the use request of the shared resource 30. . Therefore, in the PEs 20-1, 20-2, 20-3 to which the use authority of the shared resource 30 is given, the shared resources are used before the use time given to the PEs 20-1, 20-2, 20-3 is used up. Even when 30 is released, the PE 20-1, 20- that has issued a use request for the shared resource 30 without waiting for the elapse of the use time given to the PE 20-1, 20-2, 20-3. 2 and 20-3 can use the shared resource 30, and the utilization efficiency of the shared resource 30 can be improved.

FIG. 5 is a view showing a configuration example of the control table of FIG.
In FIG. 5, the control table 140 can store a control policy related to the shared resource 30 among the PEs 10, 20-1, 20-2, and 20-3. The PE 10 can execute the scheduling of the use of the shared resource 30 among the PEs 20-1, 20-2, and 20-3 that have received the use request by referring to the control table 140 when the shared resource management program is executed. it can.

The control table 140 stores a control policy to be referred to and updated when the use authority grant order control of the shared resources 30 for the PEs 10, 20-1, 20-2, and 20-3 is executed by executing the shared resource management program. It is an area. The control table 140 includes the following fields for each of the target PEs 10, 20-1, 20-2, and 20-3 for shared control.
In order to simplify the following description, unless otherwise specified, among the plurality of PEs 10, 20-1, 20-2, and 20-3 included in the microcomputers 1 and 1 B, the PE having the smallest PE identifier, that is, PE 0 is changed to PE 10. Let PE1, PE2, and PE3 be PE 20-1, 20-2, and 20-3 in ascending order of PE identifiers.

  (1) Enable (EN) field: This field indicates whether the settings of the following fields relating to the PEs 10, 20-1, 20-2, and 20-3 are valid. When an application operating on the PE 10, 20-1, 20-2, 20-3 can request the use of the shared resource 30, it must be set to be valid.

  (2) Basic priority (Priority, PR) field: Zero or a positive integer indicating the priority when granting the use authority of the shared resource 30 to the relevant PE 10, 20-1, 20-2, 20-3. It is. The smaller the value is, the higher the priority is, and the order of granting the usage right of the shared resource 30 becomes faster.

  (3) Control period upper limit time (PT) field: an upper limit value of shared resource use time that can be assigned to the PEs 10, 20-1, 20-2, and 20-3 in each control period. Set a value based on either an absolute value or a percentage of control cycle time. The result of adding the setting value of this field for all PEs 10, 20-1, 20-2 and 20-3 for which the EN field is valid at any time is the control cycle time (when using the absolute value as an index) or 100 % (When percentage is used as an indicator) must not be exceeded. This restriction may be imposed on the user as a restriction necessary for the normal operation of the microcomputers 1 and 1B, or a part of the functions of the shared resource management program is detected to detect the restriction violation during operation. If it is determined, predetermined error processing such as log acquisition may be executed. In addition, in order to compensate for control errors due to processing time variation related to shared resource management, control cycle time (when using absolute value as an index) or 100% (when using a ratio as an index) And may be compared with a value obtained by subtracting a predetermined grace time or a grace rate from.

  (4) Authority re-grant (Re-Grant, RG) field within a control cycle: In one control cycle, the PE 10, 20-1, 20-2, 20-3 uses the set value of the PT field as an upper limit, and the shared resource Specifies whether or not 30 can be divided and used multiple times. This field may be optional, in which case it is interpreted that prohibition of division is specified.

  (5) Authority within the control cycle (Order, OR) field: This field is updated by the shared resource management program for each control cycle based on a predetermined order determination algorithm. The set value is zero or a positive integer indicating the order of granting the shared resource use authority in the current control cycle, and each PE 10, 20-1, 20- is set so that the value set in this field is ascending from zero. 2 and 20-3 are used in a time-sharing manner. Depending on the order determination algorithm used, this field may be optional. For example, when there is a request for use of one or more shared resources 30 at the time of switching the use authorization destination PE, the PE with the highest priority is set. In the case where there is no request for use of the shared resource 30, the request for use of the shared resource 30 may be polled at predetermined intervals until a request occurs.

  (6) Remaining Time (RT) field in control cycle: Remaining time of use time of shared resource 30 that can be assigned to the relevant PE 10, 20-1, 20-2, 20-3 in the current control cycle Field. A value obtained by dividing the absolute value of time by the decrement operation period of the hardware timer channels 610-1, 610-2, 610-3, 610-4, that is, the hardware timer channels 610-1, 610-2, 610-3, It can be directly written in the initial count value register 617 or the current count value register 616 of 610-4, or can be a positive integer value obtained by converting the magnitude of the value into a value that can be directly compared. This field value is reset to a value obtained by converting the value of the PT field in accordance with the above procedure for each control cycle, and the granting period of the right to use the shared resource 30 for a certain PE 10, 20-1, 20-2, 20-3 is set. Each time the end of use or the end of use of the shared resource 30 is notified from the PE 10, 20-1, 20-2, 20-3, this field value related to the PE 10, 20-1, 20-2, 20-3 is updated. To be controlled. The updated value newly set in this field may be zero or a count value corresponding to the remaining time obtained by subtracting the actual usage time of the shared resource 30 from the current setting value.

  (7) Use authority granting flag (In-Use, IU) field: A flag indicating whether or not the use authority of the shared resource 30 is being granted to the PEs 10, 20-1, 20-2, and 20-3. It is. The number of PEs to which the shared resource management program simultaneously grants the right of use is at most 1, and only 0 or 1 of the fields in this number of PEs is true.

FIG. 6 is a diagram showing a configuration example of the use request register of FIG. Note that FIG. 6 shows the internal configuration of the use request register 50, the flag for holding the presence / absence of the use request of the shared resource 30 for each request source PE, and the inter-register mapping regarding flag set / clear means.
In FIG. 6, the use request register 50 is accessible from each of the PEs 10, 20-1, 20-2, 20-3 via the inter-PE connection bus 40, and is used in the address space of the microcomputers 1 and 1B. It can be arranged in the partial area. The use request register 50 includes two use request register banks having different addresses, that is, a use request register bank 50-0 (Bank-0) and a use request register bank 50-1 (Bank-1).

  The functions of the use request register banks 50-0 and 50-1 are common between the banks except for the difference in the addresses assigned to the control registers as the constituent elements. For example, one of the two use request register banks 50-0 and 50-1 is referred to by a common resource management program operating on the PE 10 for the purpose of controlling the use of the shared resource 30 in the current control cycle. The bank (hereinafter referred to as the front bank), and the other bank (hereinafter referred to as the back bank) that accumulates requests for assigning the right to use the shared resource 30 in the next control cycle from applications operating on the PEs 20-1, 20-2, and 20-3. Bank), and the front and back banks may be switched for each control cycle. In order to simplify the back bank address generation procedure to which the application accesses, a register (not shown) that stores a flag that identifies the allocation status of the front and back banks and the address area of the front and back banks according to the status of the flag By further providing an address conversion unit (not shown) to be replaced in the use request register 50, a function may be provided to fix the addresses of the front and back banks regardless of the assignment state of the banks. A part or all of the use request register 50 may be implemented as a hardware module designed specifically, or at least a part may be allocated to a memory connected to the inside or outside of the microcomputer 1 or 1B. Also, due to implementation restrictions, the use request register 50 may be configured as a single bank of only the use request register bank 50-0. A method of using each of the usage request register banks 50-0 and 50-1 in the 1-bank or 2-bank configuration will be described later together with a detailed control flow for granting the usage right of the shared resource 30.

  The use request register bank 50-0, 50-1 holds a use request flag register for holding the presence or absence of the use request of the shared resource 30 in a bit map format for each request source PE, and a use request flag stored in the use request flag register The following control registers are provided as means for setting / clearing each PE 10, 20-1, 20-2, 20-3 individually or collectively for a plurality of PEs.

  (1) Shared resource use request set register 520-0, 520-1, 520-2, 520-3: PE10, 20-1, 20-2, 20-3 set the use request flag of the shared resource 30, respectively. It is a 32-bit wide register that serves as an interface. From registers SET_REQ_REG0 (for requests from PE10), SET_REQ_REG1 (for requests from PE20-1), SET_REQ_REG2 (for requests from PE20-2), and SET_REQ_REG3 (for requests from PE20-3) for each requesting PE Configured An application that operates on each PE 10, 20-1, 20-2, 20-3 and requests the use authorization of the shared resource 30 uses the shared resource for its own PE within a predetermined time window of the control cycle. The value 1 is written in the flag set request fields SR0, SR1, SR2, SR3 in the request set registers 520-0, 520-1, 520-2, 520-3. Each flag set request field SR0, SR1, SR2, SR3 is mapped to an independent flag field RQ0, RQ1, RQ2, RQ3 in the shared resource use request flag register 510 for each request source PE, and the set request is made. The flag RQn (n = 0, 1, 2, 3) is set to the value 1 in response to the writing of the value 1 into SRn (n = 0, 1, 2, 3). In addition, at the time of reading of this register, it is assumed that a zero value is always read.

  (2) Shared resource use request flag register 510: Flag fields RQ0, RQ1, RQ2, and RQ3 that hold the presence / absence of use requests of the shared resource 30 by the PEs 10, 20-1, 20-2, and 20-3 in a bitmap format, respectively. Is a 32-bit wide read only register FLG_REQ_REG, which is integrated into one register. The shared resource management program operating on the PE 10 reads out.

  (3) Shared resource use request clear register 530: A 32-bit wide register CLR_REQ_REG serving as an interface when the PEs 10, 20-1, 20-2, and 20-3 clear the use request flag of the shared resource 30, respectively. The shared resource management program operating on the PE 10 writes. Clear request fields CR0, CR1, CR2, and CR3 mapped independently for each of the flag fields RQ0, RQ1, RQ2, and RQ3 of the shared resource use request flag register 510 to be cleared are aggregated into one register and cleared. The flag field RQn (n = 0, 1, 2, 3) is cleared to the value 0 in response to the writing of the value 1 into the request field CRn (n = 0, 1, 2, 3). At the time of reading, a zero value is always read.

FIG. 7 is a view showing a configuration example of the inter-PE interrupt control device of FIG. FIG. 7 shows the internal configuration of the inter-PE interrupt control unit 70, a flag for holding the presence or absence of an inter-PE interrupt request for each combination of request source / request destination PE, and mapping between registers regarding flag set / clear means. The
In FIG. 7, the inter-PE interrupt control device 70 can be accessed from each of the PEs 10, 20-1, 20-2, 20-3 via the inter-PE connection bus 40, and is one on the address space of the microcomputer 1B. A plurality of control registers arranged in the partial area are included. A part or all of the control register may be implemented as a hardware module designed specifically, or at least a part may be allocated to a memory connected to the inside or outside of the microcomputer 1B. The inter-PE interrupt control unit 70 aggregates the presence or absence of the inter-PE interrupt in a separate register for each request destination PE to be processed, and holds it in a bit map format for the request source PE from the specific request source PE. Regarding interrupt requests As a means to set individually or for multiple request destination PEs individually for each request destination PE, and for an inter-PE interrupt request flag for a specific request destination PE, separately for each request source PE The following control registers are provided as means for collectively clearing a plurality of request source PEs.

  (1) Inter-PE interrupt request set register 720-n (n = 0, 1, 2, 3): An inter-PE interrupt request flag having PEs 10, 20-1, 20-2, and 20-3 as request source PEs This is a 32-bit wide register serving as an interface for setting. From registers SET_IPIR_REG0 (for requests from PE10), SET_IPIR_REG1 (for requests from PE20-1), SET_IPIR_REG2 (for requests from PE20-2), and SET_IPIR_REG3 (for requests from PE20-3) for each requesting PE Configured An application that operates on each PE 10, 20-1, 20-2, 20-3 and requests message transmission based on a predetermined format to its own PE or another PE is an inter-PE interrupt request for its own PE (PEn) Among the flag set request fields SRn0, SRn1, SRn2, SRn3 in the set register 720-n (n = 0, 1, 2, 3), one or more fields corresponding to the PE that is the interrupt request destination from the own PE Write the value 1 to

  The flag set request field SRnm (m = 0, 1, 2, 3) of the inter-PE interrupt request set register SET_IPIR_REGn (n = 0, 1, 2, 3) is an inter-PE interrupt request aggregated for each interrupt request destination PE. It is mapped to the field RQnm (n = 0, 1, 2, 3) of the flag register FLG_IPIR_REGm (m = 0, 1, 2, 3), and the field RQnm according to the writing of the value 1 to the flag set request field SRnm Is set to the value 1. In addition, at the time of reading of this register, it is assumed that a zero value is always read.

  (2) Inter-PE interrupt request flag register 710-m (m = 0, 1, 2, 3): An inter-PE interrupt request flag for which PEs 10, 20-1, 20-2, and 20-3 are the request destination PEs A 32-bit read-only register serving as an interface capable of acquiring the request source PE in a bit map format. From registers FLG_IPIR_REG0 (for request to master PE10), FLG_IPIR_REG1 (for request to PE20-1), FLG_IPIR_REG2 (for request to PE20-2), FLG_IPIR_REG3 (for request to PE20-3) for each request destination Configured In general, an inter-PE interrupt request flag register 710-m (m = 0, m) is used for the purpose of specifying the request source of the inter-PE interrupt whose request is the self PE (PEm). Read from 1, 2, 3). The inter-PE interrupt signal 71-m (m = 0, 1, 2, 3) can be defined as a logical sum of the fields RQ0m, RQ1m, RQ2m, and RQ3m.

  (3) Inter-PE interrupt request clear register 730-m (m = 0, 1, 2, 3): An inter-PE interrupt request flag with PEs 10, 20-1, 20-2 and 20-3 as request destination PEs This is a 32-bit wide register serving as an interface for clearing. From each register CLR_IPIR_REG0 (for request to PE10), CLR_IPIR_REG1 (for request to PE20-1), CLR_IPIR_REG2 (for request to PE20-2), CLR_IPIR_REG3 (for request to PE20-3) for each request destination PE Configured Usually, an application for which an inter-PE interrupt request is requested clears an interrupt request from one or more PEs (PEn) that have completed processing among inter-PE interrupts that request the PE (PEm) as a request destination. Thus, writing to the inter-PE interrupt request clear register 730-m (m = 0, 1, 2, 3) is performed. The field CR nm (n = 0, 1, 2, 3) of the inter-PE interrupt request clear register CLR_IPIR_REGm (m = 0, 1, 2, 3) is an inter-PE interrupt request flag register FLG_IPIR_REGm (m = 0, 1, 2, The field RQnm is mapped to the field RQnm (n = 0, 1, 2, 3) of 3), and the field RQnm is cleared to the value 0 according to the writing of the value 1 to the field CRnm. In addition, at the time of reading of this register, it is assumed that a zero value is always read.

  The following are two main control models that focus on the relationship between the control period, which is a unit of control time, and the time window for accepting the use request of the shared resource 30 when realizing the shared resource use authority grant control based on the control policy. Explain.

FIGS. 8A and 8B are timing charts showing the relationship between the control cycle of the microcomputer shown in FIG. 1 and the shared resource use request time window.
8 (a) and 8 (b), the control period (Control Period) refers to the application operating on the microcomputers 1 and 1B, or the system clock with which the real-time OS providing the execution environment of the application serves as a reference for time management. It is a fixed time period generated based on (Tick). The operation of the application or / and the real time OS is controlled in principle in units of control cycles. In order to realize resource sharing control with a time granularity smaller than the control period, at least a part of the control state and control parameters related to the granting of the authority to use the shared resource 30 is reset (initialized) every control period, The granting period of the use authority of the resource 30 is completed within a single control cycle, the granting of authority over a plurality of control cycles is not performed, and one or more that requested the use authorization of the shared resource 30 in a specific control cycle The PE 10, 20-1, 20-2, and 20-3 may be imposed as a restriction to perform shared control so that at least one use authority is given within the control cycle. In the following description, it is assumed that the application executed on the PE 10 does not request the use of the shared resource 30, but the generality of the use authorization control based on the control policy is not lost.

  FIG. 8A shows a control model when the use request register 50 has a one-bank configuration including only the use request register bank 50-0. In this control model, one usage request register is stored between the usage right assignment request sharing request of the shared resource 30 from the PEs 20-1, 20-2, and 20-3 and the reference of the request status from the shared resource management program. The bank 50-0 is shared by time division. Therefore, the use request acceptance window period W for receiving the shared resource use request R in the control cycle is set only during a designated period from the beginning of each control cycle. The PEs 20-1, 20-2 and 20-3 which require allocation of the use authority are the shared resource use request set registers 520-1 and 520-2 of the use request register bank 50-0 within the use request acceptance window period W. The request flag of the shared resource use request flag register 510 is set via 520-3. If there is one or more use authority assignment requests within the use request acceptance window period W, the shared resource management program operating on the PE 10 is based on the control policy defined in the control table 140, and Determine the order of grant A.

  Subsequently, according to the determined order of assignment, the PEs 20-1, 20-2 and 20-3 to which the usage right is to be granted next are identified, and the hardware in the usage right control devices 60 and 60A required to manage the granting time Wear timer channels 610-2, 610-3, and 610-4 are set and activated. The PEs 20-1, 20-2, and 20-3 that are subject to authorization are polled for the operating state of the hardware timer channels 610-2, 610-3, and 610-4 associated with the own PE, or Recognizing that the authority to use the shared resource 30 is granted to the own PE by detecting the authority grant start interrupt via the outputted use authority control interrupt signals 62-1, 62-2, and 62-3, the shared resource Execute U of the application using 30. Under the control of the shared resource management program, the PEs 20-1, 20-2 and 20-3 to which the use authority is given can occupy the shared resource 30 for a period until the authorization end interrupt to the own PE is detected. .

  For example, in the control cycle (n−1), if there is a shared resource use request R from two PEs 20-1 and 20-3 within the use request acceptance window period W, the control cycle (n−1) The authority to use the shared resource 30 is allocated to the PEs 20-1 and 20-3 in a time-sharing manner. Then, the PEs 20-1 and 20-3 execute the application U by using the shared resource 30 exclusively within the control period (n-1). Further, in the control cycle (n), assuming that the shared resource use request R is received from the three PEs 20-1, 20-2, and 20-3 in the use request reception window period W, the control cycle (n) The authority to use the shared resource 30 is allocated to the PEs 20-1, 20-2, and 20-3 in a time division manner. Then, the PEs 20-1, 20-2, and 20-3 execute the application U by using the shared resource 30 exclusively within the control period (n).

  This makes it possible to realize resource sharing control with a smaller time granularity than each control cycle (n-1), (n), and to provide resource sharing control time granularity for each control cycle (n-1), (n). Can be changed. Therefore, for example, in the PEs 20-1 and 20-3 that have issued the shared resource use request R in the control cycle (n-1), use of the shared resource 30 in the PE 20-1 in the control cycle (n-1) Even when the right is assigned, the PE 20-3 can acquire the right to use the shared resource 30 within its control cycle (n-1), and the control cycle (n-1) after the control cycle (n-1) Since it is not necessary to wait for the execution U of the application until n) and (n + 1), it is possible to improve the calculation efficiency of the PE 20-3. A more detailed control flow will be described again with another figure.

  FIG. 8B shows a control model when the use request register 50 has a two-bank configuration of use request register banks 50-0 and 50-1. In this control model, usage request register banks 50-0 different from each other in the usage right assignment request accumulation of shared resources 30 from the PEs 20-1, 20-2 and 20-3 and the reference of the request status from the shared resource management program 50-1 can be assigned, and time-division sharing of the use request register bank 50-0 described with reference to FIG. 8A becomes unnecessary. Therefore, the entire control period (Control Period (n)) is set as a use request reception window period W (n + 1) for receiving the shared resource use request R in the next control period (Control Period (n + 1)). can do. The PEs 20-1, 20-2 and 20-3 requiring allocation of the use authority have the reverse side of the use request register banks 50-0 and 50-1 within the use request acceptance window period W (n + 1). The request flag of the shared resource use request flag register 510 is set through the shared resource use request set register 520-1, 520-2, 520-3. As a result of switching the front / back banks of the use request registers 50-0 and 50-1 at the beginning of each control cycle, when there is one or more use authority allocation requests on the front bank side, shared resources operated by the PE 10 Based on the control policy defined in the control table 140, the management program determines the use authority grant order A in the control cycle (n + 1).

  Subsequently, according to the determined order of assignment, the PEs 20-1, 20-2 and 20-3 to which the usage right is to be granted next are identified, and the hardware in the usage right control devices 60 and 60A required to manage the granting time Wear timer channels 610-2, 610-3, and 610-4 are set and activated. The PEs 20-1, 20-2 and 20-3 that are subject to authorization are connected to the polling of the operation status of the hardware timer channel 610-2, 610-3, 610-4 associated with the own PE, or to the own PE By detecting the authority grant start interrupt via the use authority control interrupt signals 62-1, 62-2, and 62-3, it is recognized that the use authority of the shared resource 30 is granted to the own PE, and the shared resource 30 Execute U of the application to use. Under the control of the shared resource management program, the PEs 20-1, 20-2 and 20-3 to which the use authority is given can monopolize the shared resource 30 for a period of time until the authorization end interrupt to the own PE is detected. .

  In this control model, an application can be executed in the form of a software pipeline with a control cycle as a unit. Therefore, compared with the control model in FIG. 8A, porting work required to adapt an existing application to this control model. Can be reduced. A more detailed control flow will be described again with another figure.

  Hereinafter, four typical control flows will be described in detail with regard to grant control of shared resource use authority based on control policy.

<First shared resource use authorization control flow>
9 to 11 are flowcharts showing the operation of giving the shared resource use right of the microcomputer according to the first embodiment.

The first shared resource use authorization control flow exemplifies the following case.
(1) The use request register 50 is configured as one bank (only the use request register bank 50-0), and is used as a use request register bank S30.

  (2) The usage authority control device is configured to be either 60 or 60A, and sets an interrupt request when a usage authority grant period end event occurs for all PEs to be permitted.

  (3) Regarding the setting of the control table 140, the basic priority (PR) field of the master PE (PE0) can be converted to zero (highest priority), and the upper limit time (PT) field in the control cycle can be converted into a use request reception window period. It is set to a value, and furthermore, the in-control-period reauthorization (RG) field is set to be invalid for each of the master PE (PE0) and all satellite PEs (PE1, PE2, PE3).

  (4) Only a predetermined time from the beginning of each control cycle is set as a use request acceptance window period W, and a shared resource use request from a satellite PE that requires the use authorization of the shared resource 30 within the control cycle is accepted. .

  (5) Notification of the use authority grant start timing is to poll the operation state of the hardware timer channel associated with the own PE provided in the use authority control devices 60 and 60A from the application operating on each satellite PE. To achieve.

  (6) Notification of use authority grant end timing is realized by requesting an interrupt associated with the use authority grant period end event from the use authority control devices 60 and 60A to the application operating on each satellite PE.

  The PEn which is the first satellite PE is associated with the hardware timer channel S41 included in the usage authority control devices 60 and 60A, and controls the end timing of granting the shared resource usage authority to at least the application S40 operating on the PEn and PEn. Do. Similarly, with respect to master PE (PE0), hardware timer channel S11 independent of hardware timer channel S41 is associated, and usage request acceptance is accepted as a part of shared control processing by shared resource management program S10 operating on PE0. In order to measure the window period W, more preferably, the state and operation of the hardware timer channel associated with the satellite PE holding the usage right is used as a replicated replica.

  The application S40 operating on PEn sets the request flag in the use request register bank S30 of 1-bank configuration. The shared resource management program S10 determines the usage authority assignment order and the usage authority control device while referring to / updates the shared resource usage request stored in the usage request register bank S30 and the control information set in the control table S20. Control 60 and 60A. It is assumed that the control table S20 is appropriately set prior to the start of the sharing control.

  In FIG. 9, when the shared resource management program S10 detects the start timing of the control cycle using hardware or software means (not shown), the following initialization processing S1001 is sequentially executed.

  (1) Simultaneous stop of all the hardware timer channels S11 and S41 is requested (T1001 and T1002) by writing to the stop trigger register 626 included in the usage right control devices 60 and 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request enter the stop state (S1101 and S4101), respectively.

  (2) The use request flag of all PEs is cleared by writing to the shared resource use request clear register 530 provided in the use request register bank S30, and the use request flag of PE0 is written by writing to the shared resource use request set register 520-0. Is set, the contents of the shared resource use request flag register 510 are updated (T1003) so that only the use request flag of PE0 becomes valid (S3001).

  (3) For all the PEs in the control table S20, the use authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. By updating (T1005) from the (PT) field value to a value (hereinafter referred to as a converted value) converted to a value that can be set in the count registers in the hardware timer channels S11 and S41, control at the start of the control cycle is performed. The initial state (S2001) of the table S20 is assumed.

  (4) The remaining time (RT) field value in the control period of the control table S20 is set to the initial count value register 617 of the hardware timer channels S11 and S41 associated with each PE (T1006 and T1007). At this point in time, a value corresponding to the use request acceptance window period W is set in the hardware timer channel S11 for PE0.

  (5) At the beginning of the control cycle, in order to operate the PE0 hardware timer channel S11 for the purpose of realizing the use request acceptance window period W in the form of granting the shared resource use authority to PE0, the PE0 use authority granting flag (IU) The field value is set (set to true) (T1008), and the state of the control table S20 is updated to the state S2002 in which PE0 holds the use authority. This processing combines processing relating to granting shared resource usage authority to PE0 and other PEn in common by combining with the basic priority setting of PE0 being highest, and other than PE0 before usage request acceptance window period W This is an optional process that is effective for suppressing the granting of usage rights to PEn.

  (6) The activation of the PE0 hardware timer channel S11 is requested (T1009) by writing to the start trigger register 625 included in the usage authority control devices 60 and 60A. The hardware timer channel S11 that has received the start request transitions to the operating state S1102, starts the decrement operation based on the predetermined condition with the value of the initial count value register 617 copied to the current count value register 616 as an initial value. .

  The application S40 operating on the PEn, which has detected the control cycle start timing by means similar to the shared resource management program S10, executes predetermined preprocessing such as initialization related to processing to be executed within the control cycle (S4001). Do. If the process to be executed requires the assignment of shared resource use authority, it is used as part of the pre-processing within the use request acceptance window period W, that is, while counting the hardware timer channel S11 for PE0. The use request flag of PEn is set (T4001) by writing to the PEn shared resource use request set register in the request register bank S30.

  Although not shown in the figure, an application operating on a satellite PE (PEm) different from PEn within the same use request acceptance window period W also sets the PEm use request flag in the same procedure. . As a result, at the end of the use request acceptance window period W, the use request flags of PE0, PEn and PEm are set in the use request register bank S30, and the state S3002 is reached.

  As shown in FIGS. 9 and 10, the application S40 on the PEn that has completed the pre-processing, as at least a part of the waiting process S4002 for granting the shared resource use authority to the PEn, indicates the channel state of the hardware timer channel S41 for PEn. The register 615 is polled (T4002, T4003, T4004) at a predetermined cycle. The application S40 polls until the usage right has been granted to PEn, that is, the hardware timer channel S41 is activated by an instruction of the shared resource management program S10 and the channel state register 615 becomes a value indicating that counting is in progress. Repeat the action.

  On the other hand, the hardware timer channel S11 for PE0 in the count operation state decrements the contents of the current count value register 616 every time a use request acceptance window period W and a predetermined time elapse. When it is detected that the contents of the current count value register 616 have become equal to or less than the predefined lower limit value, the usage right control devices 60, 60A receive the interrupt request registers 630, 635A in the interrupt request registers 635, 635A. The field value holding the occurrence state of the usage authorization period end event from the hardware timer channel S11 to PE0 is set to true. In this control flow, since an interrupt caused by the event is set to be permitted, an interrupt caused by the event is requested by the use authority control interrupt signal 61 to the PE0 (T1101).

  The shared resource management program S10 that has detected an interrupt request caused by the use authority grant period end event by the PE0 hardware timer channel S11 sequentially executes a series of processes S1002 related to the end of the use request acceptance window period W.

  (1) In the interrupt factor registers 635 and 635A included in the interrupt request control unit 630 and 630A of the usage right control apparatus 60 and 60A, hold the occurrence status of the usage authority granting period end event for the hardware timer channel S11 for PE0 to PE0 The field value is cleared to false, and more preferably, when the channel S11 continues the count operation state, the stop of the hardware timer channel S11 is requested by writing to the stop trigger register 626 (T1010). As a result, the hardware timer channel S11 transitions to the count stop state S1103.

  (2) With the end of the use request acceptance window period W implemented in the shared resource use authorization aspect for PE0, clear (set to false) the in-use grant flag (IU) field value of PE0 (T1011), The state of the control table S20 is updated to a state S2003 in which no PE0, PEn, and PEm hold the use authority. The process T1011 is paired with the process T1008, and when the process T1008 is omitted, the process T1011 may be omitted as well.

  (3) Subsequently, the remaining time (RT) field value in PE0 is updated in accordance with the setting of the reauthorization (RG) field in PE0. In this control flow, the RG field is set to be invalid (prohibition of re-applying), and in this case, the RT field value is converted to the remaining time zero so that use authorization to PE0 is not performed erroneously again. Update to value (T1012).

  (4) If the remaining time in the control cycle of PE0 becomes zero, the use request flag of PE0 is cleared (T1013) by writing to the shared resource use request clear register 530 provided in the use request register bank S30. As a result, the use request register bank S30 enters a state S3003 in which the use request flags of PEn and PEm are set.

  Subsequently, as shown in FIG. 10, the shared resource management program S10 reads the shared resource use request flag register 510 provided in the use request register bank S30 (T1014), and uses the shared resource stored in the use request acceptance window period W. The presence or absence of a request is checked (S1003). If one or more use requests have been made, based on the flow shown in FIG. 22, the assignment order of the shared resource use right is collectively determined (S1004), and at least use of the shared resource 30 in the control table S20 is performed. For all requested PEs, a value specifying the determined grant order is set in the control cycle authorization order (OR) field (T1015). Furthermore, desirably, for PEs that are not targeted for shared resource use authorization in the current control cycle due to a predetermined reason such as no use request for shared resource 30 and invalidation of control policy setting in control table S20. A specific value indicating being outside may be set in the OR field of the PE.

  Thereafter, the shared resource management program S10 grants the use authority of the shared resource 30 to the satellite PE to be provided in accordance with the assignment order of the shared resource use right determined in the process S1004. The specific procedure is as follows.

  (1) Referring to the in-control-cycle authorization granting order (OR) field of the control table S20, the satellite PE to be granted the usage authorization next (or first) is specified (S1005). The in-use granting flag (IU) field value of the identified PE (referred to as PEn) is set (set to true) (T1016), and the state of the control table S20 is changed to the state S2004 in which the PEn holds the use right. Update.

  (2) In order to operate the hardware timer channel S10 for PE0 as a replica of the hardware timer channel S41 for PEn to which the next usage authorization is given, the remaining time within the control cycle of PEn in the setting of the control table S20 ( RT) A field value is set in the initial count value register 617 of the hardware timer channel S11 (T1017).

  (3) The simultaneous activation of the hardware timer channels S11 and S41 for PE0 and PEn is requested (T1018 and T1019) by writing to the start trigger register 625 provided in the usage right control devices 60 and 60A. The hardware timer channels S11 and S41 that have received the activation request respectively transition to the operating state (S1104 and S4102), and the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11 and S41 in each case. The decrement operation based on a predetermined condition is started with the value of as an initial value. Here, it is equivalent that the hardware timer channel S41 is in the count operation state and that the shared resource use right is being granted to PEn, and the two hardware timer channels S11 and S41 perform the decrement operation synchronously. I do.

  The application S40 polling (T4004) the channel state register 615 of the hardware timer channel S41 for PEn in a predetermined cycle as at least a part of waiting processing S4002 for granting the shared resource usage right to PEn is a hardware timer channel. When the count operation state of S41, that is, the state indicating that the right to use PEn has been granted, is detected, processing S4003 involving the use of the shared resource 30 is executed. While the application timer S40 can occupy and use the shared resource 30 while the hardware timer channel S41 is in the count operation state, an interrupt request caused by an end-of-authorization period end event notifying an end timing of the end of use authority is It is assumed that the process S4003 must be ended before it occurs.

  The time set in the initial count value register 617 of each hardware timer channel S11, S41 after the hardware timer channels S11, S41 for PE0 and PEn transit to the count operation state by the simultaneous start request (T1018, T1019), ie, When the time designated in the control cycle remaining time (RT) field assignable to PEn in the control table S20 has elapsed, the interrupt factor register 635 included in the interrupt request control unit 630 or 630A of the usage right control unit 60 or 60A In 635A, field values holding the occurrence status of usage authorization period end event for hardware timer channel S11 to PE0 and usage authorization period termination event for hardware timer channel S41 to PEn are respectively It is set to true. In this control flow, since the interrupt based on the event is set to be permitted, the hardware channels S11 and S41 use the interrupt for notifying the end of the use authorization period based on the event as the use authority interrupt signal. Request for PE0 (T1102) and PEn (T4101) at the same time.

  The application S40 that has detected an interrupt request caused by the use authority grant period end event by the hardware timer channel S41 for PEn executes a process S4004 related to the end of the use authority grant period as shown in FIG.

  (1) In the interrupt factor registers 635 and 635A included in the interrupt request control unit 630 and 630A of the usage right control apparatus 60 and 60A, hold the occurrence status of the usage authority giving period end event for the hardware timer channel S41 to PEn for PEn The field value is cleared to false, and more desirably, when the channel S41 continues the count operation state, the stop of the hardware timer channel S41 is requested by writing to the stop trigger register 626 (T4005). As a result, the hardware timer channel S41 transitions to the count stop state S4103.

  (2) If necessary, the application S40 executes predetermined post-processing S4005 such as recovery processing from interruption, processing that does not require shared resource use authority and should be executed within the control cycle.

  The shared resource management program S10 that has detected an interrupt request due to the usage authorization period end event by the hardware timer channel S11 for PE 0 sequentially executes the following processing as processing S1006 related to the termination of the usage authority period.

  (1) In the interrupt factor registers 635 and 635A included in the interrupt request control unit 630 and 630A of the usage right control apparatus 60 and 60A, hold the occurrence status of the usage authority granting period end event for the hardware timer channel S11 for PE0 to PE0 The field value is cleared to false, and more preferably, when the hardware timer channel S11 continues the count operation state, the hardware timer channel S11 is requested to stop by writing to the stop trigger register 626 ( T1020). As a result, the hardware timer channel S11 transitions to the count stop state S1105.

  (2) As an option process corresponding to safety, the interrupt factor registers 635 and 635A clear the field value holding the occurrence state of all events for PEn to false, and write to the stop trigger register 626 for PEn The stop of the hardware timer channel S41 is requested (T1021).

  (3) For the control table S20, clear (set to false) the flag (IU) field value in use granting of PEn (T1022), and no PE0, PEn, PEm hold the use right in a state S2005. Update.

  (4) Subsequently, the remaining time (RT) field value in the PEn control period is updated according to the setting of the authority re-grantion (RG) field in the PEn control period. In this control flow, the RG field is set to be invalid (prohibition of re-applying), in which case, the RT field value is converted to equivalent to the remaining time zero so that use authorization to PEn is not performed erroneously again. Update to value (T1023).

  (5) When the remaining time in the control period of PEn becomes zero, the use request flag of PEn is cleared by writing to the shared resource use request clear register 530 provided in the use request register bank S30 (T1024). As a result, the use request register bank S30 enters a state S3004 in which the use request flag of PEm is set.

  Subsequently, the shared resource management program S10 executes a series of processes S1007 related to the specification of the PE to which the use authority is given next to the PEn and the grant of the authority of the shared resource 30 to the specified PE. The specific procedure is as follows.

  (1) Refer to the authority grant order (OR) field in the control table S20, and specify the satellite PE to which the use authority is to be given next. The use authorization granting flag (IU) field value of the identified PE (PEm) is set (set to true) (T1025), and the state of the control table S20 is changed to the state S2006 in which the PEm holds the use authority. Update.

  (2) In order to operate the PE0 hardware timer channel S11 as a replica of the PEm hardware timer channel (not shown) which is the next use authority grant destination, the PEm control cycle is set in the control table S20. The remaining time (RT) field value is set in the initial count value register 617 of the hardware timer channel S11 (T1026).

  (3) Simultaneous activation of the hardware timer channel S11 for PE0 and the hardware timer channel (not shown) for PEm is requested by writing to the start trigger register 625 included in the usage right control device 60 or 60A (T1027, T1028) Do. The hardware timer channel S11 that has received the start request transitions to the operating state (S1106), and the value of the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11 is set as an initial value, Initiate a decrement operation based on conditions. The hardware timer channel for PEm (not shown) also starts the decrement operation according to the same procedure, and enters a count operation state indicating that the shared resource use right is being granted to PEm.

  According to this control flow, by using the limited functions installed in the microcomputers 1 and 1B, the above-mentioned use authority granting process is sequentially executed to request assignment of use authority within the use request acceptance window period W. For all PEs, it is possible to realize resource sharing control that grants the right to use at least once in each control cycle based on a strict priority setting and in a time unit with as fine a granularity as the hardware timer channels S11 and S41 allow.

<Second shared resource use authorization control flow>
12 to 14 are flowcharts showing the operation of giving the shared resource use authority of the microcomputer according to the second embodiment.
In the second shared resource use authorization control flow, the conditions of (2) and (5) are different with respect to the first shared resource use authorization control flow.

  (2) The usage authority control device has a configuration of 60A, sets an interrupt request when the usage authority grant period end event occurs for all PEs to be enabled, and interrupt requests when a usage authority grant period start event occurs for all PEs except PE0. Set to permission.

  (5) Notification of the use authority grant start timing is realized by requesting an interrupt associated with the use authority grant period start event from the use authority control device 60A to the application operating on each satellite PE.

  The hardware timer channel S41 of the usage right control device 60A is associated with the first satellite PE PEn, and controls the start / end timing of granting shared resource usage authority to the application S40 operating on PEn and PEn. . Similarly, with respect to master PE (PE0), hardware timer channel S11 independent of hardware timer channel S41 is associated, and usage request acceptance is accepted as a part of shared control processing by shared resource management program S10 operating on PE0. In order to measure the window period W, more preferably, the state and operation of the hardware timer channel S41 associated with the satellite PE holding the usage right is used as a replicated replica. The application S40 operating on the PEn sets a request flag in the use request register bank S30 of 1 bank configuration, and the shared resource management program S10 controls the shared resource use request stored in the use request register bank S30 and the control table. While referring to / updating the control information set in S20, determination of the usage authorization order and control of the usage authorization control apparatus 60A are performed. It is assumed that the control table S20 is appropriately set prior to the start of the sharing control.

  In FIG. 12, when the shared resource management program S10 detects the start timing of the control cycle using hardware or software means (not shown), the following initialization processing S1001 is sequentially executed.

  (1) A simultaneous stop of all the hardware timer channels S11 and S41 is requested (T1001, T1002) by writing to the stop trigger register 626 included in the usage right control device 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request are in the stop state (S1101 and S4101), respectively.

  (2) The use request flag of all PEs is cleared by writing to the shared resource use request clear register 530 provided in the use request register bank S30, and the use request flag of PE0 is written by writing to the shared resource use request set register 520-0. Is set, the contents of the shared resource use request flag register 510 are updated (T1003) so that only the use request flag of PE0 becomes valid (S3001).

  (3) For all the PEs in the control table S20, the use authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. The control table at the start of the control cycle is updated by updating (T1005) the (PT) field value to a value (hereinafter referred to as a conversion value) converted into a value settable in the count register in the hardware timer channel S11, S41. Let S20 be the initial state (S2001).

  (4) The remaining time (RT) field value in the control period of the control table S20 is set to the initial count value register 617 of the hardware timer channels S11 and S41 associated with each PE (T1006 and T1007). At this point, a value corresponding to the use request acceptance window period W is set in the hardware timer channel S11 for PE0.

  (5) At the beginning of the control cycle, in order to operate the PE0 hardware timer channel S11 for the purpose of realizing the use request acceptance window period W in the form of granting the shared resource use authority to PE0, the PE0 use authority granting flag (IU) The field value is set (set to true) (T1008), and the state of the control table S20 is updated to the state S2002 in which PE0 holds the use authority. This processing combines processing relating to granting shared resource usage authority to PE0 and other PEn in common by combining with the basic priority setting of PE0 being highest, and other than PE0 before usage request acceptance window period W This is an optional process that is effective for suppressing the granting of usage rights to PEn.

  (6) A request to start the PE0 hardware timer channel S11 is made by writing to the start trigger register 625 included in the use authority control device 60A (T1009). The hardware timer channel S11 that has received the start request transitions to the operating state S1102, starts the decrement operation based on the predetermined condition with the value of the initial count value register 617 copied to the current count value register 616 as an initial value. .

  The application S40 operating on the PEn, which has detected the control cycle start timing by means similar to the shared resource management program S10, executes predetermined preprocessing such as initialization related to processing to be executed within the control cycle (S4001). Do. If the process to be executed requires the assignment of shared resource use authority, it is used as part of the pre-processing within the use request acceptance window period W, that is, while counting the hardware timer channel S11 for PE0. The use request flag of PEn is set (T4001) by writing to the PEn shared resource use request set register in the request register bank S30.

  Although not shown, an application that operates on a satellite PE (PEm) different from PEn within the same use request acceptance window period W also sets the PEm use request flag in the same procedure. As a result, at the end of the use request acceptance window period W, the use request flags of PE0, PEn and PEm are set in the use request register bank S30, and the state S3002 is reached.

  Unlike the first shared resource use authority granting control flow, the application S40 on the PEn that has completed the pre-processing, as at least a part of the process of waiting for granting the shared resource use authority to the PEn, the PEn hardware timer channel S41 There is no need to poll the current channel status register 615. In response to the activation request of the hardware timer channel S41 by the shared resource management program S10, it suffices to wait for an interrupt caused by the usage authority assignment period start event to be requested from the usage right control device 60A. The period may be allocated to the execution of another task process.

  On the other hand, the hardware timer channel S11 for PE0 in the count operation state decrements the contents of the current count value register 616 every time a use request acceptance window period W and a predetermined time elapse. When it is detected that the content of the current count value register 616 has become equal to or less than the previously defined lower limit value, the use authority control device 60A determines that the hardware timer channel S11 is in the interrupt factor register 635A included in the interrupt request control unit 630A. The field value holding the occurrence state of the usage authorization period end event for PE0 to PE0 is set to true. In this control flow, since an interrupt caused by the event is set to be permitted, an interrupt caused by the event is requested by the use authority control interrupt signal 61 to the PE0 (T1101).

  The shared resource management program S10 that has detected the interrupt request T1001 caused by the usage authorization period end event by the hardware timer channel S11 for PE0 sequentially executes a series of processes S1002 related to the end of the usage request acceptance window period W. .

  (1) In the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, the field value holding the occurrence status of the usage authority giving period end event from the hardware timer channel S11 for PE0 to PE0 is cleared to false. More preferably, when the hardware timer channel S11 continues the count operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1010). As a result, the hardware timer channel S11 transitions to the count stop state S1103.

  (2) With the end of the use request acceptance window period W implemented in the shared resource use authorization aspect for PE0, clear (set to false) the in-use grant flag (IU) field value of PE0 (T1011), The state of the control table S20 is updated to a state S2003 in which no PE0, PEn, and PEm hold the use authority. The process T1011 is paired with the process T1008, and when the process T1008 is omitted, the process T1011 may be omitted as well.

  (3) Subsequently, the remaining time (RT) field value in PE0 is updated in accordance with the setting of the reauthorization (RG) field in PE0. In this control flow, the RG field is set to be invalid (prohibition of re-applying), and in this case, the RT field value is converted to the remaining time zero so that use authorization to PE0 is not performed erroneously again. Update to value (T1012).

  (4) If the remaining time in the control cycle of PE0 becomes zero, the use request flag of PE0 is cleared (T1013) by writing to the shared resource use request clear register 530 provided in the use request register bank S30. As a result, the use request register bank S30 enters a state S3003 in which the use request flags of PEn and PEm are set.

  Subsequently, as shown in FIG. 13, the shared resource management program S10 reads the shared resource use request flag register 510 provided in the use request register bank S30 (T1014), and uses the shared resource stored in the use request acceptance window period W. The presence or absence of the request is checked (S1003). If one or more use requests have been made, based on the flow shown in FIG. 22, the assignment order of the shared resource use right is collectively determined (S1004), and at least use of the shared resource 30 in the control table S20 is performed. For all requested PEs, a value specifying the determined grant order is set in the control cycle authorization order (OR) field (T1015). Furthermore, desirably, for PEs that are not targeted for shared resource use authorization in the current control cycle due to a predetermined reason such as no use request for shared resource 30 and invalidation of control policy setting in control table S20. A predetermined value indicating being outside may be set in the OR field of the PE.

  Thereafter, the shared resource management program S10 grants the use authority of the shared resource 30 to the satellite PE to be granted according to the order of granting the shared resource use authority determined in the process S1004. The specific procedure is as follows.

  (1) Referring to the in-control-cycle authorization granting order (OR) field of the control table S20, the satellite PE to be granted the usage authorization next (or first) is specified (S1005). The in-use granting flag (IU) field value of the identified PE (referred to as PEn) is set (set to true) (T1016), and the state of the control table S20 is changed to the state S2004 in which the PEn holds the use right. Update.

  (2) In order to operate the hardware timer channel S10 for PE0 as a replica of the hardware timer channel S41 for PEn to which the next usage authorization is given, the remaining time within the control cycle of PEn in the setting of the control table S20 ( RT) The field value is set in the initial count value register 617 of the channel S11 (T1017).

  (3) Requests simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 (T1018, T1019) by writing to the start trigger register 625 of the use authority control device 60A. The hardware timer channels S11 and S41 that have received the activation request respectively transition to the operating state (S1104 and S4102), and the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11 and S41 in each case. The decrement operation based on a predetermined condition is started with the value of as an initial value. Here, it is equivalent that the hardware timer channel S41 is in the count operation state and that the shared resource use right is being granted to PEn, and the two hardware timer channels S11 and S41 perform the decrement operation synchronously. I do.

  When the activation request T1018 for the hardware timer channel S41 for PEn is received from the shared resource management program S10, the use of the hardware timer channel S11 for PE0 in the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A. The field value holding the generation state of the authority grant period start event and the use authority grant period start event for the hardware timer channels S41 to PEn is set to true. In this control flow, only the interrupt caused by the latter event is set to be permitted. Therefore, the hardware timer channel S41 uses the interrupt that notifies the start of the use authorization period due to the event, the use authority interrupt signal. Request the PEn (T4121).

  The application S40 that has detected the interrupt request T4121 caused by the use authority grant period start event by the PEn hardware timer channel S41 executes a process S4021 related to the start of the use authority grant period. That is, in the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, the field value holding the occurrence state of the usage right giving period start event for the hardware timer channel S41 for PEn to PEn is cleared to false ( T4021), and then executes processing S4003 involving the use of the shared resource 30. Similar to the first control flow, while the hardware timer channel S41 is in the count operation state, the application S40 can occupy and use the shared resource 30, while the end of the granting period for notifying the granting end timing of the use right It is assumed that the process S4003 must be completed until an interrupt request caused by the occurrence of an event is generated.

  The time set in the initial count value register 617 of each hardware timer channel S11, S41 after the hardware timer channels S11, S41 for PE0 and PEn transit to the count operation state by the simultaneous start request (T1018, T1019), ie, When the time designated in the control cycle remaining time (RT) field assignable to PEn in control table S20 has elapsed, hardware timer is executed in interrupt factor register 635A included in interrupt request control unit 630A of usage right control device 60A. The field values that hold the occurrence status of the use authority grant period end event for channels S11 to PE0 and the use authority grant period end event for hardware timer channels S41 to PEn are respectively set to true. In this control flow, since the interrupt caused by the event is set to permission, as shown in FIG. 14, the hardware timer channels S11 and S41 notify the end of the use authorization period based on the event. The interrupt request is simultaneously requested to PE0 (T1102) and PEn (T4101) through the use authority interrupt signal.

  The application S40 that detects an interrupt request caused by the use authority grant period end event by the PEn hardware timer channel S41 executes a process S4004 related to the end of the use authority grant period.

  (1) In the interrupt factor register 635A of the interrupt request control unit 630A of the usage right control device 60A, clear the field value holding the occurrence of all events for PEn to false, and more preferably, the hardware timer channel When S41 continues the count operation state, the stop of the hardware timer channel S41 is requested by writing to the stop trigger register 626 (T4005). As a result, the hardware timer channel S41 transitions to the count stop state S4103.

  (2) If necessary, the application S40 executes predetermined post-processing S4005 such as recovery processing from an interrupt, processing that does not require shared resource use authority and should be executed within the control cycle.

  The shared resource management program S10 that has detected an interrupt request due to the usage authorization period end event by the hardware timer channel S11 for PE 0 sequentially executes the following processing as processing S1006 related to the termination of the usage authority period.

  (1) In the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, clear the field value holding the occurrence state of all events for PE0 to false, more preferably the hardware timer When the channel S11 continues the count operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1020). As a result, the hardware timer channel S11 transitions to the count stop state S1105.

  (2) As an option process for safety, clear the field value holding the occurrence state of all events for PEn in the interrupt factor register 635A to false, and write to the stop trigger register 626, the hardware for PEn The stop of the timer channel S41 is requested (T1021).

  (3) For the control table S20, clear (set to false) the flag (IU) field value in use granting of PEn (T1022), and no PE0, PEn, PEm hold the use right in a state S2005. Update.

  (4) Subsequently, the remaining time (RT) field value in the PEn control period is updated according to the setting of the authority re-grantion (RG) field in the PEn control period. In this control flow, the RG field is set to be invalid (prohibition of re-applying), in which case, the RT field value is converted to equivalent to the remaining time zero so that use authorization to PEn is not performed erroneously again. Update to value (T1023).

  (5) When the remaining time in the control period of PEn becomes zero, the use request flag of PEn is cleared by writing to the shared resource use request clear register 530 provided in the use request register bank S30 (T1024). As a result, the use request register bank S30 enters a state S3004 in which the use request flag of PEm is set.

  Subsequently, the shared resource management program S10 executes a series of processes S1007 related to the specification of the PE to which the use authority is given next to the PEn and the grant of the authority of the shared resource 30 to the specified PE. The specific procedure is as follows.

  (1) Refer to the authority grant order (OR) field in the control table S20, and specify the satellite PE to which the use authority is to be given next. The use authorization granting flag (IU) field value of the identified PE (PEm) is set (set to true) (T1025), and the state of the control table S20 is changed to the state S2006 in which the PEm holds the use authority. Update.

  (2) In order to operate the hardware timer channel S10 for PE0 as a replica of the hardware timer channel (not shown) for PEm to which the next usage authorization is given, control cycle of PEm among the settings of the control table S20 The remaining time (RT) field value is set in the initial count value register 617 of the channel S11 (T1026).

  (3) Simultaneous write of the hardware timer channel S11 for PE 0 and the hardware timer channel (not shown) for PEm is requested (T1027, T1028) by writing to the start trigger register 625 provided in the usage right control device 60A. The hardware timer channel S11 that has received the start request transitions to the operating state (S1106), and the value of the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11 is set as an initial value, Initiate a decrement operation based on conditions. The hardware timer channel for PEm (not shown) also starts the decrement operation according to the same procedure, and enters a count operation state indicating that the shared resource use right is being granted to PEm.

  Compared to the first control flow, according to this control flow, the polling process for acquiring the shared resource use authorization state for the satellite PE becomes unnecessary, and particularly the CPU in the satellite PE that supports the simultaneous execution of a plurality of tasks. The utilization efficiency of calculation resources such as cores can be improved.

<Third shared resource use authorization control flow>
FIG. 15 to FIG. 18 are flowcharts showing the operation of giving the shared resource use authority of the microcomputer according to the third embodiment.
In the third shared resource use authorization control flow, conditions of (3) and (6) are different from those of the second shared resource use authorization control flow.

  (3) Regarding the setting of the control table 140, the basic priority (PR) field of the master PE (PE0) can be converted to zero (highest priority), and the upper limit time (PT) field within the control cycle can be converted into a use request reception window period W. Set the value to a valid value, and enable the in-cycle reauthorization (RG) field of at least one satellite PE (PEn), and disable the RG field for satellite PEs excluding master PEn and master PE (PE0). Set to each.

  (6) The application S40 has completed the process involving the use of the shared resource 30 instead of detecting the interrupt request accompanying the occurrence of the use authority grant period end event from the use authority control device 60A that notifies the end timing of the use authority grant. At this point, the application S40 proactively notifies the shared resource management program S10 of the return of the use authority by an inter-PE interrupt request via the inter-PE interrupt control device 70.

  The hardware timer channel S41 of the usage right control device 60A is associated with the first satellite PE PEn, and controls the start / end timing of granting shared resource usage authority to the application S40 operating on PEn and PEn. . Similarly, with respect to master PE (PE0), hardware timer channel S11 independent of hardware timer channel S41 is associated, and usage request acceptance is accepted as a part of shared control processing by shared resource management program S10 operating on PE0. In order to measure the window period W, more preferably, the state and operation of the hardware timer channel S41 associated with the satellite PE holding the usage right is used as a replicated replica. The application S40 operating on the PEn sets a request flag in the use request register bank S30 of 1 bank configuration, and the shared resource management program S10 controls the shared resource use request stored in the use request register bank S30 and the control table. While referring to / updating the control information set in S20, determination of the usage authorization order and control of the usage authorization control apparatus 60A are performed. In this control flow, an inter-PE interrupt request via the inter-PE interrupt control device 70 is further used as a means for at least notifying the shared resource management program S10 of the return of the shared resource use right actively from the application S40. . It is assumed that the control table S20 is appropriately set prior to the start of the sharing control.

  In FIG. 15, when the shared resource management program S10 detects the start timing of the control cycle using hardware or software means (not shown), the following initialization processing S1001 is sequentially executed.

  (1) A simultaneous stop of all the hardware timer channels S11 and S41 is requested (T1001, T1002) by writing to the stop trigger register 626 included in the usage right control device 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request are in the stop state (S1101 and S4101), respectively.

  (2) The use request flag of all PEs is cleared by writing to the shared resource use request clear register 530 provided in the use request register bank S30, and the use request flag of PE0 is written by writing to the shared resource use request set register 520-0. Is set, the contents of the shared resource use request flag register 510 are updated (T1003) so that only the use request flag of PE0 becomes valid (S3001).

  (3) For all the PEs in the control table S20, the use authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. The control table at the start of the control cycle is updated by updating (T1005) the (PT) field value to a value (hereinafter referred to as a conversion value) converted into a value settable in the count register in the hardware timer channel S11, S41. Let S20 be the initial state (S2001).

  (4) The remaining time (RT) field value in the control period of the control table S20 is set to the initial count value register 617 of the hardware timer channels S11 and S41 associated with each PE (T1006 and T1007). At this point, a value corresponding to the use request acceptance window period W is set in the hardware timer channel S11 for PE0.

  (5) At the beginning of the control cycle, in order to operate the PE0 hardware timer channel S11 for the purpose of realizing the use request acceptance window period W in the form of granting the shared resource use authority to PE0, the PE0 use authority granting flag (IU) The field value is set (set to true) (T1008), and the state of the control table S20 is updated to the state S2002 in which PE0 holds the use authority. This processing combines processing relating to granting shared resource usage authority to PE0 and other PEn in common by combining with the basic priority setting of PE0 being highest, and other than PE0 before usage request acceptance window period W This is an optional process that is effective for suppressing the granting of usage rights to PEn.

  (6) A request to start the PE0 hardware timer channel S11 is made by writing to the start trigger register 625 included in the use authority control device 60A (T1009). The hardware timer channel S11 that has received the start request transitions to the operating state S1102, starts the decrement operation based on the predetermined condition with the value of the initial count value register 617 copied to the current count value register 616 as an initial value. .

  The application S40 operating on the PEn, which has detected the control cycle start timing by means similar to the shared resource management program S10, executes predetermined preprocessing such as initialization related to processing to be executed within the control cycle (S4001). Do. If the process to be executed requires the assignment of shared resource use authority, it is used as part of the pre-processing within the use request acceptance window period W, that is, while counting the hardware timer channel S11 for PE0. The use request flag of PEn is set (T4001) by writing to the PEn shared resource use request set register in the request register bank S30.

  Although not shown in the figure, an application operating on a satellite PE (PEm) different from PEn within the same use request acceptance window period W also sets the PEm use request flag in the same procedure. . As a result, at the end of the use request acceptance window period W, the use request flags of PE0, PEn and PEm are set in the use request register bank S30, and the state S3002 is reached.

  Similar to the second shared resource use authority granting control flow, the application S40 on the PEn that has completed the pre-processing uses the PEn hardware timer channel S41 as at least a part of the waiting process for granting the shared resource use authority to the PEn. There is no need to poll the channel status register 615. In response to the activation request of the hardware timer channel S41 by the shared resource management program S10, it suffices to wait for an interrupt caused by the usage authority assignment period start event to be requested from the usage right control device 60A. The period may be allocated to the execution of another task process.

  On the other hand, the hardware timer channel S11 for PE0 in the count operation state decrements the contents of the current count value register 616 every time a use request acceptance window period W and a predetermined time elapse. When it is detected that the content of the current count value register 616 has become equal to or less than the previously defined lower limit value, the use authority control device 60A determines that the hardware timer channel S11 is in the interrupt factor register 635A included in the interrupt request control unit 630A. The field value holding the occurrence state of the usage authorization period end event for PE0 to PE0 is set to true. In this control flow, since an interrupt caused by the event is set to be permitted, an interrupt caused by the event is requested by the use authority control interrupt signal 61 to the PE0 (T1101).

  The shared resource management program S10 that has detected the interrupt request T1101 caused by the use authorization period end event by the hardware timer channel S11 for PE0 sequentially executes a series of processes S1002 related to the end of the use request reception window period.

  (1) In the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, the field value holding the occurrence status of the usage authority giving period end event from the hardware timer channel S11 for PE0 to PE0 is cleared to false. More preferably, when the hardware timer channel S11 continues the count operation state, the hardware timer channel S11 is requested to be stopped by writing to the stop trigger register 626 (T1010). As a result, the hardware timer channel S11 transitions to the count stop state S1103.

  (2) With the end of the use request acceptance window period W implemented in the shared resource use authorization aspect for PE0, clear (set to false) the in-use grant flag (IU) field value of PE0 (T1011), The state of the control table S20 is updated to a state S2003 in which no PE0, PEn, and PEm hold the use authority. The process T1011 is paired with the process T1008, and when the process T1008 is omitted, the process T1011 may be omitted as well.

  (3) Subsequently, the remaining time (RT) field value in PE0 is updated in accordance with the setting of the reauthorization (RG) field in PE0. In this control flow, the RG field is set to be invalid (prohibition of re-applying), and in this case, the RT field value is converted to the remaining time zero so that use authorization to PE0 is not performed erroneously again. Update to value (T1012).

  (4) If the remaining time in the control cycle of PE0 becomes zero, the use request flag of PE0 is cleared (T1013) by writing to the shared resource use request clear register 530 provided in the use request register bank S30. As a result, the use request register bank S30 enters a state S3003 in which the use request flags of PEn and PEm are set.

  Subsequently, as shown in FIG. 16, the shared resource management program S10 reads the shared resource use request flag register 510 provided in the use request register bank S30 (T1014), and uses the shared resource stored in the use request acceptance window period W. The presence or absence of the request is checked (S1003). If one or more use requests have been made, one PE with the highest priority at the time of execution of this process is dynamically determined as the first shared resource use authorization destination based on the flow shown in FIG. 23 (S1041 ). In the shared control policy in this control flow, the setting value of the OR field may be arbitrary because it does not refer to the in-control cycle authorization order (OR) field in the control table S20.

  Thereafter, the shared resource management program S10 executes a process S1042 for granting the use authority of the shared resource 30 to the satellite PE that is a grant target of the share resource use authority dynamically determined in the process S1041. The specific procedure is as follows.

  (1) Set (set to true) the use authority granting flag (IU) field value of the PE (PEn) to which the use authority is to be granted (set to T1041), the status of the control table S20, and PEn Update to the held state S2004.

  (2) In order to operate the hardware timer channel S10 for PE0 as a replica of the hardware timer channel S41 for PEn to which the first usage authorization is given, the remaining time within the control cycle of PEn in the setting of the control table S20 ( RT) The field value is set in the initial count value register 617 of the channel S11 (T1017).

  (3) Requests simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 (T1018, T1019) by writing to the start trigger register 625 of the use authority control device 60A. The hardware timer channels S11 and S41 that have received the activation request respectively transition to the operating state (S1104 and S4102), and the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11 and S41 in each case. The decrement operation based on a predetermined condition is started with the value of as an initial value. Here, it is equivalent that the hardware timer channel S41 is in the count operation state and that the shared resource use right is being granted to PEn, and the two hardware timer channels S11 and S41 perform the decrement operation synchronously. I do.

  When the activation request T1018 for the hardware timer channel S41 for PEn is received from the shared resource management program S10, the use of the hardware timer channel S11 for PE0 in the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A. The field value holding the generation state of the authority grant period start event and the use authority grant period start event for the hardware timer channels S41 to PEn is set to true. In this control flow, only the interrupt caused by the latter event is set to be permitted. Therefore, the hardware timer channel S41 uses the interrupt that notifies the start of the use authorization period due to the event, the use authority interrupt signal. Request the PEn (T4121).

  The application S40 that has detected the interrupt request T4121 caused by the use authority grant period start event by the PEn hardware timer channel S41 executes a process S4021 related to the start of the use authority grant period. That is, in the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, the field value holding the occurrence state of the usage right giving period start event for the hardware timer channel S41 for PEn to PEn is cleared to false ( T4021), and then executes processing S4003 involving the use of the shared resource 30. Similar to the second control flow, while the hardware timer channel S41 is in the count operation state, the application S40 can occupy the shared resource 30 and can be used, while the end of the granting period for notifying the granting end timing of the use right It is assumed that the process S4003 must be completed until an interrupt request caused by the occurrence of an event is generated.

  In the second control flow, regardless of whether or not the process S4003 using the shared resource 30 is completed in the application S40, the shared resource continues until the usage authorization period end event and the interrupt request as the event factor are detected. PEn continues to hold 30 usage rights. On the other hand, in this control flow, when the right of use of the shared resource 30 becomes unnecessary, the following right of use is used as shown in FIG. A return process S4041 is executed independently.

  (1) In order to safely stop the hardware timer channel S41 for PEn in operation, writing to the interrupt enable register 636A included in the interrupt request control unit 630A of the usage right control device 60A makes all events targeted for PEn The interrupt request as a factor is temporarily prohibited (T4041).

  (2) In the interrupt factor register 635A, the field value holding the occurrence state of all events for PEn is cleared to false, and the stop trigger register 626 is written to stop the hardware timer channel S41 for PEn. Request (T4042). As a result, the hardware timer channel S41 transitions to the count stop state S4103.

  (3) The inter-PE interrupt request set register 720-n having the PEn as the request source PE included in the inter-PE interrupt control device 70 sets the inter-PE interrupt request flag having the PE0 as the request destination PE by writing to the PEn Request an inter-PE interrupt from PE to PE0 (T4043). In addition, when it is necessary to transmit a message different from the release of the shared resource 30 due to the return of the use authority for the inter-PE interrupt, a means (not shown) for notifying the interrupt factor accompanying the inter-PE interrupt signal May be provided separately.

  (4) By writing to the interrupt enable register 636A, the interrupt request temporarily prohibited in process T4041 is re-enabled (T4044).

  (5) If necessary, the application S40 executes predetermined post-processing S4005 such as a process that does not require the shared resource use authority and should be executed within the control cycle.

  The shared resource management program S10 that has detected the inter-PE interrupt request T4043 from PEn to PE0 via the inter-PE interrupt signal sequentially executes the following processing as processing S1043 related to use authority return.

  (1) In order to safely stop the hardware timer channel S10 for PE0 in operation, writing to the interrupt enable register 636A included in the interrupt request control unit 630A of the usage right control device 60A makes all events for the PE0 target The interrupt request as a factor is temporarily prohibited (T1042).

  (2) In the interrupt factor register 635A, the field value holding the occurrence state of all events for PE0 is cleared to false, and writing to the stop trigger register 626 stops the hardware timer channel S11 for PEn. Request (T1043). As a result, the hardware timer channel S41 transitions to the count stop state S1105.

  (3) As an optional processing for safety, in the interrupt factor register 635A, the field value holding the occurrence state of all the events for PEn is cleared to false and writing to the stop trigger register 626 makes the hardware for PEn hard The stop of the wear timer channel S41 is requested (T1021).

  (4) By writing to the interrupt enable register 636A, the interrupt request temporarily prohibited in the process T1042 is permitted again (T1044).

  (5) For the control table S20, clear (set to false) the flag (IU) field value in use granting of PEn (T1022), and no PE0, PEn, or PEm holds the use right in a state S2005. Update.

  (6) Subsequently, the control period remaining time (RT) field value of PEn is updated according to the setting of the control period reauthorization (RG) field of PEn. In this control flow, the RG field is set to be valid (re-granting permission), and in this case, the current count value register 616 of the hardware timer channel S41 for PEn or / and the hardware timer channel S11 for PE0 The contents of the current count value register 616 are read out (T1045, T1046), respectively, and the converted value of the remaining time in the control cycle that can be allocated to PEn is calculated by subtracting the time when PEn actually occupied the shared resource 30. The calculation method may be any one of the conversion value acquired in the process T1045, the average of the two conversion values acquired in the process T1045 and the process T1046, or the smaller value of the two conversion values.

  (7) For the PEn in the control table S20, the RT field value is updated to the converted value calculated in (6) (T1047).

  (8) In preparation for re-granting the shared resource use authority to PEn, the initial count value register 617 of the PEn hardware timer channel S41 is similarly updated to the converted value calculated in (7) (T1048).

  (9) If the remaining time within the control cycle of PEn calculated in (6) becomes zero, reauthorization of PEn within the current control cycle is prohibited regardless of the setting of the RG field, and the use request register bank S30 The PEn use request flag is cleared by writing to the shared resource use request clear register 530 (T1049). As a result, the use request register bank S30 is in either state S3041 in which the use request flags of PEn and PEm are set or in which only the use request of PEm is set. In this control flow, the following description will be continued assuming that the use request flags of PEn and PEm are set.

  Next, as shown in FIG. 18, the shared resource management program S10 executes a series of processes related to the specification of the PE to which the use authority is given next to PEn and the authorization of the shared resource 30 to the specified PE. To do. Specifically, the shared resource use request flag register 510 included in the use request register bank S30 is read again (T1050), and the shared resource use including use authority re-granting by the PE having a positive value as the remaining time within the control period The presence or absence of a request is checked (S1044). If there is one or more use requests, one PE with the highest priority at the time of execution of this process is dynamically determined as the next shared resource use authorization destination based on the flow shown in FIG. 23 (S1045 ).

  Thereafter, the shared resource management program S10 executes a process S1046 of granting the use authority of the shared resource 30 to the satellite PE to which the shared resource use right dynamically decided in the process S1045 is to be granted. The specific procedure is as follows.

  (1) Set the use authorization in-progress flag (IU) field value of the PE (PEn, assuming a case where the use authorization is given twice in a row to the same PE) to which the use authorization is given next (set to true (T1051), and the state of the control table S20 is updated to the state S2006 in which PEn holds the use authority again.

  (2) In order to operate the hardware timer channel S10 for PE0 as a replica of the hardware timer channel S41 for PEn to which the next usage authorization is given, the remaining time within the control cycle of PEn in the setting of the control table S20 ( RT) A field value is set in the initial count value register 617 of the hardware timer channel S11 (T1017). The value set here is a value obtained by subtracting a value corresponding to the time when the PEn actually occupied the shared resource 30 at the time of the first grant of use authorization.

  (3) Requests simultaneous activation of PE0 and PEn hardware timer channels S11 and S41 (T1018, T1019) by writing to the start trigger register 625 of the use authority control device 60A. As in the case of the first grant of authorization to PEn, the hardware timer channels S11 and S41 that have received the activation request respectively transition to the operating state (S1106 and S4141), and both count the current count of the hardware timer channels S11 and S41. With the value of the initial count value register 617 copied to the value register 616 as an initial value, a decrement operation based on a predetermined condition is started.

  Compared with the second control flow, according to this control flow, when the time when the satellite PE actually uses the shared resource 30 is shorter than the setting of the upper limit time in the control cycle in the control table S20, for example, non-stationary By allocating the surplus time to the shared resource use request by the interrupt processing, it is possible to reduce the dead time when the shared resource 30 is unused and to improve the utilization efficiency of the shared resource 30.

<Fourth shared resource use authorization control flow>
19 to 21 are flowcharts showing the operation of giving the shared resource use right of the microcomputer according to the fourth embodiment.
In the fourth shared resource use authorization control flow, conditions of (1), (3) and (4) are further different with respect to the second shared resource use authorization control flow example.

  (1) The use request register 50 has a configuration of two banks (use request register banks 50-0 and 50-1), and uses request register banks S31 and S32 (Bank-0 and Bank-1).

  (3) Regarding the setting of the control table 140, the enable (EN) field of the master PE (PE0) is set to be invalid, and the authority re-granting (RG) field within the control period is set to be invalid for all satellite PEs. .

  (4) As conceptually shown using FIG. 8B, the entire control cycle is set as a use request reception window period for receiving a shared resource use request in the next control cycle.

  The PEn that is the first satellite PE is associated with the hardware timer channel S41 included in the use authority control device 60A, and controls the start / end timing of the authority to use the shared resource to the application S40 operating on the PEn and the PEn. Do. Similarly, for the master PE (PE0), a hardware timer channel S11 independent of the hardware timer channel S41 is associated, and preferably as part of the sharing control process by the shared resource management program S10 operating on PE0, The state and operation of the hardware timer channel S41 associated with the satellite PE holding the usage right are used as a replicated replica.

  The application S40 operating on the PEn sets the request flag in the use request register bank on the back bank side among the use request register banks S31 and S32 of the two banks, and the shared resource management program S10 is executed on the table bank side. Reference and update of shared resource usage requests stored in the usage request register bank and control information set in the control table S20, respectively, and determination and use of the usage authority granting sequence while switching the front and back of the bank for each control cycle The authority control device 60A is controlled. It is assumed that the control table S20 is appropriately set prior to the start of the sharing control. Further, at the start of control, it is assumed that among the two use request register banks S31 and S32, the use request register bank S32 is a front bank (also referred to as a current bank) and the use request register bank S31 is a reverse bank.

  In FIG. 19, when the shared resource management program S10 detects the start timing of the control cycle using hardware or software means (not shown), the following initialization process S1061 is sequentially executed.

  (1) A simultaneous stop of all the hardware timer channels S11 and S41 is requested (T1001, T1002) by writing to the stop trigger register 626 included in the usage right control device 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request are in the stop state (S1101 and S4101), respectively.

  (2) At this time, the use request flags of all PEs are invalidated by clearing the use request flags of all PEs by writing to the shared resource use request clear register 530 included in the use request register bank S32 corresponding to the table bank. The content of the shared resource use request flag register 510 is updated (T1061) so as to be in the correct state (S3261).

  (3) The front and back banks of the use request register banks S31 and S32 are switched according to a predetermined procedure (T1062), and the use request register bank S31 is set as the front bank (S3161).

  (4) For all the PEs in the control table S20, the use authority granting flag (IU) field value is cleared (set to false) (T1004), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. The control table at the start of the control cycle is updated (T1005) to a value (hereinafter referred to as a converted value) converted from a (PT) field value to a value that can be set in the count registers in the hardware timer channels S11 and S41. Let S20 be the initial state (S2001).

  (5) In the initial count value register 617 of the hardware timer channel associated with each satellite PE, the remaining control period (RT) field value of the control table S20 is set (T1006). In this control flow, since it is not necessary to measure the use request reception window period using the PE0 hardware timer channel S11, it is not necessary to set or start the hardware timer channel S11 at this time.

  The application S40 operating on the PEn, which has detected the start timing of the control cycle by means similar to the shared resource management program S10, performs predetermined processing such as initialization related to processing to be executed in the current or / and next control cycle. The pre-processing is executed (S4061). If the process to be executed in the next control cycle requires the assignment of shared resource use authority, the shared resource use request for PEn in the use request register bank S32 on the back bank side as at least a part of the pre-processing By writing to the set register, the use request flag of PEn is set (T4061).

  Although not shown, an application operating on a satellite PE (PEm) different from PEn also sets the PEm use request flag in the use request register bank S32 by the same procedure. As a result, at the end of the current control cycle, it becomes a state S3262 in which use request flags of PEn and PEm are set in the use request register bank S32.

  Similar to the second shared resource use authority granting control flow, the application S40 on the PEn that has completed the preprocessing is used from the use authority control apparatus 60A in response to the activation request of the hardware timer channel S41 by the shared resource management program S10. It waits for an interrupt request due to an authorization period start event. The period until the interrupt request may be used to execute another task process. Whether the application S40 has been requested to grant the use authority of the shared resource 30 in the previous control cycle as an internal resource holding the correspondence between the interrupt caused by the use authority giving period start event and the control cycle A flag may be provided to indicate.

  Following initialization of the control table S20, the shared resource management program S10 reads the shared resource use request flag register 510 provided in the use request register bank S31 on the front bank side (T1063), and the shared resource stored in the previous control cycle The presence / absence of a use request is checked (S1062). In order to simplify the explanation, at this point in time it is assumed that no use request has been made from any satellite PEn or PEm, and the processing relating to use authorization in the current control cycle is ended.

  When the shared resource management program S10 detects the start timing of the control cycle again, the following initialization process S1061A is sequentially executed again.

  (1) A simultaneous stop of all the hardware timer channels S11 and S41 is requested (T1001A, T1002A) by writing to the stop trigger register 626 included in the usage right control device 60A. The hardware timer channels S11 and S41 for PE0 and PEn that have received the stop request transition to the stop state (S1101A, S4101A), or maintain the stop state.

  (2) At this time, the use request flags of all PEs are invalidated by clearing the use request flags of all PEs by writing to the shared resource use request clear register 530 provided in the use request register bank S31 corresponding to the table bank. The content of the shared resource use request flag register 510 is updated (T1064) so that the current state (S3162) is reached.

  (3) The front and back banks of the use request register banks S31 and S32 are switched according to a predetermined procedure (T1065), and the use request register bank S32 is set as the front bank (S3263).

  (4) For all PEs in the control table S20, the use authority granting flag (IU) field value is cleared (set to false) (T1004A), and the remaining time in the control cycle (RT) field value is the upper limit time in the control cycle. The control table at the start of the control cycle is updated (T1005A) to a value (hereinafter referred to as a converted value) converted from a (PT) field value to a value that can be set in the count registers in the hardware timer channels S11 and S41. Let S20 be the initial state (S2001A).

  (5) In the initial count value register 617 of the hardware timer channel associated with each satellite PE, set the remaining time (RT) field value within the control period of the control table S20 (T1006A). As in the case of the previous control cycle, at this time, setting or activation of the hardware timer channel S11 for PE 0 may not be performed.

  Subsequently, as shown in FIG. 20, the shared resource management program S10 reads the shared resource use request flag register 510 included in the use request register bank S32 on the front bank side (T1066), and shares the data stored in the previous control cycle. The presence / absence of a resource use request is checked (S1062A). If one or more use requests have been made, based on the flow shown in FIG. 22, the assignment order of the shared resource use right is collectively determined (S1004A), and at least use of the shared resource 30 in the control table S20 is performed. For all requested PEs, a value specifying the determined grant order is set in the control cycle authorization order (OR) field (T1015A). Furthermore, desirably, for PEs that are not targeted for shared resource use authorization in the current control cycle due to a predetermined reason such as no use request for shared resource 30 and invalidation of control policy setting in control table S20. A predetermined value indicating being outside may be set in the OR field of the PE.

  Thereafter, the shared resource management program S10 grants the use authority of the shared resource 30 to the satellite PE to be provided in accordance with the assignment order of the shared resource use right determined in the process S1004A. The specific procedure is as follows.

  (1) Referring to the control cycle in-cycle authorization granting order (OR) field of the control table S20, the satellite PE to be granted the usage authorization next (or first) is specified (S1005A). The in-use granting flag (IU) field value of the identified PE (PEn) is set (set to true) (T1016A), and the state of the control table S20 is changed to the state S2004A in which the PEn holds the use right Update.

  (2) In order to operate the hardware timer channel S10 for PE0 as a replica of the hardware timer channel S41 for PEn to which the next usage authorization is given, the remaining time within the control cycle of PEn in the setting of the control table S20 ( RT) Set the field value to the initial count value register of channel S11 (T1017A).

  (3) Requests simultaneous activation of the PE0 and PEn hardware timer channels S11 and S41 (T1018A and T1019A) by writing to the start trigger register 625 included in the use authority control device 60A. The hardware timer channels S11 and S41 that have received the activation request respectively transition to the operating state (S1104A, S4102A), and the initial count value register 617 copied to the current count value register 616 of the hardware timer channel S11 or S41. The decrement operation based on a predetermined condition is started with the value of as an initial value. Here, it is equivalent that the hardware timer channel S41 is in the count operation state and that the shared resource use right is being granted to PEn, and the two hardware timer channels S11 and S41 perform the decrement operation synchronously. I do.

  When the activation request T1018A for the hardware timer channel S41 for PEn is received from the shared resource management program S10, the use of the hardware timer channel S11 to PEn is performed in the interrupt factor register 635A provided in the interrupt request control unit 630A of the usage right control device 60A. The field value holding the generation state of the authority grant period start event and the use authority grant period start event for the hardware timer channels S41 to PEn is set to true. In this control flow, only the interrupt caused by the latter event is set to be permitted. Therefore, the hardware timer channel S41 uses an interrupt to notify the start of the use authorization period due to the event, the use authority interrupt signal Request to PEn (T4121A).

  The application S40 that has detected the interrupt request T4121A caused by the use authority grant period start event by the PEn hardware timer channel S41 executes the process S4021A related to the start of the use authority grant period. That is, in the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, the field value holding the occurrence state of the usage right giving period start event for the hardware timer channel S41 for PEn to PEn is cleared to false ( T1021A), and then executes processing S4003A involving the use of the shared resource 30. Similar to the second and second control flows, while the hardware timer channel S41 occupies the period shared resource 30 and can be used while the hardware timer channel S41 is in the count operation state, the application S40 is authorized to notify the use end timing of the use right. It is assumed that the process S4003A must be completed until an interrupt request caused by the period end event is generated.

  The time set in the initial count value register 617 of each hardware timer channel S11, S41 after the hardware timer channels S11, S41 for PE0 and PEn transit to the count operation state by the simultaneous start request (T1018A, T1019A), ie, When the time designated in the control cycle remaining time (RT) field assignable to PEn in control table S20 has elapsed, hardware timer is executed in interrupt factor register 635A included in interrupt request control unit 630A of usage right control device 60A. The field values that hold the generation status of the usage right grant period end event for channel S11 to PE0 and the usage right grant period end event for hardware timer channel S41 to PEn are set to true.In this control flow, since the interrupt caused by the event is set to be permitted, the hardware timer channels S11 and S41, as shown in FIG. 21, terminate the usage authorization period caused by the event. The interrupt to be notified is simultaneously requested to PE0 (T1102A) and PEn (T4101A) via the use authority interrupt signal.

  The application S40 that has detected an interrupt request due to the usage authorization period end event by the hardware timer channel S41 for PEn executes processing S4004A related to the termination of the usage authority period.

  (1) In the interrupt factor register 635A of the interrupt request control unit 630A of the usage right control device 60A, clear the field value holding the occurrence of all events for PEn to false, and more preferably, the hardware timer channel When S41 continues the count operation state, the stop of the hardware timer channel S41 is requested by writing to the stop trigger register 626 (T4005A). As a result, the hardware timer channel S41 transitions to the count stop state S4103A.

  (2) As necessary, the application S40 executes predetermined post-processing S4005A such as recovery processing from an interrupt, processing that should not be performed using the shared resource use right and is to be performed within the control period.

  The shared resource management program S10 that has detected an interrupt request due to the usage authorization period end event by the hardware timer channel S11 for PE 0 sequentially executes the following processing as processing S1063A related to the usage authority period termination.

  (1) In the interrupt factor register 635A included in the interrupt request control unit 630A of the usage right control device 60A, clear the field value holding the occurrence state of all events for PE0 to false, more preferably the hardware timer When the channel S11 continues the count operation state, the stop of the hardware timer channel S11 is requested by writing to the stop trigger register 626 (T1020A). As a result, the hardware timer channel S11 transitions to the count stop state S1105A.

  (2) As an option process corresponding to safety, the interrupt factor register 635A clears the field value holding the occurrence state of all the events for PEn to false, and writes to the stop trigger register 626 to write hardware for PEn. The stop of the wear timer channel S41 is requested (T1021A).

  (3) For the control table S20, clear (set to false) field value of the granting right of use of PEn (IU) field value (T1022A), and no PE0, PEn, and PEm hold the use right in a state S2005A. Update.

  (4) Subsequently, the remaining time (RT) field value in the PEn control period is updated according to the setting of the authority re-grantion (RG) field in the PEn control period. In this control flow, the RG field is set to be invalid (prohibition of re-applying), in which case, the RT field value is converted to equivalent to the remaining time zero so that use authorization to PEn is not performed erroneously again. Update to a value (T1023A).

  (5) When the remaining time in the control cycle of PEn becomes zero, the use request flag of PEn is cleared by writing to the shared resource use request clear register 530 included in the use request register bank S32 on the table bank side (T1067 ) As a result, the use request register bank S32 is in the state S3264 in which the use request flag of PEm is set.

  Subsequently, the shared resource management program S10 executes a series of processes S1007A relating to the identification of the PE to which the usage right is to be given next to the PEn and the assignment of the shared resource 30 to the identified PE. The specific procedure is as follows.

  (1) Refer to the authority grant order (OR) field in the control table S20, and specify the satellite PE to which the use authority is to be given next. The in-use granting flag (IU) field value of the identified PE (PEm) is set (set to true) (T1025A), and the state of the control table S20 is changed to the state S2006A in which the PEm holds the use right Update.

  (2) In order to operate the PE0 hardware timer channel S11 as a replica of the PEm hardware timer channel (not shown) which is the next use authority grant destination, the PEm control cycle is set in the control table S20. The internal remaining time (RT) field value is set in the initial count value register 617 of the hardware timer channel S11 (T1026A).

  (3) Simultaneous write of the hardware timer channel S11 for PE 0 and the hardware timer channel (not shown) for PEm is requested (T1027A, T1028A) by writing to the start trigger register 625 included in the usage right control device 60A. The hardware timer channel S11 that has received the start request transitions to the operating state (S1106A), and the value of the initial count value register 67 copied to the current count value register 616 of the hardware timer channel S11 is used as an initial value, Initiate a decrement operation based on conditions. The hardware timer channel for PEm (not shown) also starts the decrement operation according to the same procedure, and enters a count operation state indicating that the shared resource use right is being granted to PEm.

  Compared with the first control flow, according to the present control flow, it is not necessary to set a part of the control cycle as the use request reception window period, and the time corresponding to the use request reception window period is set in various satellite PEs. It is possible to allocate to use of processing and shared resource 30, and it is possible to further improve the utilization efficiency of computational resources such as CPU core and shared resource 30. In addition, time constraints on shared resource use request timing from satellite PEs are greatly eased, and affinity with software pipeline processing implementation in units of control cycles is high, facilitating porting of applications. Can.

  FIG. 22 is a flow chart showing a process of determining the order of granting use authority in the microcomputer of FIG. In FIG. 22, among the four typical shared resource use authorization control flows exemplified above, all of the one or more shared resource use requests stored in shared resource use request flag register 510 at the start of this processing The detailed flow of process S1004 and S1004 A which collectively determines the usage authorization provision order in the present control period with respect to a use request | requirement is shown.

  Here, a plurality of PEs 10, 20-1, 20-2, and 20-3 included in the microcomputers 1 and 1B are PE identifiers having unique values (zero or a positive integer value, where zero indicates PE0). Is assigned. The values that can be set in the basic priority (PR) field in the control table 140 are zero (highest priority, but can be set only for PE0) or a positive integer value less than a predetermined maximum value (lowest priority) It is either. Among PEs having the same priority, those with smaller PE identifiers are treated as higher priorities. In addition, the value indicating the assignment order of shared resource usage rights to be set in the control cycle authorization order (OR) field is zero or a positive integer value less than the number of PEs for PEs to be granted within the control cycle. One of the PEs that are not to be granted is a negative integer value (for example, -1), and authorization is given in ascending order from the PE set to the value zero.

  In FIG. 22, the order counter N and the priority counter P, which are internal parameters, are initialized to zero (S901). Subsequently, the content of the shared resource use request flag register 510 read before the start of this process is checked for the use request of the shared resource 30 (S902). If there is no use request (S902: No) The OR field value is set to −1 for all the PEs that are not subject to use authorization (S 910), and this processing ends.

  If there is a use request from one or more PEs (S902: Yes), the PE counter C is initialized to zero as an internal parameter for scanning the control table 140 for each PE (S903). Subsequently, as a process of determining whether a PE having a PE identifier that matches the value of the PE counter C can be a target of use authorization, the enable (EN) field value of the PE is true (valid) and the basic priority ( PR) Confirm in the control table whether the field value matches the value of priority counter P and the remaining time in control cycle (RT) field value is not zero, and additionally use request from the relevant PE It is checked whether or not there is (S904). If it is determined that the PE is to be assigned (S904: Yes), the value of the order counter N is set in the OR field of the PE, and then the order counter N is incremented (S905). If it is determined that the PE is not the assignment target PE (S904: No), the process S905 is skipped.

  Subsequently, the PE counter C is incremented (S906), and it is checked whether the value of the PE counter C is the maximum value, that is, ((the number of PEs included in the microcomputers 1 and 1B) -1) or more (S907). If the result of the process S 907 is not established (S 907: No), the process returns to the process S 904.

  When the result of the processing S907 is established (S907: Yes), the same processing for the PE with the next lowest priority, that is, the setting scan for each PE in the control table 140 and the order of granting the usage authority to the granting PE In order to execute the setting, the priority counter P is incremented (S908), and it is checked whether the value of the priority counter P is equal to or greater than a predetermined maximum value (S909). If the result of the process S 909 is not established (S 909: No), the process returns to the process S 903, and if established (S 909: Yes), the OR field value is set to −1 for all PEs not subject to use authorization. The setting is made (S910), and this processing is ended.

  FIG. 23 is a flow chart showing a process of determining a grant destination of use authority in the microcomputer of FIG. In FIG. 23, among the four typical shared resource use authorization control flows exemplified above, the highest priority is given to one or more shared resource use requests stored in shared resource use request flag register 510 at the start of this processing. The detailed flow of processing S1041 and S1045 which determine one high degree PE as the next usage authorization object is shown.

  Here, a plurality of PEs 10, 20-1, 20-2, and 20-3 included in the microcomputers 1 and 1B have PE identifiers (zero or positive integer values, where zero indicates PE0) having unique values. Assigned. The values that can be set in the basic priority (PR) field in the control table 140 are zero (highest priority, but can be set only for PE0) or a positive integer value less than a predetermined maximum value (lowest priority) It is either. Among PEs having the same priority, those with smaller PE identifiers are treated as higher priorities. Unlike the processing of FIG. 22, the control cycle authorization order (OR) field is not updated.

  In FIG. 23, the priority counter P, which is an internal parameter, is initialized to zero (S921). Subsequently, from the contents of the shared resource use request flag register 510 read before the start of this processing, the presence or absence of the use request is checked (S922). If there is no use request (S922: No), the next authority After the predetermined processing S 930 in the case where there is no assignment destination PE, the present processing ends.

  If there is a use request from one or more PEs (S922: Yes), the PE counter C is initialized to zero as an internal parameter for scanning the control table 140 for each PE (S923). Subsequently, as a process of determining whether a PE having the same PE identifier as the value of the PE counter C can be an object of usage authorization, the enable (EN) field value of the PE is true (valid) and the basic priority (PR) ) Check with control table 140 whether the field value matches the value of priority counter P and the remaining time in control cycle (RT) field value is not zero, and additionally use request from the relevant PE It is checked whether or not there is (S924). If it is determined that the PE is to be assigned (S 924: Yes), the PE is determined as the next assignment destination (S 925), and the process ends.

  If the result of the process S 924 is not satisfied (S 924: No), the PE counter C is incremented (S 926), and the value of the PE counter C is the maximum value, ie, ((the number of PEs provided to the microcomputers 1 and 1 B) −1) or more It is checked whether there is any (S927). If the result of the process S 927 is not established (S 927: No), the process returns to the process S 924.

  If the result of the process S 927 is satisfied (S 927: Yes), the priority counter P is incremented to execute the same process for the PE having the next lower priority, that is, the setting scan in PE units in the control table 140. (S928) Then, it is checked whether the value of the priority counter P is equal to or more than a predetermined maximum value (S929). If the result of the process S929 is not established (S929: No), the process returns to the process S923, and if established (S929: Yes), after performing the predetermined process S930 in the case where there is no next empowered PE, This process ends.

  As described above, according to the above-described embodiment, it is possible to improve the use efficiency of computation elements and shared resources as compared to access exclusive control using spin lock processing, and control specified by the user. It is possible to realize resource sharing control with a small time granularity suitable for applications that require strict scheduling control based on a policy and hard real-time performance. In addition, the power consumption for resource sharing control can be reduced by reducing the processing not involved in the operation.

FIG. 24 is a diagram showing an example of a time change of power consumption at the time of operation of FIG. 8A of the microcomputer of FIG. 1 or FIG.
In FIG. 24, not only the entire power consumption is averaged in the microcomputers 1 and 1B, but also the power consumption itself required for shared control is almost limited by the amount of one PE for which the shared resource management program operates. It contributes to the reduction of power consumption.

FIG. 25 is a diagram showing an example of the time change of the power consumption at the time of the operation of FIG. 8 (b) of the microcomputer of FIG. 1 or FIG.
Referring to FIG. 25, in the method of FIG. 8A, the shared resource use request R, the determination A of the grant order of use authority, the setting and activation S of the hardware timer channel, and the execution U of the application are executed in time series. . On the other hand, in the method of FIG. 8 (a), the shared resource use request R is executed in parallel with the determination A of the grant of use authority, the setting and activation S of the hardware timer channel, or the execution U of the application. Ru.
For this reason, in the method of FIG. 8 (b), when there is a shared resource use request R, the power consumption necessary for the processing is added to the power consumption of the method of FIG. 8 (a).

FIG. 26 is a block diagram showing a configuration example of a microcomputer according to a comparative example of the present embodiment.
In FIG. 26, the microcomputer 1001 includes a plurality of PEs 1010-0, 1010-1, 1010-2, 1010-3, a shared resource 1030, and a lock variable register 1080 that holds the lock state of the shared resource 1030 as built-in function modules. . PEs 1010-0, 1010-1, 1010-2, and 1010-3 can be used as computing elements. The PEs 1010-0, 1010-1, 1010-2, 1010-3, the shared resource 1030, and the lock variable register 1080 are interconnected via an inter-PE connection bus 1040.

  Each PE 1010-0, 1010-1, 1010-2, 1010-3 has one or more CPU cores 1100 that execute a program created according to a predetermined instruction set architecture, and access from programs executed by the CPU core 1100 A PE interface comprising a bus interface 1120 for controlling access between the relevant PE and the inter-PE connection bus 1040 according to a request, a program and / or a cache memory for storing data necessary for program execution and / or a RAM memory A memory 1130 is included. The bus interface 1120 is interconnected with the CPU core 1100 by the bus interface connection interface 1121, and the PE internal memory 1130 is interconnected with the CPU core 1100 by the PE internal memory-CPU core connection interface 1132, respectively. Furthermore, the PE internal memory 1130 is interconnected with the bus interface 1120 by the PE internal memory-bus interface connection interface 1131.

  The shared resource 1030 is a resource that is shared in a time-division manner by applications operating in the plurality of PEs 1010-0, 1010-1, 1010-2, and 1010-3. The shared resource 1030 is, for example, one or more microcomputer built-in peripheral modules such as a communication module for controlling communication with hardware connected to the outside of the microcomputer 1001, or one or more connected to the inside or outside of the PE. It may be at least a part of the memory of Although only one shared resource 1030 is illustrated for ease of explanation, it may be two or more.

  The lock variable register 1080 is accessible from each PE 1010-0, 1010-1, 1010-2, 1010-3 via the inter-PE connection bus 1040, and is arranged in a partial area on the address space of the microcomputer 1001. Is done. The lock variable register 1080 is provided for each shared resource 1030, and holds a flag indicating whether the shared resource 1030 is in use (locked state).

FIG. 27 is a timing chart showing an access exclusion control method using a lock variable in the microcomputer of FIG.
In FIG. 27, the lock variable held in the lock variable register 1080 has either the non-locked state (OFF) or the locked state (ON). When an application running on each PE 1010-0, 1010-1, 1010-2, 1010-3 uses the shared resource 1030, the application checks the state of the lock variable prior to actual use. The lock is acquired by setting (P) the lock variable to the locked state. The PE that has acquired the lock executes (U) processing that uses the shared resource 1030. When the processing is completed, the PE that has acquired the lock releases the shared resource 1030 by setting (V) the lock variable to the unlocked state.

  Here, when a plurality of PEs 1010-0, 1010-1, 1010-2, and 1010-3 request to use the shared resource 1030 at the same time, the PE that has failed to acquire the lock is locked until the lock variable is in an unlocked state. Execute spin lock (SL) processing that keeps checking variables. Then, the PE that failed in lock acquisition can realize exclusive access to the shared resource 1030 by acquiring the lock when the lock variable is in the non-locked state.

FIG. 28 is a diagram showing an example of a time change of power consumption in the microcomputer of FIG.
In FIG. 28, in order to compare with the power consumption of FIG. 24 and FIG. 25 under the same conditions, each PE 1010-1, 1010-2, 1010-3 executes only one task that needs to be given a shared resource use authority. Is assumed. In the comparative example, in particular, the plurality of PEs 1010-1, 1010-2, and 1010-3 have large power consumption during a long period of waiting for granting the use authority while being spin-locked, and the peak and average consumption of the entire microcomputer 1001 Power is being pushed up.

  The power consumption due to spin lock (SL) processing increases in proportion to the number of PEs that simultaneously request the use of the shared resource 1030. Therefore, as the number of PEs mounted on the microcomputer 1001 increases, the peak power consumption of the entire microcomputer 1001 increases.

  On the other hand, the microcomputers 1 and 1B of FIGS. 1 and 4 can realize exclusive access to the shared resource 1030 without executing the spin lock (SL) process, and consume power corresponding to the exclusive access. Can be reduced. Therefore, even when the number of PEs mounted on the microcomputers 1 and 1B increases, it is possible to prevent an increase in peak power consumption of the entire microcomputers 1 and 1B.

1, 1B: Microcomputer, 10, 20-1, 20-2, 20-3: Arithmetic element (processor element, PE), 30: Shared resource, 40: Connection bus between PEs, 50: Use request register, 50-0 50-1: Usage request register bank, 60, 60A: Usage authority control device, 61, 62-1, 62-2, 62-3: Usage authority control interrupt signal, 70: Inter-PE interrupt control device, 71-0 71-1, 71-2, 71-3: Interrupt signal between PEs, 100: CPU core, 110: Interrupt controller, 111: Interrupt controller connection interface, 120: Bus interface, 121: Bus interface connection interface, 130: PE Internal memory, 131: PE internal memory-bus interface connection interface, 132: PE internal Memory-CPU core connection interface 140: Control table 141: Control table connection interface 510: Shared resource use request flag register 520-0, 520-1, 520-2, 520-3: Shared resource use request set Register, 530: Shared resource use request clear register, 600: Bus interface, 610-1, 610-2, 610-3, 610-4: Hardware timer channel, 611: Hardware timer channel connection interface, 612-1 612-2, 612-3, 612-4: Trigger control signal, 613-1, 613-2, 613-3, 613-4: Timer value comparison result signal, 615: Channel status register, 616: Current count value register 617: Initial count value register 620: Riga control unit, 621: Trigger control unit connection interface, 625: Start trigger register, 626: Stop trigger register, 630, 630A: Interrupt request control unit, 631: Interrupt request control unit connection interface, 635, 635A: Interrupt factor register, 636, 636A: Interrupt enable register, 637: Channel mapping register, 710-m ,: Inter-PE interrupt request flag register, 720-n ,: Inter-PE interrupt request set register, 730-m ,: Inter-PE interrupt request clear register

Claims (15)

  An electronic control device comprising: a first arithmetic unit that stores policy information related to shared resource allocation and executes the shared resource allocation processing based on the policy information. A right of use management device that holds at least one of the presence / absence of the right of use of the shared resource and the use permission amount set based on the policy information;
A plurality of second computing devices that exclusively use the shared resource based on the operating state of the usage right management device;
The electronic control device according to claim 1, further comprising: a storage device that holds presence or absence of a use request for the shared resource by the plurality of second computing devices.   The electronic control device according to claim 2, wherein the first arithmetic device assigns the use authority of the shared resource to the plurality of second arithmetic devices based on the request state and the policy information held in the storage device. The first computing device is
The operation of the usage authority management device such that the shared resource usage authority of one second computing device selected from the plurality of second computing devices becomes effective based on the request state and the policy information held in the storage device Update the status,
The operation state of the usage right management device is updated so that the shared resource usage right of the selected one second computing device becomes invalid based on the comparison result of the usage permission amount and a predetermined value. Electronic control unit. The first computing device is
Operates on a predetermined control cycle time basis,
The electronic control device according to claim 4, wherein the use permission amount is reset in a predetermined period within the control cycle.   The first computing device is controlled to make only the usage request made during a predetermined period in the control cycle among the usage requests of the shared resource notified from the plurality of second computing devices to the storage device. The electronic control device according to claim 5.   The electronic control device according to claim 2, wherein the usage right management device and the first arithmetic device are mounted on the same or different silicon chip. The usage right management device comprises one or more counters,
The electronic control unit according to claim 2, wherein the count value of the counter is updated in response to a predetermined time lapse or access to the shared resource.   The usage right management device requests the second processing device to start an operation start interrupt indicating the start of the counting operation of the counter, whereby the second processing device is given the usage right of the shared resource. The electronic control device according to claim 8, which notifies that it is present.   The use authority management device requests the second arithmetic device to generate an underflow interrupt indicating that the count value of the counter is less than or equal to a predetermined value, whereby the use authority of the shared resource is the second operation. 9. The electronic control unit according to claim 8, wherein the electronic control unit is notified that it has not been assigned to the unit.   The use authority management device requests the second arithmetic device and the first arithmetic device to generate an underflow interrupt indicating that the count value of the counter is equal to or less than a predetermined value. The electronic control unit according to claim 8, wherein the predetermined processing of is started. A plurality of second computing devices using the shared resource;
A storage device for storing a use request from the second computing device;
A usage right control device for granting the usage right of the shared resource to the second computing device based on a scheduling result of usage of the shared resource;
The first computing device is
Accepting a use request from the second computing device;
Scheduling of use of the shared resource is executed based on the policy information between the second computing devices that have received the use request,
The electronic control device according to claim 1, wherein the second computing device exclusively uses the shared resource based on the usage right granted by the usage right control device. The acceptance of the use request, the scheduling of the use of the shared resource, and the granting of the use right of the shared resource are repeatedly performed within a control cycle, or
The scheduling of the use of the shared resource and the granting of the usage right of the shared resource are repeatedly performed in a control cycle, and the acceptance of the use request is before the control cycle in which the scheduling of the usage of the shared resource is executed. The electronic control device according to claim 12, which is performed within a control cycle. The use authority control device includes counters associated with each of the second arithmetic devices one to one,
The electronic control unit according to claim 12, wherein the second computing device exclusively uses the shared resource based on an operation of a counter associated with itself. Equipped with multiple computing devices that use shared resources,
The plurality of arithmetic devices are
Request the use of the shared resource,
An electronic control unit exclusively using the shared resource based on the usage authority of the shared resource time-divisionally assigned to each of the plurality of arithmetic devices in response to a request for use of the shared resource.

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