JP6987316B1 - Error correction / decoding device, control circuit, storage medium and error correction / decoding method - Google Patents

Abstract

An interference elimination unit (1) that removes interference from a received signal by a plurality of interference elimination algorithms and generates an interference elimination signal for each interference elimination algorithm, a demodulation unit (3) that demodulates the interference elimination signal, and a demodulation unit. Based on the error correction unit (4) that performs error correction decoding on the signal demodulated in (3) and outputs the decoding result and the judgment reference value indicating the reliability of the decoding result, and the judgment reference value, the most It is provided with an output control unit (10) that outputs a decoding result when a highly reliable determination reference value is obtained as a final error correction decoding result.

Description

The present disclosure relates to an error correction / decoding device, a control circuit, a storage medium, and an error correction / decoding method for performing error correction / decoding on a received signal.

Conventionally, in a receiving device, error correction and decoding are performed on a received signal. In Patent Document 1, a symbol replica generation unit that generates a symbol replica based on bit likelihood information obtained by error correction and decoding when the receiving device performs interference removal, and a propagation path estimation unit that obtains a propagation path estimation value. And a signal detection unit that reduces multipath interference, and a technique for performing error correction and decoding is disclosed. Specifically, in the receiving device described in Patent Document 1, the signal detecting unit includes an interference removing unit that removes inter-carrier interference from the propagation path estimation value and the symbol replica, and a combining unit that synthesizes the output of the interference removing unit. If there is no error in the error correction / decoding result, the reception process is terminated. When the decoding result of the receiving device described in Patent Document 1 is incorrect, the performance is improved by repeatedly generating a symbol replica based on the generated bit likelihood information and repeatedly removing the interference.

Japanese Unexamined Patent Publication No. 2010-288140

However, according to the above-mentioned conventional technique, since the replica signal is generated and the interference is removed, it is necessary to feed back the signal to perform the interference removal. Therefore, there is a problem that the delay becomes large. In addition, there is a problem that control becomes complicated.

The present disclosure has been made in view of the above, and an object of the present invention is to obtain an error correction / decoding device capable of performing error correction / decoding with simple control while suppressing delay.

In order to solve the above-mentioned problems and achieve the object, the error correction decoding apparatus of the present disclosure performs interference removal on a received signal by a plurality of interference elimination algorithms, and generates an interference elimination signal for each interference elimination algorithm. The interference elimination unit, the demodulation unit that demodulates the interference elimination signal, and the signal demodulated by the demodulation unit are subjected to error correction and decoding, and the decoding result and the value obtained in the process of error correction and decoding, which is the value obtained in the decoding result. The error correction unit that outputs the judgment reference value indicating the reliability is compared with each judgment reference value obtained when error correction and decoding is performed on the signal in which each interference elimination signal for each interference elimination algorithm is demodulated. and, characterized in that it comprises the most reliable high criterion value output control unit for outputting a final error-correction decoded result of the decoding result when obtained, the.

The error correction / decoding device according to the present disclosure has an effect that error correction / decoding can be performed with simple control while suppressing delay.

A block diagram showing a configuration example of an error correction / decoding device according to the first embodiment. A flowchart showing the operation of the error correction decoding device according to the first embodiment. The figure which shows the structural example of the processing circuit in the case where the processing circuit provided in the error correction decoding apparatus which concerns on Embodiment 1 is realized by a processor and a memory. The figure which shows the example of the processing circuit in the case where the processing circuit provided in the error correction decoding apparatus which concerns on Embodiment 1 is configured by the dedicated hardware. A block diagram showing a configuration example of the error correction decoding device according to the second embodiment. A flowchart showing the operation of the error correction decoding device according to the second embodiment. A flowchart showing the operation of the error correction decoding device according to the third embodiment. A flowchart showing the operation of the error correction decoding device according to the fourth embodiment.

Hereinafter, the error correction / decoding device, the control circuit, the storage medium, and the error correction / decoding method according to the embodiment of the present disclosure will be described in detail with reference to the drawings.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration example of the error correction / decoding device 30 according to the first embodiment. The error correction / decoding device 30 includes an interference removing unit 1, a selection unit 2, a demodulation unit 3, an error correction unit 4, a comparison unit 5, a selection unit 6, a decoding result candidate storage unit 7, and a selection unit 8. And a determination reference value candidate storage unit 9. Further, in the error correction decoding device 30, the output control unit 10 is composed of the comparison unit 5, the selection unit 6, the decoding result candidate storage unit 7, the selection unit 8, and the determination reference value candidate storage unit 9.

The interference removing unit 1 removes interference from a received signal by a plurality of different interference removing algorithms. The interference removing unit 1 includes an interference removing processing unit 20-1 to 20-k. The interference elimination processing units 20-1 to 20-k perform interference elimination with respect to the received signal by different interference elimination algorithms. In the example of FIG. 1, the interference removing unit 1 performs interference removal by k kinds of interference removing algorithms, and generates an interference removing signal for each of k kinds of interference removing algorithms.

The selection unit 2 selects one from a plurality of interference elimination signals generated by the interference elimination unit 1. The selection unit 2 outputs the selected interference elimination signal to the demodulation unit 3.

The demodulation unit 3 demodulates the interference elimination signal selected by the selection unit 2. The demodulation unit 3 outputs the demodulated signal to the error correction unit 4.

The error correction unit 4 performs error correction and decoding on the signal demodulated by the demodulation unit 3. The error correction unit 4 outputs the decoding result obtained as a result of the error correction decoding to the selection unit 6. Further, the error correction unit 4 outputs a determination reference value, which is a value obtained in the process of error correction / decoding and indicates the reliability of the decoding result, to the comparison unit 5 and the selection unit 8. The determination reference value can be represented by, for example, a value such as the number of bits inverted by comparing the received hardness determination bit and the decoding bit, the sum of the absolute values of the likelihood ratios after decoding, and the like, but the determination reference value is not limited thereto.

The comparison unit 5 compares the determination reference value output from the error correction unit 4 with the determination reference value candidate stored in the determination reference value candidate storage unit 9. The determination reference value candidate is a determination reference value obtained in the decoding process of the most likely decoding result output from the error correction decoding device 30 as an error correction decoding result. The comparison unit 5 controls the selection by the selection units 6 and 8, that is, the output from the selection units 6 and 8 based on the comparison result.

The selection unit 6 selects the decoding result output from the error correction unit 4 or the decoding result candidate stored in the decoding result candidate storage unit 7 based on the control of the comparison unit 5. The decoding result candidate is the most probable decoding result output from the error correction decoding device 30 as an error correction decoding result.

The decoding result candidate storage unit 7 stores the most probable decoding result, which is selected by the selection unit 6 and is output as an error correction decoding result from the error correction decoding device 30, as a decoding result candidate.

The selection unit 8 selects the determination reference value output from the error correction unit 4 or the determination reference value candidate stored in the determination reference value candidate storage unit 9 based on the control of the comparison unit 5.

The determination reference value candidate storage unit 9 is selected by the selection unit 8, and is a determination obtained in the decoding process of the most probable decoding result output from the error correction decoding device 30 as the error correction decoding result. The reference value is stored as a judgment reference value candidate.

The output control unit 10 outputs the decoding result when the most reliable determination reference value is obtained as the final error correction decoding result based on the determination reference value.

Next, the operation of the error correction / decoding device 30 will be described. FIG. 2 is a flowchart showing the operation of the error correction / decoding device 30 according to the first embodiment.

When the received signal is input, in the error correction decoding device 30, the interference removing processing unit 20-1 of the interference removing unit 1 performs interference removal on the received signal using the first interference removing algorithm (step S101). ), Generate an interference elimination signal. The selection unit 2 selects the interference elimination signal generated by the interference elimination processing unit 20-1 of the interference elimination unit 1 (step S102), and outputs the interference elimination signal to the demodulation unit 3. The demodulation unit 3 demodulates the interference elimination signal selected by the selection unit 2 (step S103), generates soft determination information as the demodulated signal, and outputs it to the error correction unit 4. The error correction unit 4 performs error correction / decoding on the soft determination information generated by the demodulation unit 3 (step S104), and generates an error correction / decoding decoding result and a determination reference value obtained in the decoding process. Output.

The comparison unit 5 acquires the determination reference value from the error correction unit 4, and compares the determination reference value acquired from the error correction unit 4 with the determination reference value candidate stored in the determination reference value candidate storage unit 9 (). Step S105). In the case of the first time, the comparison unit 5 determines that the determination reference value candidate acquired from the error correction unit 4 has high reliability because the determination reference value candidate is not stored in the determination reference value candidate storage unit 9 (step S105). : No). The comparison unit 5 controls the selection unit 6 to select the decoding result output from the error correction unit 4. Further, the comparison unit 5 controls the selection unit 8 to select the determination reference value output from the error correction unit 4. The selection unit 6 selects the decoding result output from the error correction unit 4 and stores it in the decoding result candidate storage unit 7 as a decoding result candidate, that is, updates it (step S106). The selection unit 8 selects the determination reference value output from the error correction unit 4 and stores it in the determination reference value candidate storage unit 9 as a determination reference value candidate, that is, updates it (step S106).

Since the error correction decoding device 30 has not completed the interference elimination in all the interference elimination algorithms (step S108: No), the error correction decoding device 30 returns to the operation of step S101.

Next, the interference elimination processing unit 20-2 of the interference elimination unit 1 performs interference elimination on the received signal using the second interference elimination algorithm (step S101), and generates an interference elimination signal. The selection unit 2 selects the interference elimination signal generated by the interference elimination processing unit 20-2 of the interference elimination unit 1 (step S102), and outputs the interference elimination signal to the demodulation unit 3. The demodulation unit 3 demodulates the interference elimination signal selected by the selection unit 2 (step S103), generates soft determination information as the demodulated signal, and outputs it to the error correction unit 4. The error correction unit 4 performs error correction / decoding on the soft determination information generated by the demodulation unit 3 (step S104), and generates an error correction / decoding decoding result and a determination reference value obtained in the decoding process. Output.

The comparison unit 5 acquires the determination reference value from the error correction unit 4, and compares the determination reference value acquired from the error correction unit 4 with the determination reference value candidate stored in the determination reference value candidate storage unit 9 (). Step S105). As a result of comparison, when the reliability of the determination reference value candidate stored in the determination reference value candidate storage unit 9 is high (step S105: Yes), the comparison unit 5 has the decoding result candidate storage unit 7 with respect to the selection unit 6. The decoding result candidate stored in is selected, and the selection unit 8 is made to select the determination reference value candidate stored in the determination reference value candidate storage unit 9. By selecting the decoding result candidate stored in the decoding result candidate storage unit 7, the selection unit 6 keeps the decoding result candidate stored in the decoding result candidate storage unit 7 as it is (step S107). .. By selecting the determination reference value candidate stored in the determination reference value candidate storage unit 9, the selection unit 8 retains the determination reference value candidate stored in the determination reference value candidate storage unit 9 as it is. (Step S107).

On the other hand, when the reliability of the determination reference value acquired from the error correction unit 4 is high as a result of comparison (step S105: No), the comparison unit 5 outputs the decoding result output from the error correction unit 4 to the selection unit 6. Is selected, and the selection unit 8 is made to select the determination reference value output from the error correction unit 4. The selection unit 6 updates the decoding result candidate stored in the decoding result candidate storage unit 7 by selecting the decoding result output from the error correction unit 4 (step S106). The selection unit 8 updates the determination reference value candidates stored in the determination reference value candidate storage unit 9 by selecting the determination reference value output from the error correction unit 4 (step S106).

Similarly, the error correction decoding device 30 changes the signal from the third interference elimination algorithm used by the interference elimination processing units 20-3 to 20-k of the interference elimination unit 1 to the signal whose interference is eliminated by the kth interference elimination algorithm. It is demodulated and error corrected, and the decoding result and the judgment reference value are generated. The error correction decoding device 30 repeatedly holds or updates the decoding result candidate stored in the decoding result candidate storage unit 7 and the determination reference value candidate stored in the determination reference value candidate storage unit 9. When the interference elimination by all the interference elimination algorithms is completed (step S108: Yes), the error correction decoding apparatus 30 finally obtains the decoding result candidate stored in the decoding result candidate storage unit 7 as an error correction decoding result. Is output as (step S109).

In the present embodiment, as the determination reference value, as described above, a value such as the number of bits inverted by comparing the received hardness determination bit and the decoding bit, the sum of the absolute values of the likelihood ratios after decoding, and the like is used. Can be done. When the number of inverted bits is used, the smaller the number of bits, the more reliable the decoding result can be. Further, when the sum of the absolute values of the likelihood ratios after decoding is used, the larger the sum of the absolute values, the more reliable the decoding result can be obtained. As for the determination reference value, in the case of a code for repeated decoding in the error correction unit 4, in addition to the above values, an external value, a change amount of the determination reference value between repeated decoding, and the like can be used.

Next, the hardware configuration of the error correction / decoding device 30 will be described. In the error correction decoding device 30, the interference removing unit 1, the selection unit 2, the demodulation unit 3, the error correction unit 4, the comparison unit 5, the selection unit 6, the decoding result candidate storage unit 7, the selection unit 8, and the determination reference value candidate storage. Part 9 is realized by a processing circuit. The processing circuit may be a processor and memory for executing a program stored in the memory, or may be dedicated hardware. The processing circuit is also called a control circuit.

FIG. 3 is a diagram showing a configuration example of the processing circuit 90 when the processing circuit included in the error correction / decoding device 30 according to the first embodiment is realized by the processor 91 and the memory 92. The processing circuit 90 shown in FIG. 3 is a control circuit and includes a processor 91 and a memory 92. When the processing circuit 90 is composed of the processor 91 and the memory 92, each function of the processing circuit 90 is realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 92. In the processing circuit 90, each function is realized by the processor 91 reading and executing the program stored in the memory 92. That is, the processing circuit 90 includes a memory 92 for storing a program in which the processing of the error correction decoding device 30 is eventually executed. It can be said that this program is a program for causing the error correction / decoding device 30 to execute each function realized by the processing circuit 90. This program may be provided by a storage medium in which the program is stored, or may be provided by other means such as a communication medium.

In the above program, the interference elimination unit 1 performs interference removal on the received signal by a plurality of interference elimination algorithms, and the first step of generating an interference elimination signal for each interference elimination algorithm, and the demodulation unit 3 perform interference elimination. In the second step of demodulating the signal, the error correction unit 4 performs error correction and decoding on the signal demodulated by the demodulation unit 3, and outputs the decoding result and the determination reference value indicating the reliability of the decoding result. The third step and the fourth step in which the output control unit 10 outputs the decoding result when the most reliable determination reference value is obtained based on the determination reference value as the final error correction decoding result. It can be said that this is a program for causing the error correction / decoding device 30 to execute.

Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic unit, a microprocessor, a microcomputer, a DSP (Digital Signal Processor), or the like. Further, the memory 92 may be non-volatile or volatile, for example, RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EEPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), or the like. This includes semiconductor memory, magnetic disk, flexible disk, optical disk, compact disk, mini disk, DVD (Digital Versatile Disc), and the like.

FIG. 4 is a diagram showing an example of a processing circuit 93 in the case where the processing circuit included in the error correction / decoding device 30 according to the first embodiment is configured by dedicated hardware. The processing circuit 93 shown in FIG. 4 is, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The thing is applicable. As for the processing circuit, a part may be realized by dedicated hardware and a part may be realized by software or firmware. As described above, the processing circuit can realize each of the above-mentioned functions by the dedicated hardware, software, firmware, or a combination thereof.

As described above, according to the present embodiment, the error correction / decoding device 30 demodulates the signal obtained by separately deinterfering the received signal with respect to a plurality of interference elimination algorithms prepared in advance, and demodulates the signal. Error correction and decoding are performed for each of the received signals. Since the error correction decoding device 30 can obtain a plurality of decoding results, the error correction decoding device 30 selects and outputs the final error correction decoding result from the plurality of decoding results based on the determination reference value indicating the reliability of the decoding result. did. As a result, the error correction / decoding device 30 can perform processing without feeding back to the flow of information, so that error correction / decoding can be performed with simple control while suppressing delay.

Embodiment 2.
In the second embodiment, a case where the error correction / decoding device performs error detection by CRC (Cyclic Redundancy Check) will be described.

FIG. 5 is a block diagram showing a configuration example of the error correction decoding device 31 according to the second embodiment. The error correction / decoding device 31 includes an interference removing unit 1, a selection unit 2, a demodulation unit 3, an error correction unit 4, a comparison unit 5, an error detection unit 13, a selection unit 14, and a decoding result candidate storage unit. 7, a selection unit 15, and a determination reference value candidate storage unit 9. Further, in the error correction decoding device 31, the output control unit 16 is configured by the comparison unit 5, the error detection unit 13, the selection unit 14, the decoding result candidate storage unit 7, the selection unit 15, and the determination reference value candidate storage unit 9. ing. In the error correction / decoding device 31, the same reference numerals are given to the same configurations as those provided in the error correction / decoding device 30 of the first embodiment, and the description thereof will be omitted.

The error detection unit 13 performs error detection by CRC. The error detection unit 13 outputs the detection result of error detection by CRC to the selection unit 14 and the selection unit 15.

The selection unit 14 selects the decoding result output from the error correction unit 4 or the decoding result candidate stored in the decoding result candidate storage unit 7 based on the detection result of the error detection unit 13 and the control of the comparison unit 5. select. Specifically, when an error is not detected by the error detection unit 13, the selection unit 14 outputs a decoding result output from the error correction unit 4 under the control of the comparison unit 5, as in the first embodiment. Alternatively, the decoding result candidate stored in the decoding result candidate storage unit 7 is selected. When an error is detected by the error detection unit 13, the selection unit 14 selects the decoding result candidate stored in the decoding result candidate storage unit 7 regardless of the control of the comparison unit 5.

The selection unit 15 is based on the detection result of the error detection unit 13 and the control of the comparison unit 5, the determination reference value output from the error correction unit 4, or the determination standard stored in the determination reference value candidate storage unit 9. Select a value candidate. Specifically, when the error detection unit 13 does not detect an error, the selection unit 15 has a determination reference value output from the error correction unit 4 based on the control of the comparison unit 5, as in the first embodiment. , Or the determination reference value candidate stored in the determination reference value candidate storage unit 9 is selected. When an error is detected by the error detection unit 13, the selection unit 15 selects the determination reference value candidate stored in the determination reference value candidate storage unit 9 regardless of the control of the comparison unit 5.

The output control unit 16 performs error detection on the decoding result, and excludes the decoding result in which the error is detected from the candidates for the final error correction decoding result.

Next, the operation of the error correction decoding device 31 will be described. FIG. 6 is a flowchart showing the operation of the error correction decoding device 31 according to the second embodiment. In the flowchart of FIG. 6, the operation of the error correction / decoding device 31 from step S101 to step S104 is the same as the operation of the error correction / decoding device 30 in the flowchart of FIG. In the error correction decoding device 31, when the error is not detected (step S201: No), the error detection unit 13 outputs to the selection unit 14 and the selection unit 15 that the error is not detected. In this case, the subsequent operation of the selection unit 14 is the same as the operation of the selection unit 6 included in the error correction decoding device 30 of the first embodiment. Further, the subsequent operation of the selection unit 15 is the same as the operation of the selection unit 8 provided in the error correction decoding device 30 of the first embodiment.

In the error correction decoding device 31, when an error is detected (step S201: Yes), the error detection unit 13 outputs to the selection unit 14 and the selection unit 15 that the error has been detected. In this case, as described above, the selection unit 14 stores the decoding result candidate stored in the decoding result candidate storage unit 7 by selecting the decoding result candidate stored in the decoding result candidate storage unit 7, regardless of the control of the comparison unit 5. The decryption result candidate that has been performed is retained as it is (step S107). Similarly, as described above, the selection unit 15 selects the determination reference value candidate stored in the determination reference value candidate storage unit 9 regardless of the control of the comparison unit 5, thereby selecting the determination reference value candidate storage unit. The determination reference value candidate stored in 9 is retained as it is (step S107). In the flowchart of FIG. 6, the operation of the error correction / decoding device 31 in steps S108 and S109 is the same as the operation of the error correction / decoding device 30 in the flowchart of FIG.

In the second embodiment, the decoding result candidate storage unit 7 has the highest possibility of being output as an error correction decoding result from the error correction decoding apparatus 31 among the codes in which the error detection unit 13 has not detected an error. The result is stored as a decoding result candidate. Similarly, the determination reference value candidate storage unit 9 is the most probable decoding result output from the error correction decoding device 31 as the error correction decoding result among the codes in which the error is not detected by the error detection unit 13. The judgment reference value obtained in the decoding process is stored as a judgment reference value candidate.

The hardware configuration of the error correction decoding device 31 will be described. In the error correction decoding device 31, the interference removal unit 1, the selection unit 2, the demodulation unit 3, the error correction unit 4, the comparison unit 5, the error detection unit 13, the selection unit 14, the decoding result candidate storage unit 7, the selection unit 15, and The determination reference value candidate storage unit 9 is realized by a processing circuit. Similar to the error correction / decoding device 30 of the first embodiment, the processing circuit may be a processor and a memory for executing a program stored in the memory, or may be dedicated hardware.

As described above, according to the present embodiment, the error correction and decoding device 31 selects the most reliable decoding result among the codes in which the error is not detected by the error detection unit 13. As a result, the error correction / decoding device 31 can output a highly reliable error correction / decoding result as the final error correction / decoding result as compared with the error correction / decoding device 30 of the first embodiment.

Embodiment 3.
In the third embodiment, different usage methods of the detection results of the error detection unit 13 will be described in the same configuration as the error correction / decoding device 31 of the second embodiment.

FIG. 7 is a flowchart showing the operation of the error correction decoding device 31 according to the third embodiment. The difference from the flowchart of the second embodiment shown in FIG. 6 is the part of step S301. In the third embodiment, when the error detection / decoding device 31 does not detect an error in the error detection unit 13 (step S301: No), the error correction / decoding device 31 outputs the decoding result output from the error correction unit 4 as the final decoding result, that is, It is output as an error correction decoding result (step S109). In this case, the error correction decoding device 31 ends the process even if the interference elimination algorithm for which the interference elimination is not performed remains in the interference elimination unit 1.

On the other hand, when the error is detected by the error detection unit 13 (step S301: Yes), the error correction / decoding device 31 performs the same operation as that of the first embodiment. When an error is finally detected for all the interference removal algorithms, the error correction decoding device 31 finally outputs the decoding result candidate stored in the decoding result candidate storage unit 7 as an error correction decoding result. (Step S109).

In the third embodiment, the decoding result candidate storage unit 7 has the highest possibility of being output as an error correction decoding result from the error correction decoding apparatus 31 among the codes in which the error is detected by the error detection unit 13. Will be stored as a decoding result candidate. Similarly, the determination reference value candidate storage unit 9 decodes the most likely decoding result output as the error correction decoding result from the error correction decoding apparatus 31 among the codes in which the error is detected by the error detection unit 13. The judgment reference value obtained in the process is stored as a judgment reference value candidate.

As described above, in the third embodiment, the output control unit 16 performs error detection on the decoding result, and when the error is detected in all the decoding results based on the plurality of interference elimination algorithms, the error is detected. Among the decoding results, the decoding result when the most reliable determination reference value is obtained is output as the final error correction decoding result.

As described above, according to the present embodiment, if the error detection / decoding device 31 does not detect an error in the error detection unit 13, the error correction / decoding can be terminated at that point, so that the processing amount The average of can be reduced, the number of processing steps can be reduced, and the power consumption can be reduced.

Further, when an error is detected for all the interference removal algorithms in the error correction / decoding device 31, the error remains in the error correction / decoding result output from the error correction / decoding device 31. However, in the latter stage of the output control unit 16 (not shown), for example, when handling audio information, video information, etc., error correction with high reliability is performed by using the decoding result in which errors before and after are not detected. The decoding device 31 can be obtained.

Embodiment 4.
In the fourth embodiment, in the error correction decoding device 30 of the first embodiment or the error correction decoding device 31 of the second embodiment, the error correction unit 4 repeatedly decodes LDPC (Low Density Parity Check), turbo code, and the like. The operation when the code for performing the above is used will be described. Hereinafter, the error correction / decoding device 30 of the first embodiment will be specifically described as an example, but the present invention can also be applied to the error correction / decoding device 31 of the second embodiment.

FIG. 8 is a flowchart showing the operation of the error correction / decoding device 30 according to the fourth embodiment. The flowchart of FIG. 8 replaces the operation of step S104 with steps S401 and S402 with respect to the flowchart of FIG. 2 of the first embodiment. In the error correction / decoding device 30, when performing error correction / decoding, the error correction unit 4 has a determination reference value at a number of repetitions less than a predetermined number of repetitions for the completion of decoding, that is, a determination reference value during error correction / decoding. Ask for. The error correction unit 4 compares the obtained determination reference value during error correction and decoding with the threshold value defined for determining the reliability of the determination reference value (step S401).

When the determination reference value during error correction and decoding is equal to or greater than the threshold value (step S401: Yes), the error correction unit 4 continues error correction and decoding by the corresponding interference elimination algorithm (step S402). In this case, the error correction / decoding device 30 is in a state where the operation of step S104 is performed in the flowchart of FIG. 2 of the first embodiment. Subsequent operations of the error correction decoding device 30 are the same as those in the first embodiment.

If the determination reference value during error correction / decoding is less than the threshold value (step S401: No), the error correction unit 4 cancels the error correction / decoding by the corresponding interference elimination algorithm (step S403). In this case, the error correction / decoding device 30 omits the operation of steps S105 to S107 in the flowchart of FIG. 2 of the first embodiment, and performs error correction / decoding of the signal whose interference has been removed by the following interference removal algorithm. Subsequent operations of the error correction decoding device 30 are the same as those in the first embodiment.

As described above, in the fourth embodiment, when the error correction unit 4 uses the code for performing repeated decoding, the error correction unit 4 compares the determination reference value and the threshold value in the number of repetitions in the middle before the error correction decoding is completed, and determines the threshold value. If the value is larger, the interference is removed by the corresponding interference elimination algorithm, and error correction / decoding for the demodulated signal is stopped. The error correction unit 4 performs error correction and decoding on the signal that has been deinterfered by another interference elimination algorithm and demodulated.

As described above, according to the present embodiment, the error correction decoding apparatus 30 completes the processing in a small number of steps for the one decoded by the interference elimination algorithm, which is unlikely to obtain a correct decoding result. .. As a result, the error correction / decoding device 30 can reduce the total number of processing steps.

The configuration shown in the above embodiments is an example, and can be combined with another known technique, can be combined with each other, and does not deviate from the gist. It is also possible to omit or change a part of the configuration.

1 Interference removal unit, 2, 6, 8, 14, 15 selection unit, 3 Demodulation unit, 4 Error correction unit, 5 Comparison unit, 7 Decoding result candidate storage unit, 9 Judgment reference value candidate storage unit, 10, 16 Output control Unit, 13 Error detection unit, 20-1 to 20-k interference elimination processing unit, 30, 31 Error correction / decoding device.

Claims (7)

An interference elimination unit that eliminates interference from a received signal by a plurality of interference elimination algorithms and generates an interference elimination signal for each interference elimination algorithm.
A demodulation unit that demodulates the interference elimination signal,
Error correction / decoding is performed on the signal demodulated by the demodulation unit, and an error correction that outputs a decoding result and a judgment reference value that is a value obtained in the process of the error correction / decoding and indicates the reliability of the decoding result. Department and
The most reliable determination reference value was obtained by comparing each determination reference value obtained when error correction and decoding was performed on the signal in which each interference elimination signal was demodulated for each interference elimination algorithm. An output control unit that outputs the above-mentioned decoding result as the final error correction decoding result,
An error correction / decoding device characterized by comprising. The output control unit performs error detection on the decoding result, and excludes the decoding result in which the error is detected from the candidates for the final error correction decoding result.
The error correction decoding device according to claim 1. The output control unit detects an error in the decoding result, and when an error is detected in all the decoding results based on the plurality of interference elimination algorithms, the most error-detected decoding result. The decoding result when the highly reliable determination reference value is obtained is output as the final error correction decoding result.
The error correction decoding device according to claim 1. When the code for performing the error correction decoding is used, the error correction unit compares the determination reference value and the threshold value in the number of repetitions in the middle before the error correction decoding is completed, and when the threshold value is larger, it corresponds. The error correction and decoding of the signal that has been de-interfered and demodulated by the interference elimination algorithm is stopped, and the error correction and decoding of the signal that has been de-interfered and demodulated by the other interference-removal algorithm is performed.
The error correction decoding device according to any one of claims 1 to 3, wherein the error correction / decoding device is characterized. A control circuit for controlling an error correction / decoding device.
Interference removal is performed on the received signal by a plurality of interference elimination algorithms, and an interference elimination signal is generated for each of the interference elimination algorithms.
Demodulate the interference elimination signal,
Error correction decoding is performed on the demodulated signal, and the decoding result and the judgment reference value obtained in the process of the error correction decoding and indicating the reliability of the decoding result are output.
The most reliable determination reference value was obtained by comparing each determination reference value obtained when error correction and decoding was performed on the signal in which each interference elimination signal was demodulated for each interference elimination algorithm. Output the above-mentioned decoding result at the time as the final error correction decoding result,
A control circuit comprising the above-mentioned error correction decoding apparatus. A storage medium in which a program for controlling an error correction decoding device is stored.
The program
Interference removal is performed on the received signal by a plurality of interference elimination algorithms, and an interference elimination signal is generated for each of the interference elimination algorithms.
Demodulate the interference elimination signal,
Error correction decoding is performed on the demodulated signal, and the decoding result and the judgment reference value obtained in the process of the error correction decoding and indicating the reliability of the decoding result are output.
The most reliable determination reference value was obtained by comparing each determination reference value obtained when error correction and decoding was performed on the signal in which each interference elimination signal was demodulated for each interference elimination algorithm. Output the above-mentioned decoding result at the time as the final error correction decoding result,
A storage medium, characterized in that the error correction and decoding apparatus is used. This is an error correction / decoding method in an error correction / decoding device.
The first step in which the interference removing unit performs interference removal on the received signal by a plurality of interference removing algorithms and generates an interference removing signal for each of the interference removing algorithms.
The second step in which the demodulation unit demodulates the interference elimination signal,
The error correction unit performs error correction / decoding on the signal demodulated by the demodulation unit, and the decoding result and the judgment reference value which is a value obtained in the process of the error correction / decoding and indicates the reliability of the decoding result. And the third step to output
The output control unit compares each judgment reference value obtained when error correction and decoding is performed on the signal in which each interference removal signal is demodulated for each interference removal algorithm, and the most reliable judgment standard. The fourth step of outputting the decoding result when the value is obtained as the final error correction decoding result, and
An error correction / decoding method characterized by including.

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