JP6986569B2 - ニューラル・ネットワークの更新管理のためのコンピュータ実装方法、コンピュータ・プログラム、およびコンピュータ処理システム - Google Patents

ニューラル・ネットワークの更新管理のためのコンピュータ実装方法、コンピュータ・プログラム、およびコンピュータ処理システム Download PDF

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JP6986569B2
JP6986569B2 JP2019554891A JP2019554891A JP6986569B2 JP 6986569 B2 JP6986569 B2 JP 6986569B2 JP 2019554891 A JP2019554891 A JP 2019554891A JP 2019554891 A JP2019554891 A JP 2019554891A JP 6986569 B2 JP6986569 B2 JP 6986569B2
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JP2020517002A (ja
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ゴクメン、タイフン
ムラト オネン、オグツァン
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    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
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    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
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    • G06F2207/4802—Special implementations
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    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4824—Neural networks
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    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
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    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4828—Negative resistance devices, e.g. tunnel diodes, gunn effect devices

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JP2019554891A 2017-04-14 2018-03-13 ニューラル・ネットワークの更新管理のためのコンピュータ実装方法、コンピュータ・プログラム、およびコンピュータ処理システム Active JP6986569B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/487,701 2017-04-14
US15/487,701 US10783432B2 (en) 2017-04-14 2017-04-14 Update management for RPU array
PCT/IB2018/051644 WO2018189600A1 (en) 2017-04-14 2018-03-13 Update management for rpu array

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JP2020517002A JP2020517002A (ja) 2020-06-11
JP2020517002A5 JP2020517002A5 (enExample) 2020-07-27
JP6986569B2 true JP6986569B2 (ja) 2021-12-22

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US (2) US10783432B2 (enExample)
JP (1) JP6986569B2 (enExample)
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Families Citing this family (11)

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US10303998B2 (en) * 2017-09-28 2019-05-28 International Business Machines Corporation Floating gate for neural network inference
US11651231B2 (en) 2019-03-01 2023-05-16 Government Of The United States Of America, As Represented By The Secretary Of Commerce Quasi-systolic processor and quasi-systolic array
US11562249B2 (en) * 2019-05-01 2023-01-24 International Business Machines Corporation DNN training with asymmetric RPU devices
CN110750231B (zh) * 2019-09-27 2021-09-28 东南大学 一种面向卷积神经网络的双相系数可调模拟乘法计算电路
US11501148B2 (en) * 2020-03-04 2022-11-15 International Business Machines Corporation Area and power efficient implementations of modified backpropagation algorithm for asymmetric RPU devices
US11501023B2 (en) 2020-04-30 2022-11-15 International Business Machines Corporation Secure chip identification using resistive processing unit as a physically unclonable function
US11366876B2 (en) 2020-06-24 2022-06-21 International Business Machines Corporation Eigenvalue decomposition with stochastic optimization
US11568217B2 (en) * 2020-07-15 2023-01-31 International Business Machines Corporation Sparse modifiable bit length deterministic pulse generation for updating analog crossbar arrays
US11443171B2 (en) * 2020-07-15 2022-09-13 International Business Machines Corporation Pulse generation for updating crossbar arrays
US12488250B2 (en) * 2020-11-02 2025-12-02 International Business Machines Corporation Weight repetition on RPU crossbar arrays
US12165046B2 (en) * 2021-03-16 2024-12-10 International Business Machines Corporation Enabling hierarchical data loading in a resistive processing unit (RPU) array for reduced communication cost

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US5258934A (en) 1990-05-14 1993-11-02 California Institute Of Technology Charge domain bit serial vector-matrix multiplier and method thereof
JPH04153827A (ja) * 1990-10-18 1992-05-27 Fujitsu Ltd ディジタル乗算器
US20040083193A1 (en) 2002-10-29 2004-04-29 Bingxue Shi Expandable on-chip back propagation learning neural network with 4-neuron 16-synapse
EP1508872A1 (en) * 2003-08-22 2005-02-23 Semeion An algorithm for recognising relationships between data of a database and a method for image pattern recognition based on the said algorithm
US9715655B2 (en) 2013-12-18 2017-07-25 The United States Of America As Represented By The Secretary Of The Air Force Method and apparatus for performing close-loop programming of resistive memory devices in crossbar array based hardware circuits and systems
US9466362B2 (en) 2014-08-12 2016-10-11 Arizona Board Of Regents On Behalf Of Arizona State University Resistive cross-point architecture for robust data representation with arbitrary precision
US20170061279A1 (en) * 2015-01-14 2017-03-02 Intel Corporation Updating an artificial neural network using flexible fixed point representation
US10748064B2 (en) 2015-08-27 2020-08-18 International Business Machines Corporation Deep neural network training with native devices
US10387778B2 (en) 2015-09-29 2019-08-20 International Business Machines Corporation Scalable architecture for implementing maximization algorithms with resistive devices
US10325006B2 (en) 2015-09-29 2019-06-18 International Business Machines Corporation Scalable architecture for analog matrix operations with resistive devices
CN105488565A (zh) * 2015-11-17 2016-04-13 中国科学院计算技术研究所 加速深度神经网络算法的加速芯片的运算装置及方法

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US20180300622A1 (en) 2018-10-18
WO2018189600A1 (en) 2018-10-18
US11062208B2 (en) 2021-07-13
US10783432B2 (en) 2020-09-22
CN110506282A (zh) 2019-11-26
US20180300627A1 (en) 2018-10-18
CN110506282B (zh) 2023-04-28
DE112018000723T5 (de) 2019-10-24
GB201916146D0 (en) 2019-12-18
JP2020517002A (ja) 2020-06-11
GB2576275A (en) 2020-02-12

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