JP6983624B2 - Manufacturing methods for semiconductor devices, power supplies, high-frequency amplifiers, and semiconductor devices - Google Patents

Description

The present invention relates to a semiconductor device, a power supply device, a high frequency amplifier, and a method for manufacturing the semiconductor device.

There are various types of semiconductor devices that use compound semiconductors such as GaN. Among them, HEMT (High Electron Mobility Transistor) has a feature that noise is small and high-speed operation is possible.

In the HEMT, two-dimensional electron gas can be induced in the electron traveling layer below it by spontaneous polarization or piezo polarization generated in the electron supply layer.

In particular, when a compound semiconductor layer containing indium such as an InAlN layer or an InAlGaN layer is used as the electron supply layer, the spontaneous polarization of the electron supply layer is enhanced and a high-concentration two-dimensional electron gas is applied to the electron traveling layer below it. Can be induced.

Japanese Unexamined Patent Publication No. 2017-085062

However, in the HEMT using the electron supply layer containing indium in this way, there is room for improvement in terms of achieving both reduction of leakage current and high output.

According to one aspect, it is an object of the present invention to increase the output of a semiconductor device while reducing the leakage current of the semiconductor device.

According to one aspect, the substrate, the electron traveling layer formed above the substrate, the electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium, and the electron supply layer. A source electrode formed on the electron supply layer, a drain electrode formed on the electron supply layer at a distance from the source electrode, and the source electrode and the drain electrode on the electron supply layer. A first insulating layer formed in a partial region between the two, and an electron supply layer between the first insulating layer and the source electrode are formed on the first insulating layer. It is formed on the electron supply layer between the extended gate electrode and the first insulating layer and the drain electrode , covers the side surface and the upper surface of the gate electrode, and has a band more than the first insulating layer. possess the gap is wide second insulating layer, said first insulating layer, a silicon nitride layer, a silicon oxide layer, silicon oxynitride layer, is provided a hafnium oxide layer or a silicon oxide carbide layer der Ru semiconductor device To.

According to one aspect, since the region forming the first insulating layer is a part of the region between the gate electrode and the drain electrode, the conductive indium of the electron supply layer is diffused into the first insulating layer. Also, it is possible to prevent a leak path from being generated in the first insulating layer between the gate electrode and the drain electrode.

Moreover, the withstand voltage of the semiconductor device is increased by the second insulating layer having a wider bandgap and a higher withstand voltage than the first insulating layer.

Further, by forming the second insulating layer except for a part of the region between the drain electrode and the gate electrode exposed to the strong electric field, the electrons moving along the strong electric field are captured by the second insulating layer. It can be suppressed. As a result, it is possible to suppress the current collapse caused by the capture of electrons in the second insulating layer, and it is possible to realize high output of the semiconductor device.

FIG. 1 is a cross-sectional view of the semiconductor device used in the investigation. FIG. 2 is an enlarged cross-sectional view of the semiconductor device used in the investigation. FIG. 3 is a diagram drawn based on the TEM image of the semiconductor device used in the survey. FIG. 4 is a graph showing the relationship between the gate-drain current Ig and the gate voltage Vg of the semiconductor device in which the leak current is generated. FIG. 5 is an enlarged cross-sectional view of a semiconductor device devised by the inventor of the present application in order to prevent leakage current from being generated. FIG. 6 is a graph showing the relationship between the drain voltage Vd and the drain current Id of the semiconductor device when electrons are trapped in the alumina layer. 7 (a) and 7 (b) are cross-sectional views (No. 1) of the semiconductor device according to the first embodiment during manufacturing. 8 (a) and 8 (b) are cross-sectional views (No. 2) of the semiconductor device according to the first embodiment during manufacturing. 9 (a) and 9 (b) are cross-sectional views (No. 3) of the semiconductor device according to the first embodiment during manufacturing. FIG. 10 is a cross-sectional view (No. 4) of the semiconductor device according to the first embodiment during manufacturing. FIG. 11 is an enlarged cross-sectional view of the semiconductor device according to the first embodiment. FIG. 12 is a graph showing the relationship between the gate-drain current Ig and the gate voltage Vg of the semiconductor device according to the first embodiment. FIG. 13 is a graph showing the relationship between the drain voltage Vd and the drain current Id of the semiconductor device according to the first embodiment. 14 (a) and 14 (b) are cross-sectional views (No. 1) of the semiconductor device according to the second embodiment during manufacturing. 15 (a) and 15 (b) are cross-sectional views (No. 2) of the semiconductor device according to the second embodiment during manufacturing. 16 (a) and 16 (b) are cross-sectional views (No. 3) of the semiconductor device according to the second embodiment during manufacturing. FIG. 17 is a plan view of the discrete package according to the third embodiment. FIG. 18 is a circuit diagram of the PFC circuit according to the fourth embodiment. FIG. 19 is a circuit diagram of the power supply device according to the fifth embodiment. FIG. 20 is a circuit diagram of the high frequency amplifier according to the sixth embodiment.

Prior to the description of the present embodiment, the matters investigated by the inventor of the present application will be described.

FIG. 1 is a cross-sectional view of the semiconductor device used in the investigation.

This semiconductor device 1 is a HEMT and has a substrate 2 such as a SiC substrate and a buffer layer 3 formed on the substrate 2.

The buffer layer 3 is an AlGaN layer or an AlN layer that prevents the lattice defects of the substrate 2 from being transmitted to the layer above the buffer layer 3, and the electron traveling layer 4 is formed on the AlGaN layer or the AlN layer. In this example, an i-type GaN layer containing no impurities is formed as the electron traveling layer 4, and electron impurity scattering is suppressed in the electron traveling layer 4.

Then, an InAlGaN layer is formed as the electron supply layer 5 on the electron traveling layer 4. Two-dimensional electron gas 10 is induced in the electron traveling layer 4 by the spontaneous polarization of the electron supply layer 5, but the InAlGaN layer formed as the electron supply layer 5 has a large spontaneous polarization due to the indium in the film, so that the concentration is high. Two-dimensional electron gas 10 can be induced.

Further, a source electrode 6 and a drain electrode 7 are formed on the electron supply layer 5 at intervals.

Then, on the electron supply layer 5 between the source electrode 6 and the drain electrode 7, a silicon nitride (SiN) layer 8 having excellent moisture resistance is formed in order to protect the electron supply layer 5 from moisture in the atmosphere and the like. It is formed.

An opening 8a is formed in the silicon nitride layer 8, and a gate electrode 9 is formed in and around the opening 8a on the silicon nitride layer 8. The gate electrode 9 is formed in a T shape in a cross-sectional view, and the gate electrode 9 at a portion formed on the silicon nitride layer 8 is a field plate 9a.

The field plate 9a is provided with a facing surface 9b facing the electron supply layer 5. The strong electric field E applied from the drain electrode 7 to the gate electrode 9 is dispersed on the facing surface 9b thereof, so that the electron supply layer 5 and the silicon nitride layer 8 can be prevented from being destroyed by the electric field E, and the height of the semiconductor device 1 can be increased. Withstand voltage can be realized.

According to such a semiconductor device 1, a high-concentration two-dimensional electron gas 10 can be induced by forming an InAlGaN layer containing indium as the electron supply layer 5 as described above, and high output of the semiconductor device 1 is expected. can.

However, according to the investigation by the inventor of the present application, it has become clear that the following problems occur due to the indium of the electron supply layer 5.

FIG. 2 is an enlarged cross-sectional view of the semiconductor device 1.

In FIG. 2, the same elements as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted below.

The inventor of the present application obtained a TEM (Transmission Electron Microscopy) image of the region shown by the dotted line A in FIG. 2 in order to investigate the influence of indium in the electron supply layer 5.

FIG. 3 is a diagram drawn based on the TEM image.

As shown in FIG. 3, indium is diffused from the underlying electron supply layer 5 into the silicon nitride layer 8. Since indium has a low melting point of about 156 ° C., it is considered that indium was heated and melted when the silicon nitride layer 8 was formed on the electron supply layer 5, and indium was diffused in the silicon nitride layer 8 in this way. ..

As a result, as shown in FIG. 2, a leak current path P is formed in the silicon nitride layer 8 by the conductive indium, and a leak current is generated between the drain electrode 7 and the gate electrode 9 along the path P. Resulting in.

FIG. 4 is a graph showing the relationship between the gate-drain current Ig and the gate voltage Vg of the semiconductor device 1 in which the leak current is generated.

In FIG. 4, an ideal case in which a leak current along the path P does not exist is also shown as a comparative example.

As shown in FIG. 4, when a leak current is generated as described above, the gate-drain current Ig increases when a negative voltage is applied to the gate voltage Vg as compared with the case of the comparative example.

FIG. 5 is an enlarged cross-sectional view of the semiconductor device 1 devised by the inventor of the present application in order to prevent such a leak current from being generated.

In FIG. 5, the same elements as described in FIG. 1 are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted below.

As shown in FIG. 5, in this semiconductor device 1, an alumina (Al ₂ O ₃ ) layer 11 is provided between the electron supply layer 5 and the silicon nitride layer 8.

The alumina layer 11 functions as a diffusion prevention layer that prevents indium contained in the electron supply layer 5 from diffusing into the silicon nitride layer 8. This makes it difficult for indium to diffuse from the electron supply layer 5 to the silicon nitride layer 8, so that it is possible to prevent a leak path due to indium from forming in the silicon nitride layer 8, and the current flows between the drain electrode 7 and the gate electrode 9. Leakage current can be suppressed.

However, according to the investigation by the inventor of the present application, it has been clarified that the alumina layer 11 has an electron trap that traps electrons, and the electron e is captured in the alumina layer 11 as shown in the dotted rectangle. ..

FIG. 6 is a graph showing the relationship between the drain voltage Vd and the drain current Id of the semiconductor device 1 when the electron e is trapped in the alumina layer 11 in this way.

In FIG. 6, an ideal case in which the electron e is not trapped in the alumina layer 11 is also shown as a comparative example.

As shown in FIG. 6, when the electron e is trapped in the alumina layer 11 as described above, the drain current Id that flows when the drain voltage Vd is increased becomes smaller than that in the comparative example. Such a phenomenon is called a current collapse phenomenon.

When the current collapse phenomenon occurs, the drain current Id output from the semiconductor device 1 decreases, so that the output of the semiconductor device 1 cannot be increased.

Therefore, in this semiconductor device 1, although the leak current flowing between the drain electrode 7 and the gate electrode 9 can be reduced, there is a problem that high output of the semiconductor device 1 cannot be realized.

Hereinafter, each embodiment will be described.

(First Embodiment)
The semiconductor device according to this embodiment will be described while following the manufacturing method thereof.

7 to 10 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.

This semiconductor device is HEMT and is manufactured as follows.

First, as shown in FIG. 7A, a SiC substrate is prepared as the substrate 21, and an AlGaN layer as a buffer layer 22 is formed on the SiC substrate by the MOVPE (Metal Organic Vapor Phase Epitaxy) method with a thickness of about 0.001 μm to 0.5 μm. Form to thickness. The AlN layer may be formed as the buffer layer 22 instead of the AlGaN layer.

Further, instead of the SiC substrate, any one of a silicon substrate, an AlN substrate, a sapphire substrate, and a GaN substrate may be used as the substrate 21.

The film forming conditions of the buffer layer 22 are also not particularly limited. In this embodiment, TMA (Trimethylaluminum) gas is used as the raw material gas for aluminum, and TMG (Trimethylgalium) gas is used as the raw material gas for gallium.

Next, the same chamber in which the buffer layer 22 was formed is continued to be used, and a GaN layer is formed on the buffer layer 22 as the electron traveling layer 23 by the MOVPE method.

In this example, the electron traveling layer 23 is formed to have a thickness of about 100 nm to 3000 nm by using a mixed gas of TMG gas and ammonia gas as a film forming gas.

Further, the above chamber is continued to be used, and an InAlGaN layer is formed on the electron traveling layer 23 as an electron supply layer 24 by the MOVPE method in the chamber to a thickness of about 1 nm to 30 nm, for example, about 5 nm. Examples of the film-forming gas of the electron supply layer 24 include a mixed gas such as TMA gas, TMG gas, and TMI (Trimethylindium) gas.

The electron supply layer 24 is not limited to the InAlGaN layer as long as it is a compound semiconductor layer containing indium having a large spontaneous polarization. Examples of such a compound semiconductor layer include an InAlN layer.

Next, as shown in FIG. 7B, a tantalum layer and an aluminum layer are formed in this order on the electron supply layer 24 by a vapor deposition method, and then these laminated films are patterned by a lift-off method to obtain a source electrode. The 25 and the drain electrode 26 are formed at intervals.

The film thickness of each of the tantalum layer and the aluminum layer is not particularly limited, but the tantalum layer is formed to have a thickness of 0.01 μm to 100 μm, for example, about 7 μm. Further, the aluminum layer is formed to have a thickness of, for example, about 0.01 μm to 100 μm.

After that, the source electrode 25 and the drain electrode 26 are heated under the condition that the substrate temperature is 400 ° C. to 900 ° C., for example, about 580 ° C. in a nitrogen atmosphere.

Since the tantalum layer formed on the lowermost layer of the source electrode 25 has a property of taking in nitrogen, the nitrogen contained in the electron supply layer 24 is diffused to the source electrode 25 by heating in this way. As a result, the band between the electron supply layer 24 and the source electrode 25 becomes smooth, and the source electrode 25 can be brought into ohmic contact with the electron supply layer 24. Similarly, the drain electrode 26 also makes ohmic contact with the electron supply layer 24.

Next, as shown in FIG. 8A, the alumina layer 27 is placed on each of the electron supply layer 24, the source electrode 25, and the drain electrode 26 by the ALD (Atomic Layer Deposition) method at 1 nm to 50 nm, for example, about 20 nm. Form to the thickness of. The alumina layer 27 is an example of the second insulating layer.

Further, instead of the alumina layer 27, an aluminum nitride (AlON) layer or an aluminum nitride (AlN) layer may be formed.

Subsequently, as shown in FIG. 8B, the alumina layer 27 is patterned by photolithography and wet etching. As a result, the alumina layer 27 is left in the region R1 near the drain electrode 26 in the region between the source electrode 25 and the drain electrode 26.

The etching solution used in this wet etching includes, for example, hydrofluoric acid.

Further, the alumina layer 27 may be patterned by ion milling instead of wet etching.

Next, as shown in FIG. 9A, a silicon nitride layer 31 is formed on the entire upper surface of the substrate 21 by a plasma CVD (Chemical Vapor Deposition) method under the condition that the substrate temperature is 300 ° C. to 400 ° C., and the silicon nitride thereof is formed. The layer 31 protects the electron supply layer 24.

As the film-forming gas of the silicon nitride layer 31, for example, there is a mixed gas of _{silane (SiH 4) gas and ammonia gas.} Further, the silicon nitride layer 31 is an example of the first insulating layer, and is formed to have a thickness of about 1 nm to 1000 nm, for example, about 600 nm.

Since the indium in the electron supply layer 24 is melted and diffused into the silicon nitride layer 31 by the heat generated when the silicon nitride layer 31 is formed, the silicon nitride layer 31 after the completion of this step contains indium. Will be.

Further, although the silicon nitride layer 31 plays a role of protecting the electron supply layer 24 from moisture in the atmosphere, an insulating layer having the same function as this may be formed as the silicon nitride layer 31. Such insulating layers include, for example, a silicon oxide (SiO ₂ ) layer, a silicon nitride (SiON) layer, a hafnium oxide (HfO ₂ ) layer, and a silicon carbide (SiOC) layer.

Next, as shown in FIG. 9B, the silicon nitride layer 31 is patterned by photolithography and dry etching to remove the silicon nitride layer 31 from above the alumina layer 27 and open the silicon nitride layer 31. Form 31a. In the dry etching, for example, BCl ₃ gas is used as the etching gas.

The silicon nitride layer 31 may be patterned by ion milling instead of dry etching.

As a result of this patterning, the silicon nitride layer 31 is left in a partial region R2 between the opening 31a and the alumina layer 27. Further, the silicon nitride layer 31 is also left between the opening 31a and the source electrode 25.

Subsequently, as shown in FIG. 10, the nickel layer 32a and the gold layer 32b are formed in this order on the entire upper surface of the substrate 21 by the vapor deposition method, and then these films are patterned by the lift-off method to form the inside of the opening 31a. The gate electrode 32 is formed on the silicon nitride layer 31 around the gate electrode 32.

The gate electrode 32 is T-shaped in cross-sectional view, and is formed so as to come into contact with the electron supply layer 24 in the opening 31a and extend from the opening 31a onto the silicon nitride layer 31 in the partial region R2. .. The gate electrode 32 in the partial region R2 becomes a field plate 32c for relaxing the electric field applied from the drain electrode 26 to the gate electrode 32.

As described above, the basic structure of the semiconductor device 40 according to the present embodiment is completed.

FIG. 11 is an enlarged cross-sectional view of the semiconductor device 40 according to the present embodiment.

In this semiconductor device 40, indium in the film induces a high-concentration two-dimensional electron gas 39 in the electron traveling layer 23 by the action of the electron supply layer 24 having a large spontaneous polarization, so that the source-drain current is increased. Can be done.

The voltage applied to each electrode for turning on the semiconductor device 40 is not particularly limited, but for example, the source electrode 25 (see FIG. 10) is set to the ground potential, and a voltage of about 1 V to 2 V is applied to the gate electrode 32. Further, a high voltage of about 90 V is applied to the drain electrode 26.

By applying such a high voltage, a strong electric field E acts from the drain electrode 26 to the gate electrode 32, but the electric field E is dispersed and applied to the field plate 32c, which is caused by the electric field concentration. Therefore, it is possible to prevent the withstand voltage of the silicon nitride layer 31 from decreasing.

Further, in the present embodiment, by removing the alumina layer 27 from the partial region R2 where the field plate 32c is located, it becomes difficult for the electrons moving along the electric field E to be captured by the alumina layer 27.

In particular, since the movement of electrons is promoted by the strong electric field E in a part of the region R2, there is a high practical benefit of removing the alumina layer 27 in this way to prevent the electrons from being captured.

Moreover, by leaving the silicon nitride layer 31 in which indium is diffused from the underlying electron supply layer 24 in a part of the region R2, the electrons moving along the electric field E can be easily generated in the silicon nitride layer 31 by the conductive indium. It becomes possible to move, and it becomes difficult for electrons to be captured by the silicon nitride layer 31.

As a result, electron traps are less likely to occur in both the alumina layer 27 and the silicon nitride layer 31, and it is possible to suppress the occurrence of the current collapse phenomenon in the semiconductor device 40.

Further, since the silicon nitride layer 31 is removed from between the gate electrode 32 and the drain electrode 26, the leak path from the gate electrode 32 to the drain electrode 26 is not formed in the silicon nitride layer 31, so that the leakage current in the semiconductor device 40 Can be suppressed.

Further, by forming the alumina layer 27 having a dielectric constant higher than that of air between the gate electrode 32 and the drain electrode 26, a part of the electric field E passes through the alumina layer 27. As a result, it is possible to alleviate the concentration of the electric field E on the silicon nitride layer 31 under the field plate 32c, and it is also possible to increase the withstand voltage of the silicon nitride layer 31.

In particular, the band gap of the alumina layer 27 is about 5 eV, which is higher than the band gap (about 3 eV) of the silicon nitride layer 31, so that the alumina layer 27 is not easily destroyed even when exposed to the electric field E, and the withstand voltage of the semiconductor device 40. Can be enhanced.

As an insulating layer having a wider bandgap than the silicon nitride layer 31, there are aluminum-containing insulating layers such as an aluminum oxynitride layer and an aluminum nitride layer in addition to the above alumina layer 27, and any of these is replaced with the alumina layer 27. May be formed. Since the aluminum-containing insulating film has a wide band gap and a high withstand voltage, it is effective in increasing the withstand voltage of the semiconductor device 40.

The inventor of the present application has verified the effect of the present embodiment. The verification results are shown in FIGS. 12 and 13.

FIG. 12 is a graph showing the relationship between the gate-drain current Ig and the gate voltage Vg of the semiconductor device 40 according to the present embodiment.

In addition, in FIG. 12, the ideal case where the leakage current between the gate and the drain does not exist is described as a first comparative example, and the graph of the semiconductor device 1 shown in FIG. 1 is also described as a second comparative example. It has been done.

As shown in FIG. 12, in the present embodiment, the current Ig is reduced to the same extent as the ideal first comparative example, and it is clear that the leak current between the gate and the drain is suppressed. rice field. This is because the silicon nitride layer 31 is removed from between the gate electrode 32 and the drain electrode 26 as described above, so that the leak path from the gate electrode 32 to the drain electrode 26 is no longer formed in the silicon nitride layer 31. it is conceivable that.

FIG. 13 is a graph showing the relationship between the drain voltage Vd and the drain current Id of the semiconductor device 40 according to the present embodiment.

In FIG. 13, an ideal case in which electrons are not trapped in the alumina layer 27 or the silicon nitride layer 31 is described as a first comparative example, and the graph of the semiconductor device 1 shown in FIG. 1 is shown in the second. It is also described as a comparative example of.

As shown in FIG. 13, in the present embodiment, the drain current Id is increased to the same extent as in the ideal first comparative example, and it is clear that the current collapse phenomenon is suppressed. It is considered that this is because the alumina layer 27 in which the electron trap is present is removed from the partial region R2 as described above, so that it becomes difficult for electrons to be captured by the alumina layer 27. It is also considered that the current collapse phenomenon could be suppressed by leaving the silicon nitride layer 31 in which indium was diffused in a part of the region R2 so that the electrons moving along the electric field E were less likely to be trapped in the silicon nitride layer 31. Be done.

(Second Embodiment)
In this embodiment, the HEMT is manufactured by a method different from that of the first embodiment.

14 to 16 are cross-sectional views of the semiconductor device according to the present embodiment during manufacturing.

In FIGS. 14 to 16, the same elements as in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

First, by performing the steps of FIGS. 7 (a) and 7 (b) of the first embodiment, as shown in FIG. 14 (a), the source electrode 25 and the drain electrode 26 are spaced from each other on the electron supply layer 24. To obtain the formed structure.

Next, as shown in FIG. 14B, a silicon nitride layer 31 is formed on the entire upper surface of the substrate 21 by a plasma CVD method to a thickness of about 1 nm to 1000 nm, for example, about 600 nm. Since the film forming conditions of the silicon nitride layer 31 are the same as those in the first embodiment, they are omitted here.

Further, as described in the first embodiment, since the substrate 21 is heated when the silicon nitride layer 31 is formed, indium diffuses from the InAlGaN layer formed as the electron supply layer 24 to the silicon nitride layer 31.

Subsequently, as shown in FIG. 15A, the silicon nitride layer 31 is patterned by photolithography and dry etching to form an opening 31a in the silicon nitride layer 31 between the source electrode 25 and the drain electrode 26. .. Further, in this patterning, the silicon nitride layer 31 is removed from between the partial region R2 and the drain electrode 26 while leaving the silicon nitride layer 31 in the partial region R2 between the opening 31a and the drain electrode 26.

Next, as shown in FIG. 15B, a nickel layer 32a and a gold layer 32b are formed in this order on the entire upper surface of the substrate 21 by a vapor deposition method, and these films are further patterned by a lift-off method to form a T-shape. Gate electrode 32 is formed. As described in the first embodiment, the gate electrode 32 in the partial region R2 is a field plate 32c for relaxing the electric field applied from the drain electrode 26 to the gate electrode 32.

Next, as shown in FIG. 16A, an alumina layer 27 is formed on the entire upper surface of the substrate 21 to a thickness of about 1 nm to 50 nm, for example, 20 nm by the ALD method, and the gate electrode 32 is formed by the alumina layer 27. Cover.

Then, as shown in FIG. 16B, by patterning the alumina layer 27 by photolithography and wet etching, the alumina layer 27 is removed from each of the source electrode 25 and the drain electrode 26, and these electrodes are not suitable. Allow the illustrated wiring to be connected. As described in the first embodiment, the etching solution used in this wet etching includes, for example, hydrofluoric acid.

As described above, the basic structure of the semiconductor device 50 according to the present embodiment is completed.

Also in this semiconductor device 50, the indium-containing silicon nitride layer 31 is formed under the field plate 32c without forming the alumina layer 27 under the field plate 32c. Therefore, for the same reason as in the first embodiment, it becomes difficult to form an electron trap in the silicon nitride layer 31, and it is possible to suppress the occurrence of a current collapse phenomenon in the semiconductor device 50.

Further, by removing the silicon nitride layer 31 from between the partial region R2 and the drain electrode 26, it is possible to prevent a leak path from occurring in the film of the silicon nitride layer 31 containing indium, and the drain electrode 26 and the gate electrode can be prevented from occurring. It is possible to prevent a leak current from flowing between the device and the device 32.

Moreover, since the side surface and the upper surface of the gate electrode 32 are covered with the alumina layer 27, the alumina layer 27 can prevent moisture and the like in the atmosphere from entering the gate electrode 32.

(Third Embodiment)
In this embodiment, a discrete package including the semiconductor devices 40 and 50 according to the first embodiment and the second embodiment will be described.

FIG. 17 is a plan view of the discrete package according to the present embodiment.

The discrete package 100 has a HEMT chip 101 including any one of the semiconductor devices 40 and 50, and a resin 102 for encapsulating the HEMT chip 101.

Of these, the HEMT chip 101 is provided with a gate pad 103, a drain pad 104, and a source pad 105. Each of these pads is electrically connected to each of the above-mentioned gate electrode 32, drain electrode 26, and source electrode 25 via wiring (not shown).

Further, a part of each of the gate lead 110, the drain lead 111, and the source lead 112 is embedded in the resin 102. Of these, the drain lead 111 is provided with a square land 111a, and the HEMT chip 101 is adhered to the land 111a by the die attach material 107.

Each of these leads 110, 111, 112 is electrically connected to each of the gate pad 103, the drain pad 104, and the source pad 105 via a metal wire 114 such as an aluminum wire.

According to the present embodiment described above, since the HEMT chip 101 includes any of the semiconductor devices 40 and 50 in which the leakage current is suppressed, it is possible to provide the discrete package 100 having a high withstand voltage. Moreover, since the current collapse phenomenon is suppressed in the semiconductor devices 40 and 50, it is possible to increase the output of the discrete package 100.

(Fourth Embodiment)
In this embodiment, a PFC (Power Factor Correction) circuit using the HEMT chip 101 of the third embodiment will be described.

FIG. 18 is a circuit diagram of the PFC circuit.

As shown in FIG. 18, the PFC circuit 200 includes a diode 201, a choke coil 202, capacitors 203 and 204, a diode bridge 205, an AC power supply 206, and a switch element 210.

Of these, the HEMT chip 101 described in the third embodiment can be adopted as the switch element 210. The drain electrode of the switch element 210 is connected to the anode terminal of the diode 201 and one terminal of the choke coil 202.

Further, the source electrode of the switch element 210 is connected to one terminal of the capacitor 203 and one terminal of the capacitor 204.

A gate driver (not shown) is connected to the gate electrode of the switch element 210.

Further, the other terminal of the capacitor 203 and the other terminal of the choke coil 202 are connected, and the other terminal of the capacitor 204 and the cathode terminal of the diode 201 are connected.

An AC power supply 206 is connected between both terminals of the capacitor 203 via a diode bridge 205, and a DC power supply DC is connected between both terminals of the capacitor 204.

(Fifth Embodiment)
In this embodiment, the power supply device using the HEMT chip 101 of the third embodiment will be described.

FIG. 19 is a circuit diagram of the power supply device. In FIG. 19, the same elements as described in the fourth embodiment are designated by the same reference numerals as those in the fourth embodiment, and the description thereof will be omitted below.

As shown in FIG. 19, the power supply unit 300 includes a high voltage primary circuit 301, a low voltage secondary circuit 302, and a transformer 303 connected between them.

Of these, the primary side circuit 301 is provided with the PFC circuit 200 described in the fourth embodiment and the full bridge inverter circuit 304 connected between both terminals of the capacitor 204 of the PFC circuit 200.

The full-bridge inverter circuit 304 is provided with four switch elements 304a, 304b, 304c, 304d. As each of these switch elements 304a, 304b, 304c, 304d, the HEMT chip 101 described in the third embodiment can be adopted.

On the other hand, the secondary circuit 302 includes three switch elements 302a, 302b, and 302c. As these switch elements 302a, 302b, 302c, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) in which a channel is formed on a silicon substrate can be adopted.

According to the present embodiment described above, the HEMT chip 101 is adopted for each of the switch elements 210, 304a, 304b, 304c, and 304d. Since the HEMT chip 101 suppresses the leakage current and the current collapse phenomenon, it is possible to provide a power supply device 300 having a high withstand voltage and suitable for high output applications.

(Sixth Embodiment)
In this embodiment, the high frequency amplifier using the HEMT chip 101 of the third embodiment will be described.

FIG. 20 is a circuit diagram of the high frequency amplifier.

As shown in FIG. 20, the high frequency amplifier 400 includes a digital predistortion circuit 401, mixers 402 and 403, and a power amplifier 404.

Of these, the digital predistortion circuit 401 compensates for the non-linear distortion of the input signal. Further, the mixer 402 mixes the input signal compensated for the non-linear distortion and the AC signal.

The power amplifier 404 includes the above-mentioned HEMT chip 101, and amplifies the input signal mixed with the AC signal. In this embodiment, the output side signal can be mixed with the AC signal by the mixer 403 and sent to the digital predistortion circuit 401 by switching the switch.

According to the present embodiment described above, since the leakage current and the current collapse phenomenon are suppressed in the HEMT chip 101 built in the power amplifier 404, it is possible to provide a high frequency amplifier 400 having a high withstand voltage and suitable for high output applications. can.

The following additional notes will be further disclosed with respect to each of the above-described embodiments.

(Appendix 1) Board and
An electronic traveling layer formed above the substrate and
An electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium,
The source electrode formed on the electron supply layer and
A drain electrode formed on the electron supply layer at a distance from the source electrode,
A first insulating layer on the electron supply layer and formed in a partial region between the source electrode and the drain electrode.
A gate electrode formed on the electron supply layer between the first insulating layer and the source electrode and extending over the first insulating layer, and a gate electrode.
A second insulating layer formed on the electron supply layer between the first insulating layer and the drain electrode and having a wider bandgap than the first insulating layer.
Semiconductor device with.

(Appendix 2) The semiconductor device according to Appendix 1, wherein the second insulating layer is an aluminum-containing insulating layer.

(Supplementary Note 3) The semiconductor device according to Supplementary Note 1, wherein the second insulating layer covers the side surface and the upper surface of the gate electrode.

(Appendix 4) The semiconductor device according to Appendix 1, wherein the first insulating layer contains indium.

(Appendix 5) The process of forming an electronic traveling layer above the substrate and
A step of forming an electron supply layer made of a compound semiconductor containing indium on the electron traveling layer, and a step of forming the electron supply layer.
A step of forming a source electrode and a drain electrode on the electron supply layer at intervals from each other,
A step of forming a first insulating layer on a partial region between the source electrode and the drain electrode on the electron supply layer.
A step of forming a gate electrode so as to extend from the electron supply layer onto the first insulating layer on the electron supply layer between the first insulating layer and the source electrode.
A step of forming a second insulating layer having a bandgap wider than that of the first insulating layer on the electron supply layer between the first insulating layer and the drain electrode.
A method for manufacturing a semiconductor device having.

(Appendix 6) Board and
An electronic traveling layer formed above the substrate and
An electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium,
The source electrode formed on the electron supply layer and
A drain electrode formed on the electron supply layer at a distance from the source electrode,
A first insulating layer on the electron supply layer and formed in a partial region between the source electrode and the drain electrode.
A gate electrode formed on the electron supply layer between the first insulating layer and the source electrode and extending over the first insulating layer, and a gate electrode.
A second insulating layer formed on the electron supply layer between the first insulating layer and the drain electrode and having a wider bandgap than the first insulating layer.
A power supply unit having a semiconductor device.

(Appendix 7) With the board
An electronic traveling layer formed above the substrate and
An electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium,
The source electrode formed on the electron supply layer and
A drain electrode formed on the electron supply layer at a distance from the source electrode,
A first insulating layer on the electron supply layer and formed in a partial region between the source electrode and the drain electrode.
A gate electrode formed on the electron supply layer between the first insulating layer and the source electrode and extending over the first insulating layer, and a gate electrode.
A second insulating layer formed on the electron supply layer between the first insulating layer and the drain electrode and having a wider bandgap than the first insulating layer.
A high frequency amplifier with a semiconductor device equipped with.

1 ... semiconductor device, 2 ... substrate, 3 ... buffer layer, 4 ... electron traveling layer, 5 ... electron supply layer, 6 ... source electrode, 7 ... drain electrode, 8 ... silicon nitride layer, 8a ... opening, 9 ... gate electrode , 9a ... field plate, 9b ... facing surface, 10 ... two-dimensional electron gas, 11 ... alumina layer, 21 ... substrate, 22 ... buffer layer, 23 ... electron traveling layer, 24 ... electron supply layer, 25 ... source electrode, 26. Drain electrode, 27 ... alumina layer, 31 ... silicon nitride layer, 31a ... opening, 32 ... gate electrode, 32a ... nickel layer, 32b ... gold layer, 32c ... field plate, 40, 50 ... semiconductor device, 100 ... discrete package , 101 ... HEMT chip, 102 ... resin, 103 ... gate pad, 104 ... drain pad, 105 ... source pad, 107 ... diode material, 110 ... gate lead, 111a ... land, 111 ... drain lead, 112 ... source lead, 114 ... metal wire, 200 ... PFC circuit, 201 ... diode, 202 ... choke coil, 203, 204 ... capacitor, 205 ... diode bridge, 206 ... AC power supply, 301 ... primary side circuit, 302 ... secondary side circuit, 303 ... Transformer, 304 ... Full bridge inverter circuit, 302a, 302b, 302c ... Switch element, 400 ... High frequency amplifier, 401 ... Digital predistortion circuit, 402, 403 ... Mixer, 404 ... Power amplifier.

Claims (5)

With the board
An electronic traveling layer formed above the substrate and
An electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium,
The source electrode formed on the electron supply layer and
A drain electrode formed on the electron supply layer at a distance from the source electrode,
A first insulating layer on the electron supply layer and formed in a partial region between the source electrode and the drain electrode.
A gate electrode formed on the electron supply layer between the first insulating layer and the source electrode and extending over the first insulating layer, and a gate electrode.
A second layer formed on the electron supply layer between the first insulating layer and the drain electrode , covering the side surface and the upper surface of the gate electrode, and having a wider bandgap than the first insulating layer. Insulation layer and
Have a,
The first insulating layer, a silicon nitride layer, a silicon oxide layer, silicon oxynitride layer, a hafnium oxide layer or a silicon oxide carbide layer der Ru semiconductor device. The semiconductor device according to claim 1, wherein the second insulating layer is an aluminum-containing insulating layer. The process of forming an electronic traveling layer above the substrate,
A step of forming an electron supply layer made of a compound semiconductor containing indium on the electron traveling layer, and a step of forming the electron supply layer.
A step of forming a source electrode and a drain electrode on the electron supply layer at intervals from each other,
A step of forming a first insulating layer on a partial region between the source electrode and the drain electrode on the electron supply layer.
A step of forming a gate electrode so as to extend from the electron supply layer onto the first insulating layer on the electron supply layer between the first insulating layer and the source electrode.
A second insulating layer that covers the side surface and the upper surface of the gate electrode on the electron supply layer between the first insulating layer and the drain electrode and has a bandgap wider than that of the first insulating layer. And the process of forming
Have a,
The first insulating layer, a silicon nitride layer, a silicon oxide layer, silicon oxynitride layer, a manufacturing method of a hafnium oxide layer or a silicon oxide carbide layer der Ru semiconductor device. With the board
An electronic traveling layer formed above the substrate and
An electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium,
The source electrode formed on the electron supply layer and
A drain electrode formed on the electron supply layer at a distance from the source electrode,
A first insulating layer on the electron supply layer and formed in a partial region between the source electrode and the drain electrode.
A gate electrode formed on the electron supply layer between the first insulating layer and the source electrode and extending over the first insulating layer, and a gate electrode.
A second layer formed on the electron supply layer between the first insulating layer and the drain electrode , covering the side surface and the upper surface of the gate electrode, and having a wider bandgap than the first insulating layer. Insulation layer and
Equipped with
The first insulating layer is a power supply device having a semiconductor device which is a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, or a silicon carbide layer. With the board
An electronic traveling layer formed above the substrate and
An electron supply layer formed on the electron traveling layer and made of a compound semiconductor containing indium,
The source electrode formed on the electron supply layer and
A drain electrode formed on the electron supply layer at a distance from the source electrode,
A first insulating layer on the electron supply layer and formed in a partial region between the source electrode and the drain electrode.
A gate electrode formed on the electron supply layer between the first insulating layer and the source electrode and extending over the first insulating layer, and a gate electrode.
A second layer formed on the electron supply layer between the first insulating layer and the drain electrode , covering the side surface and the upper surface of the gate electrode, and having a wider bandgap than the first insulating layer. Insulation layer and
Equipped with
The first insulating layer is a high frequency amplifier having a semiconductor device which is a silicon nitride layer, a silicon oxide layer, a silicon nitride layer, a hafnium oxide layer, or a silicon carbide layer.

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