JP6981505B2 - Method for manufacturing silicon carbide epitaxial substrate - Google Patents

Description

The present disclosure relates to a silicon carbide epitaxial substrate.

Japanese Unexamined Patent Publication No. 2015-32788 (Patent Document 1) discloses a silicon carbide epitaxial substrate provided with a deformation suppressing layer on the back surface side of the silicon carbide substrate.

Japanese Unexamined Patent Publication No. 2015-032788

An object of the present disclosure is to provide a silicon carbide epitaxial substrate capable of suppressing the occurrence of chucking defects.

The silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide layer is on the first main surface. The silicon carbide single crystal substrate does not have a strain layer on the second main surface. When the amount of warpage when the substrate temperature is room temperature is defined as the first amount of warpage, and the amount of warpage when the substrate temperature is 350 ° C. or higher and 600 ° C. or lower is defined as the second warp amount, the first warp amount is It is 25 μm or less. Further, the absolute value of the difference between the first warp amount and the second warp amount is 25 μm or less.

According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate capable of suppressing the occurrence of chucking defects.

It is a perspective schematic diagram which shows the silicon carbide epitaxial substrate which concerns on this embodiment. It is sectional drawing of the line segment II-II of FIG. It is a schematic diagram for demonstrating the method of measuring the warp of a silicon carbide epitaxial substrate. It is a schematic diagram for demonstrating the warp of a silicon carbide epitaxial substrate. It is a flowchart which shows the outline of the manufacturing method of the silicon carbide epitaxial substrate which concerns on this embodiment.

[Explanation of Embodiments of the present disclosure]
In the following description, the same or corresponding elements are designated by the same reference numerals, and the same description is not repeated for them. In the crystallographic description of the present specification, the individual orientation is indicated by [], the aggregate orientation is indicated by <>, the individual plane is indicated by (), and the aggregate plane is indicated by {}. Negative crystallographic exponents are usually expressed by adding a "-" (bar) above the number, but here the number is preceded by a negative sign for crystallography. Represents the above negative exponent. Further, in the following description, regarding the crystal plane of silicon carbide (SiC), the (000-1) plane may be referred to as a “C (carbon) plane” and the (0001) plane may be referred to as a “Si (silicon) plane”.

(1) The silicon carbide epitaxial substrate 10 according to the present disclosure includes a silicon carbide single crystal substrate 1 and a silicon carbide layer 2. The silicon carbide single crystal substrate 1 has a first main surface 3 and a second main surface 4 opposite to the first main surface 3. The silicon carbide layer 2 is on the first main surface 3. The silicon carbide single crystal substrate 1 does not have a strain layer on the second main surface 4. When the amount of warpage when the substrate temperature is room temperature is defined as the first amount of warpage, and the amount of warpage when the substrate temperature is 350 ° C. or higher and 600 ° C. or lower is defined as the second warp amount, the first warp amount is It is 25 μm or less. Further, the absolute value of the difference between the first warp amount and the second warp amount is 25 μm or less.

By doing so, the amount of warpage of the silicon carbide epitaxial substrate 10 is sufficiently small both when the substrate temperature is room temperature and when the substrate temperature is as high as 350 ° C. or higher and 600 ° C. or lower. Therefore, when forming the silicon carbide layer 2 on the silicon carbide single crystal substrate 1 or when manufacturing a silicon carbide semiconductor device using the silicon carbide epitaxial substrate 10, for example, a manufacturing device such as a film forming device or an ion injection device. When a silicon carbide single crystal substrate or the silicon carbide epitaxial substrate is fixed to the chucking stage of the substrate in the above, it is possible to suppress the occurrence of chucking defects due to a large amount of warpage of the substrate. As a result, it is possible to suppress the occurrence of quality defects in the manufacturing process due to chucking defects.

Here, the strain layer is a damage layer generated on the second main surface 4 when the second main surface 4 of the silicon carbide single crystal substrate 1 is processed by mechanical polishing or the like, and specifically. Means a layer in which the crystal lattice is disturbed. The presence or absence of this strain layer can be determined by using, for example, the EBSD (Electron Back Scatter Diffraction Patterns) method described later. Further, as the substrate temperature, for example, a value measured by an arbitrary measuring means for the surface temperature of the silicon carbide layer of the silicon carbide epitaxial substrate 10 may be used, or the temperature of the second main surface of the silicon carbide single crystal substrate may be arbitrary. The value measured by the measuring means of may be used. As the measuring means, for example, a radiation thermometer can be used.

(2) In the silicon carbide epitaxial substrate 10 according to (1) above, the total thickness of the silicon carbide single crystal substrate 1 and the silicon carbide layer 2 may be 300 μm or more and 550 μm or less.

(3) In the silicon carbide epitaxial substrate 10 according to the above (1) or (2), the maximum diameter of the silicon carbide single crystal substrate 1 may be 110 mm or more and 150 mm or less.

(4) In the silicon carbide epitaxial substrate 10 according to any one of (1) to (3) above, even if the arithmetic average roughness Sa in the three-dimensional surface roughness measurement of the second main surface 4 is 0.3 nm or less. good.

Here, "arithmetic mean roughness Sa" is a three-dimensional surface texture parameter defined in the international standard ISO25178, and can be measured using, for example, a white interference microscope. The measurement area of the white interference microscope is, for example, 255 μm square.

(5) In the silicon carbide epitaxial substrate 10 according to any one of (1) to (4) above, when the amount of warpage when the substrate temperature is more than 600 ° C. and 1200 ° C. or less is taken as the third warp amount. The absolute value of the difference between the first warp amount and the third warp amount may be 25 μm or less.

(6) In the silicon carbide epitaxial substrate 10 according to any one of (1) to (5) above, the thickness of the silicon carbide layer 2 may be 5 μm or more and 50 μm or less.

[Details of Embodiments of the present disclosure]
Hereinafter, an embodiment of the present disclosure (hereinafter, also referred to as “the present embodiment”) will be described. However, this embodiment is not limited to these.

(Silicon carbide epitaxial substrate)
As shown in FIGS. 1 and 2, the silicon carbide epitaxial substrate 10 according to the present embodiment has a silicon carbide single crystal substrate 1 and a silicon carbide layer 2. The silicon carbide single crystal substrate 1 includes a first main surface 3 and a second main surface 4 opposite to the first main surface 3. The silicon carbide layer 2 includes a third main surface 5 in contact with the silicon carbide single crystal substrate 1 and a fourth main surface 6 opposite to the third main surface 5.

The silicon carbide single crystal substrate 1 does not have a strain layer on the second main surface 4. For the measurement regarding the presence or absence of the strain layer on the second main surface 4, for example, the EBSD method can be used. The details of the method for measuring the strain layer will be described later. Further, in the silicon carbide epitaxial substrate 10, the warp amount when the substrate temperature of the silicon carbide epitaxial substrate 10 is room temperature is set as the first warp amount, and the warp amount when the substrate temperature is 350 ° C. or higher and 600 ° C. or lower is used. When the second warp amount is used, the first warp amount is 25 μm or less. Further, the absolute value of the difference between the first warp amount and the second warp amount is 25 μm or less. Further, when the amount of warpage when the substrate temperature is more than 600 ° C. and 1200 ° C. or less is taken as the third warp amount, the absolute value of the difference between the first warp amount and the third warp amount is 25 μm or less. You may. Details of such a method for measuring the amount of warpage will be described later.

The first warp amount may be 20 μm or less, or 15 μm or less. The lower limit of the first warp amount may be, for example, 5 μm. Further, the absolute value of the difference between the first warp amount and the second warp amount may be 20 μm or less, or 15 μm or less. The lower limit of the absolute value of the difference may be, for example, 5 μm.

Further, the absolute value of the difference between the first warp amount and the third warp amount may be 20 μm or less, or 15 μm or less. The lower limit of the absolute value of the difference may be, for example, 5 μm.

The thickness of the silicon carbide epitaxial substrate 10 is, for example, the total thickness of the silicon carbide single crystal substrate 1 and the silicon carbide layer 2. The total thickness is, for example, 300 μm or more. The total thickness may be 350 μm or more, or 400 μm or more. The upper limit of the total thickness is not particularly limited. The upper limit of the total thickness may be, for example, 550 μm.

Further, the maximum diameter (diameter) of the silicon carbide single crystal substrate 1 is, for example, 110 mm or more. The maximum diameter may be 150 mm or more, 200 mm or more, or 250 mm or more. The upper limit of the maximum diameter is not particularly limited. The upper limit of the maximum diameter may be, for example, 300 mm.

In the silicon carbide epitaxial substrate 10, the arithmetic average roughness Sa in the three-dimensional surface roughness measurement of the second main surface 4 is 0.3 nm or less. The arithmetic mean roughness Sa may be 0.2 nm or less, 0.15 nm or less, or 0.1 nm or less. The lower limit of the arithmetic mean roughness Sa may be, for example, 0.03 nm.

The silicon carbide single crystal substrate 1 (hereinafter, may be abbreviated as “single crystal substrate”) is composed of a silicon carbide single crystal. The polytype of the silicon carbide single crystal is, for example, 4H-SiC. 4H-SiC is superior to other polytypes in electron mobility, dielectric breakdown electric field strength and the like. The silicon carbide single crystal substrate 1 contains n-type impurities such as nitrogen. The conductive type of the silicon carbide single crystal substrate 1 is, for example, n type. The first main surface 3 is, for example, a {0001} surface or a surface inclined by 8 ° or less from the {0001} surface. When the first main surface 3 is inclined from the {0001} surface, the inclination direction of the normal of the first main surface 3 is, for example, the <11-20> direction.

The silicon carbide layer 2 is an epitaxial layer formed on the silicon carbide single crystal substrate 1. The silicon carbide layer 2 is on the first main surface 3. The silicon carbide layer 2 is in contact with the first main surface 3. The silicon carbide layer 2 contains n-type impurities such as nitrogen. The conductive type of the silicon carbide layer 2 is, for example, n type. The concentration of the n-type impurities contained in the silicon carbide layer 2 may be higher than the concentration of the n-type impurities contained in the silicon carbide single crystal substrate 1. The thickness of the silicon carbide layer 2 is, for example, 5 μm or more. The thickness of the silicon carbide layer 2 may be 10 μm or more, 15 μm or more, or 20 μm or more. The upper limit of the thickness of the silicon carbide layer 2 is not particularly limited. The upper limit of the thickness of the silicon carbide layer 2 may be, for example, 50 μm.

The fourth main surface 6 shown in FIG. 2 may be, for example, a {0001} surface or a surface inclined by 8 ° or less from the {0001} surface. Specifically, the fourth main surface 6 may be a (0001) plane or a plane inclined by 8 ° or less from the (0001) plane. The inclination direction (off direction) of the normal of the fourth main surface 6 may be, for example, the <11-20> direction. The inclination angle (off angle) from the {0001} plane may be 1 ° or more, or 2 ° or more. The off angle may be 7 ° or less, or 6 ° or less.

(Measurement of strain layer)
The presence or absence of the strain layer can be determined by using the EBSD method. Specifically, the presence of the strain layer is determined by measuring the plane orientation at the center and the end of the second main surface 4 of the silicon carbide single crystal substrate 1 by the EBSD method.

(Measurement of warpage)
The amount of warpage of the silicon carbide epitaxial substrate 10 is measured using the measuring device shown in FIG. This will be described in detail below.

The measuring device shown in FIG. 3 mainly includes a measuring container 22 in which the heating stage 20 is arranged at the bottom, a laser light source 24, a mirror 25, and a detector 27. A plurality of support pins 21 are arranged on the upper surface of the heating stage 20. The number of support pins 21 may be, for example, three. The silicon carbide epitaxial substrate 10 to be measured is mounted on the support pin 21. In addition, there is an opening in the upper part of the measuring container 22, and the lid 23 may be arranged so as to close the opening. As the lid 23, for example, a glass plate can be used. The lid 23 may be made of any material as long as it can transmit the laser beam.

A mirror 25 and a detector 27 are arranged on the upper part of the measuring container 22. The mirror 25 reflects the laser light emitted from the laser light source 24 and irradiates the silicon carbide epitaxial substrate 10 on the heating stage 20 with the laser light. The irradiated laser beam is reflected on the surface of the silicon carbide epitaxial substrate 10. The laser beam reflected on the surface is detected by the detector 27. Here, in order to irradiate the entire silicon carbide epitaxial substrate 10 with the laser beam, the mirror 25 can move in the direction along the upper surface of the heating stage 20 indicated by the arrow 26. Further, as the mirror 25 moves, the detector 27 also becomes movable.

In this way, the reflection angle of the laser light on the surface of the silicon carbide epitaxial substrate 10 can be detected from the positional relationship between the mirror 25 and the detector 27 and the detection position of the laser light in the detector 27. Further, the position of the surface of the silicon carbide epitaxial substrate 10 in the vertical direction can be obtained based on the detection angle.

Further, the heating stage 20 includes a heating device having an arbitrary configuration such as a heat transfer heater. By heating the silicon carbide epitaxial substrate 10 by the heating stage 20, the substrate temperature of the silicon carbide epitaxial substrate 10 can be set to an arbitrary temperature. Then, with the substrate temperature of the silicon carbide epitaxial substrate 10 set arbitrarily, the surface of the silicon carbide epitaxial substrate 10 is irradiated with the laser light as described above, and the reflected laser light is detected. In this way, the position of the surface of the silicon carbide epitaxial substrate 10 in the vertical direction can be obtained at an arbitrary substrate temperature.

Here, the amount of warpage of the silicon carbide epitaxial substrate 10 is the main surface of the silicon carbide epitaxial substrate 10 when the silicon carbide epitaxial substrate 10 is placed on a flat surface 31 such as a gantry 30 as shown in FIG. It can be defined as the height difference H between the highest position and the lowest position with respect to the flat surface 31. Therefore, the value corresponding to the difference H in FIG. 4 can be obtained from the data of the position of the surface of the silicon carbide epitaxial substrate 10 in the vertical direction measured by the apparatus shown in FIG.

(Measuring method of warpage when the substrate temperature is 350 ° C or higher and 600 ° C or lower)
Using the measuring device shown in FIG. 3, the amount of warpage of the silicon carbide epitaxial substrate 10 is measured when the substrate temperature is 350 ° C. or higher and 600 ° C. or lower. Specifically, the amount of warpage is measured at a plurality of substrate temperatures having a predetermined temperature difference, for example, a temperature difference of 50 ° C. For example, the amount of warpage may be measured by the methods described above in a state where the substrate temperature is 350 ° C., 400 ° C., 450 ° C., 500 ° C., 550 ° C., and 600 ° C., respectively. The maximum amount of warpage at each of the above-mentioned substrate temperatures in the above-mentioned range of 350 ° C. or higher and 600 ° C. or lower may be used as the second warp amount.

(Measuring method of warpage when the substrate temperature exceeds 600 ° C and is 1200 ° C or less)
Using the measuring device shown in FIG. 3, the amount of warpage of the silicon carbide epitaxial substrate 10 is measured when the substrate temperature exceeds 600 ° C. and is 1200 ° C. or lower. Specifically, the amount of warpage is measured at a plurality of substrate temperatures having a predetermined temperature difference, for example, a temperature difference of 50 ° C. For example, the substrate temperature was set to 650 ° C, 700 ° C, 750 ° C, 800 ° C, 850 ° C, 900 ° C, 950 ° C, 1000 ° C, 1050 ° C, 1100 ° C, 1150 ° C, and 1200 ° C, respectively, by the above-mentioned methods. The amount of warpage may be measured. The maximum amount of warpage at each of the above-mentioned substrate temperatures in the above-mentioned range of more than 600 ° C. and 1200 ° C. or less may be used as the third warp amount.

(Manufacturing method of silicon carbide epitaxial substrate)
Next, a method for manufacturing the silicon carbide epitaxial substrate according to the present embodiment will be described.

First, a step (S10) of preparing a substrate is carried out as shown in FIG. Specifically, for example, a silicon carbide single crystal is produced by a sublimation method. By slicing the silicon carbide single crystal with, for example, a wire saw, a substrate to be a silicon carbide single crystal substrate is obtained.

Next, as shown in FIG. 5, a step (S20) of processing the substrate is performed. Specifically, first, the end portion of the substrate is chamfered (S21). As the chamfering method, any conventionally known method can be used. Next, in the substrate, the surface to be the first main surface and the second main surface of the silicon carbide single crystal substrate is ground (S22). Any method can be used as the grinding method.

Next, the first main surface and the surface to be the second main surface are mechanically polished (S23). Any method can be used for mechanical polishing, but for example, mechanical polishing may be performed using a polishing cloth while supplying a liquid containing at least abrasive grains to the surface of the substrate. Further, the above two surfaces may be polished at the same time. By this mechanical polishing, a strain layer is formed on the surface of the surface to be the second surface of the substrate. The particle size of the abrasive grains used in mechanical polishing may be, for example, 0.2 μm or more and 3.0 μm or less.

Next, chemical mechanical polishing (CMP) processing is performed on the surface to be the second main surface (back surface) of the substrate (S24). Process conditions such as abrasive grains and additives used in CMP processing can be appropriately selected from conventionally known conditions. However, the amount of polishing in this CMP step is three times or more the diameter of the abrasive grains used in the above-mentioned mechanical polishing. By doing so, the strain layer on the second surface of the silicon carbide crystal substrate can be removed. The particle size of the abrasive grains used in the CMP step may be, for example, 1 nm or more and 200 nm or less.

Next, CMP processing is performed on the surface to be the first main surface of the substrate (S25). Process conditions such as abrasive grains and additives used in CMP processing can be appropriately selected from conventionally known conditions. In this way, the silicon carbide single crystal substrate 1 constituting the silicon carbide epitaxial substrate 10 is obtained.

Next, as shown in FIG. 5, the step (S30) of forming the epitaxial layer is carried out. Specifically, the silicon carbide layer 2 is epitaxially grown on the first main surface of the silicon carbide single crystal substrate 1. As a method for growing the silicon carbide layer 2, any conventionally known method can be used. In this way, the silicon carbide epitaxial substrate shown in FIG. 1 can be obtained.

In the step of forming the epitaxial layer (S30), the silicon carbide single crystal substrate 1 is mounted on a susceptor or the like of a film forming apparatus and heated. Since the silicon carbide single crystal substrate 1 according to the present embodiment does not have a strain layer on the second main surface, the amount of warpage of the silicon carbide single crystal substrate 1 becomes large during heating as described above, resulting in poor chucking and the like. It is possible to suppress the occurrence of the problem.

(Example)
<Sample>
The following No. 1-No. As a sample of 7, a silicon carbide single crystal substrate having a diameter of 6 inches and a thickness of 350 μm was prepared.

No. Sample 1:
The steps (S10), steps (S21) to steps (S23), and steps (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 1 was obtained. In the mechanical polishing in the step (S23), an abrasive grain made of diamond having a particle size of 1 μm was used as the abrasive grain.

No. Sample 2:
The steps (S10) and steps (S21) to (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 2 was obtained. Regarding the step (S10), the step (S21) to the step (S23), and the step (S25), No. The conditions were the same as in the manufacturing process of the sample of 1. As the conditions for CMP in the step (S24), a slurry containing colloidal silica as abrasive grains and sodium triisosocyanurate and tetramethylammonium hydroxide (TMAH) as additives in ultrapure water was used. Further, as the polishing cloth used in the CMP in this step (S24), suede or a non-woven fabric was used. As the non-woven fabric, the Asker A hardness may be 30 to 70 or 30 to 50. The polishing amount in this step (S24) was 1 μm.

No. Sample of 3:
The steps (S10) and steps (S21) to (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 3 was obtained. Regarding the step (S10) and the steps (S21) to (S25), No. The conditions were the same as in the sample manufacturing process of 2. However, the amount of polishing by CMP in the step (S24) was set to 3 μm.

No. Sample of 4:
The steps (S10) and steps (S21) to (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 4 was obtained. Regarding the step (S10) and the steps (S21) to (S25), No. The conditions were the same as in the sample manufacturing process of 2. However, the amount of polishing by CMP in the step (S24) was set to 5 μm.

No. Sample of 5:
The steps (S10) and steps (S21) to (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 5 was obtained. Regarding the step (S10), the step (S21) to the step (S23), and the step (S25), No. The conditions were the same as in the manufacturing process of the sample of 1. As the conditions for CMP in the step (S24), a slurry containing colloidal silica as abrasive grains and sodium dichloroisocyanurate as an additive in ultrapure water was used. The polishing amount in this step (S24) was set to 3 μm.

No. Sample of 6:
The steps (S10) and steps (S21) to (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 6 was obtained. Regarding the step (S10), the step (S21) to the step (S23), and the step (S25), No. The conditions were the same as in the manufacturing process of the sample of 1. As the conditions for CMP in the step (S24), a slurry containing zirconium oxide as abrasive grains and nitric acid and sodium permanganate as additives in ultrapure water was used. The polishing amount in this step (S24) was set to 3 μm.

No. Sample 7:
The steps (S10) and steps (S21) to (S25) shown in FIG. 5 were carried out to obtain the sample No. A silicon carbide single crystal substrate as No. 7 was obtained. Regarding the step (S10), the step (S21) to the step (S23), and the step (S25), No. The conditions were the same as in the manufacturing process of the sample of 1. As the conditions for CMP in the step (S24), a slurry containing chromium oxide as abrasive grains and sodium hypochlorite and malic acid as additives in ultrapure water was used. The polishing amount in this step (S24) was set to 3 μm.

<Measurement>
Measurement of Arithmetic Mean Roughness Sa of Surface:
Arithmetic mean roughness Sa (hereinafter, also referred to as surface roughness Sa) was measured for the first main surface (front surface) and the second main surface (back surface) of each sample. As a measurement method, measurement was performed using a white interference microscope or the like. The measurement area of the white interference microscope is, for example, 255 μm square, and the measurement positions are the center of each surface and the position of 30 mm from the center to the outer periphery, and are arranged at equal intervals in the circumferential direction, for a total of 5 points. The arithmetic average roughness Sa was measured, and the average value of the measured data was taken as the arithmetic average roughness Sa of each surface.

Strain layer measurement:
The depth of the strain layer (sometimes called the damage layer) was measured for the second main surface (back surface) of each sample. The EBSD method was used as a method for measuring the strain layer. Specifically, the presence of the strain layer was determined by measuring the plane orientation at the center and the end of the second main surface of each sample by the EBSD method.

Measurement of substrate warpage during heating:
Using the apparatus shown in FIG. 3, the amount of warpage of each sample was measured when the substrate temperature was set to 450 ° C.

<Result>
The results are shown in Table 1. In Table 1, the CMP polishing amount on the back surface indicates the polishing amount in the above-mentioned step (S24). Further, the back surface roughness Sa indicates the arithmetic mean roughness Sa on the second main surface. The surface roughness Sa indicates the arithmetic mean roughness Sa on the first main surface. The EBSD back surface damage depth indicates the depth of the strain layer measured by the EBSD method on the second surface. Further, in the column for evaluating the substrate warp at 450 ° C., the case where the warp amount is less than the threshold value of 25 μm is displayed as OK, and the case where the warp amount is equal to or more than the threshold value is displayed as NG.

As shown in Table 1, the sample No. 1 and sample No. Regarding No. 2, since the amount of CMP polishing with respect to the second main surface was small, the strain layer remained on the second main surface, so that the amount of warpage at 450 ° C. was relatively large. On the other hand, sample No. For Nos. 3 to 7, since the strain layer did not remain on the second main surface, the amount of warpage at 450 ° C. was relatively small.

The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the embodiments described above, and is intended to include the meaning equivalent to the scope of claims and all modifications within the scope.

1 Silicon carbide single crystal substrate 2 Silicon carbide layer 3 1st main surface 4 2nd main surface 5 3rd main surface 6 4th main surface 10 Silicon carbide epitaxial substrate 20 Heating stage 21 Support pin 22 Measuring container 23 Lid (glass plate) )
24 Laser light source 25 Mirror 26 Arrow 27 Detector 30 Mount 31 Flat surface H Difference in height between the highest position and the lowest position with respect to the flat surface on the main surface of the silicon carbide epitaxial substrate S10 Step to prepare the substrate S20 Step of processing the substrate S30 Step of forming the epitaxial layer

Claims (2)

The process of preparing a silicon carbide single crystal substrate and
A step of mechanically polishing the first main surface of the silicon carbide single crystal substrate and the second main surface opposite to the first main surface.
After the step of performing the mechanical polishing, a step of performing a second main surface chemical mechanical polishing on the second main surface with a polishing amount of 3 times or more the particle size of the abrasive grains used in the mechanical polishing.
After the step of performing the second main surface chemical mechanical polishing, the step of performing the first main surface chemical mechanical polishing on the first main surface and
A method for manufacturing a silicon carbide epitaxial substrate, comprising a step of forming an epitaxial layer of silicon carbide on the first main surface after the step of performing the first main surface chemical mechanical polishing. The machine abrasive grains having a grain size in the polishing is at 0.2μm or 3.0μm or less, the second major surface chemical mechanical polishing definitive abrasive grains having a grain size is 1nm or more 200nm or less, carbonization of claim 1 A method for manufacturing a silicon epitaxial substrate.

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