JP6960602B2 - Silicon carbide semiconductor device - Google Patents

Description

The present disclosure relates to silicon carbide semiconductor devices.

A power semiconductor device is a semiconductor device used for applications in which a large current flows with a high withstand voltage, and is desired to have a low loss. Conventionally, power semiconductor devices using a silicon (Si) substrate have been the mainstream, but in recent years, power semiconductor devices using a silicon carbide (SiC) substrate have attracted attention and are being developed.

Since silicon carbide (SiC) has an order of magnitude higher breakdown voltage of the material itself than silicon (Si), it is possible to maintain the withstand voltage even if the depletion layer at the pn junction or Schottky junction is thinned. It has characteristics. Therefore, when silicon carbide is used, the thickness of the device can be reduced and the doping concentration can be increased. Therefore, silicon carbide is a power semiconductor device having a low on-resistance, a high withstand voltage, and a low loss. It is expected as a material for forming.

In recent years, vehicles using a motor as a drive source, such as a hybrid vehicle, an electric vehicle, and a fuel cell vehicle, have been developed. Since the above-mentioned features are advantageous for switching elements of inverter circuits that drive the motors of these vehicles, silicon carbide power semiconductor devices for automobiles have been developed.

In-vehicle electronic components are required to be more durable against harsh environmental conditions than other consumer electronic components from the viewpoint that the vehicle can be used in various outdoor environments. For example, the durability of electronic components is evaluated by a high temperature and high humidity bias test (hereinafter referred to as THB test). Patent Documents 1 and 2 disclose semiconductor devices that are reliable in a high temperature and high humidity bias environment.

JP-A-2015-220334 Japanese Unexamined Patent Publication No. 2014-138090

In the above-mentioned conventional semiconductor device, further improvement in reliability has been required. One aspect of the present disclosure provides a more reliable silicon carbide semiconductor device.

The silicon carbide semiconductor device of the present disclosure includes a first conductive type silicon carbide substrate including an active region and a terminal region surrounding the active region, a plurality of unit cells located in the active region, and a terminal located in the terminal region. A silicon carbide semiconductor device having a structure, each unit cell is selected on the surface of at least the silicon carbide substrate, the first silicon carbide semiconductor layer on the silicon carbide substrate, and the first silicon carbide semiconductor layer. The first body region of the second conductive type, the source region selectively formed in the first body region, and the gate insulating film located above the first silicon carbide semiconductor layer. A gate electrode located on the gate insulating film, a first contact region in contact with the first body region, and an inner peripheral upper source electrode electrically connected to the first contact region and the source region are included. The terminal structure is selectively formed on the surfaces of the silicon carbide substrate, the first silicon carbide semiconductor layer located on the silicon carbide substrate, and the first silicon carbide semiconductor layer, and surrounds the active region. A second conductive type second body region having a shape, at least one second conductive type ring located on the surface of the first silicon carbide semiconductor layer and surrounding the second body region, and the second body. A second conductive type second contact region selectively formed on the surface of the region, an interlayer insulating film located above the second contact region, and an interlayer insulating film located above the interlayer insulating film. And electrically connected to the second contact region, at least one outer peripheral upper source electrode surrounding the active region, and electrically connected to the gate electrode, the inner peripheral upper source electrode of the active region. It includes an upper gate electrode located between the outer peripheral upper source electrode and the outer peripheral upper source electrode, is made of silicon nitride, and in the active region and the terminal region, except for the pad region, the inner peripheral upper source electrode and the upper gate electrode. A second protective film that covers at least the inner surface of the outer peripheral upper source electrode and an organic material, and covers the first protective film and at least above the ring in the active region and the terminal region. Further provided with a protective film.

According to the silicon carbide semiconductor device of the present disclosure, it is possible to further improve the reliability in a high temperature and high humidity bias environment.

FIG. 1A is a plan view showing a first embodiment of a silicon carbide semiconductor device. FIG. 1B is a plan view showing an active region and a terminal region in the silicon carbide semiconductor device shown in FIG. 1A. FIG. 1C is a plan view of an upper source electrode and an upper gate electrode of the silicon carbide semiconductor device shown in FIG. 1A. FIG. 1D is a plan view of a first protective film and a second protective film of the silicon carbide semiconductor device shown in FIG. 1A. FIG. 2A is a cross-sectional view of the silicon carbide semiconductor device in line AA'of FIG. 1A. FIG. 2B is a cross-sectional view of the silicon carbide semiconductor device in line BB'of FIG. 1A. FIG. 2C is a plan view showing the vicinity of the AA'line and the BB'line shown in FIG. 1A on the surface of the first silicon carbide semiconductor layer. FIG. 2D is a plan view showing the vicinity of the AA'line and the BB'line shown in FIG. 1A among the gate electrodes formed on the second silicon carbide semiconductor layer. FIG. 3 is a diagram showing the difference in off-leakage characteristics depending on the presence or absence of the second silicon carbide semiconductor layer on the FLR region. FIG. 4A shows the path of the charging current flowing through the first and second body regions when the silicon carbide semiconductor device is turned from on to off. FIG. 4B shows the path of the charging current flowing through the first and second body regions when the silicon carbide semiconductor device of the first embodiment is turned from on to off. FIG. 5A is a cross-sectional view of the second embodiment of the silicon carbide semiconductor device, corresponding to the line AA'of FIG. 1A. FIG. 5B is a cross-sectional view of the second embodiment of the silicon carbide semiconductor device, corresponding to the line BB'of FIG. 1A. FIG. 6A is a cross-sectional view of the third embodiment of the silicon carbide semiconductor device, corresponding to the line AA'of FIG. 1A. FIG. 6B is a cross-sectional view of the third embodiment of the silicon carbide semiconductor device, corresponding to the line BB'of FIG. 1A. FIG. 7A is a cross-sectional view of the fourth embodiment of the silicon carbide semiconductor device, corresponding to the line AA'of FIG. 1A. FIG. 7B is a cross-sectional view of the fourth embodiment of the silicon carbide semiconductor device, corresponding to the line AA'of FIG. 1A. FIG. 8A is a diagram showing the results of a THB test performed using the silicon carbide semiconductor device of Sample 1. FIG. 8B is a diagram showing the results of a THB test performed using the silicon carbide semiconductor device of Sample 2. FIG. 8C is a diagram showing the results of a THB test performed using the silicon carbide semiconductor device of Sample 3. FIG. 8D is a diagram showing the results of a THB test performed using the silicon carbide semiconductor device of Sample 4. FIG. 9A is a diagram showing the results of a THB test performed using the silicon carbide semiconductor device of Sample 5. FIG. 9B is a diagram showing the results of a THB test performed using the silicon carbide semiconductor device of Sample 6. FIG. 10A is a diagram showing the results of observing the silicon carbide semiconductor device of Sample 5 after the THB test. FIG. 10B is a diagram showing the results of observing the silicon carbide semiconductor device of Sample 5 after the THB test. FIG. 11A is a diagram showing the results of observing the silicon carbide semiconductor device of Sample 6 after the THB test. FIG. 11B is a diagram showing the results of observing the silicon carbide semiconductor device of Sample 6 after the THB test. FIG. 12A is a diagram showing the results of an HTRB test performed using the silicon carbide semiconductor device of Sample 1. FIG. 12B is a diagram showing the results of an HTRB test performed using the silicon carbide semiconductor device of Sample 2. FIG. 12C is a diagram showing the results of an HTRB test performed using the silicon carbide semiconductor device of Sample 3. FIG. 12D is a diagram showing the results of an HTRB test performed using the silicon carbide semiconductor device of Sample 4. FIG. 13 is a diagram showing the results of an HTRB test performed using the silicon carbide semiconductor device of Sample 5.

The inventor of the present application conducted a THB test on a semiconductor device according to a conventional technique to evaluate its reliability. The semiconductor device disclosed in Patent Document 1 includes a protective film made of an organic insulator that covers the entire chip. Further, the semiconductor device disclosed in Patent Document 2 includes a protective film having a two-layer structure composed of an inorganic protective film and an organic insulating film. When these semiconductor devices were manufactured and a storage test was conducted by applying a bias voltage of 1200 V at 85 ° C. and a relative humidity of 85%, it was confirmed that a decrease in the threshold voltage or a leak between the drain and the source occurred. rice field. It is considered that the decrease in the threshold voltage causes moisture or mobile ions to invade from the protective film and cause the threshold voltage to fluctuate. In addition, the leak between the drain and the source is caused by the silicon nitride film floating or cracking in the silicon nitride film, especially in the terminal region of the chip, and moisture or the like invading the semiconductor device from the protective film and causing a leak current to flow. It is considered to be.

Based on these findings, the inventor of the present application has conceived a silicon carbide semiconductor device having a novel protective structure. The outline of the silicon carbide semiconductor device of the present disclosure is as follows.

The silicon carbide semiconductor device of the present disclosure includes a first conductive type silicon carbide substrate including an active region and a terminal region surrounding the active region, a plurality of unit cells located in the active region, and a terminal located in the terminal region. A silicon carbide semiconductor device having a structure, each unit cell is selected on the surface of at least the silicon carbide substrate, the first silicon carbide semiconductor layer on the silicon carbide substrate, and the first silicon carbide semiconductor layer. The first body region of the second conductive type, the source region selectively formed in the first body region, and the gate insulating film located above the first silicon carbide semiconductor layer. A gate electrode located on the gate insulating film, a first contact region in contact with the first body region, and an inner peripheral upper source electrode electrically connected to the first contact region and the source region are included. The terminal structure is selectively formed on the surfaces of the silicon carbide substrate, the first silicon carbide semiconductor layer located on the silicon carbide substrate, and the first silicon carbide semiconductor layer, and surrounds the active region. A second conductive type second body region having a shape, at least one second conductive type ring located on the surface of the first silicon carbide semiconductor layer and surrounding the second body region, and the second body. A second conductive type second contact region selectively formed on the surface of the region, an interlayer insulating film located above the second contact region, and an interlayer insulating film located above the interlayer insulating film. And electrically connected to the second contact region, one or more outer peripheral upper source electrodes surrounding the active region, and electrically connected to the gate electrode, the inner peripheral upper part of the active region. The inner peripheral upper source electrode and the upper portion, including the upper gate electrode located between the source electrode and the outer peripheral upper source electrode, made of silicon nitride, excluding the pad region in the active region and the terminal region. It is composed of a gate electrode, a first protective film covering the inner surface of the outermost upper source electrode located on the innermost side of the one or more outer peripheral upper source electrodes, and an organic material, and in the active region and the terminal region. A second protective film that covers at least a part of the ring is further provided.

The one or more outer peripheral upper source electrodes and the inner peripheral upper source electrode may be electrically connected.

The outer surface of the first protective film may be located between the outermost outer peripheral upper source electrode located on the outermost side of the one or more outer peripheral upper source electrodes and the at least one ring.

The outer surface of the first protective film is located on the outermost outer peripheral upper source electrode located on the outermost side of the one or more outer peripheral upper source electrodes, and the outer peripheral upper source electrode of the one or more outer peripheral upper source electrodes. Of these, the outer surface of the outermost outer peripheral upper source electrode located on the outermost side may be in contact with the second protective film.

The termination structure comprises two or more of the rings, the first protective film covering at least the innermost ring of the rings and of the rings. It does not have to cover at least the outermost ring.

The termination structure comprises three or more of the rings, the first protective film covering above two or more of the rings, including the innermost ring, and Of the plurality of rings, it is not necessary to cover at least the outermost ring.

In the cross section perpendicular to the extending direction of the plurality of rings, in the cross section perpendicular to the extending direction of the plurality of rings, the distance W between the inner surface of the innermost ring and the outer surface of the outermost ring is 60 μm or more and 120 μm or less. In the cross section, the distance between the outer surface of the first protective film and the outer surface of the innermost ring may be 18 μm or more and 50 μm or less.

The silicon carbide substrate has a scribe line region, and the second protective film does not have to cover the scribe line region.

The terminal structure is located on the inner peripheral surface of the second contact region and is electrically in contact with the first base electrode, and is located on the outer peripheral surface of the second contact region and is electrically connected. The first base electrode is electrically connected to the inner peripheral upper source electrode, and the second base electrode is electrically connected to the outer peripheral upper source electrode. It may be electrically connected.

The second base electrode may surround the active region on the surface of the second contact region.

The termination structure may include a plurality of first base electrodes having an island shape.

On the surface of the first silicon carbide semiconductor layer, a third contact region located outside the ring and selectively formed so as to surround the ring is in electrical contact with the third contact region. A third base electrode that is connected to the third base electrode and a seal electrode that is connected to the third base electrode and surrounds the outermost ring of the rings may be further provided.

The second protective film may cover the seal electrode.

(First Embodiment)
Hereinafter, embodiments of the silicon carbide semiconductor device of the present disclosure will be described with reference to the drawings.

1A is a plan view of the silicon carbide semiconductor device 201 of the present embodiment, and FIGS. 2A and 2B are cross-sectional views of the silicon carbide semiconductor device 201 on the AA'line and the BB' line shown in FIG. 1A, respectively. It is a figure. FIG. 2C is a plan view showing the vicinity of the AA'line and the BB'line shown in FIG. 1A on the surface of the first silicon carbide semiconductor layer 102, which will be described later.

The silicon carbide semiconductor device 201 includes a first conductive type silicon carbide substrate 101 and a first silicon carbide semiconductor layer (drift layer) 102 located on the main surface of the silicon carbide substrate 101. A drain electrode 110 and a wiring electrode 113 arranged on the drain electrode 110 are located on the back surface of the silicon carbide substrate 101. In the present embodiment, the first conductive type is n-type and the second conductive type is p-type. However, the first conductive type may be p-type and the second conductive type may be n-type.

The silicon carbide substrate 101 includes an active region 100A and a terminal region 100E. FIG. 1B schematically shows the arrangement of these regions as viewed from the direction perpendicular to the main surface of the silicon carbide substrate 101. As shown in FIG. 1B, the termination region 100E surrounds the active region 100A. The silicon carbide substrate 101 further includes a scribe line region 100S located on the outside so as to surround the terminal region 100E. The scribe line region is a cutting margin when the wafer is diced and divided into chips, and no metal is arranged here.

The silicon carbide semiconductor device 201 includes a plurality of unit cells 100u located in the active region 100A. Each of the plurality of unit cells 100u functions as a MOSFET (metal-oxide-semiconductor field-effect transistor) and is connected in parallel to each other. That is, a transistor is configured in the unit cell 100u, and the silicon carbide semiconductor device 201 includes a plurality of transistors. The plurality of unit cells 100u are arranged two-dimensionally when viewed from the direction perpendicular to the main surface of the silicon carbide substrate 101.

Each unit cell 100u is selected on the surfaces of the first conductive type silicon carbide substrate 101, the first conductive type first silicon carbide semiconductor layer 102 located on the silicon carbide substrate 101, and the first silicon carbide semiconductor layer 102. The first body region 103 of the second conductive type, the source region 104 selectively formed on the surface of the first body region 103, and the gate insulation located above the first silicon carbide semiconductor layer 102. A film 107 and a gate electrode 108 located on the gate insulating film 107 are provided. In the present embodiment, the second silicon carbide semiconductor layer 106 is provided as a channel layer between the first silicon carbide semiconductor layer 102 and the gate insulating film 107.

In the first silicon carbide semiconductor layer 102, the source region 104 contains a first conductive type impurity at a high concentration (n ⁺ type). Due to the electrical connection to the first body region 103, the second conductive type first contact region 105 containing the second conductive type impurities at a higher concentration than the first body region 103 is in the source region 104. It is provided below the source region 104 at a position in contact with the first body region 103. Further, on the surface of the first silicon carbide semiconductor layer 102, a source electrode 109 electrically connected to the source region 104 and the first contact region 105 by ohmic contact is provided. Therefore, the first body region 103 is electrically connected to the source electrode 109 via the first contact region 105.

The first body region 103, the source region 104, and the first contact region 105 activate, for example, the step of injecting impurities into the first silicon carbide semiconductor layer 102 and the impurities injected into the first silicon carbide semiconductor layer 102. It is formed by a high temperature heat treatment (activation annealing) step. The source electrode 109 can be formed, for example, by forming, for example, a conductive material (Ni) layer on the source region 104 and the first contact region 105 of the first silicon carbide semiconductor layer 102, and then heat-treating at a high temperature.

The source region 104 and the first silicon carbide semiconductor layer 102 are connected via the second silicon carbide semiconductor layer 106. The second silicon carbide semiconductor layer 106 is, for example, a 4H-SiC layer formed on the first silicon carbide semiconductor layer 102 by epitaxial growth, and is doped with first conductive type impurities. The thickness of the second silicon carbide semiconductor layer 106 may be, for example, 75 nm or less, and the doping concentration may be 1 × 10 ¹⁸ cm ^-3 or more.

The second silicon carbide semiconductor layer 106 may have a two-layer structure including the above-mentioned first conductive type impurity layer having a doping concentration and an undoped layer provided on the impurity layer. The thickness of the second silicon carbide semiconductor layer 106 may be reduced due to the formation of sacrificial oxidation or gate oxidation during the manufacturing process of the silicon carbide semiconductor device 201. If the amount of decrease in the thickness of the second silicon carbide semiconductor layer 106 varies, the electrical characteristics of the silicon carbide semiconductor device 201, such as the threshold voltage in the forward direction and the rising voltage in the reverse direction, vary. If the second silicon carbide semiconductor layer 106 includes an undoped layer, even if the thickness of the undoped layer is mainly reduced due to the formation of sacrificial oxidation or gate oxidation, the impurity layer containing the first conductive type impurities remains as it is. The characteristics are less likely to fluctuate.

Further, the second silicon carbide semiconductor layer 106 may have a three-layer structure including a first conductive type low-concentration impurity layer located on the first silicon carbide semiconductor layer 102 side, in addition to the above-mentioned two-layer structure. For example, the doping concentration of the first conductive type low-concentration impurity layer is 1 × 10 ¹⁷ cm ^-3 or less. By adopting such a structure, it is possible to reduce the variation in the impurity concentration due to the unstable growth rate at the initial stage of the epitaxial growth of the second silicon carbide semiconductor layer 106.

It is preferable that the second silicon carbide semiconductor layer 106 is not provided on the FLR region 100F of the terminal region described later. For example, it is preferable to remove the second silicon carbide semiconductor layer 106 in the FLR region 100F after forming the second silicon carbide semiconductor layer 106 on the first silicon carbide semiconductor layer 102. Since the second silicon carbide semiconductor layer has the first conductive type, the region in contact with the ring 120 having the second conductive type is depleted to generate a positive space charge. This is because the positive space charge makes it difficult for the depletion layer to extend from the ring in the FLR region to the first silicon carbide semiconductor layer, and the withstand voltage is lowered. FIG. 3 shows the difference in Id-Vd characteristics in the off state depending on the presence or absence of the second silicon carbide semiconductor layer on the FLR region 100F. It can be seen that the magnitude of the leakage current does not change when the second silicon carbide semiconductor layer on the FLR region 100F is removed, but the withstand voltage is higher. The removal of the second silicon carbide semiconductor layer can be performed by, for example, dry etching.

The source region 104 and the first contact region 105 form ohmic contact with the source electrode 109, respectively. By applying the gate voltage, an inversion layer serving as a channel can be formed in the vicinity of the surface of the first body region 103 to operate the transistor.

The gate insulating film 107 is, for example, a thermal oxide film (SiO ₂ film) formed by thermally oxidizing the surface of the second silicon carbide semiconductor layer 106. The gate electrode 108 is formed using, for example, conductive polysilicon.

The interlayer insulating film 111 is located on the first silicon carbide layer 102 or the second silicon carbide layer so as to cover the gate electrode 108 in the active region 100A and the terminal region 100E, the gate insulating film 107 in the terminal region 100E, and the like. Therefore, the gate electrode 108 is covered with the interlayer insulating film 111. Further, in the terminal region 100E, the interlayer insulating film is located above the second contact region 116. An opening 111c is formed in the interlayer insulating film 111, and the source electrode 109 in each unit cell is connected in parallel to the upper source electrode (for example, Al electrode) 112 via the opening 111c. As will be described later, of the upper source electrode 112, a portion located in a part of the active region 100A and the terminal region 100E is referred to as an inner peripheral upper source electrode 112F.

The silicon carbide semiconductor device 201 has a terminal structure 100e in the terminal region 100E. Silicon carbide semiconductors have a dielectric breakdown electric field strength that is 10 times or more higher than that of Si. Therefore, in a silicon carbide semiconductor device, it is important to suppress dielectric breakdown due to electric field concentration in the surface structure of the semiconductor device, and the terminal structure 100e relaxes the electric field concentration on the surface of the semiconductor device. The unit cell 100u that operates as a transistor is not provided in the terminal region 100E.

The terminal structure 100e includes a silicon carbide substrate 101 and a first silicon carbide semiconductor layer 102 located on the main surface of the silicon carbide substrate 101 in the terminal region 100E. Further, the terminal structure 100e is selectively formed on the surface of the first silicon carbide semiconductor layer 102, and is selectively formed on the surfaces of the second conductive type second body region 115 surrounding the active region 100A and the second body region 115. Includes a second conductive type second contact region 116 formed in. The concentration of the second conductive type impurities in the first body region is, for example, 1 × 10 ¹⁷ cm ^-3 to 1 × 10 ¹⁹ cm ^-3 , and the concentration of the second conductive type impurities in the second body region is, for example, 1 × 10 ¹⁹ cm. ^-3 to 1 x 10 ²¹ cm ^-3 . The second contact region 116 also surrounds the active region 100A like the second body region 115. The second body region 115 may have the same impurity concentration profile as the first body region 103 in the depth direction. Similarly, the second contact region 116 may have the same impurity concentration profile as the first contact region 105 in the depth direction. That is, the second body region 115 may be formed by the same process as the first body region 103, and the second contact region 116 may be formed by the same process as the first contact region 105.

The terminal structure 100e includes a plurality of base electrodes including a first base electrode 119a and a plurality of second base electrodes 119b and 119c. The base electrodes 119a, 119b, and 119c are formed on the surface of the first silicon carbide semiconductor layer 102 so as to come into contact with the second contact region 116. The first base electrode 119a is located in a region on the inner peripheral side (left side in the drawing) close to the active region 100A in the second contact region 116 of the terminal region 100E. FIG. 2C is a drawing showing a semiconductor layer and electrodes located in the vicinity of the AA'and BB'parts of FIG. 1A in the silicon carbide semiconductor device and below the gate oxide film. Therefore, FIG. 2C does not include the interlayer insulating film, the gate insulating film, the upper electrode, and the gate electrode. As shown in FIG. 2C, on the surface of the first silicon carbide semiconductor layer 102, the first base electrode 119a is formed in an island shape, and is arranged in the same manner as the source electrode 109 in the active region 100A, for example. On the other hand, the second base electrodes 119b and 119c are located outside the outer peripheral edge of the gate electrode 108, which will be described later, on the outer peripheral side (right side in the drawing) of the second contact region 116, and surround the active region 100A. .. That is, it has a ring shape when viewed from the direction perpendicular to the main surface of the silicon carbide substrate 101. In this embodiment, the termination structure 100e includes two second base electrodes 119b and 119c having a ring shape. The second base electrode 119c located on the outer side of the active region 100A surrounds the second base electrode 119b located on the inner side. The number of ring-shaped second base electrodes may be one, or may be three or more. The base electrodes 119a, 119b, and 119c can be formed, for example, by forming a conductive material (Ni) layer on the second contact region 116 of the first silicon carbide semiconductor layer 102 and then heat-treating at a high temperature. It can be formed of the same material as 109.

In the terminal region 100E, the second silicon carbide semiconductor layer 106 and the gate insulating film 107 are located on the first silicon carbide semiconductor layer 102. Further, in the terminal region 100E, the gate electrode 108 is also located on the gate insulating film 107 in order to provide the upper gate electrode. Further, the interlayer insulating film 111 is located so as to cover the gate electrode 108. These components are contiguous with the corresponding components in the active region 100A.

FIG. 2D is a diagram showing the positional relationship between the gate electrode 108 formed on the second silicon carbide semiconductor layer 106, the lower semiconductor layer, the source electrode, and the base electrode in the region of FIG. 2C. In the active region 100A, the gate electrode 108 is provided on the gate insulating film 107 in the form of a network structure except for the source electrode 109 and the base electrode 119a. The gate electrodes between the adjacent unit cells 100u are connected to each other. Therefore, as shown in FIGS. 2A and 2D, in the AA'line cross section crossing the source electrode 109, the gate electrode 108 is divided at the position of the source electrode 109. On the other hand, as shown in FIGS. 2B and 2D, in the BB'line cross section not crossing the source electrode 109, the gate electrode 108 is continuous in the active region 100A.

An opening 111d is formed in the interlayer insulating film 111, and the base electrodes 119a, 119b, and 119c are connected to the upper source electrode 112 via the opening 111d. As will be described later, the portion of the upper source electrode 112 connected to the ring-shaped second base electrode 119b and 119c is referred to as the outer peripheral upper source electrode 112H. The outer peripheral upper source electrode 112H has a ring shape corresponding to the second base electrodes 119b and 119c. On the other hand, of the upper source electrode 112, the portion located in the active region 100A and the portion 112a connected to the first base electrode 119a are referred to as the inner peripheral upper source electrode 112F. In FIG. 2, the outer peripheral upper source electrodes 112Hb and 112Hc corresponding to the second base electrodes 119b and 119c are located. In the present embodiment, the outer peripheral upper source electrodes 112Hb and 112Hc are connected, but may be separated. That is, the termination structure has one or more outer peripheral upper source electrodes 112H. When there is one outer peripheral upper source electrode 112H, the outermost outer peripheral upper source electrode 112H refers to the one outer peripheral upper source electrode 112H.

Similarly, an opening 111 g is formed in the interlayer insulating film, and the gate electrode 108 is connected to the upper gate electrode 114 via the opening 111 g. The upper gate electrode 114 is, for example, an Al electrode, and can be formed by the same process as the upper source electrode 112.

The termination structure 100e is located on the surface of the first silicon carbide semiconductor layer 102 and has at least one second conductive ring 120 in the FLR region 100F surrounding the second body region 115. The first silicon carbide semiconductor layer is composed of, for example ^{, n-type silicon carbide having an impurity concentration of 1 × 10 15} to 1 × 10 ¹⁶ cm ^-3 , and the second conductive type ring has an ^{impurity concentration of 1 × 10 17} to 1 × 10 ¹⁹ cm ^-3 . It consists of p-type silicon carbide. The second conductive type ring is usually selectively formed by ion implantation on the surface of the first silicon carbide semiconductor layer by ion implantation, but the same impurities as the first body region and the second body region of the terminal region of the unit cell. It may be a concentration, and in this case, it may be formed simultaneously by the same ion implantation step. The p-shaped ring 120 has a ring shape surrounding the second body region 115 located outside the active region 100A when viewed from a direction perpendicular to the surface of the silicon carbide substrate 101. In this embodiment, a plurality of rings 120 are provided to form an FLR structure. Specifically, when viewed from the direction perpendicular to the surface of the silicon carbide substrate 101, each of the plurality of rings 120 has a ring shape surrounding the active region 100A, and the entire plurality of rings 120 have a nested structure. doing. That is, the inner ring 120 is surrounded by the outer ring 120.

Further, when viewed from a direction perpendicular to the surface of the silicon carbide substrate 101, each ring has a quadrangular shape with four corners rounded in an arc shape. Since the four corners of the ring are rounded in an arc shape, it is possible to prevent the electric field from concentrating on the four corners. For example, the ring 120 may have the same impurity concentration profile in the depth direction as the first body region 103 and the second body region 115 of the active region 100A.

FIG. 1C is a plan view of the upper source electrode 112 and the upper gate electrode 114 as viewed from the main surface of the silicon carbide substrate 101. The dotted line d1 indicates the position of the boundary between the inner peripheral upper source electrode 112F and the outer peripheral upper source electrode 112H. Of the upper source electrode 112, the portion located within the region indicated by the dotted line d1 is the inner peripheral upper source electrode 112F, and the portion located outside the region indicated by the dotted line d1 is the outer peripheral upper source electrode 112H. The inner peripheral upper source electrode 112F and the outer peripheral upper source electrode 112H are connected to each other and are electrically connected to each other. As shown in FIG. 1C, the outer peripheral upper source electrodes 112Hb and 112Hc are located outside the upper gate electrode 114, and the upper gate electrode 114 is located between the inner peripheral upper source electrode 112F and the outer peripheral upper source electrode 112H. doing. In the present embodiment, the outer peripheral upper source electrode 112Hb and the outer peripheral upper source electrode 112Hc constitute the outer peripheral upper source electrode 112H.

The silicon carbide semiconductor device 201 includes a first protective film 125 and a second protective film 126 in order to protect the internal structure from the external environment. FIG. 1D is a plan view of the second protective film 126 as viewed from the main surface of the silicon carbide substrate 101. In FIG. 1D, the outline of the first protective film 125 is shown by a thick dotted line. As shown in FIGS. 1A, 1D, 2A and 2B, the first protective film 125 covers the entire inner peripheral upper source electrode 112F in the active region 100A and the terminal region 100E, except for the pad regions 112P and 114P. It covers the entire upper gate electrode 114 and at least the entire inner surface 112Hi of the outer peripheral upper source electrode 112H. When there are a plurality of outer peripheral upper source electrodes 112H, the first protective film 125 includes the entire inner peripheral upper source electrode 112F, the entire upper gate electrode 114, and the entire inner side surface 112Hi of the outermost outer peripheral upper source electrode 112H. Covering. Here, the pad region is an region in which a wire, a ribbon, or the like is connected in order to connect to the terminal of the package among the inner peripheral upper source electrode and the upper gate electrode, and is an region in which the protective film is opened. In the present embodiment, the first protective film 125 covers the inner side surface 112Hi and the outer side surface 112Hj of the outer peripheral upper source electrode 112H. That is, the first protective film 125 covers the outer peripheral upper source electrode 112H. In this case, it is preferable that the first protective film 125 does not cover at least the outermost ring 120. That is, the outer surface 125j of the first protective film 125 is located in the second body region 115 and is between the outermost outer peripheral upper source electrode 112H and the ring 120, which are located on the outermost side of the plurality of outer peripheral upper source electrodes 112H. positioned. That is, the first protective film 125 does not cover the uppermost ring 120 in the present embodiment.

The second protective film 126 continuously covers the first protective film 125 and at least a part above the ring 120 in the active region 100A and the terminal region 100E. Preferably, the second protective film 126 covers the main surface of the silicon carbide substrate 101 except for the scribe line region 100S. Since the first protective film 125 is not located in the pad areas 112P and 114P, the second protective film 126 covers the inner side surface 125i of the first protective film 125 in the pad areas 112P and 114P and covers the pad areas 112P and 114P. 114P is exposed. In the present embodiment, the inner peripheral upper source electrode 112F, the upper gate electrode 114, and the outer peripheral upper source electrode 112H are not in direct contact with the second protective film 126.

The first protective film 125 is preferably made of a dense inorganic material. Specifically, the first protective film 125 is made of silicon nitride. The silicon nitride film is dense and has an excellent barrier property against moisture. In particular, a silicon nitride film formed by the plasma CVD method can be suitably used as the first protective film. The thickness of the first protective film 125 is, for example, 0.2 μm to 2 μm.

On the other hand, the second protective film 126 is preferably made of an organic material. For example, the second protective film 126 is made of a polyimide resin, a polybenzoxazole resin, an acrylic resin, or the like. The thickness of the second protective film 126 is, for example, 3 μm to 20 μm.

For the first protective film 125, for example, after forming the upper source electrode 112 and the upper gate electrode 114, the silicon nitride film is formed by a plasma CVD method, and the silicon nitride film is patterned so that the pad regions 112P and 114P are exposed. It can be formed by doing. Further, the second protective film 126 is formed, for example, by applying the above-mentioned organic material or spin coating on a wafer on which a plurality of silicon carbide semiconductor devices 201 are formed after the formation of the first protective film 125. It can be formed by forming a film of the organic material and patterning the film of the organic material so that the pad regions 112P and 114P and the silicon line region 100S are exposed. Alternatively, the second protective film 126 on the scribe line region 100S may be removed by a dicing blade or the like.

The silicon carbide semiconductor device 201 can be manufactured according to the same procedure as that of a general semiconductor device, using the elemental techniques in the manufacture of the semiconductor device described in accordance with the description of each component.

In the silicon carbide semiconductor device 201 having the above-described structure, the first protective film 125 covers the pad regions 112P and 114P so as to cover the inner side surface 112Hi of the outer peripheral upper source electrode 112H located in the terminal region 100E surrounding the active region 100A. Except for this, it covers the inner peripheral upper source electrode 112F and the upper gate electrode 114.

Further, the outer peripheral upper source electrode 112H penetrates the interlayer insulating film 111 from above the interlayer insulating film 111 and is connected to the base electrode 119 located in the second contact region 116 in the first silicon carbide semiconductor layer 102. That is, the outer peripheral upper source electrode 112H is a continuous single structure extending from the upper surface of the interlayer insulating film 111 to the first silicon carbide semiconductor layer 102. Generally, a semiconductor device is configured by laminating thin film structures, so that water or the like easily penetrates between the thin film layers from the outside. In this respect, the outer peripheral upper source electrode 112H is continuous from the first silicon carbide semiconductor layer 102 to the upper surface of the interlayer insulating film 111 in a direction perpendicular to the main surface of the silicon carbide substrate 101, and is active. Since the region 100A is continuously enclosed, the active region 100A is sealed from the side.

Therefore, the plurality of unit cells 100u, the inner peripheral upper source electrode 112F and the upper gate electrode 114 in the active region 100A inside the outer peripheral upper source electrode 112H are effective by the combination of the outer peripheral upper source electrode 112H and the first protective film 125. Is sealed. The number of the base electrode located on the outer periphery of the second body region, the opening of the interlayer insulating film connected to the base electrode, and the outer peripheral upper source electrode 112Hb or 112Hc formed by embedding the base electrode may be one, but it is more effective to have a plurality of them. .. Since the outer peripheral upper source electrode 112H of the present embodiment is connected to the first silicon carbide semiconductor layer 102 via the base electrodes 119 (119b and 119c) at a plurality of locations, the sealing structure is multiplexed and high. A sealing effect can be obtained. That is, since the silicon nitride constituting the first protective film 125 and the metal constituting the electrode are excellent in barrier properties against moisture, the silicon carbide semiconductor device 201 is provided with moisture by providing the first protective film 125 in the above-mentioned region. Invasion can be effectively suppressed.

On the other hand, the second protective film 126 covers the first protective film 125 and is provided on the entire main surface side of the silicon carbide semiconductor device 201 excluding the scribe line region 100S and the pad regions 112P and 114P. Since the second protective film 126 is made of an organic material, its barrier property against moisture is lower than that of silicon nitride. However, the hardness of the organic material is smaller than that of silicon nitride, and even if stress is applied from the outside, it is less likely to crack or crack, and it is less likely to lift or peel off.

Therefore, when the silicon carbide semiconductor device 201 is housed in the package, even if stress is generated in the FLR region 100F due to the curing of the mold resin, the second protective film 126 may be cracked or lifted in the FLR region 100F. It is suppressed. As will be described later, even when a two-layer structure composed of the first protective film 125 and the second protective film 126 is provided in the FLR region 100F, the first protective film 125 is cracked and lifted.

The electric field from the first silicon carbide semiconductor layer 102 leaks from the surface of the FLR region 100F. The region where the cracks and lifts occur is filled with the atmosphere, but the dielectric breakdown electric field in the atmosphere is lower than that of the first protective film 125 and the second protective film 126, and the first silicon carbide semiconductor layer in the region where the cracks and lifts occur. Leakage current tends to flow due to the leakage electric field from 102. Moisture that has entered the cracked or lifted area can also cause a leak current. On the other hand, according to the silicon carbide semiconductor device 201, since the first protective film 125 is not located in the FLR region 100F, it is possible to suppress a decrease in reliability due to cracks or the like generated in the first protective film 125.

As described above, the silicon carbide semiconductor device 201 of the present embodiment not only includes the first protective film 125 and the second protective film 126, but as described above, the outer peripheral upper source electrode 112H in the terminal region 100E , And an appropriate spatial arrangement of the outer peripheral upper source electrode 112H and the first protective film 125 and the second protective film 126 realizes a highly airtight structure.

On the other hand, the semiconductor device disclosed in Patent Document 2 has a structure in which a two-layer structure of an inorganic protective film and an organic protective film covers the entire semiconductor device, or the inorganic protective film has only a gate metal wiring and a source electrode pad. It has a structure in which a covering and an organic protective film covers the entire semiconductor device, and does not have a combination of a structure penetrating an interlayer insulating film in a terminal structure and an inorganic protective film. That is, Patent Document 2 only discloses that the gate metal wiring and the source electrode pad are individually covered with an inorganic protective film, and also discloses a structure that airtightly protects the entire semiconductor device using the inorganic protective film. I haven't done it.

Further, according to the silicon carbide semiconductor device 201, the charge / discharge current generated in the depletion layer during the high-speed switching operation can be passed through the upper source electrode, whereby the potential of the second body region 115 rises and the gate caused by the increase. Destruction of the insulating film 107 can be suppressed. This feature will be described below.

Normally, in a circuit such as an inverter, a load is connected in series with the silicon carbide semiconductor device, and when the gate of the silicon carbide semiconductor device is turned on and a current is flowing through the load, a voltage is generated across the load. Therefore, the power supply voltage Vcc is distributed between the silicon carbide semiconductor device and the load. When the gate of the silicon carbide semiconductor device is turned off, no current flows, so no voltage is generated in the load, and the entire power supply voltage Vcc is applied to the silicon carbide semiconductor device. That is, Vcc is applied to the drain of the silicon carbide semiconductor device. At this time, the PN junction consisting of the body region and the first silicon carbide semiconductor layer (drift region) in each unit cell in the active region of the silicon carbide semiconductor device, and the body region and the first silicon carbide semiconductor layer in the terminal region The PN junction composed of the above is in a reverse biased state, and the depletion layer spreads on both sides of the body region and the first silicon carbide semiconductor layer. Since the depletion layer spreads, holes flow to the outside in the body region (p-type semiconductor region), and a negative space charge layer is formed. In the case of the first silicon carbide semiconductor layer (n-type semiconductor region), electrons flow to the outside and a positive space charge layer is formed. Therefore, when the silicon carbide semiconductor device is turned from on to off, a charging current using the depletion layer as a capacitor flows, and conversely, when the silicon carbide semiconductor device is turned from off to on, the charge charged in the depletion layer flows in the opposite direction as a discharge current.

The charge q of the depletion layer is expressed by the following equation. Here, C is the capacitance of the depletion layer, and V is the reverse bias voltage applied to the pn junction.
q = CV

The charge / discharge current I can be obtained by differentiating both sides.
I = dq / dt = C · dV / dt

Therefore, the larger the dV / dt, that is, the higher the switching speed, the larger the charge / discharge current. Conversely, high-speed switching of MOSFETs cannot be realized unless the charge / discharge current is large.

As described above, the silicon carbide semiconductor device has a pn junction in the active region and a pn junction in the terminal region. FIG. 4A shows the path of the charging current flowing through the body region when the silicon carbide semiconductor device is turned from on to off. Since the resistance of the body region formed by injecting or diffusing impurities into the silicon carbide semiconductor layer is generally high, when a charging current flows, the resistance of the current and the current path in the body region (electrode contact resistance + resistance of the body region). A potential rise that is determined by the product of As the current path in the body region becomes longer, the resistance of the current path also increases, so that the larger the body region, the larger the potential generated. As a result, an excessive voltage is applied to the gate insulating film sandwiched between the body region and the gate electrode, and the gate insulating film may be destroyed.

Normally, the size of the unit cell in the active region is about 5 μm to 10 μm, and the body region is also small. Therefore, the capacity of the depletion layer is small and the charging current is also small. Further, since the current path is short and the resistance is small, the generation of charging current and the increase in potential in the body region due to the on / off of the silicon carbide semiconductor device described above are often not a problem. On the other hand, since the body region located in the terminal region usually has a size of about several tens of μm, the charging current is large and the current path is long. As a result, the potential rise is large in the body region, and the possibility that the gate insulating film is broken is higher than in the active region. In particular, the gate insulating film is liable to break when the silicon carbide semiconductor device switches at high speed.

In the structure shown in FIG. 4A, in the terminal region 100E, only the island-shaped base electrode 119a close to the active region 100A exists in the second contact region 116 in the second body region 115. Therefore, the position p1 outside the second body region 115 farthest from the base electrode 119a has the highest potential. Since the pn junction charging current path from the position p1 to the base electrode 119a has the full width L of the ring shape of the second body region 115, it has a high resistance and a high voltage.

On the other hand, as shown in FIG. 4B, according to the silicon carbide semiconductor device 201 of the present embodiment, the terminal structure 100e is close to the active region 100A in the ring-shaped second body region 115 surrounding the active region 100A. It has a first base electrode 119a located on the inner peripheral side and a second base electrode 119b and 119c located on the outer peripheral side. The first base electrode 119a is connected to the inner peripheral upper source electrode 112A, and the second base electrodes 119b and 119c are connected to the outer peripheral upper source electrode 112H. Therefore, in the cross section crossing the ring shape of the second body region 115, the position where the potential is highest due to the charging current is the position p2 substantially in the middle between the base electrodes 119a and the base electrodes 119b and 119c. At position p2, the charging current generated by the pn junction between the second body region 115 and the first silicon carbide semiconductor layer 102 is the first base electrode 119a or the second base electrode 119b via a path having a length of about L / 2. It flows from 119c to the inner peripheral upper source electrode 112A or the outer peripheral upper source electrode 112H. That is, in the second body region 115, even at the position p2 farthest from the first base electrode 119a or the second base electrode 119b or 119c which becomes the ground potential, the first base electrode 119a or the second base electrode 119b 119c The distance from is L / 2. That is, the potential increase at the position p2 in the silicon carbide semiconductor device 201 in FIG. 4B can be suppressed to about half as compared with the position p1 in FIG. 4A. Therefore, even if the silicon carbide semiconductor device 201 is operated at high speed, the effect that the gate insulating film is not easily broken can be obtained.

(Second Embodiment)
A second embodiment of the silicon carbide semiconductor device of the present disclosure will be described. 5A and 5B are cross-sectional views corresponding to the lines AA'and BB'shown in FIG. 1A of the silicon carbide semiconductor device 202 of the present embodiment.

The silicon carbide semiconductor device 202 is the first in that the outer surface 112Hj of the outermost outer peripheral upper source electrode 112Hc located on the outermost side of the one or more outer peripheral upper source electrodes 112H is not covered with the first protective film 125. It is different from the silicon carbide semiconductor device 201 of the embodiment.

Of the outer peripheral upper source electrodes 112Hb and 112Hc located outside the upper gate electrode 114, the inner side surface 112Hi is entirely covered with the first protective film 125, but the outermost outer peripheral upper source electrode 112Hc is located on the outermost side. The outer surface 112Hj of the above is not covered with the first protective film 125. The outer surface 125j of the first protective film 125 is located on the outermost outer peripheral upper source electrode 112H located on the outermost side. Therefore, the outer surface 112Hj is in contact with the second protective film 126.

As will be described later, it has been found that a large stress is also applied to the vicinity of the outer surface 112Hj of the outer peripheral upper source electrode 112Hc located on the outermost side of the outer peripheral upper source electrode 112H due to the curing of the mold resin described above. Further, the internal stress of the first protective film 125 also tends to be high at the edge portion. In particular, it was found that cracks were likely to occur at the outer upper edge of the outer peripheral upper source electrode 112Hc. According to the silicon carbide semiconductor device 202, the vicinity of the outer surface 112Hj of the outer peripheral upper source electrode 112Hc is not covered with the first protective film 125, but is covered only with the second protective film 126, so that the stress generated during curing of the mold resin causes the stress. It is possible to protect the first protective film 125 with the second protective film 126, which is resistant to stress, while suppressing the occurrence of cracks and the like.

Similar to the first embodiment, the first protective film 125 excludes the pad regions 112P and 114P so as to cover the entire inner side surface 112Hi of the outer peripheral upper source electrode 112H located in the terminal region 100E surrounding the active region 100A. It covers the inner peripheral upper source electrode 112F and the upper gate electrode 114. Therefore, as described in the first embodiment, the active region 100A can be effectively sealed by the inner peripheral upper source electrode 112F, the first protective film 125, and the outer peripheral upper source electrode 112H. Therefore, according to the silicon carbide semiconductor device 202, in addition to the effect of the silicon carbide semiconductor device 201 of the first embodiment, cracks and the like are more effectively suppressed in the first protective film 125 to improve reliability. be able to.

(Third Embodiment)
A third embodiment of the silicon carbide semiconductor device of the present disclosure will be described. 6A and 6B are cross-sectional views corresponding to the lines AA'and BB'shown in FIG. 1A of the silicon carbide semiconductor device 203 of the present embodiment.

In the silicon carbide semiconductor device 203, the silicon carbide semiconductor device 201 and the silicon carbide semiconductor device 201 of the first embodiment are provided in that the first protective film 125 covers at least the upper side of the ring 120 located on the innermost side of the plurality of rings 120. It is different from the semiconductor device 202 of the second embodiment.

As shown in FIGS. 6A and 6B, the first protective film 125 includes a plurality of inner peripheral upper source electrodes 112F and upper gate electrodes 114 in the active region 100A and the terminal region 100E, except for the pad regions 112P and 114P. It covers at least the innermost ring 120 of the rings 120. That is, the first protective film 125 projects outward from the entire active region 100A excluding the pad regions 112P and 114P to at least above the innermost ring 120. In this embodiment, the first protective film 125 covers a plurality of rings 120 including the innermost ring 120. The first protective film 125 does not cover at least the outermost ring 120. That is, the first protective film 125 covers only a part of the inner ring 120 among the plurality of rings.

When the inventor of the present application simulated the electric field in the FLR region 100F, the electric field was high at the outer peripheral end of each ring in the FLR region 100F. In particular, the electric field at the outer peripheral end of the innermost ring was the highest, and the electric field from the second ring from the inner to the ring located around the center of the FLR region 100F was lower than this, but about the same. It was found that the electric field was lower in the ring located from the center of the FLR region to the outside than in the inside, and the electric field gradually decreased toward the outside.

When a reverse bias is applied to the silicon carbide semiconductor device, the largest electric field is structurally applied to the innermost ring among the plurality of rings. On the other hand, since the second protective film is made of an organic material such as a resin, the second protective film 126 may contain movable ions depending on the type of the organic material. Further, as compared with the silicon nitride constituting the first protective film 125, the organic resin constituting the second protective film 126 is not dense, so that movable ions and moisture easily invade from the outside. In this case, the movable ions that have entered the second protective film 126 move according to the electric field leaking from the semiconductor layer while the silicon carbide semiconductor device is stored at a high temperature and a reverse bias is applied, and the innermost ring. It moves to the vicinity, changes the shape of the depletion layer in the FLR region 100F, and increases the drain leak current when a reverse bias is applied. This invasion and movement of mobile ions is more likely to occur at high temperatures. As a result, the drain leakage current tends to increase, especially when the silicon carbide semiconductor device is stored under a high temperature reverse bias. That is, the increase in drain leakage current due to the above causes is more likely to occur in the high temperature reverse bias test (HTRB) conducted in the atmosphere at a temperature of 150 to 200 ° C. than in the high temperature and high humidity bias test (THB) at a temperature of 85 ° C. and a humidity of 85%. ..

On the other hand, since silicon nitride is a dense material, it is unlikely that movable ions invade the first protective film 125 and move within the first protective film 125.

Therefore, in the silicon carbide semiconductor device 203 of the present embodiment, in such a case, the first protective film 125 covers at least the upper side of the innermost ring 120, so that movable ions are accumulated in the vicinity of the innermost ring 120. It is possible to suppress the occurrence of the leak path when the above-mentioned reverse bias is applied.

However, when only the innermost ring 120 is covered with the first protective film 125, movable ions move to the vicinity of the second ring 120 from the inside, which is not covered by the first protective film 125, and the leak path when reverse bias is applied is established. May form. Therefore, it is preferable that the first protective film 125 covers a plurality of rings 120 including the innermost ring 120. In the embodiments shown in FIGS. 6A and 6B, the first protective film 125 covers the three rings 120. For example, in a silicon carbide semiconductor device actually manufactured, when the terminal structure 100e includes 25 rings, the first protective film 125 may cover about 10 rings. With this structure, the influence of moving ions can be more reliably suppressed, and the reliability of the silicon carbide semiconductor device in storage under high temperature reverse bias can be improved.

Further, when only the innermost ring 120 is covered with the first protective film 125, the margin of the position of the outer surface 125j of the first protective film 125 at the time of manufacturing the silicon carbide semiconductor device is small. As a result, misalignment occurs, and reliability can be significantly reduced when a silicon carbide semiconductor device in which the first protective film 125 does not cover the innermost ring 120 is manufactured. On the other hand, if the silicon carbide semiconductor device includes the first protective film 125 that covers the plurality of rings 120, even if the position of the outer surface 125j of the first protective film 125 is displaced due to the misalignment. The innermost ring 120 can be reliably covered with the first protective film 125. Therefore, it can also contribute to the improvement of the manufacturing yield of the silicon carbide semiconductor device.

As described in the second embodiment, from the viewpoint of stress, it may be preferable not to cover the vicinity of the outer surface 112Hj of the outer peripheral upper source electrode 112Hc with the first protective film 125. Therefore, the position of the outer surface 125j of the first protective film 125 may be determined according to the characteristics required for the silicon carbide semiconductor device.

For example, in the cross section perpendicular to the extending direction of the ring 120, the width W provided with the plurality of rings 120 is 60 μm or more and 120 μm or less, and in this cross section, the outermost surface 120j of the ring 120 located at the innermost side is the first. The distance D to the outer surface 125j of the protective film 125 is 18 μm or more and 50 μm or less. Here, the width W is defined by the distance between the inner surface of the innermost ring 120 and the outer surface of the outermost ring 120.

(Fourth Embodiment)
A fourth embodiment of the silicon carbide semiconductor device of the present disclosure will be described. FIG. 7A is a cross-sectional view of the silicon carbide semiconductor device 204 of the present embodiment corresponding to the line AA'shown in FIG. 1A.

The silicon carbide semiconductor device 204 is a high-concentration first conductive type that is located outside the FLR region 100F on the surface of the first silicon carbide semiconductor layer 102 and is selectively formed so as to surround the FLR region 100F. A point that further includes a third contact region 130, a base electrode (third base electrode) 131 connected to the third contact region 130, and a seal electrode 132 connected to the base electrode 131 and surrounding the ring. Therefore, it is different from the silicon carbide semiconductor device 201 of the first embodiment. The second protective film 126 covers the entire seal electrode 132. The third contact region 130, the base electrode 131, and the seal electrode 132 can be formed at the same time as, for example, the source region 104 of the active region 100A, the source electrode 109, and the inner peripheral upper source electrode 112F, respectively.

The third contact region 130 is provided so as to function as a so-called channel stop region, not for obtaining ohmic contact with the first silicon carbide semiconductor layer 102. The side wall 140 at the end of the chip formed by dicing has a mechanical defect, and when the depletion layer extending from the ring 120 through the first silicon carbide semiconductor layer 102 to the outside of the chip reaches the side wall 140 at the end of the chip. , Causes drain leaks. By increasing the concentration of the first conductive impurity in the third contact region 130 by an order of magnitude or more higher than that of the first silicon carbide semiconductor layer 102, it is possible to make it difficult for the depletion layer to spread in the third contact region 130. can. Therefore, it is possible to prevent the depletion layer from reaching the side wall 140 at the end of the chip and causing a drain leak.

Further, even if a contraction stress or an expansion stress due to thermal expansion that may occur when the second protective film 126 is cured is generated, the inner side surface 132i or the outer surface 132j of the seal electrode 132 and the second protective film 126 engage with each other, whereby the second protective film 126 is engaged. The contraction and expansion of the second protective film 126 can be suppressed, and the floating of the second protective film 126 from the interlayer insulating film 111 can be suppressed.

The third contact region 130, the base electrode 131, and the seal electrode 132 may be provided in the silicon carbide semiconductor device 202 of the second embodiment. As shown in FIG. 7B, the silicon carbide semiconductor device 205 of the second embodiment further includes a third contact region 130 having the above-mentioned structure, a base electrode 131, and a seal electrode 132. Different from 202. According to the silicon carbide semiconductor device 205, the above-mentioned effect can be obtained in the same manner. Further, although not shown, the silicon carbide semiconductor device 203 of the third embodiment may be provided with the third contact region 130, the base electrode 131, and the seal electrode 132.

(Example 1)
A silicon carbide semiconductor device having the structure described in the above embodiment was manufactured. The silicon carbide semiconductor device having the cross-sectional structure shown in FIGS. 2A, 2B, 5A, and 5B was produced as Sample 1 and Sample 2. Further, as Samples 3 and 4, silicon carbide semiconductor devices having the cross-sectional structures shown in FIGS. 6A and 6B and having D = 18 μm and D = 50 μm were produced. For comparison, the silicon carbide semiconductor device in which the second protective film 126 is not provided and the terminal region is covered with the first protective film 125, and both the first protective film 125 and the second protective film 126 are the terminal regions (FLR region). A silicon carbide semiconductor device covering (including 100F) was prepared and used as Samples 5 and 6. In the silicon carbide semiconductor device of Samples 5 and 6, the outer peripheral upper source electrode is further provided on the outside of the FLR region 100F. A silicon nitride film formed by plasma CVD was used as the first protective film 125, and a polyimide resin film was used as the second protective film.

Table 1 summarizes the structures of Samples 1 to 6.

A high temperature and high humidity bias (THB) test was performed using the prepared sample. A plurality of prepared samples were prepared, and a voltage of 1000 V was applied between the source and drain at a temperature of 85 ° C. and a relative humidity of 85%, and the samples were stored. After storage, the drain leak current was measured periodically with a reverse bias of 1200 V. When the leak current ^{exceeds 1 × 10 -6} A, it is determined that the silicon carbide semiconductor device has failed.

8A, 8B, 8C and 8D show the test results of Samples 1, 2, 3 and 4. The results of samples 5 and 6 are shown in FIGS. 9A and 9B. Table 1 summarizes the test results.

As shown in Table 1, FIG. 8A and FIG. 8B, in the silicon carbide semiconductor devices of Samples 1 and 2, the leakage current is below the ^{standard (1 × 10 -6 A) even after 2000 hours have passed since the start of the test.} , No failure was seen. However, in the silicon carbide semiconductor device of Sample 1, it was found that the leak current once increased about 100 hours after the start of the test, but then the leak current decreased and the good characteristics were maintained. Further, in the silicon carbide semiconductor device of Sample 2, the leakage current hardly changed regardless of the passage of time.

As shown in Tables 1, 8C and 8D, even with the silicon carbide semiconductor devices of Samples 3 and 4, the leakage current is below the ^{standard (1 × 10 -6 A) even after 2000 hours have passed since the start of the test.} , No failure was seen.

On the other hand, as shown in Tables 1, 9A and 9B, the silicon carbide semiconductor devices of Samples 5 and 6 were determined to be out of order before the lapse of 2000 hours. The silicon carbide semiconductor device of Sample 5 failed in about 1000 hours, and the silicon carbide semiconductor device of Sample 6 failed in about 100 to 500 hours.

After the test was completed, the package was opened and each silicon carbide semiconductor device was observed with an optical microscope. 10A and 10B show the observation results of the silicon carbide semiconductor device of Sample 5 after the test. 11A and 11B show the observation results of the silicon carbide semiconductor device of Sample 6 after the test. 10A and 11A show the FLR region near the corner of the silicon carbide semiconductor device, and FIGS. 10B and 11B show the FLR region near the center of one side of the silicon carbide semiconductor device.

In the silicon carbide semiconductor devices of Samples 1, 2, 3 and 4, no particularly noticeable changes such as cracks and peeling of the protective film were confirmed at the corners and near the center of the FLR region. On the other hand, in the silicon carbide semiconductor devices of Samples 5 and 6, it was found that the protective film had cracks at the corners of the FLR region and the protective film had floated near the center of the FLR region. rice field.

From these results, it was found that the silicon carbide semiconductor device of the present embodiment has reliability in a high temperature and high humidity bias environment. Further, it was found that the reliability can be further improved by not covering the outer surface 112Hj of the outer peripheral upper source electrode 112H with the first protective film 125. It was also found that the reliability tends to decrease when a protective film having high hardness such as a silicon nitride film is provided in the FLR region.

(Example 2)
As described above, the increase in drain leakage current due to moving ions is more likely to occur in the high temperature reverse bias test performed at a higher temperature than in the high temperature and high humidity bias test. It was prepared and a high temperature reverse bias test was performed to examine the fluctuation of the drain leak current. Each sample was stored at a temperature of 175 ° C. in the air with a reverse voltage of 1200 V applied between the source and drain (HTRB test). After storage, the drain leak current (Idss) was measured periodically with a reverse bias of 1200 V.

12A, 12B, 12C and 12D show the test results of Samples 1, 2, 3 and 4. FIG. 13 shows the test results of sample 5.

As shown in FIGS. 12A and 12B, in the silicon carbide semiconductor devices of Samples 1 and 2, the drain leakage current increases in the initial stage of the high temperature reverse bias test as compared with that before the start of the test, but increases by about an order of magnitude. Therefore, there is no tendency for the drain leak current to continue to increase thereafter. This is because the movable ions move in the second protective film in the initial stage of the high temperature reverse bias test and the pressure resistance characteristics are slightly lowered, but the amount of movable ions contained in the second protective film is small, so that the high temperature reverse bias is performed. It is considered that the decrease in withstand voltage characteristics almost converges at the initial stage of the test.

As shown in FIGS. 12C and 12D, the drain leak current hardly changed in the silicon carbide semiconductor devices of Samples 3 and 4. Further, as shown in FIG. 13, in the silicon carbide semiconductor device of sample 5, the drain leak current hardly changed except for one sample.

From these results, it was found that the structure of the third embodiment shows excellent reliability, especially in the high temperature reverse bias test.

From the above results, the structures of the first, second and third embodiments all show excellent reliability in the high temperature and high humidity bias test and the high temperature reverse bias test, and in particular, the third embodiment. It was found that the structure was excellent in reliability with almost no increase in drain leak in the high temperature reverse bias test as compared with the first and second forms.

The silicon carbide semiconductor device of the present disclosure can be widely applied to semiconductor devices for various purposes and various driving devices such as an inverter circuit provided with the semiconductor device. For example, it can be suitably used for semiconductor devices such as those for automobiles and industrial equipment.

100 Silicon carbide semiconductor device 100A Active region 100E Termination region 100F FLR region 100S Scribly electrode region 100u Unit cell 101 Silicon carbide substrate 102 First silicon carbide semiconductor layer 103 First body region 104 Source region 105 First contact region 106 Second silicon carbide Semiconductor layer 107 Gate insulating film 108 Gate electrode 109 Source electrode 110 Drain electrode 111 Interlayer insulating film 111c, 111d, 111g Opening 112 Upper source electrode 112F Inner circumference Upper source electrode 112H, 112Hb, 112Hc Outer outer peripheral upper source electrode 112Hi Inner side surface 112Hj Outside Side surface 112P, 114P Pad area 113 Wiring electrode 114 Upper gate electrode 115 Second body area 116 Second contact area 119, 119a, 119b, 119c Base electrode 120 Ring 125 First protective film 125i Inner side surface 125j Outer side surface 126 Second protective film 130 Third contact area 131 Base electrode 132 Seal electrode

Claims (11)

A silicon carbide semiconductor device including a first conductive type silicon carbide substrate including an active region and a terminal region surrounding the active region, a plurality of unit cells located in the active region, and a terminal structure located in the terminal region. And
Each unit cell has at least the silicon carbide substrate and
The first silicon carbide semiconductor layer on the silicon carbide substrate and
A second conductive type first body region selectively formed on the surface of the first silicon carbide semiconductor layer,
A source region selectively formed in the first body region and
The gate insulating film located above the first silicon carbide semiconductor layer and
The gate electrode located on the gate insulating film and
The first contact area in contact with the first body area and
An inner peripheral upper source electrode electrically connected to the first contact region and the source region,
Including
The terminal structure is
With the silicon carbide substrate
The first silicon carbide semiconductor layer located on the silicon carbide substrate and
A second conductive type second body region selectively formed on the surface of the first silicon carbide semiconductor layer and having a ring shape surrounding the active region,
A second conductive ring located on the surface of the first silicon carbide semiconductor layer and surrounding the second body region.
A second conductive type second contact region selectively formed on the surface of the second body region,
An interlayer insulating film located above the second contact region and
One or more outer peripheral upper source electrodes located above the interlayer insulating film, penetrating the interlayer insulating film and electrically connected to the second contact region, and surrounding the active region.
An upper gate electrode electrically connected to the gate electrode and located between the inner peripheral upper source electrode and the outer peripheral upper source electrode in the active region.
Including
It is composed of silicon nitride and is located on the innermost side of the inner peripheral upper source electrode and the upper gate electrode and the one or more outer peripheral upper source electrodes in the active region and the terminal region except for the pad region. A first protective film that covers the inner surface of the outer peripheral upper source electrode and
A second protective film made of an organic material and covering at least a part of the at least one ring in the active region and the terminal region.
With more
The outer surface of the first protective film is a silicon carbide semiconductor located between the outermost outer peripheral upper source electrode and at least one ring of the one or more outer peripheral upper source electrodes. Device. A silicon carbide semiconductor device including a first conductive type silicon carbide substrate including an active region and a terminal region surrounding the active region, a plurality of unit cells located in the active region, and a terminal structure located in the terminal region. And
Each unit cell is at least
With the silicon carbide substrate
The first silicon carbide semiconductor layer on the silicon carbide substrate and
A second conductive type first body region selectively formed on the surface of the first silicon carbide semiconductor layer,
A source region selectively formed in the first body region and
The gate insulating film located above the first silicon carbide semiconductor layer and
The gate electrode located on the gate insulating film and
The first contact area in contact with the first body area and
An inner peripheral upper source electrode electrically connected to the first contact region and the source region,
Including
The terminal structure is
With the silicon carbide substrate
The first silicon carbide semiconductor layer located on the silicon carbide substrate and
A second conductive type second body region selectively formed on the surface of the first silicon carbide semiconductor layer and having a ring shape surrounding the active region,
A second conductive ring located on the surface of the first silicon carbide semiconductor layer and surrounding the second body region.
A second conductive type second contact region selectively formed on the surface of the second body region,
An interlayer insulating film located above the second contact region and
One or more outer peripheral upper source electrodes located above the interlayer insulating film, penetrating the interlayer insulating film and electrically connected to the second contact region, and surrounding the active region.
An upper gate electrode electrically connected to the gate electrode and located between the inner peripheral upper source electrode and the outer peripheral upper source electrode in the active region.
Including
It is composed of silicon nitride and is located on the innermost side of the inner peripheral upper source electrode and the upper gate electrode and the one or more outer peripheral upper source electrodes in the active region and the terminal region except for the pad region. A first protective film that covers the inner surface of the outer peripheral upper source electrode and
A second protective film made of an organic material and covering at least a part of the at least one ring in the active region and the terminal region.
With more
The outer surface of the first protective film is located on the outermost outer peripheral upper source electrode located on the outermost side of the one or more outer peripheral upper source electrodes.
Among the one or more of the peripheral upper source electrode, the outermost surface of the outer peripheral upper source electrode located outside, that in contact with the second protective film, a silicon carbide semiconductor device. A silicon carbide semiconductor device including a first conductive type silicon carbide substrate including an active region and a terminal region surrounding the active region, a plurality of unit cells located in the active region, and a terminal structure located in the terminal region. And
Each unit cell is at least
With the silicon carbide substrate
The first silicon carbide semiconductor layer on the silicon carbide substrate and
A second conductive type first body region selectively formed on the surface of the first silicon carbide semiconductor layer,
A source region selectively formed in the first body region and
The gate insulating film located above the first silicon carbide semiconductor layer and
The gate electrode located on the gate insulating film and
The first contact area in contact with the first body area and
An inner peripheral upper source electrode electrically connected to the first contact region and the source region,
Including
The terminal structure is
With the silicon carbide substrate
The first silicon carbide semiconductor layer located on the silicon carbide substrate and
A second conductive type second body region selectively formed on the surface of the first silicon carbide semiconductor layer and having a ring shape surrounding the active region,
Two or more second conductive type rings located on the surface of the first silicon carbide semiconductor layer and surrounding the second body region.
A second conductive type second contact region selectively formed on the surface of the second body region,
An interlayer insulating film located above the second contact region and
One or more outer peripheral upper source electrodes located above the interlayer insulating film, penetrating the interlayer insulating film and electrically connected to the second contact region, and surrounding the active region.
An upper gate electrode electrically connected to the gate electrode and located between the inner peripheral upper source electrode and the outer peripheral upper source electrode in the active region.
Including
It is composed of silicon nitride and is located on the innermost side of the inner peripheral upper source electrode and the upper gate electrode and the one or more outer peripheral upper source electrodes in the active region and the terminal region except for the pad region. A first protective film that covers the inner surface of the outer peripheral upper source electrode and
A second protective film made of an organic material and covering at least a part of the first protective film and at least a part of the two or more rings in the active region and the terminal region.
With more
The first protective film covers at least the innermost ring of the two or more rings, and covers at least the outermost ring of the plurality of rings. No , silicon carbide semiconductor device. A silicon carbide semiconductor device including a first conductive type silicon carbide substrate including an active region and a terminal region surrounding the active region, a plurality of unit cells located in the active region, and a terminal structure located in the terminal region. And
Each unit cell is at least
With the silicon carbide substrate
The first silicon carbide semiconductor layer on the silicon carbide substrate and
A second conductive type first body region selectively formed on the surface of the first silicon carbide semiconductor layer,
A source region selectively formed in the first body region and
The gate insulating film located above the first silicon carbide semiconductor layer and
The gate electrode located on the gate insulating film and
The first contact area in contact with the first body area and
An inner peripheral upper source electrode electrically connected to the first contact region and the source region,
Including
The terminal structure is
With the silicon carbide substrate
The first silicon carbide semiconductor layer located on the silicon carbide substrate and
A second conductive type second body region selectively formed on the surface of the first silicon carbide semiconductor layer and having a ring shape surrounding the active region,
A plurality of second conductive type rings located on the surface of the first silicon carbide semiconductor layer and surrounding the second body region, and three or more second conductive type rings.
A second conductive type second contact region selectively formed on the surface of the second body region,
An interlayer insulating film located above the second contact region and
One or more outer peripheral upper source electrodes located above the interlayer insulating film, penetrating the interlayer insulating film and electrically connected to the second contact region, and surrounding the active region.
An upper gate electrode electrically connected to the gate electrode and located between the inner peripheral upper source electrode and the outer peripheral upper source electrode in the active region.
Including
It is composed of silicon nitride and is located on the innermost side of the inner peripheral upper source electrode and the upper gate electrode and the one or more outer peripheral upper source electrodes in the active region and the terminal region except for the pad region. A first protective film that covers the inner surface of the outer peripheral upper source electrode and
A second protective film made of an organic material and covering at least a part of the first protective film and the upper part of the plurality of rings in the active region and the terminal region.
With more
The first protective film covers the upper part of two or more rings including the innermost ring among the plurality of rings, and at least the outermost ring among the plurality of rings. It does not cover the upper silicon carbide semiconductor device. In the cross section perpendicular to the extending direction of the plurality of rings, the distance W between the inner surface of the innermost ring and the outer surface of the outermost ring is 60 μm or more and 120 μm or less.
The silicon carbide semiconductor device according to claim 4 , wherein in the cross section, the distance between the outer surface of the first protective film and the outer surface of the innermost ring is 18 μm or more and 50 μm or less. The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein the one or more outer peripheral upper source electrodes and the inner peripheral upper source electrode are electrically connected. The silicon carbide semiconductor device according to any one of claims 1 to 6 , wherein the silicon carbide substrate has a scribe line region, and the second protective film does not cover the scribe line region. The terminal structure is located on the inner peripheral surface of the second contact region and is electrically in contact with the first base electrode, and is located on the outer peripheral surface of the second body region and is electrically connected. With at least one second base electrode in contact with the
The first base electrode is electrically connected to the inner peripheral upper source electrode, and the second base electrode is electrically connected to the outer peripheral upper source electrode according to any one of claims 1 to 7. Silicon carbide semiconductor device. The silicon carbide semiconductor device according to claim 8 , wherein the second base electrode surrounds the active region on the surface of the second contact region. On the surface of the first silicon carbide semiconductor layer, a first located outside the at least one ring or the plurality of rings and selectively formed so as to surround the at least one ring or the plurality of rings. 3 contact areas and
A third base electrode that is in electrical contact with the third contact region,
A seal electrode connected to the third base electrode and surrounding the outermost ring of the at least one ring or the plurality of rings.
The silicon carbide semiconductor device according to any one of claims 1 to 9. The silicon carbide semiconductor device according to claim 10 , wherein the second protective film covers the seal electrode.

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