JP6958962B2 - Semiconductor memory devices and semiconductor memory systems - Google Patents

Description

The present invention relates to a technique of a semiconductor memory device capable of communicating with a host device.

The semiconductor memory device includes a semiconductor memory (for example, a flash memory) and a microprocessor that controls the semiconductor memory. In such a semiconductor memory device, various processes can be realized by processing using the code and data stored in the semiconductor memory by the microprocessor.

In order to improve the processing speed, a semiconductor memory provided with a volatile high-speed memory (for example, SRAM (Static Random Access Memory)) has also been developed.

Since the volatile high-speed memory can be accessed at high speed, the code and data used for CPU processing are stored. Then, the microprocessor accesses the volatile high-speed memory, and the CPU processing by the microprocessor is realized at high speed. That is, the volatile high-speed memory is allowed access only from the microprocessor and is not accessed from the external device (host device) in order to ensure that the CPU processing by the microprocessor is stably executed. ..

Patent Document 1 discloses a digital system including a cache memory (for example, a cache memory realized by using SRAM), a main memory, and a CPU. In the technique of Patent Document 1, only the CPU accesses a cache memory (for example, SRAM) which is a volatile high-speed memory and performs CPU processing to realize high-speed CPU processing.

Japanese Unexamined Patent Publication No. 8-221323

As described above, the volatile high-speed memory is accessed only from the microprocessor and is accessed from the external device (host device) in order to ensure that the CPU processing by the microprocessor is stably executed. There is no such thing.

That is, the volatile high-speed memory usually does not allow access from an external device (host device) because there is a risk that CPU processing by the microprocessor becomes unstable if access is permitted from the outside.

However, if the volatile high-speed memory of the semiconductor memory device can be safely accessed from the external device (host device), various processes can be realized at high speed, so that the semiconductor can be safely accessed from the external device (host device). It is desired to realize a technique for accessing a volatile high-speed memory of a memory device.

Therefore, an object of the present invention is to realize a semiconductor memory device or a semiconductor memory system capable of safely accessing the volatile high-speed memory of the semiconductor memory device from an external device (host device).

In order to solve the above problems, the first invention is a semiconductor memory device capable of communicating with a host device, which includes a bus, a first storage unit, a second storage unit, a microprocessor, an interface unit, and the like. To be equipped.

The first storage unit is connected to the bus and performs at least one of reading and writing of data according to the first access speed.

The second storage unit is connected to the bus and performs at least one of reading and writing of data at a second access speed that is faster than the first access speed.

The microprocessor is connected to the bus.

The interface unit is connected to the bus and provides an interface that can be directly accessed from the host device to the second storage unit.

In this semiconductor memory device, since the interface unit provides an interface that can be directly accessed from the host device to the second storage unit, the host device can access the second storage unit via the interface unit. That is, in this semiconductor memory device, the host device temporarily connects the host device to the second storage device (for example, SRAM) having a high access speed, and directly (to the buffer or the first storage unit (for example, non-volatile memory) having a slow access speed). Can be accessed (without having to retain data in).

The second invention is the first invention, and the first storage unit can store a code for the microprocessor to perform an operation.

The interface unit stores the calculation result when the microprocessor executes the code in the second storage unit, reads the calculation result from the second storage unit, and transmits the calculation result to the host device.

As a result, in this semiconductor memory device, the host device can read the calculation result via the interface unit.

The "code" is, for example, data including a code (instruction code for performing an operation by a microprocessor).

The third invention is the first or second invention, in which the microprocessor reads a code for calculation by the microprocessor from the first storage unit and stores it in the second storage unit.

As a result, in this semiconductor memory device, the code for the microprocessor to calculate can be read from the first storage unit and stored in the second storage unit.

The fourth invention is any one of the first to third inventions, in which the interface unit stores the code received from the host device in the second storage unit.

As a result, in this semiconductor memory device, the code received from the host device can be stored in the second storage unit.

A fifth invention is any one of the first to fourth inventions, in which the interface unit sets and sets an externally accessible area, which is a memory area that allows access from the host device to the second storage unit. Access control to the second storage unit is performed based on the information of the externally accessible area.

In this semiconductor memory device, the interface unit sets information for specifying the external access permission area by, for example, specifying the memory area of the second storage unit by the offset Offst and the depth Dpt, and is based on the information. Then, the interface unit determines whether or not to allow access to the second storage unit from the host device. In this semiconductor memory device, when the interface unit permits access to the second storage unit from the host device based on the information for specifying the external access permission area, the host device performs the access to the second storage unit via the interface unit. The second storage unit can be accessed. That is, in this semiconductor memory device, data is not temporarily held in a second storage device (for example, SRAM) having a high access speed from the host device directly (in a buffer, a non-volatile memory having a slow access speed, or the like). ), Can be accessed. Further, in this semiconductor memory device, as described above, the interface unit controls access to the second storage device, and the area accessible from the external device (for example, the host device) can be limited to the external access permission area. As a result, in this semiconductor memory device, the second storage unit, which is a high-speed memory of the semiconductor memory device, is not illegally accessed from an external device (for example, a host device).

In this way, in this semiconductor memory device, the second storage unit, which is a high-speed memory of the semiconductor memory device, can be safely accessed from an external device (for example, a host device).

The sixth invention is the fifth invention, and the initial value of the information in the externally accessible area is a value indicating that access to the entire memory area of the second storage unit is prohibited.

As a result, it is possible to appropriately prevent unauthorized access to the second storage unit from the external device (for example, the host device) even when the external accessible area is not set.

The seventh invention is the sixth invention, further including an access prohibition information holding unit, a wrapper unit, and the like.

The access prohibition information holding unit holds the access prohibition information which is the information for setting the access prohibition area of the second storage unit.

The wrapper unit sets the access prohibited area of the second storage unit based on the access prohibited information.

As a result, in the semiconductor memory device, unauthorized access to the access prohibited area of the second storage unit can be appropriately prevented.

The eighth invention is the seventh invention, in which the access prohibition information holding unit includes a ROM that can be written only once, and the access prohibition information is written in the ROM.

As a result, in this semiconductor memory device, the access prohibition information is not changed later, so that unauthorized access to the access prohibited area of the second storage unit can be appropriately prevented.

The ninth invention is the seventh invention, in which the access prohibition information holding unit includes a circuit for holding the access prohibition information, and outputs the access prohibition information to the wrapper unit as a signal output from the circuit. do.

As a result, in this semiconductor memory device, the access prohibition information is not changed later, so that unauthorized access to the access prohibited area of the second storage unit can be appropriately prevented.

The tenth invention is any one of the seventh to ninth inventions, wherein the wrapper unit is a signal value indicating that the fetch access signal from the microprocessor is valid, and the instruction fetch signal received from the microprocessor. When the address indicated by is in the access prohibited area, access control to the second storage unit is performed so as to allow access to the access prohibited area of the second storage unit.

As a result, in this semiconductor memory device, access to the access prohibited area can be permitted when the above conditions are satisfied.

The eleventh invention is any one of the seventh to tenth inventions, in which the wrapper unit accesses the second storage unit based on the access prohibition information and the information of the external accessible area set by the interface unit. Take control.

As a result, in this semiconductor memory device, access control to the second storage unit can be performed under various conditions by using both the access prohibition information and the information of the externally accessible area.

The twelfth invention is any one of the seventh to eleventh inventions, and in the wrapper unit, the address requesting access to the second storage unit is an address in the external accessible area, and If it is determined that the area is within the access prohibited area, all access to the second storage unit is prohibited.

As a result, in this semiconductor memory device, it is possible to detect a state in which there is a high possibility that an unauthorized access to the second storage unit 4 is being executed from the external device, and an unauthorized access to the second storage unit 4 from the external device. Can be appropriately prevented.

The thirteenth invention is any one of the first to the twelfth inventions, and when the interface unit receives a command from the host device to access the entire memory area of the second storage unit of the semiconductor memory device, the thirteenth invention is the thirteenth invention. 2 A response indicating that the data stored in the storage unit cannot be read normally is transmitted to the host device.

Thereby, by investigating the response transmitted from the semiconductor memory device to the host device, it is possible to determine whether or not the thirteenth invention has been implemented.

A fourteenth invention is a semiconductor memory system including a host device and a semiconductor memory device according to any one of the first to thirteenth inventions.

Thereby, the semiconductor memory system can be realized by using the semiconductor memory device according to any one of the first to thirteenth inventions.

According to the present invention, it is possible to realize a semiconductor memory device or a semiconductor memory system capable of safely accessing the volatile high-speed memory of the semiconductor memory device from an external device (host device).

The schematic block diagram of the semiconductor memory system 1000 which concerns on 1st Embodiment. The operation sequence diagram of the semiconductor memory system 1000. The operation sequence diagram of the semiconductor memory system 1000. The figure which shows typically the state of the semiconductor memory system 1000 in the initial state. The figure which shows typically the state of the semiconductor memory system 1000 after the start processing executed by the microprocessor 2 after the semiconductor memory apparatus 100 is started. FIG. 5 is a diagram schematically showing a state of the semiconductor memory system 1000 when the host device H1 transmits an execution reservation command to the semiconductor memory device 100. The figure which shows typically the state of the semiconductor memory system 1000 when the external access permission area of the 2nd storage part 4 is set in the semiconductor memory apparatus 100. FIG. 5 is a diagram schematically showing a state of the semiconductor memory system 1000 when the host device H1 transmits a write instruction of data to be calculated to the semiconductor memory device 100. The figure which shows typically the state of the semiconductor memory system 1000 when the host device H1 transmits the calculation execution instruction to the semiconductor memory device 100. The figure which shows typically the state of the semiconductor memory system 1000 when the host device H1 transmits the reading instruction of the calculation result to the semiconductor memory device 100. The figure which shows typically the state of the semiconductor memory system 1000 when the external access permission area of the 2nd storage part 4 is set. The schematic block diagram of the semiconductor memory system 2000 which concerns on 2nd Embodiment. The figure for demonstrating the operation of the semiconductor memory system 2000 which concerns on 2nd Embodiment. The schematic block diagram of the semiconductor memory system 2000A of the 1st modification of 2nd Embodiment. The figure which shows the table which showed the condition for deciding the access control method for the 2nd storage part 4 in the semiconductor memory system of the 2nd modification of 2nd Embodiment. The figure which shows the CPU bus configuration.

[First Embodiment]
The first embodiment will be described below with reference to the drawings.

<1.1: Configuration of semiconductor memory system>
FIG. 1 is a schematic configuration diagram of the semiconductor memory system 1000 according to the first embodiment.

As shown in FIG. 1, the semiconductor memory system 1000 includes a host device H1 and a semiconductor memory device 100. The host device H1 and the semiconductor memory device 100 are connected by a communication path CH1 and can communicate in both directions. The communication path may be wired or wireless. A command, data, a clock signal, or the like is communicated between the host device H1 and the semiconductor memory device 100 via the communication path CH1.

The host device H1 is connected to the semiconductor memory device 100 via the communication path CH1. The host device H1 transmits, for example, a command, data, a clock signal, or the like to the semiconductor memory device 100.

Further, the host device H1 receives data or the like transmitted from the semiconductor memory device 100.

As shown in FIG. 1, the semiconductor memory device 100 includes an internal bus Bus, a host interface (host IF) 1, a microprocessor 2, a first storage unit 3, and a second storage unit 4.

The internal bus Bus is composed of, for example, a data bus, a control bus, and an address bus, and is connected to each functional unit of the semiconductor memory device 100. Then, each functional unit of the semiconductor memory device 100 can transmit and receive various data via the internal bus Bus.

The host interface 1 is connected to the internal bus Bus, and transmits and receives various data to and from the microprocessor 2 and the second storage unit 4. Further, the host interface 1 can be connected to the host device H1 via the communication path CH1. The host interface 1 transmits and receives commands, data, and the like via the communication path CH1.

Further, the host interface 1 includes a memory control unit 11, and uses the memory control unit 11 to execute access control of the second storage unit 4.

The memory control unit 11 is used to execute access control of the second storage unit 4. The memory control unit 11 may be realized by, for example, a register.

The microprocessor 2 controls each functional unit of the semiconductor memory device 100. The microprocessor 2 is connected to the internal bus Bus. The microprocessor 2 transmits various data to each functional unit of the semiconductor memory device 100 via the internal bus Bus, and also transmits various data from each functional unit of the semiconductor memory device 100 via the internal bus Bus. Receive.

The first storage unit 3 is a memory capable of reading / writing data. The first storage unit 3 is connected to the internal bus Bus and is controlled by the microprocessor 2.

The second storage unit 4 is a memory (for example, SRAM) that can be accessed at high speed, and can read / write data at an access speed faster than the access speed of the first storage unit 3. The second storage unit 4 is connected to the internal bus Bus and is controlled by the memory control unit 11 of the microprocessor 2 or the host IF1.

<1.2: Operation of semiconductor memory system>
The operation of the semiconductor memory system 1000 configured as described above will be described below.

2 and 3 are operation sequence diagrams of the semiconductor memory system 1000.

FIG. 4 is a diagram schematically showing a state of the semiconductor memory system 1000 in the initial state.

FIG. 5 is a diagram schematically showing a state of the semiconductor memory system 1000 after the startup process executed by the microprocessor 2 after the semiconductor memory device 100 is started.

FIG. 6 is a diagram schematically showing a state of the semiconductor memory system 1000 when the host device H1 transmits an execution reservation command to the semiconductor memory device 100.

FIG. 7 is a diagram schematically showing a state of the semiconductor memory system 1000 when the external access permission area of the second storage unit 4 is set in the semiconductor memory device 100.

FIG. 8 is a diagram schematically showing a state of the semiconductor memory system 1000 when the host device H1 transmits a write instruction of data to be calculated to the semiconductor memory device 100.

FIG. 9 is a diagram schematically showing a state of the semiconductor memory system 1000 when the host device H1 transmits an arithmetic execution command to the semiconductor memory device 100.

FIG. 10 is a diagram schematically showing a state of the semiconductor memory system 1000 when the host device H1 transmits a read instruction of the calculation result to the semiconductor memory device 100.

Hereinafter, description will be made with reference to the operation sequence diagrams of the semiconductor memory system 1000 of FIGS. 2 and 3.

First, in the initial state, as shown in FIG. 4, the second storage unit 4 is in a state in which no data is stored. In FIG. 4, the hatched portion of the second storage unit 4 indicates that the data is not stored.

As shown in FIG. 4, the first storage unit 3 stores a resident code, an additional function code, and confidential information. FIG. 4 schematically shows that the resident code, the additional function code, and the confidential information are stored in a predetermined memory area of the first storage unit 3, respectively.

(Step S1 to Step S3):
In step S1, the semiconductor memory device 100 is activated, and the microprocessor 2 executes the activation process.

Then, the microprocessor 2 executes the memory access process. Specifically, the microprocessor 2 reads the resident code from the first storage unit 3 (step S2) and writes the read resident code to the second storage unit 4 (step S3).

After the completion of step S3, the microprocessor 2 goes into a standby state.

FIG. 5 shows the state of the semiconductor memory system 1000 when the process of step S3 is completed.

(Step S4):
In step S4, the host device H1 transmits an execution reservation instruction Dh (RsvExe) to the semiconductor memory device 100. Note that "Dh (X)" is data transmitted by the host device H1 to the semiconductor memory device 100, and the data includes commands and arguments (for example, address data) necessary for executing X. ), Information for specifying the data to be processed, predetermined data, etc. can be included.

The host IF1 of the semiconductor memory device 100 analyzes the data (command) received from the host device H1 and determines that the data (command) is the execution reservation command Dh (RsvExe). Then, the host IF1 transfers the data (execution reservation instruction Dh (RsvExe)) received from the host device H1 to the microprocessor 2 via the bus Bus.

The microprocessor 2 receives the data (execution reservation instruction Dh (RsvExe)) from the host IF1.

(Steps S5 and S6):
In step S5, the microprocessor 2 executes the memory access process according to the execution reservation instruction Dh (RsvExe) received from the host IF1. Specifically, the microprocessor 2 reads (1) an additional function code and (2) confidential information from the first storage unit 3. The confidential information may be read out as needed.

In step S6, the microprocessor 2 writes (1) an additional function code and (2) confidential information read from the first storage unit 3 to the second storage unit 4. The confidential information may be written as needed.

FIG. 6 shows the state of the semiconductor memory system 1000 when the process of step S6 is completed.

(Step S7):
In step S7, the microprocessor 2 performs a process of setting an external access permission area of the second storage unit 4. Specifically, the microprocessor 2 outputs information for setting the external access permission area of the second storage unit 4 to the memory control unit 11 of the host IF1 via the bus Bus. The information for setting the external access permission area is, for example, the offset Offst from the start address of the memory area of the second storage unit 4 and the address of the memory area of the second storage unit 4 determined by the offset Offst. Depth from Dpt.

In this case, the second storage unit 4 from the address determined by "(start address) + (offset Offst)" to the address determined by "(start address) + (offset Offst) + (depth Dpt)". The memory area becomes the external access permission area.

The memory control unit 11 is set with a value indicating that access to the entire memory area of the second storage unit 4 is prohibited. As a result, it is possible to appropriately prevent unauthorized access to the second storage unit 4 from the external device (for example, the host device H1) even when the external accessible area is not set.

The memory control unit 11 of the host IF1 holds information (for example, offset Offst and depth Dpt) for setting an external access permission area from the microprocessor 2. The host IF1 controls the access of the second storage unit 4 based on the external access permission area setting information (for example, offset Offst and depth Dpt) held in the memory control unit 11.

FIG. 7 shows the state of the semiconductor memory system 1000 when the process of step S7 is completed.

(Step S8):
In step S8, the host device H1 transmits a write command Dh (Write) of the calculation target data to the semiconductor memory device 100.

The host IF1 of the semiconductor memory device 100 analyzes the data (command) received from the host device H1 and determines that the data (command) is a write instruction Dh (Write) of the data to be calculated. Then, the host IF1 executes the memory access process based on the data received from the host device H1 (write instruction Dh (Write) of the calculation target data).

(Step S9):
In step S9, the host IF1 extracts the calculation target data included in the calculation target data write command Dh (Write), and writes the extracted calculation target data in the second storage unit 4. At this time, the host IF1 refers to the information of the external access permission area held in the memory control unit 11 and writes the calculation target data to the external access permission area of the second storage unit 4.

FIG. 8 shows the state of the semiconductor memory system 1000 when the process of step S9 is completed. As can be seen from FIG. 8, the calculation target data transmitted from the host device H1 is stored in the external access permission area of the second storage unit 4.

(Step S10):
In step S10, the host device H1 transmits an arithmetic execution instruction Dh (Exe) (microprocessor start command) to the semiconductor memory device 100.

The host IF1 of the semiconductor memory device 100 analyzes the data (command) received from the host device H1 and determines that the data (command) is the calculation execution instruction Dh (Exe). Then, the host IF1 transfers the data (calculation execution instruction Dh (Exe)) received from the host device H1 to the microprocessor 2 via the bus Bus.

The microprocessor 2 receives the data (execution reservation instruction Dh (Exe)) from the host IF1.

(Steps S11 to S13)
In step S11, the microprocessor 2 executes the memory access process according to the arithmetic execution instruction Dh (Exe) received from the host IF1. Specifically, the microprocessor 2 reads (1) an additional function code, (2) calculation target data, and (3) confidential information (if necessary) from the second storage unit 4.

In step S12, the microprocessor 2 uses (1) an additional function code read from the second storage unit 4, (2) data to be calculated, and (3) confidential information (if necessary) to perform a calculation (CPU calculation). Process) is executed.

In step S13, the microprocessor 2 performs a memory access process to the second storage unit 4. Specifically, the microprocessor 2 writes the execution result (calculation result) of the above calculation (CPU calculation processing) in the external access permission area of the second storage unit 4.

FIG. 9 shows the state of the semiconductor memory system 1000 when the process of step S13 is completed. As can be seen from FIG. 9, the result of the calculation by the microprocessor 2 using (1) the additional function code, (2) the data to be calculated, and (3) the confidential information (if necessary) is the outside of the second storage unit 4. It is stored in the permission area.

The host device H1 polls the semiconductor memory device 100, for example, and grasps that the arithmetic processing by the microprocessor 2 of the semiconductor memory device 100 has been completed.

(Steps S14 to S16)
In step S14, the host device H1 transmits a read instruction Dh (Read) of the calculation result to the semiconductor memory device 100.

The host IF1 of the semiconductor memory device 100 analyzes the data (command) received from the host device H1 and determines that the data (command) is the operation result read instruction Dh (Read). Then, the host IF1 executes the memory access process based on the data received from the host device H1 (the operation result read instruction Dh (Read)).

In step S15, the host IF1 reads the calculation result from the external access permission area.

In step S16, the host IF1 creates transmission data including the calculation result read from the external access permission area, and transmits the created transmission data as transmission data Ds (Result) to the host device H1.

The host device H1 receives the data Ds (Result) transmitted from the host IF1 and extracts the calculation result from the received data Ds (Result).

As described above, in the semiconductor memory system 1000, the memory control unit 11 of the host IF1 holds information (for example, offset Offst and depth Dpt) for specifying the external access permission area of the second storage unit 4, and the relevant information is provided. Based on the information, it is determined whether or not the host IF1 permits access to the second storage unit 4 from the host device H1. In the semiconductor memory system 1000, when the host IF1 permits access to the second storage unit 4 from the host device H1 based on the information held in the memory control unit 11, the host device H1 sets the host IF1. The second storage unit 4 can be accessed via the second storage unit 4. That is, in the semiconductor memory system 1000, the host device H1 temporarily holds data in a second storage device (for example, SRAM) having a high access speed directly (in a buffer, a non-volatile memory having a slow access speed, or the like). Can be accessed (without). Further, in the semiconductor memory system 1000, as described above, the host IF1 controls access to the second storage unit 4, and the area accessible from the external device (for example, the host device H1) can be limited to the external access permission area. can. As a result, in the semiconductor memory system 1000, the second storage unit 4, which is the high-speed memory of the semiconductor memory device 100, is not illegally accessed from an external device (for example, the host device H1).

In this way, in the semiconductor memory system 1000, the second storage unit 4, which is the high-speed memory of the semiconductor memory device 100, can be safely accessed from an external device (for example, the host device H1).

Here, as an example of using the semiconductor memory system 1000, (A) a case where an encryption function is added, (B) a case where a random number generation function is added, and (C) a case where a test function at the time of shipment is added. Will be described.

≪ (A) When adding an encryption function≫
First, as an example of using the semiconductor memory system 1000, a case where (A) an encryption function is added will be described.

In this case, the semiconductor memory system 1000 executes the following processing.
(1) The firmware (F / W) that realizes the encryption function is stored in the first storage unit 3. The firmware (F / W) that realizes this encryption function is stored in the first storage unit 3 as a resident code, an additional function code, and confidential information.
(2) The microprocessor 2 reads the resident code stored in the first storage unit 3 at startup (boot time) from the first storage unit 3 and writes it in the second storage unit 4. After that, the microprocessor 2 goes into a standby state.
(3) The host device H1 transmits an execution reservation command Dh (RsvExe) to the semiconductor memory device 100. When the semiconductor memory device 100 receives the execution reservation instruction Dh (RsvExe), the semiconductor memory device 100 reads the additional function code and the secret information from the first storage unit 3, and writes the read additional function code and the secret information in the second storage unit 4. ..

Further, the semiconductor memory device 100 holds information for setting an external access permission area of the second storage unit 4 in the memory control unit 11 of the host IF1. As a result, in the semiconductor memory device 100, the external access permission area of the second storage unit 4 is set by the host IF1, and thereafter, the access control to the second storage unit 4 is executed by the host IF1.
(4) The host device H1 transmits a write command Dh (Write) of the calculation target data to the semiconductor memory device 100. The semiconductor memory device 100 receives the write instruction Dh (Write) of the calculation target data, and writes the calculation target data to the external access permission area of the second storage unit 4 by the host IF1.
(5) The host device H1 transmits an arithmetic execution command Dh (Exe) (microprocessor start command) to the semiconductor memory device 100.

The microprocessor 2 of the semiconductor memory device 100 executes an encryption process on the calculation target data stored in the second storage unit 4 by using the additional function code stored in the second storage unit 4.

Then, the calculation result of the encryption process is written in the external access permission area of the second storage unit 4.
(6) The host device H1 confirms that the processing of the microprocessor 2 in the semiconductor memory device 100 is completed by polling, for example, and then sends a calculation result read instruction Dh (Read) to the semiconductor memory device 100. To send. The host IF1 of the semiconductor memory device 100 reads the calculation result of the encryption process from the second storage unit 4 and transmits it to the host device H1.

As described above, the encryption function can be added to the semiconductor memory system 1000.

≪ (B) When adding a random number generation function≫
Next, as an example of using the semiconductor memory system 1000, a case where (B) a random number generation function is added will be described.

In this case, the semiconductor memory system 1000 executes the following processing.
(1) The firmware (F / W) that realizes the random number generation function is stored in the first storage unit 3. The firmware (F / W) that realizes this random number generation function is stored in the first storage unit 3 as a resident code and an additional function code.
(2) The microprocessor 2 reads the resident code stored in the first storage unit 3 at startup (boot time) from the first storage unit 3 and writes it in the second storage unit 4. After that, the microprocessor 2 goes into a standby state.
(3) The host device H1 transmits an execution reservation command Dh (RsvExe) to the semiconductor memory device 100. When the semiconductor memory device 100 receives the execution reservation instruction Dh (RsvExe), the semiconductor memory device 100 reads the additional function code from the first storage unit 3 and writes the read additional function code to the second storage unit 4.

Further, the semiconductor memory device 100 holds information for setting an external access permission area of the second storage unit 4 in the memory control unit 11 of the host IF1. As a result, in the semiconductor memory device 100, the external access permission area of the second storage unit 4 is set by the host IF1, and thereafter, the access control to the second storage unit 4 is executed by the host IF1.
(4) The host device H1 transmits an arithmetic execution command Dh (Exe) (microprocessor start command) to the semiconductor memory device 100.

The microprocessor 2 of the semiconductor memory device 100 executes the random number generation process using the additional function code stored in the second storage unit 4.

Then, the calculation result of the random number generation process is written in the external access permission area of the second storage unit 4.
(6) The host device H1 confirms that the processing of the microprocessor 2 in the semiconductor memory device 100 is completed by polling, for example, and then sends a calculation result read instruction Dh (Read) to the semiconductor memory device 100. To send. The host IF1 of the semiconductor memory device 100 reads the calculation result of the random number generation process from the second storage unit 4 and transmits it to the host device H1.

As described above, the random number generation function can be added to the semiconductor memory system 1000.

≪ (C) When adding a factory test function≫
Next, as an example of using the semiconductor memory system 1000, (C) a case where a test function at the time of shipment is added will be described.

In this case, the semiconductor memory system 1000 executes the following processing.
(1) The firmware (F / W) that realizes the function of executing the instruction of the specific address Adrs_spec of the second storage unit 4 is stored in the first storage unit 3. The firmware (F / W) that realizes this function is stored in the first storage unit 3 as a resident code.
(2) The microprocessor 2 performs the activation process by the resident code stored in the first storage unit 3, and acquires the information of the specific address Adrs_spec of the second storage unit 4 from the resident code. Then, the microprocessor 2 holds the information for setting the external access permission area of the second storage unit 4 in the memory control unit 11 of the host IF1 based on the acquired specific address Addrs_spec.

FIG. 11 is a diagram schematically showing a state of the semiconductor memory system 1000 when the external access permission area of the second storage unit 4 is set. As can be seen from FIG. 11, in this case, the specific address Adrs_spec is set at the address (memory address) next to the memory area in which the resident code is stored, and the memory area after the specific address Adrs_spec is the external access permission area. Is set to.
(3) The host device H1 transmits a test code write command Dh (Write) to the semiconductor memory device 100. The semiconductor memory device 100 receives the test code write command Dh (Write), and writes the test code to the memory area after the specific address Adrs_spec of the second storage unit 4, that is, the external access permission area by the host IF1.
(4) The host device H1 transmits an arithmetic execution command Dh (Exe) (microprocessor start command) to the semiconductor memory device 100.

The microprocessor 2 of the semiconductor memory device 100 executes a test process using the test code stored in the second storage unit 4.
Then, the calculation result of the test process is written in the external access permission area of the second storage unit 4.
(6) The host device H1 confirms that the processing of the microprocessor 2 in the semiconductor memory device 100 is completed by polling, for example, and then sends a calculation result read instruction Dh (Read) to the semiconductor memory device 100. To send. The host IF1 of the semiconductor memory device 100 reads the calculation result of the test process from the second storage unit 4 and transmits it to the host device H1.

As described above, the test function (test function at the time of shipment) can be added to the semiconductor memory system 1000.

[Second Embodiment]
Next, the second embodiment will be described.

The same parts as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

<2.1: Configuration of semiconductor memory system>
FIG. 12 is a schematic configuration diagram of the semiconductor memory system 2000 according to the second embodiment.

As shown in FIG. 12, the semiconductor memory system 2000 of the second embodiment further includes a wrapper unit 5 and an access prohibition information holding unit 6 in the semiconductor memory system 1000 of the first embodiment.

The wrapper unit 5 is installed between the second storage unit 4 and the bus Bus, and is connected to the access prohibition information holding unit 6. The wrapper unit 5 is realized by, for example, a wrapper circuit. The wrapper unit 5 acquires access prohibition information for setting the access prohibited area of the second storage unit 4 from the access prohibition information holding unit 6, and based on the acquired access prohibition information, transfers to the second storage unit 4. Perform access control. Further, the wrapper unit 5 inputs a fetch access signal output from the microprocessor 2 via the bus Bus. When the fetch access signal is enabled (when it is a signal value indicating the enable), the wrapper unit 5 reads data from the second storage unit 4 and outputs the read data to the microprocessor 2 via the bus Bus.

The access prohibition information holding unit 6 stores and holds the access prohibition information for setting the access prohibited area of the second storage unit 4. Then, the access prohibition information holding unit 6 outputs the held access prohibition information to the wrapper unit 5 in accordance with the request from the wrapper unit 5.

<2.2: Operation of semiconductor memory system>
The operation of the semiconductor memory system 2000 configured as described above will be described below.

The description of the same part as that of the first embodiment will be omitted.

The basic operation of the semiconductor memory system 2000 is the same as that of the semiconductor memory system 1000 of the first embodiment shown in the operation sequences of FIGS. 2 and 3.

FIG. 13 is a diagram for explaining the operation of the semiconductor memory system 2000 according to the second embodiment.

The access prohibition information holding unit 6 stores access prohibition information for setting the access prohibition area of the second storage unit 4. The access prohibition information holding unit 6 is realized by, for example, an OTP (One Time Program) type ROM. Therefore, the access prohibition information held in the access prohibition information holding unit 6 cannot be changed later. Therefore, the security strength of the access prohibited information held in the access prohibited information holding unit 6 is high.

The access prohibition information holding unit 6 may be implemented by hardware (may be implemented by hard-wired logic). In this case, since the hardware that realizes the access prohibition information holding unit 6 cannot be changed, the access prohibition information output from the access prohibition information holding unit 6 cannot be changed later. Therefore, the security strength of the access prohibited information held in the access prohibited information holding unit 6 is high.

The wrapper unit 5 acquires the access prohibition information for setting the access prohibition area of the second storage unit 4 from the access prohibition information holding unit 6. Then, the wrapper unit 5 controls access to the second storage unit 4 based on the acquired access prohibition information. Specifically, the wrapper unit 5 sets the access prohibited area of the second storage unit 4 based on the access prohibited information. This access prohibited area is a memory area where access from an external device (for example, the host device H1) is prohibited. The access prohibited area is a memory area that can be read by instruction fetch from the microprocessor 2. Specifically, only when the fetch access signal input from the microprocessor 2 to the wrapper unit 5 is a signal value indicating fetch enable, the instruction fetch from the microprocessor 2 causes the access prohibited area of the second storage unit 4 to be occupied. Data (instruction code) can be read.

FIG. 13 schematically shows an example of an access prohibited area set by the wrapper unit 5. Specifically, in FIG. 13, the memory areas prohibit_AR1 and prohibit_AR2 are access prohibited areas set by the wrapper unit 5. In this case, in the second storage unit 4, the memory area in which the resident code is stored (the area set as the memory area prohibit_AR1) and the memory area in which the confidential information is stored (memory area prohibit_AR1) are the wrapper unit. This is the access prohibited area set by 5.

By setting the access prohibited area in this way, the memory area in which the resident code of the second storage unit 4 is stored and the memory area in which the confidential information is stored can be an external device (for example, the host device H1). It is possible to appropriately prevent unauthorized access from.

The data (code) stored in the access prohibited area is read by instruction fetch as follows.

The microprocessor 2 outputs the fetch access signal and the instruction fetch signal to the wrapper unit 5 via the bus Bus.

The wrapper unit 5 receives the fetch access signal and the instruction fetch signal from the microprocessor 2, and acquires the address of the instruction fetch target from the received instruction fetch signal. Further, the wrapper unit 5 determines whether or not the received fetch access signal is a signal value indicating enable. Then, when the received fetch access signal is a signal value indicating enable, the wrapper unit 5 even when the acquired instruction fetch target address is an address in the access prohibited area of the second storage unit 4. , Read the data (instruction code) from the address. Then, the wrapper unit 5 outputs the read data (instruction code) to the microprocessor 2 via the bus Bus.

In the semiconductor memory system 2000, the confidential information is stored in the second storage unit 4 in the form of an instruction code. As a result, in the semiconductor memory system 2000, as shown in FIG. 13, even if the memory area in which the confidential information is stored is set in the access prohibited area prohibit_AR2, it can be read only from the microprocessor 2 by the above processing.

That is, (1) the fetch access signal input to the wrapper unit 5 is a signal value indicating enable, and (2) the wrapper unit 5 is the code of the address included in the access prohibited area prohibit_AR2 from the microprocessor 2. When the instruction fetch signal for reading is received, the confidential information (confidential information stored as data in the instruction code format) can be read from the access prohibited area processor_AR2.

The confidential information may be included in a field in which arbitrary data can be included, for example, in the format of the instruction code.

As described above, in the semiconductor memory system 2000, the access prohibited area can be set by the wrapper unit 5, and the data stored in the access prohibited area of the second storage unit 4 can be fetched and accessed from the microprocessor 2. Read by instruction fetch only when the signal is enabled.

Therefore, in the semiconductor memory system 2000, it is possible to effectively prevent an external device (for example, the host device H1) from illegally accessing the memory area set in the access prohibited area in the second storage unit 4.

≪First modification≫
Next, a first modification of the second embodiment will be described. A detailed description of the same parts as those of the above embodiment will be omitted.

FIG. 14 is a schematic configuration diagram of the semiconductor memory system 2000A of the first modification of the second embodiment.

The semiconductor memory system 2000A of the present modification has a configuration in which the microprocessor 2 is replaced with the microprocessor 2A and the wrapper unit 5 is replaced with the wrapper unit 5A in the semiconductor memory system 2000 of the second embodiment.

The microprocessor 2A is connected to the wrapper unit 5A by a signal line L1 for outputting a fetch access signal. The microprocessor 2A directly outputs a fetch access signal to the wrapper unit 5A by the signal line L1 without going through the bus Bus. Other than the above, the microprocessor 2A is the same as the microprocessor 2.

The wrapper unit 5A is connected to the microprocessor 2A by the signal line L1. The wrapper unit 5A inputs a fetch access signal from the microprocessor 2A by the signal line L1. Other than the above, the wrapper unit 5A is the same as the wrapper unit 5.

In the semiconductor memory system 2000A of this modification, the wrapper unit 5A receives the fetch access signal output from the microprocessor 2A via the signal line L1.

Then, in the semiconductor memory system 2000A, the same operation as in the second embodiment is executed by using the received fetch access signal.

As a result, in the semiconductor memory system 2000A, similarly to the semiconductor memory system 2000, the external device (for example, the host device H1) illegally accesses the memory area set in the access prohibited area in the second storage unit 4. It can be effectively prevented.

≪Second modification≫
Next, a second modification of the second embodiment will be described. In addition, detailed description of the same parts as those of the above-described embodiment and modification will be omitted.

FIG. 15 is a diagram showing a table showing conditions for determining an access control method for the second storage unit 4 in the semiconductor memory system of the second modification of the second embodiment.

The configuration of the semiconductor memory system of this modification is the same as the configuration of the semiconductor memory system 2000 of the second embodiment or the semiconductor memory system 2000A of the first modification of the second embodiment.

The processing contents of the wrapper unit 5 (or the wrapper unit 5A) are different.

The wrapper unit 5 (or wrapper unit 5A) of this modification determines the access control method for the second storage unit 4 according to the conditions (patterns) shown in FIG.

Specifically, the wrapper unit 5 (or wrapper unit 5A) of this modification determines the access control method according to the following patterns 1 to 4.

(Pattern 1):
The wrapper unit 5 (or wrapper unit 5A) of this modification determines the external access permission area from the data (offset Offst and depth Dpt) held in the memory control unit 11 of the host IF1. Further, the wrapper unit 5 (or the wrapper unit 5A) of this modification determines the access prohibited area from the access prohibited information held in the access prohibited information holding unit 6.

Then, in the wrapper unit 5 (or wrapper unit 5A) of this modification, the address of the second storage unit 4 to be accessed from the host IF1 is set.
(1) The address is outside the external access permission area, and
(2) If the address is within the access prohibited area
Access to the address of the second storage unit 4 is prohibited.

If the wrapper unit 5 (or wrapper unit 5A) of this modification is a signal indicating that the fetch access signal is enabled, the access to the address by instruction fetch from the microprocessor 2 (or 2A) is performed. to approve.

(Pattern 2):
The wrapper unit 5 (or wrapper unit 5A) of this modification determines the external access permission area from the data (offset Offst and depth Dpt) held in the memory control unit 11 of the host IF1. Further, the wrapper unit 5 (or the wrapper unit 5A) of this modification determines the access prohibited area from the access prohibited information held in the access prohibited information holding unit 6.

Then, in the wrapper unit 5 (or wrapper unit 5A) of this modification, the address of the second storage unit 4 to be accessed from the host IF1 is set.
(1) The address is outside the external access permission area, and
(2) If the address is outside the access prohibited area
Access to the address of the second storage unit 4 is prohibited.

If the wrapper unit 5 (or wrapper unit 5A) of this modification is a signal indicating that the fetch access signal is enabled, the access to the address by instruction fetch from the microprocessor 2 (or 2A) is performed. to approve.

(Pattern 3):
The wrapper unit 5 (or wrapper unit 5A) of this modification determines the external access permission area from the data (offset Offst and depth Dpt) held in the memory control unit 11 of the host IF1. Further, the wrapper unit 5 (or the wrapper unit 5A) of this modification determines the access prohibited area from the access prohibited information held in the access prohibited information holding unit 6.

Then, in the wrapper unit 5 (or wrapper unit 5A) of this modification, the address of the second storage unit 4 to be accessed from the host IF1 is set.
(1) It is an address in the external access permission area and
(2) If the address is within the access prohibited area
All access to the address of the second storage unit 4 is prohibited.

In this case, since there is a high possibility that the access is unauthorized from the external device (for example, the host device H1), all access to the address of the second storage unit 4 is prohibited.

(Pattern 4):
The wrapper unit 5 (or wrapper unit 5A) of this modification determines the external access permission area from the data (offset Offst and depth Dpt) held in the memory control unit 11 of the host IF1. Further, the wrapper unit 5 (or the wrapper unit 5A) of this modification determines the access prohibited area from the access prohibited information held in the access prohibited information holding unit 6.

Then, in the wrapper unit 5 (or wrapper unit 5A) of this modification, the address of the second storage unit 4 to be accessed from the host IF1 is set.
(1) It is an address in the external access permission area and
(2) If the address is outside the access prohibited area
The access to the address of the second storage unit 4 is permitted.

In the above patterns 1 to 3, the access permission and access prohibition settings are different because the external access permission area setting information and / or the access prohibition area setting information is illegally changed. Alternatively, it is presumed that it was changed due to noise or the like.

In the semiconductor memory system of this modification, the wrapper unit 5 (or the wrapper unit 5A) performs access control as described above, so that access control to the second storage unit 4 with even higher security strength can be realized. can.

[Other Embodiments]
A semiconductor memory system and a semiconductor memory device may be configured by combining the above embodiments and modifications.

Further, in the above embodiment (including a modification), the information for setting the external access permission area set by the memory control unit 11 of the host IF1 does not have to be fixed data (value), for example. It may be changed at a predetermined timing when the semiconductor memory device is operating. As a result, the external access permission area of the second storage unit 4 can be dynamically changed. Further, the information for setting the external access permission area may be included in the resident code. In this case, the host IF1 may extract information for setting the external access permission area from the resident code, and set (change) the external access permission area of the second storage unit 4 based on the information. ..

Further, in the semiconductor memory device described in the above embodiment (including a modification), each block may be individually integrated into one chip by a semiconductor device such as an LSI, or one chip so as to include a part or all of the blocks. It may be converted.

Although it is referred to as LSI here, it may be referred to as IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

Further, the method of making an integrated circuit is not limited to the LSI, and may be realized by a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after the LSI is manufactured, or a reconfigurable processor that can reconfigure the connection and settings of circuit cells inside the LSI may be used.

In addition, a part or all of the processing of each functional block of each of the above embodiments may be realized by a program. Then, a part or all of the processing of each functional block of each of the above embodiments is performed by the central processing unit (CPU) in the computer. Further, the program for performing each process is stored in a storage device such as a hard disk or a ROM, and is read and executed in the ROM or the RAM.

Further, each process of the above embodiment may be realized by hardware, or may be realized by software (including a case where it is realized together with an OS (operating system), middleware, or a predetermined library). Further, it may be realized by mixed processing of software and hardware.

For example, when each functional unit of the above embodiment (including a modified example) is realized by software, the hardware configuration (for example, CPU, ROM, RAM, input unit, output unit, etc.) shown in FIG. 16 is realized by a bus Bus. Each functional part may be realized by software processing by using the connected hardware configuration).

Further, the execution order of the processing methods in the above-described embodiment is not necessarily limited to the description of the above-described embodiment, and the execution order can be changed without departing from the gist of the invention.

A computer program that causes a computer to perform the above-mentioned method and a computer-readable recording medium on which the program is recorded are included in the scope of the present invention. Here, examples of computer-readable recording media include flexible disks, hard disks, CD-ROMs, MOs, DVDs, DVD-ROMs, DVD-RAMs, large-capacity DVDs, next-generation DVDs, and semiconductor memories. ..

The computer program is not limited to the one recorded on the recording medium, and may be transmitted via a telecommunication line, a wireless or wired communication line, a network represented by the Internet, or the like.

Further, the wording "part" may be a concept including "circuitity". The circuit may be realized in whole or in part by hardware, software, or a mixture of hardware and software.

The specific configuration of the present invention is not limited to the above-described embodiment, and various changes and modifications can be made without departing from the gist of the invention.

1000, 2000, 2000A Semiconductor memory system 100, 100A, 100B Semiconductor memory device 1 Host interface (interface part)
11 Memory control unit 2, 2A microprocessor 3 1st storage unit 4 2nd storage unit 5, 5A wrapper unit 6 Access prohibition information holding unit Bus Internal bus H1 Host device

Claims (12)

A semiconductor memory device that can communicate with the host device
With the bus
A first storage unit connected to the bus and performing at least one of reading and writing data at a first access speed, and a first storage unit.
A volatile second storage unit that is connected to the bus and performs at least one of reading and writing data at a second access speed that is faster than the first access speed.
With the microprocessor connected to the bus
An interface unit that is connected to the bus, has an externally accessible area of the second storage unit set, and provides an interface that allows the host device to directly access the externally accessible area of the second storage unit. When,
With
The first storage unit can store a code for calculation by the microprocessor.
The microprocessor
A code for calculation by the microprocessor is read from the first storage unit and stored in the second storage unit.
The code stored in the second storage unit is executed in response to the operation execution command being received from the host device via the interface unit, and the calculation result when the code is executed is stored in the second storage unit. Stored in the externally accessible area of the unit
The interface unit
In response to the operation result read instruction being received from the host device, the calculation result is read from the externally accessible area of the second storage unit and transmitted to the host device.
Semiconductor memory device. The interface unit
The code received from the host device is stored in the externally accessible area of the second storage unit, and the code is stored in the externally accessible area.
The microprocessor executes the code stored in the externally accessible area of the second storage unit.
The semiconductor memory device according to claim 1. The interface unit
The external accessible area is set, and access control to the second storage unit is performed based on the set information of the external accessible area.
The semiconductor memory device according to claim 1 or 2. The initial value of the information of the externally accessible area is a value indicating that access to the entire memory area of the second storage unit is prohibited.
The semiconductor memory device according to claim 3. An access prohibition information holding unit that holds access prohibition information, which is information for setting an access prohibited area of the second storage unit, and an access prohibition information holding unit.
A wrapper unit for setting an access prohibited area of the second storage unit based on the access prohibited information is further provided.
The semiconductor memory device according to any one of claims 1 to 4. The access prohibition information holding unit includes a ROM that can be written only once.
The access prohibition information is written in the ROM.
The semiconductor memory device according to claim 5. The access prohibition information holding unit is
Includes a circuit for holding the access prohibition information
The access prohibition information is output to the wrapper unit as a signal output from the circuit.
The semiconductor memory device according to claim 5. The wrapper part
When the fetch access signal from the microprocessor is a signal value indicating enable and the address indicated by the instruction fetch signal received from the microprocessor is within the access prohibited area, the access of the second storage unit is performed. Access control to the second storage unit is performed so as to allow access to the prohibited area.
The semiconductor memory device according to any one of claims 5 to 7. An access prohibition information holding unit that holds access prohibition information, which is information for setting an access prohibited area of the second storage unit, and an access prohibition information holding unit.
A wrapper unit for setting an access prohibited area of the second storage unit based on the access prohibited information is further provided .
Before Symbol wrapper part,
Access control to the second storage unit is performed based on the access prohibition information and the information of the external accessible area set by the interface unit.
The semiconductor memory device according to claim 1 or 2. The wrapper part
When it is determined that the address requesting access from the interface unit to the second storage unit is an address in the external accessible area and within the access prohibited area, the second storage unit Prohibit all access to,
The semiconductor memory device according to claim 9. The interface unit
When a command for accessing the entire memory area of the second storage unit is received from the host device, a response indicating that the data stored in the second storage unit cannot be normally read is sent to the host device. Send,
The semiconductor memory device according to any one of claims 1 to 10. With the host device
A semiconductor memory system comprising the semiconductor memory device according to any one of claims 1 to 11.

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