JP5380392B2 - Semiconductor device, bus interface device, and computer system - Google Patents

Description

  The present invention relates to a microprocessor capable of protecting confidential information inside a processor with an external bus interface.

  In Patent Document 1, a security circuit is provided between a memory interface circuit and a memory in order to limit data access to the memory, and monitoring whether the memory access is performed in a correct procedure. This security circuit is provided with a key address, and when access occurs in a specific procedure corresponding to this key address, the range that can be accessed to the memory space is expanded, or memory that is not used for predicted memory access It was possible to protect the space and prevent data transfer. Further, there has been a proposal that the read data is not guaranteed when an access to an address for which the memory protection function is not released occurs.

JP 2001-306400 A

  Conventionally, the protection function is only for the external memory space, and the data in the processor internal memory is not guaranteed. Further, if this function is installed in the entire memory space inside the processor, the redundant logic increases, leading to an enlargement of the processor.

  Moreover, since the memory protection is accepted or rejected by hardware depending on the address issue order to the memory space, the versatility is poor.

  In addition, because a processor without a protection function can read and modify the internal registers and local memory from the external bus, confidential data such as encryption keys can be browsed or developed software can be copied. There was sex.

  The present invention has been made in view of such a problem, and an object thereof is to prevent unauthorized access using a general-purpose bus through which a processor communicates with an external device.

  The processor according to the present invention updates an access control device that controls data transfer between a general-purpose bus outside the processor, such as a PCI bus, and an internal bus of the processor, a TLB in which an accessible range is stored, and the contents of the TLB A TLB control circuit is provided.

  The contents of the TLB are updated by a TLB control circuit that updates the TLB only by access from the inside of the processor, and the updated contents are referred to from the access control circuit by access from a general-purpose bus outside the processor such as a PCI bus.

  In response to a request from the access control circuit, the TLB responds to the access control circuit as to whether or not it is an accessible area, and based on the result, decides whether to issue a request to the internal bus or discard it, and protects confidential information inside the processor To do.

  By applying the present invention, it is possible to protect confidential information inside the processor and the contents of an external memory such as a local memory or a flash memory connected to the processor and prevent unauthorized reading from the outside.

It is the block diagram which connected the media processor which mounts this invention to the PCI bus. It is the block diagram which connected the media processor carrying this invention to a general purpose bus | bath. It is the block diagram which connected DSP which mounts this invention to the general purpose bus. It is a block diagram which connects an external bus and an internal bus using TLB. It is a block diagram which connects an external bus and an internal bus using an access control bit group. It is a flowchart figure of access control. It is a block diagram inside TLB. It is a block diagram inside TLB which has an address translation function in TLB. It is a figure which shows the allocation to a memory or a register map. It is a block diagram of access control using BAR. It is a block diagram of access control using BAR. It is the block diagram which used the media processor carrying this invention for STB.

  Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration example of a computer system to which the present invention is applied. For simplification, portions not directly related to the application of the present invention are omitted.

  The processor bus 2 is used to connect to the main CPU 1 and the north bridge 3 having a high-speed bus interface. The north bridge 3 is connected to the main storage device 5 by the memory bus 4 and is connected to the south bridge 7 having a low-speed bus interface and the inter-bridge connection bus 6.

  The south bridge 7 is connected to the PCI bus 8, and two media processors 100 a and 100 b are connected on the PCI bus 8. Each media processor 100a, 100b is connected to local memory 201a, 201b using local memory buses 200a, 200b, respectively. Further, the flash memory 203a and 203b are connected using the flash memory buses 202a and 202b. The media processor and its corresponding part in this embodiment are configured with one chip, but can be realized with a plurality of chips.

  The media processor 100a uses an internal bus 109 to access a processor core 101 for performing computation, a PCI bus interface 102 for connection to the PCI bus 8, a coprocessor 103 for assisting computation of the processor core 101, and access to a local memory. A memory interface 104 for controlling, an I / O interface 105 for controlling the I / O interface, and a cryptographic processing arithmetic circuit 108 for performing cryptographic processing are connected. Examples of cryptographic processing include Multi2 / DES. The coprocessor 103 is connected to the coprocessor memory 106 using a coprocessor memory bus 107.

  Further, the PCI bus interface 102 has a PCI bus interface PIO register 116 for setting operation, the processor core 101 has a processor core PIO register 117, the coprocessor 103 has a coprocessor PIO register 118, and the memory interface 104 has a memory interface PIO. The register 119, the I / O interface 105 has an I / O interface PIO register 120, and the cryptographic processing arithmetic circuit 108 has a cryptographic processing arithmetic circuit PIO register 121.

  When the media processor 100 a is booted, the I / O interface 105 loads a program from the flash memory 203 a and the processor core 101 executes the program through the internal bus 109, so that the TLB control circuit 112 in the PCI bus interface 102 is first executed. Generate a TLB rewrite request. In response to the request, the TLB control circuit 112 changes the inside of the TLB 111 by issuing a TLB update signal 115 to the TLB 111, the inside of the processor that can be accessed at startup, the local memory 201a of the media processor 100a, and the flash memory 203a. Only a specific area of all the areas can be accessed.

  When a read access from the main CPU 1 to the media processor 100 a occurs, the request signal is sent to the north bridge 3 and the south bridge 7 and is received by the PCI bus interface 102 inside the media processor 100 a through the PCI bus 8. Upon receiving the request signal, the access control circuit 110 inquires to the TLB 111 through the TLB determination signal 113 whether the read address is accessible. The TLB 111 that received the signal compares it with the set address, and returns a pass / fail result to the access control circuit through the TLB pass / fail signal 114. If the response indicates that access is possible, a request is issued to the internal bus 109, the target data is extracted, and the data is returned to the main CPU via the PCI bus 8 via the south bridge 7 and the north bridge 3. However, if it is a read request to an inaccessible area, the access control circuit 110 returns indefinite data to the main CPU 1.

  When a write request is issued from the main CPU 1 to the media processor 100a, it is sent to the PCI bus interface 102 through the same route as the read request. The access control circuit 110 that has received the write request inquires the TLB 111 through the TLB determination signal 113 whether the address to be written is accessible. The TLB 111 that has received the signal compares it with the internal address, and returns a pass / fail result to the access control circuit through the TLB pass / fail signal 114. This is a case where the response indicates that access is possible, and a request is issued to the internal bus 109 to rewrite. However, if it is a write request to an inaccessible area, the access control circuit 110 discards the request.

  Further, read requests and write requests from the media processor 100b, which is another PCI device, are determined in the same manner as the access from the main CPU 1, and access restriction is performed.

  In particular, the TLB 111 can be changed only from the processor core 101 and cannot be changed from the main CPU 1 or another PCI device.

  FIG. 2 is a configuration diagram of the media processor 126 having the general-purpose bus interface 123. The general-purpose bus interface is a bus having control signals such as an address bus, a data bus, and a request. By issuing a read request and an address, the data of the requested address can be obtained on the data bus. Also, by issuing a write request and an address and transmitting the data to be written to the data bus, the data of the address to be changed Can be rewritten.

  The media processor 126 has an internal bus 109, and the processor core 101, coprocessor 103, memory interface 104, I / O interface 105, cryptographic processing arithmetic circuit 108, and general-purpose bus interface 123 are connected to the internal bus 109. The coprocessor 103 is connected to the coprocessor memory 106 using the coprocessor memory bus 107, the memory interface 104 is connected to the local memory 201 using the local memory bus 200, and the I / O interface 105 is using the flash memory bus 202. To the flash memory 203.

  Furthermore, the general-purpose bus interface 123 has a general-purpose bus interface PIO register 116 for performing operation settings, the processor core 101 has a processor core PIO register 117, the coprocessor 103 has a coprocessor PIO register 118, and the memory interface 104 has a memory interface PIO. The register 119, the I / O interface 105 has an I / O interface PIO register 120, and the cryptographic processing arithmetic circuit 108 has a cryptographic processing arithmetic circuit PIO register 121.

  When the media processor 126 boots, the I / O interface 105 sends the boot program from the flash memory 203 to the processor core 101 via the internal bus 109. According to the program, a TLB rewrite request is generated from the processor core 101 to the TLB control circuit 112 using the internal bus 109, and the TLB 111 in the general-purpose bus interface 123 is updated. By the update, it is made possible to access only a specific area among the entire area of the local memory 201 and the flash memory 203 that the inside of the processor accessible at the time of startup and the media processor 102 has.

  The general-purpose processor 125 that communicates with the media processor 126 using the general-purpose bus 122 is connected to the general-purpose processor flash memory 127 using the general-purpose processor flash memory bus 128, and the general-purpose processor local memory 129 and the general-purpose processor. In this configuration, the local memory bus 130 is used for connection. In response to a read request from the general-purpose processor 125 to the media processor 126, the access control circuit 124 inquires to the TLB 111 through the TLB determination signal 113 whether the read address is accessible. The TLB 111 that received the signal compares it with the set address, and returns a pass / fail result to the access control circuit through the TLB pass / fail signal 114. When the response indicates that access is possible, a request is issued to the internal bus 109, the target data is extracted, and the response is sent to the general-purpose processor 125 through the general-purpose bus 122.

  Further, when a write request is issued from the general-purpose processor 125 to the media processor 126, it is determined whether or not it is an accessible area as with the read request. As a result of the determination, if the access is possible, the target address is rewritten through the internal bus 109. However, in the access prohibited area, the write data is not written but discarded.

  In particular, the TLB 111 can be changed only from the processor core 101 and cannot be changed from the general-purpose processor 125 at all.

  FIG. 3 shows an embodiment in which the present invention is applied to a digital signal processor (hereinafter referred to as DSP) 131 dedicated to computation.

  The DSP 131 has an internal bus 109, and a processor core 101, a memory interface 104, an I / O interface 105, and a general-purpose bus interface 123 are connected to the internal bus 109. The memory interface 104 is connected to the local memory 201 using the local memory bus 200, and the I / O interface 105 is connected to the flash memory 203 using the flash memory bus 202.

  The general-purpose bus interface 123 is a general-purpose bus interface PIO register 116 for performing operation settings, the processor core 101 is a processor core PIO register 117, the memory interface 104 is a memory interface PIO register 119, and the I / O interface 105 is an I / O interface. Each has an interface PIO register 120.

  A general-purpose processor 125 serving as a host CPU is connected to the general-purpose bus interface 122, a general-purpose processor flash memory 127 is connected to the general-purpose processor 125 using a general-purpose processor flash memory 128, and a general-purpose processor local memory 129 is connected using a general-purpose processor local memory bus 130. The general-purpose processor 125 can normally access all the DSPs 131. At this time, the DSP 131 loads and boots a program from the general-purpose processor flash memory, and also performs initial setting of the DSP 131. When the initial setting is completed, the DSP 131 sets the TLB 111 in the general-purpose bus interface 123 from the flash memory 203 through the I / O interface 105 from the internal bus 109. Upon receiving the TLB rewrite request from the processor core 101, the TLB control circuit 112 changes the inside of the TLB 111 by issuing a TLB update signal 115 to the TLB 111, and the local memory 201 possessed by the DSP 131 Only a specific area of the entire area of the flash memory 203 can be accessed.

  In response to a read request from the general-purpose processor 125 to the DSP 131, the access control circuit 124 inquires the TLB 111 through the TLB determination signal 113 as to whether or not the read address is accessible. The TLB 111 that received the signal compares it with the set address, and returns a pass / fail result to the access control circuit through the TLB pass / fail signal 114. When the response indicates that access is possible, a request is issued to the internal bus 109, the target data is extracted, and the response is sent to the general-purpose processor 125 through the general-purpose bus 122.

  Further, when a write request is issued from the general-purpose processor 125 to the DSP 131, it is determined whether or not it is an accessible area as with the read request. As a result of the determination, if the access is possible, the target address is rewritten through the internal bus 109. However, in the access prohibited area, the write data is not written but discarded.

  FIG. 4 shows a configuration diagram in which the present invention is applied to a bus interface circuit for connecting the external bus 140 and the internal bus 141.

  The access control circuit 124 is connected to the external bus 140 and the internal bus 141, and performs data transfer between both buses. In order to check whether access from the access control circuit 124 is possible, the query address 142 is used to connect to the TLB 111. The TLB 111 that has received it determines whether or not it is accessible, and sends a TLB pass / fail signal 143 that is the result and an address 144 that is the result of address conversion using the TLB 111 to the access control circuit 124. Using the result, the access control circuit outputs a request to the internal bus 141. Further, since the TLB 111 can be rewritten only through the internal bus 141, the TLB control circuit 147 receives a TLB update request from the internal bus 141, and an address for notifying which entry in the TLB update signal 145 and the TLB 111 is changed. It is sent to the TLB 111 through the entry address 146. It is possible to update the inside of the TLB 111 based on the sent address and restrict access.

  Here, the TLB update request is issued from the processor core 101. The TLB update request is also transmitted to the access control circuit, but is determined as a request to either the access control circuit or the TLB control circuit from the address of the internal bus.

  FIG. 5 shows an embodiment in which the present invention is applied by a method different from that shown in FIG. The access control circuit 150 is connected to the external bus 151 and the internal bus 152, and performs data transfer between both buses. The permission bit control circuit 161 accepts a request from a processor core connected to the internal bus 152 at any time, and a request is sent when it is desired to change the access restriction from the external bus 151.

  First, an address is sent from the external bus 151 to the access control circuit 150 and the address decoder 154 inside the access determination circuit 153 by a read or write request. An area selection signal 155 is sent to the selector 156 based on the address sent to the address decoder 154. One of the permission bit signals always sent from the permission bit group 160 to the selector 156 through the permission bit signals 158 and 159 is selected by the area selection signal 155 and the result is sent to the access control circuit 150 through the access pass / fail signal 157. Send. Here, the bit group means bit information stored in the register group. Upon receipt of the signal, the access control circuit 150 determines whether to discard the requested address, and if it is an accessible area, generates a request to the internal bus 152.

  Further, the rewriting of the permission bit group 160 is performed by sending a rewriting request generated from the internal bus 152 to the permission bit control circuit 161 and changing the permission bit group 160 through the permission bit change signals 162 and 163 to the bits to be changed according to the request. In particular, the permission bit group 160 can be changed only from the internal bus 152 and cannot be changed from the external bus 151 at all.

  FIG. 6 is a flowchart of access control. First, the media processor is activated (400) and TLB setting 401 is performed. Data is read from the TLB initial value 402 and the TLB is set. The initial setting value is stored in a nonvolatile memory such as a flash memory. After the TLB setting 401, the media processor reads the program 404 stored in the flash memory in the program reading 403 like the TLB initial value 402 to the local memory of the media processor itself.

  It is determined whether or not an external access 405 has occurred during execution of the program. If it has not occurred, the program execution is continued. If it has occurred, TLB reference 406 is performed. As a result of the TLB reference 406, it is determined whether or not the access is a permitted area 407. If it is not a permitted area, the request is discarded, the program continues to be executed, and waiting until an external access 405 occurs. To do. If it is an access to the permitted area, data transfer 408 is performed. If it is a read request, data is read from the memory 409, and if it is a write request, data is written to the memory 409. At this time, the memory 409 is a local memory, an internal memory, or an internal register.

  The internal structure of the TLB is shown in FIG. First, the TLB update signal 115 is received to rewrite information in the TLB 111. The TLB update signal 115 includes TLB entry data 300 and a TLB address 301. The signal of the TLB address 301 is transmitted to the decoder 302, and the entry of the TLB 111 to be rewritten by the decoder 302 is determined. The TLB entry data 300 is written to the address, and the valid bit 303, the virtual page number 304, and the access size 305, which are the contents of the TLB 111, are updated.

  The updated comparator 310 in the TLB 111 compares the access address 307 due to access from the outside with the contents stored in the TLB 111. At this time, the valid bit 303 is sent to the comparator 310 through the valid bit signal 311 and is compared only with a valid entry. The virtual page number 304 of the valid entry indicates the start address of the address that is permitted to be accessed, and the value obtained by adding the access size 305 indicates the end address. Therefore, these signals are sent to the comparator 310 as a virtual page number signal 308 and an access size signal 309, respectively, and it is determined whether or not the access address 307 is within the range, and a comparison result 312 is output for each entry. To do.

  The comparison result 312 output for each entry is ORed by the OR circuit 313 and an access determination signal 314 is returned. Access permission or disapproval is determined by such a circuit.

  Further, FIG. 8 shows the internal structure of the TLB when it has an address conversion function. In order to rewrite information in the TLB 111, there is a TLB update signal 115, which is a signal of the TLB entry data 300 and the TLB address 301. The entry of the TLB 111 where the signal of the TLB address 301 is to be rewritten by the decoder 302 is determined. The TLB entry data 300 is written to the address, and the valid bit 303, virtual page number 304, access size 305, and physical page number 316, which are the contents of the TLB 111, are updated. In the present embodiment, the parameter is selected as a parameter to be updated. However, it is not always necessary to update the parameter.

  For example, when a valid bit is not selected, it is conceivable that all the same data is initially placed in the physical page number and the access size, and the access size can be accessed in the entire area.

  In addition, the physical page number and access size indicate the start point and end point, and describe from where to where it can be accessed. If these parameters are not selected, the fixed area can be accessed from the physical page area. It is also possible to do.

  The updated TLB 111 is compared with the contents of the TLB 111 by the comparator 310 using the access address 307 by external access. At this time, the valid bit 303 is sent to the comparator 310 through the valid bit signal 311 and only the valid entry is compared. The virtual page number 304 of the valid entry indicates the start address of the address that is permitted to be accessed, and the value obtained by adding the access size 305 indicates the end address. Therefore, these signals are sent to the comparator 310 as a virtual page number signal 308 and an access size signal 309, respectively, and the comparator 310 determines whether the access address 307 is accessing within the range, and the comparison result 312 is obtained for each of the comparison results 312. Output for each entry. This signal is sent to the OR circuit 313 and the selector 318 that selects the physical page number of the corresponding entry. The comparison result 312 sent to the OR circuit 313 is ORed and an access determination signal 314 is returned. The selector 318 selects one of n physical page numbers (PPN) 316 and outputs a post-conversion address 319. This conversion is performed with an address on the external bus when an access from the external bus occurs. Since the address is different from the internal address of the processor on which the TLB 111 is mounted, it is necessary to convert the address. In order to eliminate this bottleneck in address conversion, it is possible to provide a conversion function to a physical page number and to convert the address into an address that can be accessed inside the processor at high speed.

  A case where an accessible area and an inaccessible area are set in the TLB 111 is shown in FIG. The local memory 334 is set as a referenceable area by an entry A330 in the TLB 111. Further, the local memory 336 is set as a referenceable area by the entry B331. Since the local memory 335 and the local memory 337 are not set as referenceable areas by the TLB 111, access from the outside is blocked.

  Further, the area of the coprocessor memory 338 can be referred to by the entry C332. However, since the area of the coprocessor memory 339 is not set as a referenceable area by the TLB 111, access from the outside is blocked. Similarly, the register map 341 can be referred to by the entry D333 in the register map area. The register map 340 and the register map 342, which are the space before and after the register map 341, are non-referenceable areas, and access from outside the processor is blocked and cannot be read or written.

  However, the inaccessible area is blocked only from the outside, and can be accessed without restriction from the inside of the processor.

  FIG. 10 shows a method of limiting the accessible area of the memory space using a PCI base address register (hereinafter referred to as BAR).

  First, an outline of a method for limiting the accessible area of the memory space using the PCI BAR will be described.

  A PCI device has a memory space required by the device, and the size varies depending on each device. In the current PCI standard, PCI has a memory space of 4 GB, but the memory space of the PCI device is allocated on the space. For example, when the PCI device A has a memory space of 0x4000, if the PCI device A is allocated from 0x1000 of the PCI space, it is possible to operate the memory space of the PCI device A by accessing the PCI buses 0x1000 to 0x4fff. Here, the BAR is used when setting the memory space, and allows the device side to change the size of its own BAR as necessary. Specifically, when the PCI device has 128 MB of memory, a space of 128 MB can be originally allocated to the PCI space. However, by intentionally allocating only 64 MB (the implementation method is shown in FIGS. 10 and 11), it is possible to hide the remaining 64 MB from the PCI.

  For example, when a request occurs on the PCI bus, each PCI device compares the address of the request with the contents of the BAR, and replies when it is determined that the address is addressed to itself. That is, the PCI interface of the PCI device compares the set BAR with the request address to determine whether to access its own memory space. However, if the BAR is set to have only 64 MB in advance, even if 65 MB is accessed, it is determined that it is not access to itself.

  Next, a specific method for restricting the accessible area of the memory space using the PCI BAR will be described.

  A BAR setting signal 350 for designating a BAR area input from the outside of the processor is held by the data holding register 354 when the power is turned on or a reset is generated by a software reset or an external reset button. When the reset signal 351 indicates a reset period when the logical value is 1, it is input to the AND circuit 352 together with the clock signal 353 to obtain a logical product, and when the reset signal 351 takes the logical value 1, the data holding register 354 Update. As for the retained data 355, data to be sent to the BAR is determined by the decoder 356.

  The determined signals send decode results 358, 359, 360, and 361 to the AND circuit 362 for the n-th bit 364, n + 1-th bit 365, n + 2-th bit 366, and n + 3-th bit 367 of the BAR 363, respectively. These signals and the BAR change signal 357 are logically ANDed, and the result is reflected in the nth bit 364, the n + 1th bit 365, the n + 2th bit 366, and the n + 3th bit 367 of the BAR363.

  In the case of the method shown in FIG. 10, when all the logical values 1 are output from the decoder 356 to the decoding results 358, 359, 360, and 361, the upper bits including the n-th bit 364 are changed by the BAR change signal 357. It is possible. This area is the minimum area allocated to the PCI space, and the memory space has 2 ^ n. In this way, it is possible to allocate a maximum of 2 ^ (n + 3) areas to the PCI space. A processor capable of such setting has 2 ^ (n + 3) local memories, so that 2 ^ n can be set in BAR. In this case, addresses 0 to (2 ^ n-1) can be referred from the PCI space, but addresses (2 ^ n) to (2 ^ (n + 3) -1) are not assigned to the PCI space. It is invisible from external devices and cannot be accessed. Access can be suppressed using such a method.

  FIG. 11 shows a case where the data holding register 354 of FIG. 10 is changed from the inside of the processor. A BAR setting signal 368 for designating a BAR area from the data holding register 354 or the processor is selected by the selection signal 370 using the selector 369. The data holding register 354 is updated again with the selected data. As for the retained data 355, data to be sent to the BAR is determined by the decoder 356. The determined signals send decode results 358, 359, 360, and 361 to the AND circuit 362 for the n-th bit 364, n + 1-th bit 365, n + 2-th bit 366, and n + 3-th bit 367 of the BAR 363, respectively. These signals and the BAR change signal 357 are logically ANDed, and the result is reflected in the nth bit 364, the n + 1th bit 365, the n + 2th bit 366, and the n + 3th bit 367 of the BAR363.

  In other words, in a PCI bus interface having a function of fixing a specific bit of the base address register to a logical value 0, the PCI device has a bit by fixing a specific base address register bit to a logical value of 0. A memory space smaller than the local memory is allocated to the memory space on the PCI bus, and the PCI device having the local memory itself can access the entire space, but other PCI devices can access the memory space on the PCI bus. Only the small memory space allocated to can be accessed.

  The BAR can also be changed by such a method, and an inaccessible area can be designated.

  FIG. 12 shows a set top box (hereinafter referred to as STB) equipped with a media processor employing the present invention.

  The STB 380 is mounted with a media processor 100, a local memory 201 using a local memory bus 200, a flash memory 203 using a flash memory bus 202, and a service port 382 using a general-purpose bus 381. Further, since this system is an STB, a video input / output 386 for inputting / outputting video signals, an audio input / output 387 for inputting / outputting audio signals, and an encryption storage card for holding an encryption key used for decoding video signals, etc. It has an interface signal 388, a high-speed digital bus 389 for performing high-speed data communication with an external storage device, and a transport stream interface signal 390 for receiving a video signal from the BS digital tuner.

  The service port 382 is used to connect the maintenance terminal 391 at the time of failure diagnosis, and is connected to the service port 382 using the general-purpose interface signal 383. The general-purpose interface signal 383 is connected to the maintenance processor 392, and the maintenance processor itself is connected to the local memory 394 using the local memory bus 393.

  When the maintenance terminal 391 is connected, the memory inside the STB is not in a readable / writable state, and only the accessible area 385 on the local memory can be read / written. The inaccessible area 384 on the local memory is accessible only from the media processor 100 mounted on the STB 380, and when performing maintenance, the accessible area 385 is used to communicate with the media processor 100.

  For this reason, a terminal other than the maintenance terminal is connected to the service port 382, and the encryption key used for decryption, which is important data in the media processor 100, and the software for operating the media processor 100 can be protected.

  In addition, unauthorized access from the outside can block access to the encryption key and the memory that stores software, which are confidential matters inside the media processor, and the access range can be freely changed by the application. . In this embodiment, the access restriction is applied to the physical area, but the logical area may be restricted.

  The present invention is not limited to the above-described embodiment, and it goes without saying that the present invention can be modified and implemented without departing from the gist, regardless of the application field.

DESCRIPTION OF SYMBOLS 1 ... Main CPU, 3 ... North bridge, 5 ... Main memory, 7 ... South bridge, 100 ... Media processor, 101 ... Processor core, 102 ... PCI bus interface, 110 ... Access control circuit, 111 ... TLB, 112 ... TLB Control circuit, 125 ... general-purpose processor, 131 ... digital signal processor, 201 ... local memory, 203 ... flash memory, 303 ... valid bit, 304 ... virtual page number, 305 ... access size, 316 ... physical page number

Claims (14)

A processor core for performing an operation; an external bus interface for connecting to an external bus; a memory interface for controlling access to a local memory; and an internal bus connecting the processor core, the external bus interface, and the memory interface; A semiconductor device comprising:
The external bus interface includes an access control circuit that receives a request from the external bus, a TLB that is connected to the access control circuit and determines whether the external bus can be accessed, and a TLB that rewrites the TLB in response to a request from the processor core. Having a control circuit,
The access control circuit that has received the request from the external bus transmits a TLB determination signal inquiring whether the address of the request is an address within an access permission range set in the TLB, to the TLB,
The TLB searches whether the address of the request is an address within an access permission range set in the TLB, and returns a TLB pass / fail signal indicating whether access is possible to the access control circuit,
The access control circuit grants access to the internal bus when the TLB pass / fail signal indicates that access is possible, and grants the request when the TLB pass / fail signal indicates that access is not allowed. Destroy,
Further, the TLB can be set only from the internal bus, and has a function of converting to an address of the internal bus when accessed from the external bus,
The processor core issues a TLB update request, which is a request for updating the TLB setting, to the internal bus,
The TLB control circuit receives the TLB update request issued from the processor core from the internal bus, and notifies the TLB update signal and which entry in the TLB is changed based on the received TLB update request. To the TLB, and an entry address for
The TLB updates the inside of the TLB based on the TLB update signal and the entry address transmitted from the TLB control circuit,
The TLB update request is transmitted in common to the access control circuit and the TLB control circuit, and it is determined from the address of the internal bus whether the TLB update request is a request to the access control circuit or the TLB control circuit. A semiconductor device that is characterized in that: The semiconductor device according to claim 1,
The TLB control circuit is capable of changing the access permission range based on a TLB update request output from the processor core. The semiconductor device according to claim 1,
The semiconductor device, wherein the external bus is a PCI bus. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the external bus is a general-purpose bus. The semiconductor device according to claim 1,
A cryptographic operation circuit connected to the internal bus for performing cryptographic processing;
The semiconductor device characterized in that the access control circuit restricts access to a register that determines a secret key and a cryptographic processing method of the cryptographic operation circuit. The semiconductor device according to claim 1,
The access control circuit permits access to the local memory via the internal bus and the memory interface when the TLB pass / fail signal indicates that access is possible. A bus interface device in a semiconductor device connected to an external bus,
Connected to an internal bus in the semiconductor device, the semiconductor device has a processor core for performing operations,
An access control circuit that receives a request from the external bus, a TLB that is connected to the access control circuit and determines whether the external bus can be accessed, and a TLB control circuit that rewrites the TLB in response to a request from the processor core,
The access control circuit that has received the request from the external bus transmits a TLB determination signal inquiring whether the address of the request is an address within an access permission range set in the TLB, to the TLB,
The TLB searches whether the address of the request is an address within an access permission range set in the TLB, and returns a TLB pass / fail signal indicating whether access is possible to the access control circuit,
The access control circuit grants access to the internal bus when the TLB pass / fail signal indicates that access is possible, and grants the request when the TLB pass / fail signal indicates that access is not allowed. Destroy,
Further, the TLB can be set only from the internal bus, and has a function of converting to an address of the internal bus when accessed from the external bus,
The processor core issues a TLB update request, which is a request for updating the TLB setting, to the internal bus,
The TLB control circuit receives the TLB update request issued from the processor core from the internal bus, and notifies the TLB update signal and which entry in the TLB is changed based on the received TLB update request. To the TLB, and an entry address for
The TLB updates the inside of the TLB based on the TLB update signal and the entry address transmitted from the TLB control circuit,
The TLB update request is transmitted in common to the access control circuit and the TLB control circuit, and it is determined from the address of the internal bus whether the TLB update request is a request to the access control circuit or the TLB control circuit. A bus interface device. The bus interface device according to claim 7, wherein
A decoder for converting an address accessed from the external bus into an address for use in the internal bus;
The access control circuit transmits a request to the internal bus using the address converted by the decoder. The bus interface device according to claim 8, wherein
A register storing a permission bit group indicating whether or not a predetermined address space in the semiconductor device is accessible, and whether or not the address indicated by the access from the external bus is an address of an accessible area in the semiconductor device An access determination circuit for determining
The access determination circuit includes the decoder and a selector connected to the decoder,
Generate an area selection signal from the address converted by the decoder, compare the area selection signal with the permission bit signal output from the register of the permission bit group,
When the area selection signal and the permission bit signal match, an access pass / fail signal indicating that access is possible is output,
The bus interface apparatus, wherein when the area selection signal and the permission bit signal do not match, an access pass / fail signal indicating that access is not allowed is output. The bus interface device according to claim 9, wherein
A permission bit control circuit for updating data stored in the permission bit group;
The bus interface apparatus, wherein the permission bit control circuit is capable of changing data stored in the permission bit group based on a rewrite request signal transmitted via the internal bus. A computer system having a first semiconductor device to which a storage device is connected, a second semiconductor device, and the first semiconductor device and an external bus connecting the second semiconductor device,
The first semiconductor device includes:
A processor core that performs an operation, an external bus interface to be connected to the external bus, a memory interface that controls access to the storage device, and the processor core, the external bus interface, and the memory interface are connected to each other. An internal bus,
When the storage device is accessed from the second semiconductor device,
The first semiconductor device determines whether the access address is an address within an access permission range set in advance in the TLB in the first semiconductor device;
When the address of the access is included in the address within the access permission range, permit access to the storage device via the internal bus;
If the address of the access is not included in the address within the access permission range, the access is discarded and access to the storage device is not permitted,
Further, the TLB can be set only from the internal bus, and has a function of converting to an address of the internal bus when accessed from the external bus,
The processor core issues a TLB update request, which is a request for updating the TLB setting, to the internal bus,
The TLB control circuit receives the TLB update request issued from the processor core from the internal bus, and notifies the TLB update signal and which entry in the TLB is changed based on the received TLB update request. And an entry address for the TLB,
The TLB updates the inside of the TLB based on the TLB update signal and the entry address transmitted from the TLB control circuit,
The TLB update request is transmitted in common to the access control circuit and the TLB control circuit, and it is determined from the address of the internal bus whether the TLB update request is a request to the access control circuit or the TLB control circuit. A computer system characterized by that. 12. A computer system according to claim 11, comprising:
The external bus interface includes an access control circuit that receives a request from the external bus, a TLB that is connected to the access control circuit and determines whether the external bus can be accessed, and a TLB that rewrites the TLB in response to a request from the processor core. Having a control circuit,
The access control circuit that has received the request from the external bus transmits a TLB determination signal inquiring whether the address of the request is an address within an access permission range set in the TLB, to the TLB,
The TLB searches whether the address of the request is an address within an access permission range set in the TLB, and returns a TLB pass / fail signal indicating whether access is possible to the access control circuit,
The access control circuit grants access to the internal bus when the TLB pass / fail signal indicates that access is possible, and grants the request when the TLB pass / fail signal indicates that access is not allowed. A computer system characterized by discarding. A semiconductor device having a module having an arbitrary function, an external bus interface to be connected to an external bus, and an internal bus connecting the module and the external bus interface,
When there is access to the module from another device connected to the external bus,
The semiconductor device determines whether the access address is an address within an access permission range set in advance in the TLB in the semiconductor device;
When the access address is included in an address within the access permission range, permit access to the module via the internal bus;
If the address of the access is not included in the address within the access permission range, the access is discarded and access to the storage device is not permitted,
Further, the TLB can be set only from the internal bus, and has a function of converting to an address of the internal bus when accessed from the external bus,
The processor core issues a TLB update request, which is a request for updating the TLB setting, to the internal bus,
The TLB control circuit receives the TLB update request issued from the processor core from the internal bus, and notifies the TLB update signal and which entry in the TLB is changed based on the received TLB update request. And an entry address for the TLB,
The TLB updates the inside of the TLB based on the TLB update signal and the entry address transmitted from the TLB control circuit,
The TLB update request is transmitted in common to the access control circuit and the TLB control circuit, and it is determined from the address of the internal bus whether the TLB update request is a request to the access control circuit or the TLB control circuit. A semiconductor device. A semiconductor device according to claim 13,
A storage device is connected to the semiconductor device,
A memory interface for controlling access to the storage device;
When the access address is included in an address within the access permission range, the semiconductor device permits access to the storage device via the internal bus and the memory interface.

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