JP6958240B2

JP6958240B2 - Circuit boards, wireless communication devices, and how to make circuit boards

Info

Publication number: JP6958240B2
Application number: JP2017211083A
Authority: JP
Inventors: 渉土井; 一樹江島; 理山口
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2017-10-31
Filing date: 2017-10-31
Publication date: 2021-11-02
Anticipated expiration: 2037-10-31
Also published as: JP2019083285A

Description

本発明は、電子部品が実装された回路基板、回路基板を備えた無線通信デバイス、およびその回路基板の作製方法に関する。 The present invention relates to a circuit board on which electronic components are mounted, a wireless communication device provided with the circuit board, and a method for manufacturing the circuit board.

回路基板を有するデバイスが小型化すればするほど、回路基板の大きさや厚さが小さくなるとともに、回路基板に形成される導体パターンが高密度に設けられる。そのため、例えば特許文献１に記載するように、回路基板の平面視（厚さ方向視）で、回路基板に実装される電子部品に導体パターンの一部が重なる。 The smaller the device having the circuit board, the smaller the size and thickness of the circuit board, and the higher the density of the conductor patterns formed on the circuit board. Therefore, for example, as described in Patent Document 1, a part of the conductor pattern overlaps with the electronic component mounted on the circuit board in the plan view (thickness direction view) of the circuit board.

国際公開第２０１６／０９８３７９号公報International Publication No. 2016/098379

電子部品が実装される回路基板の主面とは反対側の主面に、導体パターンが高密度に設けられることがある。しかし、この場合、その導体パターンのパターンレイアウトおよび実装方法との関係によっては、電子部品の実装不良が発生することがあった。 Conductor patterns may be provided at high density on the main surface opposite to the main surface of the circuit board on which electronic components are mounted. However, in this case, depending on the relationship between the pattern layout of the conductor pattern and the mounting method, mounting defects of electronic components may occur.

そこで、本発明は、電子部品が実装される主面とは反対側の主面に導体パターンが形成されている回路基板において、その導体パターンを高密度に設けつつ、電子部品の実装不良の発生を抑制することを課題とする。 Therefore, according to the present invention, in a circuit board in which a conductor pattern is formed on a main surface opposite to the main surface on which an electronic component is mounted, a poor mounting of the electronic component occurs while the conductor pattern is provided at a high density. The problem is to suppress.

上記技術的課題を解決するために、本発明の一態様によれば、
厚さ方向に対向する第１および第２の主面を備える基板と、
前記基板の第１の主面に設けられた導体パターンと、
前記基板の第２の主面に設けられた複数の電極パッドと、
前記複数の電極パッドに対してそれぞれ対向して接続される複数の実装用電極を備える電子部品と、を有し、
前記導体パターンは、前記基板の平面視で、前記複数の実装用電極にはいずれも重ならず、前記電子部品の部分に重なる部分を有することを特徴とする、回路基板が提供される。 In order to solve the above technical problems, according to one aspect of the present invention,
A substrate having first and second main surfaces facing each other in the thickness direction,
A conductor pattern provided on the first main surface of the substrate and
A plurality of electrode pads provided on the second main surface of the substrate, and
An electronic component having a plurality of mounting electrodes connected to the plurality of electrode pads facing each other.
Provided is a circuit board, wherein the conductor pattern has a portion that does not overlap with the plurality of mounting electrodes but overlaps with a portion of the electronic component in a plan view of the substrate.

また、本発明の別態様によれば、
回路基板と、
前記回路基板に搭載されるアンテナと、を含み、
前記回路基板が、
厚さ方向に対向する第１および第２の主面を備える基板と、
前記基板の第１の主面に設けられた導体パターンと、
前記基板の第２の主面に設けられた複数の電極パッドと、
前記複数の電極パッドに対してそれぞれ対向して接続される複数の実装用電極を備える電子部品と、を有し、
前記導体パターンは、前記基板の平面視で、前記複数の実装用電極にはいずれも重ならず、前記電子部品の部分に重なる部分を有し、
前記導体パターンは、前記アンテナの一部であることを特徴とする、無線通信デバイスが提供される。 Further, according to another aspect of the present invention.
With the circuit board
Including an antenna mounted on the circuit board
The circuit board
A substrate having first and second main surfaces facing each other in the thickness direction,
A conductor pattern provided on the first main surface of the substrate and
A plurality of electrode pads provided on the second main surface of the substrate, and
An electronic component having a plurality of mounting electrodes connected to the plurality of electrode pads facing each other.
The conductor pattern has a portion that does not overlap with the plurality of mounting electrodes but overlaps with the portion of the electronic component in a plan view of the substrate.
A wireless communication device is provided in which the conductor pattern is a part of the antenna.

さらに、本発明の異なる態様によれば、
複数の実装用電極を備える電子部品が実装された回路基板の作製方法であって、
厚さ方向に対向する第１および第２の主面を備え、前記第１の主面に導体パターンが設けられているとともに、前記第２の主面に複数の電極パッドが設けられた基板を用意し、
前記複数の実装用電極が前記電極パッドに対向するように、前記電子部品を前記基板上に配置し、
前記電子部品を前記基板に向かって押圧することにより、前記複数の実装用電極を前記電極パッドに圧着し、
前記導体パターンは、前記基板の平面視で、前記複数の実装用電極にはいずれも重ならず、前記電子部品の部分に重なる部分を有することを特徴とする、回路基板の製造方法が提供される。 Further, according to different aspects of the invention.
A method for manufacturing a circuit board on which electronic components having a plurality of mounting electrodes are mounted.
A substrate having first and second main surfaces facing each other in the thickness direction, a conductor pattern provided on the first main surface, and a plurality of electrode pads provided on the second main surface. Prepare and
The electronic components are arranged on the substrate so that the plurality of mounting electrodes face the electrode pads.
By pressing the electronic component toward the substrate, the plurality of mounting electrodes are crimped to the electrode pad.
Provided is a method for manufacturing a circuit board, wherein the conductor pattern has a portion that does not overlap with any of the plurality of mounting electrodes but overlaps with a portion of the electronic component in a plan view of the substrate. NS.

本発明によれば、電子部品が実装される主面とは反対側の主面に導体パターンが形成されている回路基板において、その導体パターンを高密度に設けつつ、電子部品の実装不良の発生を抑制することができる。 According to the present invention, in a circuit board in which a conductor pattern is formed on a main surface opposite to the main surface on which an electronic component is mounted, a poor mounting of the electronic component occurs while the conductor pattern is provided at a high density. Can be suppressed.

本発明の一実施の形態に係る無線通信デバイスの斜視図Perspective view of the wireless communication device according to the embodiment of the present invention. 図１のＡ−Ａ線に沿った無線通信デバイスの断面図Sectional view of the wireless communication device along the line AA of FIG. 無線通信デバイスの等価回路図Equivalent circuit diagram of wireless communication device 無線通信デバイスの端子ブロックの内部構成を示す斜視図Perspective view showing the internal configuration of the terminal block of the wireless communication device 第１の主面側から見た、無線通信デバイスの回路基板の斜視図Perspective view of the circuit board of the wireless communication device as seen from the first main surface side. 第２の主面側から見た回路基板の斜視図Perspective view of the circuit board seen from the second main surface side 第１の主面側から見た、レジストを取り除いた状態の回路基板の斜視図Perspective view of the circuit board with the resist removed as seen from the first main surface side. 端子ブロックと回路基板とを接合する溶融樹脂の塗布位置を示す回路基板の上面図Top view of the circuit board showing the coating position of the molten resin that joins the terminal block and the circuit board. 第２の主面側から見た、レジストを取り除いた状態の回路基板の斜視図Perspective view of the circuit board with the resist removed as seen from the second main surface side. 基板の第２の主面の一部の上面図Top view of a part of the second main surface of the substrate 本実施の形態における、RFICチップを基板に超音波圧着する様子を示す図The figure which shows the state which the RFIC chip is ultrasonically crimped to the substrate in this embodiment. 比較例の回路基板を示す図The figure which shows the circuit board of the comparative example 比較例における、RFICチップを基板に超音波圧着する様子を示す図The figure which shows the state which the RFIC chip is ultrasonically crimped to the substrate in the comparative example. 本発明の別の実施の形態に係る回路基板の部分断面図Partial sectional view of the circuit board according to another embodiment of the present invention. 本発明のさらに別の実施の形態に係る回路基板の部分断面図Partial sectional view of the circuit board according to still another embodiment of the present invention.

本発明の一態様の回路基板は、厚さ方向に対向する第１および第２の主面を備える基板と、前記基板の第１の主面に設けられた導体パターンと、前記基板の第２の主面に設けられた複数の電極パッドと、前記複数の電極パッドに対してそれぞれ対向して接続される複数の実装用電極を備える電子部品と、を有し、前記導体パターンは、前記基板の平面視で、前記複数の実装用電極には重ならず、前記電子部品の部分に重なる部分を有することを特徴とする。 The circuit board of one aspect of the present invention includes a substrate having first and second main surfaces facing each other in the thickness direction, a conductor pattern provided on the first main surface of the substrate, and a second substrate. It has a plurality of electrode pads provided on the main surface of the above, and an electronic component having a plurality of mounting electrodes connected to the plurality of electrode pads so as to face each other, and the conductor pattern is the substrate. It is characterized in that it has a portion that does not overlap with the plurality of mounting electrodes but overlaps with the portion of the electronic component in the plan view of the above.

この態様によれば、電子部品が実装される主面とは反対側の主面に導体パターンが形成されている回路基板において、その導体パターンを高密度に設けつつ、電子部品の実装不良の発生を抑制することができる。 According to this aspect, in a circuit board in which a conductor pattern is formed on a main surface opposite to the main surface on which an electronic component is mounted, a poor mounting of the electronic component occurs while the conductor pattern is provided at a high density. Can be suppressed.

例えば、前記導体パターンが、第１の線状導体部と第２の線状導体部とを含み、前記複数の実装用電極が、第１の実装用電極を含み、前記第１の実装用電極が、前記平面視で、前記第１の線状導体部と前記第２の線状導体部との間に位置してもよい。 For example, the conductor pattern includes a first linear conductor portion and a second linear conductor portion, and the plurality of mounting electrodes include a first mounting electrode and the first mounting electrode. However, in the plan view, it may be located between the first linear conductor portion and the second linear conductor portion.

例えば、前記導体パターンがさらに、第３の線状導体部を含み、前記複数の実装用電極がさらに、第２の実装用電極を含み、前記第２の実装用電極が、前記平面視で、前記第１の線状導体部と前記第３の線状導体部との間に位置し、前記第１の線状導体部が、前記平面視で、前記第１の実装用電極と前記第２の実装用電極との間に位置してもよい。 For example, the conductor pattern further includes a third linear conductor portion, the plurality of mounting electrodes further includes a second mounting electrode, and the second mounting electrode is the plan view. The first linear conductor portion is located between the first linear conductor portion and the third linear conductor portion, and the first linear conductor portion is the first mounting electrode and the second mounting electrode in the plan view. It may be located between the mounting electrode and the mounting electrode.

本発明の別態様の無線通信デバイスは、回路基板と、前記回路基板に搭載されるアンテナと、を含み、前記回路基板が、厚さ方向に対向する第１および第２の主面を備える基板と、前記基板の第１の主面に設けられた導体パターンと、前記基板の第２の主面に設けられた複数の電極パッドと、前記複数の電極パッドに対してそれぞれ対向して接続される複数の実装用電極を備える電子部品と、を有し、前記導体パターンは、前記基板の平面視で、前記複数の実装用電極には重ならず、前記電子部品の部分に重なる部分を有し、前記導体パターンは、前記アンテナの一部であることを特徴とする。 Another aspect of the wireless communication device of the present invention includes a circuit board and an antenna mounted on the circuit board, and the circuit board includes first and second main surfaces facing each other in the thickness direction. The conductor pattern provided on the first main surface of the substrate, the plurality of electrode pads provided on the second main surface of the substrate, and the plurality of electrode pads are connected to each other so as to face each other. The conductor pattern has a portion that does not overlap the plurality of mounting electrodes but overlaps the portion of the electronic component in the plan view of the substrate. However, the conductor pattern is characterized in that it is a part of the antenna.

本発明の異なる態様の回路基板の作製方法は、複数の実装用電極を備える電子部品が実装された回路基板の作製方法であって、厚さ方向に対向する第１および第２の主面を備え、前記第１の主面に導体パターンが設けられているとともに、前記第２の主面に複数の電極パッドが設けられた基板を用意し、前記複数の実装用電極が前記電極パッドに対向するように、前記電子部品を前記基板上に配置し、前記電子部品を前記基板に向かって押圧することにより、前記複数の実装用電極を前記電極パッドに圧着し、前記導体パターンは、前記基板の平面視で、前記複数の実装用電極にはいずれも重ならず、前記電子部品の部分に重なる部分を有することを特徴とする。 The method for manufacturing a circuit board according to a different aspect of the present invention is a method for manufacturing a circuit board on which electronic components having a plurality of mounting electrodes are mounted, and the first and second main surfaces facing each other in the thickness direction are formed. A substrate is prepared in which a conductor pattern is provided on the first main surface and a plurality of electrode pads are provided on the second main surface, and the plurality of mounting electrodes face the electrode pads. By arranging the electronic component on the substrate and pressing the electronic component toward the substrate, the plurality of mounting electrodes are crimped to the electrode pad, and the conductor pattern is formed on the substrate. In a plan view of the above, none of the plurality of mounting electrodes overlaps with each other, but has a portion overlapping with the portion of the electronic component.

以下、本発明の実施の形態について、図面を参照しながら説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の一実施の形態に係る無線通信デバイスを示す斜視図である。図２は、図１に示すＡ−Ａ線に沿った断面図である。そして、図３は、無線通信デバイスの等価回路図である。なお、なお、図中において、Ｘ−Ｙ−Ｚ座標系は、発明の理解を容易にするためのものであって、発明を限定するものではない。 FIG. 1 is a perspective view showing a wireless communication device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along the line AA shown in FIG. FIG. 3 is an equivalent circuit diagram of the wireless communication device. In addition, in the figure, the XYZ coordinate system is for facilitating the understanding of the invention, and does not limit the invention.

本実施の形態の場合、無線通信デバイス１０は、例えばＨＦ帯の周波数で無線通信を行うRFID(Radio-Frequency IDentification)タグであって、回路基板１２と、コイルアンテナ１４とを有する。詳細は後述するが、回路基板１２には、電子部品としてのRFIC（Radio-Frequency Integrated Circuit）チップ１６が実装されている。また、本実施の形態の場合、詳細は後述するが、RFICチップ１６とコイルアンテナ１４との間のインピーダンス整合をとるために、コンデンサチップ１８が回路基板１２に実装されている。なお、RFICチップ１６の内部容量でインピーダンス整合をとることが可能である場合には、コンデンサチップ１８を省略することができる。 In the case of the present embodiment, the wireless communication device 10 is, for example, an RFID (Radio-Frequency IDentification) tag that performs wireless communication at a frequency in the HF band, and has a circuit board 12 and a coil antenna 14. Although details will be described later, an RFIC (Radio-Frequency Integrated Circuit) chip 16 as an electronic component is mounted on the circuit board 12. Further, in the case of the present embodiment, the details will be described later, but the capacitor chip 18 is mounted on the circuit board 12 in order to achieve impedance matching between the RFIC chip 16 and the coil antenna 14. If impedance matching can be achieved with the internal capacitance of the RFIC chip 16, the capacitor chip 18 can be omitted.

このような無線通信デバイス１０は、コイルアンテナ１４を介して、外部の無線通信装置（例えば、リーダ／ライタ装置）と磁界結合を介して通信を行う。例えば、コイルアンテナ１４に外部の無線通信装置からの磁束が鎖交することで、起電力が生じ、その起電力によってRFICチップ１６が駆動する。駆動したRFICチップ１６は、その記憶部に記憶されたデータを、コイルアンテナ１４を介して送信する。 Such a wireless communication device 10 communicates with an external wireless communication device (for example, a reader / writer device) via a coil antenna 14 via a magnetic field coupling. For example, an electromotive force is generated by interlinking magnetic flux from an external wireless communication device with the coil antenna 14, and the electromotive force drives the RFIC chip 16. The driven RFIC chip 16 transmits the data stored in the storage unit via the coil antenna 14.

ここからは、無線通信デバイス１０の構成の詳細について説明する。 From here, the details of the configuration of the wireless communication device 10 will be described.

図１に示すように、本実施の形態の場合、無線通信デバイス１０は、回路基板１２と、回路基板１２に取り付けられる端子ブロック２０とから構成される。 As shown in FIG. 1, in the case of the present embodiment, the wireless communication device 10 is composed of a circuit board 12 and a terminal block 20 attached to the circuit board 12.

図４は、端子ブロックの内部構成を示す斜視図である。図５および図６は、回路基板１２の斜視図である。 FIG. 4 is a perspective view showing the internal configuration of the terminal block. 5 and 6 are perspective views of the circuit board 12.

図４に示すように、端子ブロック２０は、例えば樹脂材料から作製されたブロック状の本体部２２と、その本体部２２内に埋め込まれたコイルアンテナ１４の一部である複数の導体部材２４Ａ〜２４Ｆを有する。複数の導体部材２４Ａ〜２４Ｆそれぞれは、例えば銅などの導体によって作製された門型の部材である。複数の導体部材２４Ａ〜２４Ｆは、間隔をあけた状態で並んでいる（Ｙ軸方向に並んでいる）。また、複数の導体部材２４Ａ〜２４Ｆそれぞれは、詳細は後述するが、回路基板１２上の導体パターンと接続するための一端２４Ａａ〜２４Ｆａと他端２４Ａｂ〜２４Ｆｂとを備える。 As shown in FIG. 4, the terminal block 20 includes, for example, a block-shaped main body 22 made of a resin material, and a plurality of conductor members 24A to which are a part of a coil antenna 14 embedded in the main body 22. It has 24F. Each of the plurality of conductor members 24A to 24F is a gate-shaped member made of a conductor such as copper. The plurality of conductor members 24A to 24F are arranged at intervals (arranged in the Y-axis direction). Further, each of the plurality of conductor members 24A to 24F includes one end 24Aa to 24Fa and the other end 24Ab to 24Fb for connecting to the conductor pattern on the circuit board 12, although details will be described later.

図５および図６に示すように、回路基板１２は、厚さ方向（Ｚ軸方向）に対向する第１の主面２６ａおよび第２の主面２６ｂを備える基板２６を有する。本実施の形態の場合、基板２６は、例えばＦＲ４基板などの薄い基板である。なお、基板２６は、樹脂基板であってもよい。本実施の形態の場合、基板２６は例えば２００μｍの厚さを備える。 As shown in FIGS. 5 and 6, the circuit board 12 has a substrate 26 having a first main surface 26a and a second main surface 26b facing in the thickness direction (Z-axis direction). In the case of this embodiment, the substrate 26 is a thin substrate such as an FR4 substrate. The substrate 26 may be a resin substrate. In the case of this embodiment, the substrate 26 has a thickness of, for example, 200 μm.

図５に示すように、基板２６の第１の主面２６ａには、端子ブロック２０の複数の導体部材２４Ａ〜２４Ｆと接続する導体パターン２８が設けられている。導体パターン２８は、例えば銅や金などの導体から作製された回路パターンである。例えば、導体パターン２８は、パターン印刷などによって基板２６の第１の主面２６ａに形成される。本実施の形態の場合、導体パターン２８は、３５μｍの厚さで形成されている。なお、本実施の形態の場合、導体パターン２８は、レジスト３０によって部分的に覆われて保護されている。 As shown in FIG. 5, a conductor pattern 28 for connecting to a plurality of conductor members 24A to 24F of the terminal block 20 is provided on the first main surface 26a of the substrate 26. The conductor pattern 28 is a circuit pattern made of a conductor such as copper or gold. For example, the conductor pattern 28 is formed on the first main surface 26a of the substrate 26 by pattern printing or the like. In the case of the present embodiment, the conductor pattern 28 is formed with a thickness of 35 μm. In the case of the present embodiment, the conductor pattern 28 is partially covered and protected by the resist 30.

具体的には、レジストを省略した図７に示すように、導体パターン２８は、複数の線状導体部３２Ａ〜３２Ｇを含んでいる。複数の線状導体部３２Ａ〜３２Ｇそれぞれは、コイルアンテナ１４の一部であって、回路基板１２の長手方向（Ｘ軸方向）に延在している。また、複数の線状導体部３２Ａ〜３２Ｇそれぞれは、一端３２Ａａ〜３２Ｇａおよび他端３２Ａｂ〜３２Ｇｂを備える。これらの一端および他端は、図５に示すように、端子ブロック２０の導体部材２４Ａ〜２４Ｆと接続するために、レジスト３０に覆われることなく露出している。 Specifically, as shown in FIG. 7 in which the resist is omitted, the conductor pattern 28 includes a plurality of linear conductor portions 32A to 32G. Each of the plurality of linear conductor portions 32A to 32G is a part of the coil antenna 14 and extends in the longitudinal direction (X-axis direction) of the circuit board 12. Further, each of the plurality of linear conductor portions 32A to 32G includes one end 32Aa to 32Ga and the other end 32Ab to 32Gb. As shown in FIG. 5, one end and the other end thereof are exposed without being covered with the resist 30 in order to connect with the conductor members 24A to 24F of the terminal block 20.

図４および図７を参照して説明すると、導体パターン２８における線状導体部３２Ａの他端３２Ａｂは、端子ブロック２０における導体部材２４Ａの他端２４Ａｂに接続する。その導体部材２４Ａの一端２４Ａａは、導体パターン２８における線状導体部３２Ｂの一端３２Ｂａに接続する。 Explaining with reference to FIGS. 4 and 7, the other end 32Ab of the linear conductor portion 32A in the conductor pattern 28 is connected to the other end 24Ab of the conductor member 24A in the terminal block 20. One end 24Aa of the conductor member 24A is connected to one end 32Ba of the linear conductor portion 32B in the conductor pattern 28.

線状導体部３２Ｂの他端３２Ｂｂは、端子ブロック２０における導体部材２４Ｂの他端２４Ｂｂに接続する。その導体部材２４Ｂの一端２４Ｂａは、導体パターン２８における線状導体部３２Ｃの一端３２Ｃａに接続する。 The other end 32Bb of the linear conductor portion 32B is connected to the other end 24Bb of the conductor member 24B in the terminal block 20. One end 24Ba of the conductor member 24B is connected to one end 32Ca of the linear conductor portion 32C in the conductor pattern 28.

線状導体部３２Ｃの他端３２Ｃｂは、端子ブロック２０における導体部材２４Ｃの他端２４Ｃｂに接続する。その導体部材２４Ｃの一端２４Ｃａは、導体パターン２８における線状導体部３２Ｄの一端３２Ｄａに接続する。 The other end 32Cb of the linear conductor portion 32C is connected to the other end 24Cb of the conductor member 24C in the terminal block 20. One end 24Ca of the conductor member 24C is connected to one end 32Da of the linear conductor portion 32D in the conductor pattern 28.

線状導体部３２Ｄの他端３２Ｄｂは、端子ブロック２０における導体部材２４Ｄの他端２４Ｄｂに接続する。その導体部材２４Ｄの一端２４Ｄａは、導体パターン２８における線状導体部３２Ｅの一端３２Ｅａに接続する。 The other end 32Db of the linear conductor portion 32D is connected to the other end 24Db of the conductor member 24D in the terminal block 20. One end 24Da of the conductor member 24D is connected to one end 32Ea of the linear conductor portion 32E in the conductor pattern 28.

線状導体部３２Ｅの他端３２Ｅｂは、端子ブロック２０における導体部材２４Ｅの他端２４Ｅｂに接続する。その導体部材２４Ｅの一端２４Ｅａは、導体パターン２８における線状導体部３２Ｆの一端３２Ｆａに接続する。 The other end 32Eb of the linear conductor portion 32E is connected to the other end 24Eb of the conductor member 24E in the terminal block 20. One end 24Ea of the conductor member 24E is connected to one end 32Fa of the linear conductor portion 32F in the conductor pattern 28.

線状導体部３２Ｆの他端３２Ｆｂは、端子ブロック２０における導体部材２４Ｆの他端２４Ｆｂに接続する。その導体部材２４Ｆの一端２４Ｆａは、導体パターン２８における線状導体部３２Ｇの一端３２Ｇａに接続する。 The other end 32Fb of the linear conductor portion 32F is connected to the other end 24Fb of the conductor member 24F in the terminal block 20. One end 24Fa of the conductor member 24F is connected to one end 32Ga of the linear conductor portion 32G in the conductor pattern 28.

このように導体パターン２８における複数の線状導体部３２Ａ〜３２Ｇと端子ブロック２０における複数の導体部材２４Ａ〜２４Ｆとが接続することにより、図１に示すように、電流がヘリカル状に流れることが可能な６つのループを備えるヘリカルコイル状のコイルアンテナ１４が形成される。なお、導体パターン２８における線状導体部３２Ａの一端３２Ａａと線状導体部３２Ｇの他端３２Ｇｂが、コイルアンテナ１４の両端として機能する。 By connecting the plurality of linear conductor portions 32A to 32G in the conductor pattern 28 and the plurality of conductor members 24A to 24F in the terminal block 20 in this way, as shown in FIG. 1, the current can flow in a helical shape. A helical coiled coil antenna 14 with six possible loops is formed. One end 32Aa of the linear conductor portion 32A and the other end 32Gb of the linear conductor portion 32G in the conductor pattern 28 function as both ends of the coil antenna 14.

導体パターン２８における複数の線状導体部３２Ａ〜３２Ｇと端子ブロック２０における複数の導体部材２４Ａ〜２４Ｆとの接続を維持するために、端子ブロック２０が回路基板１２に接合される。具体的には、図２に示すように、端子ブロック２０と回路基板１２は、樹脂材料（例えば樹脂系接着剤）３４を介して接合される。 The terminal block 20 is joined to the circuit board 12 in order to maintain the connection between the plurality of linear conductor portions 32A to 32G in the conductor pattern 28 and the plurality of conductor members 24A to 24F in the terminal block 20. Specifically, as shown in FIG. 2, the terminal block 20 and the circuit board 12 are joined via a resin material (for example, a resin-based adhesive) 34.

図８は、回路基板１２（基板２６）における樹脂材料（溶融した樹脂材料）３４の塗布領域ＡＲを示している。この塗布領域ＡＲに樹脂材料３４を塗布して回路基板１２に端子ブロック２０を接触させることにより、樹脂材料３４が回路基板１２と端子ブロック２０との間の隙間全体に行きわたる。その後、樹脂材料３４が硬化することにより、回路基板１２と端子ブロック２０が接合される。 FIG. 8 shows the coating region AR of the resin material (melted resin material) 34 in the circuit board 12 (board 26). By applying the resin material 34 to the coating region AR and bringing the terminal block 20 into contact with the circuit board 12, the resin material 34 spreads over the entire gap between the circuit board 12 and the terminal block 20. After that, the resin material 34 is cured to join the circuit board 12 and the terminal block 20.

本実施の形態の場合、図８に示すように、導体パターン２８を保護するレジスト３０は、基板２６の幅方向（Ｙ軸方向）全体にわたって第１の主面２６ａを覆っていない。具体的には、導体パターン２８を必要最低限覆うことができる大きさで基板２６の第１の主面２６ａ上に設けられている。そのため、第１の主面２６ａにおける幅方向の両端側部分が、レジスト３０に覆われずに露出している。また、樹脂材料３４の塗布領域ＡＲは、レジスト３０のみならず、基板２６の第１の主面２６ａも含んでいる。これにより、樹脂材料３４が基板２６の第１の主面２６ａに直接的に接触することができる。その結果、端子ブロック２０は、その幅方向中央部分が樹脂材料３４を介してレジスト３０に接合されるとともに、その幅方向両側部分が樹脂材料３４を介して基板２６の第１の主面２６ａに接合される。その結果として、端子ブロック２０が回路基板１２に強固に接合される。 In the case of the present embodiment, as shown in FIG. 8, the resist 30 that protects the conductor pattern 28 does not cover the first main surface 26a over the entire width direction (Y-axis direction) of the substrate 26. Specifically, it is provided on the first main surface 26a of the substrate 26 in a size capable of covering the conductor pattern 28 to the minimum necessary. Therefore, both end portions of the first main surface 26a in the width direction are exposed without being covered with the resist 30. Further, the coating region AR of the resin material 34 includes not only the resist 30 but also the first main surface 26a of the substrate 26. As a result, the resin material 34 can come into direct contact with the first main surface 26a of the substrate 26. As a result, the central portion of the terminal block 20 in the width direction is bonded to the resist 30 via the resin material 34, and both side portions in the width direction are joined to the first main surface 26a of the substrate 26 via the resin material 34. Be joined. As a result, the terminal block 20 is firmly bonded to the circuit board 12.

なお、本実施の形態の場合、図８に示すように、導体パターン２８における複数の線状導体部３２Ｂ〜３２Ｆそれぞれは、回路基板１２の長手方向（Ｘ軸方向）の両端から中央に向かって該長手方向に直線状に延在し、回路基板１２の長手方向の中央でクランクしている。そのため、導体パターン２８が存在しない２つの領域ＳＳが、第１の主面２６ａの中心対称に出現する。これらの領域ＳＳは、導体パターン２８が存在しない他の領域に比べて大きい。そのため、これらの領域ＳＳが樹脂材料３４を介して端子ブロック２０に接合されることにより、端子ブロック２０が一様な接合強度で回路基板１２に接合される。 In the case of the present embodiment, as shown in FIG. 8, each of the plurality of linear conductor portions 32B to 32F in the conductor pattern 28 is directed from both ends in the longitudinal direction (X-axis direction) of the circuit board 12 toward the center. It extends linearly in the longitudinal direction and is cranked at the center of the circuit board 12 in the longitudinal direction. Therefore, the two regions SS in which the conductor pattern 28 does not exist appear symmetrically with respect to the center of the first main surface 26a. These regions SS are larger than other regions in which the conductor pattern 28 does not exist. Therefore, these regions SS are bonded to the terminal block 20 via the resin material 34, so that the terminal block 20 is bonded to the circuit board 12 with uniform bonding strength.

図６に示すように、基板２６の第２の主面２６ｂには、RFICチップ１６とコンデンサチップ１８が実装されている。 As shown in FIG. 6, the RFIC chip 16 and the capacitor chip 18 are mounted on the second main surface 26b of the substrate 26.

これらのRFICチップ１６およびコンデンサチップ１８に接続される導体パターン４０が、基板２６の第２の主面２６ｂに設けられている。なお、導体パターン４０も、第１の主面２６ａ上の導体パターン２８と同様に、レジスト４２に部分的に覆われて保護されている。 A conductor pattern 40 connected to the RFIC chip 16 and the capacitor chip 18 is provided on the second main surface 26b of the substrate 26. The conductor pattern 40 is also partially covered and protected by the resist 42, similarly to the conductor pattern 28 on the first main surface 26a.

レジスト（およびRFICチップなど）を省略した図９に示すように、導体パターン４０は、第１の主面２６ａ上の導体パターン２８と同様に、例えば銅や金などの導体から作製された回路パターンである。例えば、導体パターン４０は、パターン印刷などによって基板２６の第２の主面２６ｂに形成される。本実施の形態の場合、導体パターン４０は、３５μｍの厚さで形成されている。 As shown in FIG. 9 in which the resist (and RFIC chip, etc.) is omitted, the conductor pattern 40 is a circuit pattern made of a conductor such as copper or gold, similarly to the conductor pattern 28 on the first main surface 26a. Is. For example, the conductor pattern 40 is formed on the second main surface 26b of the substrate 26 by pattern printing or the like. In the case of the present embodiment, the conductor pattern 40 is formed with a thickness of 35 μm.

また、本実施の形態の場合、導体パターン４０は、接続導体部４４Ａ、４４Ｂを含んでいる。 Further, in the case of the present embodiment, the conductor pattern 40 includes the connecting conductor portions 44A and 44B.

導体パターン４０における接続導体部４４Ａ、４４Ｂは、RFICチップ１６およびコンデンサチップ１８とコイルアンテナ１４とを接続するための導体である。 The connecting conductor portions 44A and 44B in the conductor pattern 40 are conductors for connecting the RFIC chip 16 and the capacitor chip 18 to the coil antenna 14.

接続導体部４４Ａは、RFICチップ１６と接続するための電極パッド４４Ａａと、コンデンサチップ１８と接続するための電極パッド４４Ａｂとを備える。また、接続導体部４４Ａは、ビアホール導体などの層間接続導体４６を介して、第１の主面２６ａ上の導体パターン２８における線状導体部３２Ａの一端３２Ａａに接続されている。すなわち、接続導体部４４Ａは、コイルアンテナ１４の一端に接続されている。 The connecting conductor portion 44A includes an electrode pad 44Aa for connecting to the RFIC chip 16 and an electrode pad 44Ab for connecting to the capacitor chip 18. Further, the connecting conductor portion 44A is connected to one end 32Aa of the linear conductor portion 32A in the conductor pattern 28 on the first main surface 26a via an interlayer connecting conductor 46 such as a via hole conductor. That is, the connecting conductor portion 44A is connected to one end of the coil antenna 14.

接続導体部４４Ｂは、RFICチップ１６と接続するための電極パッド４４Ｂａと、コンデンサチップ１８と接続するための電極パッド４４Ｂｂとを備える。また、接続導体部４４Ｂは、ビアホール導体などの層間接続導体４８を介して、第１の主面２６ａ上の導体パターン２８における線状導体部３２Ｇの他端３２Ｇｂに接続されている。すなわち、接続導体部４４Ｂは、コイルアンテナ１４の他端に接続されている。 The connecting conductor portion 44B includes an electrode pad 44Ba for connecting to the RFIC chip 16 and an electrode pad 44Bb for connecting to the capacitor chip 18. Further, the connecting conductor portion 44B is connected to the other end 32Gb of the linear conductor portion 32G in the conductor pattern 28 on the first main surface 26a via an interlayer connecting conductor 48 such as a via hole conductor. That is, the connecting conductor portion 44B is connected to the other end of the coil antenna 14.

基板２６の第２の主面２６ｂの一部の上面図である図１０に示すように、RFICチップ１６は、４つの実装用電極１６ａ〜１６ｂを備える。４つの実装用電極において、図２に示すように、実装用電極１６ａは電極パッド４４Ａａに対向して接続され、実装用電極１６ｂは電極パッド４４Ｂａに対向して接続されている。なお、図１０に示すように、残りの実装用電極１６ｃ、１６ｄは、本実施の形態の場合、接続導体部４４Ａ、４４Ｂから独立したダミー電極５０に接続されている。 As shown in FIG. 10, which is a top view of a part of the second main surface 26b of the substrate 26, the RFIC chip 16 includes four mounting electrodes 16a to 16b. In the four mounting electrodes, as shown in FIG. 2, the mounting electrode 16a is connected to face the electrode pad 44Aa, and the mounting electrode 16b is connected to face the electrode pad 44Ba. As shown in FIG. 10, the remaining mounting electrodes 16c and 16d are connected to the dummy electrodes 50 independent of the connecting conductor portions 44A and 44B in the case of the present embodiment.

このような接続導体部４４Ａ、４４Ｂに接続されるRFICチップ１６およびコンデンサチップ１８、図１および図２に示すように、樹脂の保護層５２によって覆われて保護されている。 As shown in the RFIC chip 16 and the capacitor chip 18, which are connected to such connecting conductor portions 44A and 44B, and FIGS. 1 and 2, they are covered and protected by a resin protective layer 52.

ここからは、RFICチップ１６の実装用電極１６ａ〜１６ｄと導体パターン４０の電極パッド４４Ａａ、４４Ｂａ、およびダミー電極５０との間の接続方法について説明する。 From here, a connection method between the mounting electrodes 16a to 16d of the RFIC chip 16 and the electrode pads 44Aa and 44Ba of the conductor pattern 40 and the dummy electrode 50 will be described.

本実施の形態の場合、RFICチップ１６の実装用電極１６ａ〜１６ｄと導体パターン４０の電極パッド４４Ａａ、４４Ｂａ、およびダミー電極５０との間の接続は、超音波圧着によって確立される。なお、本実施の形態の場合、コンデンサチップ１８と電極パッド４４Ａｂ、４４Ｂｂは、はんだを介して接続される。 In the case of this embodiment, the connection between the mounting electrodes 16a to 16d of the RFIC chip 16 and the electrode pads 44Aa and 44Ba of the conductor pattern 40 and the dummy electrode 50 is established by ultrasonic crimping. In the case of this embodiment, the capacitor chip 18 and the electrode pads 44Ab and 44Bb are connected via solder.

図１１は、RFICチップを基板に実装する様子を示している。図１１に示すように、RFICチップ１６と基板２６との間の超音波圧着は、超音波溶接装置１００を用いて行われる。 FIG. 11 shows how the RFIC chip is mounted on the substrate. As shown in FIG. 11, ultrasonic crimping between the RFIC chip 16 and the substrate 26 is performed using an ultrasonic welding apparatus 100.

超音波溶接装置１００は、基板２６を支持するアンビル１０２と、RFICチップ１６を基板２６に向かって押圧しつつ振動するホーン１０４とを有する。ホーン１０４が所定の押圧力ＰＦでRFICチップ１６を押圧しつつ所定の振幅ストロークＷＳで且つ所定の周波数で振動することにより、RFICチップ１６の実装用電極１６ａ〜１６ｄが電極パッド４４Ａａ、４４Ｂａ、およびダミー電極５０に超音波圧着される。例えば、ホーン１０４は、４．０〜７．５Ｎの押圧力ＰＦでRFICチップ１６を押圧しつつ、１．４０〜１．６７μｍの振幅ストロークＷＳと６０Ｈｚの周波数で振動する。なお、本実施の形態の場合、超音波溶接装置１００のホーン１０４は、短手方向である基板２６の幅方向（Ｙ軸方向）に振動するが、長手方向である基板２６の延在方向（Ｘ軸方向）に振動してもよい。 The ultrasonic welding apparatus 100 has an anvil 102 that supports the substrate 26 and a horn 104 that vibrates while pressing the RFIC chip 16 toward the substrate 26. When the horn 104 vibrates with a predetermined amplitude stroke WS and a predetermined frequency while pressing the RFIC chip 16 with a predetermined pressing force PF, the mounting electrodes 16a to 16d of the RFIC chip 16 are formed by the electrode pads 44Aa, 44Ba, and The dummy electrode 50 is ultrasonically pressure-bonded. For example, the horn 104 vibrates with an amplitude stroke WS of 1.40 to 1.67 μm and a frequency of 60 Hz while pressing the RFIC chip 16 with a pressing force PF of 4.0 to 7.5 N. In the case of the present embodiment, the horn 104 of the ultrasonic welding apparatus 100 vibrates in the width direction (Y-axis direction) of the substrate 26 in the lateral direction, but extends in the extending direction of the substrate 26 in the longitudinal direction (Y-axis direction). It may vibrate in the X-axis direction).

なお、超音波圧着されるRFICチップ１６の実装用電極１６ａ〜１６ｄと導体パターン４０（すなわち電極パッド４４Ａａ、４４Ｂａ）は、より高い接合強度を得るためには同一材料から作製されているのが好ましい。例えば、実装用電極と電極パッドの両方が、金または銅から作製される。異なる場合、電極パッドを実装用電極の材料と同一の材料でメッキしてもよい。例えば、電極パッドは、銅、ニッケル、銀、またはアルミニウムから作製され、その表面に金や銅のメッキ層が形成される。 The mounting electrodes 16a to 16d of the RFIC chip 16 ultrasonically pressure-bonded and the conductor pattern 40 (that is, the electrode pads 44Aa and 44Ba) are preferably made of the same material in order to obtain higher bonding strength. .. For example, both mounting electrodes and electrode pads are made from gold or copper. If different, the electrode pads may be plated with the same material as the mounting electrodes. For example, the electrode pad is made of copper, nickel, silver, or aluminum, and a gold or copper plating layer is formed on the surface thereof.

RFICチップ１６を適切に基板２６に実装するために、すなわちRFICチップ１６の実装不良の発生を抑制するために、RFICチップ１６が実装される第２の主面２６ｂとは反対側の第１の主面２６ａに設けられた導体パターン２８０のパターンレイアウトが考慮されている。 In order to properly mount the RFIC chip 16 on the substrate 26, that is, to suppress the occurrence of mounting defects of the RFIC chip 16, the first surface opposite to the second main surface 26b on which the RFIC chip 16 is mounted is the first. The pattern layout of the conductor pattern 280 provided on the main surface 26a is taken into consideration.

具体的には、図１０に示すように、基板２６の平面視（基板２６の厚さ方向視（Ｚ軸方向視））で、RFICチップ１６の複数の実装用電極１６ａ〜１６ｄに対して、第１の主面２６ａ上の導体パターン２８が重なっていない。ただし、導体パターン２８を高密度に設けるために、導体パターン２８の部分、すなわち線状導体部３２Ｄが、複数の実装用電極１６ａ〜１６ｄには重ならず、これらの実装用電極を除くRFICチップ１６の部分に重なっている。本実施の形態の場合、線状導体部３２Ｄ以外の残りの線状導体部はRFICチップ１６に重なっていない。 Specifically, as shown in FIG. 10, in a plan view of the substrate 26 (thickness direction view (Z-axis direction view) of the substrate 26), with respect to a plurality of mounting electrodes 16a to 16d of the RFIC chip 16. The conductor patterns 28 on the first main surface 26a do not overlap. However, in order to provide the conductor pattern 28 at a high density, the portion of the conductor pattern 28, that is, the linear conductor portion 32D does not overlap with the plurality of mounting electrodes 16a to 16d, and the RFIC chip excluding these mounting electrodes It overlaps with 16 parts. In the case of this embodiment, the remaining linear conductor portions other than the linear conductor portion 32D do not overlap the RFIC chip 16.

なお、本実施の形態の場合、このような導体パターン２８のレイアウトを実現するために、RFICチップ１６に重なる線状導体部３２Ｄの部分３２Ｄｃの幅Ｗ１が他の部分の幅Ｗ０に比べて小さくされている。これにより、線状導体部３２Ｄが、基板２６の平面視（Ｚ軸方向視）で、複数の実装用電極１６ａ〜１６ｄを避けてRFICチップ１６に重なることができる。また、RFICチップ１６に重なる線状導体部３２Ｄと隣接し合う線状導体部３２Ｃ、３２Ｅとの間のピッチ間隔が、部分的に異なる。すなわち、複数の実装用電極１６ａ〜１６ｄを避けるように、一部分のピッチ間隔ｐ１が他の部分のピッチ間隔ｐ０に比べて大きくされている。これにより、基板２６の平面視で、実装用電極１６ｂ、１６ｃが線状導体部３２Ｄ、３２Ｅに重なることなくこれらの間に位置するとともに、実装用電極１６ａ、１６ｄが線状導体部３２Ｃ、３２Ｄに重なることなくこれらの間に位置することができる。 In the case of the present embodiment, in order to realize such a layout of the conductor pattern 28, the width W1 of the portion 32Dc of the linear conductor portion 32D overlapping the RFIC chip 16 is smaller than the width W0 of the other portions. Has been done. As a result, the linear conductor portion 32D can overlap the RFIC chip 16 in a plan view (Z-axis direction view) of the substrate 26, avoiding a plurality of mounting electrodes 16a to 16d. Further, the pitch intervals between the linear conductor portions 32D overlapping the RFIC chip 16 and the adjacent linear conductor portions 32C and 32E are partially different. That is, the pitch interval p1 of a part is made larger than the pitch interval p0 of the other portion so as to avoid a plurality of mounting electrodes 16a to 16d. As a result, in the plan view of the substrate 26, the mounting electrodes 16b and 16c are located between them without overlapping the linear conductor portions 32D and 32E, and the mounting electrodes 16a and 16d are located between the linear conductor portions 32C and 32D. Can be located between these without overlapping.

このように、基板２６の平面視（Ｚ軸方向視）でRFICチップ１６の複数の実装用電極１６ａ〜１６ｄに重ならないように第１の主面２６ａ上の導体パターン２８をレイアウトする理由について説明する。その理由を、比較例の回路基板を挙げて説明する。 The reason for laying out the conductor pattern 28 on the first main surface 26a so as not to overlap the plurality of mounting electrodes 16a to 16d of the RFIC chip 16 in the plan view (Z-axis direction view) of the substrate 26 will be described. do. The reason will be described with reference to a circuit board of a comparative example.

図１２は、比較例の基板にRFICチップが実装された比較例の回路基板を示している。比較例の回路基板は、基板の第１の主面に設けられている導体パターンのパターンレイアウトが異なる点を除いて、本実施の形態の回路基板１２と実質的に同一である。 FIG. 12 shows a circuit board of a comparative example in which an RFIC chip is mounted on the substrate of the comparative example. The circuit board of the comparative example is substantially the same as the circuit board 12 of the present embodiment except that the pattern layout of the conductor pattern provided on the first main surface of the substrate is different.

図１２に示すように、本実施の形態の回路基板１２と異なり、比較例の回路基板２１２の場合、基板２６の第１の主面２６ａに設けられている導体パターン２２８において、線状導体部２３２Ｂが基板２６の平面視（Ｚ軸方向視）でRFICチップ１６の実装用電極１６ａに重なるとともに、線状導体部２３２Ｃが実装用電極１６ｂに重なる。 As shown in FIG. 12, unlike the circuit board 12 of the present embodiment, in the case of the circuit board 212 of the comparative example, the linear conductor portion in the conductor pattern 228 provided on the first main surface 26a of the substrate 26. The 232B overlaps the mounting electrode 16a of the RFIC chip 16 in the plan view (Z-axis direction view) of the substrate 26, and the linear conductor portion 232C overlaps the mounting electrode 16b.

比較例の回路基板２１２の場合、図１３に示すように超音波溶接装置１００のホーン１０４がRFICチップ１６を基板２６に向かって押圧すると、実装用電極１６ａ、１６ｂに対向する電極パッド４４Ａａ、４４Ｂａに局所的な力が加わる。基板や実装電極の厚さの関係によっては、撓むこともある。その結果、実装用電極１６ａ、１６ｂが、電極パッド４４Ａａ、４４Ｂａに適切に圧着せずに、RFICチップ１６の実装不良が発生する。例えば、実装用電極が全体にわたって電極パッドに圧着しない不良や、実装用電極が全体にわたって電極パッドに圧着しても接合強度の分布が一様でない不良が発生する。このような実装不良が生じると、RFICチップと導体パターンとの間の抵抗値が設計値からずれ、その結果として無線通信デバイスが設計どおりの通信特性を備えることができなくなる。 In the case of the circuit board 212 of the comparative example, when the horn 104 of the ultrasonic welding apparatus 100 presses the RFIC chip 16 toward the substrate 26 as shown in FIG. 13, the electrode pads 44Aa and 44Ba facing the mounting electrodes 16a and 16b Local force is applied to. It may bend depending on the thickness of the substrate and mounting electrodes. As a result, the mounting electrodes 16a and 16b are not properly crimped to the electrode pads 44Aa and 44Ba, resulting in a mounting failure of the RFIC chip 16. For example, there may be a defect that the mounting electrode is not crimped to the electrode pad over the entire surface, or a defect that the distribution of the bonding strength is not uniform even if the mounting electrode is crimped to the electrode pad over the entire surface. When such a mounting defect occurs, the resistance value between the RFIC chip and the conductor pattern deviates from the design value, and as a result, the wireless communication device cannot have the communication characteristics as designed.

具体的に説明すると、このような実装不良は、超音波溶接装置１００のホーン１０４の押圧力に対応するアンビル１０２からの反力によって線状導体部２３２Ａ〜２３２Ｄそれぞれが基板２６に向かって押され、それにより基板２６に局所的な力が加わること（すなわち基板が全体にわたって一様な力で支持されていないこと）を起因とする。このような局所的な力は、複数の線状導体部２３２Ａ〜２３２Ｄの存在により、基板２６の第１の主面２６ａ側が、平坦面ではなく、凹凸面であることによって生じる。比較例の回路基板２１２の場合、線状導体部２３２Ａ〜２３２Ｄの存在により、レジスト３０の表面３０ａに凹凸が生じている。 Specifically, in such a mounting defect, each of the linear conductor portions 232A to 232D is pushed toward the substrate 26 by the reaction force from the anvil 102 corresponding to the pressing force of the horn 104 of the ultrasonic welding apparatus 100. This is due to the fact that a local force is applied to the substrate 26 (ie, the substrate is not supported by a uniform force throughout). Such a local force is generated because the first main surface 26a side of the substrate 26 is not a flat surface but an uneven surface due to the presence of the plurality of linear conductor portions 232A to 232D. In the case of the circuit board 212 of the comparative example, the surface 30a of the resist 30 has irregularities due to the presence of the linear conductor portions 232A to 232D.

特に言えば、線状導体部２３２Ｂ、２３２Ｃが基板２６の平面視（Ｚ軸方向視）でRFICチップ１６の実装用電極１６ａ、１６ｂと重なるために、実装用電極１６ａ、１６ｂに対向して圧着される電極パッド４４Ａａ、４４Ｂａに局所的な力が加わる（伝わる）ことを原因として、実装不良が発生する。さらに言えば、基板２６の平面視で、実装用電極１６ａ、１６ｂの一部に線状導体部２３２Ｂ、２３２Ｃが重なっていることにもよる。 In particular, since the linear conductor portions 232B and 232C overlap the mounting electrodes 16a and 16b of the RFIC chip 16 in the plan view (Z-axis direction view) of the substrate 26, they are crimped against the mounting electrodes 16a and 16b. A mounting defect occurs due to the local force being applied (transmitted) to the electrode pads 44Aa and 44Ba. Furthermore, it is also due to the fact that the linear conductor portions 232B and 232C overlap a part of the mounting electrodes 16a and 16b in the plan view of the substrate 26.

図１１に示す本実施の形態の回路基板１２でも、超音波溶接装置１００のホーン１０４の押圧力に対応するアンビル１０２からの反力によって線状導体部３２Ｂ〜３２Ｆが基板２６に向かって押され、それにより基板２６に局所的な力が加わる。しかしながら、基板２６の平面視（Ｚ軸方向視）でRFICチップ１６の実装用電極１６ａ、１６ｂに重なる線状導体部が存在しないために、実装用電極１６ａ、１６ｂに対向して圧着される電極パッド４４Ａａ、４４Ｂａに局所的な力が実質的に加わらない（伝わらない）。そのため、図１２および図１３に示す比較例の回路基板２１２において発生するような実装不良は生じにくく、実装用電極１６ａ、１６ｂが電極パッド４４Ａａ、４４Ｂａに適切に圧着される。 Also in the circuit board 12 of the present embodiment shown in FIG. 11, the linear conductor portions 32B to 32F are pushed toward the substrate 26 by the reaction force from the anvil 102 corresponding to the pressing force of the horn 104 of the ultrasonic welding apparatus 100. As a result, a local force is applied to the substrate 26. However, since there is no linear conductor portion that overlaps the mounting electrodes 16a and 16b of the RFIC chip 16 in the plan view (Z-axis direction view) of the substrate 26, the electrodes are crimped against the mounting electrodes 16a and 16b. Local force is not substantially applied (transmitted) to the pads 44Aa and 44Ba. Therefore, mounting defects such as those that occur in the circuit board 212 of the comparative example shown in FIGS. 12 and 13 are unlikely to occur, and the mounting electrodes 16a and 16b are appropriately crimped to the electrode pads 44Aa and 44Ba.

表１は、図１１に示す本実施の形態の回路基板１２（実施例）において発生する実装不良率と、図１２および図１３に示す比較例の回路基板２１２（比較例）において発生する実装不良率とを示している。なお、このときの超音波溶接装置におけるホーンの周波数は６０Ｈｚであって、振幅は１．４５μｍである。また、ホーンの押圧力は、５．０Ｎと６．０Ｎである。さらに、実施例および比較例それぞれのサンプル数は９６個である。

Table 1 shows the mounting defect rate occurring in the circuit board 12 (Example) of the present embodiment shown in FIG. 11 and the mounting defect occurring in the circuit board 212 (Comparative Example) of the comparative example shown in FIGS. 12 and 13. It shows the rate. The frequency of the horn in the ultrasonic welding apparatus at this time is 60 Hz, and the amplitude is 1.45 μm. The pressing force of the horn is 5.0N and 6.0N. Further, the number of samples in each of the examples and the comparative examples is 96.

表１に示すように、本実施の形態の回路基板１２では発生しない実装不良が、比較例の回路基板２１２の場合、押圧力５．０Ｎでは３個、押圧力６．０Ｎでは５個発生している。また、ホーンの押圧力が高いほど、実装不良率が高い。 As shown in Table 1, in the case of the circuit board 212 of the comparative example, three mounting defects that do not occur in the circuit board 12 of the present embodiment occur at a pressing pressure of 5.0 N and five at a pressing pressure of 6.0 N. ing. Further, the higher the pressing force of the horn, the higher the mounting defect rate.

表１に示す結果から、本実施の形態のように、基板２６の平面視で第２の主面２６ｂ上のRFICチップ１６の実装用電極１６ａ、１６ｂに対して重ならないように第１の主面２６ａに導体パターン４０を設けることにより、RFICチップ１６の実装不良の発生が抑制されていることが明らかである。 From the results shown in Table 1, as in the present embodiment, the first main surface is not overlapped with the mounting electrodes 16a and 16b of the RFIC chip 16 on the second main surface 26b in the plan view of the substrate 26. It is clear that the occurrence of mounting defects of the RFIC chip 16 is suppressed by providing the conductor pattern 40 on the surface 26a.

なお、図１２に示す比較例の回路基板２１２において、導体パターン２２８を保護するレジスト３０をその表面３０ａが平坦になるまで厚くして基板２６に局所的な力が加わることを抑制し、それによりRFICチップの実装不良の発生を抑制することも考えられる。しかし、その場合、回路基板２１２全体の厚さが大きくなり、回路基板２１２を備える電子デバイスの小型化が妨害される。 In the circuit board 212 of the comparative example shown in FIG. 12, the resist 30 that protects the conductor pattern 228 is thickened until the surface 30a becomes flat to suppress the application of a local force to the substrate 26, thereby suppressing the application of a local force to the substrate 26. It is also possible to suppress the occurrence of mounting defects on the RFIC chip. However, in that case, the thickness of the entire circuit board 212 becomes large, which hinders the miniaturization of the electronic device including the circuit board 212.

このような本実施の形態によれば、RFICチップ１６が実装される第２の主面２６ｂとは反対側の第１の主面２６ａに導体パターン２８が形成されている回路基板１２において、その導体パターン２８を高密度に設けつつ、RFICチップ１６の実装不良の発生を抑制することができる。 According to this embodiment, in the circuit board 12 in which the conductor pattern 28 is formed on the first main surface 26a on the side opposite to the second main surface 26b on which the RFIC chip 16 is mounted. While the conductor pattern 28 is provided at a high density, it is possible to suppress the occurrence of mounting defects of the RFIC chip 16.

以上、上述の実施の形態を挙げて本発明を説明したが、本発明の実施の形態はこれに限らない。 Although the present invention has been described above with reference to the above-described embodiments, the embodiments of the present invention are not limited to this.

例えば、上述の実施の形態１の場合、図１に示すように、無線通信デバイス１０は、６つのループを備えるヘリカルコイル状のコイルアンテナ１４を有するが、本発明の実施の形態は、これに限らない。例えば、７つ以上または５つ以下のループを備えるコイルアンテナであってもよい。 For example, in the case of the first embodiment described above, as shown in FIG. 1, the wireless communication device 10 has a helical coil-shaped coil antenna 14 having six loops, but the embodiment of the present invention includes the same. Not exclusively. For example, it may be a coil antenna having 7 or more or 5 or less loops.

なお、図１４は、本発明の別の実施の形態に係る、２つのループを備えるコイルアンテナを有する無線通信デバイスに使用される回路基板を示している。 Note that FIG. 14 shows a circuit board used in a wireless communication device having a coil antenna having two loops according to another embodiment of the present invention.

図１４に示すように、２つのループを備えるコイルアンテナを有する無線通信デバイスの場合、回路基板３１２の基板２６における第１の主面２６ａ上の導体パターン３２８は、コイルアンテナの一部である線状導体部３３２Ａ、３３２Ｂを含む。この場合、一方の線状導体部３３２Ａは、基板２６の平面視（Ｚ軸方向視）で、RFICチップ１６の複数の実装用電極１６ａ、１６ｂ（加えて、図示しない実装用電極１６ｃ、１６ｄ（図１０参照））に対して重ならず、これらの間に位置する。他方の線状導体部３３２Ｂは、RFICチップ１６に重なっていない。 As shown in FIG. 14, in the case of a wireless communication device having a coil antenna having two loops, the conductor pattern 328 on the first main surface 26a on the substrate 26 of the circuit board 312 is a line that is a part of the coil antenna. The shape conductor portion 332A and 332B are included. In this case, one of the linear conductor portions 332A is a plurality of mounting electrodes 16a and 16b of the RFIC chip 16 (in addition, mounting electrodes 16c and 16d (not shown)) in a plan view (Z-axis direction view) of the substrate 26. It does not overlap with respect to (see FIG. 10)) and is located between them. The other linear conductor portion 332B does not overlap the RFIC chip 16.

なお、図１４に示すように、２つの線状導体部３３２Ａ、３３２Ｂを覆うレジスト３０は、基板２６の平面視（Ｚ軸方向視）でRFICチップ１６の複数の実装用電極１６ａ〜１６ｄ全てに重なるように基板２６に設けられるのが好ましい。これにより、超音波溶接装置のホーンに押圧されたときに、RFIチップ１６がレジスト３０によって支持される。例えば、実装用電極１６ａに重なるレジストがない場合、実装用電極１６ａに対向する電極パッド４４Ａａがホーンから逃げるようにアンビルに向かって撓み、実装用電極１６ａと電極パッド４４Ａａとの間の接触圧が不足しうる。その結果として実装不良が発生しうる。 As shown in FIG. 14, the resist 30 covering the two linear conductor portions 332A and 332B is applied to all of the plurality of mounting electrodes 16a to 16d of the RFIC chip 16 in a plan view (Z-axis direction view) of the substrate 26. It is preferable that the substrates 26 are provided so as to overlap each other. As a result, the RFI tip 16 is supported by the resist 30 when pressed against the horn of the ultrasonic welding apparatus. For example, when there is no resist overlapping the mounting electrode 16a, the electrode pad 44Aa facing the mounting electrode 16a bends toward the anvil so as to escape from the horn, and the contact pressure between the mounting electrode 16a and the electrode pad 44Aa increases. It can run short. As a result, mounting defects can occur.

また、本発明の実施の形態に係る無線通信デバイスのアンテナは、ＨＦ帯の周波数で使用されるコイルアンテナに限らない。例えば、ＵＨＦ帯の周波数で使用されるループアンテナ（１つのループを備えるアンテナ）、またはダイポールアンテナなどのポールアンテナであってもよい。 Further, the antenna of the wireless communication device according to the embodiment of the present invention is not limited to the coil antenna used in the frequency of the HF band. For example, it may be a loop antenna (antenna having one loop) used at a frequency in the UHF band, or a pole antenna such as a dipole antenna.

図１５は、本発明のさらに別の実施の形態に係る、ループアンテナを有する無線通信デバイスに使用される回路基板を示している。 FIG. 15 shows a circuit board used in a wireless communication device having a loop antenna according to still another embodiment of the present invention.

図１５に示すように、ループアンテナを有する無線通信デバイスの場合、回路基板４１２の基板２６における第１の主面２６ａ上の導体パターン４２８は、コイルアンテナの一部である線状導体部４２８Ａを含む。この場合、線状導体部４２８Ａは、基板２６の平面視（Ｚ軸方向視）で、RFICチップ１６の複数の実装用電極１６ａ、１６ｂ（加えて、図示しない実装用電極１６ｃ、１６ｄ（図１０参照））に対して重ならず、これらの間に位置する。 As shown in FIG. 15, in the case of a wireless communication device having a loop antenna, the conductor pattern 428 on the first main surface 26a of the substrate 26 of the circuit board 412 has a linear conductor portion 428A which is a part of the coil antenna. include. In this case, the linear conductor portion 428A is a plurality of mounting electrodes 16a and 16b (in addition, mounting electrodes 16c and 16d (not shown)) of the RFIC chip 16 in a plan view (Z-axis direction view) of the substrate 26 (FIG. 10). It does not overlap with respect to (see)) and is located between them.

なお、ポールアンテナを有する無線通信デバイスの場合、線状導体部４２８Ａがポールアンテナ全体を構成する。この場合、図３に示す端子ブロックが必要なくなる。 In the case of a wireless communication device having a pole antenna, the linear conductor portion 428A constitutes the entire pole antenna. In this case, the terminal block shown in FIG. 3 is not required.

さらに、上述の実施の形態の場合、基板２６の第１の主面２６ａ上の導体パターン２８はレジスト３０によって保護され、第２の主面２６ｂ上の導体パターン４０はレジスト４２によって保護されている。しかしながら、本発明の実施の形態はこれに限らない。回路基板が、例えばケーシング、または無線通信デバイスのハウジング内に収容される場合には、導体パターンを保護するためのレジストを省略してもよい。 Further, in the case of the above-described embodiment, the conductor pattern 28 on the first main surface 26a of the substrate 26 is protected by the resist 30, and the conductor pattern 40 on the second main surface 26b is protected by the resist 42. .. However, the embodiments of the present invention are not limited to this. If the circuit board is housed, for example, in a casing or housing of a wireless communication device, the resist to protect the conductor pattern may be omitted.

さらにまた、上述の実施の形態の場合、図１０に示すように、RFICチップ１６は、４つの実装用電極１６ａ〜１６ｄを備えるが、本発明の実施の形態はこれに限らない。RFICチップが備える複数の実装用電極は、２つ、６つ以上、またはその他の数であってもよい。 Furthermore, in the case of the above-described embodiment, as shown in FIG. 10, the RFIC chip 16 includes four mounting electrodes 16a to 16d, but the embodiment of the present invention is not limited to this. The plurality of mounting electrodes included in the RFIC chip may be two, six or more, or any other number.

加えて、上述の実施の形態の場合、図１０に示すように、基板２６の平面視（Ｚ軸方向視）で、RFICチップ１６の複数の実装用電極１６ａ〜１６ｄの間に位置する線状導体部は１つであるが、本発明の実施の形態はこれに限らない。基板の平面視で、複数の実装用電極の間に複数の線状導体部が位置してもよい。 In addition, in the case of the above-described embodiment, as shown in FIG. 10, in a plan view (Z-axis direction view) of the substrate 26, a linear shape located between a plurality of mounting electrodes 16a to 16d of the RFIC chip 16. Although there is only one conductor portion, the embodiment of the present invention is not limited to this. A plurality of linear conductor portions may be located between the plurality of mounting electrodes in a plan view of the substrate.

加えてまた、上述の実施の形態の場合、図１１に示すように、RFICチップ１６の複数の実装用電極１６ａ〜１６ｄと基板２６の電極パッド４４Ａａ、４４Ｂａ、およびダミー電極５０は超音波圧着によって圧着されているが、本発明の実施の形態はこれに限らない。例えば、導電性接着剤や熱圧着接着剤を介して実装用電極と電極パッドとが圧着されてもよい。 In addition, in the case of the above-described embodiment, as shown in FIG. 11, the plurality of mounting electrodes 16a to 16d of the RFIC chip 16, the electrode pads 44Aa and 44Ba of the substrate 26, and the dummy electrode 50 are ultrasonically pressure-bonded. Although it is crimped, the embodiment of the present invention is not limited to this. For example, the mounting electrode and the electrode pad may be crimped via a conductive adhesive or a thermocompression bonding adhesive.

さらに加えて、上述の実施の形態の無線通信デバイスは、いわゆるRFIDタグであって、電子部品としてRFICチップを備えるが、本発明の実施の形態はこれに限らない。また、上述の実施の形態の回路基板は、無線通信デバイス以外のデバイスでも使用可能である。 Furthermore, the wireless communication device of the above-described embodiment is a so-called RFID tag and includes an RFID chip as an electronic component, but the embodiment of the present invention is not limited to this. Further, the circuit board of the above-described embodiment can be used in a device other than the wireless communication device.

すなわち、本発明の実施の形態に係る回路基板は、広義には、厚さ方向に対向する第１および第２の主面を備える基板と、前記基板の第１の主面に設けられた導体パターンと、前記基板の第２の主面に設けられた複数の電極パッドと、前記複数の電極パッドに対してそれぞれ対向して接続される複数の実装用電極を備える電子部品と、を有し、前記導体パターンが、前記基板の平面視で、前記複数の実装用電極にはいずれも重ならず、前記電子部品の部分に重なる部分を有するものである。 That is, in a broad sense, the circuit board according to the embodiment of the present invention includes a substrate having first and second main surfaces facing each other in the thickness direction, and a conductor provided on the first main surface of the substrate. It has a pattern, a plurality of electrode pads provided on a second main surface of the substrate, and an electronic component having a plurality of mounting electrodes connected to the plurality of electrode pads so as to face each other. The conductor pattern has a portion that does not overlap with the plurality of mounting electrodes but overlaps with the portion of the electronic component in the plan view of the substrate.

以上、本発明に係る複数の実施の形態を説明してきたが、ある実施の形態に対して別の少なくとも１つの実施の形態を全体としてまたは部分的に組み合わせて本発明に係るさらなる実施の形態とすることが可能であることは、当業者にとって明らかである。 Although a plurality of embodiments according to the present invention have been described above, there is a further embodiment according to the present invention in which at least one other embodiment is combined with a certain embodiment as a whole or partially. It is clear to those skilled in the art that it is possible to do so.

本発明は、電子部品が実装される主面とは反対側の主面に導体パターンが形成されている回路基板に適用可能である。 The present invention is applicable to a circuit board in which a conductor pattern is formed on a main surface opposite to the main surface on which electronic components are mounted.

１２回路基板
１６電子部品（RFICチップ）
１６ａ実装用電極
１６ｂ実装用電極
２６基板
２６ａ第１の主面
２６ｂ第２の主面
２８導体パターン
４４Ａａ電極パッド
４４Ｂａ電極パッド 12 Circuit board 16 Electronic components (RFIC chip)
16a Mounting electrode 16b Mounting electrode 26 Substrate 26a First main surface 26b Second main surface 28 Conductor pattern 44Aa Electrode pad 44Ba Electrode pad

Claims

A substrate having first and second main surfaces facing each other in the thickness direction,
A conductor pattern provided on the first main surface of the substrate and
A plurality of electrode pads provided on the second main surface of the substrate, and
An electronic component having a plurality of mounting electrodes connected to the plurality of electrode pads facing each other.
Wherein the conductive pattern in a plan view of the substrate, the not overlapped Both the plurality of mounting electrodes, have a portion overlapping the portion of the electronic component,
The conductor pattern includes a first linear conductor portion and a second linear conductor portion.
The plurality of mounting electrodes include a first mounting electrode.
A circuit board in which the first mounting electrode is located between the first linear conductor portion and the second linear conductor portion in the plan view.

The conductor pattern further includes a third linear conductor portion.
The plurality of mounting electrodes further include a second mounting electrode.
The second mounting electrode is located between the first linear conductor portion and the third linear conductor portion in the plan view.
The first linear conductor portion, in the plan view, is located between the first mounting electrode and the second mounting electrode, the circuit board according to claim 1.

With the circuit board
Including an antenna mounted on the circuit board
The circuit board
A substrate having first and second main surfaces facing each other in the thickness direction,
A conductor pattern provided on the first main surface of the substrate and
A plurality of electrode pads provided on the second main surface of the substrate, and
An electronic component having a plurality of mounting electrodes connected to the plurality of electrode pads facing each other.
The conductor pattern has a portion that does not overlap with the plurality of mounting electrodes but overlaps with the portion of the electronic component in a plan view of the substrate.
A wireless communication device, wherein the conductor pattern is a part of the antenna.

A method for manufacturing a circuit board on which electronic components having a plurality of mounting electrodes are mounted.
A substrate having first and second main surfaces facing each other in the thickness direction, a conductor pattern provided on the first main surface, and a plurality of electrode pads provided on the second main surface. Prepare and
The electronic components are arranged on the substrate so that the plurality of mounting electrodes face the electrode pads.
By pressing the electronic component toward the substrate, the plurality of mounting electrodes are crimped to the electrode pad.
Wherein the conductive pattern in a plan view of the substrate, the not overlapped Both the plurality of mounting electrodes, have a portion overlapping the portion of the electronic component,
The conductor pattern includes a first linear conductor portion and a second linear conductor portion.
The plurality of mounting electrodes include a first mounting electrode.
A method for manufacturing a circuit board, wherein the first mounting electrode is located between the first linear conductor portion and the second linear conductor portion in the plan view.