JP6950435B2 - Clock output circuit - Google Patents

Description

The present invention relates to a clock output circuit.

For example, in an audio device or the like, assuming that the output buffer circuit operates at ± 6 V, the input circuit of the buffer circuit requires an input waveform centered on the GND at the midpoint. Therefore, when the clock waveform from the crystal oscillator is not centered on GND, the DC component must be cut through the capacitor, level-shifted, and then supplied to the output buffer circuit.

FIG. 6 shows an example of a conventional clock output circuit. Further, FIG. 7 shows a signal waveform of the clock circuit shown in FIG.

A crystal oscillator 10 such as an OCXO (crystal oscillator with a constant temperature bath) is driven by, for example, a power supply voltage of 5 V, and outputs an amplitude centered on a voltage (+ 2.5 V) that is approximately half the voltage of 5 V.

On the other hand, assuming that the output buffer circuit 12 is operating at ± 6 V, the output buffer circuit 12 requires an input waveform centered on the GND at its midpoint, so that there is a discrepancy between the two.

Therefore, a capacitor 14 is connected between the crystal oscillator 10 and the output buffer circuit 12, the DC component is cut, the center of the input waveform is level-shifted to GND, and then supplied to the output buffer circuit 12.

Patent Document 1 describes a circuit method for circuit-coupling a grounded-emitter amplifier and a differential amplifier without using a capacitor.

Japanese Unexamined Patent Publication No. 11-88054

As shown in FIG. 6, in the circuit configuration in which the capacitor is interposed, the DC component can be cut, but the information originally contained in the waveform is not completely supplied to the output buffer circuit, but is passed through the capacitor. There is a problem that some information is lost.

In Patent Document 1, the same power supply and the same GND are used, and the method of applying the bias of the transistor of the differential amplifier in the subsequent stage is changed to realize a capacitorless circuit configuration without using a capacitor, but a simpler configuration is realized. It is required to realize capacitorless.

An object of the present invention is to provide a clock output circuit capable of realizing capacitorless with a simple configuration.

The present invention is connected to a voltage adjusting circuit that adjusts the power supply voltage to generate a first positive voltage, a second positive voltage, and a second negative voltage, and the voltage adjusting circuit, and the first positive voltage is applied to the power supply terminal. The crystal oscillator that outputs a clock signal with the digital ground potential set to the ground terminal is connected to the voltage adjustment circuit, operates by applying the second positive voltage and the second negative voltage, and the crystal. The voltage is provided with an output buffer circuit that is connected to the oscillator without the intervention of a capacitor, the clock signal from the crystal oscillator is set to the ground potential for analog via a resistor, and is supplied to the non-inverting input terminal. The adjusting circuit is connected to the transformer that transforms the power supply voltage, the first diode bridge circuit and the second diode bridge circuit connected to the secondary side of the transformer, and the first diode bridge circuit, and the first positive A first voltage regulator that generates a voltage and outputs it to the power supply terminal of the crystal oscillator and is connected to the first diode bridge circuit to generate a voltage intermediate between the first positive voltage and the digital ground potential. A second voltage regulator that is set to ground for analog and supplies to the inverting input terminal of the output buffer circuit, and is connected to the second diode bridge circuit to generate the second positive voltage and be on the positive side of the output buffer circuit. A clock including a third voltage regulator that outputs to the power supply terminal and a fourth voltage regulator that is connected to the second diode bridge circuit and generates the second negative voltage and outputs it to the negative power supply terminal of the output buffer circuit. It is an output circuit.

Further, the present invention is connected to the voltage adjusting circuit and the first positive voltage, the first negative voltage, the second positive voltage and the second negative voltage by adjusting the power supply voltage. A crystal oscillator in which a positive voltage is applied to the power supply terminal, the first negative voltage is applied to the ground terminal, and a clock signal centered on an intermediate potential between the first positive voltage and the first negative voltage is output, and the voltage. It is connected to the adjustment circuit, operates by applying the second positive voltage and the second negative voltage, and is connected to the crystal oscillator without the intervention of a capacitor, and the clock signal from the crystal oscillator is transmitted via a resistor. It includes an output buffer circuit that is grounded and supplied to the non-inverting input terminal and the ground potential is set to the inverting input terminal. The voltage adjusting circuit includes a transformer that transforms the power supply voltage and a secondary side of the transformer. A diode bridge circuit connected to the above, a fifth voltage regulator connected to the diode bridge circuit, generating the second positive voltage and outputting the second positive voltage to the positive power supply terminal of the output buffer circuit, and connecting to the diode bridge circuit. The sixth voltage regulator that generates the second negative voltage and outputs it to the negative power supply terminal of the output buffer circuit and the output terminal of the fifth voltage regulator are connected to the first positive voltage from the second positive voltage. The seventh voltage regulator that generates a positive voltage and outputs it to the power supply terminal of the crystal oscillator and the first negative voltage that is connected to the output terminal of the sixth voltage regulator to generate the first negative voltage from the second negative voltage. This is a clock output circuit including an eighth voltage regulator that outputs to the ground terminal of the crystal oscillator.

According to the present invention, a capacitor-less clock output circuit can be realized with a simple configuration. According to the present invention, since the capacitor is not interposed, the clock signal waveform from the crystal oscillator can be output as it is, and the clock signal can be supplied to an audio device or the like that requires particularly high-precision digital processing.

It is a schematic block diagram of an embodiment. It is a signal waveform diagram of an embodiment. It is a circuit block diagram of an embodiment. It is a circuit block diagram of another embodiment. It is a circuit block diagram of still another embodiment. It is a conventional circuit block diagram. It is a conventional signal waveform diagram.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Embodiment 1>
FIG. 1 shows a schematic configuration of a clock output circuit of this embodiment. Further, FIG. 2 shows a signal waveform of the clock output circuit shown in FIG. The operating power supply voltage of the crystal oscillator is roughly classified into a 5V system, a 3.3V system, and a 1.8V system. In the present embodiment, the 5V system is exemplified, but the present invention is not limited to this.

A crystal oscillator 10 such as an OCXO (crystal oscillator with a constant temperature bath) is driven by a power supply voltage of, for example, ± 2.5 V, and outputs a clock signal with an amplitude centered on GND.

On the other hand, assuming that the output buffer circuit 12 in the subsequent stage operates at ± 6 V, the output buffer circuit 12 requests an input waveform centered on the GND at the midpoint thereof, but there is no discrepancy between the two. , The clock signal from the crystal oscillator 10 can be directly supplied to the output buffer circuit 12 without interposing a capacitor. The output buffer circuit 12 outputs a clock signal to the output bus.

Compared with the circuit configuration shown in FIG. 6, the present embodiment includes a voltage adjusting circuit that generates a power supply voltage of ± 2.5 V from a power supply voltage of + 5 V and applies it to the crystal oscillator 10, thereby making it capacitorless. It can be said that it has been realized.

Since the clock output circuit of the present embodiment does not use a capacitor, the information originally contained in the waveform can be completely supplied to the output buffer circuit, and the accuracy of the clock signal is improved. The clock output circuit of this embodiment can be applied to a master clock generator or the like that outputs an accurate 10 MHz clock signal required for high resolution sound source reproduction of a high sampling rate such as DSD (Direct Stream Digital) 22.5 MHz or PCM 768 kHz.

Next, the configuration of the clock output circuit in the present embodiment, particularly the configuration of the voltage adjusting circuit for adjusting the power supply voltage applied to the crystal oscillator 10, will be described in detail.

FIG. 3 shows the circuit configuration of the clock output circuit. The voltage adjustment circuit in this embodiment adjusts the power supply voltage so that the crystal oscillator 10 operating at + 5V to GND (0V) operates at + 2.5V to −2.5V.

In addition to the crystal oscillator 10 and the output buffer circuit 12, the clock output circuit includes an AC plug 20, a transformer 22, diode bridge circuits 24 and 30, 3-terminal regulators (voltage regulators) 26 and 28, and a shunt regulator (voltage regulator). ) 32, 34 are provided.

The primary side of the transformer 22 is connected to the AC plug 20, and the secondary side of the transformer 22 is connected to the diode bridge circuits 24 and 30. The transformer 22 extracts the digital + 5V voltage and the analog ± 6V voltage from the AC power supply voltage, outputs the digital + 5V voltage to the diode bridge circuit 24, and outputs the analog ± 6V voltage to the diode bridge circuit. Output to 30.

The diode bridge circuit 24 functions as a first diode bridge circuit, two opposing input terminals of the diode bridge circuit 24 are connected to the secondary side of the transformer 22, and one output terminal is connected to a digital GND (GNDD). It is connected and the other output terminal is connected to the 3-terminal regulators 26 and 28. The diode bridge circuit 24 full-wave rectifies the input AC voltage and outputs it to the 3-terminal regulators 26 and 28.

The 3-terminal regulator 26 functions as a first voltage regulator, the input terminal IN of the 3-terminal regulator 26 is connected to the output terminal of the diode bridge circuit 24, the GND terminal is connected to the digital GND (GND), and the output terminal. OUT is connected to the + VDC terminal of the crystal oscillator 10. The 3-terminal regulator 26 generates a constant voltage + 5V voltage from the output of the diode bridge circuit 24 and outputs it to the + VDC terminal of the crystal oscillator 10.

Further, the 3-terminal regulator 28 functions as a second voltage regulator, the input terminal IN of the 3-terminal regulator 28 is connected to the output terminal of the diode bridge circuit 24, and the GND terminal is connected to the digital GND (GND). The output terminal OUT is connected to an analog GND (GNDA). The 3-terminal regulator 28 generates and outputs a constant voltage + 2.5V voltage, that is, an intermediate voltage between GND and + 5V voltage from the output of the diode bridge circuit 24.

The GND terminal of the crystal oscillator 10 such as OCXO is connected to the digital GND (GND), and the constant voltage + 5V voltage from the 3-terminal regulator 26 is applied to the + VDC terminal (power supply terminal) as described above. Further, the output terminal OUT is connected to the analog GND (GNDA) via a resistor and is also connected to the non-inverting input terminal (+) of the output buffer circuit 12.

On the other hand, the diode bridge circuit 30 functions as a second diode bridge circuit, the two opposing input terminals of the diode bridge circuit 30 are connected to the secondary side of the transformer 22, and the output terminals are connected to the shunt regulators 32 and 34. NS. The diode bridge circuit 30 full-wave rectifies the input AC voltage and outputs it to the shunt regulators 32 and 34.

The shunt regulator 32 functions as a third voltage regulator, the reference terminal of the shunt regulator 32 is connected to the output terminal of the diode bridge circuit 30, the anode terminal is connected to the analog GND (GNDA), and the shunt regulator 34 It is connected to the cathode terminal, and the cathode terminal is connected to the power supply terminal V + of the output buffer circuit 12.

The shunt regulator 34 functions as a fourth voltage regulator, the cathode terminal of the shunt regulator 34 is connected to the anode terminal of the shunt regulator 32, and the anode terminal is connected to the power supply terminal V- of the output buffer circuit 12. The shunt regulators 32 and 34 generate a constant voltage ± 6V from the output of the diode bridge circuit 30 and output it to the output buffer circuit 12 as a power supply voltage.

The non-inverting input terminal (+) of the output buffer circuit 12 is connected to the output terminal OUT of the crystal oscillator 10 as described above, and the inverting input terminal (−) is connected to the analog GND (GNDA).

In such a circuit configuration, the + 5V voltage from the 3-terminal regulator 26 is applied to the + VDC terminal of the crystal oscillator 10, but the output of the 3-terminal regulator 28 that generates + 2.5V, which is an intermediate voltage between GND and + 5V. The terminal is connected to the analog system GND (GNDA), and the digital system + 2.5V is set to the GND level (0V) based on the analog system. Then, the + 5V of the digital system applied to the + VDC of the crystal oscillator 10 becomes 2.5V based on the analog system, and the digital GND (GND) applied to the GND terminal of the crystal oscillator 10 is based on the analog system. Then, it becomes −2.5V, which is equivalent to applying a power supply voltage of + 2.5V to −2.5V to the crystal oscillator 10 based on the analog system.

Therefore, the crystal oscillator 10 is driven by a power supply voltage of ± 2.5 V with reference to the analog system, that is, the output buffer circuit 12, and outputs a clock signal to the output buffer circuit 12 with an amplitude centered on the analog system GND (GNDA). Since it will be supplied, capacitor-less will be realized.

<Embodiment 2>
In the first embodiment, the analog ± 6V voltage is generated by the shunt regulators 32 and 34, but a 3-terminal regulator may be used.

FIG. 4 shows the circuit configuration of the clock output circuit in this case. The difference from FIG. 3 is that 3-terminal regulators 36 and 38 are provided instead of the analog shunt regulators 32 and 34.

The 3-terminal regulator 36 functions as a third voltage regulator, the input terminal IN of the 3-terminal regulator 36 is connected to the output terminal of the diode bridge circuit 30, and the GND terminal is connected to the analog GND (GNDA). It is connected to the GND terminal of the terminal regulator 38, and the output terminal OUT is connected to the power supply terminal V + of the output buffer circuit 12.

The 3-terminal regulator 38 functions as a 4th voltage regulator, the input terminal IN of the 3-terminal regulator 38 is connected to the other output terminal of the diode bridge circuit 30, and the GND terminal is connected to the analog GND (GNDA). At the same time, it is connected to the GND terminal of the 3-terminal regulator 36, and the output terminal OUT is connected to the power supply terminal V- of the output buffer circuit. The three-terminal regulators 36 and 38 generate a constant voltage ± 6V from the output of the diode bridge circuit 30 and output it to the output buffer circuit 12 as a power supply voltage.

Even in this circuit configuration, the + 5V voltage from the 3-terminal regulator 26 is applied to the + VDC terminal of the crystal oscillator 10, but the output terminal of the 3-terminal regulator 28 that generates + 2.5V, which is an intermediate voltage between GND and + 5V. Is connected to the analog system GND (GNDA), and the digital system + 2.5V is set to the GND level (0V) based on the analog system. Then, the + 5V of the digital system applied to the + VDC of the crystal oscillator 10 becomes 2.5V based on the analog system, and the digital GND (GND) applied to the GND terminal of the crystal oscillator 10 is based on the analog system. Then, it becomes −2.5V, which is equivalent to applying a power supply voltage of + 2.5V to −2.5V to the crystal oscillator 10 based on the analog system.

<Embodiment 3>
FIG. 5 shows the circuit configuration of the clock output circuit in this embodiment.

The clock output circuit includes an AC plug 20, a transformer 22, a diode bridge circuit 40, and 3-terminal regulators 42, 44, 46, 48 in addition to the crystal oscillator 10 and the output buffer circuit 12.

The primary side of the transformer 22 is connected to the AC plug 20, and the secondary side of the transformer 22 is connected to the diode bridge circuit 40.

The two opposing input terminals of the diode bridge circuit 40 are connected to the secondary side of the transformer 22, and the output terminals are connected to the three-terminal regulators 42 and 44. The diode bridge circuit 40 full-wave rectifies the input AC voltage and outputs it to the three-terminal regulators 42 and 44.

The 3-terminal regulator 42 functions as a 5th voltage regulator, the input terminal IN of the 3-terminal regulator 42 is connected to the output terminal of the diode bridge circuit 40, the GND terminal is connected to the analog GND (GNDA), and 3 It is connected to the GND terminal of the terminal regulator 44, the output terminal OUT is connected to the V + terminal of the output buffer circuit 12, and is connected to the input terminal IN of the 3-terminal regulator 46. The 3-terminal regulator 42 generates a constant voltage + 6V voltage from the output of the diode bridge circuit 40 and outputs it to the V + terminal of the output buffer circuit 12.

The 3-terminal regulator 44 functions as a 6th voltage regulator, the input terminal IN of the 3-terminal regulator 44 is connected to the output terminal of the diode bridge circuit 40, the GND terminal is connected to the analog GND (GNDA), and 3 It is connected to the GND terminal of the terminal regulator 42, the output terminal OUT is connected to the V- terminal of the output buffer circuit 12, and is connected to the input terminal IN of the 3-terminal regulator 48. The 3-terminal regulator 44 generates a constant voltage -6V voltage from the output of the diode bridge circuit 40 and outputs it to the V-terminal of the output buffer circuit 12.

The 3-terminal regulator 46 functions as a 7th voltage regulator, and the input terminal IN of the 3-terminal regulator 46 is connected to the output terminal OUT of the 3-terminal regulator 42 as described above, and a constant voltage + 6V is input. The GND terminal of the 3-terminal regulator 46 is connected to the analog GND (GNDA), and the output terminal OUT is connected to the + VDC terminal (power supply terminal) of the crystal oscillator. The 3-terminal regulator 46 generates a + 2.5V voltage from the + 6V voltage and outputs it to the + VDC terminal of the crystal oscillator 10.

The 3-terminal regulator 48 functions as an eighth voltage regulator, and the input terminal IN of the 3-terminal regulator 48 is connected to the output terminal OUT of the 3-terminal regulator 44 as described above, and a constant voltage of -6V is input. The GND terminal of the 3-terminal regulator 48 is connected to the analog GND (GNDA), and the output terminal OUT is connected to the GND terminal of the crystal oscillator. The 3-terminal regulator 48 generates a −2.5V voltage from the −6V voltage and outputs it to the GND terminal of the crystal oscillator 10.

The output terminal OUT of the crystal oscillator 10 such as OCXO is connected to the analog GND (GNDA) via a resistor and is also connected to the non-inverting input terminal (+) of the output buffer circuit 12.

In this way, the 3-terminal regulators 42 and 44 generate + 6V and -6V, and the 3-terminal regulators 46 and 48 generate + 2.5V and -2.5V from these voltages as the power supply voltage of the crystal oscillator 10. It can output and realizes capacitorless.

As described above, in the present embodiment, the power supply voltage of the crystal oscillator 10 is 2.5 V to -2 in a simple configuration using the transformer 22, the diode bridge circuits 24, 30, 40, and the voltage regulators 26 to 48. By applying 5V, the center can generate a GND level clock signal and supply it to the output buffer circuit 12 operating at + 6V to -6V without interposing a capacitor, and the clock signal can be output to the outside.

10 crystal oscillator, 12 output buffer circuit, 20 AC plug, 22 transformer, 24, 30, 40 diode bridge circuit, 26, 28, 36, 38, 42, 44, 46, 48 3-terminal regulator, 32, 34 shunt regulator.

Claims (5)

A voltage adjustment circuit that adjusts the power supply voltage to generate a first positive voltage, a second positive voltage, and a second negative voltage.
A crystal oscillator connected to the voltage adjustment circuit, the first positive voltage is applied to the power supply terminal , the digital ground potential is set to the ground terminal, and a clock signal is output.
Is connected to the voltage regulating circuit, said clock signal from said second positive voltage, and connected to the crystal oscillator without intervening capacitor in operation to and the crystal oscillator by applying the second negative voltage via a resistor The output buffer circuit that is set to the ground potential for analog and supplied to the non-inverting input terminal,
With
The voltage adjustment circuit
A transformer that transforms the power supply voltage and
A first diode bridge circuit and a second diode bridge circuit connected to the secondary side of the transformer,
A first voltage regulator that is connected to the first diode bridge circuit, generates the first positive voltage, and outputs the first positive voltage to the power supply terminal of the crystal oscillator.
A second voltage connected to the first diode bridge circuit to generate an intermediate voltage between the first positive voltage and the digital ground potential, set it to analog ground, and supply it to the inverting input terminal of the output buffer circuit. With a regulator
A third voltage regulator that is connected to the second diode bridge circuit, generates the second positive voltage, and outputs the second positive voltage to the positive power supply terminal of the output buffer circuit.
A fourth voltage regulator that is connected to the second diode bridge circuit, generates the second negative voltage, and outputs the second negative voltage to the negative power supply terminal of the output buffer circuit.
A clock output circuit. The first voltage regulator and the second voltage regulator are three-terminal voltage regulators.
The third voltage regulator and the fourth voltage regulator are shunt regulators.
The clock output circuit according to claim 1. The first voltage regulator, the second voltage regulator, the third voltage regulator, and the fourth voltage regulator are three-terminal voltage regulators.
The clock output circuit according to claim 1. A voltage adjustment circuit that adjusts the power supply voltage to generate a first positive voltage, a first negative voltage, a second positive voltage, and a second negative voltage.
Connected to the voltage adjustment circuit, the first positive voltage is applied to the power supply terminal, the first negative voltage is applied to the ground terminal, and the intermediate potential between the first positive voltage and the first negative voltage is centered. A crystal oscillator that outputs a clock signal and
It is connected to the voltage adjustment circuit, operates by applying the second positive voltage and the second negative voltage, and is connected to the crystal oscillator without interposing a capacitor, and the clock signal from the crystal oscillator acts as a resistor. An output buffer circuit that is grounded through and supplied to the non-inverting input terminal and the ground potential is set to the inverting input terminal.
With
The voltage adjustment circuit
A transformer that transforms the power supply voltage and
A diode bridge circuit connected to the secondary side of the transformer and
A fifth voltage regulator that is connected to the diode bridge circuit, generates the second positive voltage, and outputs the second positive voltage to the positive power supply terminal of the output buffer circuit.
A sixth voltage regulator that is connected to the diode bridge circuit, generates the second negative voltage, and outputs the second negative voltage to the negative power supply terminal of the output buffer circuit.
A seventh voltage regulator that is connected to the output terminal of the fifth voltage regulator, generates the first positive voltage from the second positive voltage, and outputs the first positive voltage to the power supply terminal of the crystal oscillator.
An eighth voltage regulator that is connected to the output terminal of the sixth voltage regulator, generates the first negative voltage from the second negative voltage, and outputs the first negative voltage to the ground terminal of the crystal oscillator.
The clock output circuit comprising a. The fifth voltage regulator, the sixth voltage regulator, the seventh voltage regulator, and the eighth voltage regulator are three-terminal voltage regulators.
The clock output circuit according to claim 4.

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